drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc.h"
  32 #include "drm_crtc_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "intel_dp.h"
  37
  38 #define DP_LINK_STATUS_SIZE     6
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 #define DP_LINK_CONFIGURATION_SIZE      9
  42
  43 struct intel_dp_priv {
  44         uint32_t output_reg;
  45         uint32_t DP;
  46         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  47         uint32_t save_DP;
  48         uint8_t  save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
  49         bool has_audio;
  50         uint8_t link_bw;
  51         uint8_t lane_count;
  52         uint8_t dpcd[4];
  53         struct intel_output *intel_output;
  54         struct i2c_adapter adapter;
  55         struct i2c_algo_dp_aux_data algo;
  56 };
  57
  58 static void
  59 intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
  60                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
  61
  62 static void
  63 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
  64
  65 static int
  66 intel_dp_max_lane_count(struct intel_output *intel_output)
  67 {
  68         struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
  69         int max_lane_count = 4;
  70
  71         if (dp_priv->dpcd[0] >= 0x11) {
  72                 max_lane_count = dp_priv->dpcd[2] & 0x1f;
  73                 switch (max_lane_count) {
  74                 case 1: case 2: case 4:
  75                         break;
  76                 default:
  77                         max_lane_count = 4;
  78                 }
  79         }
  80         return max_lane_count;
  81 }
  82
  83 static int
  84 intel_dp_max_link_bw(struct intel_output *intel_output)
  85 {
  86         struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
  87         int max_link_bw = dp_priv->dpcd[1];
  88
  89         switch (max_link_bw) {
  90         case DP_LINK_BW_1_62:
  91         case DP_LINK_BW_2_7:
  92                 break;
  93         default:
  94                 max_link_bw = DP_LINK_BW_1_62;
  95                 break;
  96         }
  97         return max_link_bw;
  98 }
  99
 100 static int
 101 intel_dp_link_clock(uint8_t link_bw)
 102 {
 103         if (link_bw == DP_LINK_BW_2_7)
 104                 return 270000;
 105         else
 106                 return 162000;
 107 }
 108
 109 /* I think this is a fiction */
 110 static int
 111 intel_dp_link_required(int pixel_clock)
 112 {
 113         return pixel_clock * 3;
 114 }
 115
 116 static int
 117 intel_dp_mode_valid(struct drm_connector *connector,
 118                     struct drm_display_mode *mode)
 119 {
 120         struct intel_output *intel_output = to_intel_output(connector);
 121         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
 122         int max_lanes = intel_dp_max_lane_count(intel_output);
 123
 124         if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
 125                 return MODE_CLOCK_HIGH;
 126
 127         if (mode->clock < 10000)
 128                 return MODE_CLOCK_LOW;
 129
 130         return MODE_OK;
 131 }
 132
 133 static uint32_t
 134 pack_aux(uint8_t *src, int src_bytes)
 135 {
 136         int     i;
 137         uint32_t v = 0;
 138
 139         if (src_bytes > 4)
 140                 src_bytes = 4;
 141         for (i = 0; i < src_bytes; i++)
 142                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 143         return v;
 144 }
 145
 146 static void
 147 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 148 {
 149         int i;
 150         if (dst_bytes > 4)
 151                 dst_bytes = 4;
 152         for (i = 0; i < dst_bytes; i++)
 153                 dst[i] = src >> ((3-i) * 8);
 154 }
 155
 156 static int
 157 intel_dp_aux_ch(struct intel_output *intel_output,
 158                 uint8_t *send, int send_bytes,
 159                 uint8_t *recv, int recv_size)
 160 {
 161         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 162         uint32_t output_reg = dp_priv->output_reg;
 163         struct drm_device *dev = intel_output->base.dev;
 164         struct drm_i915_private *dev_priv = dev->dev_private;
 165         uint32_t ch_ctl = output_reg + 0x10;
 166         uint32_t ch_data = ch_ctl + 4;
 167         int i;
 168         int recv_bytes;
 169         uint32_t ctl;
 170         uint32_t status;
 171
 172         /* Load the send data into the aux channel data registers */
 173         for (i = 0; i < send_bytes; i += 4) {
 174                 uint32_t    d = pack_aux(send + i, send_bytes - i);;
 175
 176                 I915_WRITE(ch_data + i, d);
 177         }
 178
 179         /* The clock divider is based off the hrawclk,
 180          * and would like to run at 2MHz. The 133 below assumes
 181          * a 266MHz hrawclk; need to figure out how we're supposed
 182          * to know what hrawclk is...
 183          */
 184         ctl = (DP_AUX_CH_CTL_SEND_BUSY |
 185                DP_AUX_CH_CTL_TIME_OUT_1600us |
 186                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 187                (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 188                (133 << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 189                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 190                DP_AUX_CH_CTL_RECEIVE_ERROR);
 191
 192         /* Send the command and wait for it to complete */
 193         I915_WRITE(ch_ctl, ctl);
 194         (void) I915_READ(ch_ctl);
 195         for (;;) {
 196                 udelay(100);
 197                 status = I915_READ(ch_ctl);
 198                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 199                         break;
 200         }
 201
 202         /* Clear done status and any errors */
 203         I915_WRITE(ch_ctl, (ctl |
 204                         DP_AUX_CH_CTL_DONE |
 205                         DP_AUX_CH_CTL_TIME_OUT_ERROR |
 206                         DP_AUX_CH_CTL_RECEIVE_ERROR));
 207         (void) I915_READ(ch_ctl);
 208
 209         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 210                 printk(KERN_ERR "dp_aux_ch not done status 0x%08x\n", status);
 211                 return -1;
 212         }
 213
 214         /* Check for timeout or receive error.
 215          * Timeouts occur when the sink is not connected
 216          */
 217         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_RECEIVE_ERROR)) {
 218                 printk(KERN_ERR "dp_aux_ch error status 0x%08x\n", status);
 219                 return -1;
 220         }
 221
 222         /* Unload any bytes sent back from the other side */
 223         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 224                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 225
 226         if (recv_bytes > recv_size)
 227                 recv_bytes = recv_size;
 228
 229         for (i = 0; i < recv_bytes; i += 4) {
 230                 uint32_t    d = I915_READ(ch_data + i);
 231
 232                 unpack_aux(d, recv + i, recv_bytes - i);
 233         }
 234
 235         return recv_bytes;
 236 }
 237
 238 /* Write data to the aux channel in native mode */
 239 static int
 240 intel_dp_aux_native_write(struct intel_output *intel_output,
 241                           uint16_t address, uint8_t *send, int send_bytes)
 242 {
 243         int ret;
 244         uint8_t msg[20];
 245         int msg_bytes;
 246         uint8_t ack;
 247
 248         if (send_bytes > 16)
 249                 return -1;
 250         msg[0] = AUX_NATIVE_WRITE << 4;
 251         msg[1] = address >> 8;
 252         msg[2] = address;
 253         msg[3] = send_bytes - 1;
 254         memcpy(&msg[4], send, send_bytes);
 255         msg_bytes = send_bytes + 4;
 256         for (;;) {
 257                 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
 258                 if (ret < 0)
 259                         return ret;
 260                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 261                         break;
 262                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 263                         udelay(100);
 264                 else
 265                         return -1;
 266         }
 267         return send_bytes;
 268 }
 269
 270 /* Write a single byte to the aux channel in native mode */
 271 static int
 272 intel_dp_aux_native_write_1(struct intel_output *intel_output,
 273                             uint16_t address, uint8_t byte)
 274 {
 275         return intel_dp_aux_native_write(intel_output, address, &byte, 1);
 276 }
 277
 278 /* read bytes from a native aux channel */
 279 static int
 280 intel_dp_aux_native_read(struct intel_output *intel_output,
 281                          uint16_t address, uint8_t *recv, int recv_bytes)
 282 {
 283         uint8_t msg[4];
 284         int msg_bytes;
 285         uint8_t reply[20];
 286         int reply_bytes;
 287         uint8_t ack;
 288         int ret;
 289
 290         msg[0] = AUX_NATIVE_READ << 4;
 291         msg[1] = address >> 8;
 292         msg[2] = address & 0xff;
 293         msg[3] = recv_bytes - 1;
 294
 295         msg_bytes = 4;
 296         reply_bytes = recv_bytes + 1;
 297
 298         for (;;) {
 299                 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
 300                                       reply, reply_bytes);
 301                 if (ret <= 0)
 302                         return ret;
 303                 ack = reply[0];
 304                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 305                         memcpy(recv, reply + 1, ret - 1);
 306                         return ret - 1;
 307                 }
 308                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 309                         udelay(100);
 310                 else
 311                         return -1;
 312         }
 313 }
 314
 315 static int
 316 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
 317                     uint8_t *send, int send_bytes,
 318                     uint8_t *recv, int recv_bytes)
 319 {
 320         struct intel_dp_priv *dp_priv = container_of(adapter,
 321                                                      struct intel_dp_priv,
 322                                                      adapter);
 323         struct intel_output *intel_output = dp_priv->intel_output;
 324
 325         return intel_dp_aux_ch(intel_output,
 326                                send, send_bytes, recv, recv_bytes);
 327 }
 328
 329 static int
 330 intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
 331 {
 332         struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
 333
 334         DRM_ERROR("i2c_init %s\n", name);
 335         dp_priv->algo.running = false;
 336         dp_priv->algo.address = 0;
 337         dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
 338
 339         memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
 340         dp_priv->adapter.owner = THIS_MODULE;
 341         dp_priv->adapter.class = I2C_CLASS_DDC;
 342         strncpy (dp_priv->adapter.name, name, sizeof dp_priv->adapter.name - 1);
 343         dp_priv->adapter.name[sizeof dp_priv->adapter.name - 1] = '\0';
 344         dp_priv->adapter.algo_data = &dp_priv->algo;
 345         dp_priv->adapter.dev.parent = &intel_output->base.kdev;
 346
 347         return i2c_dp_aux_add_bus(&dp_priv->adapter);
 348 }
 349
 350 static bool
 351 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 352                     struct drm_display_mode *adjusted_mode)
 353 {
 354         struct intel_output *intel_output = enc_to_intel_output(encoder);
 355         struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
 356         int lane_count, clock;
 357         int max_lane_count = intel_dp_max_lane_count(intel_output);
 358         int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
 359         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 360
 361         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 362                 for (clock = 0; clock <= max_clock; clock++) {
 363                         int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
 364
 365                         if (intel_dp_link_required(mode->clock) <= link_avail) {
 366                                 dp_priv->link_bw = bws[clock];
 367                                 dp_priv->lane_count = lane_count;
 368                                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 369                                 printk(KERN_ERR "link bw %02x lane count %d clock %d\n",
 370                                        dp_priv->link_bw, dp_priv->lane_count,
 371                                        adjusted_mode->clock);
 372                                 return true;
 373                         }
 374                 }
 375         }
 376         return false;
 377 }
 378
 379 struct intel_dp_m_n {
 380         uint32_t        tu;
 381         uint32_t        gmch_m;
 382         uint32_t        gmch_n;
 383         uint32_t        link_m;
 384         uint32_t        link_n;
 385 };
 386
 387 static void
 388 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 389 {
 390         while (*num > 0xffffff || *den > 0xffffff) {
 391                 *num >>= 1;
 392                 *den >>= 1;
 393         }
 394 }
 395
 396 static void
 397 intel_dp_compute_m_n(int bytes_per_pixel,
 398                      int nlanes,
 399                      int pixel_clock,
 400                      int link_clock,
 401                      struct intel_dp_m_n *m_n)
 402 {
 403         m_n->tu = 64;
 404         m_n->gmch_m = pixel_clock * bytes_per_pixel;
 405         m_n->gmch_n = link_clock * nlanes;
 406         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 407         m_n->link_m = pixel_clock;
 408         m_n->link_n = link_clock;
 409         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 410 }
 411
 412 void
 413 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 414                  struct drm_display_mode *adjusted_mode)
 415 {
 416         struct drm_device *dev = crtc->dev;
 417         struct drm_mode_config *mode_config = &dev->mode_config;
 418         struct drm_connector *connector;
 419         struct drm_i915_private *dev_priv = dev->dev_private;
 420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 421         int lane_count = 4;
 422         struct intel_dp_m_n m_n;
 423
 424         /*
 425          * Find the lane count in the intel_output private
 426          */
 427         list_for_each_entry(connector, &mode_config->connector_list, head) {
 428                 struct intel_output *intel_output = to_intel_output(connector);
 429                 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 430
 431                 if (!connector->encoder || connector->encoder->crtc != crtc)
 432                         continue;
 433
 434                 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
 435                         lane_count = dp_priv->lane_count;
 436                         break;
 437                 }
 438         }
 439
 440         /*
 441          * Compute the GMCH and Link ratios. The '3' here is
 442          * the number of bytes_per_pixel post-LUT, which we always
 443          * set up for 8-bits of R/G/B, or 3 bytes total.
 444          */
 445         intel_dp_compute_m_n(3, lane_count,
 446                              mode->clock, adjusted_mode->clock, &m_n);
 447
 448         if (intel_crtc->pipe == 0) {
 449                 I915_WRITE(PIPEA_GMCH_DATA_M,
 450                        ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 451                        m_n.gmch_m);
 452                 I915_WRITE(PIPEA_GMCH_DATA_N,
 453                        m_n.gmch_n);
 454                 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 455                 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 456         } else {
 457                 I915_WRITE(PIPEB_GMCH_DATA_M,
 458                        ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 459                        m_n.gmch_m);
 460                 I915_WRITE(PIPEB_GMCH_DATA_N,
 461                        m_n.gmch_n);
 462                 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 463                 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 464         }
 465 }
 466
 467 static void
 468 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 469                   struct drm_display_mode *adjusted_mode)
 470 {
 471         struct intel_output *intel_output = enc_to_intel_output(encoder);
 472         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 473         struct drm_crtc *crtc = intel_output->enc.crtc;
 474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 475
 476         dp_priv->DP = (DP_LINK_TRAIN_OFF |
 477                         DP_VOLTAGE_0_4 |
 478                         DP_PRE_EMPHASIS_0 |
 479                         DP_SYNC_VS_HIGH |
 480                         DP_SYNC_HS_HIGH);
 481
 482         switch (dp_priv->lane_count) {
 483         case 1:
 484                 dp_priv->DP |= DP_PORT_WIDTH_1;
 485                 break;
 486         case 2:
 487                 dp_priv->DP |= DP_PORT_WIDTH_2;
 488                 break;
 489         case 4:
 490                 dp_priv->DP |= DP_PORT_WIDTH_4;
 491                 break;
 492         }
 493         if (dp_priv->has_audio)
 494                 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
 495
 496         memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 497         dp_priv->link_configuration[0] = dp_priv->link_bw;
 498         dp_priv->link_configuration[1] = dp_priv->lane_count;
 499
 500         /*
 501          * Check for DPCD version > 1.1,
 502          * enable enahanced frame stuff in that case
 503          */
 504         if (dp_priv->dpcd[0] >= 0x11) {
 505                 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 506                 dp_priv->DP |= DP_ENHANCED_FRAMING;
 507         }
 508
 509         if (intel_crtc->pipe == 1)
 510                 dp_priv->DP |= DP_PIPEB_SELECT;
 511 }
 512
 513
 514 static void
 515 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 516 {
 517         struct intel_output *intel_output = enc_to_intel_output(encoder);
 518         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 519         struct drm_device *dev = intel_output->base.dev;
 520         struct drm_i915_private *dev_priv = dev->dev_private;
 521         uint32_t dp_reg = I915_READ(dp_priv->output_reg);
 522
 523         if (mode != DRM_MODE_DPMS_ON) {
 524                 if (dp_reg & DP_PORT_EN)
 525                         intel_dp_link_down(intel_output, dp_priv->DP);
 526         } else {
 527                 if (!(dp_reg & DP_PORT_EN))
 528                         intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
 529         }
 530 }
 531
 532 /*
 533  * Fetch AUX CH registers 0x202 - 0x207 which contain
 534  * link status information
 535  */
 536 static bool
 537 intel_dp_get_link_status(struct intel_output *intel_output,
 538                          uint8_t link_status[DP_LINK_STATUS_SIZE])
 539 {
 540         int ret;
 541
 542         ret = intel_dp_aux_native_read(intel_output,
 543                                        DP_LANE0_1_STATUS,
 544                                        link_status, DP_LINK_STATUS_SIZE);
 545         if (ret != DP_LINK_STATUS_SIZE)
 546                 return false;
 547         return true;
 548 }
 549
 550 static uint8_t
 551 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 552                      int r)
 553 {
 554         return link_status[r - DP_LANE0_1_STATUS];
 555 }
 556
 557 static void
 558 intel_dp_save(struct drm_connector *connector)
 559 {
 560         struct intel_output *intel_output = to_intel_output(connector);
 561         struct drm_device *dev = intel_output->base.dev;
 562         struct drm_i915_private *dev_priv = dev->dev_private;
 563         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 564
 565         dp_priv->save_DP = I915_READ(dp_priv->output_reg);
 566         intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
 567                                  dp_priv->save_link_configuration,
 568                                  sizeof (dp_priv->save_link_configuration));
 569 }
 570
 571 static uint8_t
 572 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 573                                  int lane)
 574 {
 575         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 576         int         s = ((lane & 1) ?
 577                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 578                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 579         uint8_t l = intel_dp_link_status(link_status, i);
 580
 581         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 582 }
 583
 584 static uint8_t
 585 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 586                                       int lane)
 587 {
 588         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 589         int         s = ((lane & 1) ?
 590                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 591                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 592         uint8_t l = intel_dp_link_status(link_status, i);
 593
 594         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 595 }
 596
 597
 598 #if 0
 599 static char     *voltage_names[] = {
 600         "0.4V", "0.6V", "0.8V", "1.2V"
 601 };
 602 static char     *pre_emph_names[] = {
 603         "0dB", "3.5dB", "6dB", "9.5dB"
 604 };
 605 static char     *link_train_names[] = {
 606         "pattern 1", "pattern 2", "idle", "off"
 607 };
 608 #endif
 609
 610 /*
 611  * These are source-specific values; current Intel hardware supports
 612  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 613  */
 614 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
 615
 616 static uint8_t
 617 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 618 {
 619         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 620         case DP_TRAIN_VOLTAGE_SWING_400:
 621                 return DP_TRAIN_PRE_EMPHASIS_6;
 622         case DP_TRAIN_VOLTAGE_SWING_600:
 623                 return DP_TRAIN_PRE_EMPHASIS_6;
 624         case DP_TRAIN_VOLTAGE_SWING_800:
 625                 return DP_TRAIN_PRE_EMPHASIS_3_5;
 626         case DP_TRAIN_VOLTAGE_SWING_1200:
 627         default:
 628                 return DP_TRAIN_PRE_EMPHASIS_0;
 629         }
 630 }
 631
 632 static void
 633 intel_get_adjust_train(struct intel_output *intel_output,
 634                        uint8_t link_status[DP_LINK_STATUS_SIZE],
 635                        int lane_count,
 636                        uint8_t train_set[4])
 637 {
 638         uint8_t v = 0;
 639         uint8_t p = 0;
 640         int lane;
 641
 642         for (lane = 0; lane < lane_count; lane++) {
 643                 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
 644                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
 645
 646                 if (this_v > v)
 647                         v = this_v;
 648                 if (this_p > p)
 649                         p = this_p;
 650         }
 651
 652         if (v >= I830_DP_VOLTAGE_MAX)
 653                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 654
 655         if (p >= intel_dp_pre_emphasis_max(v))
 656                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 657
 658         for (lane = 0; lane < 4; lane++)
 659                 train_set[lane] = v | p;
 660 }
 661
 662 static uint32_t
 663 intel_dp_signal_levels(uint8_t train_set, int lane_count)
 664 {
 665         uint32_t        signal_levels = 0;
 666
 667         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 668         case DP_TRAIN_VOLTAGE_SWING_400:
 669         default:
 670                 signal_levels |= DP_VOLTAGE_0_4;
 671                 break;
 672         case DP_TRAIN_VOLTAGE_SWING_600:
 673                 signal_levels |= DP_VOLTAGE_0_6;
 674                 break;
 675         case DP_TRAIN_VOLTAGE_SWING_800:
 676                 signal_levels |= DP_VOLTAGE_0_8;
 677                 break;
 678         case DP_TRAIN_VOLTAGE_SWING_1200:
 679                 signal_levels |= DP_VOLTAGE_1_2;
 680                 break;
 681         }
 682         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 683         case DP_TRAIN_PRE_EMPHASIS_0:
 684         default:
 685                 signal_levels |= DP_PRE_EMPHASIS_0;
 686                 break;
 687         case DP_TRAIN_PRE_EMPHASIS_3_5:
 688                 signal_levels |= DP_PRE_EMPHASIS_3_5;
 689                 break;
 690         case DP_TRAIN_PRE_EMPHASIS_6:
 691                 signal_levels |= DP_PRE_EMPHASIS_6;
 692                 break;
 693         case DP_TRAIN_PRE_EMPHASIS_9_5:
 694                 signal_levels |= DP_PRE_EMPHASIS_9_5;
 695                 break;
 696         }
 697         return signal_levels;
 698 }
 699
 700 static uint8_t
 701 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 702                       int lane)
 703 {
 704         int i = DP_LANE0_1_STATUS + (lane >> 1);
 705         int s = (lane & 1) * 4;
 706         uint8_t l = intel_dp_link_status(link_status, i);
 707
 708         return (l >> s) & 0xf;
 709 }
 710
 711 /* Check for clock recovery is done on all channels */
 712 static bool
 713 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 714 {
 715         int lane;
 716         uint8_t lane_status;
 717
 718         for (lane = 0; lane < lane_count; lane++) {
 719                 lane_status = intel_get_lane_status(link_status, lane);
 720                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 721                         return false;
 722         }
 723         return true;
 724 }
 725
 726 /* Check to see if channel eq is done on all channels */
 727 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
 728                          DP_LANE_CHANNEL_EQ_DONE|\
 729                          DP_LANE_SYMBOL_LOCKED)
 730 static bool
 731 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 732 {
 733         uint8_t lane_align;
 734         uint8_t lane_status;
 735         int lane;
 736
 737         lane_align = intel_dp_link_status(link_status,
 738                                           DP_LANE_ALIGN_STATUS_UPDATED);
 739         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
 740                 return false;
 741         for (lane = 0; lane < lane_count; lane++) {
 742                 lane_status = intel_get_lane_status(link_status, lane);
 743                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
 744                         return false;
 745         }
 746         return true;
 747 }
 748
 749 static bool
 750 intel_dp_set_link_train(struct intel_output *intel_output,
 751                         uint32_t dp_reg_value,
 752                         uint8_t dp_train_pat,
 753                         uint8_t train_set[4],
 754                         bool first)
 755 {
 756         struct drm_device *dev = intel_output->base.dev;
 757         struct drm_i915_private *dev_priv = dev->dev_private;
 758         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 759         int ret;
 760
 761         I915_WRITE(dp_priv->output_reg, dp_reg_value);
 762         POSTING_READ(dp_priv->output_reg);
 763         if (first)
 764                 intel_wait_for_vblank(dev);
 765
 766         intel_dp_aux_native_write_1(intel_output,
 767                                     DP_TRAINING_PATTERN_SET,
 768                                     dp_train_pat);
 769
 770         ret = intel_dp_aux_native_write(intel_output,
 771                                         DP_TRAINING_LANE0_SET, train_set, 4);
 772         if (ret != 4)
 773                 return false;
 774
 775         return true;
 776 }
 777
 778 static void
 779 intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
 780                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
 781 {
 782         struct drm_device *dev = intel_output->base.dev;
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 785         uint8_t train_set[4];
 786         uint8_t link_status[DP_LINK_STATUS_SIZE];
 787         int i;
 788         uint8_t voltage;
 789         bool clock_recovery = false;
 790         bool channel_eq = false;
 791         bool first = true;
 792         int tries;
 793
 794         /* Write the link configuration data */
 795         intel_dp_aux_native_write(intel_output, 0x100,
 796                                   link_configuration, DP_LINK_CONFIGURATION_SIZE);
 797
 798         DP |= DP_PORT_EN;
 799         DP &= ~DP_LINK_TRAIN_MASK;
 800         memset(train_set, 0, 4);
 801         voltage = 0xff;
 802         tries = 0;
 803         clock_recovery = false;
 804         for (;;) {
 805                 /* Use train_set[0] to set the voltage and pre emphasis values */
 806                 uint32_t    signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
 807                 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
 808
 809                 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
 810                                              DP_TRAINING_PATTERN_1, train_set, first))
 811                         break;
 812                 first = false;
 813                 /* Set training pattern 1 */
 814
 815                 udelay(100);
 816                 if (!intel_dp_get_link_status(intel_output, link_status))
 817                         break;
 818
 819                 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
 820                         clock_recovery = true;
 821                         break;
 822                 }
 823
 824                 /* Check to see if we've tried the max voltage */
 825                 for (i = 0; i < dp_priv->lane_count; i++)
 826                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 827                                 break;
 828                 if (i == dp_priv->lane_count)
 829                         break;
 830
 831                 /* Check to see if we've tried the same voltage 5 times */
 832                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 833                         ++tries;
 834                         if (tries == 5)
 835                                 break;
 836                 } else
 837                         tries = 0;
 838                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 839
 840                 /* Compute new train_set as requested by target */
 841                 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
 842         }
 843
 844         /* channel equalization */
 845         tries = 0;
 846         channel_eq = false;
 847         for (;;) {
 848                 /* Use train_set[0] to set the voltage and pre emphasis values */
 849                 uint32_t    signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
 850                 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
 851
 852                 /* channel eq pattern */
 853                 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
 854                                              DP_TRAINING_PATTERN_2, train_set,
 855                                              false))
 856                         break;
 857
 858                 udelay(400);
 859                 if (!intel_dp_get_link_status(intel_output, link_status))
 860                         break;
 861
 862                 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
 863                         channel_eq = true;
 864                         break;
 865                 }
 866
 867                 /* Try 5 times */
 868                 if (tries > 5)
 869                         break;
 870
 871                 /* Compute new train_set as requested by target */
 872                 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
 873                 ++tries;
 874         }
 875
 876         I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
 877         POSTING_READ(dp_priv->output_reg);
 878         intel_dp_aux_native_write_1(intel_output,
 879                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
 880 }
 881
 882 static void
 883 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
 884 {
 885         struct drm_device *dev = intel_output->base.dev;
 886         struct drm_i915_private *dev_priv = dev->dev_private;
 887         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 888
 889         I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
 890         POSTING_READ(dp_priv->output_reg);
 891 }
 892
 893 static void
 894 intel_dp_restore(struct drm_connector *connector)
 895 {
 896         struct intel_output *intel_output = to_intel_output(connector);
 897         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 898
 899         if (dp_priv->save_DP & DP_PORT_EN)
 900                 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
 901         else
 902                 intel_dp_link_down(intel_output,  dp_priv->save_DP);
 903 }
 904
 905 #if 0
 906 /*
 907  * According to DP spec
 908  * 5.1.2:
 909  *  1. Read DPCD
 910  *  2. Configure link according to Receiver Capabilities
 911  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 912  *  4. Check link status on receipt of hot-plug interrupt
 913  */
 914
 915 static void
 916 intel_dp_check_link_status(struct intel_output *intel_output)
 917 {
 918         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 919         uint8_t link_status[DP_LINK_STATUS_SIZE];
 920
 921         if (!intel_output->enc.crtc)
 922                 return;
 923
 924         if (!intel_dp_get_link_status(intel_output, link_status)) {
 925                 intel_dp_link_down(intel_output, dp_priv->DP);
 926                 return;
 927         }
 928
 929         if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
 930                 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
 931 }
 932 #endif
 933
 934 /**
 935  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
 936  *
 937  * \return true if DP port is connected.
 938  * \return false if DP port is disconnected.
 939  */
 940 static enum drm_connector_status
 941 intel_dp_detect(struct drm_connector *connector)
 942 {
 943         struct intel_output *intel_output = to_intel_output(connector);
 944         struct drm_device *dev = intel_output->base.dev;
 945         struct drm_i915_private *dev_priv = dev->dev_private;
 946         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 947         uint32_t temp, bit;
 948         enum drm_connector_status status;
 949
 950         dp_priv->has_audio = false;
 951
 952         temp = I915_READ(PORT_HOTPLUG_EN);
 953
 954         I915_WRITE(PORT_HOTPLUG_EN,
 955                temp |
 956                DPB_HOTPLUG_INT_EN |
 957                DPC_HOTPLUG_INT_EN |
 958                DPD_HOTPLUG_INT_EN);
 959
 960         POSTING_READ(PORT_HOTPLUG_EN);
 961
 962         switch (dp_priv->output_reg) {
 963         case DP_B:
 964                 bit = DPB_HOTPLUG_INT_STATUS;
 965                 break;
 966         case DP_C:
 967                 bit = DPC_HOTPLUG_INT_STATUS;
 968                 break;
 969         case DP_D:
 970                 bit = DPD_HOTPLUG_INT_STATUS;
 971                 break;
 972         default:
 973                 return connector_status_unknown;
 974         }
 975
 976         temp = I915_READ(PORT_HOTPLUG_STAT);
 977
 978         if ((temp & bit) == 0)
 979                 return connector_status_disconnected;
 980
 981         status = connector_status_disconnected;
 982         if (intel_dp_aux_native_read(intel_output,
 983                                      0x000, dp_priv->dpcd,
 984                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
 985         {
 986                 if (dp_priv->dpcd[0] != 0)
 987                         status = connector_status_connected;
 988         }
 989         return status;
 990 }
 991
 992 static int intel_dp_get_modes(struct drm_connector *connector)
 993 {
 994         struct intel_output *intel_output = to_intel_output(connector);
 995
 996         /* We should parse the EDID data and find out if it has an audio sink
 997          */
 998
 999         return intel_ddc_get_modes(intel_output);
1000 }
1001
1002 static void
1003 intel_dp_destroy (struct drm_connector *connector)
1004 {
1005         struct intel_output *intel_output = to_intel_output(connector);
1006
1007         if (intel_output->i2c_bus)
1008                 intel_i2c_destroy(intel_output->i2c_bus);
1009         drm_sysfs_connector_remove(connector);
1010         drm_connector_cleanup(connector);
1011         kfree(intel_output);
1012 }
1013
1014 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1015         .dpms = intel_dp_dpms,
1016         .mode_fixup = intel_dp_mode_fixup,
1017         .prepare = intel_encoder_prepare,
1018         .mode_set = intel_dp_mode_set,
1019         .commit = intel_encoder_commit,
1020 };
1021
1022 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1023         .dpms = drm_helper_connector_dpms,
1024         .save = intel_dp_save,
1025         .restore = intel_dp_restore,
1026         .detect = intel_dp_detect,
1027         .fill_modes = drm_helper_probe_single_connector_modes,
1028         .destroy = intel_dp_destroy,
1029 };
1030
1031 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1032         .get_modes = intel_dp_get_modes,
1033         .mode_valid = intel_dp_mode_valid,
1034         .best_encoder = intel_best_encoder,
1035 };
1036
1037 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1038 {
1039         drm_encoder_cleanup(encoder);
1040 }
1041
1042 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1043         .destroy = intel_dp_enc_destroy,
1044 };
1045
1046 void
1047 intel_dp_init(struct drm_device *dev, int output_reg)
1048 {
1049         struct drm_i915_private *dev_priv = dev->dev_private;
1050         struct drm_connector *connector;
1051         struct intel_output *intel_output;
1052         struct intel_dp_priv *dp_priv;
1053
1054         intel_output = kcalloc(sizeof(struct intel_output) +
1055                                sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1056         if (!intel_output)
1057                 return;
1058
1059         dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1060
1061         connector = &intel_output->base;
1062         drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1063                            DRM_MODE_CONNECTOR_DisplayPort);
1064         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1065
1066         intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
1067
1068         connector->interlace_allowed = true;
1069         connector->doublescan_allowed = 0;
1070
1071         dp_priv->intel_output = intel_output;
1072         dp_priv->output_reg = output_reg;
1073         dp_priv->has_audio = false;
1074         intel_output->dev_priv = dp_priv;
1075
1076         drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1077                          DRM_MODE_ENCODER_TMDS);
1078         drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1079
1080         drm_mode_connector_attach_encoder(&intel_output->base,
1081                                           &intel_output->enc);
1082         drm_sysfs_connector_add(connector);
1083
1084         /* Set up the DDC bus. */
1085         intel_dp_i2c_init(intel_output,
1086                           (output_reg == DP_B) ? "DPDDC-B" :
1087                           (output_reg == DP_C) ? "DPDDC-C" : "DPDDC-D");
1088         intel_output->ddc_bus = &dp_priv->adapter;
1089
1090         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1091          * 0xd.  Failure to do so will result in spurious interrupts being
1092          * generated on the port when a cable is not attached.
1093          */
1094         if (IS_G4X(dev) && !IS_GM45(dev)) {
1095                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1096                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1097         }
1098 }