drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc.h"
  32 #include "drm_crtc_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "drm_dp_helper.h"
  37
  38
  39 #define DP_LINK_STATUS_SIZE     6
  40 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  41
  42 #define DP_LINK_CONFIGURATION_SIZE      9
  43
  44 #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
  45
  46 struct intel_dp_priv {
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int dpms_mode;
  52         uint8_t link_bw;
  53         uint8_t lane_count;
  54         uint8_t dpcd[4];
  55         struct intel_encoder *intel_encoder;
  56         struct i2c_adapter adapter;
  57         struct i2c_algo_dp_aux_data algo;
  58 };
  59
  60 static void
  61 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
  62                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
  63
  64 static void
  65 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
  66
  67 void
  68 intel_edp_link_config (struct intel_encoder *intel_encoder,
  69                 int *lane_num, int *link_bw)
  70 {
  71         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  72
  73         *lane_num = dp_priv->lane_count;
  74         if (dp_priv->link_bw == DP_LINK_BW_1_62)
  75                 *link_bw = 162000;
  76         else if (dp_priv->link_bw == DP_LINK_BW_2_7)
  77                 *link_bw = 270000;
  78 }
  79
  80 static int
  81 intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
  82 {
  83         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  84         int max_lane_count = 4;
  85
  86         if (dp_priv->dpcd[0] >= 0x11) {
  87                 max_lane_count = dp_priv->dpcd[2] & 0x1f;
  88                 switch (max_lane_count) {
  89                 case 1: case 2: case 4:
  90                         break;
  91                 default:
  92                         max_lane_count = 4;
  93                 }
  94         }
  95         return max_lane_count;
  96 }
  97
  98 static int
  99 intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
 100 {
 101         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 102         int max_link_bw = dp_priv->dpcd[1];
 103
 104         switch (max_link_bw) {
 105         case DP_LINK_BW_1_62:
 106         case DP_LINK_BW_2_7:
 107                 break;
 108         default:
 109                 max_link_bw = DP_LINK_BW_1_62;
 110                 break;
 111         }
 112         return max_link_bw;
 113 }
 114
 115 static int
 116 intel_dp_link_clock(uint8_t link_bw)
 117 {
 118         if (link_bw == DP_LINK_BW_2_7)
 119                 return 270000;
 120         else
 121                 return 162000;
 122 }
 123
 124 /* I think this is a fiction */
 125 static int
 126 intel_dp_link_required(struct drm_device *dev,
 127                        struct intel_encoder *intel_encoder, int pixel_clock)
 128 {
 129         struct drm_i915_private *dev_priv = dev->dev_private;
 130
 131         if (IS_eDP(intel_encoder))
 132                 return (pixel_clock * dev_priv->edp_bpp) / 8;
 133         else
 134                 return pixel_clock * 3;
 135 }
 136
 137 static int
 138 intel_dp_mode_valid(struct drm_connector *connector,
 139                     struct drm_display_mode *mode)
 140 {
 141         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
 142         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
 143         int max_lanes = intel_dp_max_lane_count(intel_encoder);
 144
 145         if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
 146                         > max_link_clock * max_lanes)
 147                 return MODE_CLOCK_HIGH;
 148
 149         if (mode->clock < 10000)
 150                 return MODE_CLOCK_LOW;
 151
 152         return MODE_OK;
 153 }
 154
 155 static uint32_t
 156 pack_aux(uint8_t *src, int src_bytes)
 157 {
 158         int     i;
 159         uint32_t v = 0;
 160
 161         if (src_bytes > 4)
 162                 src_bytes = 4;
 163         for (i = 0; i < src_bytes; i++)
 164                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 165         return v;
 166 }
 167
 168 static void
 169 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 170 {
 171         int i;
 172         if (dst_bytes > 4)
 173                 dst_bytes = 4;
 174         for (i = 0; i < dst_bytes; i++)
 175                 dst[i] = src >> ((3-i) * 8);
 176 }
 177
 178 /* hrawclock is 1/4 the FSB frequency */
 179 static int
 180 intel_hrawclk(struct drm_device *dev)
 181 {
 182         struct drm_i915_private *dev_priv = dev->dev_private;
 183         uint32_t clkcfg;
 184
 185         clkcfg = I915_READ(CLKCFG);
 186         switch (clkcfg & CLKCFG_FSB_MASK) {
 187         case CLKCFG_FSB_400:
 188                 return 100;
 189         case CLKCFG_FSB_533:
 190                 return 133;
 191         case CLKCFG_FSB_667:
 192                 return 166;
 193         case CLKCFG_FSB_800:
 194                 return 200;
 195         case CLKCFG_FSB_1067:
 196                 return 266;
 197         case CLKCFG_FSB_1333:
 198                 return 333;
 199         /* these two are just a guess; one of them might be right */
 200         case CLKCFG_FSB_1600:
 201         case CLKCFG_FSB_1600_ALT:
 202                 return 400;
 203         default:
 204                 return 133;
 205         }
 206 }
 207
 208 static int
 209 intel_dp_aux_ch(struct intel_encoder *intel_encoder,
 210                 uint8_t *send, int send_bytes,
 211                 uint8_t *recv, int recv_size)
 212 {
 213         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 214         uint32_t output_reg = dp_priv->output_reg;
 215         struct drm_device *dev = intel_encoder->base.dev;
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         uint32_t ch_ctl = output_reg + 0x10;
 218         uint32_t ch_data = ch_ctl + 4;
 219         int i;
 220         int recv_bytes;
 221         uint32_t ctl;
 222         uint32_t status;
 223         uint32_t aux_clock_divider;
 224         int try, precharge;
 225
 226         /* The clock divider is based off the hrawclk,
 227          * and would like to run at 2MHz. So, take the
 228          * hrawclk value and divide by 2 and use that
 229          */
 230         if (IS_eDP(intel_encoder)) {
 231                 if (IS_GEN6(dev))
 232                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 233                 else
 234                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 235         } else if (HAS_PCH_SPLIT(dev))
 236                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 237         else
 238                 aux_clock_divider = intel_hrawclk(dev) / 2;
 239
 240         if (IS_GEN6(dev))
 241                 precharge = 3;
 242         else
 243                 precharge = 5;
 244
 245         /* Must try at least 3 times according to DP spec */
 246         for (try = 0; try < 5; try++) {
 247                 /* Load the send data into the aux channel data registers */
 248                 for (i = 0; i < send_bytes; i += 4) {
 249                         uint32_t    d = pack_aux(send + i, send_bytes - i);
 250
 251                         I915_WRITE(ch_data + i, d);
 252                 }
 253
 254                 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
 255                        DP_AUX_CH_CTL_TIME_OUT_400us |
 256                        (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 257                        (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 258                        (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 259                        DP_AUX_CH_CTL_DONE |
 260                        DP_AUX_CH_CTL_TIME_OUT_ERROR |
 261                        DP_AUX_CH_CTL_RECEIVE_ERROR);
 262
 263                 /* Send the command and wait for it to complete */
 264                 I915_WRITE(ch_ctl, ctl);
 265                 (void) I915_READ(ch_ctl);
 266                 for (;;) {
 267                         udelay(100);
 268                         status = I915_READ(ch_ctl);
 269                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 270                                 break;
 271                 }
 272
 273                 /* Clear done status and any errors */
 274                 I915_WRITE(ch_ctl, (status |
 275                                 DP_AUX_CH_CTL_DONE |
 276                                 DP_AUX_CH_CTL_TIME_OUT_ERROR |
 277                                 DP_AUX_CH_CTL_RECEIVE_ERROR));
 278                 (void) I915_READ(ch_ctl);
 279                 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
 280                         break;
 281         }
 282
 283         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 284                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 285                 return -EBUSY;
 286         }
 287
 288         /* Check for timeout or receive error.
 289          * Timeouts occur when the sink is not connected
 290          */
 291         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 292                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 293                 return -EIO;
 294         }
 295
 296         /* Timeouts occur when the device isn't connected, so they're
 297          * "normal" -- don't fill the kernel log with these */
 298         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 299                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 300                 return -ETIMEDOUT;
 301         }
 302
 303         /* Unload any bytes sent back from the other side */
 304         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 305                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 306
 307         if (recv_bytes > recv_size)
 308                 recv_bytes = recv_size;
 309
 310         for (i = 0; i < recv_bytes; i += 4) {
 311                 uint32_t    d = I915_READ(ch_data + i);
 312
 313                 unpack_aux(d, recv + i, recv_bytes - i);
 314         }
 315
 316         return recv_bytes;
 317 }
 318
 319 /* Write data to the aux channel in native mode */
 320 static int
 321 intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
 322                           uint16_t address, uint8_t *send, int send_bytes)
 323 {
 324         int ret;
 325         uint8_t msg[20];
 326         int msg_bytes;
 327         uint8_t ack;
 328
 329         if (send_bytes > 16)
 330                 return -1;
 331         msg[0] = AUX_NATIVE_WRITE << 4;
 332         msg[1] = address >> 8;
 333         msg[2] = address & 0xff;
 334         msg[3] = send_bytes - 1;
 335         memcpy(&msg[4], send, send_bytes);
 336         msg_bytes = send_bytes + 4;
 337         for (;;) {
 338                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
 339                 if (ret < 0)
 340                         return ret;
 341                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 342                         break;
 343                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 344                         udelay(100);
 345                 else
 346                         return -EIO;
 347         }
 348         return send_bytes;
 349 }
 350
 351 /* Write a single byte to the aux channel in native mode */
 352 static int
 353 intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
 354                             uint16_t address, uint8_t byte)
 355 {
 356         return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
 357 }
 358
 359 /* read bytes from a native aux channel */
 360 static int
 361 intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
 362                          uint16_t address, uint8_t *recv, int recv_bytes)
 363 {
 364         uint8_t msg[4];
 365         int msg_bytes;
 366         uint8_t reply[20];
 367         int reply_bytes;
 368         uint8_t ack;
 369         int ret;
 370
 371         msg[0] = AUX_NATIVE_READ << 4;
 372         msg[1] = address >> 8;
 373         msg[2] = address & 0xff;
 374         msg[3] = recv_bytes - 1;
 375
 376         msg_bytes = 4;
 377         reply_bytes = recv_bytes + 1;
 378
 379         for (;;) {
 380                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
 381                                       reply, reply_bytes);
 382                 if (ret == 0)
 383                         return -EPROTO;
 384                 if (ret < 0)
 385                         return ret;
 386                 ack = reply[0];
 387                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 388                         memcpy(recv, reply + 1, ret - 1);
 389                         return ret - 1;
 390                 }
 391                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 392                         udelay(100);
 393                 else
 394                         return -EIO;
 395         }
 396 }
 397
 398 static int
 399 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 400                     uint8_t write_byte, uint8_t *read_byte)
 401 {
 402         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 403         struct intel_dp_priv *dp_priv = container_of(adapter,
 404                                                      struct intel_dp_priv,
 405                                                      adapter);
 406         struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
 407         uint16_t address = algo_data->address;
 408         uint8_t msg[5];
 409         uint8_t reply[2];
 410         int msg_bytes;
 411         int reply_bytes;
 412         int ret;
 413
 414         /* Set up the command byte */
 415         if (mode & MODE_I2C_READ)
 416                 msg[0] = AUX_I2C_READ << 4;
 417         else
 418                 msg[0] = AUX_I2C_WRITE << 4;
 419
 420         if (!(mode & MODE_I2C_STOP))
 421                 msg[0] |= AUX_I2C_MOT << 4;
 422
 423         msg[1] = address >> 8;
 424         msg[2] = address;
 425
 426         switch (mode) {
 427         case MODE_I2C_WRITE:
 428                 msg[3] = 0;
 429                 msg[4] = write_byte;
 430                 msg_bytes = 5;
 431                 reply_bytes = 1;
 432                 break;
 433         case MODE_I2C_READ:
 434                 msg[3] = 0;
 435                 msg_bytes = 4;
 436                 reply_bytes = 2;
 437                 break;
 438         default:
 439                 msg_bytes = 3;
 440                 reply_bytes = 1;
 441                 break;
 442         }
 443
 444         for (;;) {
 445           ret = intel_dp_aux_ch(intel_encoder,
 446                                 msg, msg_bytes,
 447                                 reply, reply_bytes);
 448                 if (ret < 0) {
 449                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 450                         return ret;
 451                 }
 452                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 453                 case AUX_I2C_REPLY_ACK:
 454                         if (mode == MODE_I2C_READ) {
 455                                 *read_byte = reply[1];
 456                         }
 457                         return reply_bytes - 1;
 458                 case AUX_I2C_REPLY_NACK:
 459                         DRM_DEBUG_KMS("aux_ch nack\n");
 460                         return -EREMOTEIO;
 461                 case AUX_I2C_REPLY_DEFER:
 462                         DRM_DEBUG_KMS("aux_ch defer\n");
 463                         udelay(100);
 464                         break;
 465                 default:
 466                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 467                         return -EREMOTEIO;
 468                 }
 469         }
 470 }
 471
 472 static int
 473 intel_dp_i2c_init(struct intel_encoder *intel_encoder, const char *name)
 474 {
 475         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 476
 477         DRM_DEBUG_KMS("i2c_init %s\n", name);
 478         dp_priv->algo.running = false;
 479         dp_priv->algo.address = 0;
 480         dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
 481
 482         memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
 483         dp_priv->adapter.owner = THIS_MODULE;
 484         dp_priv->adapter.class = I2C_CLASS_DDC;
 485         strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
 486         dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
 487         dp_priv->adapter.algo_data = &dp_priv->algo;
 488         dp_priv->adapter.dev.parent = &intel_encoder->base.kdev;
 489
 490         return i2c_dp_aux_add_bus(&dp_priv->adapter);
 491 }
 492
 493 static bool
 494 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 495                     struct drm_display_mode *adjusted_mode)
 496 {
 497         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 498         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 499         int lane_count, clock;
 500         int max_lane_count = intel_dp_max_lane_count(intel_encoder);
 501         int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
 502         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 503
 504         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 505                 for (clock = 0; clock <= max_clock; clock++) {
 506                         int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
 507
 508                         if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
 509                                         <= link_avail) {
 510                                 dp_priv->link_bw = bws[clock];
 511                                 dp_priv->lane_count = lane_count;
 512                                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 513                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 514                                                 "count %d clock %d\n",
 515                                        dp_priv->link_bw, dp_priv->lane_count,
 516                                        adjusted_mode->clock);
 517                                 return true;
 518                         }
 519                 }
 520         }
 521         return false;
 522 }
 523
 524 struct intel_dp_m_n {
 525         uint32_t        tu;
 526         uint32_t        gmch_m;
 527         uint32_t        gmch_n;
 528         uint32_t        link_m;
 529         uint32_t        link_n;
 530 };
 531
 532 static void
 533 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 534 {
 535         while (*num > 0xffffff || *den > 0xffffff) {
 536                 *num >>= 1;
 537                 *den >>= 1;
 538         }
 539 }
 540
 541 static void
 542 intel_dp_compute_m_n(int bytes_per_pixel,
 543                      int nlanes,
 544                      int pixel_clock,
 545                      int link_clock,
 546                      struct intel_dp_m_n *m_n)
 547 {
 548         m_n->tu = 64;
 549         m_n->gmch_m = pixel_clock * bytes_per_pixel;
 550         m_n->gmch_n = link_clock * nlanes;
 551         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 552         m_n->link_m = pixel_clock;
 553         m_n->link_n = link_clock;
 554         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 555 }
 556
 557 void
 558 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 559                  struct drm_display_mode *adjusted_mode)
 560 {
 561         struct drm_device *dev = crtc->dev;
 562         struct drm_mode_config *mode_config = &dev->mode_config;
 563         struct drm_connector *connector;
 564         struct drm_i915_private *dev_priv = dev->dev_private;
 565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 566         int lane_count = 4;
 567         struct intel_dp_m_n m_n;
 568
 569         /*
 570          * Find the lane count in the intel_encoder private
 571          */
 572         list_for_each_entry(connector, &mode_config->connector_list, head) {
 573                 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
 574                 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 575
 576                 if (!connector->encoder || connector->encoder->crtc != crtc)
 577                         continue;
 578
 579                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
 580                         lane_count = dp_priv->lane_count;
 581                         break;
 582                 }
 583         }
 584
 585         /*
 586          * Compute the GMCH and Link ratios. The '3' here is
 587          * the number of bytes_per_pixel post-LUT, which we always
 588          * set up for 8-bits of R/G/B, or 3 bytes total.
 589          */
 590         intel_dp_compute_m_n(3, lane_count,
 591                              mode->clock, adjusted_mode->clock, &m_n);
 592
 593         if (HAS_PCH_SPLIT(dev)) {
 594                 if (intel_crtc->pipe == 0) {
 595                         I915_WRITE(TRANSA_DATA_M1,
 596                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 597                                    m_n.gmch_m);
 598                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 599                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 600                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 601                 } else {
 602                         I915_WRITE(TRANSB_DATA_M1,
 603                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 604                                    m_n.gmch_m);
 605                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 606                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 607                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 608                 }
 609         } else {
 610                 if (intel_crtc->pipe == 0) {
 611                         I915_WRITE(PIPEA_GMCH_DATA_M,
 612                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 613                                    m_n.gmch_m);
 614                         I915_WRITE(PIPEA_GMCH_DATA_N,
 615                                    m_n.gmch_n);
 616                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 617                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 618                 } else {
 619                         I915_WRITE(PIPEB_GMCH_DATA_M,
 620                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 621                                    m_n.gmch_m);
 622                         I915_WRITE(PIPEB_GMCH_DATA_N,
 623                                         m_n.gmch_n);
 624                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 625                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 626                 }
 627         }
 628 }
 629
 630 static void
 631 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 632                   struct drm_display_mode *adjusted_mode)
 633 {
 634         struct drm_device *dev = encoder->dev;
 635         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 636         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 637         struct drm_crtc *crtc = intel_encoder->enc.crtc;
 638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 639
 640         dp_priv->DP = (DP_VOLTAGE_0_4 |
 641                         DP_PRE_EMPHASIS_0 |
 642                         DP_SYNC_VS_HIGH |
 643                         DP_SYNC_HS_HIGH);
 644
 645         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
 646                 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
 647         else
 648                 dp_priv->DP |= DP_LINK_TRAIN_OFF;
 649
 650         switch (dp_priv->lane_count) {
 651         case 1:
 652                 dp_priv->DP |= DP_PORT_WIDTH_1;
 653                 break;
 654         case 2:
 655                 dp_priv->DP |= DP_PORT_WIDTH_2;
 656                 break;
 657         case 4:
 658                 dp_priv->DP |= DP_PORT_WIDTH_4;
 659                 break;
 660         }
 661         if (dp_priv->has_audio)
 662                 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
 663
 664         memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 665         dp_priv->link_configuration[0] = dp_priv->link_bw;
 666         dp_priv->link_configuration[1] = dp_priv->lane_count;
 667
 668         /*
 669          * Check for DPCD version > 1.1,
 670          * enable enahanced frame stuff in that case
 671          */
 672         if (dp_priv->dpcd[0] >= 0x11) {
 673                 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 674                 dp_priv->DP |= DP_ENHANCED_FRAMING;
 675         }
 676
 677         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 678         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 679                 dp_priv->DP |= DP_PIPEB_SELECT;
 680
 681         if (IS_eDP(intel_encoder)) {
 682                 /* don't miss out required setting for eDP */
 683                 dp_priv->DP |= DP_PLL_ENABLE;
 684                 if (adjusted_mode->clock < 200000)
 685                         dp_priv->DP |= DP_PLL_FREQ_160MHZ;
 686                 else
 687                         dp_priv->DP |= DP_PLL_FREQ_270MHZ;
 688         }
 689 }
 690
 691 static void ironlake_edp_backlight_on (struct drm_device *dev)
 692 {
 693         struct drm_i915_private *dev_priv = dev->dev_private;
 694         u32 pp;
 695
 696         DRM_DEBUG_KMS("\n");
 697         pp = I915_READ(PCH_PP_CONTROL);
 698         pp |= EDP_BLC_ENABLE;
 699         I915_WRITE(PCH_PP_CONTROL, pp);
 700 }
 701
 702 static void ironlake_edp_backlight_off (struct drm_device *dev)
 703 {
 704         struct drm_i915_private *dev_priv = dev->dev_private;
 705         u32 pp;
 706
 707         DRM_DEBUG_KMS("\n");
 708         pp = I915_READ(PCH_PP_CONTROL);
 709         pp &= ~EDP_BLC_ENABLE;
 710         I915_WRITE(PCH_PP_CONTROL, pp);
 711 }
 712
 713 static void
 714 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 715 {
 716         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 717         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 718         struct drm_device *dev = intel_encoder->base.dev;
 719         struct drm_i915_private *dev_priv = dev->dev_private;
 720         uint32_t dp_reg = I915_READ(dp_priv->output_reg);
 721
 722         if (mode != DRM_MODE_DPMS_ON) {
 723                 if (dp_reg & DP_PORT_EN) {
 724                         intel_dp_link_down(intel_encoder, dp_priv->DP);
 725                         if (IS_eDP(intel_encoder))
 726                                 ironlake_edp_backlight_off(dev);
 727                 }
 728         } else {
 729                 if (!(dp_reg & DP_PORT_EN)) {
 730                         intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
 731                         if (IS_eDP(intel_encoder))
 732                                 ironlake_edp_backlight_on(dev);
 733                 }
 734         }
 735         dp_priv->dpms_mode = mode;
 736 }
 737
 738 /*
 739  * Fetch AUX CH registers 0x202 - 0x207 which contain
 740  * link status information
 741  */
 742 static bool
 743 intel_dp_get_link_status(struct intel_encoder *intel_encoder,
 744                          uint8_t link_status[DP_LINK_STATUS_SIZE])
 745 {
 746         int ret;
 747
 748         ret = intel_dp_aux_native_read(intel_encoder,
 749                                        DP_LANE0_1_STATUS,
 750                                        link_status, DP_LINK_STATUS_SIZE);
 751         if (ret != DP_LINK_STATUS_SIZE)
 752                 return false;
 753         return true;
 754 }
 755
 756 static uint8_t
 757 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 758                      int r)
 759 {
 760         return link_status[r - DP_LANE0_1_STATUS];
 761 }
 762
 763 static uint8_t
 764 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 765                                  int lane)
 766 {
 767         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 768         int         s = ((lane & 1) ?
 769                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 770                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 771         uint8_t l = intel_dp_link_status(link_status, i);
 772
 773         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 774 }
 775
 776 static uint8_t
 777 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 778                                       int lane)
 779 {
 780         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 781         int         s = ((lane & 1) ?
 782                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 783                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 784         uint8_t l = intel_dp_link_status(link_status, i);
 785
 786         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 787 }
 788
 789
 790 #if 0
 791 static char     *voltage_names[] = {
 792         "0.4V", "0.6V", "0.8V", "1.2V"
 793 };
 794 static char     *pre_emph_names[] = {
 795         "0dB", "3.5dB", "6dB", "9.5dB"
 796 };
 797 static char     *link_train_names[] = {
 798         "pattern 1", "pattern 2", "idle", "off"
 799 };
 800 #endif
 801
 802 /*
 803  * These are source-specific values; current Intel hardware supports
 804  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 805  */
 806 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
 807
 808 static uint8_t
 809 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 810 {
 811         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 812         case DP_TRAIN_VOLTAGE_SWING_400:
 813                 return DP_TRAIN_PRE_EMPHASIS_6;
 814         case DP_TRAIN_VOLTAGE_SWING_600:
 815                 return DP_TRAIN_PRE_EMPHASIS_6;
 816         case DP_TRAIN_VOLTAGE_SWING_800:
 817                 return DP_TRAIN_PRE_EMPHASIS_3_5;
 818         case DP_TRAIN_VOLTAGE_SWING_1200:
 819         default:
 820                 return DP_TRAIN_PRE_EMPHASIS_0;
 821         }
 822 }
 823
 824 static void
 825 intel_get_adjust_train(struct intel_encoder *intel_encoder,
 826                        uint8_t link_status[DP_LINK_STATUS_SIZE],
 827                        int lane_count,
 828                        uint8_t train_set[4])
 829 {
 830         uint8_t v = 0;
 831         uint8_t p = 0;
 832         int lane;
 833
 834         for (lane = 0; lane < lane_count; lane++) {
 835                 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
 836                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
 837
 838                 if (this_v > v)
 839                         v = this_v;
 840                 if (this_p > p)
 841                         p = this_p;
 842         }
 843
 844         if (v >= I830_DP_VOLTAGE_MAX)
 845                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 846
 847         if (p >= intel_dp_pre_emphasis_max(v))
 848                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 849
 850         for (lane = 0; lane < 4; lane++)
 851                 train_set[lane] = v | p;
 852 }
 853
 854 static uint32_t
 855 intel_dp_signal_levels(uint8_t train_set, int lane_count)
 856 {
 857         uint32_t        signal_levels = 0;
 858
 859         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 860         case DP_TRAIN_VOLTAGE_SWING_400:
 861         default:
 862                 signal_levels |= DP_VOLTAGE_0_4;
 863                 break;
 864         case DP_TRAIN_VOLTAGE_SWING_600:
 865                 signal_levels |= DP_VOLTAGE_0_6;
 866                 break;
 867         case DP_TRAIN_VOLTAGE_SWING_800:
 868                 signal_levels |= DP_VOLTAGE_0_8;
 869                 break;
 870         case DP_TRAIN_VOLTAGE_SWING_1200:
 871                 signal_levels |= DP_VOLTAGE_1_2;
 872                 break;
 873         }
 874         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 875         case DP_TRAIN_PRE_EMPHASIS_0:
 876         default:
 877                 signal_levels |= DP_PRE_EMPHASIS_0;
 878                 break;
 879         case DP_TRAIN_PRE_EMPHASIS_3_5:
 880                 signal_levels |= DP_PRE_EMPHASIS_3_5;
 881                 break;
 882         case DP_TRAIN_PRE_EMPHASIS_6:
 883                 signal_levels |= DP_PRE_EMPHASIS_6;
 884                 break;
 885         case DP_TRAIN_PRE_EMPHASIS_9_5:
 886                 signal_levels |= DP_PRE_EMPHASIS_9_5;
 887                 break;
 888         }
 889         return signal_levels;
 890 }
 891
 892 /* Gen6's DP voltage swing and pre-emphasis control */
 893 static uint32_t
 894 intel_gen6_edp_signal_levels(uint8_t train_set)
 895 {
 896         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
 897         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
 898                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
 899         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
 900                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
 901         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
 902                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
 903         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
 904                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
 905         default:
 906                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
 907                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
 908         }
 909 }
 910
 911 static uint8_t
 912 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 913                       int lane)
 914 {
 915         int i = DP_LANE0_1_STATUS + (lane >> 1);
 916         int s = (lane & 1) * 4;
 917         uint8_t l = intel_dp_link_status(link_status, i);
 918
 919         return (l >> s) & 0xf;
 920 }
 921
 922 /* Check for clock recovery is done on all channels */
 923 static bool
 924 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 925 {
 926         int lane;
 927         uint8_t lane_status;
 928
 929         for (lane = 0; lane < lane_count; lane++) {
 930                 lane_status = intel_get_lane_status(link_status, lane);
 931                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 932                         return false;
 933         }
 934         return true;
 935 }
 936
 937 /* Check to see if channel eq is done on all channels */
 938 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
 939                          DP_LANE_CHANNEL_EQ_DONE|\
 940                          DP_LANE_SYMBOL_LOCKED)
 941 static bool
 942 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 943 {
 944         uint8_t lane_align;
 945         uint8_t lane_status;
 946         int lane;
 947
 948         lane_align = intel_dp_link_status(link_status,
 949                                           DP_LANE_ALIGN_STATUS_UPDATED);
 950         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
 951                 return false;
 952         for (lane = 0; lane < lane_count; lane++) {
 953                 lane_status = intel_get_lane_status(link_status, lane);
 954                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
 955                         return false;
 956         }
 957         return true;
 958 }
 959
 960 static bool
 961 intel_dp_set_link_train(struct intel_encoder *intel_encoder,
 962                         uint32_t dp_reg_value,
 963                         uint8_t dp_train_pat,
 964                         uint8_t train_set[4],
 965                         bool first)
 966 {
 967         struct drm_device *dev = intel_encoder->base.dev;
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 970         int ret;
 971
 972         I915_WRITE(dp_priv->output_reg, dp_reg_value);
 973         POSTING_READ(dp_priv->output_reg);
 974         if (first)
 975                 intel_wait_for_vblank(dev);
 976
 977         intel_dp_aux_native_write_1(intel_encoder,
 978                                     DP_TRAINING_PATTERN_SET,
 979                                     dp_train_pat);
 980
 981         ret = intel_dp_aux_native_write(intel_encoder,
 982                                         DP_TRAINING_LANE0_SET, train_set, 4);
 983         if (ret != 4)
 984                 return false;
 985
 986         return true;
 987 }
 988
 989 static void
 990 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
 991                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
 992 {
 993         struct drm_device *dev = intel_encoder->base.dev;
 994         struct drm_i915_private *dev_priv = dev->dev_private;
 995         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 996         uint8_t train_set[4];
 997         uint8_t link_status[DP_LINK_STATUS_SIZE];
 998         int i;
 999         uint8_t voltage;
1000         bool clock_recovery = false;
1001         bool channel_eq = false;
1002         bool first = true;
1003         int tries;
1004         u32 reg;
1005
1006         /* Write the link configuration data */
1007         intel_dp_aux_native_write(intel_encoder, 0x100,
1008                                   link_configuration, DP_LINK_CONFIGURATION_SIZE);
1009
1010         DP |= DP_PORT_EN;
1011         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1012                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1013         else
1014                 DP &= ~DP_LINK_TRAIN_MASK;
1015         memset(train_set, 0, 4);
1016         voltage = 0xff;
1017         tries = 0;
1018         clock_recovery = false;
1019         for (;;) {
1020                 /* Use train_set[0] to set the voltage and pre emphasis values */
1021                 uint32_t    signal_levels;
1022                 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1023                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1024                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1025                 } else {
1026                         signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1027                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1028                 }
1029
1030                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1031                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1032                 else
1033                         reg = DP | DP_LINK_TRAIN_PAT_1;
1034
1035                 if (!intel_dp_set_link_train(intel_encoder, reg,
1036                                              DP_TRAINING_PATTERN_1, train_set, first))
1037                         break;
1038                 first = false;
1039                 /* Set training pattern 1 */
1040
1041                 udelay(100);
1042                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1043                         break;
1044
1045                 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1046                         clock_recovery = true;
1047                         break;
1048                 }
1049
1050                 /* Check to see if we've tried the max voltage */
1051                 for (i = 0; i < dp_priv->lane_count; i++)
1052                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1053                                 break;
1054                 if (i == dp_priv->lane_count)
1055                         break;
1056
1057                 /* Check to see if we've tried the same voltage 5 times */
1058                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1059                         ++tries;
1060                         if (tries == 5)
1061                                 break;
1062                 } else
1063                         tries = 0;
1064                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1065
1066                 /* Compute new train_set as requested by target */
1067                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1068         }
1069
1070         /* channel equalization */
1071         tries = 0;
1072         channel_eq = false;
1073         for (;;) {
1074                 /* Use train_set[0] to set the voltage and pre emphasis values */
1075                 uint32_t    signal_levels;
1076
1077                 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1078                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1079                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1080                 } else {
1081                         signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1082                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1083                 }
1084
1085                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1086                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1087                 else
1088                         reg = DP | DP_LINK_TRAIN_PAT_2;
1089
1090                 /* channel eq pattern */
1091                 if (!intel_dp_set_link_train(intel_encoder, reg,
1092                                              DP_TRAINING_PATTERN_2, train_set,
1093                                              false))
1094                         break;
1095
1096                 udelay(400);
1097                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1098                         break;
1099
1100                 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1101                         channel_eq = true;
1102                         break;
1103                 }
1104
1105                 /* Try 5 times */
1106                 if (tries > 5)
1107                         break;
1108
1109                 /* Compute new train_set as requested by target */
1110                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1111                 ++tries;
1112         }
1113
1114         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1115                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1116         else
1117                 reg = DP | DP_LINK_TRAIN_OFF;
1118
1119         I915_WRITE(dp_priv->output_reg, reg);
1120         POSTING_READ(dp_priv->output_reg);
1121         intel_dp_aux_native_write_1(intel_encoder,
1122                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1123 }
1124
1125 static void
1126 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1127 {
1128         struct drm_device *dev = intel_encoder->base.dev;
1129         struct drm_i915_private *dev_priv = dev->dev_private;
1130         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1131
1132         DRM_DEBUG_KMS("\n");
1133
1134         if (IS_eDP(intel_encoder)) {
1135                 DP &= ~DP_PLL_ENABLE;
1136                 I915_WRITE(dp_priv->output_reg, DP);
1137                 POSTING_READ(dp_priv->output_reg);
1138                 udelay(100);
1139         }
1140
1141         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
1142                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1143                 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1144                 POSTING_READ(dp_priv->output_reg);
1145         } else {
1146                 DP &= ~DP_LINK_TRAIN_MASK;
1147                 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1148                 POSTING_READ(dp_priv->output_reg);
1149         }
1150
1151         udelay(17000);
1152
1153         if (IS_eDP(intel_encoder))
1154                 DP |= DP_LINK_TRAIN_OFF;
1155         I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1156         POSTING_READ(dp_priv->output_reg);
1157 }
1158
1159 /*
1160  * According to DP spec
1161  * 5.1.2:
1162  *  1. Read DPCD
1163  *  2. Configure link according to Receiver Capabilities
1164  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1165  *  4. Check link status on receipt of hot-plug interrupt
1166  */
1167
1168 static void
1169 intel_dp_check_link_status(struct intel_encoder *intel_encoder)
1170 {
1171         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1172         uint8_t link_status[DP_LINK_STATUS_SIZE];
1173
1174         if (!intel_encoder->enc.crtc)
1175                 return;
1176
1177         if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1178                 intel_dp_link_down(intel_encoder, dp_priv->DP);
1179                 return;
1180         }
1181
1182         if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1183                 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
1184 }
1185
1186 static enum drm_connector_status
1187 ironlake_dp_detect(struct drm_connector *connector)
1188 {
1189         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1190         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1191         enum drm_connector_status status;
1192
1193         status = connector_status_disconnected;
1194         if (intel_dp_aux_native_read(intel_encoder,
1195                                      0x000, dp_priv->dpcd,
1196                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1197         {
1198                 if (dp_priv->dpcd[0] != 0)
1199                         status = connector_status_connected;
1200         }
1201         return status;
1202 }
1203
1204 /**
1205  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1206  *
1207  * \return true if DP port is connected.
1208  * \return false if DP port is disconnected.
1209  */
1210 static enum drm_connector_status
1211 intel_dp_detect(struct drm_connector *connector)
1212 {
1213         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1214         struct drm_device *dev = intel_encoder->base.dev;
1215         struct drm_i915_private *dev_priv = dev->dev_private;
1216         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1217         uint32_t temp, bit;
1218         enum drm_connector_status status;
1219
1220         dp_priv->has_audio = false;
1221
1222         if (HAS_PCH_SPLIT(dev))
1223                 return ironlake_dp_detect(connector);
1224
1225         temp = I915_READ(PORT_HOTPLUG_EN);
1226
1227         I915_WRITE(PORT_HOTPLUG_EN,
1228                temp |
1229                DPB_HOTPLUG_INT_EN |
1230                DPC_HOTPLUG_INT_EN |
1231                DPD_HOTPLUG_INT_EN);
1232
1233         POSTING_READ(PORT_HOTPLUG_EN);
1234
1235         switch (dp_priv->output_reg) {
1236         case DP_B:
1237                 bit = DPB_HOTPLUG_INT_STATUS;
1238                 break;
1239         case DP_C:
1240                 bit = DPC_HOTPLUG_INT_STATUS;
1241                 break;
1242         case DP_D:
1243                 bit = DPD_HOTPLUG_INT_STATUS;
1244                 break;
1245         default:
1246                 return connector_status_unknown;
1247         }
1248
1249         temp = I915_READ(PORT_HOTPLUG_STAT);
1250
1251         if ((temp & bit) == 0)
1252                 return connector_status_disconnected;
1253
1254         status = connector_status_disconnected;
1255         if (intel_dp_aux_native_read(intel_encoder,
1256                                      0x000, dp_priv->dpcd,
1257                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1258         {
1259                 if (dp_priv->dpcd[0] != 0)
1260                         status = connector_status_connected;
1261         }
1262         return status;
1263 }
1264
1265 static int intel_dp_get_modes(struct drm_connector *connector)
1266 {
1267         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1268         struct drm_device *dev = intel_encoder->base.dev;
1269         struct drm_i915_private *dev_priv = dev->dev_private;
1270         int ret;
1271
1272         /* We should parse the EDID data and find out if it has an audio sink
1273          */
1274
1275         ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
1276         if (ret)
1277                 return ret;
1278
1279         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1280         if (IS_eDP(intel_encoder)) {
1281                 if (dev_priv->panel_fixed_mode != NULL) {
1282                         struct drm_display_mode *mode;
1283                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1284                         drm_mode_probed_add(connector, mode);
1285                         return 1;
1286                 }
1287         }
1288         return 0;
1289 }
1290
1291 static void
1292 intel_dp_destroy (struct drm_connector *connector)
1293 {
1294         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1295
1296         if (intel_encoder->i2c_bus)
1297                 intel_i2c_destroy(intel_encoder->i2c_bus);
1298         drm_sysfs_connector_remove(connector);
1299         drm_connector_cleanup(connector);
1300         kfree(intel_encoder);
1301 }
1302
1303 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1304         .dpms = intel_dp_dpms,
1305         .mode_fixup = intel_dp_mode_fixup,
1306         .prepare = intel_encoder_prepare,
1307         .mode_set = intel_dp_mode_set,
1308         .commit = intel_encoder_commit,
1309 };
1310
1311 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1312         .dpms = drm_helper_connector_dpms,
1313         .detect = intel_dp_detect,
1314         .fill_modes = drm_helper_probe_single_connector_modes,
1315         .destroy = intel_dp_destroy,
1316 };
1317
1318 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1319         .get_modes = intel_dp_get_modes,
1320         .mode_valid = intel_dp_mode_valid,
1321         .best_encoder = intel_best_encoder,
1322 };
1323
1324 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1325 {
1326         drm_encoder_cleanup(encoder);
1327 }
1328
1329 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1330         .destroy = intel_dp_enc_destroy,
1331 };
1332
1333 void
1334 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1335 {
1336         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1337
1338         if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1339                 intel_dp_check_link_status(intel_encoder);
1340 }
1341
1342 /* Return which DP Port should be selected for Transcoder DP control */
1343 int
1344 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1345 {
1346         struct drm_device *dev = crtc->dev;
1347         struct drm_mode_config *mode_config = &dev->mode_config;
1348         struct drm_encoder *encoder;
1349         struct intel_encoder *intel_encoder = NULL;
1350
1351         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1352                 if (!encoder || encoder->crtc != crtc)
1353                         continue;
1354
1355                 intel_encoder = enc_to_intel_encoder(encoder);
1356                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1357                         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1358                         return dp_priv->output_reg;
1359                 }
1360         }
1361         return -1;
1362 }
1363
1364 void
1365 intel_dp_init(struct drm_device *dev, int output_reg)
1366 {
1367         struct drm_i915_private *dev_priv = dev->dev_private;
1368         struct drm_connector *connector;
1369         struct intel_encoder *intel_encoder;
1370         struct intel_dp_priv *dp_priv;
1371         const char *name = NULL;
1372
1373         intel_encoder = kcalloc(sizeof(struct intel_encoder) +
1374                                sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1375         if (!intel_encoder)
1376                 return;
1377
1378         dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
1379
1380         connector = &intel_encoder->base;
1381         drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1382                            DRM_MODE_CONNECTOR_DisplayPort);
1383         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1384
1385         if (output_reg == DP_A)
1386                 intel_encoder->type = INTEL_OUTPUT_EDP;
1387         else
1388                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1389
1390         if (output_reg == DP_B || output_reg == PCH_DP_B)
1391                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1392         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1393                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1394         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1395                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1396
1397         if (IS_eDP(intel_encoder))
1398                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1399
1400         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1401         connector->interlace_allowed = true;
1402         connector->doublescan_allowed = 0;
1403
1404         dp_priv->intel_encoder = intel_encoder;
1405         dp_priv->output_reg = output_reg;
1406         dp_priv->has_audio = false;
1407         dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1408         intel_encoder->dev_priv = dp_priv;
1409
1410         drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1411                          DRM_MODE_ENCODER_TMDS);
1412         drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1413
1414         drm_mode_connector_attach_encoder(&intel_encoder->base,
1415                                           &intel_encoder->enc);
1416         drm_sysfs_connector_add(connector);
1417
1418         /* Set up the DDC bus. */
1419         switch (output_reg) {
1420                 case DP_A:
1421                         name = "DPDDC-A";
1422                         break;
1423                 case DP_B:
1424                 case PCH_DP_B:
1425                         dev_priv->hotplug_supported_mask |=
1426                                 HDMIB_HOTPLUG_INT_STATUS;
1427                         name = "DPDDC-B";
1428                         break;
1429                 case DP_C:
1430                 case PCH_DP_C:
1431                         dev_priv->hotplug_supported_mask |=
1432                                 HDMIC_HOTPLUG_INT_STATUS;
1433                         name = "DPDDC-C";
1434                         break;
1435                 case DP_D:
1436                 case PCH_DP_D:
1437                         dev_priv->hotplug_supported_mask |=
1438                                 HDMID_HOTPLUG_INT_STATUS;
1439                         name = "DPDDC-D";
1440                         break;
1441         }
1442
1443         intel_dp_i2c_init(intel_encoder, name);
1444
1445         intel_encoder->ddc_bus = &dp_priv->adapter;
1446         intel_encoder->hot_plug = intel_dp_hot_plug;
1447
1448         if (output_reg == DP_A) {
1449                 /* initialize panel mode from VBT if available for eDP */
1450                 if (dev_priv->lfp_lvds_vbt_mode) {
1451                         dev_priv->panel_fixed_mode =
1452                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1453                         if (dev_priv->panel_fixed_mode) {
1454                                 dev_priv->panel_fixed_mode->type |=
1455                                         DRM_MODE_TYPE_PREFERRED;
1456                         }
1457                 }
1458         }
1459
1460         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1461          * 0xd.  Failure to do so will result in spurious interrupts being
1462          * generated on the port when a cable is not attached.
1463          */
1464         if (IS_G4X(dev) && !IS_GM45(dev)) {
1465                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1466                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1467         }
1468 }