drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc.h"
  32 #include "drm_crtc_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "drm_dp_helper.h"
  37
  38
  39 #define DP_LINK_STATUS_SIZE     6
  40 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  41
  42 #define DP_LINK_CONFIGURATION_SIZE      9
  43
  44 #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
  45
  46 struct intel_dp_priv {
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int dpms_mode;
  52         uint8_t link_bw;
  53         uint8_t lane_count;
  54         uint8_t dpcd[4];
  55         struct intel_encoder *intel_encoder;
  56         struct i2c_adapter adapter;
  57         struct i2c_algo_dp_aux_data algo;
  58 };
  59
  60 static void
  61 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
  62                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
  63
  64 static void
  65 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
  66
  67 void
  68 intel_edp_link_config (struct intel_encoder *intel_encoder,
  69                 int *lane_num, int *link_bw)
  70 {
  71         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  72
  73         *lane_num = dp_priv->lane_count;
  74         if (dp_priv->link_bw == DP_LINK_BW_1_62)
  75                 *link_bw = 162000;
  76         else if (dp_priv->link_bw == DP_LINK_BW_2_7)
  77                 *link_bw = 270000;
  78 }
  79
  80 static int
  81 intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
  82 {
  83         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  84         int max_lane_count = 4;
  85
  86         if (dp_priv->dpcd[0] >= 0x11) {
  87                 max_lane_count = dp_priv->dpcd[2] & 0x1f;
  88                 switch (max_lane_count) {
  89                 case 1: case 2: case 4:
  90                         break;
  91                 default:
  92                         max_lane_count = 4;
  93                 }
  94         }
  95         return max_lane_count;
  96 }
  97
  98 static int
  99 intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
 100 {
 101         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 102         int max_link_bw = dp_priv->dpcd[1];
 103
 104         switch (max_link_bw) {
 105         case DP_LINK_BW_1_62:
 106         case DP_LINK_BW_2_7:
 107                 break;
 108         default:
 109                 max_link_bw = DP_LINK_BW_1_62;
 110                 break;
 111         }
 112         return max_link_bw;
 113 }
 114
 115 static int
 116 intel_dp_link_clock(uint8_t link_bw)
 117 {
 118         if (link_bw == DP_LINK_BW_2_7)
 119                 return 270000;
 120         else
 121                 return 162000;
 122 }
 123
 124 /* I think this is a fiction */
 125 static int
 126 intel_dp_link_required(struct drm_device *dev,
 127                        struct intel_encoder *intel_encoder, int pixel_clock)
 128 {
 129         struct drm_i915_private *dev_priv = dev->dev_private;
 130
 131         if (IS_eDP(intel_encoder))
 132                 return (pixel_clock * dev_priv->edp_bpp) / 8;
 133         else
 134                 return pixel_clock * 3;
 135 }
 136
 137 static int
 138 intel_dp_mode_valid(struct drm_connector *connector,
 139                     struct drm_display_mode *mode)
 140 {
 141         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
 142         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
 143         int max_lanes = intel_dp_max_lane_count(intel_encoder);
 144
 145         if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
 146                         > max_link_clock * max_lanes)
 147                 return MODE_CLOCK_HIGH;
 148
 149         if (mode->clock < 10000)
 150                 return MODE_CLOCK_LOW;
 151
 152         return MODE_OK;
 153 }
 154
 155 static uint32_t
 156 pack_aux(uint8_t *src, int src_bytes)
 157 {
 158         int     i;
 159         uint32_t v = 0;
 160
 161         if (src_bytes > 4)
 162                 src_bytes = 4;
 163         for (i = 0; i < src_bytes; i++)
 164                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 165         return v;
 166 }
 167
 168 static void
 169 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 170 {
 171         int i;
 172         if (dst_bytes > 4)
 173                 dst_bytes = 4;
 174         for (i = 0; i < dst_bytes; i++)
 175                 dst[i] = src >> ((3-i) * 8);
 176 }
 177
 178 /* hrawclock is 1/4 the FSB frequency */
 179 static int
 180 intel_hrawclk(struct drm_device *dev)
 181 {
 182         struct drm_i915_private *dev_priv = dev->dev_private;
 183         uint32_t clkcfg;
 184
 185         clkcfg = I915_READ(CLKCFG);
 186         switch (clkcfg & CLKCFG_FSB_MASK) {
 187         case CLKCFG_FSB_400:
 188                 return 100;
 189         case CLKCFG_FSB_533:
 190                 return 133;
 191         case CLKCFG_FSB_667:
 192                 return 166;
 193         case CLKCFG_FSB_800:
 194                 return 200;
 195         case CLKCFG_FSB_1067:
 196                 return 266;
 197         case CLKCFG_FSB_1333:
 198                 return 333;
 199         /* these two are just a guess; one of them might be right */
 200         case CLKCFG_FSB_1600:
 201         case CLKCFG_FSB_1600_ALT:
 202                 return 400;
 203         default:
 204                 return 133;
 205         }
 206 }
 207
 208 static int
 209 intel_dp_aux_ch(struct intel_encoder *intel_encoder,
 210                 uint8_t *send, int send_bytes,
 211                 uint8_t *recv, int recv_size)
 212 {
 213         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 214         uint32_t output_reg = dp_priv->output_reg;
 215         struct drm_device *dev = intel_encoder->base.dev;
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         uint32_t ch_ctl = output_reg + 0x10;
 218         uint32_t ch_data = ch_ctl + 4;
 219         int i;
 220         int recv_bytes;
 221         uint32_t ctl;
 222         uint32_t status;
 223         uint32_t aux_clock_divider;
 224         int try;
 225
 226         /* The clock divider is based off the hrawclk,
 227          * and would like to run at 2MHz. So, take the
 228          * hrawclk value and divide by 2 and use that
 229          */
 230         if (IS_eDP(intel_encoder))
 231                 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 232         else if (HAS_PCH_SPLIT(dev))
 233                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 234         else
 235                 aux_clock_divider = intel_hrawclk(dev) / 2;
 236
 237         /* Must try at least 3 times according to DP spec */
 238         for (try = 0; try < 5; try++) {
 239                 /* Load the send data into the aux channel data registers */
 240                 for (i = 0; i < send_bytes; i += 4) {
 241                         uint32_t    d = pack_aux(send + i, send_bytes - i);
 242
 243                         I915_WRITE(ch_data + i, d);
 244                 }
 245
 246                 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
 247                        DP_AUX_CH_CTL_TIME_OUT_400us |
 248                        (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 249                        (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 250                        (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 251                        DP_AUX_CH_CTL_DONE |
 252                        DP_AUX_CH_CTL_TIME_OUT_ERROR |
 253                        DP_AUX_CH_CTL_RECEIVE_ERROR);
 254
 255                 /* Send the command and wait for it to complete */
 256                 I915_WRITE(ch_ctl, ctl);
 257                 (void) I915_READ(ch_ctl);
 258                 for (;;) {
 259                         udelay(100);
 260                         status = I915_READ(ch_ctl);
 261                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 262                                 break;
 263                 }
 264
 265                 /* Clear done status and any errors */
 266                 I915_WRITE(ch_ctl, (status |
 267                                 DP_AUX_CH_CTL_DONE |
 268                                 DP_AUX_CH_CTL_TIME_OUT_ERROR |
 269                                 DP_AUX_CH_CTL_RECEIVE_ERROR));
 270                 (void) I915_READ(ch_ctl);
 271                 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
 272                         break;
 273         }
 274
 275         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 276                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 277                 return -EBUSY;
 278         }
 279
 280         /* Check for timeout or receive error.
 281          * Timeouts occur when the sink is not connected
 282          */
 283         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 284                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 285                 return -EIO;
 286         }
 287
 288         /* Timeouts occur when the device isn't connected, so they're
 289          * "normal" -- don't fill the kernel log with these */
 290         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 291                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 292                 return -ETIMEDOUT;
 293         }
 294
 295         /* Unload any bytes sent back from the other side */
 296         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 297                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 298
 299         if (recv_bytes > recv_size)
 300                 recv_bytes = recv_size;
 301
 302         for (i = 0; i < recv_bytes; i += 4) {
 303                 uint32_t    d = I915_READ(ch_data + i);
 304
 305                 unpack_aux(d, recv + i, recv_bytes - i);
 306         }
 307
 308         return recv_bytes;
 309 }
 310
 311 /* Write data to the aux channel in native mode */
 312 static int
 313 intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
 314                           uint16_t address, uint8_t *send, int send_bytes)
 315 {
 316         int ret;
 317         uint8_t msg[20];
 318         int msg_bytes;
 319         uint8_t ack;
 320
 321         if (send_bytes > 16)
 322                 return -1;
 323         msg[0] = AUX_NATIVE_WRITE << 4;
 324         msg[1] = address >> 8;
 325         msg[2] = address & 0xff;
 326         msg[3] = send_bytes - 1;
 327         memcpy(&msg[4], send, send_bytes);
 328         msg_bytes = send_bytes + 4;
 329         for (;;) {
 330                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
 331                 if (ret < 0)
 332                         return ret;
 333                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 334                         break;
 335                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 336                         udelay(100);
 337                 else
 338                         return -EIO;
 339         }
 340         return send_bytes;
 341 }
 342
 343 /* Write a single byte to the aux channel in native mode */
 344 static int
 345 intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
 346                             uint16_t address, uint8_t byte)
 347 {
 348         return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
 349 }
 350
 351 /* read bytes from a native aux channel */
 352 static int
 353 intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
 354                          uint16_t address, uint8_t *recv, int recv_bytes)
 355 {
 356         uint8_t msg[4];
 357         int msg_bytes;
 358         uint8_t reply[20];
 359         int reply_bytes;
 360         uint8_t ack;
 361         int ret;
 362
 363         msg[0] = AUX_NATIVE_READ << 4;
 364         msg[1] = address >> 8;
 365         msg[2] = address & 0xff;
 366         msg[3] = recv_bytes - 1;
 367
 368         msg_bytes = 4;
 369         reply_bytes = recv_bytes + 1;
 370
 371         for (;;) {
 372                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
 373                                       reply, reply_bytes);
 374                 if (ret == 0)
 375                         return -EPROTO;
 376                 if (ret < 0)
 377                         return ret;
 378                 ack = reply[0];
 379                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 380                         memcpy(recv, reply + 1, ret - 1);
 381                         return ret - 1;
 382                 }
 383                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 384                         udelay(100);
 385                 else
 386                         return -EIO;
 387         }
 388 }
 389
 390 static int
 391 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 392                     uint8_t write_byte, uint8_t *read_byte)
 393 {
 394         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 395         struct intel_dp_priv *dp_priv = container_of(adapter,
 396                                                      struct intel_dp_priv,
 397                                                      adapter);
 398         struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
 399         uint16_t address = algo_data->address;
 400         uint8_t msg[5];
 401         uint8_t reply[2];
 402         int msg_bytes;
 403         int reply_bytes;
 404         int ret;
 405
 406         /* Set up the command byte */
 407         if (mode & MODE_I2C_READ)
 408                 msg[0] = AUX_I2C_READ << 4;
 409         else
 410                 msg[0] = AUX_I2C_WRITE << 4;
 411
 412         if (!(mode & MODE_I2C_STOP))
 413                 msg[0] |= AUX_I2C_MOT << 4;
 414
 415         msg[1] = address >> 8;
 416         msg[2] = address;
 417
 418         switch (mode) {
 419         case MODE_I2C_WRITE:
 420                 msg[3] = 0;
 421                 msg[4] = write_byte;
 422                 msg_bytes = 5;
 423                 reply_bytes = 1;
 424                 break;
 425         case MODE_I2C_READ:
 426                 msg[3] = 0;
 427                 msg_bytes = 4;
 428                 reply_bytes = 2;
 429                 break;
 430         default:
 431                 msg_bytes = 3;
 432                 reply_bytes = 1;
 433                 break;
 434         }
 435
 436         for (;;) {
 437           ret = intel_dp_aux_ch(intel_encoder,
 438                                 msg, msg_bytes,
 439                                 reply, reply_bytes);
 440                 if (ret < 0) {
 441                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 442                         return ret;
 443                 }
 444                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 445                 case AUX_I2C_REPLY_ACK:
 446                         if (mode == MODE_I2C_READ) {
 447                                 *read_byte = reply[1];
 448                         }
 449                         return reply_bytes - 1;
 450                 case AUX_I2C_REPLY_NACK:
 451                         DRM_DEBUG_KMS("aux_ch nack\n");
 452                         return -EREMOTEIO;
 453                 case AUX_I2C_REPLY_DEFER:
 454                         DRM_DEBUG_KMS("aux_ch defer\n");
 455                         udelay(100);
 456                         break;
 457                 default:
 458                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 459                         return -EREMOTEIO;
 460                 }
 461         }
 462 }
 463
 464 static int
 465 intel_dp_i2c_init(struct intel_encoder *intel_encoder, const char *name)
 466 {
 467         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 468
 469         DRM_DEBUG_KMS("i2c_init %s\n", name);
 470         dp_priv->algo.running = false;
 471         dp_priv->algo.address = 0;
 472         dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
 473
 474         memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
 475         dp_priv->adapter.owner = THIS_MODULE;
 476         dp_priv->adapter.class = I2C_CLASS_DDC;
 477         strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
 478         dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
 479         dp_priv->adapter.algo_data = &dp_priv->algo;
 480         dp_priv->adapter.dev.parent = &intel_encoder->base.kdev;
 481
 482         return i2c_dp_aux_add_bus(&dp_priv->adapter);
 483 }
 484
 485 static bool
 486 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 487                     struct drm_display_mode *adjusted_mode)
 488 {
 489         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 490         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 491         int lane_count, clock;
 492         int max_lane_count = intel_dp_max_lane_count(intel_encoder);
 493         int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
 494         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 495
 496         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 497                 for (clock = 0; clock <= max_clock; clock++) {
 498                         int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
 499
 500                         if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
 501                                         <= link_avail) {
 502                                 dp_priv->link_bw = bws[clock];
 503                                 dp_priv->lane_count = lane_count;
 504                                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 505                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 506                                                 "count %d clock %d\n",
 507                                        dp_priv->link_bw, dp_priv->lane_count,
 508                                        adjusted_mode->clock);
 509                                 return true;
 510                         }
 511                 }
 512         }
 513         return false;
 514 }
 515
 516 struct intel_dp_m_n {
 517         uint32_t        tu;
 518         uint32_t        gmch_m;
 519         uint32_t        gmch_n;
 520         uint32_t        link_m;
 521         uint32_t        link_n;
 522 };
 523
 524 static void
 525 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 526 {
 527         while (*num > 0xffffff || *den > 0xffffff) {
 528                 *num >>= 1;
 529                 *den >>= 1;
 530         }
 531 }
 532
 533 static void
 534 intel_dp_compute_m_n(int bytes_per_pixel,
 535                      int nlanes,
 536                      int pixel_clock,
 537                      int link_clock,
 538                      struct intel_dp_m_n *m_n)
 539 {
 540         m_n->tu = 64;
 541         m_n->gmch_m = pixel_clock * bytes_per_pixel;
 542         m_n->gmch_n = link_clock * nlanes;
 543         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 544         m_n->link_m = pixel_clock;
 545         m_n->link_n = link_clock;
 546         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 547 }
 548
 549 void
 550 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 551                  struct drm_display_mode *adjusted_mode)
 552 {
 553         struct drm_device *dev = crtc->dev;
 554         struct drm_mode_config *mode_config = &dev->mode_config;
 555         struct drm_connector *connector;
 556         struct drm_i915_private *dev_priv = dev->dev_private;
 557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 558         int lane_count = 4;
 559         struct intel_dp_m_n m_n;
 560
 561         /*
 562          * Find the lane count in the intel_encoder private
 563          */
 564         list_for_each_entry(connector, &mode_config->connector_list, head) {
 565                 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
 566                 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 567
 568                 if (!connector->encoder || connector->encoder->crtc != crtc)
 569                         continue;
 570
 571                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
 572                         lane_count = dp_priv->lane_count;
 573                         break;
 574                 }
 575         }
 576
 577         /*
 578          * Compute the GMCH and Link ratios. The '3' here is
 579          * the number of bytes_per_pixel post-LUT, which we always
 580          * set up for 8-bits of R/G/B, or 3 bytes total.
 581          */
 582         intel_dp_compute_m_n(3, lane_count,
 583                              mode->clock, adjusted_mode->clock, &m_n);
 584
 585         if (HAS_PCH_SPLIT(dev)) {
 586                 if (intel_crtc->pipe == 0) {
 587                         I915_WRITE(TRANSA_DATA_M1,
 588                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 589                                    m_n.gmch_m);
 590                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 591                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 592                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 593                 } else {
 594                         I915_WRITE(TRANSB_DATA_M1,
 595                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 596                                    m_n.gmch_m);
 597                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 598                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 599                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 600                 }
 601         } else {
 602                 if (intel_crtc->pipe == 0) {
 603                         I915_WRITE(PIPEA_GMCH_DATA_M,
 604                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 605                                    m_n.gmch_m);
 606                         I915_WRITE(PIPEA_GMCH_DATA_N,
 607                                    m_n.gmch_n);
 608                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 609                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 610                 } else {
 611                         I915_WRITE(PIPEB_GMCH_DATA_M,
 612                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 613                                    m_n.gmch_m);
 614                         I915_WRITE(PIPEB_GMCH_DATA_N,
 615                                         m_n.gmch_n);
 616                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 617                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 618                 }
 619         }
 620 }
 621
 622 static void
 623 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 624                   struct drm_display_mode *adjusted_mode)
 625 {
 626         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 627         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 628         struct drm_crtc *crtc = intel_encoder->enc.crtc;
 629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 630
 631         dp_priv->DP = (DP_LINK_TRAIN_OFF |
 632                         DP_VOLTAGE_0_4 |
 633                         DP_PRE_EMPHASIS_0 |
 634                         DP_SYNC_VS_HIGH |
 635                         DP_SYNC_HS_HIGH);
 636
 637         switch (dp_priv->lane_count) {
 638         case 1:
 639                 dp_priv->DP |= DP_PORT_WIDTH_1;
 640                 break;
 641         case 2:
 642                 dp_priv->DP |= DP_PORT_WIDTH_2;
 643                 break;
 644         case 4:
 645                 dp_priv->DP |= DP_PORT_WIDTH_4;
 646                 break;
 647         }
 648         if (dp_priv->has_audio)
 649                 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
 650
 651         memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 652         dp_priv->link_configuration[0] = dp_priv->link_bw;
 653         dp_priv->link_configuration[1] = dp_priv->lane_count;
 654
 655         /*
 656          * Check for DPCD version > 1.1,
 657          * enable enahanced frame stuff in that case
 658          */
 659         if (dp_priv->dpcd[0] >= 0x11) {
 660                 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 661                 dp_priv->DP |= DP_ENHANCED_FRAMING;
 662         }
 663
 664         if (intel_crtc->pipe == 1)
 665                 dp_priv->DP |= DP_PIPEB_SELECT;
 666
 667         if (IS_eDP(intel_encoder)) {
 668                 /* don't miss out required setting for eDP */
 669                 dp_priv->DP |= DP_PLL_ENABLE;
 670                 if (adjusted_mode->clock < 200000)
 671                         dp_priv->DP |= DP_PLL_FREQ_160MHZ;
 672                 else
 673                         dp_priv->DP |= DP_PLL_FREQ_270MHZ;
 674         }
 675 }
 676
 677 static void ironlake_edp_backlight_on (struct drm_device *dev)
 678 {
 679         struct drm_i915_private *dev_priv = dev->dev_private;
 680         u32 pp;
 681
 682         DRM_DEBUG_KMS("\n");
 683         pp = I915_READ(PCH_PP_CONTROL);
 684         pp |= EDP_BLC_ENABLE;
 685         I915_WRITE(PCH_PP_CONTROL, pp);
 686 }
 687
 688 static void ironlake_edp_backlight_off (struct drm_device *dev)
 689 {
 690         struct drm_i915_private *dev_priv = dev->dev_private;
 691         u32 pp;
 692
 693         DRM_DEBUG_KMS("\n");
 694         pp = I915_READ(PCH_PP_CONTROL);
 695         pp &= ~EDP_BLC_ENABLE;
 696         I915_WRITE(PCH_PP_CONTROL, pp);
 697 }
 698
 699 static void
 700 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 701 {
 702         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 703         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 704         struct drm_device *dev = intel_encoder->base.dev;
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706         uint32_t dp_reg = I915_READ(dp_priv->output_reg);
 707
 708         if (mode != DRM_MODE_DPMS_ON) {
 709                 if (dp_reg & DP_PORT_EN) {
 710                         intel_dp_link_down(intel_encoder, dp_priv->DP);
 711                         if (IS_eDP(intel_encoder))
 712                                 ironlake_edp_backlight_off(dev);
 713                 }
 714         } else {
 715                 if (!(dp_reg & DP_PORT_EN)) {
 716                         intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
 717                         if (IS_eDP(intel_encoder))
 718                                 ironlake_edp_backlight_on(dev);
 719                 }
 720         }
 721         dp_priv->dpms_mode = mode;
 722 }
 723
 724 /*
 725  * Fetch AUX CH registers 0x202 - 0x207 which contain
 726  * link status information
 727  */
 728 static bool
 729 intel_dp_get_link_status(struct intel_encoder *intel_encoder,
 730                          uint8_t link_status[DP_LINK_STATUS_SIZE])
 731 {
 732         int ret;
 733
 734         ret = intel_dp_aux_native_read(intel_encoder,
 735                                        DP_LANE0_1_STATUS,
 736                                        link_status, DP_LINK_STATUS_SIZE);
 737         if (ret != DP_LINK_STATUS_SIZE)
 738                 return false;
 739         return true;
 740 }
 741
 742 static uint8_t
 743 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 744                      int r)
 745 {
 746         return link_status[r - DP_LANE0_1_STATUS];
 747 }
 748
 749 static uint8_t
 750 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 751                                  int lane)
 752 {
 753         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 754         int         s = ((lane & 1) ?
 755                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 756                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 757         uint8_t l = intel_dp_link_status(link_status, i);
 758
 759         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 760 }
 761
 762 static uint8_t
 763 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 764                                       int lane)
 765 {
 766         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 767         int         s = ((lane & 1) ?
 768                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 769                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 770         uint8_t l = intel_dp_link_status(link_status, i);
 771
 772         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 773 }
 774
 775
 776 #if 0
 777 static char     *voltage_names[] = {
 778         "0.4V", "0.6V", "0.8V", "1.2V"
 779 };
 780 static char     *pre_emph_names[] = {
 781         "0dB", "3.5dB", "6dB", "9.5dB"
 782 };
 783 static char     *link_train_names[] = {
 784         "pattern 1", "pattern 2", "idle", "off"
 785 };
 786 #endif
 787
 788 /*
 789  * These are source-specific values; current Intel hardware supports
 790  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 791  */
 792 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
 793
 794 static uint8_t
 795 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 796 {
 797         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 798         case DP_TRAIN_VOLTAGE_SWING_400:
 799                 return DP_TRAIN_PRE_EMPHASIS_6;
 800         case DP_TRAIN_VOLTAGE_SWING_600:
 801                 return DP_TRAIN_PRE_EMPHASIS_6;
 802         case DP_TRAIN_VOLTAGE_SWING_800:
 803                 return DP_TRAIN_PRE_EMPHASIS_3_5;
 804         case DP_TRAIN_VOLTAGE_SWING_1200:
 805         default:
 806                 return DP_TRAIN_PRE_EMPHASIS_0;
 807         }
 808 }
 809
 810 static void
 811 intel_get_adjust_train(struct intel_encoder *intel_encoder,
 812                        uint8_t link_status[DP_LINK_STATUS_SIZE],
 813                        int lane_count,
 814                        uint8_t train_set[4])
 815 {
 816         uint8_t v = 0;
 817         uint8_t p = 0;
 818         int lane;
 819
 820         for (lane = 0; lane < lane_count; lane++) {
 821                 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
 822                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
 823
 824                 if (this_v > v)
 825                         v = this_v;
 826                 if (this_p > p)
 827                         p = this_p;
 828         }
 829
 830         if (v >= I830_DP_VOLTAGE_MAX)
 831                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 832
 833         if (p >= intel_dp_pre_emphasis_max(v))
 834                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 835
 836         for (lane = 0; lane < 4; lane++)
 837                 train_set[lane] = v | p;
 838 }
 839
 840 static uint32_t
 841 intel_dp_signal_levels(uint8_t train_set, int lane_count)
 842 {
 843         uint32_t        signal_levels = 0;
 844
 845         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 846         case DP_TRAIN_VOLTAGE_SWING_400:
 847         default:
 848                 signal_levels |= DP_VOLTAGE_0_4;
 849                 break;
 850         case DP_TRAIN_VOLTAGE_SWING_600:
 851                 signal_levels |= DP_VOLTAGE_0_6;
 852                 break;
 853         case DP_TRAIN_VOLTAGE_SWING_800:
 854                 signal_levels |= DP_VOLTAGE_0_8;
 855                 break;
 856         case DP_TRAIN_VOLTAGE_SWING_1200:
 857                 signal_levels |= DP_VOLTAGE_1_2;
 858                 break;
 859         }
 860         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 861         case DP_TRAIN_PRE_EMPHASIS_0:
 862         default:
 863                 signal_levels |= DP_PRE_EMPHASIS_0;
 864                 break;
 865         case DP_TRAIN_PRE_EMPHASIS_3_5:
 866                 signal_levels |= DP_PRE_EMPHASIS_3_5;
 867                 break;
 868         case DP_TRAIN_PRE_EMPHASIS_6:
 869                 signal_levels |= DP_PRE_EMPHASIS_6;
 870                 break;
 871         case DP_TRAIN_PRE_EMPHASIS_9_5:
 872                 signal_levels |= DP_PRE_EMPHASIS_9_5;
 873                 break;
 874         }
 875         return signal_levels;
 876 }
 877
 878 static uint8_t
 879 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 880                       int lane)
 881 {
 882         int i = DP_LANE0_1_STATUS + (lane >> 1);
 883         int s = (lane & 1) * 4;
 884         uint8_t l = intel_dp_link_status(link_status, i);
 885
 886         return (l >> s) & 0xf;
 887 }
 888
 889 /* Check for clock recovery is done on all channels */
 890 static bool
 891 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 892 {
 893         int lane;
 894         uint8_t lane_status;
 895
 896         for (lane = 0; lane < lane_count; lane++) {
 897                 lane_status = intel_get_lane_status(link_status, lane);
 898                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 899                         return false;
 900         }
 901         return true;
 902 }
 903
 904 /* Check to see if channel eq is done on all channels */
 905 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
 906                          DP_LANE_CHANNEL_EQ_DONE|\
 907                          DP_LANE_SYMBOL_LOCKED)
 908 static bool
 909 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 910 {
 911         uint8_t lane_align;
 912         uint8_t lane_status;
 913         int lane;
 914
 915         lane_align = intel_dp_link_status(link_status,
 916                                           DP_LANE_ALIGN_STATUS_UPDATED);
 917         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
 918                 return false;
 919         for (lane = 0; lane < lane_count; lane++) {
 920                 lane_status = intel_get_lane_status(link_status, lane);
 921                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
 922                         return false;
 923         }
 924         return true;
 925 }
 926
 927 static bool
 928 intel_dp_set_link_train(struct intel_encoder *intel_encoder,
 929                         uint32_t dp_reg_value,
 930                         uint8_t dp_train_pat,
 931                         uint8_t train_set[4],
 932                         bool first)
 933 {
 934         struct drm_device *dev = intel_encoder->base.dev;
 935         struct drm_i915_private *dev_priv = dev->dev_private;
 936         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 937         int ret;
 938
 939         I915_WRITE(dp_priv->output_reg, dp_reg_value);
 940         POSTING_READ(dp_priv->output_reg);
 941         if (first)
 942                 intel_wait_for_vblank(dev);
 943
 944         intel_dp_aux_native_write_1(intel_encoder,
 945                                     DP_TRAINING_PATTERN_SET,
 946                                     dp_train_pat);
 947
 948         ret = intel_dp_aux_native_write(intel_encoder,
 949                                         DP_TRAINING_LANE0_SET, train_set, 4);
 950         if (ret != 4)
 951                 return false;
 952
 953         return true;
 954 }
 955
 956 static void
 957 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
 958                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
 959 {
 960         struct drm_device *dev = intel_encoder->base.dev;
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 963         uint8_t train_set[4];
 964         uint8_t link_status[DP_LINK_STATUS_SIZE];
 965         int i;
 966         uint8_t voltage;
 967         bool clock_recovery = false;
 968         bool channel_eq = false;
 969         bool first = true;
 970         int tries;
 971
 972         /* Write the link configuration data */
 973         intel_dp_aux_native_write(intel_encoder, 0x100,
 974                                   link_configuration, DP_LINK_CONFIGURATION_SIZE);
 975
 976         DP |= DP_PORT_EN;
 977         DP &= ~DP_LINK_TRAIN_MASK;
 978         memset(train_set, 0, 4);
 979         voltage = 0xff;
 980         tries = 0;
 981         clock_recovery = false;
 982         for (;;) {
 983                 /* Use train_set[0] to set the voltage and pre emphasis values */
 984                 uint32_t    signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
 985                 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
 986
 987                 if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_1,
 988                                              DP_TRAINING_PATTERN_1, train_set, first))
 989                         break;
 990                 first = false;
 991                 /* Set training pattern 1 */
 992
 993                 udelay(100);
 994                 if (!intel_dp_get_link_status(intel_encoder, link_status))
 995                         break;
 996
 997                 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
 998                         clock_recovery = true;
 999                         break;
1000                 }
1001
1002                 /* Check to see if we've tried the max voltage */
1003                 for (i = 0; i < dp_priv->lane_count; i++)
1004                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1005                                 break;
1006                 if (i == dp_priv->lane_count)
1007                         break;
1008
1009                 /* Check to see if we've tried the same voltage 5 times */
1010                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1011                         ++tries;
1012                         if (tries == 5)
1013                                 break;
1014                 } else
1015                         tries = 0;
1016                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1017
1018                 /* Compute new train_set as requested by target */
1019                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1020         }
1021
1022         /* channel equalization */
1023         tries = 0;
1024         channel_eq = false;
1025         for (;;) {
1026                 /* Use train_set[0] to set the voltage and pre emphasis values */
1027                 uint32_t    signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1028                 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1029
1030                 /* channel eq pattern */
1031                 if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_2,
1032                                              DP_TRAINING_PATTERN_2, train_set,
1033                                              false))
1034                         break;
1035
1036                 udelay(400);
1037                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1038                         break;
1039
1040                 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1041                         channel_eq = true;
1042                         break;
1043                 }
1044
1045                 /* Try 5 times */
1046                 if (tries > 5)
1047                         break;
1048
1049                 /* Compute new train_set as requested by target */
1050                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1051                 ++tries;
1052         }
1053
1054         I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
1055         POSTING_READ(dp_priv->output_reg);
1056         intel_dp_aux_native_write_1(intel_encoder,
1057                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1058 }
1059
1060 static void
1061 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1062 {
1063         struct drm_device *dev = intel_encoder->base.dev;
1064         struct drm_i915_private *dev_priv = dev->dev_private;
1065         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1066
1067         DRM_DEBUG_KMS("\n");
1068
1069         if (IS_eDP(intel_encoder)) {
1070                 DP &= ~DP_PLL_ENABLE;
1071                 I915_WRITE(dp_priv->output_reg, DP);
1072                 POSTING_READ(dp_priv->output_reg);
1073                 udelay(100);
1074         }
1075
1076         DP &= ~DP_LINK_TRAIN_MASK;
1077         I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1078         POSTING_READ(dp_priv->output_reg);
1079
1080         udelay(17000);
1081
1082         if (IS_eDP(intel_encoder))
1083                 DP |= DP_LINK_TRAIN_OFF;
1084         I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1085         POSTING_READ(dp_priv->output_reg);
1086 }
1087
1088 /*
1089  * According to DP spec
1090  * 5.1.2:
1091  *  1. Read DPCD
1092  *  2. Configure link according to Receiver Capabilities
1093  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1094  *  4. Check link status on receipt of hot-plug interrupt
1095  */
1096
1097 static void
1098 intel_dp_check_link_status(struct intel_encoder *intel_encoder)
1099 {
1100         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1101         uint8_t link_status[DP_LINK_STATUS_SIZE];
1102
1103         if (!intel_encoder->enc.crtc)
1104                 return;
1105
1106         if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1107                 intel_dp_link_down(intel_encoder, dp_priv->DP);
1108                 return;
1109         }
1110
1111         if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1112                 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
1113 }
1114
1115 static enum drm_connector_status
1116 ironlake_dp_detect(struct drm_connector *connector)
1117 {
1118         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1119         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1120         enum drm_connector_status status;
1121
1122         status = connector_status_disconnected;
1123         if (intel_dp_aux_native_read(intel_encoder,
1124                                      0x000, dp_priv->dpcd,
1125                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1126         {
1127                 if (dp_priv->dpcd[0] != 0)
1128                         status = connector_status_connected;
1129         }
1130         return status;
1131 }
1132
1133 /**
1134  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1135  *
1136  * \return true if DP port is connected.
1137  * \return false if DP port is disconnected.
1138  */
1139 static enum drm_connector_status
1140 intel_dp_detect(struct drm_connector *connector)
1141 {
1142         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1143         struct drm_device *dev = intel_encoder->base.dev;
1144         struct drm_i915_private *dev_priv = dev->dev_private;
1145         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1146         uint32_t temp, bit;
1147         enum drm_connector_status status;
1148
1149         dp_priv->has_audio = false;
1150
1151         if (HAS_PCH_SPLIT(dev))
1152                 return ironlake_dp_detect(connector);
1153
1154         temp = I915_READ(PORT_HOTPLUG_EN);
1155
1156         I915_WRITE(PORT_HOTPLUG_EN,
1157                temp |
1158                DPB_HOTPLUG_INT_EN |
1159                DPC_HOTPLUG_INT_EN |
1160                DPD_HOTPLUG_INT_EN);
1161
1162         POSTING_READ(PORT_HOTPLUG_EN);
1163
1164         switch (dp_priv->output_reg) {
1165         case DP_B:
1166                 bit = DPB_HOTPLUG_INT_STATUS;
1167                 break;
1168         case DP_C:
1169                 bit = DPC_HOTPLUG_INT_STATUS;
1170                 break;
1171         case DP_D:
1172                 bit = DPD_HOTPLUG_INT_STATUS;
1173                 break;
1174         default:
1175                 return connector_status_unknown;
1176         }
1177
1178         temp = I915_READ(PORT_HOTPLUG_STAT);
1179
1180         if ((temp & bit) == 0)
1181                 return connector_status_disconnected;
1182
1183         status = connector_status_disconnected;
1184         if (intel_dp_aux_native_read(intel_encoder,
1185                                      0x000, dp_priv->dpcd,
1186                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1187         {
1188                 if (dp_priv->dpcd[0] != 0)
1189                         status = connector_status_connected;
1190         }
1191         return status;
1192 }
1193
1194 static int intel_dp_get_modes(struct drm_connector *connector)
1195 {
1196         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1197         struct drm_device *dev = intel_encoder->base.dev;
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         int ret;
1200
1201         /* We should parse the EDID data and find out if it has an audio sink
1202          */
1203
1204         ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
1205         if (ret)
1206                 return ret;
1207
1208         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1209         if (IS_eDP(intel_encoder)) {
1210                 if (dev_priv->panel_fixed_mode != NULL) {
1211                         struct drm_display_mode *mode;
1212                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1213                         drm_mode_probed_add(connector, mode);
1214                         return 1;
1215                 }
1216         }
1217         return 0;
1218 }
1219
1220 static void
1221 intel_dp_destroy (struct drm_connector *connector)
1222 {
1223         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1224
1225         if (intel_encoder->i2c_bus)
1226                 intel_i2c_destroy(intel_encoder->i2c_bus);
1227         drm_sysfs_connector_remove(connector);
1228         drm_connector_cleanup(connector);
1229         kfree(intel_encoder);
1230 }
1231
1232 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1233         .dpms = intel_dp_dpms,
1234         .mode_fixup = intel_dp_mode_fixup,
1235         .prepare = intel_encoder_prepare,
1236         .mode_set = intel_dp_mode_set,
1237         .commit = intel_encoder_commit,
1238 };
1239
1240 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1241         .dpms = drm_helper_connector_dpms,
1242         .detect = intel_dp_detect,
1243         .fill_modes = drm_helper_probe_single_connector_modes,
1244         .destroy = intel_dp_destroy,
1245 };
1246
1247 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1248         .get_modes = intel_dp_get_modes,
1249         .mode_valid = intel_dp_mode_valid,
1250         .best_encoder = intel_best_encoder,
1251 };
1252
1253 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1254 {
1255         drm_encoder_cleanup(encoder);
1256 }
1257
1258 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1259         .destroy = intel_dp_enc_destroy,
1260 };
1261
1262 void
1263 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1264 {
1265         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1266
1267         if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1268                 intel_dp_check_link_status(intel_encoder);
1269 }
1270
1271 void
1272 intel_dp_init(struct drm_device *dev, int output_reg)
1273 {
1274         struct drm_i915_private *dev_priv = dev->dev_private;
1275         struct drm_connector *connector;
1276         struct intel_encoder *intel_encoder;
1277         struct intel_dp_priv *dp_priv;
1278         const char *name = NULL;
1279
1280         intel_encoder = kcalloc(sizeof(struct intel_encoder) +
1281                                sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1282         if (!intel_encoder)
1283                 return;
1284
1285         dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
1286
1287         connector = &intel_encoder->base;
1288         drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1289                            DRM_MODE_CONNECTOR_DisplayPort);
1290         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1291
1292         if (output_reg == DP_A)
1293                 intel_encoder->type = INTEL_OUTPUT_EDP;
1294         else
1295                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1296
1297         if (output_reg == DP_B || output_reg == PCH_DP_B)
1298                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1299         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1300                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1301         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1302                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1303
1304         if (IS_eDP(intel_encoder))
1305                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1306
1307         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1308         connector->interlace_allowed = true;
1309         connector->doublescan_allowed = 0;
1310
1311         dp_priv->intel_encoder = intel_encoder;
1312         dp_priv->output_reg = output_reg;
1313         dp_priv->has_audio = false;
1314         dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1315         intel_encoder->dev_priv = dp_priv;
1316
1317         drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1318                          DRM_MODE_ENCODER_TMDS);
1319         drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1320
1321         drm_mode_connector_attach_encoder(&intel_encoder->base,
1322                                           &intel_encoder->enc);
1323         drm_sysfs_connector_add(connector);
1324
1325         /* Set up the DDC bus. */
1326         switch (output_reg) {
1327                 case DP_A:
1328                         name = "DPDDC-A";
1329                         break;
1330                 case DP_B:
1331                 case PCH_DP_B:
1332                         dev_priv->hotplug_supported_mask |=
1333                                 HDMIB_HOTPLUG_INT_STATUS;
1334                         name = "DPDDC-B";
1335                         break;
1336                 case DP_C:
1337                 case PCH_DP_C:
1338                         dev_priv->hotplug_supported_mask |=
1339                                 HDMIC_HOTPLUG_INT_STATUS;
1340                         name = "DPDDC-C";
1341                         break;
1342                 case DP_D:
1343                 case PCH_DP_D:
1344                         dev_priv->hotplug_supported_mask |=
1345                                 HDMID_HOTPLUG_INT_STATUS;
1346                         name = "DPDDC-D";
1347                         break;
1348         }
1349
1350         intel_dp_i2c_init(intel_encoder, name);
1351
1352         intel_encoder->ddc_bus = &dp_priv->adapter;
1353         intel_encoder->hot_plug = intel_dp_hot_plug;
1354
1355         if (output_reg == DP_A) {
1356                 /* initialize panel mode from VBT if available for eDP */
1357                 if (dev_priv->lfp_lvds_vbt_mode) {
1358                         dev_priv->panel_fixed_mode =
1359                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1360                         if (dev_priv->panel_fixed_mode) {
1361                                 dev_priv->panel_fixed_mode->type |=
1362                                         DRM_MODE_TYPE_PREFERRED;
1363                         }
1364                 }
1365         }
1366
1367         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1368          * 0xd.  Failure to do so will result in spurious interrupts being
1369          * generated on the port when a cable is not attached.
1370          */
1371         if (IS_G4X(dev) && !IS_GM45(dev)) {
1372                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1373                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1374         }
1375 }