drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
  46 #define IS_PCH_eDP(dp_priv) ((dp_priv)->is_pch_edp)
  47
  48 struct intel_dp_priv {
  49         uint32_t output_reg;
  50         uint32_t DP;
  51         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  52         bool has_audio;
  53         int dpms_mode;
  54         uint8_t link_bw;
  55         uint8_t lane_count;
  56         uint8_t dpcd[4];
  57         struct intel_encoder *intel_encoder;
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61 };
  62
  63 static void
  64 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
  65                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
  66
  67 static void
  68 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
  69
  70 void
  71 intel_edp_link_config (struct intel_encoder *intel_encoder,
  72                 int *lane_num, int *link_bw)
  73 {
  74         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  75
  76         *lane_num = dp_priv->lane_count;
  77         if (dp_priv->link_bw == DP_LINK_BW_1_62)
  78                 *link_bw = 162000;
  79         else if (dp_priv->link_bw == DP_LINK_BW_2_7)
  80                 *link_bw = 270000;
  81 }
  82
  83 static int
  84 intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
  85 {
  86         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  87         int max_lane_count = 4;
  88
  89         if (dp_priv->dpcd[0] >= 0x11) {
  90                 max_lane_count = dp_priv->dpcd[2] & 0x1f;
  91                 switch (max_lane_count) {
  92                 case 1: case 2: case 4:
  93                         break;
  94                 default:
  95                         max_lane_count = 4;
  96                 }
  97         }
  98         return max_lane_count;
  99 }
 100
 101 static int
 102 intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
 103 {
 104         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 105         int max_link_bw = dp_priv->dpcd[1];
 106
 107         switch (max_link_bw) {
 108         case DP_LINK_BW_1_62:
 109         case DP_LINK_BW_2_7:
 110                 break;
 111         default:
 112                 max_link_bw = DP_LINK_BW_1_62;
 113                 break;
 114         }
 115         return max_link_bw;
 116 }
 117
 118 static int
 119 intel_dp_link_clock(uint8_t link_bw)
 120 {
 121         if (link_bw == DP_LINK_BW_2_7)
 122                 return 270000;
 123         else
 124                 return 162000;
 125 }
 126
 127 /* I think this is a fiction */
 128 static int
 129 intel_dp_link_required(struct drm_device *dev,
 130                        struct intel_encoder *intel_encoder, int pixel_clock)
 131 {
 132         struct drm_i915_private *dev_priv = dev->dev_private;
 133         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 134
 135         if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv))
 136                 return (pixel_clock * dev_priv->edp_bpp) / 8;
 137         else
 138                 return pixel_clock * 3;
 139 }
 140
 141 static int
 142 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 143 {
 144         return (max_link_clock * max_lanes * 8) / 10;
 145 }
 146
 147 static int
 148 intel_dp_mode_valid(struct drm_connector *connector,
 149                     struct drm_display_mode *mode)
 150 {
 151         struct drm_encoder *encoder = intel_attached_encoder(connector);
 152         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 153         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 154         struct drm_device *dev = connector->dev;
 155         struct drm_i915_private *dev_priv = dev->dev_private;
 156         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
 157         int max_lanes = intel_dp_max_lane_count(intel_encoder);
 158
 159         if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) &&
 160             dev_priv->panel_fixed_mode) {
 161                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 162                         return MODE_PANEL;
 163
 164                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 165                         return MODE_PANEL;
 166         }
 167
 168         /* only refuse the mode on non eDP since we have seen some wierd eDP panels
 169            which are outside spec tolerances but somehow work by magic */
 170         if (!IS_eDP(intel_encoder) &&
 171             (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
 172              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 173                 return MODE_CLOCK_HIGH;
 174
 175         if (mode->clock < 10000)
 176                 return MODE_CLOCK_LOW;
 177
 178         return MODE_OK;
 179 }
 180
 181 static uint32_t
 182 pack_aux(uint8_t *src, int src_bytes)
 183 {
 184         int     i;
 185         uint32_t v = 0;
 186
 187         if (src_bytes > 4)
 188                 src_bytes = 4;
 189         for (i = 0; i < src_bytes; i++)
 190                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 191         return v;
 192 }
 193
 194 static void
 195 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 196 {
 197         int i;
 198         if (dst_bytes > 4)
 199                 dst_bytes = 4;
 200         for (i = 0; i < dst_bytes; i++)
 201                 dst[i] = src >> ((3-i) * 8);
 202 }
 203
 204 /* hrawclock is 1/4 the FSB frequency */
 205 static int
 206 intel_hrawclk(struct drm_device *dev)
 207 {
 208         struct drm_i915_private *dev_priv = dev->dev_private;
 209         uint32_t clkcfg;
 210
 211         clkcfg = I915_READ(CLKCFG);
 212         switch (clkcfg & CLKCFG_FSB_MASK) {
 213         case CLKCFG_FSB_400:
 214                 return 100;
 215         case CLKCFG_FSB_533:
 216                 return 133;
 217         case CLKCFG_FSB_667:
 218                 return 166;
 219         case CLKCFG_FSB_800:
 220                 return 200;
 221         case CLKCFG_FSB_1067:
 222                 return 266;
 223         case CLKCFG_FSB_1333:
 224                 return 333;
 225         /* these two are just a guess; one of them might be right */
 226         case CLKCFG_FSB_1600:
 227         case CLKCFG_FSB_1600_ALT:
 228                 return 400;
 229         default:
 230                 return 133;
 231         }
 232 }
 233
 234 static int
 235 intel_dp_aux_ch(struct intel_encoder *intel_encoder,
 236                 uint8_t *send, int send_bytes,
 237                 uint8_t *recv, int recv_size)
 238 {
 239         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 240         uint32_t output_reg = dp_priv->output_reg;
 241         struct drm_device *dev = intel_encoder->enc.dev;
 242         struct drm_i915_private *dev_priv = dev->dev_private;
 243         uint32_t ch_ctl = output_reg + 0x10;
 244         uint32_t ch_data = ch_ctl + 4;
 245         int i;
 246         int recv_bytes;
 247         uint32_t ctl;
 248         uint32_t status;
 249         uint32_t aux_clock_divider;
 250         int try, precharge;
 251
 252         /* The clock divider is based off the hrawclk,
 253          * and would like to run at 2MHz. So, take the
 254          * hrawclk value and divide by 2 and use that
 255          */
 256         if (IS_eDP(intel_encoder)) {
 257                 if (IS_GEN6(dev))
 258                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 259                 else
 260                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 261         } else if (HAS_PCH_SPLIT(dev))
 262                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 263         else
 264                 aux_clock_divider = intel_hrawclk(dev) / 2;
 265
 266         if (IS_GEN6(dev))
 267                 precharge = 3;
 268         else
 269                 precharge = 5;
 270
 271         /* Must try at least 3 times according to DP spec */
 272         for (try = 0; try < 5; try++) {
 273                 /* Load the send data into the aux channel data registers */
 274                 for (i = 0; i < send_bytes; i += 4) {
 275                         uint32_t    d = pack_aux(send + i, send_bytes - i);
 276
 277                         I915_WRITE(ch_data + i, d);
 278                 }
 279
 280                 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
 281                        DP_AUX_CH_CTL_TIME_OUT_400us |
 282                        (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 283                        (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 284                        (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 285                        DP_AUX_CH_CTL_DONE |
 286                        DP_AUX_CH_CTL_TIME_OUT_ERROR |
 287                        DP_AUX_CH_CTL_RECEIVE_ERROR);
 288
 289                 /* Send the command and wait for it to complete */
 290                 I915_WRITE(ch_ctl, ctl);
 291                 (void) I915_READ(ch_ctl);
 292                 for (;;) {
 293                         udelay(100);
 294                         status = I915_READ(ch_ctl);
 295                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 296                                 break;
 297                 }
 298
 299                 /* Clear done status and any errors */
 300                 I915_WRITE(ch_ctl, (status |
 301                                 DP_AUX_CH_CTL_DONE |
 302                                 DP_AUX_CH_CTL_TIME_OUT_ERROR |
 303                                 DP_AUX_CH_CTL_RECEIVE_ERROR));
 304                 (void) I915_READ(ch_ctl);
 305                 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
 306                         break;
 307         }
 308
 309         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 310                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 311                 return -EBUSY;
 312         }
 313
 314         /* Check for timeout or receive error.
 315          * Timeouts occur when the sink is not connected
 316          */
 317         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 318                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 319                 return -EIO;
 320         }
 321
 322         /* Timeouts occur when the device isn't connected, so they're
 323          * "normal" -- don't fill the kernel log with these */
 324         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 325                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 326                 return -ETIMEDOUT;
 327         }
 328
 329         /* Unload any bytes sent back from the other side */
 330         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 331                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 332
 333         if (recv_bytes > recv_size)
 334                 recv_bytes = recv_size;
 335
 336         for (i = 0; i < recv_bytes; i += 4) {
 337                 uint32_t    d = I915_READ(ch_data + i);
 338
 339                 unpack_aux(d, recv + i, recv_bytes - i);
 340         }
 341
 342         return recv_bytes;
 343 }
 344
 345 /* Write data to the aux channel in native mode */
 346 static int
 347 intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
 348                           uint16_t address, uint8_t *send, int send_bytes)
 349 {
 350         int ret;
 351         uint8_t msg[20];
 352         int msg_bytes;
 353         uint8_t ack;
 354
 355         if (send_bytes > 16)
 356                 return -1;
 357         msg[0] = AUX_NATIVE_WRITE << 4;
 358         msg[1] = address >> 8;
 359         msg[2] = address & 0xff;
 360         msg[3] = send_bytes - 1;
 361         memcpy(&msg[4], send, send_bytes);
 362         msg_bytes = send_bytes + 4;
 363         for (;;) {
 364                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
 365                 if (ret < 0)
 366                         return ret;
 367                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 368                         break;
 369                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 370                         udelay(100);
 371                 else
 372                         return -EIO;
 373         }
 374         return send_bytes;
 375 }
 376
 377 /* Write a single byte to the aux channel in native mode */
 378 static int
 379 intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
 380                             uint16_t address, uint8_t byte)
 381 {
 382         return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
 383 }
 384
 385 /* read bytes from a native aux channel */
 386 static int
 387 intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
 388                          uint16_t address, uint8_t *recv, int recv_bytes)
 389 {
 390         uint8_t msg[4];
 391         int msg_bytes;
 392         uint8_t reply[20];
 393         int reply_bytes;
 394         uint8_t ack;
 395         int ret;
 396
 397         msg[0] = AUX_NATIVE_READ << 4;
 398         msg[1] = address >> 8;
 399         msg[2] = address & 0xff;
 400         msg[3] = recv_bytes - 1;
 401
 402         msg_bytes = 4;
 403         reply_bytes = recv_bytes + 1;
 404
 405         for (;;) {
 406                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
 407                                       reply, reply_bytes);
 408                 if (ret == 0)
 409                         return -EPROTO;
 410                 if (ret < 0)
 411                         return ret;
 412                 ack = reply[0];
 413                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 414                         memcpy(recv, reply + 1, ret - 1);
 415                         return ret - 1;
 416                 }
 417                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 418                         udelay(100);
 419                 else
 420                         return -EIO;
 421         }
 422 }
 423
 424 static int
 425 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 426                     uint8_t write_byte, uint8_t *read_byte)
 427 {
 428         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 429         struct intel_dp_priv *dp_priv = container_of(adapter,
 430                                                      struct intel_dp_priv,
 431                                                      adapter);
 432         struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
 433         uint16_t address = algo_data->address;
 434         uint8_t msg[5];
 435         uint8_t reply[2];
 436         int msg_bytes;
 437         int reply_bytes;
 438         int ret;
 439
 440         /* Set up the command byte */
 441         if (mode & MODE_I2C_READ)
 442                 msg[0] = AUX_I2C_READ << 4;
 443         else
 444                 msg[0] = AUX_I2C_WRITE << 4;
 445
 446         if (!(mode & MODE_I2C_STOP))
 447                 msg[0] |= AUX_I2C_MOT << 4;
 448
 449         msg[1] = address >> 8;
 450         msg[2] = address;
 451
 452         switch (mode) {
 453         case MODE_I2C_WRITE:
 454                 msg[3] = 0;
 455                 msg[4] = write_byte;
 456                 msg_bytes = 5;
 457                 reply_bytes = 1;
 458                 break;
 459         case MODE_I2C_READ:
 460                 msg[3] = 0;
 461                 msg_bytes = 4;
 462                 reply_bytes = 2;
 463                 break;
 464         default:
 465                 msg_bytes = 3;
 466                 reply_bytes = 1;
 467                 break;
 468         }
 469
 470         for (;;) {
 471           ret = intel_dp_aux_ch(intel_encoder,
 472                                 msg, msg_bytes,
 473                                 reply, reply_bytes);
 474                 if (ret < 0) {
 475                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 476                         return ret;
 477                 }
 478                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 479                 case AUX_I2C_REPLY_ACK:
 480                         if (mode == MODE_I2C_READ) {
 481                                 *read_byte = reply[1];
 482                         }
 483                         return reply_bytes - 1;
 484                 case AUX_I2C_REPLY_NACK:
 485                         DRM_DEBUG_KMS("aux_ch nack\n");
 486                         return -EREMOTEIO;
 487                 case AUX_I2C_REPLY_DEFER:
 488                         DRM_DEBUG_KMS("aux_ch defer\n");
 489                         udelay(100);
 490                         break;
 491                 default:
 492                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 493                         return -EREMOTEIO;
 494                 }
 495         }
 496 }
 497
 498 static int
 499 intel_dp_i2c_init(struct intel_encoder *intel_encoder,
 500                   struct intel_connector *intel_connector, const char *name)
 501 {
 502         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 503
 504         DRM_DEBUG_KMS("i2c_init %s\n", name);
 505         dp_priv->algo.running = false;
 506         dp_priv->algo.address = 0;
 507         dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
 508
 509         memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
 510         dp_priv->adapter.owner = THIS_MODULE;
 511         dp_priv->adapter.class = I2C_CLASS_DDC;
 512         strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
 513         dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
 514         dp_priv->adapter.algo_data = &dp_priv->algo;
 515         dp_priv->adapter.dev.parent = &intel_connector->base.kdev;
 516
 517         return i2c_dp_aux_add_bus(&dp_priv->adapter);
 518 }
 519
 520 static bool
 521 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 522                     struct drm_display_mode *adjusted_mode)
 523 {
 524         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 525         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 526         struct drm_device *dev = encoder->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         int lane_count, clock;
 529         int max_lane_count = intel_dp_max_lane_count(intel_encoder);
 530         int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
 531         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 532
 533         if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) &&
 534             dev_priv->panel_fixed_mode) {
 535                 struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
 536
 537                 adjusted_mode->hdisplay = fixed_mode->hdisplay;
 538                 adjusted_mode->hsync_start = fixed_mode->hsync_start;
 539                 adjusted_mode->hsync_end = fixed_mode->hsync_end;
 540                 adjusted_mode->htotal = fixed_mode->htotal;
 541
 542                 adjusted_mode->vdisplay = fixed_mode->vdisplay;
 543                 adjusted_mode->vsync_start = fixed_mode->vsync_start;
 544                 adjusted_mode->vsync_end = fixed_mode->vsync_end;
 545                 adjusted_mode->vtotal = fixed_mode->vtotal;
 546
 547                 adjusted_mode->clock = fixed_mode->clock;
 548                 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
 549
 550                 /*
 551                  * the mode->clock is used to calculate the Data&Link M/N
 552                  * of the pipe. For the eDP the fixed clock should be used.
 553                  */
 554                 mode->clock = dev_priv->panel_fixed_mode->clock;
 555         }
 556
 557         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 558                 for (clock = 0; clock <= max_clock; clock++) {
 559                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 560
 561                         if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
 562                                         <= link_avail) {
 563                                 dp_priv->link_bw = bws[clock];
 564                                 dp_priv->lane_count = lane_count;
 565                                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 566                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 567                                                 "count %d clock %d\n",
 568                                        dp_priv->link_bw, dp_priv->lane_count,
 569                                        adjusted_mode->clock);
 570                                 return true;
 571                         }
 572                 }
 573         }
 574
 575         if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
 576                 /* okay we failed just pick the highest */
 577                 dp_priv->lane_count = max_lane_count;
 578                 dp_priv->link_bw = bws[max_clock];
 579                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 580                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 581                               "count %d clock %d\n",
 582                               dp_priv->link_bw, dp_priv->lane_count,
 583                               adjusted_mode->clock);
 584                 return true;
 585         }
 586         return false;
 587 }
 588
 589 struct intel_dp_m_n {
 590         uint32_t        tu;
 591         uint32_t        gmch_m;
 592         uint32_t        gmch_n;
 593         uint32_t        link_m;
 594         uint32_t        link_n;
 595 };
 596
 597 static void
 598 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 599 {
 600         while (*num > 0xffffff || *den > 0xffffff) {
 601                 *num >>= 1;
 602                 *den >>= 1;
 603         }
 604 }
 605
 606 static void
 607 intel_dp_compute_m_n(int bpp,
 608                      int nlanes,
 609                      int pixel_clock,
 610                      int link_clock,
 611                      struct intel_dp_m_n *m_n)
 612 {
 613         m_n->tu = 64;
 614         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 615         m_n->gmch_n = link_clock * nlanes;
 616         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 617         m_n->link_m = pixel_clock;
 618         m_n->link_n = link_clock;
 619         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 620 }
 621
 622 bool intel_pch_has_edp(struct drm_crtc *crtc)
 623 {
 624         struct drm_device *dev = crtc->dev;
 625         struct drm_mode_config *mode_config = &dev->mode_config;
 626         struct drm_encoder *encoder;
 627
 628         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 629                 struct intel_encoder *intel_encoder;
 630                 struct intel_dp_priv *dp_priv;
 631
 632                 if (!encoder || encoder->crtc != crtc)
 633                         continue;
 634
 635                 intel_encoder = enc_to_intel_encoder(encoder);
 636                 dp_priv = intel_encoder->dev_priv;
 637
 638                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT)
 639                         return dp_priv->is_pch_edp;
 640         }
 641         return false;
 642 }
 643
 644 void
 645 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 646                  struct drm_display_mode *adjusted_mode)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         struct drm_mode_config *mode_config = &dev->mode_config;
 650         struct drm_encoder *encoder;
 651         struct drm_i915_private *dev_priv = dev->dev_private;
 652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 653         int lane_count = 4, bpp = 24;
 654         struct intel_dp_m_n m_n;
 655
 656         /*
 657          * Find the lane count in the intel_encoder private
 658          */
 659         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 660                 struct intel_encoder *intel_encoder;
 661                 struct intel_dp_priv *dp_priv;
 662
 663                 if (encoder->crtc != crtc)
 664                         continue;
 665
 666                 intel_encoder = enc_to_intel_encoder(encoder);
 667                 dp_priv = intel_encoder->dev_priv;
 668
 669                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
 670                         lane_count = dp_priv->lane_count;
 671                         if (IS_PCH_eDP(dp_priv))
 672                                 bpp = dev_priv->edp_bpp;
 673                         break;
 674                 }
 675         }
 676
 677         /*
 678          * Compute the GMCH and Link ratios. The '3' here is
 679          * the number of bytes_per_pixel post-LUT, which we always
 680          * set up for 8-bits of R/G/B, or 3 bytes total.
 681          */
 682         intel_dp_compute_m_n(bpp, lane_count,
 683                              mode->clock, adjusted_mode->clock, &m_n);
 684
 685         if (HAS_PCH_SPLIT(dev)) {
 686                 if (intel_crtc->pipe == 0) {
 687                         I915_WRITE(TRANSA_DATA_M1,
 688                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 689                                    m_n.gmch_m);
 690                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 691                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 692                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 693                 } else {
 694                         I915_WRITE(TRANSB_DATA_M1,
 695                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 696                                    m_n.gmch_m);
 697                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 698                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 699                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 700                 }
 701         } else {
 702                 if (intel_crtc->pipe == 0) {
 703                         I915_WRITE(PIPEA_GMCH_DATA_M,
 704                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 705                                    m_n.gmch_m);
 706                         I915_WRITE(PIPEA_GMCH_DATA_N,
 707                                    m_n.gmch_n);
 708                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 709                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 710                 } else {
 711                         I915_WRITE(PIPEB_GMCH_DATA_M,
 712                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 713                                    m_n.gmch_m);
 714                         I915_WRITE(PIPEB_GMCH_DATA_N,
 715                                         m_n.gmch_n);
 716                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 717                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 718                 }
 719         }
 720 }
 721
 722 static void
 723 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 724                   struct drm_display_mode *adjusted_mode)
 725 {
 726         struct drm_device *dev = encoder->dev;
 727         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 728         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 729         struct drm_crtc *crtc = intel_encoder->enc.crtc;
 730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 731
 732         dp_priv->DP = (DP_VOLTAGE_0_4 |
 733                        DP_PRE_EMPHASIS_0);
 734
 735         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 736                 dp_priv->DP |= DP_SYNC_HS_HIGH;
 737         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 738                 dp_priv->DP |= DP_SYNC_VS_HIGH;
 739
 740         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
 741                 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
 742         else
 743                 dp_priv->DP |= DP_LINK_TRAIN_OFF;
 744
 745         switch (dp_priv->lane_count) {
 746         case 1:
 747                 dp_priv->DP |= DP_PORT_WIDTH_1;
 748                 break;
 749         case 2:
 750                 dp_priv->DP |= DP_PORT_WIDTH_2;
 751                 break;
 752         case 4:
 753                 dp_priv->DP |= DP_PORT_WIDTH_4;
 754                 break;
 755         }
 756         if (dp_priv->has_audio)
 757                 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
 758
 759         memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 760         dp_priv->link_configuration[0] = dp_priv->link_bw;
 761         dp_priv->link_configuration[1] = dp_priv->lane_count;
 762
 763         /*
 764          * Check for DPCD version > 1.1 and enhanced framing support
 765          */
 766         if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
 767                 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 768                 dp_priv->DP |= DP_ENHANCED_FRAMING;
 769         }
 770
 771         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 772         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 773                 dp_priv->DP |= DP_PIPEB_SELECT;
 774
 775         if (IS_eDP(intel_encoder)) {
 776                 /* don't miss out required setting for eDP */
 777                 dp_priv->DP |= DP_PLL_ENABLE;
 778                 if (adjusted_mode->clock < 200000)
 779                         dp_priv->DP |= DP_PLL_FREQ_160MHZ;
 780                 else
 781                         dp_priv->DP |= DP_PLL_FREQ_270MHZ;
 782         }
 783 }
 784
 785 static void ironlake_edp_panel_on (struct drm_device *dev)
 786 {
 787         struct drm_i915_private *dev_priv = dev->dev_private;
 788         unsigned long timeout = jiffies + msecs_to_jiffies(5000);
 789         u32 pp, pp_status;
 790
 791         pp_status = I915_READ(PCH_PP_STATUS);
 792         if (pp_status & PP_ON)
 793                 return;
 794
 795         pp = I915_READ(PCH_PP_CONTROL);
 796         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 797         I915_WRITE(PCH_PP_CONTROL, pp);
 798         do {
 799                 pp_status = I915_READ(PCH_PP_STATUS);
 800         } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
 801
 802         if (time_after(jiffies, timeout))
 803                 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
 804
 805         pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
 806         I915_WRITE(PCH_PP_CONTROL, pp);
 807 }
 808
 809 static void ironlake_edp_panel_off (struct drm_device *dev)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         unsigned long timeout = jiffies + msecs_to_jiffies(5000);
 813         u32 pp, pp_status;
 814
 815         pp = I915_READ(PCH_PP_CONTROL);
 816         pp &= ~POWER_TARGET_ON;
 817         I915_WRITE(PCH_PP_CONTROL, pp);
 818         do {
 819                 pp_status = I915_READ(PCH_PP_STATUS);
 820         } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
 821
 822         if (time_after(jiffies, timeout))
 823                 DRM_DEBUG_KMS("panel off wait timed out\n");
 824
 825         /* Make sure VDD is enabled so DP AUX will work */
 826         pp |= EDP_FORCE_VDD;
 827         I915_WRITE(PCH_PP_CONTROL, pp);
 828 }
 829
 830 static void ironlake_edp_backlight_on (struct drm_device *dev)
 831 {
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         u32 pp;
 834
 835         DRM_DEBUG_KMS("\n");
 836         pp = I915_READ(PCH_PP_CONTROL);
 837         pp |= EDP_BLC_ENABLE;
 838         I915_WRITE(PCH_PP_CONTROL, pp);
 839 }
 840
 841 static void ironlake_edp_backlight_off (struct drm_device *dev)
 842 {
 843         struct drm_i915_private *dev_priv = dev->dev_private;
 844         u32 pp;
 845
 846         DRM_DEBUG_KMS("\n");
 847         pp = I915_READ(PCH_PP_CONTROL);
 848         pp &= ~EDP_BLC_ENABLE;
 849         I915_WRITE(PCH_PP_CONTROL, pp);
 850 }
 851
 852 static void
 853 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 854 {
 855         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 856         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 857         struct drm_device *dev = encoder->dev;
 858         struct drm_i915_private *dev_priv = dev->dev_private;
 859         uint32_t dp_reg = I915_READ(dp_priv->output_reg);
 860
 861         if (mode != DRM_MODE_DPMS_ON) {
 862                 if (dp_reg & DP_PORT_EN) {
 863                         intel_dp_link_down(intel_encoder, dp_priv->DP);
 864                         if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
 865                                 ironlake_edp_backlight_off(dev);
 866                                 ironlake_edp_panel_off(dev);
 867                         }
 868                 }
 869         } else {
 870                 if (!(dp_reg & DP_PORT_EN)) {
 871                         intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
 872                         if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
 873                                 ironlake_edp_panel_on(dev);
 874                                 ironlake_edp_backlight_on(dev);
 875                         }
 876                 }
 877         }
 878         dp_priv->dpms_mode = mode;
 879 }
 880
 881 /*
 882  * Fetch AUX CH registers 0x202 - 0x207 which contain
 883  * link status information
 884  */
 885 static bool
 886 intel_dp_get_link_status(struct intel_encoder *intel_encoder,
 887                          uint8_t link_status[DP_LINK_STATUS_SIZE])
 888 {
 889         int ret;
 890
 891         ret = intel_dp_aux_native_read(intel_encoder,
 892                                        DP_LANE0_1_STATUS,
 893                                        link_status, DP_LINK_STATUS_SIZE);
 894         if (ret != DP_LINK_STATUS_SIZE)
 895                 return false;
 896         return true;
 897 }
 898
 899 static uint8_t
 900 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 901                      int r)
 902 {
 903         return link_status[r - DP_LANE0_1_STATUS];
 904 }
 905
 906 static uint8_t
 907 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 908                                  int lane)
 909 {
 910         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 911         int         s = ((lane & 1) ?
 912                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 913                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 914         uint8_t l = intel_dp_link_status(link_status, i);
 915
 916         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 917 }
 918
 919 static uint8_t
 920 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 921                                       int lane)
 922 {
 923         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 924         int         s = ((lane & 1) ?
 925                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 926                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 927         uint8_t l = intel_dp_link_status(link_status, i);
 928
 929         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 930 }
 931
 932
 933 #if 0
 934 static char     *voltage_names[] = {
 935         "0.4V", "0.6V", "0.8V", "1.2V"
 936 };
 937 static char     *pre_emph_names[] = {
 938         "0dB", "3.5dB", "6dB", "9.5dB"
 939 };
 940 static char     *link_train_names[] = {
 941         "pattern 1", "pattern 2", "idle", "off"
 942 };
 943 #endif
 944
 945 /*
 946  * These are source-specific values; current Intel hardware supports
 947  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 948  */
 949 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
 950
 951 static uint8_t
 952 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 953 {
 954         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 955         case DP_TRAIN_VOLTAGE_SWING_400:
 956                 return DP_TRAIN_PRE_EMPHASIS_6;
 957         case DP_TRAIN_VOLTAGE_SWING_600:
 958                 return DP_TRAIN_PRE_EMPHASIS_6;
 959         case DP_TRAIN_VOLTAGE_SWING_800:
 960                 return DP_TRAIN_PRE_EMPHASIS_3_5;
 961         case DP_TRAIN_VOLTAGE_SWING_1200:
 962         default:
 963                 return DP_TRAIN_PRE_EMPHASIS_0;
 964         }
 965 }
 966
 967 static void
 968 intel_get_adjust_train(struct intel_encoder *intel_encoder,
 969                        uint8_t link_status[DP_LINK_STATUS_SIZE],
 970                        int lane_count,
 971                        uint8_t train_set[4])
 972 {
 973         uint8_t v = 0;
 974         uint8_t p = 0;
 975         int lane;
 976
 977         for (lane = 0; lane < lane_count; lane++) {
 978                 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
 979                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
 980
 981                 if (this_v > v)
 982                         v = this_v;
 983                 if (this_p > p)
 984                         p = this_p;
 985         }
 986
 987         if (v >= I830_DP_VOLTAGE_MAX)
 988                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 989
 990         if (p >= intel_dp_pre_emphasis_max(v))
 991                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 992
 993         for (lane = 0; lane < 4; lane++)
 994                 train_set[lane] = v | p;
 995 }
 996
 997 static uint32_t
 998 intel_dp_signal_levels(uint8_t train_set, int lane_count)
 999 {
1000         uint32_t        signal_levels = 0;
1001
1002         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1003         case DP_TRAIN_VOLTAGE_SWING_400:
1004         default:
1005                 signal_levels |= DP_VOLTAGE_0_4;
1006                 break;
1007         case DP_TRAIN_VOLTAGE_SWING_600:
1008                 signal_levels |= DP_VOLTAGE_0_6;
1009                 break;
1010         case DP_TRAIN_VOLTAGE_SWING_800:
1011                 signal_levels |= DP_VOLTAGE_0_8;
1012                 break;
1013         case DP_TRAIN_VOLTAGE_SWING_1200:
1014                 signal_levels |= DP_VOLTAGE_1_2;
1015                 break;
1016         }
1017         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1018         case DP_TRAIN_PRE_EMPHASIS_0:
1019         default:
1020                 signal_levels |= DP_PRE_EMPHASIS_0;
1021                 break;
1022         case DP_TRAIN_PRE_EMPHASIS_3_5:
1023                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1024                 break;
1025         case DP_TRAIN_PRE_EMPHASIS_6:
1026                 signal_levels |= DP_PRE_EMPHASIS_6;
1027                 break;
1028         case DP_TRAIN_PRE_EMPHASIS_9_5:
1029                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1030                 break;
1031         }
1032         return signal_levels;
1033 }
1034
1035 /* Gen6's DP voltage swing and pre-emphasis control */
1036 static uint32_t
1037 intel_gen6_edp_signal_levels(uint8_t train_set)
1038 {
1039         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1040         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1041                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1042         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1043                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1044         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1045                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1046         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1047                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1048         default:
1049                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1050                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1051         }
1052 }
1053
1054 static uint8_t
1055 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1056                       int lane)
1057 {
1058         int i = DP_LANE0_1_STATUS + (lane >> 1);
1059         int s = (lane & 1) * 4;
1060         uint8_t l = intel_dp_link_status(link_status, i);
1061
1062         return (l >> s) & 0xf;
1063 }
1064
1065 /* Check for clock recovery is done on all channels */
1066 static bool
1067 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1068 {
1069         int lane;
1070         uint8_t lane_status;
1071
1072         for (lane = 0; lane < lane_count; lane++) {
1073                 lane_status = intel_get_lane_status(link_status, lane);
1074                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1075                         return false;
1076         }
1077         return true;
1078 }
1079
1080 /* Check to see if channel eq is done on all channels */
1081 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1082                          DP_LANE_CHANNEL_EQ_DONE|\
1083                          DP_LANE_SYMBOL_LOCKED)
1084 static bool
1085 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1086 {
1087         uint8_t lane_align;
1088         uint8_t lane_status;
1089         int lane;
1090
1091         lane_align = intel_dp_link_status(link_status,
1092                                           DP_LANE_ALIGN_STATUS_UPDATED);
1093         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1094                 return false;
1095         for (lane = 0; lane < lane_count; lane++) {
1096                 lane_status = intel_get_lane_status(link_status, lane);
1097                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1098                         return false;
1099         }
1100         return true;
1101 }
1102
1103 static bool
1104 intel_dp_set_link_train(struct intel_encoder *intel_encoder,
1105                         uint32_t dp_reg_value,
1106                         uint8_t dp_train_pat,
1107                         uint8_t train_set[4],
1108                         bool first)
1109 {
1110         struct drm_device *dev = intel_encoder->enc.dev;
1111         struct drm_i915_private *dev_priv = dev->dev_private;
1112         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1113         int ret;
1114
1115         I915_WRITE(dp_priv->output_reg, dp_reg_value);
1116         POSTING_READ(dp_priv->output_reg);
1117         if (first)
1118                 intel_wait_for_vblank(dev);
1119
1120         intel_dp_aux_native_write_1(intel_encoder,
1121                                     DP_TRAINING_PATTERN_SET,
1122                                     dp_train_pat);
1123
1124         ret = intel_dp_aux_native_write(intel_encoder,
1125                                         DP_TRAINING_LANE0_SET, train_set, 4);
1126         if (ret != 4)
1127                 return false;
1128
1129         return true;
1130 }
1131
1132 static void
1133 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1134                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
1135 {
1136         struct drm_device *dev = intel_encoder->enc.dev;
1137         struct drm_i915_private *dev_priv = dev->dev_private;
1138         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1139         uint8_t train_set[4];
1140         uint8_t link_status[DP_LINK_STATUS_SIZE];
1141         int i;
1142         uint8_t voltage;
1143         bool clock_recovery = false;
1144         bool channel_eq = false;
1145         bool first = true;
1146         int tries;
1147         u32 reg;
1148
1149         /* Write the link configuration data */
1150         intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET,
1151                                   link_configuration, DP_LINK_CONFIGURATION_SIZE);
1152
1153         DP |= DP_PORT_EN;
1154         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1155                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1156         else
1157                 DP &= ~DP_LINK_TRAIN_MASK;
1158         memset(train_set, 0, 4);
1159         voltage = 0xff;
1160         tries = 0;
1161         clock_recovery = false;
1162         for (;;) {
1163                 /* Use train_set[0] to set the voltage and pre emphasis values */
1164                 uint32_t    signal_levels;
1165                 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1166                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1167                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1168                 } else {
1169                         signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1170                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1171                 }
1172
1173                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1174                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1175                 else
1176                         reg = DP | DP_LINK_TRAIN_PAT_1;
1177
1178                 if (!intel_dp_set_link_train(intel_encoder, reg,
1179                                              DP_TRAINING_PATTERN_1, train_set, first))
1180                         break;
1181                 first = false;
1182                 /* Set training pattern 1 */
1183
1184                 udelay(100);
1185                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1186                         break;
1187
1188                 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1189                         clock_recovery = true;
1190                         break;
1191                 }
1192
1193                 /* Check to see if we've tried the max voltage */
1194                 for (i = 0; i < dp_priv->lane_count; i++)
1195                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1196                                 break;
1197                 if (i == dp_priv->lane_count)
1198                         break;
1199
1200                 /* Check to see if we've tried the same voltage 5 times */
1201                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1202                         ++tries;
1203                         if (tries == 5)
1204                                 break;
1205                 } else
1206                         tries = 0;
1207                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1208
1209                 /* Compute new train_set as requested by target */
1210                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1211         }
1212
1213         /* channel equalization */
1214         tries = 0;
1215         channel_eq = false;
1216         for (;;) {
1217                 /* Use train_set[0] to set the voltage and pre emphasis values */
1218                 uint32_t    signal_levels;
1219
1220                 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1221                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1222                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1223                 } else {
1224                         signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1225                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1226                 }
1227
1228                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1229                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1230                 else
1231                         reg = DP | DP_LINK_TRAIN_PAT_2;
1232
1233                 /* channel eq pattern */
1234                 if (!intel_dp_set_link_train(intel_encoder, reg,
1235                                              DP_TRAINING_PATTERN_2, train_set,
1236                                              false))
1237                         break;
1238
1239                 udelay(400);
1240                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1241                         break;
1242
1243                 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1244                         channel_eq = true;
1245                         break;
1246                 }
1247
1248                 /* Try 5 times */
1249                 if (tries > 5)
1250                         break;
1251
1252                 /* Compute new train_set as requested by target */
1253                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1254                 ++tries;
1255         }
1256
1257         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1258                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1259         else
1260                 reg = DP | DP_LINK_TRAIN_OFF;
1261
1262         I915_WRITE(dp_priv->output_reg, reg);
1263         POSTING_READ(dp_priv->output_reg);
1264         intel_dp_aux_native_write_1(intel_encoder,
1265                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1266 }
1267
1268 static void
1269 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1270 {
1271         struct drm_device *dev = intel_encoder->enc.dev;
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1274
1275         DRM_DEBUG_KMS("\n");
1276
1277         if (IS_eDP(intel_encoder)) {
1278                 DP &= ~DP_PLL_ENABLE;
1279                 I915_WRITE(dp_priv->output_reg, DP);
1280                 POSTING_READ(dp_priv->output_reg);
1281                 udelay(100);
1282         }
1283
1284         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
1285                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1286                 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1287                 POSTING_READ(dp_priv->output_reg);
1288         } else {
1289                 DP &= ~DP_LINK_TRAIN_MASK;
1290                 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1291                 POSTING_READ(dp_priv->output_reg);
1292         }
1293
1294         udelay(17000);
1295
1296         if (IS_eDP(intel_encoder))
1297                 DP |= DP_LINK_TRAIN_OFF;
1298         I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1299         POSTING_READ(dp_priv->output_reg);
1300 }
1301
1302 /*
1303  * According to DP spec
1304  * 5.1.2:
1305  *  1. Read DPCD
1306  *  2. Configure link according to Receiver Capabilities
1307  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1308  *  4. Check link status on receipt of hot-plug interrupt
1309  */
1310
1311 static void
1312 intel_dp_check_link_status(struct intel_encoder *intel_encoder)
1313 {
1314         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1315         uint8_t link_status[DP_LINK_STATUS_SIZE];
1316
1317         if (!intel_encoder->enc.crtc)
1318                 return;
1319
1320         if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1321                 intel_dp_link_down(intel_encoder, dp_priv->DP);
1322                 return;
1323         }
1324
1325         if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1326                 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
1327 }
1328
1329 static enum drm_connector_status
1330 ironlake_dp_detect(struct drm_connector *connector)
1331 {
1332         struct drm_encoder *encoder = intel_attached_encoder(connector);
1333         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1334         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1335         enum drm_connector_status status;
1336
1337         status = connector_status_disconnected;
1338         if (intel_dp_aux_native_read(intel_encoder,
1339                                      0x000, dp_priv->dpcd,
1340                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1341         {
1342                 if (dp_priv->dpcd[0] != 0)
1343                         status = connector_status_connected;
1344         }
1345         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0],
1346                       dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]);
1347         return status;
1348 }
1349
1350 /**
1351  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1352  *
1353  * \return true if DP port is connected.
1354  * \return false if DP port is disconnected.
1355  */
1356 static enum drm_connector_status
1357 intel_dp_detect(struct drm_connector *connector)
1358 {
1359         struct drm_encoder *encoder = intel_attached_encoder(connector);
1360         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1361         struct drm_device *dev = intel_encoder->enc.dev;
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1364         uint32_t temp, bit;
1365         enum drm_connector_status status;
1366
1367         dp_priv->has_audio = false;
1368
1369         if (HAS_PCH_SPLIT(dev))
1370                 return ironlake_dp_detect(connector);
1371
1372         switch (dp_priv->output_reg) {
1373         case DP_B:
1374                 bit = DPB_HOTPLUG_INT_STATUS;
1375                 break;
1376         case DP_C:
1377                 bit = DPC_HOTPLUG_INT_STATUS;
1378                 break;
1379         case DP_D:
1380                 bit = DPD_HOTPLUG_INT_STATUS;
1381                 break;
1382         default:
1383                 return connector_status_unknown;
1384         }
1385
1386         temp = I915_READ(PORT_HOTPLUG_STAT);
1387
1388         if ((temp & bit) == 0)
1389                 return connector_status_disconnected;
1390
1391         status = connector_status_disconnected;
1392         if (intel_dp_aux_native_read(intel_encoder,
1393                                      0x000, dp_priv->dpcd,
1394                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1395         {
1396                 if (dp_priv->dpcd[0] != 0)
1397                         status = connector_status_connected;
1398         }
1399         return status;
1400 }
1401
1402 static int intel_dp_get_modes(struct drm_connector *connector)
1403 {
1404         struct drm_encoder *encoder = intel_attached_encoder(connector);
1405         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1406         struct drm_device *dev = intel_encoder->enc.dev;
1407         struct drm_i915_private *dev_priv = dev->dev_private;
1408         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1409         int ret;
1410
1411         /* We should parse the EDID data and find out if it has an audio sink
1412          */
1413
1414         ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
1415         if (ret) {
1416                 if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) &&
1417                     !dev_priv->panel_fixed_mode) {
1418                         struct drm_display_mode *newmode;
1419                         list_for_each_entry(newmode, &connector->probed_modes,
1420                                             head) {
1421                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1422                                         dev_priv->panel_fixed_mode =
1423                                                 drm_mode_duplicate(dev, newmode);
1424                                         break;
1425                                 }
1426                         }
1427                 }
1428
1429                 return ret;
1430         }
1431
1432         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1433         if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
1434                 if (dev_priv->panel_fixed_mode != NULL) {
1435                         struct drm_display_mode *mode;
1436                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1437                         drm_mode_probed_add(connector, mode);
1438                         return 1;
1439                 }
1440         }
1441         return 0;
1442 }
1443
1444 static void
1445 intel_dp_destroy (struct drm_connector *connector)
1446 {
1447         drm_sysfs_connector_remove(connector);
1448         drm_connector_cleanup(connector);
1449         kfree(connector);
1450 }
1451
1452 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1453         .dpms = intel_dp_dpms,
1454         .mode_fixup = intel_dp_mode_fixup,
1455         .prepare = intel_encoder_prepare,
1456         .mode_set = intel_dp_mode_set,
1457         .commit = intel_encoder_commit,
1458 };
1459
1460 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1461         .dpms = drm_helper_connector_dpms,
1462         .detect = intel_dp_detect,
1463         .fill_modes = drm_helper_probe_single_connector_modes,
1464         .destroy = intel_dp_destroy,
1465 };
1466
1467 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1468         .get_modes = intel_dp_get_modes,
1469         .mode_valid = intel_dp_mode_valid,
1470         .best_encoder = intel_attached_encoder,
1471 };
1472
1473 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1474 {
1475         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1476
1477         if (intel_encoder->i2c_bus)
1478                 intel_i2c_destroy(intel_encoder->i2c_bus);
1479         drm_encoder_cleanup(encoder);
1480         kfree(intel_encoder);
1481 }
1482
1483 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1484         .destroy = intel_dp_enc_destroy,
1485 };
1486
1487 void
1488 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1489 {
1490         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1491
1492         if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1493                 intel_dp_check_link_status(intel_encoder);
1494 }
1495
1496 /* Return which DP Port should be selected for Transcoder DP control */
1497 int
1498 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1499 {
1500         struct drm_device *dev = crtc->dev;
1501         struct drm_mode_config *mode_config = &dev->mode_config;
1502         struct drm_encoder *encoder;
1503         struct intel_encoder *intel_encoder = NULL;
1504
1505         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1506                 if (encoder->crtc != crtc)
1507                         continue;
1508
1509                 intel_encoder = enc_to_intel_encoder(encoder);
1510                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1511                         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1512                         return dp_priv->output_reg;
1513                 }
1514         }
1515         return -1;
1516 }
1517
1518 /* check the VBT to see whether the eDP is on DP-D port */
1519 bool intel_dpd_is_edp(struct drm_device *dev)
1520 {
1521         struct drm_i915_private *dev_priv = dev->dev_private;
1522         struct child_device_config *p_child;
1523         int i;
1524
1525         if (!dev_priv->child_dev_num)
1526                 return false;
1527
1528         for (i = 0; i < dev_priv->child_dev_num; i++) {
1529                 p_child = dev_priv->child_dev + i;
1530
1531                 if (p_child->dvo_port == PORT_IDPD &&
1532                     p_child->device_type == DEVICE_TYPE_eDP)
1533                         return true;
1534         }
1535         return false;
1536 }
1537
1538 void
1539 intel_dp_init(struct drm_device *dev, int output_reg)
1540 {
1541         struct drm_i915_private *dev_priv = dev->dev_private;
1542         struct drm_connector *connector;
1543         struct intel_encoder *intel_encoder;
1544         struct intel_connector *intel_connector;
1545         struct intel_dp_priv *dp_priv;
1546         const char *name = NULL;
1547         int type;
1548
1549         intel_encoder = kcalloc(sizeof(struct intel_encoder) +
1550                                sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1551         if (!intel_encoder)
1552                 return;
1553
1554         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1555         if (!intel_connector) {
1556                 kfree(intel_encoder);
1557                 return;
1558         }
1559
1560         dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
1561
1562         if (HAS_PCH_SPLIT(dev) && (output_reg == PCH_DP_D))
1563                 if (intel_dpd_is_edp(dev))
1564                         dp_priv->is_pch_edp = true;
1565
1566         if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) {
1567                 type = DRM_MODE_CONNECTOR_eDP;
1568                 intel_encoder->type = INTEL_OUTPUT_EDP;
1569         } else {
1570                 type = DRM_MODE_CONNECTOR_DisplayPort;
1571                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1572         }
1573
1574         connector = &intel_connector->base;
1575         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1576         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1577
1578         connector->polled = DRM_CONNECTOR_POLL_HPD;
1579
1580         if (output_reg == DP_B || output_reg == PCH_DP_B)
1581                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1582         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1583                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1584         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1585                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1586
1587         if (IS_eDP(intel_encoder))
1588                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1589
1590         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1591         connector->interlace_allowed = true;
1592         connector->doublescan_allowed = 0;
1593
1594         dp_priv->intel_encoder = intel_encoder;
1595         dp_priv->output_reg = output_reg;
1596         dp_priv->has_audio = false;
1597         dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1598         intel_encoder->dev_priv = dp_priv;
1599
1600         drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1601                          DRM_MODE_ENCODER_TMDS);
1602         drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1603
1604         drm_mode_connector_attach_encoder(&intel_connector->base,
1605                                           &intel_encoder->enc);
1606         drm_sysfs_connector_add(connector);
1607
1608         /* Set up the DDC bus. */
1609         switch (output_reg) {
1610                 case DP_A:
1611                         name = "DPDDC-A";
1612                         break;
1613                 case DP_B:
1614                 case PCH_DP_B:
1615                         dev_priv->hotplug_supported_mask |=
1616                                 HDMIB_HOTPLUG_INT_STATUS;
1617                         name = "DPDDC-B";
1618                         break;
1619                 case DP_C:
1620                 case PCH_DP_C:
1621                         dev_priv->hotplug_supported_mask |=
1622                                 HDMIC_HOTPLUG_INT_STATUS;
1623                         name = "DPDDC-C";
1624                         break;
1625                 case DP_D:
1626                 case PCH_DP_D:
1627                         dev_priv->hotplug_supported_mask |=
1628                                 HDMID_HOTPLUG_INT_STATUS;
1629                         name = "DPDDC-D";
1630                         break;
1631         }
1632
1633         intel_dp_i2c_init(intel_encoder, intel_connector, name);
1634
1635         intel_encoder->ddc_bus = &dp_priv->adapter;
1636         intel_encoder->hot_plug = intel_dp_hot_plug;
1637
1638         if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) {
1639                 /* initialize panel mode from VBT if available for eDP */
1640                 if (dev_priv->lfp_lvds_vbt_mode) {
1641                         dev_priv->panel_fixed_mode =
1642                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1643                         if (dev_priv->panel_fixed_mode) {
1644                                 dev_priv->panel_fixed_mode->type |=
1645                                         DRM_MODE_TYPE_PREFERRED;
1646                         }
1647                 }
1648         }
1649
1650         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1651          * 0xd.  Failure to do so will result in spurious interrupts being
1652          * generated on the port when a cable is not attached.
1653          */
1654         if (IS_G4X(dev) && !IS_GM45(dev)) {
1655                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1656                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1657         }
1658 }