drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include "drmP.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "drm_dp_helper.h"
  37
  38 #include "drm_crtc_helper.h"
  39
  40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  41
  42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  43 static void intel_update_watermarks(struct drm_device *dev);
  44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  45
  46 typedef struct {
  47     /* given values */
  48     int n;
  49     int m1, m2;
  50     int p1, p2;
  51     /* derived values */
  52     int dot;
  53     int vco;
  54     int m;
  55     int p;
  56 } intel_clock_t;
  57
  58 typedef struct {
  59     int min, max;
  60 } intel_range_t;
  61
  62 typedef struct {
  63     int dot_limit;
  64     int p2_slow, p2_fast;
  65 } intel_p2_t;
  66
  67 #define INTEL_P2_NUM                  2
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71     intel_p2_t      p2;
  72     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  73                       int, int, intel_clock_t *);
  74 };
  75
  76 #define I8XX_DOT_MIN              25000
  77 #define I8XX_DOT_MAX             350000
  78 #define I8XX_VCO_MIN             930000
  79 #define I8XX_VCO_MAX            1400000
  80 #define I8XX_N_MIN                    3
  81 #define I8XX_N_MAX                   16
  82 #define I8XX_M_MIN                   96
  83 #define I8XX_M_MAX                  140
  84 #define I8XX_M1_MIN                  18
  85 #define I8XX_M1_MAX                  26
  86 #define I8XX_M2_MIN                   6
  87 #define I8XX_M2_MAX                  16
  88 #define I8XX_P_MIN                    4
  89 #define I8XX_P_MAX                  128
  90 #define I8XX_P1_MIN                   2
  91 #define I8XX_P1_MAX                  33
  92 #define I8XX_P1_LVDS_MIN              1
  93 #define I8XX_P1_LVDS_MAX              6
  94 #define I8XX_P2_SLOW                  4
  95 #define I8XX_P2_FAST                  2
  96 #define I8XX_P2_LVDS_SLOW             14
  97 #define I8XX_P2_LVDS_FAST             7
  98 #define I8XX_P2_SLOW_LIMIT       165000
  99
 100 #define I9XX_DOT_MIN              20000
 101 #define I9XX_DOT_MAX             400000
 102 #define I9XX_VCO_MIN            1400000
 103 #define I9XX_VCO_MAX            2800000
 104 #define PINEVIEW_VCO_MIN                1700000
 105 #define PINEVIEW_VCO_MAX                3500000
 106 #define I9XX_N_MIN                    1
 107 #define I9XX_N_MAX                    6
 108 /* Pineview's Ncounter is a ring counter */
 109 #define PINEVIEW_N_MIN                3
 110 #define PINEVIEW_N_MAX                6
 111 #define I9XX_M_MIN                   70
 112 #define I9XX_M_MAX                  120
 113 #define PINEVIEW_M_MIN                2
 114 #define PINEVIEW_M_MAX              256
 115 #define I9XX_M1_MIN                  10
 116 #define I9XX_M1_MAX                  22
 117 #define I9XX_M2_MIN                   5
 118 #define I9XX_M2_MAX                   9
 119 /* Pineview M1 is reserved, and must be 0 */
 120 #define PINEVIEW_M1_MIN               0
 121 #define PINEVIEW_M1_MAX               0
 122 #define PINEVIEW_M2_MIN               0
 123 #define PINEVIEW_M2_MAX               254
 124 #define I9XX_P_SDVO_DAC_MIN           5
 125 #define I9XX_P_SDVO_DAC_MAX          80
 126 #define I9XX_P_LVDS_MIN               7
 127 #define I9XX_P_LVDS_MAX              98
 128 #define PINEVIEW_P_LVDS_MIN                   7
 129 #define PINEVIEW_P_LVDS_MAX                  112
 130 #define I9XX_P1_MIN                   1
 131 #define I9XX_P1_MAX                   8
 132 #define I9XX_P2_SDVO_DAC_SLOW                10
 133 #define I9XX_P2_SDVO_DAC_FAST                 5
 134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 135 #define I9XX_P2_LVDS_SLOW                    14
 136 #define I9XX_P2_LVDS_FAST                     7
 137 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 138
 139 /*The parameter is for SDVO on G4x platform*/
 140 #define G4X_DOT_SDVO_MIN           25000
 141 #define G4X_DOT_SDVO_MAX           270000
 142 #define G4X_VCO_MIN                1750000
 143 #define G4X_VCO_MAX                3500000
 144 #define G4X_N_SDVO_MIN             1
 145 #define G4X_N_SDVO_MAX             4
 146 #define G4X_M_SDVO_MIN             104
 147 #define G4X_M_SDVO_MAX             138
 148 #define G4X_M1_SDVO_MIN            17
 149 #define G4X_M1_SDVO_MAX            23
 150 #define G4X_M2_SDVO_MIN            5
 151 #define G4X_M2_SDVO_MAX            11
 152 #define G4X_P_SDVO_MIN             10
 153 #define G4X_P_SDVO_MAX             30
 154 #define G4X_P1_SDVO_MIN            1
 155 #define G4X_P1_SDVO_MAX            3
 156 #define G4X_P2_SDVO_SLOW           10
 157 #define G4X_P2_SDVO_FAST           10
 158 #define G4X_P2_SDVO_LIMIT          270000
 159
 160 /*The parameter is for HDMI_DAC on G4x platform*/
 161 #define G4X_DOT_HDMI_DAC_MIN           22000
 162 #define G4X_DOT_HDMI_DAC_MAX           400000
 163 #define G4X_N_HDMI_DAC_MIN             1
 164 #define G4X_N_HDMI_DAC_MAX             4
 165 #define G4X_M_HDMI_DAC_MIN             104
 166 #define G4X_M_HDMI_DAC_MAX             138
 167 #define G4X_M1_HDMI_DAC_MIN            16
 168 #define G4X_M1_HDMI_DAC_MAX            23
 169 #define G4X_M2_HDMI_DAC_MIN            5
 170 #define G4X_M2_HDMI_DAC_MAX            11
 171 #define G4X_P_HDMI_DAC_MIN             5
 172 #define G4X_P_HDMI_DAC_MAX             80
 173 #define G4X_P1_HDMI_DAC_MIN            1
 174 #define G4X_P1_HDMI_DAC_MAX            8
 175 #define G4X_P2_HDMI_DAC_SLOW           10
 176 #define G4X_P2_HDMI_DAC_FAST           5
 177 #define G4X_P2_HDMI_DAC_LIMIT          165000
 178
 179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 197
 198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 216
 217 /*The parameter is for DISPLAY PORT on G4x platform*/
 218 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 219 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 220 #define G4X_N_DISPLAY_PORT_MIN             1
 221 #define G4X_N_DISPLAY_PORT_MAX             2
 222 #define G4X_M_DISPLAY_PORT_MIN             97
 223 #define G4X_M_DISPLAY_PORT_MAX             108
 224 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 225 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 226 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 227 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 228 #define G4X_P_DISPLAY_PORT_MIN             10
 229 #define G4X_P_DISPLAY_PORT_MAX             20
 230 #define G4X_P1_DISPLAY_PORT_MIN            1
 231 #define G4X_P1_DISPLAY_PORT_MAX            2
 232 #define G4X_P2_DISPLAY_PORT_SLOW           10
 233 #define G4X_P2_DISPLAY_PORT_FAST           10
 234 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 235
 236 /* Ironlake / Sandybridge */
 237 /* as we calculate clock using (register_value + 2) for
 238    N/M1/M2, so here the range value for them is (actual_value-2).
 239  */
 240 #define IRONLAKE_DOT_MIN         25000
 241 #define IRONLAKE_DOT_MAX         350000
 242 #define IRONLAKE_VCO_MIN         1760000
 243 #define IRONLAKE_VCO_MAX         3510000
 244 #define IRONLAKE_M1_MIN          12
 245 #define IRONLAKE_M1_MAX          22
 246 #define IRONLAKE_M2_MIN          5
 247 #define IRONLAKE_M2_MAX          9
 248 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 249
 250 /* We have parameter ranges for different type of outputs. */
 251
 252 /* DAC & HDMI Refclk 120Mhz */
 253 #define IRONLAKE_DAC_N_MIN      1
 254 #define IRONLAKE_DAC_N_MAX      5
 255 #define IRONLAKE_DAC_M_MIN      79
 256 #define IRONLAKE_DAC_M_MAX      127
 257 #define IRONLAKE_DAC_P_MIN      5
 258 #define IRONLAKE_DAC_P_MAX      80
 259 #define IRONLAKE_DAC_P1_MIN     1
 260 #define IRONLAKE_DAC_P1_MAX     8
 261 #define IRONLAKE_DAC_P2_SLOW    10
 262 #define IRONLAKE_DAC_P2_FAST    5
 263
 264 /* LVDS single-channel 120Mhz refclk */
 265 #define IRONLAKE_LVDS_S_N_MIN   1
 266 #define IRONLAKE_LVDS_S_N_MAX   3
 267 #define IRONLAKE_LVDS_S_M_MIN   79
 268 #define IRONLAKE_LVDS_S_M_MAX   118
 269 #define IRONLAKE_LVDS_S_P_MIN   28
 270 #define IRONLAKE_LVDS_S_P_MAX   112
 271 #define IRONLAKE_LVDS_S_P1_MIN  2
 272 #define IRONLAKE_LVDS_S_P1_MAX  8
 273 #define IRONLAKE_LVDS_S_P2_SLOW 14
 274 #define IRONLAKE_LVDS_S_P2_FAST 14
 275
 276 /* LVDS dual-channel 120Mhz refclk */
 277 #define IRONLAKE_LVDS_D_N_MIN   1
 278 #define IRONLAKE_LVDS_D_N_MAX   3
 279 #define IRONLAKE_LVDS_D_M_MIN   79
 280 #define IRONLAKE_LVDS_D_M_MAX   127
 281 #define IRONLAKE_LVDS_D_P_MIN   14
 282 #define IRONLAKE_LVDS_D_P_MAX   56
 283 #define IRONLAKE_LVDS_D_P1_MIN  2
 284 #define IRONLAKE_LVDS_D_P1_MAX  8
 285 #define IRONLAKE_LVDS_D_P2_SLOW 7
 286 #define IRONLAKE_LVDS_D_P2_FAST 7
 287
 288 /* LVDS single-channel 100Mhz refclk */
 289 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 290 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 291 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 292 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 293 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 294 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 295 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 296 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 298 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 299
 300 /* LVDS dual-channel 100Mhz refclk */
 301 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 302 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 303 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 304 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 305 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 306 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 307 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 308 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 310 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 311
 312 /* DisplayPort */
 313 #define IRONLAKE_DP_N_MIN               1
 314 #define IRONLAKE_DP_N_MAX               2
 315 #define IRONLAKE_DP_M_MIN               81
 316 #define IRONLAKE_DP_M_MAX               90
 317 #define IRONLAKE_DP_P_MIN               10
 318 #define IRONLAKE_DP_P_MAX               20
 319 #define IRONLAKE_DP_P2_FAST             10
 320 #define IRONLAKE_DP_P2_SLOW             10
 321 #define IRONLAKE_DP_P2_LIMIT            0
 322 #define IRONLAKE_DP_P1_MIN              1
 323 #define IRONLAKE_DP_P1_MAX              2
 324
 325 static bool
 326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 327                     int target, int refclk, intel_clock_t *best_clock);
 328 static bool
 329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 330                         int target, int refclk, intel_clock_t *best_clock);
 331
 332 static bool
 333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 334                       int target, int refclk, intel_clock_t *best_clock);
 335 static bool
 336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 337                            int target, int refclk, intel_clock_t *best_clock);
 338
 339 static const intel_limit_t intel_limits_i8xx_dvo = {
 340         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 341         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 342         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 343         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 344         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 345         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 346         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 347         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 348         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 349                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 350         .find_pll = intel_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_i8xx_lvds = {
 354         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 355         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 356         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 357         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 358         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 359         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 360         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 361         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 362         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 363                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 364         .find_pll = intel_find_best_PLL,
 365 };
 366
 367 static const intel_limit_t intel_limits_i9xx_sdvo = {
 368         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 369         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 370         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 371         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 372         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 373         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 374         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 375         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 376         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 377                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 378         .find_pll = intel_find_best_PLL,
 379 };
 380
 381 static const intel_limit_t intel_limits_i9xx_lvds = {
 382         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 383         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 384         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 385         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 386         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 387         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 388         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 389         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 390         /* The single-channel range is 25-112Mhz, and dual-channel
 391          * is 80-224Mhz.  Prefer single channel as much as possible.
 392          */
 393         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 394                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 395         .find_pll = intel_find_best_PLL,
 396 };
 397
 398     /* below parameter and function is for G4X Chipset Family*/
 399 static const intel_limit_t intel_limits_g4x_sdvo = {
 400         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 401         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 402         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 403         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 404         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 405         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 406         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 407         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 408         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 409                  .p2_slow = G4X_P2_SDVO_SLOW,
 410                  .p2_fast = G4X_P2_SDVO_FAST
 411         },
 412         .find_pll = intel_g4x_find_best_PLL,
 413 };
 414
 415 static const intel_limit_t intel_limits_g4x_hdmi = {
 416         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 419         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 420         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 421         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 422         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 423         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 424         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 425                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 426                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 432         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 433                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 434         .vco = { .min = G4X_VCO_MIN,
 435                  .max = G4X_VCO_MAX },
 436         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 437                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 438         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 439                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 440         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 441                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 442         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 444         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 446         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 448         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 449                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 450                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 451         },
 452         .find_pll = intel_g4x_find_best_PLL,
 453 };
 454
 455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 456         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 457                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 458         .vco = { .min = G4X_VCO_MIN,
 459                  .max = G4X_VCO_MAX },
 460         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 461                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 462         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 463                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 464         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 465                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 466         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 468         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 470         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 472         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 473                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 474                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 475         },
 476         .find_pll = intel_g4x_find_best_PLL,
 477 };
 478
 479 static const intel_limit_t intel_limits_g4x_display_port = {
 480         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 481                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 482         .vco = { .min = G4X_VCO_MIN,
 483                  .max = G4X_VCO_MAX},
 484         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 485                  .max = G4X_N_DISPLAY_PORT_MAX },
 486         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 487                  .max = G4X_M_DISPLAY_PORT_MAX },
 488         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 489                  .max = G4X_M1_DISPLAY_PORT_MAX },
 490         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 491                  .max = G4X_M2_DISPLAY_PORT_MAX },
 492         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 493                  .max = G4X_P_DISPLAY_PORT_MAX },
 494         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 495                  .max = G4X_P1_DISPLAY_PORT_MAX},
 496         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 497                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 498                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 499         .find_pll = intel_find_pll_g4x_dp,
 500 };
 501
 502 static const intel_limit_t intel_limits_pineview_sdvo = {
 503         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 504         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 505         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 506         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 507         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 508         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 509         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 510         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 511         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 512                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 513         .find_pll = intel_find_best_PLL,
 514 };
 515
 516 static const intel_limit_t intel_limits_pineview_lvds = {
 517         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 518         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 519         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 520         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 521         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 522         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 523         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 524         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 525         /* Pineview only supports single-channel mode. */
 526         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 527                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 528         .find_pll = intel_find_best_PLL,
 529 };
 530
 531 static const intel_limit_t intel_limits_ironlake_dac = {
 532         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 533         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 534         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 535         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 536         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 537         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 538         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 539         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 540         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 541                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 542                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 543         .find_pll = intel_g4x_find_best_PLL,
 544 };
 545
 546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 547         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 548         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 549         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 550         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 551         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 552         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 553         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 554         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 555         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 556                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 557                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 558         .find_pll = intel_g4x_find_best_PLL,
 559 };
 560
 561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 562         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 563         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 564         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 565         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 566         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 567         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 568         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 569         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 570         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 571                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 572                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 573         .find_pll = intel_g4x_find_best_PLL,
 574 };
 575
 576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 577         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 578         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 579         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 580         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 581         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 582         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 583         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 584         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 585         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 586                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 587                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 588         .find_pll = intel_g4x_find_best_PLL,
 589 };
 590
 591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 592         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 593         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 594         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 595         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 596         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 597         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 598         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 599         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 600         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 601                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 602                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 603         .find_pll = intel_g4x_find_best_PLL,
 604 };
 605
 606 static const intel_limit_t intel_limits_ironlake_display_port = {
 607         .dot = { .min = IRONLAKE_DOT_MIN,
 608                  .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,
 610                  .max = IRONLAKE_VCO_MAX},
 611         .n   = { .min = IRONLAKE_DP_N_MIN,
 612                  .max = IRONLAKE_DP_N_MAX },
 613         .m   = { .min = IRONLAKE_DP_M_MIN,
 614                  .max = IRONLAKE_DP_M_MAX },
 615         .m1  = { .min = IRONLAKE_M1_MIN,
 616                  .max = IRONLAKE_M1_MAX },
 617         .m2  = { .min = IRONLAKE_M2_MIN,
 618                  .max = IRONLAKE_M2_MAX },
 619         .p   = { .min = IRONLAKE_DP_P_MIN,
 620                  .max = IRONLAKE_DP_P_MAX },
 621         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 622                  .max = IRONLAKE_DP_P1_MAX},
 623         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 624                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 625                  .p2_fast = IRONLAKE_DP_P2_FAST },
 626         .find_pll = intel_find_pll_ironlake_dp,
 627 };
 628
 629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 630 {
 631         struct drm_device *dev = crtc->dev;
 632         struct drm_i915_private *dev_priv = dev->dev_private;
 633         const intel_limit_t *limit;
 634         int refclk = 120;
 635
 636         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 637                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 638                         refclk = 100;
 639
 640                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 641                     LVDS_CLKB_POWER_UP) {
 642                         /* LVDS dual channel */
 643                         if (refclk == 100)
 644                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 645                         else
 646                                 limit = &intel_limits_ironlake_dual_lvds;
 647                 } else {
 648                         if (refclk == 100)
 649                                 limit = &intel_limits_ironlake_single_lvds_100m;
 650                         else
 651                                 limit = &intel_limits_ironlake_single_lvds;
 652                 }
 653         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 654                         HAS_eDP)
 655                 limit = &intel_limits_ironlake_display_port;
 656         else
 657                 limit = &intel_limits_ironlake_dac;
 658
 659         return limit;
 660 }
 661
 662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 663 {
 664         struct drm_device *dev = crtc->dev;
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         const intel_limit_t *limit;
 667
 668         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 670                     LVDS_CLKB_POWER_UP)
 671                         /* LVDS with dual channel */
 672                         limit = &intel_limits_g4x_dual_channel_lvds;
 673                 else
 674                         /* LVDS with dual channel */
 675                         limit = &intel_limits_g4x_single_channel_lvds;
 676         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 677                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 678                 limit = &intel_limits_g4x_hdmi;
 679         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 680                 limit = &intel_limits_g4x_sdvo;
 681         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 682                 limit = &intel_limits_g4x_display_port;
 683         } else /* The option is for other outputs */
 684                 limit = &intel_limits_i9xx_sdvo;
 685
 686         return limit;
 687 }
 688
 689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 690 {
 691         struct drm_device *dev = crtc->dev;
 692         const intel_limit_t *limit;
 693
 694         if (HAS_PCH_SPLIT(dev))
 695                 limit = intel_ironlake_limit(crtc);
 696         else if (IS_G4X(dev)) {
 697                 limit = intel_g4x_limit(crtc);
 698         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 699                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 700                         limit = &intel_limits_i9xx_lvds;
 701                 else
 702                         limit = &intel_limits_i9xx_sdvo;
 703         } else if (IS_PINEVIEW(dev)) {
 704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 705                         limit = &intel_limits_pineview_lvds;
 706                 else
 707                         limit = &intel_limits_pineview_sdvo;
 708         } else {
 709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 710                         limit = &intel_limits_i8xx_lvds;
 711                 else
 712                         limit = &intel_limits_i8xx_dvo;
 713         }
 714         return limit;
 715 }
 716
 717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 718 static void pineview_clock(int refclk, intel_clock_t *clock)
 719 {
 720         clock->m = clock->m2 + 2;
 721         clock->p = clock->p1 * clock->p2;
 722         clock->vco = refclk * clock->m / clock->n;
 723         clock->dot = clock->vco / clock->p;
 724 }
 725
 726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 727 {
 728         if (IS_PINEVIEW(dev)) {
 729                 pineview_clock(refclk, clock);
 730                 return;
 731         }
 732         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 733         clock->p = clock->p1 * clock->p2;
 734         clock->vco = refclk * clock->m / (clock->n + 2);
 735         clock->dot = clock->vco / clock->p;
 736 }
 737
 738 /**
 739  * Returns whether any output on the specified pipe is of the specified type
 740  */
 741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 742 {
 743     struct drm_device *dev = crtc->dev;
 744     struct drm_mode_config *mode_config = &dev->mode_config;
 745     struct drm_encoder *l_entry;
 746
 747     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 748             if (l_entry && l_entry->crtc == crtc) {
 749                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 750                     if (intel_encoder->type == type)
 751                             return true;
 752             }
 753     }
 754     return false;
 755 }
 756
 757 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 758 /**
 759  * Returns whether the given set of divisors are valid for a given refclk with
 760  * the given connectors.
 761  */
 762
 763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 764 {
 765         const intel_limit_t *limit = intel_limit (crtc);
 766         struct drm_device *dev = crtc->dev;
 767
 768         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 769                 INTELPllInvalid ("p1 out of range\n");
 770         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 771                 INTELPllInvalid ("p out of range\n");
 772         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 773                 INTELPllInvalid ("m2 out of range\n");
 774         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 775                 INTELPllInvalid ("m1 out of range\n");
 776         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 777                 INTELPllInvalid ("m1 <= m2\n");
 778         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 779                 INTELPllInvalid ("m out of range\n");
 780         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 781                 INTELPllInvalid ("n out of range\n");
 782         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 783                 INTELPllInvalid ("vco out of range\n");
 784         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 785          * connector, etc., rather than just a single range.
 786          */
 787         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 788                 INTELPllInvalid ("dot out of range\n");
 789
 790         return true;
 791 }
 792
 793 static bool
 794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 795                     int target, int refclk, intel_clock_t *best_clock)
 796
 797 {
 798         struct drm_device *dev = crtc->dev;
 799         struct drm_i915_private *dev_priv = dev->dev_private;
 800         intel_clock_t clock;
 801         int err = target;
 802
 803         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 804             (I915_READ(LVDS)) != 0) {
 805                 /*
 806                  * For LVDS, if the panel is on, just rely on its current
 807                  * settings for dual-channel.  We haven't figured out how to
 808                  * reliably set up different single/dual channel state, if we
 809                  * even can.
 810                  */
 811                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 812                     LVDS_CLKB_POWER_UP)
 813                         clock.p2 = limit->p2.p2_fast;
 814                 else
 815                         clock.p2 = limit->p2.p2_slow;
 816         } else {
 817                 if (target < limit->p2.dot_limit)
 818                         clock.p2 = limit->p2.p2_slow;
 819                 else
 820                         clock.p2 = limit->p2.p2_fast;
 821         }
 822
 823         memset (best_clock, 0, sizeof (*best_clock));
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         /* m1 is always 0 in Pineview */
 830                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 831                                 break;
 832                         for (clock.n = limit->n.min;
 833                              clock.n <= limit->n.max; clock.n++) {
 834                                 for (clock.p1 = limit->p1.min;
 835                                         clock.p1 <= limit->p1.max; clock.p1++) {
 836                                         int this_err;
 837
 838                                         intel_clock(dev, refclk, &clock);
 839
 840                                         if (!intel_PLL_is_valid(crtc, &clock))
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 858                         int target, int refclk, intel_clock_t *best_clock)
 859 {
 860         struct drm_device *dev = crtc->dev;
 861         struct drm_i915_private *dev_priv = dev->dev_private;
 862         intel_clock_t clock;
 863         int max_n;
 864         bool found;
 865         /* approximately equals target * 0.00585 */
 866         int err_most = (target >> 8) + (target >> 9);
 867         found = false;
 868
 869         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 870                 int lvds_reg;
 871
 872                 if (HAS_PCH_SPLIT(dev))
 873                         lvds_reg = PCH_LVDS;
 874                 else
 875                         lvds_reg = LVDS;
 876                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 877                     LVDS_CLKB_POWER_UP)
 878                         clock.p2 = limit->p2.p2_fast;
 879                 else
 880                         clock.p2 = limit->p2.p2_slow;
 881         } else {
 882                 if (target < limit->p2.dot_limit)
 883                         clock.p2 = limit->p2.p2_slow;
 884                 else
 885                         clock.p2 = limit->p2.p2_fast;
 886         }
 887
 888         memset(best_clock, 0, sizeof(*best_clock));
 889         max_n = limit->n.max;
 890         /* based on hardware requirement, prefer smaller n to precision */
 891         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 892                 /* based on hardware requirement, prefere larger m1,m2 */
 893                 for (clock.m1 = limit->m1.max;
 894                      clock.m1 >= limit->m1.min; clock.m1--) {
 895                         for (clock.m2 = limit->m2.max;
 896                              clock.m2 >= limit->m2.min; clock.m2--) {
 897                                 for (clock.p1 = limit->p1.max;
 898                                      clock.p1 >= limit->p1.min; clock.p1--) {
 899                                         int this_err;
 900
 901                                         intel_clock(dev, refclk, &clock);
 902                                         if (!intel_PLL_is_valid(crtc, &clock))
 903                                                 continue;
 904                                         this_err = abs(clock.dot - target) ;
 905                                         if (this_err < err_most) {
 906                                                 *best_clock = clock;
 907                                                 err_most = this_err;
 908                                                 max_n = clock.n;
 909                                                 found = true;
 910                                         }
 911                                 }
 912                         }
 913                 }
 914         }
 915         return found;
 916 }
 917
 918 static bool
 919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 920                            int target, int refclk, intel_clock_t *best_clock)
 921 {
 922         struct drm_device *dev = crtc->dev;
 923         intel_clock_t clock;
 924
 925         /* return directly when it is eDP */
 926         if (HAS_eDP)
 927                 return true;
 928
 929         if (target < 200000) {
 930                 clock.n = 1;
 931                 clock.p1 = 2;
 932                 clock.p2 = 10;
 933                 clock.m1 = 12;
 934                 clock.m2 = 9;
 935         } else {
 936                 clock.n = 2;
 937                 clock.p1 = 1;
 938                 clock.p2 = 10;
 939                 clock.m1 = 14;
 940                 clock.m2 = 8;
 941         }
 942         intel_clock(dev, refclk, &clock);
 943         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 944         return true;
 945 }
 946
 947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 948 static bool
 949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 950                       int target, int refclk, intel_clock_t *best_clock)
 951 {
 952     intel_clock_t clock;
 953     if (target < 200000) {
 954         clock.p1 = 2;
 955         clock.p2 = 10;
 956         clock.n = 2;
 957         clock.m1 = 23;
 958         clock.m2 = 8;
 959     } else {
 960         clock.p1 = 1;
 961         clock.p2 = 10;
 962         clock.n = 1;
 963         clock.m1 = 14;
 964         clock.m2 = 2;
 965     }
 966     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 967     clock.p = (clock.p1 * clock.p2);
 968     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 969     clock.vco = 0;
 970     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 971     return true;
 972 }
 973
 974 void
 975 intel_wait_for_vblank(struct drm_device *dev)
 976 {
 977         /* Wait for 20ms, i.e. one cycle at 50hz. */
 978         if (in_dbg_master())
 979                 mdelay(20); /* The kernel debugger cannot call msleep() */
 980         else
 981                 msleep(20);
 982 }
 983
 984 /* Parameters have changed, update FBC info */
 985 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 986 {
 987         struct drm_device *dev = crtc->dev;
 988         struct drm_i915_private *dev_priv = dev->dev_private;
 989         struct drm_framebuffer *fb = crtc->fb;
 990         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 991         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 993         int plane, i;
 994         u32 fbc_ctl, fbc_ctl2;
 995
 996         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 997
 998         if (fb->pitch < dev_priv->cfb_pitch)
 999                 dev_priv->cfb_pitch = fb->pitch;
1000
1001         /* FBC_CTL wants 64B units */
1002         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1003         dev_priv->cfb_fence = obj_priv->fence_reg;
1004         dev_priv->cfb_plane = intel_crtc->plane;
1005         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1006
1007         /* Clear old tags */
1008         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1009                 I915_WRITE(FBC_TAG + (i * 4), 0);
1010
1011         /* Set it up... */
1012         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1013         if (obj_priv->tiling_mode != I915_TILING_NONE)
1014                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1015         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1016         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1017
1018         /* enable it... */
1019         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1020         if (IS_I945GM(dev))
1021                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1022         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1023         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1024         if (obj_priv->tiling_mode != I915_TILING_NONE)
1025                 fbc_ctl |= dev_priv->cfb_fence;
1026         I915_WRITE(FBC_CONTROL, fbc_ctl);
1027
1028         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1029                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1030 }
1031
1032 void i8xx_disable_fbc(struct drm_device *dev)
1033 {
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1036         u32 fbc_ctl;
1037
1038         if (!I915_HAS_FBC(dev))
1039                 return;
1040
1041         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1042                 return; /* Already off, just return */
1043
1044         /* Disable compression */
1045         fbc_ctl = I915_READ(FBC_CONTROL);
1046         fbc_ctl &= ~FBC_CTL_EN;
1047         I915_WRITE(FBC_CONTROL, fbc_ctl);
1048
1049         /* Wait for compressing bit to clear */
1050         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1051                 if (time_after(jiffies, timeout)) {
1052                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1053                         break;
1054                 }
1055                 ; /* do nothing */
1056         }
1057
1058         intel_wait_for_vblank(dev);
1059
1060         DRM_DEBUG_KMS("disabled FBC\n");
1061 }
1062
1063 static bool i8xx_fbc_enabled(struct drm_device *dev)
1064 {
1065         struct drm_i915_private *dev_priv = dev->dev_private;
1066
1067         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1068 }
1069
1070 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1071 {
1072         struct drm_device *dev = crtc->dev;
1073         struct drm_i915_private *dev_priv = dev->dev_private;
1074         struct drm_framebuffer *fb = crtc->fb;
1075         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1076         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1078         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1079                      DPFC_CTL_PLANEB);
1080         unsigned long stall_watermark = 200;
1081         u32 dpfc_ctl;
1082
1083         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1084         dev_priv->cfb_fence = obj_priv->fence_reg;
1085         dev_priv->cfb_plane = intel_crtc->plane;
1086
1087         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1088         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1089                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1090                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1091         } else {
1092                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1093         }
1094
1095         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1096         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1097                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1098                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1099         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1100
1101         /* enable it... */
1102         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1103
1104         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1105 }
1106
1107 void g4x_disable_fbc(struct drm_device *dev)
1108 {
1109         struct drm_i915_private *dev_priv = dev->dev_private;
1110         u32 dpfc_ctl;
1111
1112         /* Disable compression */
1113         dpfc_ctl = I915_READ(DPFC_CONTROL);
1114         dpfc_ctl &= ~DPFC_CTL_EN;
1115         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1116         intel_wait_for_vblank(dev);
1117
1118         DRM_DEBUG_KMS("disabled FBC\n");
1119 }
1120
1121 static bool g4x_fbc_enabled(struct drm_device *dev)
1122 {
1123         struct drm_i915_private *dev_priv = dev->dev_private;
1124
1125         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1126 }
1127
1128 bool intel_fbc_enabled(struct drm_device *dev)
1129 {
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         if (!dev_priv->display.fbc_enabled)
1133                 return false;
1134
1135         return dev_priv->display.fbc_enabled(dev);
1136 }
1137
1138 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1139 {
1140         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1141
1142         if (!dev_priv->display.enable_fbc)
1143                 return;
1144
1145         dev_priv->display.enable_fbc(crtc, interval);
1146 }
1147
1148 void intel_disable_fbc(struct drm_device *dev)
1149 {
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151
1152         if (!dev_priv->display.disable_fbc)
1153                 return;
1154
1155         dev_priv->display.disable_fbc(dev);
1156 }
1157
1158 /**
1159  * intel_update_fbc - enable/disable FBC as needed
1160  * @crtc: CRTC to point the compressor at
1161  * @mode: mode in use
1162  *
1163  * Set up the framebuffer compression hardware at mode set time.  We
1164  * enable it if possible:
1165  *   - plane A only (on pre-965)
1166  *   - no pixel mulitply/line duplication
1167  *   - no alpha buffer discard
1168  *   - no dual wide
1169  *   - framebuffer <= 2048 in width, 1536 in height
1170  *
1171  * We can't assume that any compression will take place (worst case),
1172  * so the compressed buffer has to be the same size as the uncompressed
1173  * one.  It also must reside (along with the line length buffer) in
1174  * stolen memory.
1175  *
1176  * We need to enable/disable FBC on a global basis.
1177  */
1178 static void intel_update_fbc(struct drm_crtc *crtc,
1179                              struct drm_display_mode *mode)
1180 {
1181         struct drm_device *dev = crtc->dev;
1182         struct drm_i915_private *dev_priv = dev->dev_private;
1183         struct drm_framebuffer *fb = crtc->fb;
1184         struct intel_framebuffer *intel_fb;
1185         struct drm_i915_gem_object *obj_priv;
1186         struct drm_crtc *tmp_crtc;
1187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1188         int plane = intel_crtc->plane;
1189         int crtcs_enabled = 0;
1190
1191         DRM_DEBUG_KMS("\n");
1192
1193         if (!i915_powersave)
1194                 return;
1195
1196         if (!I915_HAS_FBC(dev))
1197                 return;
1198
1199         if (!crtc->fb)
1200                 return;
1201
1202         intel_fb = to_intel_framebuffer(fb);
1203         obj_priv = to_intel_bo(intel_fb->obj);
1204
1205         /*
1206          * If FBC is already on, we just have to verify that we can
1207          * keep it that way...
1208          * Need to disable if:
1209          *   - more than one pipe is active
1210          *   - changing FBC params (stride, fence, mode)
1211          *   - new fb is too large to fit in compressed buffer
1212          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1213          */
1214         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1215                 if (tmp_crtc->enabled)
1216                         crtcs_enabled++;
1217         }
1218         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1219         if (crtcs_enabled > 1) {
1220                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1221                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1222                 goto out_disable;
1223         }
1224         if (intel_fb->obj->size > dev_priv->cfb_size) {
1225                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1226                                 "compression\n");
1227                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1228                 goto out_disable;
1229         }
1230         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1231             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1232                 DRM_DEBUG_KMS("mode incompatible with compression, "
1233                                 "disabling\n");
1234                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1235                 goto out_disable;
1236         }
1237         if ((mode->hdisplay > 2048) ||
1238             (mode->vdisplay > 1536)) {
1239                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1240                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1241                 goto out_disable;
1242         }
1243         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1244                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1245                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1246                 goto out_disable;
1247         }
1248         if (obj_priv->tiling_mode != I915_TILING_X) {
1249                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1250                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1251                 goto out_disable;
1252         }
1253
1254         if (intel_fbc_enabled(dev)) {
1255                 /* We can re-enable it in this case, but need to update pitch */
1256                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1257                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1258                     (plane != dev_priv->cfb_plane))
1259                         intel_disable_fbc(dev);
1260         }
1261
1262         /* Now try to turn it back on if possible */
1263         if (!intel_fbc_enabled(dev))
1264                 intel_enable_fbc(crtc, 500);
1265
1266         return;
1267
1268 out_disable:
1269         /* Multiple disables should be harmless */
1270         if (intel_fbc_enabled(dev)) {
1271                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1272                 intel_disable_fbc(dev);
1273         }
1274 }
1275
1276 int
1277 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1278 {
1279         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1280         u32 alignment;
1281         int ret;
1282
1283         switch (obj_priv->tiling_mode) {
1284         case I915_TILING_NONE:
1285                 alignment = 64 * 1024;
1286                 break;
1287         case I915_TILING_X:
1288                 /* pin() will align the object as required by fence */
1289                 alignment = 0;
1290                 break;
1291         case I915_TILING_Y:
1292                 /* FIXME: Is this true? */
1293                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1294                 return -EINVAL;
1295         default:
1296                 BUG();
1297         }
1298
1299         ret = i915_gem_object_pin(obj, alignment);
1300         if (ret != 0)
1301                 return ret;
1302
1303         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1304          * fence, whereas 965+ only requires a fence if using
1305          * framebuffer compression.  For simplicity, we always install
1306          * a fence as the cost is not that onerous.
1307          */
1308         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1309             obj_priv->tiling_mode != I915_TILING_NONE) {
1310                 ret = i915_gem_object_get_fence_reg(obj);
1311                 if (ret != 0) {
1312                         i915_gem_object_unpin(obj);
1313                         return ret;
1314                 }
1315         }
1316
1317         return 0;
1318 }
1319
1320 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1321 static int
1322 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1323                            int x, int y)
1324 {
1325         struct drm_device *dev = crtc->dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1328         struct intel_framebuffer *intel_fb;
1329         struct drm_i915_gem_object *obj_priv;
1330         struct drm_gem_object *obj;
1331         int plane = intel_crtc->plane;
1332         unsigned long Start, Offset;
1333         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1334         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1335         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1336         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1337         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1338         u32 dspcntr;
1339
1340         switch (plane) {
1341         case 0:
1342         case 1:
1343                 break;
1344         default:
1345                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1346                 return -EINVAL;
1347         }
1348
1349         intel_fb = to_intel_framebuffer(fb);
1350         obj = intel_fb->obj;
1351         obj_priv = to_intel_bo(obj);
1352
1353         dspcntr = I915_READ(dspcntr_reg);
1354         /* Mask out pixel format bits in case we change it */
1355         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1356         switch (fb->bits_per_pixel) {
1357         case 8:
1358                 dspcntr |= DISPPLANE_8BPP;
1359                 break;
1360         case 16:
1361                 if (fb->depth == 15)
1362                         dspcntr |= DISPPLANE_15_16BPP;
1363                 else
1364                         dspcntr |= DISPPLANE_16BPP;
1365                 break;
1366         case 24:
1367         case 32:
1368                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1369                 break;
1370         default:
1371                 DRM_ERROR("Unknown color depth\n");
1372                 return -EINVAL;
1373         }
1374         if (IS_I965G(dev)) {
1375                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1376                         dspcntr |= DISPPLANE_TILED;
1377                 else
1378                         dspcntr &= ~DISPPLANE_TILED;
1379         }
1380
1381         if (IS_IRONLAKE(dev))
1382                 /* must disable */
1383                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1384
1385         I915_WRITE(dspcntr_reg, dspcntr);
1386
1387         Start = obj_priv->gtt_offset;
1388         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1389
1390         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1391         I915_WRITE(dspstride, fb->pitch);
1392         if (IS_I965G(dev)) {
1393                 I915_WRITE(dspbase, Offset);
1394                 I915_READ(dspbase);
1395                 I915_WRITE(dspsurf, Start);
1396                 I915_READ(dspsurf);
1397                 I915_WRITE(dsptileoff, (y << 16) | x);
1398         } else {
1399                 I915_WRITE(dspbase, Start + Offset);
1400                 I915_READ(dspbase);
1401         }
1402
1403         if ((IS_I965G(dev) || plane == 0))
1404                 intel_update_fbc(crtc, &crtc->mode);
1405
1406         intel_wait_for_vblank(dev);
1407         intel_increase_pllclock(crtc, true);
1408
1409         return 0;
1410 }
1411
1412 static int
1413 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1414                     struct drm_framebuffer *old_fb)
1415 {
1416         struct drm_device *dev = crtc->dev;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         struct drm_i915_master_private *master_priv;
1419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1420         struct intel_framebuffer *intel_fb;
1421         struct drm_i915_gem_object *obj_priv;
1422         struct drm_gem_object *obj;
1423         int pipe = intel_crtc->pipe;
1424         int plane = intel_crtc->plane;
1425         unsigned long Start, Offset;
1426         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1427         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1428         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1429         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1430         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1431         u32 dspcntr;
1432         int ret;
1433
1434         /* no fb bound */
1435         if (!crtc->fb) {
1436                 DRM_DEBUG_KMS("No FB bound\n");
1437                 return 0;
1438         }
1439
1440         switch (plane) {
1441         case 0:
1442         case 1:
1443                 break;
1444         default:
1445                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1446                 return -EINVAL;
1447         }
1448
1449         intel_fb = to_intel_framebuffer(crtc->fb);
1450         obj = intel_fb->obj;
1451         obj_priv = to_intel_bo(obj);
1452
1453         mutex_lock(&dev->struct_mutex);
1454         ret = intel_pin_and_fence_fb_obj(dev, obj);
1455         if (ret != 0) {
1456                 mutex_unlock(&dev->struct_mutex);
1457                 return ret;
1458         }
1459
1460         ret = i915_gem_object_set_to_display_plane(obj);
1461         if (ret != 0) {
1462                 i915_gem_object_unpin(obj);
1463                 mutex_unlock(&dev->struct_mutex);
1464                 return ret;
1465         }
1466
1467         dspcntr = I915_READ(dspcntr_reg);
1468         /* Mask out pixel format bits in case we change it */
1469         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1470         switch (crtc->fb->bits_per_pixel) {
1471         case 8:
1472                 dspcntr |= DISPPLANE_8BPP;
1473                 break;
1474         case 16:
1475                 if (crtc->fb->depth == 15)
1476                         dspcntr |= DISPPLANE_15_16BPP;
1477                 else
1478                         dspcntr |= DISPPLANE_16BPP;
1479                 break;
1480         case 24:
1481         case 32:
1482                 if (crtc->fb->depth == 30)
1483                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1484                 else
1485                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1486                 break;
1487         default:
1488                 DRM_ERROR("Unknown color depth\n");
1489                 i915_gem_object_unpin(obj);
1490                 mutex_unlock(&dev->struct_mutex);
1491                 return -EINVAL;
1492         }
1493         if (IS_I965G(dev)) {
1494                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1495                         dspcntr |= DISPPLANE_TILED;
1496                 else
1497                         dspcntr &= ~DISPPLANE_TILED;
1498         }
1499
1500         if (HAS_PCH_SPLIT(dev))
1501                 /* must disable */
1502                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1503
1504         I915_WRITE(dspcntr_reg, dspcntr);
1505
1506         Start = obj_priv->gtt_offset;
1507         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1508
1509         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1510                       Start, Offset, x, y, crtc->fb->pitch);
1511         I915_WRITE(dspstride, crtc->fb->pitch);
1512         if (IS_I965G(dev)) {
1513                 I915_WRITE(dspbase, Offset);
1514                 I915_READ(dspbase);
1515                 I915_WRITE(dspsurf, Start);
1516                 I915_READ(dspsurf);
1517                 I915_WRITE(dsptileoff, (y << 16) | x);
1518         } else {
1519                 I915_WRITE(dspbase, Start + Offset);
1520                 I915_READ(dspbase);
1521         }
1522
1523         if ((IS_I965G(dev) || plane == 0))
1524                 intel_update_fbc(crtc, &crtc->mode);
1525
1526         intel_wait_for_vblank(dev);
1527
1528         if (old_fb) {
1529                 intel_fb = to_intel_framebuffer(old_fb);
1530                 obj_priv = to_intel_bo(intel_fb->obj);
1531                 i915_gem_object_unpin(intel_fb->obj);
1532         }
1533         intel_increase_pllclock(crtc, true);
1534
1535         mutex_unlock(&dev->struct_mutex);
1536
1537         if (!dev->primary->master)
1538                 return 0;
1539
1540         master_priv = dev->primary->master->driver_priv;
1541         if (!master_priv->sarea_priv)
1542                 return 0;
1543
1544         if (pipe) {
1545                 master_priv->sarea_priv->pipeB_x = x;
1546                 master_priv->sarea_priv->pipeB_y = y;
1547         } else {
1548                 master_priv->sarea_priv->pipeA_x = x;
1549                 master_priv->sarea_priv->pipeA_y = y;
1550         }
1551
1552         return 0;
1553 }
1554
1555 /* Disable the VGA plane that we never use */
1556 static void i915_disable_vga (struct drm_device *dev)
1557 {
1558         struct drm_i915_private *dev_priv = dev->dev_private;
1559         u8 sr1;
1560         u32 vga_reg;
1561
1562         if (HAS_PCH_SPLIT(dev))
1563                 vga_reg = CPU_VGACNTRL;
1564         else
1565                 vga_reg = VGACNTRL;
1566
1567         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1568                 return;
1569
1570         I915_WRITE8(VGA_SR_INDEX, 1);
1571         sr1 = I915_READ8(VGA_SR_DATA);
1572         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1573         udelay(100);
1574
1575         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1576 }
1577
1578 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1579 {
1580         struct drm_device *dev = crtc->dev;
1581         struct drm_i915_private *dev_priv = dev->dev_private;
1582         u32 dpa_ctl;
1583
1584         DRM_DEBUG_KMS("\n");
1585         dpa_ctl = I915_READ(DP_A);
1586         dpa_ctl &= ~DP_PLL_ENABLE;
1587         I915_WRITE(DP_A, dpa_ctl);
1588 }
1589
1590 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1591 {
1592         struct drm_device *dev = crtc->dev;
1593         struct drm_i915_private *dev_priv = dev->dev_private;
1594         u32 dpa_ctl;
1595
1596         dpa_ctl = I915_READ(DP_A);
1597         dpa_ctl |= DP_PLL_ENABLE;
1598         I915_WRITE(DP_A, dpa_ctl);
1599         udelay(200);
1600 }
1601
1602
1603 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1604 {
1605         struct drm_device *dev = crtc->dev;
1606         struct drm_i915_private *dev_priv = dev->dev_private;
1607         u32 dpa_ctl;
1608
1609         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1610         dpa_ctl = I915_READ(DP_A);
1611         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1612
1613         if (clock < 200000) {
1614                 u32 temp;
1615                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1616                 /* workaround for 160Mhz:
1617                    1) program 0x4600c bits 15:0 = 0x8124
1618                    2) program 0x46010 bit 0 = 1
1619                    3) program 0x46034 bit 24 = 1
1620                    4) program 0x64000 bit 14 = 1
1621                    */
1622                 temp = I915_READ(0x4600c);
1623                 temp &= 0xffff0000;
1624                 I915_WRITE(0x4600c, temp | 0x8124);
1625
1626                 temp = I915_READ(0x46010);
1627                 I915_WRITE(0x46010, temp | 1);
1628
1629                 temp = I915_READ(0x46034);
1630                 I915_WRITE(0x46034, temp | (1 << 24));
1631         } else {
1632                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1633         }
1634         I915_WRITE(DP_A, dpa_ctl);
1635
1636         udelay(500);
1637 }
1638
1639 /* The FDI link training functions for ILK/Ibexpeak. */
1640 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1641 {
1642         struct drm_device *dev = crtc->dev;
1643         struct drm_i915_private *dev_priv = dev->dev_private;
1644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1645         int pipe = intel_crtc->pipe;
1646         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1647         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1648         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1649         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1650         u32 temp, tries = 0;
1651
1652         /* enable CPU FDI TX and PCH FDI RX */
1653         temp = I915_READ(fdi_tx_reg);
1654         temp |= FDI_TX_ENABLE;
1655         temp &= ~(7 << 19);
1656         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1657         temp &= ~FDI_LINK_TRAIN_NONE;
1658         temp |= FDI_LINK_TRAIN_PATTERN_1;
1659         I915_WRITE(fdi_tx_reg, temp);
1660         I915_READ(fdi_tx_reg);
1661
1662         temp = I915_READ(fdi_rx_reg);
1663         temp &= ~FDI_LINK_TRAIN_NONE;
1664         temp |= FDI_LINK_TRAIN_PATTERN_1;
1665         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1666         I915_READ(fdi_rx_reg);
1667         udelay(150);
1668
1669         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1670            for train result */
1671         temp = I915_READ(fdi_rx_imr_reg);
1672         temp &= ~FDI_RX_SYMBOL_LOCK;
1673         temp &= ~FDI_RX_BIT_LOCK;
1674         I915_WRITE(fdi_rx_imr_reg, temp);
1675         I915_READ(fdi_rx_imr_reg);
1676         udelay(150);
1677
1678         for (;;) {
1679                 temp = I915_READ(fdi_rx_iir_reg);
1680                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1681
1682                 if ((temp & FDI_RX_BIT_LOCK)) {
1683                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1684                         I915_WRITE(fdi_rx_iir_reg,
1685                                    temp | FDI_RX_BIT_LOCK);
1686                         break;
1687                 }
1688
1689                 tries++;
1690
1691                 if (tries > 5) {
1692                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1693                         break;
1694                 }
1695         }
1696
1697         /* Train 2 */
1698         temp = I915_READ(fdi_tx_reg);
1699         temp &= ~FDI_LINK_TRAIN_NONE;
1700         temp |= FDI_LINK_TRAIN_PATTERN_2;
1701         I915_WRITE(fdi_tx_reg, temp);
1702
1703         temp = I915_READ(fdi_rx_reg);
1704         temp &= ~FDI_LINK_TRAIN_NONE;
1705         temp |= FDI_LINK_TRAIN_PATTERN_2;
1706         I915_WRITE(fdi_rx_reg, temp);
1707         udelay(150);
1708
1709         tries = 0;
1710
1711         for (;;) {
1712                 temp = I915_READ(fdi_rx_iir_reg);
1713                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1714
1715                 if (temp & FDI_RX_SYMBOL_LOCK) {
1716                         I915_WRITE(fdi_rx_iir_reg,
1717                                    temp | FDI_RX_SYMBOL_LOCK);
1718                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1719                         break;
1720                 }
1721
1722                 tries++;
1723
1724                 if (tries > 5) {
1725                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1726                         break;
1727                 }
1728         }
1729
1730         DRM_DEBUG_KMS("FDI train done\n");
1731 }
1732
1733 static int snb_b_fdi_train_param [] = {
1734         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1735         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1736         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1737         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1738 };
1739
1740 /* The FDI link training functions for SNB/Cougarpoint. */
1741 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1742 {
1743         struct drm_device *dev = crtc->dev;
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1746         int pipe = intel_crtc->pipe;
1747         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1748         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1749         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1750         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1751         u32 temp, i;
1752
1753         /* enable CPU FDI TX and PCH FDI RX */
1754         temp = I915_READ(fdi_tx_reg);
1755         temp |= FDI_TX_ENABLE;
1756         temp &= ~(7 << 19);
1757         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1758         temp &= ~FDI_LINK_TRAIN_NONE;
1759         temp |= FDI_LINK_TRAIN_PATTERN_1;
1760         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1761         /* SNB-B */
1762         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1763         I915_WRITE(fdi_tx_reg, temp);
1764         I915_READ(fdi_tx_reg);
1765
1766         temp = I915_READ(fdi_rx_reg);
1767         if (HAS_PCH_CPT(dev)) {
1768                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1769                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1770         } else {
1771                 temp &= ~FDI_LINK_TRAIN_NONE;
1772                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1773         }
1774         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1775         I915_READ(fdi_rx_reg);
1776         udelay(150);
1777
1778         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1779            for train result */
1780         temp = I915_READ(fdi_rx_imr_reg);
1781         temp &= ~FDI_RX_SYMBOL_LOCK;
1782         temp &= ~FDI_RX_BIT_LOCK;
1783         I915_WRITE(fdi_rx_imr_reg, temp);
1784         I915_READ(fdi_rx_imr_reg);
1785         udelay(150);
1786
1787         for (i = 0; i < 4; i++ ) {
1788                 temp = I915_READ(fdi_tx_reg);
1789                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1790                 temp |= snb_b_fdi_train_param[i];
1791                 I915_WRITE(fdi_tx_reg, temp);
1792                 udelay(500);
1793
1794                 temp = I915_READ(fdi_rx_iir_reg);
1795                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1796
1797                 if (temp & FDI_RX_BIT_LOCK) {
1798                         I915_WRITE(fdi_rx_iir_reg,
1799                                    temp | FDI_RX_BIT_LOCK);
1800                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1801                         break;
1802                 }
1803         }
1804         if (i == 4)
1805                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1806
1807         /* Train 2 */
1808         temp = I915_READ(fdi_tx_reg);
1809         temp &= ~FDI_LINK_TRAIN_NONE;
1810         temp |= FDI_LINK_TRAIN_PATTERN_2;
1811         if (IS_GEN6(dev)) {
1812                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1813                 /* SNB-B */
1814                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1815         }
1816         I915_WRITE(fdi_tx_reg, temp);
1817
1818         temp = I915_READ(fdi_rx_reg);
1819         if (HAS_PCH_CPT(dev)) {
1820                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1821                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1822         } else {
1823                 temp &= ~FDI_LINK_TRAIN_NONE;
1824                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1825         }
1826         I915_WRITE(fdi_rx_reg, temp);
1827         udelay(150);
1828
1829         for (i = 0; i < 4; i++ ) {
1830                 temp = I915_READ(fdi_tx_reg);
1831                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1832                 temp |= snb_b_fdi_train_param[i];
1833                 I915_WRITE(fdi_tx_reg, temp);
1834                 udelay(500);
1835
1836                 temp = I915_READ(fdi_rx_iir_reg);
1837                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1838
1839                 if (temp & FDI_RX_SYMBOL_LOCK) {
1840                         I915_WRITE(fdi_rx_iir_reg,
1841                                    temp | FDI_RX_SYMBOL_LOCK);
1842                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1843                         break;
1844                 }
1845         }
1846         if (i == 4)
1847                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1848
1849         DRM_DEBUG_KMS("FDI train done.\n");
1850 }
1851
1852 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1853 {
1854         struct drm_device *dev = crtc->dev;
1855         struct drm_i915_private *dev_priv = dev->dev_private;
1856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1857         int pipe = intel_crtc->pipe;
1858         int plane = intel_crtc->plane;
1859         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1860         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1861         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1862         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1863         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1864         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1865         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1866         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1867         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1868         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1869         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1870         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1871         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1872         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1873         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1874         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1875         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1876         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1877         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1878         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1879         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1880         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1881         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1882         u32 temp;
1883         int n;
1884         u32 pipe_bpc;
1885
1886         temp = I915_READ(pipeconf_reg);
1887         pipe_bpc = temp & PIPE_BPC_MASK;
1888
1889         /* XXX: When our outputs are all unaware of DPMS modes other than off
1890          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1891          */
1892         switch (mode) {
1893         case DRM_MODE_DPMS_ON:
1894         case DRM_MODE_DPMS_STANDBY:
1895         case DRM_MODE_DPMS_SUSPEND:
1896                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1897
1898                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1899                         temp = I915_READ(PCH_LVDS);
1900                         if ((temp & LVDS_PORT_EN) == 0) {
1901                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1902                                 POSTING_READ(PCH_LVDS);
1903                         }
1904                 }
1905
1906                 if (HAS_eDP) {
1907                         /* enable eDP PLL */
1908                         ironlake_enable_pll_edp(crtc);
1909                 } else {
1910
1911                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1912                         temp = I915_READ(fdi_rx_reg);
1913                         /*
1914                          * make the BPC in FDI Rx be consistent with that in
1915                          * pipeconf reg.
1916                          */
1917                         temp &= ~(0x7 << 16);
1918                         temp |= (pipe_bpc << 11);
1919                         temp &= ~(7 << 19);
1920                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1921                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1922                         I915_READ(fdi_rx_reg);
1923                         udelay(200);
1924
1925                         /* Switch from Rawclk to PCDclk */
1926                         temp = I915_READ(fdi_rx_reg);
1927                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1928                         I915_READ(fdi_rx_reg);
1929                         udelay(200);
1930
1931                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1932                         temp = I915_READ(fdi_tx_reg);
1933                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1934                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1935                                 I915_READ(fdi_tx_reg);
1936                                 udelay(100);
1937                         }
1938                 }
1939
1940                 /* Enable panel fitting for LVDS */
1941                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1942                         temp = I915_READ(pf_ctl_reg);
1943                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1944
1945                         /* currently full aspect */
1946                         I915_WRITE(pf_win_pos, 0);
1947
1948                         I915_WRITE(pf_win_size,
1949                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1950                                    (dev_priv->panel_fixed_mode->vdisplay));
1951                 }
1952
1953                 /* Enable CPU pipe */
1954                 temp = I915_READ(pipeconf_reg);
1955                 if ((temp & PIPEACONF_ENABLE) == 0) {
1956                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1957                         I915_READ(pipeconf_reg);
1958                         udelay(100);
1959                 }
1960
1961                 /* configure and enable CPU plane */
1962                 temp = I915_READ(dspcntr_reg);
1963                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1964                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1965                         /* Flush the plane changes */
1966                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1967                 }
1968
1969                 if (!HAS_eDP) {
1970                         /* For PCH output, training FDI link */
1971                         if (IS_GEN6(dev))
1972                                 gen6_fdi_link_train(crtc);
1973                         else
1974                                 ironlake_fdi_link_train(crtc);
1975
1976                         /* enable PCH DPLL */
1977                         temp = I915_READ(pch_dpll_reg);
1978                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1979                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1980                                 I915_READ(pch_dpll_reg);
1981                         }
1982                         udelay(200);
1983
1984                         if (HAS_PCH_CPT(dev)) {
1985                                 /* Be sure PCH DPLL SEL is set */
1986                                 temp = I915_READ(PCH_DPLL_SEL);
1987                                 if (trans_dpll_sel == 0 &&
1988                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1989                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1990                                 else if (trans_dpll_sel == 1 &&
1991                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1992                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1993                                 I915_WRITE(PCH_DPLL_SEL, temp);
1994                                 I915_READ(PCH_DPLL_SEL);
1995                         }
1996
1997                         /* set transcoder timing */
1998                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1999                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2000                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2001
2002                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2003                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2004                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2005
2006                         /* enable normal train */
2007                         temp = I915_READ(fdi_tx_reg);
2008                         temp &= ~FDI_LINK_TRAIN_NONE;
2009                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2010                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2011                         I915_READ(fdi_tx_reg);
2012
2013                         temp = I915_READ(fdi_rx_reg);
2014                         if (HAS_PCH_CPT(dev)) {
2015                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2016                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2017                         } else {
2018                                 temp &= ~FDI_LINK_TRAIN_NONE;
2019                                 temp |= FDI_LINK_TRAIN_NONE;
2020                         }
2021                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2022                         I915_READ(fdi_rx_reg);
2023
2024                         /* wait one idle pattern time */
2025                         udelay(100);
2026
2027                         /* For PCH DP, enable TRANS_DP_CTL */
2028                         if (HAS_PCH_CPT(dev) &&
2029                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2030                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2031                                 int reg;
2032
2033                                 reg = I915_READ(trans_dp_ctl);
2034                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
2035                                 reg = TRANS_DP_OUTPUT_ENABLE |
2036                                       TRANS_DP_ENH_FRAMING |
2037                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
2038                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
2039
2040                                 switch (intel_trans_dp_port_sel(crtc)) {
2041                                 case PCH_DP_B:
2042                                         reg |= TRANS_DP_PORT_SEL_B;
2043                                         break;
2044                                 case PCH_DP_C:
2045                                         reg |= TRANS_DP_PORT_SEL_C;
2046                                         break;
2047                                 case PCH_DP_D:
2048                                         reg |= TRANS_DP_PORT_SEL_D;
2049                                         break;
2050                                 default:
2051                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2052                                         reg |= TRANS_DP_PORT_SEL_B;
2053                                         break;
2054                                 }
2055
2056                                 I915_WRITE(trans_dp_ctl, reg);
2057                                 POSTING_READ(trans_dp_ctl);
2058                         }
2059
2060                         /* enable PCH transcoder */
2061                         temp = I915_READ(transconf_reg);
2062                         /*
2063                          * make the BPC in transcoder be consistent with
2064                          * that in pipeconf reg.
2065                          */
2066                         temp &= ~PIPE_BPC_MASK;
2067                         temp |= pipe_bpc;
2068                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2069                         I915_READ(transconf_reg);
2070
2071                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2072                                 ;
2073
2074                 }
2075
2076                 intel_crtc_load_lut(crtc);
2077
2078         break;
2079         case DRM_MODE_DPMS_OFF:
2080                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2081
2082                 drm_vblank_off(dev, pipe);
2083                 /* Disable display plane */
2084                 temp = I915_READ(dspcntr_reg);
2085                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2086                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2087                         /* Flush the plane changes */
2088                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2089                         I915_READ(dspbase_reg);
2090                 }
2091
2092                 i915_disable_vga(dev);
2093
2094                 /* disable cpu pipe, disable after all planes disabled */
2095                 temp = I915_READ(pipeconf_reg);
2096                 if ((temp & PIPEACONF_ENABLE) != 0) {
2097                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2098                         I915_READ(pipeconf_reg);
2099                         n = 0;
2100                         /* wait for cpu pipe off, pipe state */
2101                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2102                                 n++;
2103                                 if (n < 60) {
2104                                         udelay(500);
2105                                         continue;
2106                                 } else {
2107                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2108                                                                 pipe);
2109                                         break;
2110                                 }
2111                         }
2112                 } else
2113                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2114
2115                 udelay(100);
2116
2117                 /* Disable PF */
2118                 temp = I915_READ(pf_ctl_reg);
2119                 if ((temp & PF_ENABLE) != 0) {
2120                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2121                         I915_READ(pf_ctl_reg);
2122                 }
2123                 I915_WRITE(pf_win_size, 0);
2124                 POSTING_READ(pf_win_size);
2125
2126
2127                 /* disable CPU FDI tx and PCH FDI rx */
2128                 temp = I915_READ(fdi_tx_reg);
2129                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2130                 I915_READ(fdi_tx_reg);
2131
2132                 temp = I915_READ(fdi_rx_reg);
2133                 /* BPC in FDI rx is consistent with that in pipeconf */
2134                 temp &= ~(0x07 << 16);
2135                 temp |= (pipe_bpc << 11);
2136                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2137                 I915_READ(fdi_rx_reg);
2138
2139                 udelay(100);
2140
2141                 /* still set train pattern 1 */
2142                 temp = I915_READ(fdi_tx_reg);
2143                 temp &= ~FDI_LINK_TRAIN_NONE;
2144                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2145                 I915_WRITE(fdi_tx_reg, temp);
2146                 POSTING_READ(fdi_tx_reg);
2147
2148                 temp = I915_READ(fdi_rx_reg);
2149                 if (HAS_PCH_CPT(dev)) {
2150                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2151                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2152                 } else {
2153                         temp &= ~FDI_LINK_TRAIN_NONE;
2154                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2155                 }
2156                 I915_WRITE(fdi_rx_reg, temp);
2157                 POSTING_READ(fdi_rx_reg);
2158
2159                 udelay(100);
2160
2161                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2162                         temp = I915_READ(PCH_LVDS);
2163                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2164                         I915_READ(PCH_LVDS);
2165                         udelay(100);
2166                 }
2167
2168                 /* disable PCH transcoder */
2169                 temp = I915_READ(transconf_reg);
2170                 if ((temp & TRANS_ENABLE) != 0) {
2171                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2172                         I915_READ(transconf_reg);
2173                         n = 0;
2174                         /* wait for PCH transcoder off, transcoder state */
2175                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2176                                 n++;
2177                                 if (n < 60) {
2178                                         udelay(500);
2179                                         continue;
2180                                 } else {
2181                                         DRM_DEBUG_KMS("transcoder %d off "
2182                                                         "delay\n", pipe);
2183                                         break;
2184                                 }
2185                         }
2186                 }
2187
2188                 temp = I915_READ(transconf_reg);
2189                 /* BPC in transcoder is consistent with that in pipeconf */
2190                 temp &= ~PIPE_BPC_MASK;
2191                 temp |= pipe_bpc;
2192                 I915_WRITE(transconf_reg, temp);
2193                 I915_READ(transconf_reg);
2194                 udelay(100);
2195
2196                 if (HAS_PCH_CPT(dev)) {
2197                         /* disable TRANS_DP_CTL */
2198                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2199                         int reg;
2200
2201                         reg = I915_READ(trans_dp_ctl);
2202                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2203                         I915_WRITE(trans_dp_ctl, reg);
2204                         POSTING_READ(trans_dp_ctl);
2205
2206                         /* disable DPLL_SEL */
2207                         temp = I915_READ(PCH_DPLL_SEL);
2208                         if (trans_dpll_sel == 0)
2209                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2210                         else
2211                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2212                         I915_WRITE(PCH_DPLL_SEL, temp);
2213                         I915_READ(PCH_DPLL_SEL);
2214
2215                 }
2216
2217                 /* disable PCH DPLL */
2218                 temp = I915_READ(pch_dpll_reg);
2219                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2220                 I915_READ(pch_dpll_reg);
2221
2222                 if (HAS_eDP) {
2223                         ironlake_disable_pll_edp(crtc);
2224                 }
2225
2226                 /* Switch from PCDclk to Rawclk */
2227                 temp = I915_READ(fdi_rx_reg);
2228                 temp &= ~FDI_SEL_PCDCLK;
2229                 I915_WRITE(fdi_rx_reg, temp);
2230                 I915_READ(fdi_rx_reg);
2231
2232                 /* Disable CPU FDI TX PLL */
2233                 temp = I915_READ(fdi_tx_reg);
2234                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2235                 I915_READ(fdi_tx_reg);
2236                 udelay(100);
2237
2238                 temp = I915_READ(fdi_rx_reg);
2239                 temp &= ~FDI_RX_PLL_ENABLE;
2240                 I915_WRITE(fdi_rx_reg, temp);
2241                 I915_READ(fdi_rx_reg);
2242
2243                 /* Wait for the clocks to turn off. */
2244                 udelay(100);
2245                 break;
2246         }
2247 }
2248
2249 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2250 {
2251         struct intel_overlay *overlay;
2252         int ret;
2253
2254         if (!enable && intel_crtc->overlay) {
2255                 overlay = intel_crtc->overlay;
2256                 mutex_lock(&overlay->dev->struct_mutex);
2257                 for (;;) {
2258                         ret = intel_overlay_switch_off(overlay);
2259                         if (ret == 0)
2260                                 break;
2261
2262                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2263                         if (ret != 0) {
2264                                 /* overlay doesn't react anymore. Usually
2265                                  * results in a black screen and an unkillable
2266                                  * X server. */
2267                                 BUG();
2268                                 overlay->hw_wedged = HW_WEDGED;
2269                                 break;
2270                         }
2271                 }
2272                 mutex_unlock(&overlay->dev->struct_mutex);
2273         }
2274         /* Let userspace switch the overlay on again. In most cases userspace
2275          * has to recompute where to put it anyway. */
2276
2277         return;
2278 }
2279
2280 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2281 {
2282         struct drm_device *dev = crtc->dev;
2283         struct drm_i915_private *dev_priv = dev->dev_private;
2284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2285         int pipe = intel_crtc->pipe;
2286         int plane = intel_crtc->plane;
2287         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2288         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2289         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2290         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2291         u32 temp;
2292
2293         /* XXX: When our outputs are all unaware of DPMS modes other than off
2294          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2295          */
2296         switch (mode) {
2297         case DRM_MODE_DPMS_ON:
2298         case DRM_MODE_DPMS_STANDBY:
2299         case DRM_MODE_DPMS_SUSPEND:
2300                 intel_update_watermarks(dev);
2301
2302                 /* Enable the DPLL */
2303                 temp = I915_READ(dpll_reg);
2304                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2305                         I915_WRITE(dpll_reg, temp);
2306                         I915_READ(dpll_reg);
2307                         /* Wait for the clocks to stabilize. */
2308                         udelay(150);
2309                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2310                         I915_READ(dpll_reg);
2311                         /* Wait for the clocks to stabilize. */
2312                         udelay(150);
2313                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2314                         I915_READ(dpll_reg);
2315                         /* Wait for the clocks to stabilize. */
2316                         udelay(150);
2317                 }
2318
2319                 /* Enable the pipe */
2320                 temp = I915_READ(pipeconf_reg);
2321                 if ((temp & PIPEACONF_ENABLE) == 0)
2322                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2323
2324                 /* Enable the plane */
2325                 temp = I915_READ(dspcntr_reg);
2326                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2327                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2328                         /* Flush the plane changes */
2329                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2330                 }
2331
2332                 intel_crtc_load_lut(crtc);
2333
2334                 if ((IS_I965G(dev) || plane == 0))
2335                         intel_update_fbc(crtc, &crtc->mode);
2336
2337                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2338                 intel_crtc_dpms_overlay(intel_crtc, true);
2339         break;
2340         case DRM_MODE_DPMS_OFF:
2341                 intel_update_watermarks(dev);
2342
2343                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2344                 intel_crtc_dpms_overlay(intel_crtc, false);
2345                 drm_vblank_off(dev, pipe);
2346
2347                 if (dev_priv->cfb_plane == plane &&
2348                     dev_priv->display.disable_fbc)
2349                         dev_priv->display.disable_fbc(dev);
2350
2351                 /* Disable the VGA plane that we never use */
2352                 i915_disable_vga(dev);
2353
2354                 /* Disable display plane */
2355                 temp = I915_READ(dspcntr_reg);
2356                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2357                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2358                         /* Flush the plane changes */
2359                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2360                         I915_READ(dspbase_reg);
2361                 }
2362
2363                 if (!IS_I9XX(dev)) {
2364                         /* Wait for vblank for the disable to take effect */
2365                         intel_wait_for_vblank(dev);
2366                 }
2367
2368                 /* Don't disable pipe A or pipe A PLLs if needed */
2369                 if (pipeconf_reg == PIPEACONF &&
2370                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2371                         goto skip_pipe_off;
2372
2373                 /* Next, disable display pipes */
2374                 temp = I915_READ(pipeconf_reg);
2375                 if ((temp & PIPEACONF_ENABLE) != 0) {
2376                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2377                         I915_READ(pipeconf_reg);
2378                 }
2379
2380                 /* Wait for vblank for the disable to take effect. */
2381                 intel_wait_for_vblank(dev);
2382
2383                 temp = I915_READ(dpll_reg);
2384                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2385                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2386                         I915_READ(dpll_reg);
2387                 }
2388         skip_pipe_off:
2389                 /* Wait for the clocks to turn off. */
2390                 udelay(150);
2391                 break;
2392         }
2393 }
2394
2395 /**
2396  * Sets the power management mode of the pipe and plane.
2397  *
2398  * This code should probably grow support for turning the cursor off and back
2399  * on appropriately at the same time as we're turning the pipe off/on.
2400  */
2401 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2402 {
2403         struct drm_device *dev = crtc->dev;
2404         struct drm_i915_private *dev_priv = dev->dev_private;
2405         struct drm_i915_master_private *master_priv;
2406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407         int pipe = intel_crtc->pipe;
2408         bool enabled;
2409
2410         dev_priv->display.dpms(crtc, mode);
2411
2412         intel_crtc->dpms_mode = mode;
2413
2414         if (!dev->primary->master)
2415                 return;
2416
2417         master_priv = dev->primary->master->driver_priv;
2418         if (!master_priv->sarea_priv)
2419                 return;
2420
2421         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2422
2423         switch (pipe) {
2424         case 0:
2425                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2426                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2427                 break;
2428         case 1:
2429                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2430                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2431                 break;
2432         default:
2433                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2434                 break;
2435         }
2436 }
2437
2438 static void intel_crtc_prepare (struct drm_crtc *crtc)
2439 {
2440         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2441         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2442 }
2443
2444 static void intel_crtc_commit (struct drm_crtc *crtc)
2445 {
2446         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2447         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2448 }
2449
2450 void intel_encoder_prepare (struct drm_encoder *encoder)
2451 {
2452         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2453         /* lvds has its own version of prepare see intel_lvds_prepare */
2454         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2455 }
2456
2457 void intel_encoder_commit (struct drm_encoder *encoder)
2458 {
2459         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2460         /* lvds has its own version of commit see intel_lvds_commit */
2461         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2462 }
2463
2464 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2465                                   struct drm_display_mode *mode,
2466                                   struct drm_display_mode *adjusted_mode)
2467 {
2468         struct drm_device *dev = crtc->dev;
2469         if (HAS_PCH_SPLIT(dev)) {
2470                 /* FDI link clock is fixed at 2.7G */
2471                 if (mode->clock * 3 > 27000 * 4)
2472                         return MODE_CLOCK_HIGH;
2473         }
2474         return true;
2475 }
2476
2477 static int i945_get_display_clock_speed(struct drm_device *dev)
2478 {
2479         return 400000;
2480 }
2481
2482 static int i915_get_display_clock_speed(struct drm_device *dev)
2483 {
2484         return 333000;
2485 }
2486
2487 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2488 {
2489         return 200000;
2490 }
2491
2492 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2493 {
2494         u16 gcfgc = 0;
2495
2496         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2497
2498         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2499                 return 133000;
2500         else {
2501                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2502                 case GC_DISPLAY_CLOCK_333_MHZ:
2503                         return 333000;
2504                 default:
2505                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2506                         return 190000;
2507                 }
2508         }
2509 }
2510
2511 static int i865_get_display_clock_speed(struct drm_device *dev)
2512 {
2513         return 266000;
2514 }
2515
2516 static int i855_get_display_clock_speed(struct drm_device *dev)
2517 {
2518         u16 hpllcc = 0;
2519         /* Assume that the hardware is in the high speed state.  This
2520          * should be the default.
2521          */
2522         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2523         case GC_CLOCK_133_200:
2524         case GC_CLOCK_100_200:
2525                 return 200000;
2526         case GC_CLOCK_166_250:
2527                 return 250000;
2528         case GC_CLOCK_100_133:
2529                 return 133000;
2530         }
2531
2532         /* Shouldn't happen */
2533         return 0;
2534 }
2535
2536 static int i830_get_display_clock_speed(struct drm_device *dev)
2537 {
2538         return 133000;
2539 }
2540
2541 /**
2542  * Return the pipe currently connected to the panel fitter,
2543  * or -1 if the panel fitter is not present or not in use
2544  */
2545 int intel_panel_fitter_pipe (struct drm_device *dev)
2546 {
2547         struct drm_i915_private *dev_priv = dev->dev_private;
2548         u32  pfit_control;
2549
2550         /* i830 doesn't have a panel fitter */
2551         if (IS_I830(dev))
2552                 return -1;
2553
2554         pfit_control = I915_READ(PFIT_CONTROL);
2555
2556         /* See if the panel fitter is in use */
2557         if ((pfit_control & PFIT_ENABLE) == 0)
2558                 return -1;
2559
2560         /* 965 can place panel fitter on either pipe */
2561         if (IS_I965G(dev))
2562                 return (pfit_control >> 29) & 0x3;
2563
2564         /* older chips can only use pipe 1 */
2565         return 1;
2566 }
2567
2568 struct fdi_m_n {
2569         u32        tu;
2570         u32        gmch_m;
2571         u32        gmch_n;
2572         u32        link_m;
2573         u32        link_n;
2574 };
2575
2576 static void
2577 fdi_reduce_ratio(u32 *num, u32 *den)
2578 {
2579         while (*num > 0xffffff || *den > 0xffffff) {
2580                 *num >>= 1;
2581                 *den >>= 1;
2582         }
2583 }
2584
2585 #define DATA_N 0x800000
2586 #define LINK_N 0x80000
2587
2588 static void
2589 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2590                      int link_clock, struct fdi_m_n *m_n)
2591 {
2592         u64 temp;
2593
2594         m_n->tu = 64; /* default size */
2595
2596         temp = (u64) DATA_N * pixel_clock;
2597         temp = div_u64(temp, link_clock);
2598         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2599         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2600         m_n->gmch_n = DATA_N;
2601         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2602
2603         temp = (u64) LINK_N * pixel_clock;
2604         m_n->link_m = div_u64(temp, link_clock);
2605         m_n->link_n = LINK_N;
2606         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2607 }
2608
2609
2610 struct intel_watermark_params {
2611         unsigned long fifo_size;
2612         unsigned long max_wm;
2613         unsigned long default_wm;
2614         unsigned long guard_size;
2615         unsigned long cacheline_size;
2616 };
2617
2618 /* Pineview has different values for various configs */
2619 static struct intel_watermark_params pineview_display_wm = {
2620         PINEVIEW_DISPLAY_FIFO,
2621         PINEVIEW_MAX_WM,
2622         PINEVIEW_DFT_WM,
2623         PINEVIEW_GUARD_WM,
2624         PINEVIEW_FIFO_LINE_SIZE
2625 };
2626 static struct intel_watermark_params pineview_display_hplloff_wm = {
2627         PINEVIEW_DISPLAY_FIFO,
2628         PINEVIEW_MAX_WM,
2629         PINEVIEW_DFT_HPLLOFF_WM,
2630         PINEVIEW_GUARD_WM,
2631         PINEVIEW_FIFO_LINE_SIZE
2632 };
2633 static struct intel_watermark_params pineview_cursor_wm = {
2634         PINEVIEW_CURSOR_FIFO,
2635         PINEVIEW_CURSOR_MAX_WM,
2636         PINEVIEW_CURSOR_DFT_WM,
2637         PINEVIEW_CURSOR_GUARD_WM,
2638         PINEVIEW_FIFO_LINE_SIZE,
2639 };
2640 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2641         PINEVIEW_CURSOR_FIFO,
2642         PINEVIEW_CURSOR_MAX_WM,
2643         PINEVIEW_CURSOR_DFT_WM,
2644         PINEVIEW_CURSOR_GUARD_WM,
2645         PINEVIEW_FIFO_LINE_SIZE
2646 };
2647 static struct intel_watermark_params g4x_wm_info = {
2648         G4X_FIFO_SIZE,
2649         G4X_MAX_WM,
2650         G4X_MAX_WM,
2651         2,
2652         G4X_FIFO_LINE_SIZE,
2653 };
2654 static struct intel_watermark_params i945_wm_info = {
2655         I945_FIFO_SIZE,
2656         I915_MAX_WM,
2657         1,
2658         2,
2659         I915_FIFO_LINE_SIZE
2660 };
2661 static struct intel_watermark_params i915_wm_info = {
2662         I915_FIFO_SIZE,
2663         I915_MAX_WM,
2664         1,
2665         2,
2666         I915_FIFO_LINE_SIZE
2667 };
2668 static struct intel_watermark_params i855_wm_info = {
2669         I855GM_FIFO_SIZE,
2670         I915_MAX_WM,
2671         1,
2672         2,
2673         I830_FIFO_LINE_SIZE
2674 };
2675 static struct intel_watermark_params i830_wm_info = {
2676         I830_FIFO_SIZE,
2677         I915_MAX_WM,
2678         1,
2679         2,
2680         I830_FIFO_LINE_SIZE
2681 };
2682
2683 static struct intel_watermark_params ironlake_display_wm_info = {
2684         ILK_DISPLAY_FIFO,
2685         ILK_DISPLAY_MAXWM,
2686         ILK_DISPLAY_DFTWM,
2687         2,
2688         ILK_FIFO_LINE_SIZE
2689 };
2690
2691 static struct intel_watermark_params ironlake_display_srwm_info = {
2692         ILK_DISPLAY_SR_FIFO,
2693         ILK_DISPLAY_MAX_SRWM,
2694         ILK_DISPLAY_DFT_SRWM,
2695         2,
2696         ILK_FIFO_LINE_SIZE
2697 };
2698
2699 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2700         ILK_CURSOR_SR_FIFO,
2701         ILK_CURSOR_MAX_SRWM,
2702         ILK_CURSOR_DFT_SRWM,
2703         2,
2704         ILK_FIFO_LINE_SIZE
2705 };
2706
2707 /**
2708  * intel_calculate_wm - calculate watermark level
2709  * @clock_in_khz: pixel clock
2710  * @wm: chip FIFO params
2711  * @pixel_size: display pixel size
2712  * @latency_ns: memory latency for the platform
2713  *
2714  * Calculate the watermark level (the level at which the display plane will
2715  * start fetching from memory again).  Each chip has a different display
2716  * FIFO size and allocation, so the caller needs to figure that out and pass
2717  * in the correct intel_watermark_params structure.
2718  *
2719  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2720  * on the pixel size.  When it reaches the watermark level, it'll start
2721  * fetching FIFO line sized based chunks from memory until the FIFO fills
2722  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2723  * will occur, and a display engine hang could result.
2724  */
2725 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2726                                         struct intel_watermark_params *wm,
2727                                         int pixel_size,
2728                                         unsigned long latency_ns)
2729 {
2730         long entries_required, wm_size;
2731
2732         /*
2733          * Note: we need to make sure we don't overflow for various clock &
2734          * latency values.
2735          * clocks go from a few thousand to several hundred thousand.
2736          * latency is usually a few thousand
2737          */
2738         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2739                 1000;
2740         entries_required /= wm->cacheline_size;
2741
2742         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2743
2744         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2745
2746         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2747
2748         /* Don't promote wm_size to unsigned... */
2749         if (wm_size > (long)wm->max_wm)
2750                 wm_size = wm->max_wm;
2751         if (wm_size <= 0)
2752                 wm_size = wm->default_wm;
2753         return wm_size;
2754 }
2755
2756 struct cxsr_latency {
2757         int is_desktop;
2758         int is_ddr3;
2759         unsigned long fsb_freq;
2760         unsigned long mem_freq;
2761         unsigned long display_sr;
2762         unsigned long display_hpll_disable;
2763         unsigned long cursor_sr;
2764         unsigned long cursor_hpll_disable;
2765 };
2766
2767 static struct cxsr_latency cxsr_latency_table[] = {
2768         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2769         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2770         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2771         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2772         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2773
2774         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2775         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2776         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2777         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2778         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2779
2780         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2781         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2782         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2783         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2784         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2785
2786         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2787         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2788         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2789         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2790         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2791
2792         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2793         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2794         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2795         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2796         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2797
2798         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2799         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2800         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2801         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2802         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2803 };
2804
2805 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2806                                                    int fsb, int mem)
2807 {
2808         int i;
2809         struct cxsr_latency *latency;
2810
2811         if (fsb == 0 || mem == 0)
2812                 return NULL;
2813
2814         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2815                 latency = &cxsr_latency_table[i];
2816                 if (is_desktop == latency->is_desktop &&
2817                     is_ddr3 == latency->is_ddr3 &&
2818                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2819                         return latency;
2820         }
2821
2822         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2823
2824         return NULL;
2825 }
2826
2827 static void pineview_disable_cxsr(struct drm_device *dev)
2828 {
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         u32 reg;
2831
2832         /* deactivate cxsr */
2833         reg = I915_READ(DSPFW3);
2834         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2835         I915_WRITE(DSPFW3, reg);
2836         DRM_INFO("Big FIFO is disabled\n");
2837 }
2838
2839 /*
2840  * Latency for FIFO fetches is dependent on several factors:
2841  *   - memory configuration (speed, channels)
2842  *   - chipset
2843  *   - current MCH state
2844  * It can be fairly high in some situations, so here we assume a fairly
2845  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2846  * set this value too high, the FIFO will fetch frequently to stay full)
2847  * and power consumption (set it too low to save power and we might see
2848  * FIFO underruns and display "flicker").
2849  *
2850  * A value of 5us seems to be a good balance; safe for very low end
2851  * platforms but not overly aggressive on lower latency configs.
2852  */
2853 static const int latency_ns = 5000;
2854
2855 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2856 {
2857         struct drm_i915_private *dev_priv = dev->dev_private;
2858         uint32_t dsparb = I915_READ(DSPARB);
2859         int size;
2860
2861         if (plane == 0)
2862                 size = dsparb & 0x7f;
2863         else
2864                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2865                         (dsparb & 0x7f);
2866
2867         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2868                         plane ? "B" : "A", size);
2869
2870         return size;
2871 }
2872
2873 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2874 {
2875         struct drm_i915_private *dev_priv = dev->dev_private;
2876         uint32_t dsparb = I915_READ(DSPARB);
2877         int size;
2878
2879         if (plane == 0)
2880                 size = dsparb & 0x1ff;
2881         else
2882                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2883                         (dsparb & 0x1ff);
2884         size >>= 1; /* Convert to cachelines */
2885
2886         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2887                         plane ? "B" : "A", size);
2888
2889         return size;
2890 }
2891
2892 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2893 {
2894         struct drm_i915_private *dev_priv = dev->dev_private;
2895         uint32_t dsparb = I915_READ(DSPARB);
2896         int size;
2897
2898         size = dsparb & 0x7f;
2899         size >>= 2; /* Convert to cachelines */
2900
2901         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2902                         plane ? "B" : "A",
2903                   size);
2904
2905         return size;
2906 }
2907
2908 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2909 {
2910         struct drm_i915_private *dev_priv = dev->dev_private;
2911         uint32_t dsparb = I915_READ(DSPARB);
2912         int size;
2913
2914         size = dsparb & 0x7f;
2915         size >>= 1; /* Convert to cachelines */
2916
2917         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2918                         plane ? "B" : "A", size);
2919
2920         return size;
2921 }
2922
2923 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2924                           int planeb_clock, int sr_hdisplay, int pixel_size)
2925 {
2926         struct drm_i915_private *dev_priv = dev->dev_private;
2927         u32 reg;
2928         unsigned long wm;
2929         struct cxsr_latency *latency;
2930         int sr_clock;
2931
2932         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2933                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2934         if (!latency) {
2935                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2936                 pineview_disable_cxsr(dev);
2937                 return;
2938         }
2939
2940         if (!planea_clock || !planeb_clock) {
2941                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2942
2943                 /* Display SR */
2944                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2945                                         pixel_size, latency->display_sr);
2946                 reg = I915_READ(DSPFW1);
2947                 reg &= ~DSPFW_SR_MASK;
2948                 reg |= wm << DSPFW_SR_SHIFT;
2949                 I915_WRITE(DSPFW1, reg);
2950                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2951
2952                 /* cursor SR */
2953                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2954                                         pixel_size, latency->cursor_sr);
2955                 reg = I915_READ(DSPFW3);
2956                 reg &= ~DSPFW_CURSOR_SR_MASK;
2957                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2958                 I915_WRITE(DSPFW3, reg);
2959
2960                 /* Display HPLL off SR */
2961                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2962                                         pixel_size, latency->display_hpll_disable);
2963                 reg = I915_READ(DSPFW3);
2964                 reg &= ~DSPFW_HPLL_SR_MASK;
2965                 reg |= wm & DSPFW_HPLL_SR_MASK;
2966                 I915_WRITE(DSPFW3, reg);
2967
2968                 /* cursor HPLL off SR */
2969                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2970                                         pixel_size, latency->cursor_hpll_disable);
2971                 reg = I915_READ(DSPFW3);
2972                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2973                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2974                 I915_WRITE(DSPFW3, reg);
2975                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2976
2977                 /* activate cxsr */
2978                 reg = I915_READ(DSPFW3);
2979                 reg |= PINEVIEW_SELF_REFRESH_EN;
2980                 I915_WRITE(DSPFW3, reg);
2981                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2982         } else {
2983                 pineview_disable_cxsr(dev);
2984                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2985         }
2986 }
2987
2988 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2989                           int planeb_clock, int sr_hdisplay, int pixel_size)
2990 {
2991         struct drm_i915_private *dev_priv = dev->dev_private;
2992         int total_size, cacheline_size;
2993         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2994         struct intel_watermark_params planea_params, planeb_params;
2995         unsigned long line_time_us;
2996         int sr_clock, sr_entries = 0, entries_required;
2997
2998         /* Create copies of the base settings for each pipe */
2999         planea_params = planeb_params = g4x_wm_info;
3000
3001         /* Grab a couple of global values before we overwrite them */
3002         total_size = planea_params.fifo_size;
3003         cacheline_size = planea_params.cacheline_size;
3004
3005         /*
3006          * Note: we need to make sure we don't overflow for various clock &
3007          * latency values.
3008          * clocks go from a few thousand to several hundred thousand.
3009          * latency is usually a few thousand
3010          */
3011         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3012                 1000;
3013         entries_required /= G4X_FIFO_LINE_SIZE;
3014         planea_wm = entries_required + planea_params.guard_size;
3015
3016         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3017                 1000;
3018         entries_required /= G4X_FIFO_LINE_SIZE;
3019         planeb_wm = entries_required + planeb_params.guard_size;
3020
3021         cursora_wm = cursorb_wm = 16;
3022         cursor_sr = 32;
3023
3024         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3025
3026         /* Calc sr entries for one plane configs */
3027         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3028                 /* self-refresh has much higher latency */
3029                 static const int sr_latency_ns = 12000;
3030
3031                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3032                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3033
3034                 /* Use ns/us then divide to preserve precision */
3035                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3036                               pixel_size * sr_hdisplay) / 1000;
3037                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3038                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3039                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3040         } else {
3041                 /* Turn off self refresh if both pipes are enabled */
3042                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3043                                         & ~FW_BLC_SELF_EN);
3044         }
3045
3046         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3047                   planea_wm, planeb_wm, sr_entries);
3048
3049         planea_wm &= 0x3f;
3050         planeb_wm &= 0x3f;
3051
3052         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3053                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3054                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3055         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3056                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3057         /* HPLL off in SR has some issues on G4x... disable it */
3058         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3059                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3060 }
3061
3062 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3063                            int planeb_clock, int sr_hdisplay, int pixel_size)
3064 {
3065         struct drm_i915_private *dev_priv = dev->dev_private;
3066         unsigned long line_time_us;
3067         int sr_clock, sr_entries, srwm = 1;
3068
3069         /* Calc sr entries for one plane configs */
3070         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3071                 /* self-refresh has much higher latency */
3072                 static const int sr_latency_ns = 12000;
3073
3074                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3075                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3076
3077                 /* Use ns/us then divide to preserve precision */
3078                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3079                               pixel_size * sr_hdisplay) / 1000;
3080                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
3081                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3082                 srwm = I945_FIFO_SIZE - sr_entries;
3083                 if (srwm < 0)
3084                         srwm = 1;
3085                 srwm &= 0x3f;
3086                 if (IS_I965GM(dev))
3087                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3088         } else {
3089                 /* Turn off self refresh if both pipes are enabled */
3090                 if (IS_I965GM(dev))
3091                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3092                                    & ~FW_BLC_SELF_EN);
3093         }
3094
3095         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3096                       srwm);
3097
3098         /* 965 has limitations... */
3099         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3100                    (8 << 0));
3101         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3102 }
3103
3104 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3105                            int planeb_clock, int sr_hdisplay, int pixel_size)
3106 {
3107         struct drm_i915_private *dev_priv = dev->dev_private;
3108         uint32_t fwater_lo;
3109         uint32_t fwater_hi;
3110         int total_size, cacheline_size, cwm, srwm = 1;
3111         int planea_wm, planeb_wm;
3112         struct intel_watermark_params planea_params, planeb_params;
3113         unsigned long line_time_us;
3114         int sr_clock, sr_entries = 0;
3115
3116         /* Create copies of the base settings for each pipe */
3117         if (IS_I965GM(dev) || IS_I945GM(dev))
3118                 planea_params = planeb_params = i945_wm_info;
3119         else if (IS_I9XX(dev))
3120                 planea_params = planeb_params = i915_wm_info;
3121         else
3122                 planea_params = planeb_params = i855_wm_info;
3123
3124         /* Grab a couple of global values before we overwrite them */
3125         total_size = planea_params.fifo_size;
3126         cacheline_size = planea_params.cacheline_size;
3127
3128         /* Update per-plane FIFO sizes */
3129         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3130         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3131
3132         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3133                                        pixel_size, latency_ns);
3134         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3135                                        pixel_size, latency_ns);
3136         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3137
3138         /*
3139          * Overlay gets an aggressive default since video jitter is bad.
3140          */
3141         cwm = 2;
3142
3143         /* Calc sr entries for one plane configs */
3144         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3145             (!planea_clock || !planeb_clock)) {
3146                 /* self-refresh has much higher latency */
3147                 static const int sr_latency_ns = 6000;
3148
3149                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3150                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3151
3152                 /* Use ns/us then divide to preserve precision */
3153                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3154                               pixel_size * sr_hdisplay) / 1000;
3155                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3156                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3157                 srwm = total_size - sr_entries;
3158                 if (srwm < 0)
3159                         srwm = 1;
3160
3161                 if (IS_I945G(dev) || IS_I945GM(dev))
3162                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3163                 else if (IS_I915GM(dev)) {
3164                         /* 915M has a smaller SRWM field */
3165                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3166                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3167                 }
3168         } else {
3169                 /* Turn off self refresh if both pipes are enabled */
3170                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3171                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3172                                    & ~FW_BLC_SELF_EN);
3173                 } else if (IS_I915GM(dev)) {
3174                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3175                 }
3176         }
3177
3178         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3179                   planea_wm, planeb_wm, cwm, srwm);
3180
3181         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3182         fwater_hi = (cwm & 0x1f);
3183
3184         /* Set request length to 8 cachelines per fetch */
3185         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3186         fwater_hi = fwater_hi | (1 << 8);
3187
3188         I915_WRITE(FW_BLC, fwater_lo);
3189         I915_WRITE(FW_BLC2, fwater_hi);
3190 }
3191
3192 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3193                            int unused2, int pixel_size)
3194 {
3195         struct drm_i915_private *dev_priv = dev->dev_private;
3196         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3197         int planea_wm;
3198
3199         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3200
3201         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3202                                        pixel_size, latency_ns);
3203         fwater_lo |= (3<<8) | planea_wm;
3204
3205         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3206
3207         I915_WRITE(FW_BLC, fwater_lo);
3208 }
3209
3210 #define ILK_LP0_PLANE_LATENCY           700
3211
3212 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3213                        int planeb_clock, int sr_hdisplay, int pixel_size)
3214 {
3215         struct drm_i915_private *dev_priv = dev->dev_private;
3216         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3217         int sr_wm, cursor_wm;
3218         unsigned long line_time_us;
3219         int sr_clock, entries_required;
3220         u32 reg_value;
3221
3222         /* Calculate and update the watermark for plane A */
3223         if (planea_clock) {
3224                 entries_required = ((planea_clock / 1000) * pixel_size *
3225                                      ILK_LP0_PLANE_LATENCY) / 1000;
3226                 entries_required = DIV_ROUND_UP(entries_required,
3227                                    ironlake_display_wm_info.cacheline_size);
3228                 planea_wm = entries_required +
3229                             ironlake_display_wm_info.guard_size;
3230
3231                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3232                         planea_wm = ironlake_display_wm_info.max_wm;
3233
3234                 cursora_wm = 16;
3235                 reg_value = I915_READ(WM0_PIPEA_ILK);
3236                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3237                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3238                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3239                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3240                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3241                                 "cursor: %d\n", planea_wm, cursora_wm);
3242         }
3243         /* Calculate and update the watermark for plane B */
3244         if (planeb_clock) {
3245                 entries_required = ((planeb_clock / 1000) * pixel_size *
3246                                      ILK_LP0_PLANE_LATENCY) / 1000;
3247                 entries_required = DIV_ROUND_UP(entries_required,
3248                                    ironlake_display_wm_info.cacheline_size);
3249                 planeb_wm = entries_required +
3250                             ironlake_display_wm_info.guard_size;
3251
3252                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3253                         planeb_wm = ironlake_display_wm_info.max_wm;
3254
3255                 cursorb_wm = 16;
3256                 reg_value = I915_READ(WM0_PIPEB_ILK);
3257                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3258                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3259                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3260                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3261                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3262                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3263         }
3264
3265         /*
3266          * Calculate and update the self-refresh watermark only when one
3267          * display plane is used.
3268          */
3269         if (!planea_clock || !planeb_clock) {
3270                 int line_count;
3271                 /* Read the self-refresh latency. The unit is 0.5us */
3272                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3273
3274                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3275                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3276
3277                 /* Use ns/us then divide to preserve precision */
3278                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3279                                / 1000;
3280
3281                 /* calculate the self-refresh watermark for display plane */
3282                 entries_required = line_count * sr_hdisplay * pixel_size;
3283                 entries_required = DIV_ROUND_UP(entries_required,
3284                                    ironlake_display_srwm_info.cacheline_size);
3285                 sr_wm = entries_required +
3286                         ironlake_display_srwm_info.guard_size;
3287
3288                 /* calculate the self-refresh watermark for display cursor */
3289                 entries_required = line_count * pixel_size * 64;
3290                 entries_required = DIV_ROUND_UP(entries_required,
3291                                    ironlake_cursor_srwm_info.cacheline_size);
3292                 cursor_wm = entries_required +
3293                             ironlake_cursor_srwm_info.guard_size;
3294
3295                 /* configure watermark and enable self-refresh */
3296                 reg_value = I915_READ(WM1_LP_ILK);
3297                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3298                                WM1_LP_CURSOR_MASK);
3299                 reg_value |= WM1_LP_SR_EN |
3300                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3301                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3302
3303                 I915_WRITE(WM1_LP_ILK, reg_value);
3304                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3305                                 "cursor %d\n", sr_wm, cursor_wm);
3306
3307         } else {
3308                 /* Turn off self refresh if both pipes are enabled */
3309                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3310         }
3311 }
3312 /**
3313  * intel_update_watermarks - update FIFO watermark values based on current modes
3314  *
3315  * Calculate watermark values for the various WM regs based on current mode
3316  * and plane configuration.
3317  *
3318  * There are several cases to deal with here:
3319  *   - normal (i.e. non-self-refresh)
3320  *   - self-refresh (SR) mode
3321  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3322  *   - lines are small relative to FIFO size (buffer can hold more than 2
3323  *     lines), so need to account for TLB latency
3324  *
3325  *   The normal calculation is:
3326  *     watermark = dotclock * bytes per pixel * latency
3327  *   where latency is platform & configuration dependent (we assume pessimal
3328  *   values here).
3329  *
3330  *   The SR calculation is:
3331  *     watermark = (trunc(latency/line time)+1) * surface width *
3332  *       bytes per pixel
3333  *   where
3334  *     line time = htotal / dotclock
3335  *   and latency is assumed to be high, as above.
3336  *
3337  * The final value programmed to the register should always be rounded up,
3338  * and include an extra 2 entries to account for clock crossings.
3339  *
3340  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3341  * to set the non-SR watermarks to 8.
3342   */
3343 static void intel_update_watermarks(struct drm_device *dev)
3344 {
3345         struct drm_i915_private *dev_priv = dev->dev_private;
3346         struct drm_crtc *crtc;
3347         struct intel_crtc *intel_crtc;
3348         int sr_hdisplay = 0;
3349         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3350         int enabled = 0, pixel_size = 0;
3351
3352         if (!dev_priv->display.update_wm)
3353                 return;
3354
3355         /* Get the clock config from both planes */
3356         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3357                 intel_crtc = to_intel_crtc(crtc);
3358                 if (crtc->enabled) {
3359                         enabled++;
3360                         if (intel_crtc->plane == 0) {
3361                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3362                                           intel_crtc->pipe, crtc->mode.clock);
3363                                 planea_clock = crtc->mode.clock;
3364                         } else {
3365                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3366                                           intel_crtc->pipe, crtc->mode.clock);
3367                                 planeb_clock = crtc->mode.clock;
3368                         }
3369                         sr_hdisplay = crtc->mode.hdisplay;
3370                         sr_clock = crtc->mode.clock;
3371                         if (crtc->fb)
3372                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3373                         else
3374                                 pixel_size = 4; /* by default */
3375                 }
3376         }
3377
3378         if (enabled <= 0)
3379                 return;
3380
3381         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3382                                     sr_hdisplay, pixel_size);
3383 }
3384
3385 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3386                                struct drm_display_mode *mode,
3387                                struct drm_display_mode *adjusted_mode,
3388                                int x, int y,
3389                                struct drm_framebuffer *old_fb)
3390 {
3391         struct drm_device *dev = crtc->dev;
3392         struct drm_i915_private *dev_priv = dev->dev_private;
3393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3394         int pipe = intel_crtc->pipe;
3395         int plane = intel_crtc->plane;
3396         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3397         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3398         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3399         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3400         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3401         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3402         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3403         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3404         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3405         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3406         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3407         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3408         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3409         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3410         int refclk, num_connectors = 0;
3411         intel_clock_t clock, reduced_clock;
3412         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3413         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3414         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3415         bool is_edp = false;
3416         struct drm_mode_config *mode_config = &dev->mode_config;
3417         struct drm_encoder *encoder;
3418         struct intel_encoder *intel_encoder = NULL;
3419         const intel_limit_t *limit;
3420         int ret;
3421         struct fdi_m_n m_n = {0};
3422         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3423         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3424         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3425         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3426         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3427         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3428         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3429         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3430         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3431         int lvds_reg = LVDS;
3432         u32 temp;
3433         int sdvo_pixel_multiply;
3434         int target_clock;
3435
3436         drm_vblank_pre_modeset(dev, pipe);
3437
3438         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3439
3440                 if (!encoder || encoder->crtc != crtc)
3441                         continue;
3442
3443                 intel_encoder = enc_to_intel_encoder(encoder);
3444
3445                 switch (intel_encoder->type) {
3446                 case INTEL_OUTPUT_LVDS:
3447                         is_lvds = true;
3448                         break;
3449                 case INTEL_OUTPUT_SDVO:
3450                 case INTEL_OUTPUT_HDMI:
3451                         is_sdvo = true;
3452                         if (intel_encoder->needs_tv_clock)
3453                                 is_tv = true;
3454                         break;
3455                 case INTEL_OUTPUT_DVO:
3456                         is_dvo = true;
3457                         break;
3458                 case INTEL_OUTPUT_TVOUT:
3459                         is_tv = true;
3460                         break;
3461                 case INTEL_OUTPUT_ANALOG:
3462                         is_crt = true;
3463                         break;
3464                 case INTEL_OUTPUT_DISPLAYPORT:
3465                         is_dp = true;
3466                         break;
3467                 case INTEL_OUTPUT_EDP:
3468                         is_edp = true;
3469                         break;
3470                 }
3471
3472                 num_connectors++;
3473         }
3474
3475         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3476                 refclk = dev_priv->lvds_ssc_freq * 1000;
3477                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3478                                         refclk / 1000);
3479         } else if (IS_I9XX(dev)) {
3480                 refclk = 96000;
3481                 if (HAS_PCH_SPLIT(dev))
3482                         refclk = 120000; /* 120Mhz refclk */
3483         } else {
3484                 refclk = 48000;
3485         }
3486
3487
3488         /*
3489          * Returns a set of divisors for the desired target clock with the given
3490          * refclk, or FALSE.  The returned values represent the clock equation:
3491          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3492          */
3493         limit = intel_limit(crtc);
3494         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3495         if (!ok) {
3496                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3497                 drm_vblank_post_modeset(dev, pipe);
3498                 return -EINVAL;
3499         }
3500
3501         if (is_lvds && dev_priv->lvds_downclock_avail) {
3502                 has_reduced_clock = limit->find_pll(limit, crtc,
3503                                                             dev_priv->lvds_downclock,
3504                                                             refclk,
3505                                                             &reduced_clock);
3506                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3507                         /*
3508                          * If the different P is found, it means that we can't
3509                          * switch the display clock by using the FP0/FP1.
3510                          * In such case we will disable the LVDS downclock
3511                          * feature.
3512                          */
3513                         DRM_DEBUG_KMS("Different P is found for "
3514                                                 "LVDS clock/downclock\n");
3515                         has_reduced_clock = 0;
3516                 }
3517         }
3518         /* SDVO TV has fixed PLL values depend on its clock range,
3519            this mirrors vbios setting. */
3520         if (is_sdvo && is_tv) {
3521                 if (adjusted_mode->clock >= 100000
3522                                 && adjusted_mode->clock < 140500) {
3523                         clock.p1 = 2;
3524                         clock.p2 = 10;
3525                         clock.n = 3;
3526                         clock.m1 = 16;
3527                         clock.m2 = 8;
3528                 } else if (adjusted_mode->clock >= 140500
3529                                 && adjusted_mode->clock <= 200000) {
3530                         clock.p1 = 1;
3531                         clock.p2 = 10;
3532                         clock.n = 6;
3533                         clock.m1 = 12;
3534                         clock.m2 = 8;
3535                 }
3536         }
3537
3538         /* FDI link */
3539         if (HAS_PCH_SPLIT(dev)) {
3540                 int lane = 0, link_bw, bpp;
3541                 /* eDP doesn't require FDI link, so just set DP M/N
3542                    according to current link config */
3543                 if (is_edp) {
3544                         target_clock = mode->clock;
3545                         intel_edp_link_config(intel_encoder,
3546                                         &lane, &link_bw);
3547                 } else {
3548                         /* DP over FDI requires target mode clock
3549                            instead of link clock */
3550                         if (is_dp)
3551                                 target_clock = mode->clock;
3552                         else
3553                                 target_clock = adjusted_mode->clock;
3554                         link_bw = 270000;
3555                 }
3556
3557                 /* determine panel color depth */
3558                 temp = I915_READ(pipeconf_reg);
3559                 temp &= ~PIPE_BPC_MASK;
3560                 if (is_lvds) {
3561                         int lvds_reg = I915_READ(PCH_LVDS);
3562                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3563                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3564                                 temp |= PIPE_8BPC;
3565                         else
3566                                 temp |= PIPE_6BPC;
3567                 } else if (is_edp) {
3568                         switch (dev_priv->edp_bpp/3) {
3569                         case 8:
3570                                 temp |= PIPE_8BPC;
3571                                 break;
3572                         case 10:
3573                                 temp |= PIPE_10BPC;
3574                                 break;
3575                         case 6:
3576                                 temp |= PIPE_6BPC;
3577                                 break;
3578                         case 12:
3579                                 temp |= PIPE_12BPC;
3580                                 break;
3581                         }
3582                 } else
3583                         temp |= PIPE_8BPC;
3584                 I915_WRITE(pipeconf_reg, temp);
3585                 I915_READ(pipeconf_reg);
3586
3587                 switch (temp & PIPE_BPC_MASK) {
3588                 case PIPE_8BPC:
3589                         bpp = 24;
3590                         break;
3591                 case PIPE_10BPC:
3592                         bpp = 30;
3593                         break;
3594                 case PIPE_6BPC:
3595                         bpp = 18;
3596                         break;
3597                 case PIPE_12BPC:
3598                         bpp = 36;
3599                         break;
3600                 default:
3601                         DRM_ERROR("unknown pipe bpc value\n");
3602                         bpp = 24;
3603                 }
3604
3605                 if (!lane) {
3606                         /*
3607                          * Account for spread spectrum to avoid
3608                          * oversubscribing the link. Max center spread
3609                          * is 2.5%; use 5% for safety's sake.
3610                          */
3611                         u32 bps = target_clock * bpp * 21 / 20;
3612                         lane = bps / (link_bw * 8) + 1;
3613                 }
3614
3615                 intel_crtc->fdi_lanes = lane;
3616
3617                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3618         }
3619
3620         /* Ironlake: try to setup display ref clock before DPLL
3621          * enabling. This is only under driver's control after
3622          * PCH B stepping, previous chipset stepping should be
3623          * ignoring this setting.
3624          */
3625         if (HAS_PCH_SPLIT(dev)) {
3626                 temp = I915_READ(PCH_DREF_CONTROL);
3627                 /* Always enable nonspread source */
3628                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3629                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3630                 I915_WRITE(PCH_DREF_CONTROL, temp);
3631                 POSTING_READ(PCH_DREF_CONTROL);
3632
3633                 temp &= ~DREF_SSC_SOURCE_MASK;
3634                 temp |= DREF_SSC_SOURCE_ENABLE;
3635                 I915_WRITE(PCH_DREF_CONTROL, temp);
3636                 POSTING_READ(PCH_DREF_CONTROL);
3637
3638                 udelay(200);
3639
3640                 if (is_edp) {
3641                         if (dev_priv->lvds_use_ssc) {
3642                                 temp |= DREF_SSC1_ENABLE;
3643                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3644                                 POSTING_READ(PCH_DREF_CONTROL);
3645
3646                                 udelay(200);
3647
3648                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3649                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3650                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3651                                 POSTING_READ(PCH_DREF_CONTROL);
3652                         } else {
3653                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3654                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3655                                 POSTING_READ(PCH_DREF_CONTROL);
3656                         }
3657                 }
3658         }
3659
3660         if (IS_PINEVIEW(dev)) {
3661                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3662                 if (has_reduced_clock)
3663                         fp2 = (1 << reduced_clock.n) << 16 |
3664                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3665         } else {
3666                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3667                 if (has_reduced_clock)
3668                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3669                                 reduced_clock.m2;
3670         }
3671
3672         if (!HAS_PCH_SPLIT(dev))
3673                 dpll = DPLL_VGA_MODE_DIS;
3674
3675         if (IS_I9XX(dev)) {
3676                 if (is_lvds)
3677                         dpll |= DPLLB_MODE_LVDS;
3678                 else
3679                         dpll |= DPLLB_MODE_DAC_SERIAL;
3680                 if (is_sdvo) {
3681                         dpll |= DPLL_DVO_HIGH_SPEED;
3682                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3683                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3684                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3685                         else if (HAS_PCH_SPLIT(dev))
3686                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3687                 }
3688                 if (is_dp)
3689                         dpll |= DPLL_DVO_HIGH_SPEED;
3690
3691                 /* compute bitmask from p1 value */
3692                 if (IS_PINEVIEW(dev))
3693                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3694                 else {
3695                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3696                         /* also FPA1 */
3697                         if (HAS_PCH_SPLIT(dev))
3698                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3699                         if (IS_G4X(dev) && has_reduced_clock)
3700                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3701                 }
3702                 switch (clock.p2) {
3703                 case 5:
3704                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3705                         break;
3706                 case 7:
3707                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3708                         break;
3709                 case 10:
3710                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3711                         break;
3712                 case 14:
3713                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3714                         break;
3715                 }
3716                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3717                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3718         } else {
3719                 if (is_lvds) {
3720                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3721                 } else {
3722                         if (clock.p1 == 2)
3723                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3724                         else
3725                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3726                         if (clock.p2 == 4)
3727                                 dpll |= PLL_P2_DIVIDE_BY_4;
3728                 }
3729         }
3730
3731         if (is_sdvo && is_tv)
3732                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3733         else if (is_tv)
3734                 /* XXX: just matching BIOS for now */
3735                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3736                 dpll |= 3;
3737         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3738                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3739         else
3740                 dpll |= PLL_REF_INPUT_DREFCLK;
3741
3742         /* setup pipeconf */
3743         pipeconf = I915_READ(pipeconf_reg);
3744
3745         /* Set up the display plane register */
3746         dspcntr = DISPPLANE_GAMMA_ENABLE;
3747
3748         /* Ironlake's plane is forced to pipe, bit 24 is to
3749            enable color space conversion */
3750         if (!HAS_PCH_SPLIT(dev)) {
3751                 if (pipe == 0)
3752                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3753                 else
3754                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3755         }
3756
3757         if (pipe == 0 && !IS_I965G(dev)) {
3758                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3759                  * core speed.
3760                  *
3761                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3762                  * pipe == 0 check?
3763                  */
3764                 if (mode->clock >
3765                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3766                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3767                 else
3768                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3769         }
3770
3771         dspcntr |= DISPLAY_PLANE_ENABLE;
3772         pipeconf |= PIPEACONF_ENABLE;
3773         dpll |= DPLL_VCO_ENABLE;
3774
3775
3776         /* Disable the panel fitter if it was on our pipe */
3777         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3778                 I915_WRITE(PFIT_CONTROL, 0);
3779
3780         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3781         drm_mode_debug_printmodeline(mode);
3782
3783         /* assign to Ironlake registers */
3784         if (HAS_PCH_SPLIT(dev)) {
3785                 fp_reg = pch_fp_reg;
3786                 dpll_reg = pch_dpll_reg;
3787         }
3788
3789         if (is_edp) {
3790                 ironlake_disable_pll_edp(crtc);
3791         } else if ((dpll & DPLL_VCO_ENABLE)) {
3792                 I915_WRITE(fp_reg, fp);
3793                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3794                 I915_READ(dpll_reg);
3795                 udelay(150);
3796         }
3797
3798         /* enable transcoder DPLL */
3799         if (HAS_PCH_CPT(dev)) {
3800                 temp = I915_READ(PCH_DPLL_SEL);
3801                 if (trans_dpll_sel == 0)
3802                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3803                 else
3804                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3805                 I915_WRITE(PCH_DPLL_SEL, temp);
3806                 I915_READ(PCH_DPLL_SEL);
3807                 udelay(150);
3808         }
3809
3810         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3811          * This is an exception to the general rule that mode_set doesn't turn
3812          * things on.
3813          */
3814         if (is_lvds) {
3815                 u32 lvds;
3816
3817                 if (HAS_PCH_SPLIT(dev))
3818                         lvds_reg = PCH_LVDS;
3819
3820                 lvds = I915_READ(lvds_reg);
3821                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3822                 if (pipe == 1) {
3823                         if (HAS_PCH_CPT(dev))
3824                                 lvds |= PORT_TRANS_B_SEL_CPT;
3825                         else
3826                                 lvds |= LVDS_PIPEB_SELECT;
3827                 } else {
3828                         if (HAS_PCH_CPT(dev))
3829                                 lvds &= ~PORT_TRANS_SEL_MASK;
3830                         else
3831                                 lvds &= ~LVDS_PIPEB_SELECT;
3832                 }
3833                 /* set the corresponsding LVDS_BORDER bit */
3834                 lvds |= dev_priv->lvds_border_bits;
3835                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3836                  * set the DPLLs for dual-channel mode or not.
3837                  */
3838                 if (clock.p2 == 7)
3839                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3840                 else
3841                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3842
3843                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3844                  * appropriately here, but we need to look more thoroughly into how
3845                  * panels behave in the two modes.
3846                  */
3847                 /* set the dithering flag */
3848                 if (IS_I965G(dev)) {
3849                         if (dev_priv->lvds_dither) {
3850                                 if (HAS_PCH_SPLIT(dev)) {
3851                                         pipeconf |= PIPE_ENABLE_DITHER;
3852                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3853                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
3854                                 } else
3855                                         lvds |= LVDS_ENABLE_DITHER;
3856                         } else {
3857                                 if (HAS_PCH_SPLIT(dev)) {
3858                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3859                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3860                                 } else
3861                                         lvds &= ~LVDS_ENABLE_DITHER;
3862                         }
3863                 }
3864                 I915_WRITE(lvds_reg, lvds);
3865                 I915_READ(lvds_reg);
3866         }
3867         if (is_dp)
3868                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3869         else if (HAS_PCH_SPLIT(dev)) {
3870                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3871                 if (pipe == 0) {
3872                         I915_WRITE(TRANSA_DATA_M1, 0);
3873                         I915_WRITE(TRANSA_DATA_N1, 0);
3874                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3875                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3876                 } else {
3877                         I915_WRITE(TRANSB_DATA_M1, 0);
3878                         I915_WRITE(TRANSB_DATA_N1, 0);
3879                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3880                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3881                 }
3882         }
3883
3884         if (!is_edp) {
3885                 I915_WRITE(fp_reg, fp);
3886                 I915_WRITE(dpll_reg, dpll);
3887                 I915_READ(dpll_reg);
3888                 /* Wait for the clocks to stabilize. */
3889                 udelay(150);
3890
3891                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3892                         if (is_sdvo) {
3893                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3894                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3895                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3896                         } else
3897                                 I915_WRITE(dpll_md_reg, 0);
3898                 } else {
3899                         /* write it again -- the BIOS does, after all */
3900                         I915_WRITE(dpll_reg, dpll);
3901                 }
3902                 I915_READ(dpll_reg);
3903                 /* Wait for the clocks to stabilize. */
3904                 udelay(150);
3905         }
3906
3907         if (is_lvds && has_reduced_clock && i915_powersave) {
3908                 I915_WRITE(fp_reg + 4, fp2);
3909                 intel_crtc->lowfreq_avail = true;
3910                 if (HAS_PIPE_CXSR(dev)) {
3911                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3912                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3913                 }
3914         } else {
3915                 I915_WRITE(fp_reg + 4, fp);
3916                 intel_crtc->lowfreq_avail = false;
3917                 if (HAS_PIPE_CXSR(dev)) {
3918                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3919                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3920                 }
3921         }
3922
3923         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3924                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3925                 /* the chip adds 2 halflines automatically */
3926                 adjusted_mode->crtc_vdisplay -= 1;
3927                 adjusted_mode->crtc_vtotal -= 1;
3928                 adjusted_mode->crtc_vblank_start -= 1;
3929                 adjusted_mode->crtc_vblank_end -= 1;
3930                 adjusted_mode->crtc_vsync_end -= 1;
3931                 adjusted_mode->crtc_vsync_start -= 1;
3932         } else
3933                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
3934
3935         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3936                    ((adjusted_mode->crtc_htotal - 1) << 16));
3937         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3938                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3939         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3940                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3941         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3942                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3943         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3944                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3945         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3946                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3947         /* pipesrc and dspsize control the size that is scaled from, which should
3948          * always be the user's requested size.
3949          */
3950         if (!HAS_PCH_SPLIT(dev)) {
3951                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3952                                 (mode->hdisplay - 1));
3953                 I915_WRITE(dsppos_reg, 0);
3954         }
3955         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3956
3957         if (HAS_PCH_SPLIT(dev)) {
3958                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3959                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3960                 I915_WRITE(link_m1_reg, m_n.link_m);
3961                 I915_WRITE(link_n1_reg, m_n.link_n);
3962
3963                 if (is_edp) {
3964                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3965                 } else {
3966                         /* enable FDI RX PLL too */
3967                         temp = I915_READ(fdi_rx_reg);
3968                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3969                         I915_READ(fdi_rx_reg);
3970                         udelay(200);
3971
3972                         /* enable FDI TX PLL too */
3973                         temp = I915_READ(fdi_tx_reg);
3974                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3975                         I915_READ(fdi_tx_reg);
3976
3977                         /* enable FDI RX PCDCLK */
3978                         temp = I915_READ(fdi_rx_reg);
3979                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3980                         I915_READ(fdi_rx_reg);
3981                         udelay(200);
3982                 }
3983         }
3984
3985         I915_WRITE(pipeconf_reg, pipeconf);
3986         I915_READ(pipeconf_reg);
3987
3988         intel_wait_for_vblank(dev);
3989
3990         if (IS_IRONLAKE(dev)) {
3991                 /* enable address swizzle for tiling buffer */
3992                 temp = I915_READ(DISP_ARB_CTL);
3993                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3994         }
3995
3996         I915_WRITE(dspcntr_reg, dspcntr);
3997
3998         /* Flush the plane changes */
3999         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4000
4001         if ((IS_I965G(dev) || plane == 0))
4002                 intel_update_fbc(crtc, &crtc->mode);
4003
4004         intel_update_watermarks(dev);
4005
4006         drm_vblank_post_modeset(dev, pipe);
4007
4008         return ret;
4009 }
4010
4011 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4012 void intel_crtc_load_lut(struct drm_crtc *crtc)
4013 {
4014         struct drm_device *dev = crtc->dev;
4015         struct drm_i915_private *dev_priv = dev->dev_private;
4016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4017         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4018         int i;
4019
4020         /* The clocks have to be on to load the palette. */
4021         if (!crtc->enabled)
4022                 return;
4023
4024         /* use legacy palette for Ironlake */
4025         if (HAS_PCH_SPLIT(dev))
4026                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4027                                                    LGC_PALETTE_B;
4028
4029         for (i = 0; i < 256; i++) {
4030                 I915_WRITE(palreg + 4 * i,
4031                            (intel_crtc->lut_r[i] << 16) |
4032                            (intel_crtc->lut_g[i] << 8) |
4033                            intel_crtc->lut_b[i]);
4034         }
4035 }
4036
4037 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4038                                  struct drm_file *file_priv,
4039                                  uint32_t handle,
4040                                  uint32_t width, uint32_t height)
4041 {
4042         struct drm_device *dev = crtc->dev;
4043         struct drm_i915_private *dev_priv = dev->dev_private;
4044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4045         struct drm_gem_object *bo;
4046         struct drm_i915_gem_object *obj_priv;
4047         int pipe = intel_crtc->pipe;
4048         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
4049         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
4050         uint32_t temp = I915_READ(control);
4051         size_t addr;
4052         int ret;
4053
4054         DRM_DEBUG_KMS("\n");
4055
4056         /* if we want to turn off the cursor ignore width and height */
4057         if (!handle) {
4058                 DRM_DEBUG_KMS("cursor off\n");
4059                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4060                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4061                         temp |= CURSOR_MODE_DISABLE;
4062                 } else {
4063                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4064                 }
4065                 addr = 0;
4066                 bo = NULL;
4067                 mutex_lock(&dev->struct_mutex);
4068                 goto finish;
4069         }
4070
4071         /* Currently we only support 64x64 cursors */
4072         if (width != 64 || height != 64) {
4073                 DRM_ERROR("we currently only support 64x64 cursors\n");
4074                 return -EINVAL;
4075         }
4076
4077         bo = drm_gem_object_lookup(dev, file_priv, handle);
4078         if (!bo)
4079                 return -ENOENT;
4080
4081         obj_priv = to_intel_bo(bo);
4082
4083         if (bo->size < width * height * 4) {
4084                 DRM_ERROR("buffer is to small\n");
4085                 ret = -ENOMEM;
4086                 goto fail;
4087         }
4088
4089         /* we only need to pin inside GTT if cursor is non-phy */
4090         mutex_lock(&dev->struct_mutex);
4091         if (!dev_priv->info->cursor_needs_physical) {
4092                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4093                 if (ret) {
4094                         DRM_ERROR("failed to pin cursor bo\n");
4095                         goto fail_locked;
4096                 }
4097
4098                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4099                 if (ret) {
4100                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4101                         goto fail_unpin;
4102                 }
4103
4104                 addr = obj_priv->gtt_offset;
4105         } else {
4106                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4107                 if (ret) {
4108                         DRM_ERROR("failed to attach phys object\n");
4109                         goto fail_locked;
4110                 }
4111                 addr = obj_priv->phys_obj->handle->busaddr;
4112         }
4113
4114         if (!IS_I9XX(dev))
4115                 I915_WRITE(CURSIZE, (height << 12) | width);
4116
4117         /* Hooray for CUR*CNTR differences */
4118         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4119                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4120                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4121                 temp |= (pipe << 28); /* Connect to correct pipe */
4122         } else {
4123                 temp &= ~(CURSOR_FORMAT_MASK);
4124                 temp |= CURSOR_ENABLE;
4125                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4126         }
4127
4128  finish:
4129         I915_WRITE(control, temp);
4130         I915_WRITE(base, addr);
4131
4132         if (intel_crtc->cursor_bo) {
4133                 if (dev_priv->info->cursor_needs_physical) {
4134                         if (intel_crtc->cursor_bo != bo)
4135                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4136                 } else
4137                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4138                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4139         }
4140
4141         mutex_unlock(&dev->struct_mutex);
4142
4143         intel_crtc->cursor_addr = addr;
4144         intel_crtc->cursor_bo = bo;
4145
4146         return 0;
4147 fail_unpin:
4148         i915_gem_object_unpin(bo);
4149 fail_locked:
4150         mutex_unlock(&dev->struct_mutex);
4151 fail:
4152         drm_gem_object_unreference_unlocked(bo);
4153         return ret;
4154 }
4155
4156 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4157 {
4158         struct drm_device *dev = crtc->dev;
4159         struct drm_i915_private *dev_priv = dev->dev_private;
4160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4161         struct intel_framebuffer *intel_fb;
4162         int pipe = intel_crtc->pipe;
4163         uint32_t temp = 0;
4164         uint32_t adder;
4165
4166         if (crtc->fb) {
4167                 intel_fb = to_intel_framebuffer(crtc->fb);
4168                 intel_mark_busy(dev, intel_fb->obj);
4169         }
4170
4171         if (x < 0) {
4172                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4173                 x = -x;
4174         }
4175         if (y < 0) {
4176                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4177                 y = -y;
4178         }
4179
4180         temp |= x << CURSOR_X_SHIFT;
4181         temp |= y << CURSOR_Y_SHIFT;
4182
4183         adder = intel_crtc->cursor_addr;
4184         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4185         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4186
4187         return 0;
4188 }
4189
4190 /** Sets the color ramps on behalf of RandR */
4191 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4192                                  u16 blue, int regno)
4193 {
4194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4195
4196         intel_crtc->lut_r[regno] = red >> 8;
4197         intel_crtc->lut_g[regno] = green >> 8;
4198         intel_crtc->lut_b[regno] = blue >> 8;
4199 }
4200
4201 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4202                              u16 *blue, int regno)
4203 {
4204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4205
4206         *red = intel_crtc->lut_r[regno] << 8;
4207         *green = intel_crtc->lut_g[regno] << 8;
4208         *blue = intel_crtc->lut_b[regno] << 8;
4209 }
4210
4211 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4212                                  u16 *blue, uint32_t size)
4213 {
4214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4215         int i;
4216
4217         if (size != 256)
4218                 return;
4219
4220         for (i = 0; i < 256; i++) {
4221                 intel_crtc->lut_r[i] = red[i] >> 8;
4222                 intel_crtc->lut_g[i] = green[i] >> 8;
4223                 intel_crtc->lut_b[i] = blue[i] >> 8;
4224         }
4225
4226         intel_crtc_load_lut(crtc);
4227 }
4228
4229 /**
4230  * Get a pipe with a simple mode set on it for doing load-based monitor
4231  * detection.
4232  *
4233  * It will be up to the load-detect code to adjust the pipe as appropriate for
4234  * its requirements.  The pipe will be connected to no other encoders.
4235  *
4236  * Currently this code will only succeed if there is a pipe with no encoders
4237  * configured for it.  In the future, it could choose to temporarily disable
4238  * some outputs to free up a pipe for its use.
4239  *
4240  * \return crtc, or NULL if no pipes are available.
4241  */
4242
4243 /* VESA 640x480x72Hz mode to set on the pipe */
4244 static struct drm_display_mode load_detect_mode = {
4245         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4246                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4247 };
4248
4249 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4250                                             struct drm_connector *connector,
4251                                             struct drm_display_mode *mode,
4252                                             int *dpms_mode)
4253 {
4254         struct intel_crtc *intel_crtc;
4255         struct drm_crtc *possible_crtc;
4256         struct drm_crtc *supported_crtc =NULL;
4257         struct drm_encoder *encoder = &intel_encoder->enc;
4258         struct drm_crtc *crtc = NULL;
4259         struct drm_device *dev = encoder->dev;
4260         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4261         struct drm_crtc_helper_funcs *crtc_funcs;
4262         int i = -1;
4263
4264         /*
4265          * Algorithm gets a little messy:
4266          *   - if the connector already has an assigned crtc, use it (but make
4267          *     sure it's on first)
4268          *   - try to find the first unused crtc that can drive this connector,
4269          *     and use that if we find one
4270          *   - if there are no unused crtcs available, try to use the first
4271          *     one we found that supports the connector
4272          */
4273
4274         /* See if we already have a CRTC for this connector */
4275         if (encoder->crtc) {
4276                 crtc = encoder->crtc;
4277                 /* Make sure the crtc and connector are running */
4278                 intel_crtc = to_intel_crtc(crtc);
4279                 *dpms_mode = intel_crtc->dpms_mode;
4280                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4281                         crtc_funcs = crtc->helper_private;
4282                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4283                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4284                 }
4285                 return crtc;
4286         }
4287
4288         /* Find an unused one (if possible) */
4289         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4290                 i++;
4291                 if (!(encoder->possible_crtcs & (1 << i)))
4292                         continue;
4293                 if (!possible_crtc->enabled) {
4294                         crtc = possible_crtc;
4295                         break;
4296                 }
4297                 if (!supported_crtc)
4298                         supported_crtc = possible_crtc;
4299         }
4300
4301         /*
4302          * If we didn't find an unused CRTC, don't use any.
4303          */
4304         if (!crtc) {
4305                 return NULL;
4306         }
4307
4308         encoder->crtc = crtc;
4309         connector->encoder = encoder;
4310         intel_encoder->load_detect_temp = true;
4311
4312         intel_crtc = to_intel_crtc(crtc);
4313         *dpms_mode = intel_crtc->dpms_mode;
4314
4315         if (!crtc->enabled) {
4316                 if (!mode)
4317                         mode = &load_detect_mode;
4318                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4319         } else {
4320                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4321                         crtc_funcs = crtc->helper_private;
4322                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4323                 }
4324
4325                 /* Add this connector to the crtc */
4326                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4327                 encoder_funcs->commit(encoder);
4328         }
4329         /* let the connector get through one full cycle before testing */
4330         intel_wait_for_vblank(dev);
4331
4332         return crtc;
4333 }
4334
4335 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4336                                     struct drm_connector *connector, int dpms_mode)
4337 {
4338         struct drm_encoder *encoder = &intel_encoder->enc;
4339         struct drm_device *dev = encoder->dev;
4340         struct drm_crtc *crtc = encoder->crtc;
4341         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4342         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4343
4344         if (intel_encoder->load_detect_temp) {
4345                 encoder->crtc = NULL;
4346                 connector->encoder = NULL;
4347                 intel_encoder->load_detect_temp = false;
4348                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4349                 drm_helper_disable_unused_functions(dev);
4350         }
4351
4352         /* Switch crtc and encoder back off if necessary */
4353         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4354                 if (encoder->crtc == crtc)
4355                         encoder_funcs->dpms(encoder, dpms_mode);
4356                 crtc_funcs->dpms(crtc, dpms_mode);
4357         }
4358 }
4359
4360 /* Returns the clock of the currently programmed mode of the given pipe. */
4361 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4362 {
4363         struct drm_i915_private *dev_priv = dev->dev_private;
4364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4365         int pipe = intel_crtc->pipe;
4366         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4367         u32 fp;
4368         intel_clock_t clock;
4369
4370         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4371                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4372         else
4373                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4374
4375         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4376         if (IS_PINEVIEW(dev)) {
4377                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4378                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4379         } else {
4380                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4381                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4382         }
4383
4384         if (IS_I9XX(dev)) {
4385                 if (IS_PINEVIEW(dev))
4386                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4387                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4388                 else
4389                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4390                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4391
4392                 switch (dpll & DPLL_MODE_MASK) {
4393                 case DPLLB_MODE_DAC_SERIAL:
4394                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4395                                 5 : 10;
4396                         break;
4397                 case DPLLB_MODE_LVDS:
4398                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4399                                 7 : 14;
4400                         break;
4401                 default:
4402                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4403                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4404                         return 0;
4405                 }
4406
4407                 /* XXX: Handle the 100Mhz refclk */
4408                 intel_clock(dev, 96000, &clock);
4409         } else {
4410                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4411
4412                 if (is_lvds) {
4413                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4414                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4415                         clock.p2 = 14;
4416
4417                         if ((dpll & PLL_REF_INPUT_MASK) ==
4418                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4419                                 /* XXX: might not be 66MHz */
4420                                 intel_clock(dev, 66000, &clock);
4421                         } else
4422                                 intel_clock(dev, 48000, &clock);
4423                 } else {
4424                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4425                                 clock.p1 = 2;
4426                         else {
4427                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4428                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4429                         }
4430                         if (dpll & PLL_P2_DIVIDE_BY_4)
4431                                 clock.p2 = 4;
4432                         else
4433                                 clock.p2 = 2;
4434
4435                         intel_clock(dev, 48000, &clock);
4436                 }
4437         }
4438
4439         /* XXX: It would be nice to validate the clocks, but we can't reuse
4440          * i830PllIsValid() because it relies on the xf86_config connector
4441          * configuration being accurate, which it isn't necessarily.
4442          */
4443
4444         return clock.dot;
4445 }
4446
4447 /** Returns the currently programmed mode of the given pipe. */
4448 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4449                                              struct drm_crtc *crtc)
4450 {
4451         struct drm_i915_private *dev_priv = dev->dev_private;
4452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4453         int pipe = intel_crtc->pipe;
4454         struct drm_display_mode *mode;
4455         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4456         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4457         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4458         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4459
4460         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4461         if (!mode)
4462                 return NULL;
4463
4464         mode->clock = intel_crtc_clock_get(dev, crtc);
4465         mode->hdisplay = (htot & 0xffff) + 1;
4466         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4467         mode->hsync_start = (hsync & 0xffff) + 1;
4468         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4469         mode->vdisplay = (vtot & 0xffff) + 1;
4470         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4471         mode->vsync_start = (vsync & 0xffff) + 1;
4472         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4473
4474         drm_mode_set_name(mode);
4475         drm_mode_set_crtcinfo(mode, 0);
4476
4477         return mode;
4478 }
4479
4480 #define GPU_IDLE_TIMEOUT 500 /* ms */
4481
4482 /* When this timer fires, we've been idle for awhile */
4483 static void intel_gpu_idle_timer(unsigned long arg)
4484 {
4485         struct drm_device *dev = (struct drm_device *)arg;
4486         drm_i915_private_t *dev_priv = dev->dev_private;
4487
4488         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4489
4490         dev_priv->busy = false;
4491
4492         queue_work(dev_priv->wq, &dev_priv->idle_work);
4493 }
4494
4495 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4496
4497 static void intel_crtc_idle_timer(unsigned long arg)
4498 {
4499         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4500         struct drm_crtc *crtc = &intel_crtc->base;
4501         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4502
4503         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4504
4505         intel_crtc->busy = false;
4506
4507         queue_work(dev_priv->wq, &dev_priv->idle_work);
4508 }
4509
4510 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4511 {
4512         struct drm_device *dev = crtc->dev;
4513         drm_i915_private_t *dev_priv = dev->dev_private;
4514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4515         int pipe = intel_crtc->pipe;
4516         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4517         int dpll = I915_READ(dpll_reg);
4518
4519         if (HAS_PCH_SPLIT(dev))
4520                 return;
4521
4522         if (!dev_priv->lvds_downclock_avail)
4523                 return;
4524
4525         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4526                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4527
4528                 /* Unlock panel regs */
4529                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4530                            PANEL_UNLOCK_REGS);
4531
4532                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4533                 I915_WRITE(dpll_reg, dpll);
4534                 dpll = I915_READ(dpll_reg);
4535                 intel_wait_for_vblank(dev);
4536                 dpll = I915_READ(dpll_reg);
4537                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4538                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4539
4540                 /* ...and lock them again */
4541                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4542         }
4543
4544         /* Schedule downclock */
4545         if (schedule)
4546                 mod_timer(&intel_crtc->idle_timer, jiffies +
4547                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4548 }
4549
4550 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4551 {
4552         struct drm_device *dev = crtc->dev;
4553         drm_i915_private_t *dev_priv = dev->dev_private;
4554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4555         int pipe = intel_crtc->pipe;
4556         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4557         int dpll = I915_READ(dpll_reg);
4558
4559         if (HAS_PCH_SPLIT(dev))
4560                 return;
4561
4562         if (!dev_priv->lvds_downclock_avail)
4563                 return;
4564
4565         /*
4566          * Since this is called by a timer, we should never get here in
4567          * the manual case.
4568          */
4569         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4570                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4571
4572                 /* Unlock panel regs */
4573                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4574                            PANEL_UNLOCK_REGS);
4575
4576                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4577                 I915_WRITE(dpll_reg, dpll);
4578                 dpll = I915_READ(dpll_reg);
4579                 intel_wait_for_vblank(dev);
4580                 dpll = I915_READ(dpll_reg);
4581                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4582                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4583
4584                 /* ...and lock them again */
4585                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4586         }
4587
4588 }
4589
4590 /**
4591  * intel_idle_update - adjust clocks for idleness
4592  * @work: work struct
4593  *
4594  * Either the GPU or display (or both) went idle.  Check the busy status
4595  * here and adjust the CRTC and GPU clocks as necessary.
4596  */
4597 static void intel_idle_update(struct work_struct *work)
4598 {
4599         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4600                                                     idle_work);
4601         struct drm_device *dev = dev_priv->dev;
4602         struct drm_crtc *crtc;
4603         struct intel_crtc *intel_crtc;
4604         int enabled = 0;
4605
4606         if (!i915_powersave)
4607                 return;
4608
4609         mutex_lock(&dev->struct_mutex);
4610
4611         i915_update_gfx_val(dev_priv);
4612
4613         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4614                 /* Skip inactive CRTCs */
4615                 if (!crtc->fb)
4616                         continue;
4617
4618                 enabled++;
4619                 intel_crtc = to_intel_crtc(crtc);
4620                 if (!intel_crtc->busy)
4621                         intel_decrease_pllclock(crtc);
4622         }
4623
4624         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4625                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4626                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4627         }
4628
4629         mutex_unlock(&dev->struct_mutex);
4630 }
4631
4632 /**
4633  * intel_mark_busy - mark the GPU and possibly the display busy
4634  * @dev: drm device
4635  * @obj: object we're operating on
4636  *
4637  * Callers can use this function to indicate that the GPU is busy processing
4638  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4639  * buffer), we'll also mark the display as busy, so we know to increase its
4640  * clock frequency.
4641  */
4642 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4643 {
4644         drm_i915_private_t *dev_priv = dev->dev_private;
4645         struct drm_crtc *crtc = NULL;
4646         struct intel_framebuffer *intel_fb;
4647         struct intel_crtc *intel_crtc;
4648
4649         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4650                 return;
4651
4652         if (!dev_priv->busy) {
4653                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4654                         u32 fw_blc_self;
4655
4656                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4657                         fw_blc_self = I915_READ(FW_BLC_SELF);
4658                         fw_blc_self &= ~FW_BLC_SELF_EN;
4659                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4660                 }
4661                 dev_priv->busy = true;
4662         } else
4663                 mod_timer(&dev_priv->idle_timer, jiffies +
4664                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4665
4666         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4667                 if (!crtc->fb)
4668                         continue;
4669
4670                 intel_crtc = to_intel_crtc(crtc);
4671                 intel_fb = to_intel_framebuffer(crtc->fb);
4672                 if (intel_fb->obj == obj) {
4673                         if (!intel_crtc->busy) {
4674                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4675                                         u32 fw_blc_self;
4676
4677                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4678                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4679                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4680                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4681                                 }
4682                                 /* Non-busy -> busy, upclock */
4683                                 intel_increase_pllclock(crtc, true);
4684                                 intel_crtc->busy = true;
4685                         } else {
4686                                 /* Busy -> busy, put off timer */
4687                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4688                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4689                         }
4690                 }
4691         }
4692 }
4693
4694 static void intel_crtc_destroy(struct drm_crtc *crtc)
4695 {
4696         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4697
4698         drm_crtc_cleanup(crtc);
4699         kfree(intel_crtc);
4700 }
4701
4702 struct intel_unpin_work {
4703         struct work_struct work;
4704         struct drm_device *dev;
4705         struct drm_gem_object *old_fb_obj;
4706         struct drm_gem_object *pending_flip_obj;
4707         struct drm_pending_vblank_event *event;
4708         int pending;
4709 };
4710
4711 static void intel_unpin_work_fn(struct work_struct *__work)
4712 {
4713         struct intel_unpin_work *work =
4714                 container_of(__work, struct intel_unpin_work, work);
4715
4716         mutex_lock(&work->dev->struct_mutex);
4717         i915_gem_object_unpin(work->old_fb_obj);
4718         drm_gem_object_unreference(work->pending_flip_obj);
4719         drm_gem_object_unreference(work->old_fb_obj);
4720         mutex_unlock(&work->dev->struct_mutex);
4721         kfree(work);
4722 }
4723
4724 static void do_intel_finish_page_flip(struct drm_device *dev,
4725                                       struct drm_crtc *crtc)
4726 {
4727         drm_i915_private_t *dev_priv = dev->dev_private;
4728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4729         struct intel_unpin_work *work;
4730         struct drm_i915_gem_object *obj_priv;
4731         struct drm_pending_vblank_event *e;
4732         struct timeval now;
4733         unsigned long flags;
4734
4735         /* Ignore early vblank irqs */
4736         if (intel_crtc == NULL)
4737                 return;
4738
4739         spin_lock_irqsave(&dev->event_lock, flags);
4740         work = intel_crtc->unpin_work;
4741         if (work == NULL || !work->pending) {
4742                 spin_unlock_irqrestore(&dev->event_lock, flags);
4743                 return;
4744         }
4745
4746         intel_crtc->unpin_work = NULL;
4747         drm_vblank_put(dev, intel_crtc->pipe);
4748
4749         if (work->event) {
4750                 e = work->event;
4751                 do_gettimeofday(&now);
4752                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4753                 e->event.tv_sec = now.tv_sec;
4754                 e->event.tv_usec = now.tv_usec;
4755                 list_add_tail(&e->base.link,
4756                               &e->base.file_priv->event_list);
4757                 wake_up_interruptible(&e->base.file_priv->event_wait);
4758         }
4759
4760         spin_unlock_irqrestore(&dev->event_lock, flags);
4761
4762         obj_priv = to_intel_bo(work->pending_flip_obj);
4763
4764         /* Initial scanout buffer will have a 0 pending flip count */
4765         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4766             atomic_dec_and_test(&obj_priv->pending_flip))
4767                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4768         schedule_work(&work->work);
4769 }
4770
4771 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4772 {
4773         drm_i915_private_t *dev_priv = dev->dev_private;
4774         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4775
4776         do_intel_finish_page_flip(dev, crtc);
4777 }
4778
4779 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4780 {
4781         drm_i915_private_t *dev_priv = dev->dev_private;
4782         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4783
4784         do_intel_finish_page_flip(dev, crtc);
4785 }
4786
4787 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4788 {
4789         drm_i915_private_t *dev_priv = dev->dev_private;
4790         struct intel_crtc *intel_crtc =
4791                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4792         unsigned long flags;
4793
4794         spin_lock_irqsave(&dev->event_lock, flags);
4795         if (intel_crtc->unpin_work) {
4796                 intel_crtc->unpin_work->pending = 1;
4797         } else {
4798                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4799         }
4800         spin_unlock_irqrestore(&dev->event_lock, flags);
4801 }
4802
4803 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4804                                 struct drm_framebuffer *fb,
4805                                 struct drm_pending_vblank_event *event)
4806 {
4807         struct drm_device *dev = crtc->dev;
4808         struct drm_i915_private *dev_priv = dev->dev_private;
4809         struct intel_framebuffer *intel_fb;
4810         struct drm_i915_gem_object *obj_priv;
4811         struct drm_gem_object *obj;
4812         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4813         struct intel_unpin_work *work;
4814         unsigned long flags, offset;
4815         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4816         int ret, pipesrc;
4817         u32 flip_mask;
4818
4819         work = kzalloc(sizeof *work, GFP_KERNEL);
4820         if (work == NULL)
4821                 return -ENOMEM;
4822
4823         work->event = event;
4824         work->dev = crtc->dev;
4825         intel_fb = to_intel_framebuffer(crtc->fb);
4826         work->old_fb_obj = intel_fb->obj;
4827         INIT_WORK(&work->work, intel_unpin_work_fn);
4828
4829         /* We borrow the event spin lock for protecting unpin_work */
4830         spin_lock_irqsave(&dev->event_lock, flags);
4831         if (intel_crtc->unpin_work) {
4832                 spin_unlock_irqrestore(&dev->event_lock, flags);
4833                 kfree(work);
4834
4835                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4836                 return -EBUSY;
4837         }
4838         intel_crtc->unpin_work = work;
4839         spin_unlock_irqrestore(&dev->event_lock, flags);
4840
4841         intel_fb = to_intel_framebuffer(fb);
4842         obj = intel_fb->obj;
4843
4844         mutex_lock(&dev->struct_mutex);
4845         ret = intel_pin_and_fence_fb_obj(dev, obj);
4846         if (ret != 0) {
4847                 mutex_unlock(&dev->struct_mutex);
4848
4849                 spin_lock_irqsave(&dev->event_lock, flags);
4850                 intel_crtc->unpin_work = NULL;
4851                 spin_unlock_irqrestore(&dev->event_lock, flags);
4852
4853                 kfree(work);
4854
4855                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4856                                  to_intel_bo(obj));
4857                 return ret;
4858         }
4859
4860         /* Reference the objects for the scheduled work. */
4861         drm_gem_object_reference(work->old_fb_obj);
4862         drm_gem_object_reference(obj);
4863
4864         crtc->fb = fb;
4865         i915_gem_object_flush_write_domain(obj);
4866         drm_vblank_get(dev, intel_crtc->pipe);
4867         obj_priv = to_intel_bo(obj);
4868         atomic_inc(&obj_priv->pending_flip);
4869         work->pending_flip_obj = obj;
4870
4871         if (intel_crtc->plane)
4872                 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4873         else
4874                 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
4875
4876         /* Wait for any previous flip to finish */
4877         if (IS_GEN3(dev))
4878                 while (I915_READ(ISR) & flip_mask)
4879                         ;
4880
4881         /* Offset into the new buffer for cases of shared fbs between CRTCs */
4882         offset = obj_priv->gtt_offset;
4883         offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
4884
4885         BEGIN_LP_RING(4);
4886         if (IS_I965G(dev)) {
4887                 OUT_RING(MI_DISPLAY_FLIP |
4888                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4889                 OUT_RING(fb->pitch);
4890                 OUT_RING(offset | obj_priv->tiling_mode);
4891                 pipesrc = I915_READ(pipesrc_reg);
4892                 OUT_RING(pipesrc & 0x0fff0fff);
4893         } else {
4894                 OUT_RING(MI_DISPLAY_FLIP_I915 |
4895                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4896                 OUT_RING(fb->pitch);
4897                 OUT_RING(offset);
4898                 OUT_RING(MI_NOOP);
4899         }
4900         ADVANCE_LP_RING();
4901
4902         mutex_unlock(&dev->struct_mutex);
4903
4904         return 0;
4905 }
4906
4907 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4908         .dpms = intel_crtc_dpms,
4909         .mode_fixup = intel_crtc_mode_fixup,
4910         .mode_set = intel_crtc_mode_set,
4911         .mode_set_base = intel_pipe_set_base,
4912         .mode_set_base_atomic = intel_pipe_set_base_atomic,
4913         .prepare = intel_crtc_prepare,
4914         .commit = intel_crtc_commit,
4915         .load_lut = intel_crtc_load_lut,
4916 };
4917
4918 static const struct drm_crtc_funcs intel_crtc_funcs = {
4919         .cursor_set = intel_crtc_cursor_set,
4920         .cursor_move = intel_crtc_cursor_move,
4921         .gamma_set = intel_crtc_gamma_set,
4922         .set_config = drm_crtc_helper_set_config,
4923         .destroy = intel_crtc_destroy,
4924         .page_flip = intel_crtc_page_flip,
4925 };
4926
4927
4928 static void intel_crtc_init(struct drm_device *dev, int pipe)
4929 {
4930         drm_i915_private_t *dev_priv = dev->dev_private;
4931         struct intel_crtc *intel_crtc;
4932         int i;
4933
4934         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4935         if (intel_crtc == NULL)
4936                 return;
4937
4938         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4939
4940         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4941         intel_crtc->pipe = pipe;
4942         intel_crtc->plane = pipe;
4943         for (i = 0; i < 256; i++) {
4944                 intel_crtc->lut_r[i] = i;
4945                 intel_crtc->lut_g[i] = i;
4946                 intel_crtc->lut_b[i] = i;
4947         }
4948
4949         /* Swap pipes & planes for FBC on pre-965 */
4950         intel_crtc->pipe = pipe;
4951         intel_crtc->plane = pipe;
4952         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4953                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4954                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4955         }
4956
4957         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4958                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4959         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4960         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4961
4962         intel_crtc->cursor_addr = 0;
4963         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4964         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4965
4966         intel_crtc->busy = false;
4967
4968         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4969                     (unsigned long)intel_crtc);
4970 }
4971
4972 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4973                                 struct drm_file *file_priv)
4974 {
4975         drm_i915_private_t *dev_priv = dev->dev_private;
4976         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4977         struct drm_mode_object *drmmode_obj;
4978         struct intel_crtc *crtc;
4979
4980         if (!dev_priv) {
4981                 DRM_ERROR("called with no initialization\n");
4982                 return -EINVAL;
4983         }
4984
4985         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4986                         DRM_MODE_OBJECT_CRTC);
4987
4988         if (!drmmode_obj) {
4989                 DRM_ERROR("no such CRTC id\n");
4990                 return -EINVAL;
4991         }
4992
4993         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4994         pipe_from_crtc_id->pipe = crtc->pipe;
4995
4996         return 0;
4997 }
4998
4999 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5000 {
5001         struct drm_crtc *crtc = NULL;
5002
5003         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5004                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005                 if (intel_crtc->pipe == pipe)
5006                         break;
5007         }
5008         return crtc;
5009 }
5010
5011 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5012 {
5013         int index_mask = 0;
5014         struct drm_encoder *encoder;
5015         int entry = 0;
5016
5017         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5018                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5019                 if (type_mask & intel_encoder->clone_mask)
5020                         index_mask |= (1 << entry);
5021                 entry++;
5022         }
5023         return index_mask;
5024 }
5025
5026
5027 static void intel_setup_outputs(struct drm_device *dev)
5028 {
5029         struct drm_i915_private *dev_priv = dev->dev_private;
5030         struct drm_encoder *encoder;
5031
5032         intel_crt_init(dev);
5033
5034         /* Set up integrated LVDS */
5035         if (IS_MOBILE(dev) && !IS_I830(dev))
5036                 intel_lvds_init(dev);
5037
5038         if (HAS_PCH_SPLIT(dev)) {
5039                 int found;
5040
5041                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5042                         intel_dp_init(dev, DP_A);
5043
5044                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5045                         /* PCH SDVOB multiplex with HDMIB */
5046                         found = intel_sdvo_init(dev, PCH_SDVOB);
5047                         if (!found)
5048                                 intel_hdmi_init(dev, HDMIB);
5049                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5050                                 intel_dp_init(dev, PCH_DP_B);
5051                 }
5052
5053                 if (I915_READ(HDMIC) & PORT_DETECTED)
5054                         intel_hdmi_init(dev, HDMIC);
5055
5056                 if (I915_READ(HDMID) & PORT_DETECTED)
5057                         intel_hdmi_init(dev, HDMID);
5058
5059                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5060                         intel_dp_init(dev, PCH_DP_C);
5061
5062                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
5063                         intel_dp_init(dev, PCH_DP_D);
5064
5065         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5066                 bool found = false;
5067
5068                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5069                         DRM_DEBUG_KMS("probing SDVOB\n");
5070                         found = intel_sdvo_init(dev, SDVOB);
5071                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5072                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5073                                 intel_hdmi_init(dev, SDVOB);
5074                         }
5075
5076                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5077                                 DRM_DEBUG_KMS("probing DP_B\n");
5078                                 intel_dp_init(dev, DP_B);
5079                         }
5080                 }
5081
5082                 /* Before G4X SDVOC doesn't have its own detect register */
5083
5084                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5085                         DRM_DEBUG_KMS("probing SDVOC\n");
5086                         found = intel_sdvo_init(dev, SDVOC);
5087                 }
5088
5089                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5090
5091                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5092                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5093                                 intel_hdmi_init(dev, SDVOC);
5094                         }
5095                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5096                                 DRM_DEBUG_KMS("probing DP_C\n");
5097                                 intel_dp_init(dev, DP_C);
5098                         }
5099                 }
5100
5101                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5102                     (I915_READ(DP_D) & DP_DETECTED)) {
5103                         DRM_DEBUG_KMS("probing DP_D\n");
5104                         intel_dp_init(dev, DP_D);
5105                 }
5106         } else if (IS_GEN2(dev))
5107                 intel_dvo_init(dev);
5108
5109         if (SUPPORTS_TV(dev))
5110                 intel_tv_init(dev);
5111
5112         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5113                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5114
5115                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5116                 encoder->possible_clones = intel_encoder_clones(dev,
5117                                                 intel_encoder->clone_mask);
5118         }
5119 }
5120
5121 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5122 {
5123         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5124
5125         drm_framebuffer_cleanup(fb);
5126         drm_gem_object_unreference_unlocked(intel_fb->obj);
5127
5128         kfree(intel_fb);
5129 }
5130
5131 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5132                                                 struct drm_file *file_priv,
5133                                                 unsigned int *handle)
5134 {
5135         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5136         struct drm_gem_object *object = intel_fb->obj;
5137
5138         return drm_gem_handle_create(file_priv, object, handle);
5139 }
5140
5141 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5142         .destroy = intel_user_framebuffer_destroy,
5143         .create_handle = intel_user_framebuffer_create_handle,
5144 };
5145
5146 int intel_framebuffer_init(struct drm_device *dev,
5147                            struct intel_framebuffer *intel_fb,
5148                            struct drm_mode_fb_cmd *mode_cmd,
5149                            struct drm_gem_object *obj)
5150 {
5151         int ret;
5152
5153         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5154         if (ret) {
5155                 DRM_ERROR("framebuffer init failed %d\n", ret);
5156                 return ret;
5157         }
5158
5159         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5160         intel_fb->obj = obj;
5161         return 0;
5162 }
5163
5164 static struct drm_framebuffer *
5165 intel_user_framebuffer_create(struct drm_device *dev,
5166                               struct drm_file *filp,
5167                               struct drm_mode_fb_cmd *mode_cmd)
5168 {
5169         struct drm_gem_object *obj;
5170         struct intel_framebuffer *intel_fb;
5171         int ret;
5172
5173         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5174         if (!obj)
5175                 return NULL;
5176
5177         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5178         if (!intel_fb)
5179                 return NULL;
5180
5181         ret = intel_framebuffer_init(dev, intel_fb,
5182                                      mode_cmd, obj);
5183         if (ret) {
5184                 drm_gem_object_unreference_unlocked(obj);
5185                 kfree(intel_fb);
5186                 return NULL;
5187         }
5188
5189         return &intel_fb->base;
5190 }
5191
5192 static const struct drm_mode_config_funcs intel_mode_funcs = {
5193         .fb_create = intel_user_framebuffer_create,
5194         .output_poll_changed = intel_fb_output_poll_changed,
5195 };
5196
5197 static struct drm_gem_object *
5198 intel_alloc_power_context(struct drm_device *dev)
5199 {
5200         struct drm_gem_object *pwrctx;
5201         int ret;
5202
5203         pwrctx = i915_gem_alloc_object(dev, 4096);
5204         if (!pwrctx) {
5205                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5206                 return NULL;
5207         }
5208
5209         mutex_lock(&dev->struct_mutex);
5210         ret = i915_gem_object_pin(pwrctx, 4096);
5211         if (ret) {
5212                 DRM_ERROR("failed to pin power context: %d\n", ret);
5213                 goto err_unref;
5214         }
5215
5216         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5217         if (ret) {
5218                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5219                 goto err_unpin;
5220         }
5221         mutex_unlock(&dev->struct_mutex);
5222
5223         return pwrctx;
5224
5225 err_unpin:
5226         i915_gem_object_unpin(pwrctx);
5227 err_unref:
5228         drm_gem_object_unreference(pwrctx);
5229         mutex_unlock(&dev->struct_mutex);
5230         return NULL;
5231 }
5232
5233 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5234 {
5235         struct drm_i915_private *dev_priv = dev->dev_private;
5236         u16 rgvswctl;
5237
5238         rgvswctl = I915_READ16(MEMSWCTL);
5239         if (rgvswctl & MEMCTL_CMD_STS) {
5240                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5241                 return false; /* still busy with another command */
5242         }
5243
5244         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5245                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5246         I915_WRITE16(MEMSWCTL, rgvswctl);
5247         POSTING_READ16(MEMSWCTL);
5248
5249         rgvswctl |= MEMCTL_CMD_STS;
5250         I915_WRITE16(MEMSWCTL, rgvswctl);
5251
5252         return true;
5253 }
5254
5255 void ironlake_enable_drps(struct drm_device *dev)
5256 {
5257         struct drm_i915_private *dev_priv = dev->dev_private;
5258         u32 rgvmodectl = I915_READ(MEMMODECTL);
5259         u8 fmax, fmin, fstart, vstart;
5260         int i = 0;
5261
5262         /* 100ms RC evaluation intervals */
5263         I915_WRITE(RCUPEI, 100000);
5264         I915_WRITE(RCDNEI, 100000);
5265
5266         /* Set max/min thresholds to 90ms and 80ms respectively */
5267         I915_WRITE(RCBMAXAVG, 90000);
5268         I915_WRITE(RCBMINAVG, 80000);
5269
5270         I915_WRITE(MEMIHYST, 1);
5271
5272         /* Set up min, max, and cur for interrupt handling */
5273         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5274         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5275         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5276                 MEMMODE_FSTART_SHIFT;
5277         fstart = fmax;
5278
5279         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5280                 PXVFREQ_PX_SHIFT;
5281
5282         dev_priv->fmax = fstart; /* IPS callback will increase this */
5283         dev_priv->fstart = fstart;
5284
5285         dev_priv->max_delay = fmax;
5286         dev_priv->min_delay = fmin;
5287         dev_priv->cur_delay = fstart;
5288
5289         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5290                          fstart);
5291
5292         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5293
5294         /*
5295          * Interrupts will be enabled in ironlake_irq_postinstall
5296          */
5297
5298         I915_WRITE(VIDSTART, vstart);
5299         POSTING_READ(VIDSTART);
5300
5301         rgvmodectl |= MEMMODE_SWMODE_EN;
5302         I915_WRITE(MEMMODECTL, rgvmodectl);
5303
5304         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5305                 if (i++ > 100) {
5306                         DRM_ERROR("stuck trying to change perf mode\n");
5307                         break;
5308                 }
5309                 msleep(1);
5310         }
5311         msleep(1);
5312
5313         ironlake_set_drps(dev, fstart);
5314
5315         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5316                 I915_READ(0x112e0);
5317         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5318         dev_priv->last_count2 = I915_READ(0x112f4);
5319         getrawmonotonic(&dev_priv->last_time2);
5320 }
5321
5322 void ironlake_disable_drps(struct drm_device *dev)
5323 {
5324         struct drm_i915_private *dev_priv = dev->dev_private;
5325         u16 rgvswctl = I915_READ16(MEMSWCTL);
5326
5327         /* Ack interrupts, disable EFC interrupt */
5328         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5329         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5330         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5331         I915_WRITE(DEIIR, DE_PCU_EVENT);
5332         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5333
5334         /* Go back to the starting frequency */
5335         ironlake_set_drps(dev, dev_priv->fstart);
5336         msleep(1);
5337         rgvswctl |= MEMCTL_CMD_STS;
5338         I915_WRITE(MEMSWCTL, rgvswctl);
5339         msleep(1);
5340
5341 }
5342
5343 static unsigned long intel_pxfreq(u32 vidfreq)
5344 {
5345         unsigned long freq;
5346         int div = (vidfreq & 0x3f0000) >> 16;
5347         int post = (vidfreq & 0x3000) >> 12;
5348         int pre = (vidfreq & 0x7);
5349
5350         if (!pre)
5351                 return 0;
5352
5353         freq = ((div * 133333) / ((1<<post) * pre));
5354
5355         return freq;
5356 }
5357
5358 void intel_init_emon(struct drm_device *dev)
5359 {
5360         struct drm_i915_private *dev_priv = dev->dev_private;
5361         u32 lcfuse;
5362         u8 pxw[16];
5363         int i;
5364
5365         /* Disable to program */
5366         I915_WRITE(ECR, 0);
5367         POSTING_READ(ECR);
5368
5369         /* Program energy weights for various events */
5370         I915_WRITE(SDEW, 0x15040d00);
5371         I915_WRITE(CSIEW0, 0x007f0000);
5372         I915_WRITE(CSIEW1, 0x1e220004);
5373         I915_WRITE(CSIEW2, 0x04000004);
5374
5375         for (i = 0; i < 5; i++)
5376                 I915_WRITE(PEW + (i * 4), 0);
5377         for (i = 0; i < 3; i++)
5378                 I915_WRITE(DEW + (i * 4), 0);
5379
5380         /* Program P-state weights to account for frequency power adjustment */
5381         for (i = 0; i < 16; i++) {
5382                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5383                 unsigned long freq = intel_pxfreq(pxvidfreq);
5384                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5385                         PXVFREQ_PX_SHIFT;
5386                 unsigned long val;
5387
5388                 val = vid * vid;
5389                 val *= (freq / 1000);
5390                 val *= 255;
5391                 val /= (127*127*900);
5392                 if (val > 0xff)
5393                         DRM_ERROR("bad pxval: %ld\n", val);
5394                 pxw[i] = val;
5395         }
5396         /* Render standby states get 0 weight */
5397         pxw[14] = 0;
5398         pxw[15] = 0;
5399
5400         for (i = 0; i < 4; i++) {
5401                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5402                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5403                 I915_WRITE(PXW + (i * 4), val);
5404         }
5405
5406         /* Adjust magic regs to magic values (more experimental results) */
5407         I915_WRITE(OGW0, 0);
5408         I915_WRITE(OGW1, 0);
5409         I915_WRITE(EG0, 0x00007f00);
5410         I915_WRITE(EG1, 0x0000000e);
5411         I915_WRITE(EG2, 0x000e0000);
5412         I915_WRITE(EG3, 0x68000300);
5413         I915_WRITE(EG4, 0x42000000);
5414         I915_WRITE(EG5, 0x00140031);
5415         I915_WRITE(EG6, 0);
5416         I915_WRITE(EG7, 0);
5417
5418         for (i = 0; i < 8; i++)
5419                 I915_WRITE(PXWL + (i * 4), 0);
5420
5421         /* Enable PMON + select events */
5422         I915_WRITE(ECR, 0x80000019);
5423
5424         lcfuse = I915_READ(LCFUSE02);
5425
5426         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5427 }
5428
5429 void intel_init_clock_gating(struct drm_device *dev)
5430 {
5431         struct drm_i915_private *dev_priv = dev->dev_private;
5432
5433         /*
5434          * Disable clock gating reported to work incorrectly according to the
5435          * specs, but enable as much else as we can.
5436          */
5437         if (HAS_PCH_SPLIT(dev)) {
5438                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5439
5440                 if (IS_IRONLAKE(dev)) {
5441                         /* Required for FBC */
5442                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5443                         /* Required for CxSR */
5444                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5445
5446                         I915_WRITE(PCH_3DCGDIS0,
5447                                    MARIUNIT_CLOCK_GATE_DISABLE |
5448                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5449                 }
5450
5451                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5452
5453                 /*
5454                  * According to the spec the following bits should be set in
5455                  * order to enable memory self-refresh
5456                  * The bit 22/21 of 0x42004
5457                  * The bit 5 of 0x42020
5458                  * The bit 15 of 0x45000
5459                  */
5460                 if (IS_IRONLAKE(dev)) {
5461                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5462                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5463                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5464                         I915_WRITE(ILK_DSPCLK_GATE,
5465                                         (I915_READ(ILK_DSPCLK_GATE) |
5466                                                 ILK_DPARB_CLK_GATE));
5467                         I915_WRITE(DISP_ARB_CTL,
5468                                         (I915_READ(DISP_ARB_CTL) |
5469                                                 DISP_FBC_WM_DIS));
5470                 }
5471                 return;
5472         } else if (IS_G4X(dev)) {
5473                 uint32_t dspclk_gate;
5474                 I915_WRITE(RENCLK_GATE_D1, 0);
5475                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5476                        GS_UNIT_CLOCK_GATE_DISABLE |
5477                        CL_UNIT_CLOCK_GATE_DISABLE);
5478                 I915_WRITE(RAMCLK_GATE_D, 0);
5479                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5480                         OVRUNIT_CLOCK_GATE_DISABLE |
5481                         OVCUNIT_CLOCK_GATE_DISABLE;
5482                 if (IS_GM45(dev))
5483                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5484                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5485         } else if (IS_I965GM(dev)) {
5486                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5487                 I915_WRITE(RENCLK_GATE_D2, 0);
5488                 I915_WRITE(DSPCLK_GATE_D, 0);
5489                 I915_WRITE(RAMCLK_GATE_D, 0);
5490                 I915_WRITE16(DEUC, 0);
5491         } else if (IS_I965G(dev)) {
5492                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5493                        I965_RCC_CLOCK_GATE_DISABLE |
5494                        I965_RCPB_CLOCK_GATE_DISABLE |
5495                        I965_ISC_CLOCK_GATE_DISABLE |
5496                        I965_FBC_CLOCK_GATE_DISABLE);
5497                 I915_WRITE(RENCLK_GATE_D2, 0);
5498         } else if (IS_I9XX(dev)) {
5499                 u32 dstate = I915_READ(D_STATE);
5500
5501                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5502                         DSTATE_DOT_CLOCK_GATING;
5503                 I915_WRITE(D_STATE, dstate);
5504         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5505                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5506         } else if (IS_I830(dev)) {
5507                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5508         }
5509
5510         /*
5511          * GPU can automatically power down the render unit if given a page
5512          * to save state.
5513          */
5514         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5515                 struct drm_i915_gem_object *obj_priv = NULL;
5516
5517                 if (dev_priv->pwrctx) {
5518                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5519                 } else {
5520                         struct drm_gem_object *pwrctx;
5521
5522                         pwrctx = intel_alloc_power_context(dev);
5523                         if (pwrctx) {
5524                                 dev_priv->pwrctx = pwrctx;
5525                                 obj_priv = to_intel_bo(pwrctx);
5526                         }
5527                 }
5528
5529                 if (obj_priv) {
5530                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5531                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5532                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5533                 }
5534         }
5535 }
5536
5537 /* Set up chip specific display functions */
5538 static void intel_init_display(struct drm_device *dev)
5539 {
5540         struct drm_i915_private *dev_priv = dev->dev_private;
5541
5542         /* We always want a DPMS function */
5543         if (HAS_PCH_SPLIT(dev))
5544                 dev_priv->display.dpms = ironlake_crtc_dpms;
5545         else
5546                 dev_priv->display.dpms = i9xx_crtc_dpms;
5547
5548         if (I915_HAS_FBC(dev)) {
5549                 if (IS_GM45(dev)) {
5550                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5551                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5552                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5553                 } else if (IS_I965GM(dev)) {
5554                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5555                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5556                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5557                 }
5558                 /* 855GM needs testing */
5559         }
5560
5561         /* Returns the core display clock speed */
5562         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5563                 dev_priv->display.get_display_clock_speed =
5564                         i945_get_display_clock_speed;
5565         else if (IS_I915G(dev))
5566                 dev_priv->display.get_display_clock_speed =
5567                         i915_get_display_clock_speed;
5568         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5569                 dev_priv->display.get_display_clock_speed =
5570                         i9xx_misc_get_display_clock_speed;
5571         else if (IS_I915GM(dev))
5572                 dev_priv->display.get_display_clock_speed =
5573                         i915gm_get_display_clock_speed;
5574         else if (IS_I865G(dev))
5575                 dev_priv->display.get_display_clock_speed =
5576                         i865_get_display_clock_speed;
5577         else if (IS_I85X(dev))
5578                 dev_priv->display.get_display_clock_speed =
5579                         i855_get_display_clock_speed;
5580         else /* 852, 830 */
5581                 dev_priv->display.get_display_clock_speed =
5582                         i830_get_display_clock_speed;
5583
5584         /* For FIFO watermark updates */
5585         if (HAS_PCH_SPLIT(dev)) {
5586                 if (IS_IRONLAKE(dev)) {
5587                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5588                                 dev_priv->display.update_wm = ironlake_update_wm;
5589                         else {
5590                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5591                                               "Disable CxSR\n");
5592                                 dev_priv->display.update_wm = NULL;
5593                         }
5594                 } else
5595                         dev_priv->display.update_wm = NULL;
5596         } else if (IS_PINEVIEW(dev)) {
5597                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5598                                             dev_priv->is_ddr3,
5599                                             dev_priv->fsb_freq,
5600                                             dev_priv->mem_freq)) {
5601                         DRM_INFO("failed to find known CxSR latency "
5602                                  "(found ddr%s fsb freq %d, mem freq %d), "
5603                                  "disabling CxSR\n",
5604                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5605                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5606                         /* Disable CxSR and never update its watermark again */
5607                         pineview_disable_cxsr(dev);
5608                         dev_priv->display.update_wm = NULL;
5609                 } else
5610                         dev_priv->display.update_wm = pineview_update_wm;
5611         } else if (IS_G4X(dev))
5612                 dev_priv->display.update_wm = g4x_update_wm;
5613         else if (IS_I965G(dev))
5614                 dev_priv->display.update_wm = i965_update_wm;
5615         else if (IS_I9XX(dev)) {
5616                 dev_priv->display.update_wm = i9xx_update_wm;
5617                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5618         } else if (IS_I85X(dev)) {
5619                 dev_priv->display.update_wm = i9xx_update_wm;
5620                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5621         } else {
5622                 dev_priv->display.update_wm = i830_update_wm;
5623                 if (IS_845G(dev))
5624                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5625                 else
5626                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5627         }
5628 }
5629
5630 /*
5631  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5632  * resume, or other times.  This quirk makes sure that's the case for
5633  * affected systems.
5634  */
5635 static void quirk_pipea_force (struct drm_device *dev)
5636 {
5637         struct drm_i915_private *dev_priv = dev->dev_private;
5638
5639         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5640         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5641 }
5642
5643 struct intel_quirk {
5644         int device;
5645         int subsystem_vendor;
5646         int subsystem_device;
5647         void (*hook)(struct drm_device *dev);
5648 };
5649
5650 struct intel_quirk intel_quirks[] = {
5651         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5652         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5653         /* HP Mini needs pipe A force quirk (LP: #322104) */
5654         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5655
5656         /* Thinkpad R31 needs pipe A force quirk */
5657         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5658         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5659         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5660
5661         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5662         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5663         /* ThinkPad X40 needs pipe A force quirk */
5664
5665         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5666         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5667
5668         /* 855 & before need to leave pipe A & dpll A up */
5669         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5670         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5671 };
5672
5673 static void intel_init_quirks(struct drm_device *dev)
5674 {
5675         struct pci_dev *d = dev->pdev;
5676         int i;
5677
5678         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5679                 struct intel_quirk *q = &intel_quirks[i];
5680
5681                 if (d->device == q->device &&
5682                     (d->subsystem_vendor == q->subsystem_vendor ||
5683                      q->subsystem_vendor == PCI_ANY_ID) &&
5684                     (d->subsystem_device == q->subsystem_device ||
5685                      q->subsystem_device == PCI_ANY_ID))
5686                         q->hook(dev);
5687         }
5688 }
5689
5690 void intel_modeset_init(struct drm_device *dev)
5691 {
5692         struct drm_i915_private *dev_priv = dev->dev_private;
5693         int i;
5694
5695         drm_mode_config_init(dev);
5696
5697         dev->mode_config.min_width = 0;
5698         dev->mode_config.min_height = 0;
5699
5700         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5701
5702         intel_init_quirks(dev);
5703
5704         intel_init_display(dev);
5705
5706         if (IS_I965G(dev)) {
5707                 dev->mode_config.max_width = 8192;
5708                 dev->mode_config.max_height = 8192;
5709         } else if (IS_I9XX(dev)) {
5710                 dev->mode_config.max_width = 4096;
5711                 dev->mode_config.max_height = 4096;
5712         } else {
5713                 dev->mode_config.max_width = 2048;
5714                 dev->mode_config.max_height = 2048;
5715         }
5716
5717         /* set memory base */
5718         if (IS_I9XX(dev))
5719                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5720         else
5721                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5722
5723         if (IS_MOBILE(dev) || IS_I9XX(dev))
5724                 dev_priv->num_pipe = 2;
5725         else
5726                 dev_priv->num_pipe = 1;
5727         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5728                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5729
5730         for (i = 0; i < dev_priv->num_pipe; i++) {
5731                 intel_crtc_init(dev, i);
5732         }
5733
5734         intel_setup_outputs(dev);
5735
5736         intel_init_clock_gating(dev);
5737
5738         if (IS_IRONLAKE_M(dev)) {
5739                 ironlake_enable_drps(dev);
5740                 intel_init_emon(dev);
5741         }
5742
5743         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5744         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5745                     (unsigned long)dev);
5746
5747         intel_setup_overlay(dev);
5748 }
5749
5750 void intel_modeset_cleanup(struct drm_device *dev)
5751 {
5752         struct drm_i915_private *dev_priv = dev->dev_private;
5753         struct drm_crtc *crtc;
5754         struct intel_crtc *intel_crtc;
5755
5756         mutex_lock(&dev->struct_mutex);
5757
5758         drm_kms_helper_poll_fini(dev);
5759         intel_fbdev_fini(dev);
5760
5761         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5762                 /* Skip inactive CRTCs */
5763                 if (!crtc->fb)
5764                         continue;
5765
5766                 intel_crtc = to_intel_crtc(crtc);
5767                 intel_increase_pllclock(crtc, false);
5768                 del_timer_sync(&intel_crtc->idle_timer);
5769         }
5770
5771         del_timer_sync(&dev_priv->idle_timer);
5772
5773         if (dev_priv->display.disable_fbc)
5774                 dev_priv->display.disable_fbc(dev);
5775
5776         if (dev_priv->pwrctx) {
5777                 struct drm_i915_gem_object *obj_priv;
5778
5779                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5780                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5781                 I915_READ(PWRCTXA);
5782                 i915_gem_object_unpin(dev_priv->pwrctx);
5783                 drm_gem_object_unreference(dev_priv->pwrctx);
5784         }
5785
5786         if (IS_IRONLAKE_M(dev))
5787                 ironlake_disable_drps(dev);
5788
5789         mutex_unlock(&dev->struct_mutex);
5790
5791         drm_mode_config_cleanup(dev);
5792 }
5793
5794
5795 /*
5796  * Return which encoder is currently attached for connector.
5797  */
5798 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5799 {
5800         struct drm_mode_object *obj;
5801         struct drm_encoder *encoder;
5802         int i;
5803
5804         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5805                 if (connector->encoder_ids[i] == 0)
5806                         break;
5807
5808                 obj = drm_mode_object_find(connector->dev,
5809                                            connector->encoder_ids[i],
5810                                            DRM_MODE_OBJECT_ENCODER);
5811                 if (!obj)
5812                         continue;
5813
5814                 encoder = obj_to_encoder(obj);
5815                 return encoder;
5816         }
5817         return NULL;
5818 }
5819
5820 /*
5821  * set vga decode state - true == enable VGA decode
5822  */
5823 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5824 {
5825         struct drm_i915_private *dev_priv = dev->dev_private;
5826         u16 gmch_ctrl;
5827
5828         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5829         if (state)
5830                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5831         else
5832                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5833         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5834         return 0;
5835 }