2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
33 #include "intel_drv.h"
36 #include "drm_dp_helper.h"
38 #include "drm_crtc_helper.h"
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
43 static void intel_update_watermarks(struct drm_device *dev);
44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
67 #define INTEL_P2_NUM 2
68 typedef struct intel_limit intel_limit_t;
70 intel_range_t dot, vco, n, m, m1, m2, p, p1;
72 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73 int, int, intel_clock_t *);
76 #define I8XX_DOT_MIN 25000
77 #define I8XX_DOT_MAX 350000
78 #define I8XX_VCO_MIN 930000
79 #define I8XX_VCO_MAX 1400000
83 #define I8XX_M_MAX 140
84 #define I8XX_M1_MIN 18
85 #define I8XX_M1_MAX 26
87 #define I8XX_M2_MAX 16
89 #define I8XX_P_MAX 128
91 #define I8XX_P1_MAX 33
92 #define I8XX_P1_LVDS_MIN 1
93 #define I8XX_P1_LVDS_MAX 6
94 #define I8XX_P2_SLOW 4
95 #define I8XX_P2_FAST 2
96 #define I8XX_P2_LVDS_SLOW 14
97 #define I8XX_P2_LVDS_FAST 7
98 #define I8XX_P2_SLOW_LIMIT 165000
100 #define I9XX_DOT_MIN 20000
101 #define I9XX_DOT_MAX 400000
102 #define I9XX_VCO_MIN 1400000
103 #define I9XX_VCO_MAX 2800000
104 #define PINEVIEW_VCO_MIN 1700000
105 #define PINEVIEW_VCO_MAX 3500000
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN 3
110 #define PINEVIEW_N_MAX 6
111 #define I9XX_M_MIN 70
112 #define I9XX_M_MAX 120
113 #define PINEVIEW_M_MIN 2
114 #define PINEVIEW_M_MAX 256
115 #define I9XX_M1_MIN 10
116 #define I9XX_M1_MAX 22
117 #define I9XX_M2_MIN 5
118 #define I9XX_M2_MAX 9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN 0
121 #define PINEVIEW_M1_MAX 0
122 #define PINEVIEW_M2_MIN 0
123 #define PINEVIEW_M2_MAX 254
124 #define I9XX_P_SDVO_DAC_MIN 5
125 #define I9XX_P_SDVO_DAC_MAX 80
126 #define I9XX_P_LVDS_MIN 7
127 #define I9XX_P_LVDS_MAX 98
128 #define PINEVIEW_P_LVDS_MIN 7
129 #define PINEVIEW_P_LVDS_MAX 112
130 #define I9XX_P1_MIN 1
131 #define I9XX_P1_MAX 8
132 #define I9XX_P2_SDVO_DAC_SLOW 10
133 #define I9XX_P2_SDVO_DAC_FAST 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
135 #define I9XX_P2_LVDS_SLOW 14
136 #define I9XX_P2_LVDS_FAST 7
137 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN 25000
141 #define G4X_DOT_SDVO_MAX 270000
142 #define G4X_VCO_MIN 1750000
143 #define G4X_VCO_MAX 3500000
144 #define G4X_N_SDVO_MIN 1
145 #define G4X_N_SDVO_MAX 4
146 #define G4X_M_SDVO_MIN 104
147 #define G4X_M_SDVO_MAX 138
148 #define G4X_M1_SDVO_MIN 17
149 #define G4X_M1_SDVO_MAX 23
150 #define G4X_M2_SDVO_MIN 5
151 #define G4X_M2_SDVO_MAX 11
152 #define G4X_P_SDVO_MIN 10
153 #define G4X_P_SDVO_MAX 30
154 #define G4X_P1_SDVO_MIN 1
155 #define G4X_P1_SDVO_MAX 3
156 #define G4X_P2_SDVO_SLOW 10
157 #define G4X_P2_SDVO_FAST 10
158 #define G4X_P2_SDVO_LIMIT 270000
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN 22000
162 #define G4X_DOT_HDMI_DAC_MAX 400000
163 #define G4X_N_HDMI_DAC_MIN 1
164 #define G4X_N_HDMI_DAC_MAX 4
165 #define G4X_M_HDMI_DAC_MIN 104
166 #define G4X_M_HDMI_DAC_MAX 138
167 #define G4X_M1_HDMI_DAC_MIN 16
168 #define G4X_M1_HDMI_DAC_MAX 23
169 #define G4X_M2_HDMI_DAC_MIN 5
170 #define G4X_M2_HDMI_DAC_MAX 11
171 #define G4X_P_HDMI_DAC_MIN 5
172 #define G4X_P_HDMI_DAC_MAX 80
173 #define G4X_P1_HDMI_DAC_MIN 1
174 #define G4X_P1_HDMI_DAC_MAX 8
175 #define G4X_P2_HDMI_DAC_SLOW 10
176 #define G4X_P2_HDMI_DAC_FAST 5
177 #define G4X_P2_HDMI_DAC_LIMIT 165000
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN 161670
219 #define G4X_DOT_DISPLAY_PORT_MAX 227000
220 #define G4X_N_DISPLAY_PORT_MIN 1
221 #define G4X_N_DISPLAY_PORT_MAX 2
222 #define G4X_M_DISPLAY_PORT_MIN 97
223 #define G4X_M_DISPLAY_PORT_MAX 108
224 #define G4X_M1_DISPLAY_PORT_MIN 0x10
225 #define G4X_M1_DISPLAY_PORT_MAX 0x12
226 #define G4X_M2_DISPLAY_PORT_MIN 0x05
227 #define G4X_M2_DISPLAY_PORT_MAX 0x06
228 #define G4X_P_DISPLAY_PORT_MIN 10
229 #define G4X_P_DISPLAY_PORT_MAX 20
230 #define G4X_P1_DISPLAY_PORT_MIN 1
231 #define G4X_P1_DISPLAY_PORT_MAX 2
232 #define G4X_P2_DISPLAY_PORT_SLOW 10
233 #define G4X_P2_DISPLAY_PORT_FAST 10
234 #define G4X_P2_DISPLAY_PORT_LIMIT 0
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238 N/M1/M2, so here the range value for them is (actual_value-2).
240 #define IRONLAKE_DOT_MIN 25000
241 #define IRONLAKE_DOT_MAX 350000
242 #define IRONLAKE_VCO_MIN 1760000
243 #define IRONLAKE_VCO_MAX 3510000
244 #define IRONLAKE_M1_MIN 12
245 #define IRONLAKE_M1_MAX 22
246 #define IRONLAKE_M2_MIN 5
247 #define IRONLAKE_M2_MAX 9
248 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
250 /* We have parameter ranges for different type of outputs. */
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN 1
254 #define IRONLAKE_DAC_N_MAX 5
255 #define IRONLAKE_DAC_M_MIN 79
256 #define IRONLAKE_DAC_M_MAX 127
257 #define IRONLAKE_DAC_P_MIN 5
258 #define IRONLAKE_DAC_P_MAX 80
259 #define IRONLAKE_DAC_P1_MIN 1
260 #define IRONLAKE_DAC_P1_MAX 8
261 #define IRONLAKE_DAC_P2_SLOW 10
262 #define IRONLAKE_DAC_P2_FAST 5
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN 1
266 #define IRONLAKE_LVDS_S_N_MAX 3
267 #define IRONLAKE_LVDS_S_M_MIN 79
268 #define IRONLAKE_LVDS_S_M_MAX 118
269 #define IRONLAKE_LVDS_S_P_MIN 28
270 #define IRONLAKE_LVDS_S_P_MAX 112
271 #define IRONLAKE_LVDS_S_P1_MIN 2
272 #define IRONLAKE_LVDS_S_P1_MAX 8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN 1
278 #define IRONLAKE_LVDS_D_N_MAX 3
279 #define IRONLAKE_LVDS_D_M_MIN 79
280 #define IRONLAKE_LVDS_D_M_MAX 127
281 #define IRONLAKE_LVDS_D_P_MIN 14
282 #define IRONLAKE_LVDS_D_P_MAX 56
283 #define IRONLAKE_LVDS_D_P1_MIN 2
284 #define IRONLAKE_LVDS_D_P1_MAX 8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
313 #define IRONLAKE_DP_N_MIN 1
314 #define IRONLAKE_DP_N_MAX 2
315 #define IRONLAKE_DP_M_MIN 81
316 #define IRONLAKE_DP_M_MAX 90
317 #define IRONLAKE_DP_P_MIN 10
318 #define IRONLAKE_DP_P_MAX 20
319 #define IRONLAKE_DP_P2_FAST 10
320 #define IRONLAKE_DP_P2_SLOW 10
321 #define IRONLAKE_DP_P2_LIMIT 0
322 #define IRONLAKE_DP_P1_MIN 1
323 #define IRONLAKE_DP_P1_MAX 2
326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327 int target, int refclk, intel_clock_t *best_clock);
329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330 int target, int refclk, intel_clock_t *best_clock);
333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334 int target, int refclk, intel_clock_t *best_clock);
336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337 int target, int refclk, intel_clock_t *best_clock);
339 static const intel_limit_t intel_limits_i8xx_dvo = {
340 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
341 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
342 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
343 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
344 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
345 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
346 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
347 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
348 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
350 .find_pll = intel_find_best_PLL,
353 static const intel_limit_t intel_limits_i8xx_lvds = {
354 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
355 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
356 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
357 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
358 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
359 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
360 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
361 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
362 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
364 .find_pll = intel_find_best_PLL,
367 static const intel_limit_t intel_limits_i9xx_sdvo = {
368 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
369 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
370 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
371 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
372 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
373 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
374 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
375 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
376 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
378 .find_pll = intel_find_best_PLL,
381 static const intel_limit_t intel_limits_i9xx_lvds = {
382 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
383 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
384 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
385 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
386 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
387 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
388 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
389 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
390 /* The single-channel range is 25-112Mhz, and dual-channel
391 * is 80-224Mhz. Prefer single channel as much as possible.
393 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
395 .find_pll = intel_find_best_PLL,
398 /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo = {
400 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
401 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
402 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
403 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
404 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
405 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
406 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
407 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
408 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
409 .p2_slow = G4X_P2_SDVO_SLOW,
410 .p2_fast = G4X_P2_SDVO_FAST
412 .find_pll = intel_g4x_find_best_PLL,
415 static const intel_limit_t intel_limits_g4x_hdmi = {
416 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
419 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
420 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
421 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
422 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
423 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
424 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426 .p2_fast = G4X_P2_HDMI_DAC_FAST
428 .find_pll = intel_g4x_find_best_PLL,
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
432 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434 .vco = { .min = G4X_VCO_MIN,
435 .max = G4X_VCO_MAX },
436 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
452 .find_pll = intel_g4x_find_best_PLL,
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
456 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458 .vco = { .min = G4X_VCO_MIN,
459 .max = G4X_VCO_MAX },
460 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
476 .find_pll = intel_g4x_find_best_PLL,
479 static const intel_limit_t intel_limits_g4x_display_port = {
480 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481 .max = G4X_DOT_DISPLAY_PORT_MAX },
482 .vco = { .min = G4X_VCO_MIN,
484 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
485 .max = G4X_N_DISPLAY_PORT_MAX },
486 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
487 .max = G4X_M_DISPLAY_PORT_MAX },
488 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
489 .max = G4X_M1_DISPLAY_PORT_MAX },
490 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
491 .max = G4X_M2_DISPLAY_PORT_MAX },
492 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
493 .max = G4X_P_DISPLAY_PORT_MAX },
494 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
495 .max = G4X_P1_DISPLAY_PORT_MAX},
496 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499 .find_pll = intel_find_pll_g4x_dp,
502 static const intel_limit_t intel_limits_pineview_sdvo = {
503 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
504 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
505 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
506 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
507 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
508 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
509 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
510 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
511 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
513 .find_pll = intel_find_best_PLL,
516 static const intel_limit_t intel_limits_pineview_lvds = {
517 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
518 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
519 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
520 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
521 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
522 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
523 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
524 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
525 /* Pineview only supports single-channel mode. */
526 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
528 .find_pll = intel_find_best_PLL,
531 static const intel_limit_t intel_limits_ironlake_dac = {
532 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
533 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
534 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
535 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
536 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
537 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
538 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
539 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
540 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
541 .p2_slow = IRONLAKE_DAC_P2_SLOW,
542 .p2_fast = IRONLAKE_DAC_P2_FAST },
543 .find_pll = intel_g4x_find_best_PLL,
546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
547 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
548 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
549 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
550 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
551 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
552 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
553 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
554 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
555 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558 .find_pll = intel_g4x_find_best_PLL,
561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
563 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
564 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
565 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
566 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
567 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
568 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
569 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
570 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573 .find_pll = intel_g4x_find_best_PLL,
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
578 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
579 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
582 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
583 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588 .find_pll = intel_g4x_find_best_PLL,
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
593 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
594 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
597 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
598 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
603 .find_pll = intel_g4x_find_best_PLL,
606 static const intel_limit_t intel_limits_ironlake_display_port = {
607 .dot = { .min = IRONLAKE_DOT_MIN,
608 .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN,
610 .max = IRONLAKE_VCO_MAX},
611 .n = { .min = IRONLAKE_DP_N_MIN,
612 .max = IRONLAKE_DP_N_MAX },
613 .m = { .min = IRONLAKE_DP_M_MIN,
614 .max = IRONLAKE_DP_M_MAX },
615 .m1 = { .min = IRONLAKE_M1_MIN,
616 .max = IRONLAKE_M1_MAX },
617 .m2 = { .min = IRONLAKE_M2_MIN,
618 .max = IRONLAKE_M2_MAX },
619 .p = { .min = IRONLAKE_DP_P_MIN,
620 .max = IRONLAKE_DP_P_MAX },
621 .p1 = { .min = IRONLAKE_DP_P1_MIN,
622 .max = IRONLAKE_DP_P1_MAX},
623 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624 .p2_slow = IRONLAKE_DP_P2_SLOW,
625 .p2_fast = IRONLAKE_DP_P2_FAST },
626 .find_pll = intel_find_pll_ironlake_dp,
629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
631 struct drm_device *dev = crtc->dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 const intel_limit_t *limit;
636 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
640 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641 LVDS_CLKB_POWER_UP) {
642 /* LVDS dual channel */
644 limit = &intel_limits_ironlake_dual_lvds_100m;
646 limit = &intel_limits_ironlake_dual_lvds;
649 limit = &intel_limits_ironlake_single_lvds_100m;
651 limit = &intel_limits_ironlake_single_lvds;
653 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
655 limit = &intel_limits_ironlake_display_port;
657 limit = &intel_limits_ironlake_dac;
662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
664 struct drm_device *dev = crtc->dev;
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 const intel_limit_t *limit;
668 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
671 /* LVDS with dual channel */
672 limit = &intel_limits_g4x_dual_channel_lvds;
674 /* LVDS with dual channel */
675 limit = &intel_limits_g4x_single_channel_lvds;
676 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
678 limit = &intel_limits_g4x_hdmi;
679 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
680 limit = &intel_limits_g4x_sdvo;
681 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
682 limit = &intel_limits_g4x_display_port;
683 } else /* The option is for other outputs */
684 limit = &intel_limits_i9xx_sdvo;
689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
691 struct drm_device *dev = crtc->dev;
692 const intel_limit_t *limit;
694 if (HAS_PCH_SPLIT(dev))
695 limit = intel_ironlake_limit(crtc);
696 else if (IS_G4X(dev)) {
697 limit = intel_g4x_limit(crtc);
698 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
699 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
700 limit = &intel_limits_i9xx_lvds;
702 limit = &intel_limits_i9xx_sdvo;
703 } else if (IS_PINEVIEW(dev)) {
704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705 limit = &intel_limits_pineview_lvds;
707 limit = &intel_limits_pineview_sdvo;
709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710 limit = &intel_limits_i8xx_lvds;
712 limit = &intel_limits_i8xx_dvo;
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk, intel_clock_t *clock)
720 clock->m = clock->m2 + 2;
721 clock->p = clock->p1 * clock->p2;
722 clock->vco = refclk * clock->m / clock->n;
723 clock->dot = clock->vco / clock->p;
726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
728 if (IS_PINEVIEW(dev)) {
729 pineview_clock(refclk, clock);
732 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733 clock->p = clock->p1 * clock->p2;
734 clock->vco = refclk * clock->m / (clock->n + 2);
735 clock->dot = clock->vco / clock->p;
739 * Returns whether any output on the specified pipe is of the specified type
741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
743 struct drm_device *dev = crtc->dev;
744 struct drm_mode_config *mode_config = &dev->mode_config;
745 struct drm_encoder *l_entry;
747 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748 if (l_entry && l_entry->crtc == crtc) {
749 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750 if (intel_encoder->type == type)
757 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
759 * Returns whether the given set of divisors are valid for a given refclk with
760 * the given connectors.
763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
765 const intel_limit_t *limit = intel_limit (crtc);
766 struct drm_device *dev = crtc->dev;
768 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
769 INTELPllInvalid ("p1 out of range\n");
770 if (clock->p < limit->p.min || limit->p.max < clock->p)
771 INTELPllInvalid ("p out of range\n");
772 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
773 INTELPllInvalid ("m2 out of range\n");
774 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
775 INTELPllInvalid ("m1 out of range\n");
776 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
777 INTELPllInvalid ("m1 <= m2\n");
778 if (clock->m < limit->m.min || limit->m.max < clock->m)
779 INTELPllInvalid ("m out of range\n");
780 if (clock->n < limit->n.min || limit->n.max < clock->n)
781 INTELPllInvalid ("n out of range\n");
782 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
783 INTELPllInvalid ("vco out of range\n");
784 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785 * connector, etc., rather than just a single range.
787 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
788 INTELPllInvalid ("dot out of range\n");
794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
795 int target, int refclk, intel_clock_t *best_clock)
798 struct drm_device *dev = crtc->dev;
799 struct drm_i915_private *dev_priv = dev->dev_private;
803 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
804 (I915_READ(LVDS)) != 0) {
806 * For LVDS, if the panel is on, just rely on its current
807 * settings for dual-channel. We haven't figured out how to
808 * reliably set up different single/dual channel state, if we
811 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
813 clock.p2 = limit->p2.p2_fast;
815 clock.p2 = limit->p2.p2_slow;
817 if (target < limit->p2.dot_limit)
818 clock.p2 = limit->p2.p2_slow;
820 clock.p2 = limit->p2.p2_fast;
823 memset (best_clock, 0, sizeof (*best_clock));
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 /* m1 is always 0 in Pineview */
830 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
832 for (clock.n = limit->n.min;
833 clock.n <= limit->n.max; clock.n++) {
834 for (clock.p1 = limit->p1.min;
835 clock.p1 <= limit->p1.max; clock.p1++) {
838 intel_clock(dev, refclk, &clock);
840 if (!intel_PLL_is_valid(crtc, &clock))
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
853 return (err != target);
857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
858 int target, int refclk, intel_clock_t *best_clock)
860 struct drm_device *dev = crtc->dev;
861 struct drm_i915_private *dev_priv = dev->dev_private;
865 /* approximately equals target * 0.00488 */
866 int err_most = (target >> 8) + (target >> 10);
869 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
872 if (HAS_PCH_SPLIT(dev))
876 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
878 clock.p2 = limit->p2.p2_fast;
880 clock.p2 = limit->p2.p2_slow;
882 if (target < limit->p2.dot_limit)
883 clock.p2 = limit->p2.p2_slow;
885 clock.p2 = limit->p2.p2_fast;
888 memset(best_clock, 0, sizeof(*best_clock));
889 max_n = limit->n.max;
890 /* based on hardware requirement, prefer smaller n to precision */
891 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
892 /* based on hardware requirement, prefere larger m1,m2 */
893 for (clock.m1 = limit->m1.max;
894 clock.m1 >= limit->m1.min; clock.m1--) {
895 for (clock.m2 = limit->m2.max;
896 clock.m2 >= limit->m2.min; clock.m2--) {
897 for (clock.p1 = limit->p1.max;
898 clock.p1 >= limit->p1.min; clock.p1--) {
901 intel_clock(dev, refclk, &clock);
902 if (!intel_PLL_is_valid(crtc, &clock))
904 this_err = abs(clock.dot - target) ;
905 if (this_err < err_most) {
919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
920 int target, int refclk, intel_clock_t *best_clock)
922 struct drm_device *dev = crtc->dev;
925 /* return directly when it is eDP */
929 if (target < 200000) {
942 intel_clock(dev, refclk, &clock);
943 memcpy(best_clock, &clock, sizeof(intel_clock_t));
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
950 int target, int refclk, intel_clock_t *best_clock)
953 if (target < 200000) {
966 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
967 clock.p = (clock.p1 * clock.p2);
968 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
970 memcpy(best_clock, &clock, sizeof(intel_clock_t));
975 intel_wait_for_vblank(struct drm_device *dev)
977 /* Wait for 20ms, i.e. one cycle at 50hz. */
981 /* Parameters have changed, update FBC info */
982 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
984 struct drm_device *dev = crtc->dev;
985 struct drm_i915_private *dev_priv = dev->dev_private;
986 struct drm_framebuffer *fb = crtc->fb;
987 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
988 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
991 u32 fbc_ctl, fbc_ctl2;
993 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
995 if (fb->pitch < dev_priv->cfb_pitch)
996 dev_priv->cfb_pitch = fb->pitch;
998 /* FBC_CTL wants 64B units */
999 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1000 dev_priv->cfb_fence = obj_priv->fence_reg;
1001 dev_priv->cfb_plane = intel_crtc->plane;
1002 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1004 /* Clear old tags */
1005 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1006 I915_WRITE(FBC_TAG + (i * 4), 0);
1009 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1010 if (obj_priv->tiling_mode != I915_TILING_NONE)
1011 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1012 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1013 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1016 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1018 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1019 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1020 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1021 if (obj_priv->tiling_mode != I915_TILING_NONE)
1022 fbc_ctl |= dev_priv->cfb_fence;
1023 I915_WRITE(FBC_CONTROL, fbc_ctl);
1025 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1029 void i8xx_disable_fbc(struct drm_device *dev)
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1032 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1035 if (!I915_HAS_FBC(dev))
1038 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1039 return; /* Already off, just return */
1041 /* Disable compression */
1042 fbc_ctl = I915_READ(FBC_CONTROL);
1043 fbc_ctl &= ~FBC_CTL_EN;
1044 I915_WRITE(FBC_CONTROL, fbc_ctl);
1046 /* Wait for compressing bit to clear */
1047 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1048 if (time_after(jiffies, timeout)) {
1049 DRM_DEBUG_DRIVER("FBC idle timed out\n");
1055 intel_wait_for_vblank(dev);
1057 DRM_DEBUG_KMS("disabled FBC\n");
1060 static bool i8xx_fbc_enabled(struct drm_device *dev)
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1064 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1067 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1069 struct drm_device *dev = crtc->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 struct drm_framebuffer *fb = crtc->fb;
1072 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1073 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1075 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1077 unsigned long stall_watermark = 200;
1080 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1081 dev_priv->cfb_fence = obj_priv->fence_reg;
1082 dev_priv->cfb_plane = intel_crtc->plane;
1084 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1085 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1086 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1087 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1089 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1092 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1093 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1094 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1095 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1096 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1099 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1101 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1104 void g4x_disable_fbc(struct drm_device *dev)
1106 struct drm_i915_private *dev_priv = dev->dev_private;
1109 /* Disable compression */
1110 dpfc_ctl = I915_READ(DPFC_CONTROL);
1111 dpfc_ctl &= ~DPFC_CTL_EN;
1112 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1113 intel_wait_for_vblank(dev);
1115 DRM_DEBUG_KMS("disabled FBC\n");
1118 static bool g4x_fbc_enabled(struct drm_device *dev)
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1122 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1125 bool intel_fbc_enabled(struct drm_device *dev)
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1129 if (!dev_priv->display.fbc_enabled)
1132 return dev_priv->display.fbc_enabled(dev);
1135 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1137 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1139 if (!dev_priv->display.enable_fbc)
1142 dev_priv->display.enable_fbc(crtc, interval);
1145 void intel_disable_fbc(struct drm_device *dev)
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1149 if (!dev_priv->display.disable_fbc)
1152 dev_priv->display.disable_fbc(dev);
1156 * intel_update_fbc - enable/disable FBC as needed
1157 * @crtc: CRTC to point the compressor at
1158 * @mode: mode in use
1160 * Set up the framebuffer compression hardware at mode set time. We
1161 * enable it if possible:
1162 * - plane A only (on pre-965)
1163 * - no pixel mulitply/line duplication
1164 * - no alpha buffer discard
1166 * - framebuffer <= 2048 in width, 1536 in height
1168 * We can't assume that any compression will take place (worst case),
1169 * so the compressed buffer has to be the same size as the uncompressed
1170 * one. It also must reside (along with the line length buffer) in
1173 * We need to enable/disable FBC on a global basis.
1175 static void intel_update_fbc(struct drm_crtc *crtc,
1176 struct drm_display_mode *mode)
1178 struct drm_device *dev = crtc->dev;
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1180 struct drm_framebuffer *fb = crtc->fb;
1181 struct intel_framebuffer *intel_fb;
1182 struct drm_i915_gem_object *obj_priv;
1183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1184 int plane = intel_crtc->plane;
1186 if (!i915_powersave)
1189 if (!I915_HAS_FBC(dev))
1195 intel_fb = to_intel_framebuffer(fb);
1196 obj_priv = to_intel_bo(intel_fb->obj);
1199 * If FBC is already on, we just have to verify that we can
1200 * keep it that way...
1201 * Need to disable if:
1202 * - changing FBC params (stride, fence, mode)
1203 * - new fb is too large to fit in compressed buffer
1204 * - going to an unsupported config (interlace, pixel multiply, etc.)
1206 if (intel_fb->obj->size > dev_priv->cfb_size) {
1207 DRM_DEBUG_KMS("framebuffer too large, disabling "
1209 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1212 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1213 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1214 DRM_DEBUG_KMS("mode incompatible with compression, "
1216 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1219 if ((mode->hdisplay > 2048) ||
1220 (mode->vdisplay > 1536)) {
1221 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1222 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1225 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1226 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1227 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1230 if (obj_priv->tiling_mode != I915_TILING_X) {
1231 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1232 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1236 if (intel_fbc_enabled(dev)) {
1237 /* We can re-enable it in this case, but need to update pitch */
1238 if ((fb->pitch > dev_priv->cfb_pitch) ||
1239 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1240 (plane != dev_priv->cfb_plane))
1241 intel_disable_fbc(dev);
1244 /* Now try to turn it back on if possible */
1245 if (!intel_fbc_enabled(dev))
1246 intel_enable_fbc(crtc, 500);
1251 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1252 /* Multiple disables should be harmless */
1253 if (intel_fbc_enabled(dev))
1254 intel_disable_fbc(dev);
1258 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1260 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1264 switch (obj_priv->tiling_mode) {
1265 case I915_TILING_NONE:
1266 alignment = 64 * 1024;
1269 /* pin() will align the object as required by fence */
1273 /* FIXME: Is this true? */
1274 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1280 ret = i915_gem_object_pin(obj, alignment);
1284 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1285 * fence, whereas 965+ only requires a fence if using
1286 * framebuffer compression. For simplicity, we always install
1287 * a fence as the cost is not that onerous.
1289 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1290 obj_priv->tiling_mode != I915_TILING_NONE) {
1291 ret = i915_gem_object_get_fence_reg(obj);
1293 i915_gem_object_unpin(obj);
1302 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1303 struct drm_framebuffer *old_fb)
1305 struct drm_device *dev = crtc->dev;
1306 struct drm_i915_private *dev_priv = dev->dev_private;
1307 struct drm_i915_master_private *master_priv;
1308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1309 struct intel_framebuffer *intel_fb;
1310 struct drm_i915_gem_object *obj_priv;
1311 struct drm_gem_object *obj;
1312 int pipe = intel_crtc->pipe;
1313 int plane = intel_crtc->plane;
1314 unsigned long Start, Offset;
1315 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1316 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1317 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1318 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1319 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1325 DRM_DEBUG_KMS("No FB bound\n");
1334 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1338 intel_fb = to_intel_framebuffer(crtc->fb);
1339 obj = intel_fb->obj;
1340 obj_priv = to_intel_bo(obj);
1342 mutex_lock(&dev->struct_mutex);
1343 ret = intel_pin_and_fence_fb_obj(dev, obj);
1345 mutex_unlock(&dev->struct_mutex);
1349 ret = i915_gem_object_set_to_display_plane(obj);
1351 i915_gem_object_unpin(obj);
1352 mutex_unlock(&dev->struct_mutex);
1356 dspcntr = I915_READ(dspcntr_reg);
1357 /* Mask out pixel format bits in case we change it */
1358 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1359 switch (crtc->fb->bits_per_pixel) {
1361 dspcntr |= DISPPLANE_8BPP;
1364 if (crtc->fb->depth == 15)
1365 dspcntr |= DISPPLANE_15_16BPP;
1367 dspcntr |= DISPPLANE_16BPP;
1371 if (crtc->fb->depth == 30)
1372 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1374 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1377 DRM_ERROR("Unknown color depth\n");
1378 i915_gem_object_unpin(obj);
1379 mutex_unlock(&dev->struct_mutex);
1382 if (IS_I965G(dev)) {
1383 if (obj_priv->tiling_mode != I915_TILING_NONE)
1384 dspcntr |= DISPPLANE_TILED;
1386 dspcntr &= ~DISPPLANE_TILED;
1389 if (HAS_PCH_SPLIT(dev))
1391 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1393 I915_WRITE(dspcntr_reg, dspcntr);
1395 Start = obj_priv->gtt_offset;
1396 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1398 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1399 I915_WRITE(dspstride, crtc->fb->pitch);
1400 if (IS_I965G(dev)) {
1401 I915_WRITE(dspbase, Offset);
1403 I915_WRITE(dspsurf, Start);
1405 I915_WRITE(dsptileoff, (y << 16) | x);
1407 I915_WRITE(dspbase, Start + Offset);
1411 if ((IS_I965G(dev) || plane == 0))
1412 intel_update_fbc(crtc, &crtc->mode);
1414 intel_wait_for_vblank(dev);
1417 intel_fb = to_intel_framebuffer(old_fb);
1418 obj_priv = to_intel_bo(intel_fb->obj);
1419 i915_gem_object_unpin(intel_fb->obj);
1421 intel_increase_pllclock(crtc, true);
1423 mutex_unlock(&dev->struct_mutex);
1425 if (!dev->primary->master)
1428 master_priv = dev->primary->master->driver_priv;
1429 if (!master_priv->sarea_priv)
1433 master_priv->sarea_priv->pipeB_x = x;
1434 master_priv->sarea_priv->pipeB_y = y;
1436 master_priv->sarea_priv->pipeA_x = x;
1437 master_priv->sarea_priv->pipeA_y = y;
1443 /* Disable the VGA plane that we never use */
1444 static void i915_disable_vga (struct drm_device *dev)
1446 struct drm_i915_private *dev_priv = dev->dev_private;
1450 if (HAS_PCH_SPLIT(dev))
1451 vga_reg = CPU_VGACNTRL;
1455 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1458 I915_WRITE8(VGA_SR_INDEX, 1);
1459 sr1 = I915_READ8(VGA_SR_DATA);
1460 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1463 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1466 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1468 struct drm_device *dev = crtc->dev;
1469 struct drm_i915_private *dev_priv = dev->dev_private;
1472 DRM_DEBUG_KMS("\n");
1473 dpa_ctl = I915_READ(DP_A);
1474 dpa_ctl &= ~DP_PLL_ENABLE;
1475 I915_WRITE(DP_A, dpa_ctl);
1478 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1480 struct drm_device *dev = crtc->dev;
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1484 dpa_ctl = I915_READ(DP_A);
1485 dpa_ctl |= DP_PLL_ENABLE;
1486 I915_WRITE(DP_A, dpa_ctl);
1491 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1493 struct drm_device *dev = crtc->dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1497 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1498 dpa_ctl = I915_READ(DP_A);
1499 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1501 if (clock < 200000) {
1503 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1504 /* workaround for 160Mhz:
1505 1) program 0x4600c bits 15:0 = 0x8124
1506 2) program 0x46010 bit 0 = 1
1507 3) program 0x46034 bit 24 = 1
1508 4) program 0x64000 bit 14 = 1
1510 temp = I915_READ(0x4600c);
1512 I915_WRITE(0x4600c, temp | 0x8124);
1514 temp = I915_READ(0x46010);
1515 I915_WRITE(0x46010, temp | 1);
1517 temp = I915_READ(0x46034);
1518 I915_WRITE(0x46034, temp | (1 << 24));
1520 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1522 I915_WRITE(DP_A, dpa_ctl);
1527 /* The FDI link training functions for ILK/Ibexpeak. */
1528 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1530 struct drm_device *dev = crtc->dev;
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1533 int pipe = intel_crtc->pipe;
1534 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1535 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1536 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1537 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1538 u32 temp, tries = 0;
1540 /* enable CPU FDI TX and PCH FDI RX */
1541 temp = I915_READ(fdi_tx_reg);
1542 temp |= FDI_TX_ENABLE;
1544 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1545 temp &= ~FDI_LINK_TRAIN_NONE;
1546 temp |= FDI_LINK_TRAIN_PATTERN_1;
1547 I915_WRITE(fdi_tx_reg, temp);
1548 I915_READ(fdi_tx_reg);
1550 temp = I915_READ(fdi_rx_reg);
1551 temp &= ~FDI_LINK_TRAIN_NONE;
1552 temp |= FDI_LINK_TRAIN_PATTERN_1;
1553 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1554 I915_READ(fdi_rx_reg);
1557 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1559 temp = I915_READ(fdi_rx_imr_reg);
1560 temp &= ~FDI_RX_SYMBOL_LOCK;
1561 temp &= ~FDI_RX_BIT_LOCK;
1562 I915_WRITE(fdi_rx_imr_reg, temp);
1563 I915_READ(fdi_rx_imr_reg);
1567 temp = I915_READ(fdi_rx_iir_reg);
1568 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1570 if ((temp & FDI_RX_BIT_LOCK)) {
1571 DRM_DEBUG_KMS("FDI train 1 done.\n");
1572 I915_WRITE(fdi_rx_iir_reg,
1573 temp | FDI_RX_BIT_LOCK);
1580 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1586 temp = I915_READ(fdi_tx_reg);
1587 temp &= ~FDI_LINK_TRAIN_NONE;
1588 temp |= FDI_LINK_TRAIN_PATTERN_2;
1589 I915_WRITE(fdi_tx_reg, temp);
1591 temp = I915_READ(fdi_rx_reg);
1592 temp &= ~FDI_LINK_TRAIN_NONE;
1593 temp |= FDI_LINK_TRAIN_PATTERN_2;
1594 I915_WRITE(fdi_rx_reg, temp);
1600 temp = I915_READ(fdi_rx_iir_reg);
1601 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1603 if (temp & FDI_RX_SYMBOL_LOCK) {
1604 I915_WRITE(fdi_rx_iir_reg,
1605 temp | FDI_RX_SYMBOL_LOCK);
1606 DRM_DEBUG_KMS("FDI train 2 done.\n");
1613 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1618 DRM_DEBUG_KMS("FDI train done\n");
1621 static int snb_b_fdi_train_param [] = {
1622 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1623 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1624 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1625 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1628 /* The FDI link training functions for SNB/Cougarpoint. */
1629 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1631 struct drm_device *dev = crtc->dev;
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1634 int pipe = intel_crtc->pipe;
1635 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1636 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1637 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1638 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1641 /* enable CPU FDI TX and PCH FDI RX */
1642 temp = I915_READ(fdi_tx_reg);
1643 temp |= FDI_TX_ENABLE;
1645 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1646 temp &= ~FDI_LINK_TRAIN_NONE;
1647 temp |= FDI_LINK_TRAIN_PATTERN_1;
1648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1650 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1651 I915_WRITE(fdi_tx_reg, temp);
1652 I915_READ(fdi_tx_reg);
1654 temp = I915_READ(fdi_rx_reg);
1655 if (HAS_PCH_CPT(dev)) {
1656 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1657 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1659 temp &= ~FDI_LINK_TRAIN_NONE;
1660 temp |= FDI_LINK_TRAIN_PATTERN_1;
1662 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1663 I915_READ(fdi_rx_reg);
1666 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1668 temp = I915_READ(fdi_rx_imr_reg);
1669 temp &= ~FDI_RX_SYMBOL_LOCK;
1670 temp &= ~FDI_RX_BIT_LOCK;
1671 I915_WRITE(fdi_rx_imr_reg, temp);
1672 I915_READ(fdi_rx_imr_reg);
1675 for (i = 0; i < 4; i++ ) {
1676 temp = I915_READ(fdi_tx_reg);
1677 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1678 temp |= snb_b_fdi_train_param[i];
1679 I915_WRITE(fdi_tx_reg, temp);
1682 temp = I915_READ(fdi_rx_iir_reg);
1683 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1685 if (temp & FDI_RX_BIT_LOCK) {
1686 I915_WRITE(fdi_rx_iir_reg,
1687 temp | FDI_RX_BIT_LOCK);
1688 DRM_DEBUG_KMS("FDI train 1 done.\n");
1693 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1696 temp = I915_READ(fdi_tx_reg);
1697 temp &= ~FDI_LINK_TRAIN_NONE;
1698 temp |= FDI_LINK_TRAIN_PATTERN_2;
1700 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1702 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1704 I915_WRITE(fdi_tx_reg, temp);
1706 temp = I915_READ(fdi_rx_reg);
1707 if (HAS_PCH_CPT(dev)) {
1708 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1709 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1711 temp &= ~FDI_LINK_TRAIN_NONE;
1712 temp |= FDI_LINK_TRAIN_PATTERN_2;
1714 I915_WRITE(fdi_rx_reg, temp);
1717 for (i = 0; i < 4; i++ ) {
1718 temp = I915_READ(fdi_tx_reg);
1719 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1720 temp |= snb_b_fdi_train_param[i];
1721 I915_WRITE(fdi_tx_reg, temp);
1724 temp = I915_READ(fdi_rx_iir_reg);
1725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1727 if (temp & FDI_RX_SYMBOL_LOCK) {
1728 I915_WRITE(fdi_rx_iir_reg,
1729 temp | FDI_RX_SYMBOL_LOCK);
1730 DRM_DEBUG_KMS("FDI train 2 done.\n");
1735 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1737 DRM_DEBUG_KMS("FDI train done.\n");
1740 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1742 struct drm_device *dev = crtc->dev;
1743 struct drm_i915_private *dev_priv = dev->dev_private;
1744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1745 int pipe = intel_crtc->pipe;
1746 int plane = intel_crtc->plane;
1747 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1748 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1749 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1750 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1751 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1752 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1753 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1754 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1755 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1756 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1757 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1758 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1759 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1760 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1761 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1762 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1763 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1764 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1765 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1766 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1767 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1768 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1769 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1774 temp = I915_READ(pipeconf_reg);
1775 pipe_bpc = temp & PIPE_BPC_MASK;
1777 /* XXX: When our outputs are all unaware of DPMS modes other than off
1778 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1781 case DRM_MODE_DPMS_ON:
1782 case DRM_MODE_DPMS_STANDBY:
1783 case DRM_MODE_DPMS_SUSPEND:
1784 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1786 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1787 temp = I915_READ(PCH_LVDS);
1788 if ((temp & LVDS_PORT_EN) == 0) {
1789 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1790 POSTING_READ(PCH_LVDS);
1795 /* enable eDP PLL */
1796 ironlake_enable_pll_edp(crtc);
1799 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1800 temp = I915_READ(fdi_rx_reg);
1802 * make the BPC in FDI Rx be consistent with that in
1805 temp &= ~(0x7 << 16);
1806 temp |= (pipe_bpc << 11);
1808 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1809 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1810 I915_READ(fdi_rx_reg);
1813 /* Switch from Rawclk to PCDclk */
1814 temp = I915_READ(fdi_rx_reg);
1815 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1816 I915_READ(fdi_rx_reg);
1819 /* Enable CPU FDI TX PLL, always on for Ironlake */
1820 temp = I915_READ(fdi_tx_reg);
1821 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1822 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1823 I915_READ(fdi_tx_reg);
1828 /* Enable panel fitting for LVDS */
1829 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1830 temp = I915_READ(pf_ctl_reg);
1831 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1833 /* currently full aspect */
1834 I915_WRITE(pf_win_pos, 0);
1836 I915_WRITE(pf_win_size,
1837 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1838 (dev_priv->panel_fixed_mode->vdisplay));
1841 /* Enable CPU pipe */
1842 temp = I915_READ(pipeconf_reg);
1843 if ((temp & PIPEACONF_ENABLE) == 0) {
1844 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1845 I915_READ(pipeconf_reg);
1849 /* configure and enable CPU plane */
1850 temp = I915_READ(dspcntr_reg);
1851 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1852 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1853 /* Flush the plane changes */
1854 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1858 /* For PCH output, training FDI link */
1860 gen6_fdi_link_train(crtc);
1862 ironlake_fdi_link_train(crtc);
1864 /* enable PCH DPLL */
1865 temp = I915_READ(pch_dpll_reg);
1866 if ((temp & DPLL_VCO_ENABLE) == 0) {
1867 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1868 I915_READ(pch_dpll_reg);
1872 if (HAS_PCH_CPT(dev)) {
1873 /* Be sure PCH DPLL SEL is set */
1874 temp = I915_READ(PCH_DPLL_SEL);
1875 if (trans_dpll_sel == 0 &&
1876 (temp & TRANSA_DPLL_ENABLE) == 0)
1877 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1878 else if (trans_dpll_sel == 1 &&
1879 (temp & TRANSB_DPLL_ENABLE) == 0)
1880 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1881 I915_WRITE(PCH_DPLL_SEL, temp);
1882 I915_READ(PCH_DPLL_SEL);
1885 /* set transcoder timing */
1886 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1887 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1888 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1890 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1891 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1892 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1894 /* enable normal train */
1895 temp = I915_READ(fdi_tx_reg);
1896 temp &= ~FDI_LINK_TRAIN_NONE;
1897 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1898 FDI_TX_ENHANCE_FRAME_ENABLE);
1899 I915_READ(fdi_tx_reg);
1901 temp = I915_READ(fdi_rx_reg);
1902 if (HAS_PCH_CPT(dev)) {
1903 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1904 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1906 temp &= ~FDI_LINK_TRAIN_NONE;
1907 temp |= FDI_LINK_TRAIN_NONE;
1909 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1910 I915_READ(fdi_rx_reg);
1912 /* wait one idle pattern time */
1915 /* For PCH DP, enable TRANS_DP_CTL */
1916 if (HAS_PCH_CPT(dev) &&
1917 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1918 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1921 reg = I915_READ(trans_dp_ctl);
1922 reg &= ~TRANS_DP_PORT_SEL_MASK;
1923 reg = TRANS_DP_OUTPUT_ENABLE |
1924 TRANS_DP_ENH_FRAMING |
1925 TRANS_DP_VSYNC_ACTIVE_HIGH |
1926 TRANS_DP_HSYNC_ACTIVE_HIGH;
1928 switch (intel_trans_dp_port_sel(crtc)) {
1930 reg |= TRANS_DP_PORT_SEL_B;
1933 reg |= TRANS_DP_PORT_SEL_C;
1936 reg |= TRANS_DP_PORT_SEL_D;
1939 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1940 reg |= TRANS_DP_PORT_SEL_B;
1944 I915_WRITE(trans_dp_ctl, reg);
1945 POSTING_READ(trans_dp_ctl);
1948 /* enable PCH transcoder */
1949 temp = I915_READ(transconf_reg);
1951 * make the BPC in transcoder be consistent with
1952 * that in pipeconf reg.
1954 temp &= ~PIPE_BPC_MASK;
1956 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1957 I915_READ(transconf_reg);
1959 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1964 intel_crtc_load_lut(crtc);
1967 case DRM_MODE_DPMS_OFF:
1968 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1970 drm_vblank_off(dev, pipe);
1971 /* Disable display plane */
1972 temp = I915_READ(dspcntr_reg);
1973 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1974 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1975 /* Flush the plane changes */
1976 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1977 I915_READ(dspbase_reg);
1980 i915_disable_vga(dev);
1982 /* disable cpu pipe, disable after all planes disabled */
1983 temp = I915_READ(pipeconf_reg);
1984 if ((temp & PIPEACONF_ENABLE) != 0) {
1985 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1986 I915_READ(pipeconf_reg);
1988 /* wait for cpu pipe off, pipe state */
1989 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1995 DRM_DEBUG_KMS("pipe %d off delay\n",
2001 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2006 temp = I915_READ(pf_ctl_reg);
2007 if ((temp & PF_ENABLE) != 0) {
2008 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2009 I915_READ(pf_ctl_reg);
2011 I915_WRITE(pf_win_size, 0);
2012 POSTING_READ(pf_win_size);
2015 /* disable CPU FDI tx and PCH FDI rx */
2016 temp = I915_READ(fdi_tx_reg);
2017 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2018 I915_READ(fdi_tx_reg);
2020 temp = I915_READ(fdi_rx_reg);
2021 /* BPC in FDI rx is consistent with that in pipeconf */
2022 temp &= ~(0x07 << 16);
2023 temp |= (pipe_bpc << 11);
2024 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2025 I915_READ(fdi_rx_reg);
2029 /* still set train pattern 1 */
2030 temp = I915_READ(fdi_tx_reg);
2031 temp &= ~FDI_LINK_TRAIN_NONE;
2032 temp |= FDI_LINK_TRAIN_PATTERN_1;
2033 I915_WRITE(fdi_tx_reg, temp);
2034 POSTING_READ(fdi_tx_reg);
2036 temp = I915_READ(fdi_rx_reg);
2037 if (HAS_PCH_CPT(dev)) {
2038 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2039 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2041 temp &= ~FDI_LINK_TRAIN_NONE;
2042 temp |= FDI_LINK_TRAIN_PATTERN_1;
2044 I915_WRITE(fdi_rx_reg, temp);
2045 POSTING_READ(fdi_rx_reg);
2049 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2050 temp = I915_READ(PCH_LVDS);
2051 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2052 I915_READ(PCH_LVDS);
2056 /* disable PCH transcoder */
2057 temp = I915_READ(transconf_reg);
2058 if ((temp & TRANS_ENABLE) != 0) {
2059 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2060 I915_READ(transconf_reg);
2062 /* wait for PCH transcoder off, transcoder state */
2063 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2069 DRM_DEBUG_KMS("transcoder %d off "
2076 temp = I915_READ(transconf_reg);
2077 /* BPC in transcoder is consistent with that in pipeconf */
2078 temp &= ~PIPE_BPC_MASK;
2080 I915_WRITE(transconf_reg, temp);
2081 I915_READ(transconf_reg);
2084 if (HAS_PCH_CPT(dev)) {
2085 /* disable TRANS_DP_CTL */
2086 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2089 reg = I915_READ(trans_dp_ctl);
2090 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2091 I915_WRITE(trans_dp_ctl, reg);
2092 POSTING_READ(trans_dp_ctl);
2094 /* disable DPLL_SEL */
2095 temp = I915_READ(PCH_DPLL_SEL);
2096 if (trans_dpll_sel == 0)
2097 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2099 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2100 I915_WRITE(PCH_DPLL_SEL, temp);
2101 I915_READ(PCH_DPLL_SEL);
2105 /* disable PCH DPLL */
2106 temp = I915_READ(pch_dpll_reg);
2107 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2108 I915_READ(pch_dpll_reg);
2111 ironlake_disable_pll_edp(crtc);
2114 /* Switch from PCDclk to Rawclk */
2115 temp = I915_READ(fdi_rx_reg);
2116 temp &= ~FDI_SEL_PCDCLK;
2117 I915_WRITE(fdi_rx_reg, temp);
2118 I915_READ(fdi_rx_reg);
2120 /* Disable CPU FDI TX PLL */
2121 temp = I915_READ(fdi_tx_reg);
2122 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2123 I915_READ(fdi_tx_reg);
2126 temp = I915_READ(fdi_rx_reg);
2127 temp &= ~FDI_RX_PLL_ENABLE;
2128 I915_WRITE(fdi_rx_reg, temp);
2129 I915_READ(fdi_rx_reg);
2131 /* Wait for the clocks to turn off. */
2137 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2139 struct intel_overlay *overlay;
2142 if (!enable && intel_crtc->overlay) {
2143 overlay = intel_crtc->overlay;
2144 mutex_lock(&overlay->dev->struct_mutex);
2146 ret = intel_overlay_switch_off(overlay);
2150 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2152 /* overlay doesn't react anymore. Usually
2153 * results in a black screen and an unkillable
2156 overlay->hw_wedged = HW_WEDGED;
2160 mutex_unlock(&overlay->dev->struct_mutex);
2162 /* Let userspace switch the overlay on again. In most cases userspace
2163 * has to recompute where to put it anyway. */
2168 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2170 struct drm_device *dev = crtc->dev;
2171 struct drm_i915_private *dev_priv = dev->dev_private;
2172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2173 int pipe = intel_crtc->pipe;
2174 int plane = intel_crtc->plane;
2175 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2176 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2177 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2178 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2181 /* XXX: When our outputs are all unaware of DPMS modes other than off
2182 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2185 case DRM_MODE_DPMS_ON:
2186 case DRM_MODE_DPMS_STANDBY:
2187 case DRM_MODE_DPMS_SUSPEND:
2188 intel_update_watermarks(dev);
2190 /* Enable the DPLL */
2191 temp = I915_READ(dpll_reg);
2192 if ((temp & DPLL_VCO_ENABLE) == 0) {
2193 I915_WRITE(dpll_reg, temp);
2194 I915_READ(dpll_reg);
2195 /* Wait for the clocks to stabilize. */
2197 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2198 I915_READ(dpll_reg);
2199 /* Wait for the clocks to stabilize. */
2201 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2202 I915_READ(dpll_reg);
2203 /* Wait for the clocks to stabilize. */
2207 /* Enable the pipe */
2208 temp = I915_READ(pipeconf_reg);
2209 if ((temp & PIPEACONF_ENABLE) == 0)
2210 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2212 /* Enable the plane */
2213 temp = I915_READ(dspcntr_reg);
2214 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2215 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2216 /* Flush the plane changes */
2217 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2220 intel_crtc_load_lut(crtc);
2222 if ((IS_I965G(dev) || plane == 0))
2223 intel_update_fbc(crtc, &crtc->mode);
2225 /* Give the overlay scaler a chance to enable if it's on this pipe */
2226 intel_crtc_dpms_overlay(intel_crtc, true);
2228 case DRM_MODE_DPMS_OFF:
2229 intel_update_watermarks(dev);
2231 /* Give the overlay scaler a chance to disable if it's on this pipe */
2232 intel_crtc_dpms_overlay(intel_crtc, false);
2233 drm_vblank_off(dev, pipe);
2235 if (dev_priv->cfb_plane == plane &&
2236 dev_priv->display.disable_fbc)
2237 dev_priv->display.disable_fbc(dev);
2239 /* Disable the VGA plane that we never use */
2240 i915_disable_vga(dev);
2242 /* Disable display plane */
2243 temp = I915_READ(dspcntr_reg);
2244 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2245 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2246 /* Flush the plane changes */
2247 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2248 I915_READ(dspbase_reg);
2251 if (!IS_I9XX(dev)) {
2252 /* Wait for vblank for the disable to take effect */
2253 intel_wait_for_vblank(dev);
2256 /* Next, disable display pipes */
2257 temp = I915_READ(pipeconf_reg);
2258 if ((temp & PIPEACONF_ENABLE) != 0) {
2259 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2260 I915_READ(pipeconf_reg);
2263 /* Wait for vblank for the disable to take effect. */
2264 intel_wait_for_vblank(dev);
2266 temp = I915_READ(dpll_reg);
2267 if ((temp & DPLL_VCO_ENABLE) != 0) {
2268 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2269 I915_READ(dpll_reg);
2272 /* Wait for the clocks to turn off. */
2279 * Sets the power management mode of the pipe and plane.
2281 * This code should probably grow support for turning the cursor off and back
2282 * on appropriately at the same time as we're turning the pipe off/on.
2284 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2286 struct drm_device *dev = crtc->dev;
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288 struct drm_i915_master_private *master_priv;
2289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290 int pipe = intel_crtc->pipe;
2293 dev_priv->display.dpms(crtc, mode);
2295 intel_crtc->dpms_mode = mode;
2297 if (!dev->primary->master)
2300 master_priv = dev->primary->master->driver_priv;
2301 if (!master_priv->sarea_priv)
2304 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2308 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2309 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2312 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2313 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2316 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2321 static void intel_crtc_prepare (struct drm_crtc *crtc)
2323 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2324 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2327 static void intel_crtc_commit (struct drm_crtc *crtc)
2329 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2330 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2333 void intel_encoder_prepare (struct drm_encoder *encoder)
2335 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2336 /* lvds has its own version of prepare see intel_lvds_prepare */
2337 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2340 void intel_encoder_commit (struct drm_encoder *encoder)
2342 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2343 /* lvds has its own version of commit see intel_lvds_commit */
2344 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2347 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2348 struct drm_display_mode *mode,
2349 struct drm_display_mode *adjusted_mode)
2351 struct drm_device *dev = crtc->dev;
2352 if (HAS_PCH_SPLIT(dev)) {
2353 /* FDI link clock is fixed at 2.7G */
2354 if (mode->clock * 3 > 27000 * 4)
2355 return MODE_CLOCK_HIGH;
2358 drm_mode_set_crtcinfo(adjusted_mode, 0);
2362 static int i945_get_display_clock_speed(struct drm_device *dev)
2367 static int i915_get_display_clock_speed(struct drm_device *dev)
2372 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2377 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2381 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2383 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2386 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2387 case GC_DISPLAY_CLOCK_333_MHZ:
2390 case GC_DISPLAY_CLOCK_190_200_MHZ:
2396 static int i865_get_display_clock_speed(struct drm_device *dev)
2401 static int i855_get_display_clock_speed(struct drm_device *dev)
2404 /* Assume that the hardware is in the high speed state. This
2405 * should be the default.
2407 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2408 case GC_CLOCK_133_200:
2409 case GC_CLOCK_100_200:
2411 case GC_CLOCK_166_250:
2413 case GC_CLOCK_100_133:
2417 /* Shouldn't happen */
2421 static int i830_get_display_clock_speed(struct drm_device *dev)
2427 * Return the pipe currently connected to the panel fitter,
2428 * or -1 if the panel fitter is not present or not in use
2430 int intel_panel_fitter_pipe (struct drm_device *dev)
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2435 /* i830 doesn't have a panel fitter */
2439 pfit_control = I915_READ(PFIT_CONTROL);
2441 /* See if the panel fitter is in use */
2442 if ((pfit_control & PFIT_ENABLE) == 0)
2445 /* 965 can place panel fitter on either pipe */
2447 return (pfit_control >> 29) & 0x3;
2449 /* older chips can only use pipe 1 */
2462 fdi_reduce_ratio(u32 *num, u32 *den)
2464 while (*num > 0xffffff || *den > 0xffffff) {
2470 #define DATA_N 0x800000
2471 #define LINK_N 0x80000
2474 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2475 int link_clock, struct fdi_m_n *m_n)
2479 m_n->tu = 64; /* default size */
2481 temp = (u64) DATA_N * pixel_clock;
2482 temp = div_u64(temp, link_clock);
2483 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2484 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2485 m_n->gmch_n = DATA_N;
2486 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2488 temp = (u64) LINK_N * pixel_clock;
2489 m_n->link_m = div_u64(temp, link_clock);
2490 m_n->link_n = LINK_N;
2491 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2495 struct intel_watermark_params {
2496 unsigned long fifo_size;
2497 unsigned long max_wm;
2498 unsigned long default_wm;
2499 unsigned long guard_size;
2500 unsigned long cacheline_size;
2503 /* Pineview has different values for various configs */
2504 static struct intel_watermark_params pineview_display_wm = {
2505 PINEVIEW_DISPLAY_FIFO,
2509 PINEVIEW_FIFO_LINE_SIZE
2511 static struct intel_watermark_params pineview_display_hplloff_wm = {
2512 PINEVIEW_DISPLAY_FIFO,
2514 PINEVIEW_DFT_HPLLOFF_WM,
2516 PINEVIEW_FIFO_LINE_SIZE
2518 static struct intel_watermark_params pineview_cursor_wm = {
2519 PINEVIEW_CURSOR_FIFO,
2520 PINEVIEW_CURSOR_MAX_WM,
2521 PINEVIEW_CURSOR_DFT_WM,
2522 PINEVIEW_CURSOR_GUARD_WM,
2523 PINEVIEW_FIFO_LINE_SIZE,
2525 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2526 PINEVIEW_CURSOR_FIFO,
2527 PINEVIEW_CURSOR_MAX_WM,
2528 PINEVIEW_CURSOR_DFT_WM,
2529 PINEVIEW_CURSOR_GUARD_WM,
2530 PINEVIEW_FIFO_LINE_SIZE
2532 static struct intel_watermark_params g4x_wm_info = {
2539 static struct intel_watermark_params i945_wm_info = {
2546 static struct intel_watermark_params i915_wm_info = {
2553 static struct intel_watermark_params i855_wm_info = {
2560 static struct intel_watermark_params i830_wm_info = {
2568 static struct intel_watermark_params ironlake_display_wm_info = {
2576 static struct intel_watermark_params ironlake_display_srwm_info = {
2577 ILK_DISPLAY_SR_FIFO,
2578 ILK_DISPLAY_MAX_SRWM,
2579 ILK_DISPLAY_DFT_SRWM,
2584 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2586 ILK_CURSOR_MAX_SRWM,
2587 ILK_CURSOR_DFT_SRWM,
2593 * intel_calculate_wm - calculate watermark level
2594 * @clock_in_khz: pixel clock
2595 * @wm: chip FIFO params
2596 * @pixel_size: display pixel size
2597 * @latency_ns: memory latency for the platform
2599 * Calculate the watermark level (the level at which the display plane will
2600 * start fetching from memory again). Each chip has a different display
2601 * FIFO size and allocation, so the caller needs to figure that out and pass
2602 * in the correct intel_watermark_params structure.
2604 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2605 * on the pixel size. When it reaches the watermark level, it'll start
2606 * fetching FIFO line sized based chunks from memory until the FIFO fills
2607 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2608 * will occur, and a display engine hang could result.
2610 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2611 struct intel_watermark_params *wm,
2613 unsigned long latency_ns)
2615 long entries_required, wm_size;
2618 * Note: we need to make sure we don't overflow for various clock &
2620 * clocks go from a few thousand to several hundred thousand.
2621 * latency is usually a few thousand
2623 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2625 entries_required /= wm->cacheline_size;
2627 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2629 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2631 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2633 /* Don't promote wm_size to unsigned... */
2634 if (wm_size > (long)wm->max_wm)
2635 wm_size = wm->max_wm;
2637 wm_size = wm->default_wm;
2641 struct cxsr_latency {
2643 unsigned long fsb_freq;
2644 unsigned long mem_freq;
2645 unsigned long display_sr;
2646 unsigned long display_hpll_disable;
2647 unsigned long cursor_sr;
2648 unsigned long cursor_hpll_disable;
2651 static struct cxsr_latency cxsr_latency_table[] = {
2652 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2653 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2654 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2656 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2657 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2658 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2660 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2661 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2662 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2664 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2665 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2666 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2668 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2669 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2670 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2672 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2673 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2674 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2677 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2681 struct cxsr_latency *latency;
2683 if (fsb == 0 || mem == 0)
2686 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2687 latency = &cxsr_latency_table[i];
2688 if (is_desktop == latency->is_desktop &&
2689 fsb == latency->fsb_freq && mem == latency->mem_freq)
2693 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2698 static void pineview_disable_cxsr(struct drm_device *dev)
2700 struct drm_i915_private *dev_priv = dev->dev_private;
2703 /* deactivate cxsr */
2704 reg = I915_READ(DSPFW3);
2705 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2706 I915_WRITE(DSPFW3, reg);
2707 DRM_INFO("Big FIFO is disabled\n");
2711 * Latency for FIFO fetches is dependent on several factors:
2712 * - memory configuration (speed, channels)
2714 * - current MCH state
2715 * It can be fairly high in some situations, so here we assume a fairly
2716 * pessimal value. It's a tradeoff between extra memory fetches (if we
2717 * set this value too high, the FIFO will fetch frequently to stay full)
2718 * and power consumption (set it too low to save power and we might see
2719 * FIFO underruns and display "flicker").
2721 * A value of 5us seems to be a good balance; safe for very low end
2722 * platforms but not overly aggressive on lower latency configs.
2724 static const int latency_ns = 5000;
2726 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 uint32_t dsparb = I915_READ(DSPARB);
2733 size = dsparb & 0x7f;
2735 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2738 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2739 plane ? "B" : "A", size);
2744 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 uint32_t dsparb = I915_READ(DSPARB);
2751 size = dsparb & 0x1ff;
2753 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2755 size >>= 1; /* Convert to cachelines */
2757 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2758 plane ? "B" : "A", size);
2763 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2765 struct drm_i915_private *dev_priv = dev->dev_private;
2766 uint32_t dsparb = I915_READ(DSPARB);
2769 size = dsparb & 0x7f;
2770 size >>= 2; /* Convert to cachelines */
2772 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2779 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 uint32_t dsparb = I915_READ(DSPARB);
2785 size = dsparb & 0x7f;
2786 size >>= 1; /* Convert to cachelines */
2788 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2789 plane ? "B" : "A", size);
2794 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2795 int planeb_clock, int sr_hdisplay, int pixel_size)
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct cxsr_latency *latency;
2803 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2804 dev_priv->mem_freq);
2806 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2807 pineview_disable_cxsr(dev);
2811 if (!planea_clock || !planeb_clock) {
2812 sr_clock = planea_clock ? planea_clock : planeb_clock;
2815 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2816 pixel_size, latency->display_sr);
2817 reg = I915_READ(DSPFW1);
2818 reg &= ~DSPFW_SR_MASK;
2819 reg |= wm << DSPFW_SR_SHIFT;
2820 I915_WRITE(DSPFW1, reg);
2821 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2824 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2825 pixel_size, latency->cursor_sr);
2826 reg = I915_READ(DSPFW3);
2827 reg &= ~DSPFW_CURSOR_SR_MASK;
2828 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2829 I915_WRITE(DSPFW3, reg);
2831 /* Display HPLL off SR */
2832 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2833 pixel_size, latency->display_hpll_disable);
2834 reg = I915_READ(DSPFW3);
2835 reg &= ~DSPFW_HPLL_SR_MASK;
2836 reg |= wm & DSPFW_HPLL_SR_MASK;
2837 I915_WRITE(DSPFW3, reg);
2839 /* cursor HPLL off SR */
2840 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2841 pixel_size, latency->cursor_hpll_disable);
2842 reg = I915_READ(DSPFW3);
2843 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2844 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2845 I915_WRITE(DSPFW3, reg);
2846 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2849 reg = I915_READ(DSPFW3);
2850 reg |= PINEVIEW_SELF_REFRESH_EN;
2851 I915_WRITE(DSPFW3, reg);
2852 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2854 pineview_disable_cxsr(dev);
2855 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2859 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2860 int planeb_clock, int sr_hdisplay, int pixel_size)
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 int total_size, cacheline_size;
2864 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2865 struct intel_watermark_params planea_params, planeb_params;
2866 unsigned long line_time_us;
2867 int sr_clock, sr_entries = 0, entries_required;
2869 /* Create copies of the base settings for each pipe */
2870 planea_params = planeb_params = g4x_wm_info;
2872 /* Grab a couple of global values before we overwrite them */
2873 total_size = planea_params.fifo_size;
2874 cacheline_size = planea_params.cacheline_size;
2877 * Note: we need to make sure we don't overflow for various clock &
2879 * clocks go from a few thousand to several hundred thousand.
2880 * latency is usually a few thousand
2882 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2884 entries_required /= G4X_FIFO_LINE_SIZE;
2885 planea_wm = entries_required + planea_params.guard_size;
2887 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2889 entries_required /= G4X_FIFO_LINE_SIZE;
2890 planeb_wm = entries_required + planeb_params.guard_size;
2892 cursora_wm = cursorb_wm = 16;
2895 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2897 /* Calc sr entries for one plane configs */
2898 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2899 /* self-refresh has much higher latency */
2900 static const int sr_latency_ns = 12000;
2902 sr_clock = planea_clock ? planea_clock : planeb_clock;
2903 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2905 /* Use ns/us then divide to preserve precision */
2906 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2907 pixel_size * sr_hdisplay) / 1000;
2908 sr_entries = roundup(sr_entries / cacheline_size, 1);
2909 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2910 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2912 /* Turn off self refresh if both pipes are enabled */
2913 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2917 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2918 planea_wm, planeb_wm, sr_entries);
2923 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2924 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2925 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2926 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2927 (cursora_wm << DSPFW_CURSORA_SHIFT));
2928 /* HPLL off in SR has some issues on G4x... disable it */
2929 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2930 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2933 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2934 int planeb_clock, int sr_hdisplay, int pixel_size)
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 unsigned long line_time_us;
2938 int sr_clock, sr_entries, srwm = 1;
2940 /* Calc sr entries for one plane configs */
2941 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2942 /* self-refresh has much higher latency */
2943 static const int sr_latency_ns = 12000;
2945 sr_clock = planea_clock ? planea_clock : planeb_clock;
2946 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2948 /* Use ns/us then divide to preserve precision */
2949 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2950 pixel_size * sr_hdisplay) / 1000;
2951 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2952 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2953 srwm = I945_FIFO_SIZE - sr_entries;
2957 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2959 /* Turn off self refresh if both pipes are enabled */
2960 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2964 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2967 /* 965 has limitations... */
2968 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2970 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2973 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2974 int planeb_clock, int sr_hdisplay, int pixel_size)
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2979 int total_size, cacheline_size, cwm, srwm = 1;
2980 int planea_wm, planeb_wm;
2981 struct intel_watermark_params planea_params, planeb_params;
2982 unsigned long line_time_us;
2983 int sr_clock, sr_entries = 0;
2985 /* Create copies of the base settings for each pipe */
2986 if (IS_I965GM(dev) || IS_I945GM(dev))
2987 planea_params = planeb_params = i945_wm_info;
2988 else if (IS_I9XX(dev))
2989 planea_params = planeb_params = i915_wm_info;
2991 planea_params = planeb_params = i855_wm_info;
2993 /* Grab a couple of global values before we overwrite them */
2994 total_size = planea_params.fifo_size;
2995 cacheline_size = planea_params.cacheline_size;
2997 /* Update per-plane FIFO sizes */
2998 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2999 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3001 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3002 pixel_size, latency_ns);
3003 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3004 pixel_size, latency_ns);
3005 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3008 * Overlay gets an aggressive default since video jitter is bad.
3012 /* Calc sr entries for one plane configs */
3013 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3014 (!planea_clock || !planeb_clock)) {
3015 /* self-refresh has much higher latency */
3016 static const int sr_latency_ns = 6000;
3018 sr_clock = planea_clock ? planea_clock : planeb_clock;
3019 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3021 /* Use ns/us then divide to preserve precision */
3022 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3023 pixel_size * sr_hdisplay) / 1000;
3024 sr_entries = roundup(sr_entries / cacheline_size, 1);
3025 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3026 srwm = total_size - sr_entries;
3030 if (IS_I945G(dev) || IS_I945GM(dev))
3031 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3032 else if (IS_I915GM(dev)) {
3033 /* 915M has a smaller SRWM field */
3034 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3035 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3038 /* Turn off self refresh if both pipes are enabled */
3039 if (IS_I945G(dev) || IS_I945GM(dev)) {
3040 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3042 } else if (IS_I915GM(dev)) {
3043 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3047 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3048 planea_wm, planeb_wm, cwm, srwm);
3050 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3051 fwater_hi = (cwm & 0x1f);
3053 /* Set request length to 8 cachelines per fetch */
3054 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3055 fwater_hi = fwater_hi | (1 << 8);
3057 I915_WRITE(FW_BLC, fwater_lo);
3058 I915_WRITE(FW_BLC2, fwater_hi);
3061 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3062 int unused2, int pixel_size)
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3068 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3070 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3071 pixel_size, latency_ns);
3072 fwater_lo |= (3<<8) | planea_wm;
3074 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3076 I915_WRITE(FW_BLC, fwater_lo);
3079 #define ILK_LP0_PLANE_LATENCY 700
3081 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3082 int planeb_clock, int sr_hdisplay, int pixel_size)
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3086 int sr_wm, cursor_wm;
3087 unsigned long line_time_us;
3088 int sr_clock, entries_required;
3091 /* Calculate and update the watermark for plane A */
3093 entries_required = ((planea_clock / 1000) * pixel_size *
3094 ILK_LP0_PLANE_LATENCY) / 1000;
3095 entries_required = DIV_ROUND_UP(entries_required,
3096 ironlake_display_wm_info.cacheline_size);
3097 planea_wm = entries_required +
3098 ironlake_display_wm_info.guard_size;
3100 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3101 planea_wm = ironlake_display_wm_info.max_wm;
3104 reg_value = I915_READ(WM0_PIPEA_ILK);
3105 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3106 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3107 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3108 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3109 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3110 "cursor: %d\n", planea_wm, cursora_wm);
3112 /* Calculate and update the watermark for plane B */
3114 entries_required = ((planeb_clock / 1000) * pixel_size *
3115 ILK_LP0_PLANE_LATENCY) / 1000;
3116 entries_required = DIV_ROUND_UP(entries_required,
3117 ironlake_display_wm_info.cacheline_size);
3118 planeb_wm = entries_required +
3119 ironlake_display_wm_info.guard_size;
3121 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3122 planeb_wm = ironlake_display_wm_info.max_wm;
3125 reg_value = I915_READ(WM0_PIPEB_ILK);
3126 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3127 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3128 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3129 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3130 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3131 "cursor: %d\n", planeb_wm, cursorb_wm);
3135 * Calculate and update the self-refresh watermark only when one
3136 * display plane is used.
3138 if (!planea_clock || !planeb_clock) {
3140 /* Read the self-refresh latency. The unit is 0.5us */
3141 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3143 sr_clock = planea_clock ? planea_clock : planeb_clock;
3144 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3146 /* Use ns/us then divide to preserve precision */
3147 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3150 /* calculate the self-refresh watermark for display plane */
3151 entries_required = line_count * sr_hdisplay * pixel_size;
3152 entries_required = DIV_ROUND_UP(entries_required,
3153 ironlake_display_srwm_info.cacheline_size);
3154 sr_wm = entries_required +
3155 ironlake_display_srwm_info.guard_size;
3157 /* calculate the self-refresh watermark for display cursor */
3158 entries_required = line_count * pixel_size * 64;
3159 entries_required = DIV_ROUND_UP(entries_required,
3160 ironlake_cursor_srwm_info.cacheline_size);
3161 cursor_wm = entries_required +
3162 ironlake_cursor_srwm_info.guard_size;
3164 /* configure watermark and enable self-refresh */
3165 reg_value = I915_READ(WM1_LP_ILK);
3166 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3167 WM1_LP_CURSOR_MASK);
3168 reg_value |= WM1_LP_SR_EN |
3169 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3170 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3172 I915_WRITE(WM1_LP_ILK, reg_value);
3173 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3174 "cursor %d\n", sr_wm, cursor_wm);
3177 /* Turn off self refresh if both pipes are enabled */
3178 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3182 * intel_update_watermarks - update FIFO watermark values based on current modes
3184 * Calculate watermark values for the various WM regs based on current mode
3185 * and plane configuration.
3187 * There are several cases to deal with here:
3188 * - normal (i.e. non-self-refresh)
3189 * - self-refresh (SR) mode
3190 * - lines are large relative to FIFO size (buffer can hold up to 2)
3191 * - lines are small relative to FIFO size (buffer can hold more than 2
3192 * lines), so need to account for TLB latency
3194 * The normal calculation is:
3195 * watermark = dotclock * bytes per pixel * latency
3196 * where latency is platform & configuration dependent (we assume pessimal
3199 * The SR calculation is:
3200 * watermark = (trunc(latency/line time)+1) * surface width *
3203 * line time = htotal / dotclock
3204 * and latency is assumed to be high, as above.
3206 * The final value programmed to the register should always be rounded up,
3207 * and include an extra 2 entries to account for clock crossings.
3209 * We don't use the sprite, so we can ignore that. And on Crestline we have
3210 * to set the non-SR watermarks to 8.
3212 static void intel_update_watermarks(struct drm_device *dev)
3214 struct drm_i915_private *dev_priv = dev->dev_private;
3215 struct drm_crtc *crtc;
3216 struct intel_crtc *intel_crtc;
3217 int sr_hdisplay = 0;
3218 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3219 int enabled = 0, pixel_size = 0;
3221 if (!dev_priv->display.update_wm)
3224 /* Get the clock config from both planes */
3225 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3226 intel_crtc = to_intel_crtc(crtc);
3227 if (crtc->enabled) {
3229 if (intel_crtc->plane == 0) {
3230 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3231 intel_crtc->pipe, crtc->mode.clock);
3232 planea_clock = crtc->mode.clock;
3234 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3235 intel_crtc->pipe, crtc->mode.clock);
3236 planeb_clock = crtc->mode.clock;
3238 sr_hdisplay = crtc->mode.hdisplay;
3239 sr_clock = crtc->mode.clock;
3241 pixel_size = crtc->fb->bits_per_pixel / 8;
3243 pixel_size = 4; /* by default */
3250 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3251 sr_hdisplay, pixel_size);
3254 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3255 struct drm_display_mode *mode,
3256 struct drm_display_mode *adjusted_mode,
3258 struct drm_framebuffer *old_fb)
3260 struct drm_device *dev = crtc->dev;
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3263 int pipe = intel_crtc->pipe;
3264 int plane = intel_crtc->plane;
3265 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3266 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3267 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3268 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3269 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3270 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3271 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3272 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3273 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3274 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3275 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3276 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3277 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3278 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3279 int refclk, num_connectors = 0;
3280 intel_clock_t clock, reduced_clock;
3281 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3282 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3283 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3284 bool is_edp = false;
3285 struct drm_mode_config *mode_config = &dev->mode_config;
3286 struct drm_encoder *encoder;
3287 struct intel_encoder *intel_encoder = NULL;
3288 const intel_limit_t *limit;
3290 struct fdi_m_n m_n = {0};
3291 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3292 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3293 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3294 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3295 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3296 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3297 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3298 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3299 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3300 int lvds_reg = LVDS;
3302 int sdvo_pixel_multiply;
3305 drm_vblank_pre_modeset(dev, pipe);
3307 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3309 if (!encoder || encoder->crtc != crtc)
3312 intel_encoder = enc_to_intel_encoder(encoder);
3314 switch (intel_encoder->type) {
3315 case INTEL_OUTPUT_LVDS:
3318 case INTEL_OUTPUT_SDVO:
3319 case INTEL_OUTPUT_HDMI:
3321 if (intel_encoder->needs_tv_clock)
3324 case INTEL_OUTPUT_DVO:
3327 case INTEL_OUTPUT_TVOUT:
3330 case INTEL_OUTPUT_ANALOG:
3333 case INTEL_OUTPUT_DISPLAYPORT:
3336 case INTEL_OUTPUT_EDP:
3344 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3345 refclk = dev_priv->lvds_ssc_freq * 1000;
3346 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3348 } else if (IS_I9XX(dev)) {
3350 if (HAS_PCH_SPLIT(dev))
3351 refclk = 120000; /* 120Mhz refclk */
3358 * Returns a set of divisors for the desired target clock with the given
3359 * refclk, or FALSE. The returned values represent the clock equation:
3360 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3362 limit = intel_limit(crtc);
3363 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3365 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3366 drm_vblank_post_modeset(dev, pipe);
3370 if (is_lvds && dev_priv->lvds_downclock_avail) {
3371 has_reduced_clock = limit->find_pll(limit, crtc,
3372 dev_priv->lvds_downclock,
3375 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3377 * If the different P is found, it means that we can't
3378 * switch the display clock by using the FP0/FP1.
3379 * In such case we will disable the LVDS downclock
3382 DRM_DEBUG_KMS("Different P is found for "
3383 "LVDS clock/downclock\n");
3384 has_reduced_clock = 0;
3387 /* SDVO TV has fixed PLL values depend on its clock range,
3388 this mirrors vbios setting. */
3389 if (is_sdvo && is_tv) {
3390 if (adjusted_mode->clock >= 100000
3391 && adjusted_mode->clock < 140500) {
3397 } else if (adjusted_mode->clock >= 140500
3398 && adjusted_mode->clock <= 200000) {
3408 if (HAS_PCH_SPLIT(dev)) {
3409 int lane = 0, link_bw, bpp;
3410 /* eDP doesn't require FDI link, so just set DP M/N
3411 according to current link config */
3413 target_clock = mode->clock;
3414 intel_edp_link_config(intel_encoder,
3417 /* DP over FDI requires target mode clock
3418 instead of link clock */
3420 target_clock = mode->clock;
3422 target_clock = adjusted_mode->clock;
3426 /* determine panel color depth */
3427 temp = I915_READ(pipeconf_reg);
3428 temp &= ~PIPE_BPC_MASK;
3430 int lvds_reg = I915_READ(PCH_LVDS);
3431 /* the BPC will be 6 if it is 18-bit LVDS panel */
3432 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3436 } else if (is_edp) {
3437 switch (dev_priv->edp_bpp/3) {
3453 I915_WRITE(pipeconf_reg, temp);
3454 I915_READ(pipeconf_reg);
3456 switch (temp & PIPE_BPC_MASK) {
3470 DRM_ERROR("unknown pipe bpc value\n");
3476 * Account for spread spectrum to avoid
3477 * oversubscribing the link. Max center spread
3478 * is 2.5%; use 5% for safety's sake.
3480 u32 bps = target_clock * bpp * 21 / 20;
3481 lane = bps / (link_bw * 8) + 1;
3484 intel_crtc->fdi_lanes = lane;
3486 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3489 /* Ironlake: try to setup display ref clock before DPLL
3490 * enabling. This is only under driver's control after
3491 * PCH B stepping, previous chipset stepping should be
3492 * ignoring this setting.
3494 if (HAS_PCH_SPLIT(dev)) {
3495 temp = I915_READ(PCH_DREF_CONTROL);
3496 /* Always enable nonspread source */
3497 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3498 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3499 I915_WRITE(PCH_DREF_CONTROL, temp);
3500 POSTING_READ(PCH_DREF_CONTROL);
3502 temp &= ~DREF_SSC_SOURCE_MASK;
3503 temp |= DREF_SSC_SOURCE_ENABLE;
3504 I915_WRITE(PCH_DREF_CONTROL, temp);
3505 POSTING_READ(PCH_DREF_CONTROL);
3510 if (dev_priv->lvds_use_ssc) {
3511 temp |= DREF_SSC1_ENABLE;
3512 I915_WRITE(PCH_DREF_CONTROL, temp);
3513 POSTING_READ(PCH_DREF_CONTROL);
3517 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3518 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3519 I915_WRITE(PCH_DREF_CONTROL, temp);
3520 POSTING_READ(PCH_DREF_CONTROL);
3522 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3523 I915_WRITE(PCH_DREF_CONTROL, temp);
3524 POSTING_READ(PCH_DREF_CONTROL);
3529 if (IS_PINEVIEW(dev)) {
3530 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3531 if (has_reduced_clock)
3532 fp2 = (1 << reduced_clock.n) << 16 |
3533 reduced_clock.m1 << 8 | reduced_clock.m2;
3535 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3536 if (has_reduced_clock)
3537 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3541 if (!HAS_PCH_SPLIT(dev))
3542 dpll = DPLL_VGA_MODE_DIS;
3546 dpll |= DPLLB_MODE_LVDS;
3548 dpll |= DPLLB_MODE_DAC_SERIAL;
3550 dpll |= DPLL_DVO_HIGH_SPEED;
3551 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3552 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3553 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3554 else if (HAS_PCH_SPLIT(dev))
3555 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3558 dpll |= DPLL_DVO_HIGH_SPEED;
3560 /* compute bitmask from p1 value */
3561 if (IS_PINEVIEW(dev))
3562 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3564 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3566 if (HAS_PCH_SPLIT(dev))
3567 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3568 if (IS_G4X(dev) && has_reduced_clock)
3569 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3573 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3576 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3579 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3582 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3585 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3586 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3589 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3592 dpll |= PLL_P1_DIVIDE_BY_TWO;
3594 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3596 dpll |= PLL_P2_DIVIDE_BY_4;
3600 if (is_sdvo && is_tv)
3601 dpll |= PLL_REF_INPUT_TVCLKINBC;
3603 /* XXX: just matching BIOS for now */
3604 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3606 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3607 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3609 dpll |= PLL_REF_INPUT_DREFCLK;
3611 /* setup pipeconf */
3612 pipeconf = I915_READ(pipeconf_reg);
3614 /* Set up the display plane register */
3615 dspcntr = DISPPLANE_GAMMA_ENABLE;
3617 /* Ironlake's plane is forced to pipe, bit 24 is to
3618 enable color space conversion */
3619 if (!HAS_PCH_SPLIT(dev)) {
3621 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3623 dspcntr |= DISPPLANE_SEL_PIPE_B;
3626 if (pipe == 0 && !IS_I965G(dev)) {
3627 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3630 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3634 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3635 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3637 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3640 /* Disable the panel fitter if it was on our pipe */
3641 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3642 I915_WRITE(PFIT_CONTROL, 0);
3644 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3645 drm_mode_debug_printmodeline(mode);
3647 /* assign to Ironlake registers */
3648 if (HAS_PCH_SPLIT(dev)) {
3649 fp_reg = pch_fp_reg;
3650 dpll_reg = pch_dpll_reg;
3654 ironlake_disable_pll_edp(crtc);
3655 } else if ((dpll & DPLL_VCO_ENABLE)) {
3656 I915_WRITE(fp_reg, fp);
3657 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3658 I915_READ(dpll_reg);
3662 /* enable transcoder DPLL */
3663 if (HAS_PCH_CPT(dev)) {
3664 temp = I915_READ(PCH_DPLL_SEL);
3665 if (trans_dpll_sel == 0)
3666 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3668 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3669 I915_WRITE(PCH_DPLL_SEL, temp);
3670 I915_READ(PCH_DPLL_SEL);
3674 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3675 * This is an exception to the general rule that mode_set doesn't turn
3681 if (HAS_PCH_SPLIT(dev))
3682 lvds_reg = PCH_LVDS;
3684 lvds = I915_READ(lvds_reg);
3685 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3687 if (HAS_PCH_CPT(dev))
3688 lvds |= PORT_TRANS_B_SEL_CPT;
3690 lvds |= LVDS_PIPEB_SELECT;
3692 if (HAS_PCH_CPT(dev))
3693 lvds &= ~PORT_TRANS_SEL_MASK;
3695 lvds &= ~LVDS_PIPEB_SELECT;
3697 /* set the corresponsding LVDS_BORDER bit */
3698 lvds |= dev_priv->lvds_border_bits;
3699 /* Set the B0-B3 data pairs corresponding to whether we're going to
3700 * set the DPLLs for dual-channel mode or not.
3703 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3705 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3707 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3708 * appropriately here, but we need to look more thoroughly into how
3709 * panels behave in the two modes.
3711 /* set the dithering flag */
3712 if (IS_I965G(dev)) {
3713 if (dev_priv->lvds_dither) {
3714 if (HAS_PCH_SPLIT(dev)) {
3715 pipeconf |= PIPE_ENABLE_DITHER;
3716 pipeconf |= PIPE_DITHER_TYPE_ST01;
3718 lvds |= LVDS_ENABLE_DITHER;
3720 if (HAS_PCH_SPLIT(dev)) {
3721 pipeconf &= ~PIPE_ENABLE_DITHER;
3722 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3724 lvds &= ~LVDS_ENABLE_DITHER;
3727 I915_WRITE(lvds_reg, lvds);
3728 I915_READ(lvds_reg);
3731 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3732 else if (HAS_PCH_SPLIT(dev)) {
3733 /* For non-DP output, clear any trans DP clock recovery setting.*/
3735 I915_WRITE(TRANSA_DATA_M1, 0);
3736 I915_WRITE(TRANSA_DATA_N1, 0);
3737 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3738 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3740 I915_WRITE(TRANSB_DATA_M1, 0);
3741 I915_WRITE(TRANSB_DATA_N1, 0);
3742 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3743 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3748 I915_WRITE(fp_reg, fp);
3749 I915_WRITE(dpll_reg, dpll);
3750 I915_READ(dpll_reg);
3751 /* Wait for the clocks to stabilize. */
3754 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3756 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3757 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3758 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3760 I915_WRITE(dpll_md_reg, 0);
3762 /* write it again -- the BIOS does, after all */
3763 I915_WRITE(dpll_reg, dpll);
3765 I915_READ(dpll_reg);
3766 /* Wait for the clocks to stabilize. */
3770 if (is_lvds && has_reduced_clock && i915_powersave) {
3771 I915_WRITE(fp_reg + 4, fp2);
3772 intel_crtc->lowfreq_avail = true;
3773 if (HAS_PIPE_CXSR(dev)) {
3774 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3775 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3778 I915_WRITE(fp_reg + 4, fp);
3779 intel_crtc->lowfreq_avail = false;
3780 if (HAS_PIPE_CXSR(dev)) {
3781 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3782 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3786 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3787 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3788 /* the chip adds 2 halflines automatically */
3789 adjusted_mode->crtc_vdisplay -= 1;
3790 adjusted_mode->crtc_vtotal -= 1;
3791 adjusted_mode->crtc_vblank_start -= 1;
3792 adjusted_mode->crtc_vblank_end -= 1;
3793 adjusted_mode->crtc_vsync_end -= 1;
3794 adjusted_mode->crtc_vsync_start -= 1;
3796 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
3798 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3799 ((adjusted_mode->crtc_htotal - 1) << 16));
3800 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3801 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3802 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3803 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3804 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3805 ((adjusted_mode->crtc_vtotal - 1) << 16));
3806 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3807 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3808 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3809 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3810 /* pipesrc and dspsize control the size that is scaled from, which should
3811 * always be the user's requested size.
3813 if (!HAS_PCH_SPLIT(dev)) {
3814 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3815 (mode->hdisplay - 1));
3816 I915_WRITE(dsppos_reg, 0);
3818 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3820 if (HAS_PCH_SPLIT(dev)) {
3821 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3822 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3823 I915_WRITE(link_m1_reg, m_n.link_m);
3824 I915_WRITE(link_n1_reg, m_n.link_n);
3827 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3829 /* enable FDI RX PLL too */
3830 temp = I915_READ(fdi_rx_reg);
3831 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3832 I915_READ(fdi_rx_reg);
3835 /* enable FDI TX PLL too */
3836 temp = I915_READ(fdi_tx_reg);
3837 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3838 I915_READ(fdi_tx_reg);
3840 /* enable FDI RX PCDCLK */
3841 temp = I915_READ(fdi_rx_reg);
3842 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3843 I915_READ(fdi_rx_reg);
3848 I915_WRITE(pipeconf_reg, pipeconf);
3849 I915_READ(pipeconf_reg);
3851 intel_wait_for_vblank(dev);
3853 if (IS_IRONLAKE(dev)) {
3854 /* enable address swizzle for tiling buffer */
3855 temp = I915_READ(DISP_ARB_CTL);
3856 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3859 I915_WRITE(dspcntr_reg, dspcntr);
3861 /* Flush the plane changes */
3862 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3864 if ((IS_I965G(dev) || plane == 0))
3865 intel_update_fbc(crtc, &crtc->mode);
3867 intel_update_watermarks(dev);
3869 drm_vblank_post_modeset(dev, pipe);
3874 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3875 void intel_crtc_load_lut(struct drm_crtc *crtc)
3877 struct drm_device *dev = crtc->dev;
3878 struct drm_i915_private *dev_priv = dev->dev_private;
3879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3880 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3883 /* The clocks have to be on to load the palette. */
3887 /* use legacy palette for Ironlake */
3888 if (HAS_PCH_SPLIT(dev))
3889 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3892 for (i = 0; i < 256; i++) {
3893 I915_WRITE(palreg + 4 * i,
3894 (intel_crtc->lut_r[i] << 16) |
3895 (intel_crtc->lut_g[i] << 8) |
3896 intel_crtc->lut_b[i]);
3900 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3901 struct drm_file *file_priv,
3903 uint32_t width, uint32_t height)
3905 struct drm_device *dev = crtc->dev;
3906 struct drm_i915_private *dev_priv = dev->dev_private;
3907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3908 struct drm_gem_object *bo;
3909 struct drm_i915_gem_object *obj_priv;
3910 int pipe = intel_crtc->pipe;
3911 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3912 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3913 uint32_t temp = I915_READ(control);
3917 DRM_DEBUG_KMS("\n");
3919 /* if we want to turn off the cursor ignore width and height */
3921 DRM_DEBUG_KMS("cursor off\n");
3922 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3923 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3924 temp |= CURSOR_MODE_DISABLE;
3926 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3930 mutex_lock(&dev->struct_mutex);
3934 /* Currently we only support 64x64 cursors */
3935 if (width != 64 || height != 64) {
3936 DRM_ERROR("we currently only support 64x64 cursors\n");
3940 bo = drm_gem_object_lookup(dev, file_priv, handle);
3944 obj_priv = to_intel_bo(bo);
3946 if (bo->size < width * height * 4) {
3947 DRM_ERROR("buffer is to small\n");
3952 /* we only need to pin inside GTT if cursor is non-phy */
3953 mutex_lock(&dev->struct_mutex);
3954 if (!dev_priv->info->cursor_needs_physical) {
3955 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3957 DRM_ERROR("failed to pin cursor bo\n");
3960 addr = obj_priv->gtt_offset;
3962 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3964 DRM_ERROR("failed to attach phys object\n");
3967 addr = obj_priv->phys_obj->handle->busaddr;
3971 I915_WRITE(CURSIZE, (height << 12) | width);
3973 /* Hooray for CUR*CNTR differences */
3974 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3975 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3976 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3977 temp |= (pipe << 28); /* Connect to correct pipe */
3979 temp &= ~(CURSOR_FORMAT_MASK);
3980 temp |= CURSOR_ENABLE;
3981 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3985 I915_WRITE(control, temp);
3986 I915_WRITE(base, addr);
3988 if (intel_crtc->cursor_bo) {
3989 if (dev_priv->info->cursor_needs_physical) {
3990 if (intel_crtc->cursor_bo != bo)
3991 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3993 i915_gem_object_unpin(intel_crtc->cursor_bo);
3994 drm_gem_object_unreference(intel_crtc->cursor_bo);
3997 mutex_unlock(&dev->struct_mutex);
3999 intel_crtc->cursor_addr = addr;
4000 intel_crtc->cursor_bo = bo;
4004 mutex_unlock(&dev->struct_mutex);
4006 drm_gem_object_unreference_unlocked(bo);
4010 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4012 struct drm_device *dev = crtc->dev;
4013 struct drm_i915_private *dev_priv = dev->dev_private;
4014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4015 struct intel_framebuffer *intel_fb;
4016 int pipe = intel_crtc->pipe;
4021 intel_fb = to_intel_framebuffer(crtc->fb);
4022 intel_mark_busy(dev, intel_fb->obj);
4026 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4030 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4034 temp |= x << CURSOR_X_SHIFT;
4035 temp |= y << CURSOR_Y_SHIFT;
4037 adder = intel_crtc->cursor_addr;
4038 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4039 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4044 /** Sets the color ramps on behalf of RandR */
4045 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4046 u16 blue, int regno)
4048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4050 intel_crtc->lut_r[regno] = red >> 8;
4051 intel_crtc->lut_g[regno] = green >> 8;
4052 intel_crtc->lut_b[regno] = blue >> 8;
4055 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4056 u16 *blue, int regno)
4058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4060 *red = intel_crtc->lut_r[regno] << 8;
4061 *green = intel_crtc->lut_g[regno] << 8;
4062 *blue = intel_crtc->lut_b[regno] << 8;
4065 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4066 u16 *blue, uint32_t size)
4068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4074 for (i = 0; i < 256; i++) {
4075 intel_crtc->lut_r[i] = red[i] >> 8;
4076 intel_crtc->lut_g[i] = green[i] >> 8;
4077 intel_crtc->lut_b[i] = blue[i] >> 8;
4080 intel_crtc_load_lut(crtc);
4084 * Get a pipe with a simple mode set on it for doing load-based monitor
4087 * It will be up to the load-detect code to adjust the pipe as appropriate for
4088 * its requirements. The pipe will be connected to no other encoders.
4090 * Currently this code will only succeed if there is a pipe with no encoders
4091 * configured for it. In the future, it could choose to temporarily disable
4092 * some outputs to free up a pipe for its use.
4094 * \return crtc, or NULL if no pipes are available.
4097 /* VESA 640x480x72Hz mode to set on the pipe */
4098 static struct drm_display_mode load_detect_mode = {
4099 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4100 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4103 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4104 struct drm_connector *connector,
4105 struct drm_display_mode *mode,
4108 struct intel_crtc *intel_crtc;
4109 struct drm_crtc *possible_crtc;
4110 struct drm_crtc *supported_crtc =NULL;
4111 struct drm_encoder *encoder = &intel_encoder->enc;
4112 struct drm_crtc *crtc = NULL;
4113 struct drm_device *dev = encoder->dev;
4114 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4115 struct drm_crtc_helper_funcs *crtc_funcs;
4119 * Algorithm gets a little messy:
4120 * - if the connector already has an assigned crtc, use it (but make
4121 * sure it's on first)
4122 * - try to find the first unused crtc that can drive this connector,
4123 * and use that if we find one
4124 * - if there are no unused crtcs available, try to use the first
4125 * one we found that supports the connector
4128 /* See if we already have a CRTC for this connector */
4129 if (encoder->crtc) {
4130 crtc = encoder->crtc;
4131 /* Make sure the crtc and connector are running */
4132 intel_crtc = to_intel_crtc(crtc);
4133 *dpms_mode = intel_crtc->dpms_mode;
4134 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4135 crtc_funcs = crtc->helper_private;
4136 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4137 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4142 /* Find an unused one (if possible) */
4143 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4145 if (!(encoder->possible_crtcs & (1 << i)))
4147 if (!possible_crtc->enabled) {
4148 crtc = possible_crtc;
4151 if (!supported_crtc)
4152 supported_crtc = possible_crtc;
4156 * If we didn't find an unused CRTC, don't use any.
4162 encoder->crtc = crtc;
4163 connector->encoder = encoder;
4164 intel_encoder->load_detect_temp = true;
4166 intel_crtc = to_intel_crtc(crtc);
4167 *dpms_mode = intel_crtc->dpms_mode;
4169 if (!crtc->enabled) {
4171 mode = &load_detect_mode;
4172 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4174 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4175 crtc_funcs = crtc->helper_private;
4176 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4179 /* Add this connector to the crtc */
4180 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4181 encoder_funcs->commit(encoder);
4183 /* let the connector get through one full cycle before testing */
4184 intel_wait_for_vblank(dev);
4189 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4190 struct drm_connector *connector, int dpms_mode)
4192 struct drm_encoder *encoder = &intel_encoder->enc;
4193 struct drm_device *dev = encoder->dev;
4194 struct drm_crtc *crtc = encoder->crtc;
4195 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4196 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4198 if (intel_encoder->load_detect_temp) {
4199 encoder->crtc = NULL;
4200 connector->encoder = NULL;
4201 intel_encoder->load_detect_temp = false;
4202 crtc->enabled = drm_helper_crtc_in_use(crtc);
4203 drm_helper_disable_unused_functions(dev);
4206 /* Switch crtc and encoder back off if necessary */
4207 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4208 if (encoder->crtc == crtc)
4209 encoder_funcs->dpms(encoder, dpms_mode);
4210 crtc_funcs->dpms(crtc, dpms_mode);
4214 /* Returns the clock of the currently programmed mode of the given pipe. */
4215 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4217 struct drm_i915_private *dev_priv = dev->dev_private;
4218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4219 int pipe = intel_crtc->pipe;
4220 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4222 intel_clock_t clock;
4224 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4225 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4227 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4229 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4230 if (IS_PINEVIEW(dev)) {
4231 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4232 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4234 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4235 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4239 if (IS_PINEVIEW(dev))
4240 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4241 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4243 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4244 DPLL_FPA01_P1_POST_DIV_SHIFT);
4246 switch (dpll & DPLL_MODE_MASK) {
4247 case DPLLB_MODE_DAC_SERIAL:
4248 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4251 case DPLLB_MODE_LVDS:
4252 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4256 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4257 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4261 /* XXX: Handle the 100Mhz refclk */
4262 intel_clock(dev, 96000, &clock);
4264 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4267 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4268 DPLL_FPA01_P1_POST_DIV_SHIFT);
4271 if ((dpll & PLL_REF_INPUT_MASK) ==
4272 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4273 /* XXX: might not be 66MHz */
4274 intel_clock(dev, 66000, &clock);
4276 intel_clock(dev, 48000, &clock);
4278 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4281 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4282 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4284 if (dpll & PLL_P2_DIVIDE_BY_4)
4289 intel_clock(dev, 48000, &clock);
4293 /* XXX: It would be nice to validate the clocks, but we can't reuse
4294 * i830PllIsValid() because it relies on the xf86_config connector
4295 * configuration being accurate, which it isn't necessarily.
4301 /** Returns the currently programmed mode of the given pipe. */
4302 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4303 struct drm_crtc *crtc)
4305 struct drm_i915_private *dev_priv = dev->dev_private;
4306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4307 int pipe = intel_crtc->pipe;
4308 struct drm_display_mode *mode;
4309 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4310 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4311 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4312 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4314 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4318 mode->clock = intel_crtc_clock_get(dev, crtc);
4319 mode->hdisplay = (htot & 0xffff) + 1;
4320 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4321 mode->hsync_start = (hsync & 0xffff) + 1;
4322 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4323 mode->vdisplay = (vtot & 0xffff) + 1;
4324 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4325 mode->vsync_start = (vsync & 0xffff) + 1;
4326 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4328 drm_mode_set_name(mode);
4329 drm_mode_set_crtcinfo(mode, 0);
4334 #define GPU_IDLE_TIMEOUT 500 /* ms */
4336 /* When this timer fires, we've been idle for awhile */
4337 static void intel_gpu_idle_timer(unsigned long arg)
4339 struct drm_device *dev = (struct drm_device *)arg;
4340 drm_i915_private_t *dev_priv = dev->dev_private;
4342 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4344 dev_priv->busy = false;
4346 queue_work(dev_priv->wq, &dev_priv->idle_work);
4349 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4351 static void intel_crtc_idle_timer(unsigned long arg)
4353 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4354 struct drm_crtc *crtc = &intel_crtc->base;
4355 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4357 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4359 intel_crtc->busy = false;
4361 queue_work(dev_priv->wq, &dev_priv->idle_work);
4364 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4366 struct drm_device *dev = crtc->dev;
4367 drm_i915_private_t *dev_priv = dev->dev_private;
4368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4369 int pipe = intel_crtc->pipe;
4370 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4371 int dpll = I915_READ(dpll_reg);
4373 if (HAS_PCH_SPLIT(dev))
4376 if (!dev_priv->lvds_downclock_avail)
4379 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4380 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4382 /* Unlock panel regs */
4383 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4385 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4386 I915_WRITE(dpll_reg, dpll);
4387 dpll = I915_READ(dpll_reg);
4388 intel_wait_for_vblank(dev);
4389 dpll = I915_READ(dpll_reg);
4390 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4391 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4393 /* ...and lock them again */
4394 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4397 /* Schedule downclock */
4399 mod_timer(&intel_crtc->idle_timer, jiffies +
4400 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4403 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4405 struct drm_device *dev = crtc->dev;
4406 drm_i915_private_t *dev_priv = dev->dev_private;
4407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4408 int pipe = intel_crtc->pipe;
4409 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4410 int dpll = I915_READ(dpll_reg);
4412 if (HAS_PCH_SPLIT(dev))
4415 if (!dev_priv->lvds_downclock_avail)
4419 * Since this is called by a timer, we should never get here in
4422 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4423 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4425 /* Unlock panel regs */
4426 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4428 dpll |= DISPLAY_RATE_SELECT_FPA1;
4429 I915_WRITE(dpll_reg, dpll);
4430 dpll = I915_READ(dpll_reg);
4431 intel_wait_for_vblank(dev);
4432 dpll = I915_READ(dpll_reg);
4433 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4434 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4436 /* ...and lock them again */
4437 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4443 * intel_idle_update - adjust clocks for idleness
4444 * @work: work struct
4446 * Either the GPU or display (or both) went idle. Check the busy status
4447 * here and adjust the CRTC and GPU clocks as necessary.
4449 static void intel_idle_update(struct work_struct *work)
4451 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4453 struct drm_device *dev = dev_priv->dev;
4454 struct drm_crtc *crtc;
4455 struct intel_crtc *intel_crtc;
4457 if (!i915_powersave)
4460 mutex_lock(&dev->struct_mutex);
4462 i915_update_gfx_val(dev_priv);
4464 if (IS_I945G(dev) || IS_I945GM(dev)) {
4465 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4466 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4469 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4470 /* Skip inactive CRTCs */
4474 intel_crtc = to_intel_crtc(crtc);
4475 if (!intel_crtc->busy)
4476 intel_decrease_pllclock(crtc);
4479 mutex_unlock(&dev->struct_mutex);
4483 * intel_mark_busy - mark the GPU and possibly the display busy
4485 * @obj: object we're operating on
4487 * Callers can use this function to indicate that the GPU is busy processing
4488 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4489 * buffer), we'll also mark the display as busy, so we know to increase its
4492 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4494 drm_i915_private_t *dev_priv = dev->dev_private;
4495 struct drm_crtc *crtc = NULL;
4496 struct intel_framebuffer *intel_fb;
4497 struct intel_crtc *intel_crtc;
4499 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4502 if (!dev_priv->busy) {
4503 if (IS_I945G(dev) || IS_I945GM(dev)) {
4506 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4507 fw_blc_self = I915_READ(FW_BLC_SELF);
4508 fw_blc_self &= ~FW_BLC_SELF_EN;
4509 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4511 dev_priv->busy = true;
4513 mod_timer(&dev_priv->idle_timer, jiffies +
4514 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4516 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4520 intel_crtc = to_intel_crtc(crtc);
4521 intel_fb = to_intel_framebuffer(crtc->fb);
4522 if (intel_fb->obj == obj) {
4523 if (!intel_crtc->busy) {
4524 if (IS_I945G(dev) || IS_I945GM(dev)) {
4527 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4528 fw_blc_self = I915_READ(FW_BLC_SELF);
4529 fw_blc_self &= ~FW_BLC_SELF_EN;
4530 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4532 /* Non-busy -> busy, upclock */
4533 intel_increase_pllclock(crtc, true);
4534 intel_crtc->busy = true;
4536 /* Busy -> busy, put off timer */
4537 mod_timer(&intel_crtc->idle_timer, jiffies +
4538 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4544 static void intel_crtc_destroy(struct drm_crtc *crtc)
4546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4548 drm_crtc_cleanup(crtc);
4552 struct intel_unpin_work {
4553 struct work_struct work;
4554 struct drm_device *dev;
4555 struct drm_gem_object *old_fb_obj;
4556 struct drm_gem_object *pending_flip_obj;
4557 struct drm_pending_vblank_event *event;
4561 static void intel_unpin_work_fn(struct work_struct *__work)
4563 struct intel_unpin_work *work =
4564 container_of(__work, struct intel_unpin_work, work);
4566 mutex_lock(&work->dev->struct_mutex);
4567 i915_gem_object_unpin(work->old_fb_obj);
4568 drm_gem_object_unreference(work->pending_flip_obj);
4569 drm_gem_object_unreference(work->old_fb_obj);
4570 mutex_unlock(&work->dev->struct_mutex);
4574 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4576 drm_i915_private_t *dev_priv = dev->dev_private;
4577 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4579 struct intel_unpin_work *work;
4580 struct drm_i915_gem_object *obj_priv;
4581 struct drm_pending_vblank_event *e;
4583 unsigned long flags;
4585 /* Ignore early vblank irqs */
4586 if (intel_crtc == NULL)
4589 spin_lock_irqsave(&dev->event_lock, flags);
4590 work = intel_crtc->unpin_work;
4591 if (work == NULL || !work->pending) {
4592 if (work && !work->pending) {
4593 obj_priv = to_intel_bo(work->pending_flip_obj);
4594 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4596 atomic_read(&obj_priv->pending_flip));
4598 spin_unlock_irqrestore(&dev->event_lock, flags);
4602 intel_crtc->unpin_work = NULL;
4603 drm_vblank_put(dev, intel_crtc->pipe);
4607 do_gettimeofday(&now);
4608 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4609 e->event.tv_sec = now.tv_sec;
4610 e->event.tv_usec = now.tv_usec;
4611 list_add_tail(&e->base.link,
4612 &e->base.file_priv->event_list);
4613 wake_up_interruptible(&e->base.file_priv->event_wait);
4616 spin_unlock_irqrestore(&dev->event_lock, flags);
4618 obj_priv = to_intel_bo(work->pending_flip_obj);
4620 /* Initial scanout buffer will have a 0 pending flip count */
4621 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4622 atomic_dec_and_test(&obj_priv->pending_flip))
4623 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4624 schedule_work(&work->work);
4627 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4629 drm_i915_private_t *dev_priv = dev->dev_private;
4630 struct intel_crtc *intel_crtc =
4631 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4632 unsigned long flags;
4634 spin_lock_irqsave(&dev->event_lock, flags);
4635 if (intel_crtc->unpin_work) {
4636 intel_crtc->unpin_work->pending = 1;
4638 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4640 spin_unlock_irqrestore(&dev->event_lock, flags);
4643 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4644 struct drm_framebuffer *fb,
4645 struct drm_pending_vblank_event *event)
4647 struct drm_device *dev = crtc->dev;
4648 struct drm_i915_private *dev_priv = dev->dev_private;
4649 struct intel_framebuffer *intel_fb;
4650 struct drm_i915_gem_object *obj_priv;
4651 struct drm_gem_object *obj;
4652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4653 struct intel_unpin_work *work;
4654 unsigned long flags;
4655 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4658 work = kzalloc(sizeof *work, GFP_KERNEL);
4662 mutex_lock(&dev->struct_mutex);
4664 work->event = event;
4665 work->dev = crtc->dev;
4666 intel_fb = to_intel_framebuffer(crtc->fb);
4667 work->old_fb_obj = intel_fb->obj;
4668 INIT_WORK(&work->work, intel_unpin_work_fn);
4670 /* We borrow the event spin lock for protecting unpin_work */
4671 spin_lock_irqsave(&dev->event_lock, flags);
4672 if (intel_crtc->unpin_work) {
4673 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4674 spin_unlock_irqrestore(&dev->event_lock, flags);
4676 mutex_unlock(&dev->struct_mutex);
4679 intel_crtc->unpin_work = work;
4680 spin_unlock_irqrestore(&dev->event_lock, flags);
4682 intel_fb = to_intel_framebuffer(fb);
4683 obj = intel_fb->obj;
4685 ret = intel_pin_and_fence_fb_obj(dev, obj);
4687 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4690 intel_crtc->unpin_work = NULL;
4691 mutex_unlock(&dev->struct_mutex);
4695 /* Reference the objects for the scheduled work. */
4696 drm_gem_object_reference(work->old_fb_obj);
4697 drm_gem_object_reference(obj);
4700 i915_gem_object_flush_write_domain(obj);
4701 drm_vblank_get(dev, intel_crtc->pipe);
4702 obj_priv = to_intel_bo(obj);
4703 atomic_inc(&obj_priv->pending_flip);
4704 work->pending_flip_obj = obj;
4707 OUT_RING(MI_DISPLAY_FLIP |
4708 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4709 OUT_RING(fb->pitch);
4710 if (IS_I965G(dev)) {
4711 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4712 pipesrc = I915_READ(pipesrc_reg);
4713 OUT_RING(pipesrc & 0x0fff0fff);
4715 OUT_RING(obj_priv->gtt_offset);
4720 mutex_unlock(&dev->struct_mutex);
4725 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4726 .dpms = intel_crtc_dpms,
4727 .mode_fixup = intel_crtc_mode_fixup,
4728 .mode_set = intel_crtc_mode_set,
4729 .mode_set_base = intel_pipe_set_base,
4730 .prepare = intel_crtc_prepare,
4731 .commit = intel_crtc_commit,
4732 .load_lut = intel_crtc_load_lut,
4735 static const struct drm_crtc_funcs intel_crtc_funcs = {
4736 .cursor_set = intel_crtc_cursor_set,
4737 .cursor_move = intel_crtc_cursor_move,
4738 .gamma_set = intel_crtc_gamma_set,
4739 .set_config = drm_crtc_helper_set_config,
4740 .destroy = intel_crtc_destroy,
4741 .page_flip = intel_crtc_page_flip,
4745 static void intel_crtc_init(struct drm_device *dev, int pipe)
4747 drm_i915_private_t *dev_priv = dev->dev_private;
4748 struct intel_crtc *intel_crtc;
4751 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4752 if (intel_crtc == NULL)
4755 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4757 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4758 intel_crtc->pipe = pipe;
4759 intel_crtc->plane = pipe;
4760 for (i = 0; i < 256; i++) {
4761 intel_crtc->lut_r[i] = i;
4762 intel_crtc->lut_g[i] = i;
4763 intel_crtc->lut_b[i] = i;
4766 /* Swap pipes & planes for FBC on pre-965 */
4767 intel_crtc->pipe = pipe;
4768 intel_crtc->plane = pipe;
4769 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4770 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4771 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4774 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4775 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4776 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4777 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4779 intel_crtc->cursor_addr = 0;
4780 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4781 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4783 intel_crtc->busy = false;
4785 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4786 (unsigned long)intel_crtc);
4789 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4790 struct drm_file *file_priv)
4792 drm_i915_private_t *dev_priv = dev->dev_private;
4793 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4794 struct drm_mode_object *drmmode_obj;
4795 struct intel_crtc *crtc;
4798 DRM_ERROR("called with no initialization\n");
4802 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4803 DRM_MODE_OBJECT_CRTC);
4806 DRM_ERROR("no such CRTC id\n");
4810 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4811 pipe_from_crtc_id->pipe = crtc->pipe;
4816 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4818 struct drm_crtc *crtc = NULL;
4820 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4822 if (intel_crtc->pipe == pipe)
4828 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4831 struct drm_encoder *encoder;
4834 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4835 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4836 if (type_mask & intel_encoder->clone_mask)
4837 index_mask |= (1 << entry);
4844 static void intel_setup_outputs(struct drm_device *dev)
4846 struct drm_i915_private *dev_priv = dev->dev_private;
4847 struct drm_encoder *encoder;
4849 intel_crt_init(dev);
4851 /* Set up integrated LVDS */
4852 if (IS_MOBILE(dev) && !IS_I830(dev))
4853 intel_lvds_init(dev);
4855 if (HAS_PCH_SPLIT(dev)) {
4858 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4859 intel_dp_init(dev, DP_A);
4861 if (I915_READ(HDMIB) & PORT_DETECTED) {
4862 /* PCH SDVOB multiplex with HDMIB */
4863 found = intel_sdvo_init(dev, PCH_SDVOB);
4865 intel_hdmi_init(dev, HDMIB);
4866 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4867 intel_dp_init(dev, PCH_DP_B);
4870 if (I915_READ(HDMIC) & PORT_DETECTED)
4871 intel_hdmi_init(dev, HDMIC);
4873 if (I915_READ(HDMID) & PORT_DETECTED)
4874 intel_hdmi_init(dev, HDMID);
4876 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4877 intel_dp_init(dev, PCH_DP_C);
4879 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4880 intel_dp_init(dev, PCH_DP_D);
4882 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4885 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4886 DRM_DEBUG_KMS("probing SDVOB\n");
4887 found = intel_sdvo_init(dev, SDVOB);
4888 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4889 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4890 intel_hdmi_init(dev, SDVOB);
4893 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4894 DRM_DEBUG_KMS("probing DP_B\n");
4895 intel_dp_init(dev, DP_B);
4899 /* Before G4X SDVOC doesn't have its own detect register */
4901 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4902 DRM_DEBUG_KMS("probing SDVOC\n");
4903 found = intel_sdvo_init(dev, SDVOC);
4906 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4908 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4909 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4910 intel_hdmi_init(dev, SDVOC);
4912 if (SUPPORTS_INTEGRATED_DP(dev)) {
4913 DRM_DEBUG_KMS("probing DP_C\n");
4914 intel_dp_init(dev, DP_C);
4918 if (SUPPORTS_INTEGRATED_DP(dev) &&
4919 (I915_READ(DP_D) & DP_DETECTED)) {
4920 DRM_DEBUG_KMS("probing DP_D\n");
4921 intel_dp_init(dev, DP_D);
4923 } else if (IS_GEN2(dev))
4924 intel_dvo_init(dev);
4926 if (SUPPORTS_TV(dev))
4929 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4930 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4932 encoder->possible_crtcs = intel_encoder->crtc_mask;
4933 encoder->possible_clones = intel_encoder_clones(dev,
4934 intel_encoder->clone_mask);
4938 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4940 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4942 drm_framebuffer_cleanup(fb);
4943 drm_gem_object_unreference_unlocked(intel_fb->obj);
4948 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4949 struct drm_file *file_priv,
4950 unsigned int *handle)
4952 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4953 struct drm_gem_object *object = intel_fb->obj;
4955 return drm_gem_handle_create(file_priv, object, handle);
4958 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4959 .destroy = intel_user_framebuffer_destroy,
4960 .create_handle = intel_user_framebuffer_create_handle,
4963 int intel_framebuffer_init(struct drm_device *dev,
4964 struct intel_framebuffer *intel_fb,
4965 struct drm_mode_fb_cmd *mode_cmd,
4966 struct drm_gem_object *obj)
4970 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4972 DRM_ERROR("framebuffer init failed %d\n", ret);
4976 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4977 intel_fb->obj = obj;
4981 static struct drm_framebuffer *
4982 intel_user_framebuffer_create(struct drm_device *dev,
4983 struct drm_file *filp,
4984 struct drm_mode_fb_cmd *mode_cmd)
4986 struct drm_gem_object *obj;
4987 struct intel_framebuffer *intel_fb;
4990 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4994 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4998 ret = intel_framebuffer_init(dev, intel_fb,
5001 drm_gem_object_unreference_unlocked(obj);
5006 return &intel_fb->base;
5009 static const struct drm_mode_config_funcs intel_mode_funcs = {
5010 .fb_create = intel_user_framebuffer_create,
5011 .output_poll_changed = intel_fb_output_poll_changed,
5014 static struct drm_gem_object *
5015 intel_alloc_power_context(struct drm_device *dev)
5017 struct drm_gem_object *pwrctx;
5020 pwrctx = i915_gem_alloc_object(dev, 4096);
5022 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5026 mutex_lock(&dev->struct_mutex);
5027 ret = i915_gem_object_pin(pwrctx, 4096);
5029 DRM_ERROR("failed to pin power context: %d\n", ret);
5033 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5035 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5038 mutex_unlock(&dev->struct_mutex);
5043 i915_gem_object_unpin(pwrctx);
5045 drm_gem_object_unreference(pwrctx);
5046 mutex_unlock(&dev->struct_mutex);
5050 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5055 rgvswctl = I915_READ16(MEMSWCTL);
5056 if (rgvswctl & MEMCTL_CMD_STS) {
5057 DRM_DEBUG("gpu busy, RCS change rejected\n");
5058 return false; /* still busy with another command */
5061 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5062 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5063 I915_WRITE16(MEMSWCTL, rgvswctl);
5064 POSTING_READ16(MEMSWCTL);
5066 rgvswctl |= MEMCTL_CMD_STS;
5067 I915_WRITE16(MEMSWCTL, rgvswctl);
5072 void ironlake_enable_drps(struct drm_device *dev)
5074 struct drm_i915_private *dev_priv = dev->dev_private;
5075 u32 rgvmodectl = I915_READ(MEMMODECTL);
5076 u8 fmax, fmin, fstart, vstart;
5079 /* 100ms RC evaluation intervals */
5080 I915_WRITE(RCUPEI, 100000);
5081 I915_WRITE(RCDNEI, 100000);
5083 /* Set max/min thresholds to 90ms and 80ms respectively */
5084 I915_WRITE(RCBMAXAVG, 90000);
5085 I915_WRITE(RCBMINAVG, 80000);
5087 I915_WRITE(MEMIHYST, 1);
5089 /* Set up min, max, and cur for interrupt handling */
5090 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5091 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5092 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5093 MEMMODE_FSTART_SHIFT;
5096 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5099 dev_priv->fmax = fstart; /* IPS callback will increase this */
5100 dev_priv->fstart = fstart;
5102 dev_priv->max_delay = fmax;
5103 dev_priv->min_delay = fmin;
5104 dev_priv->cur_delay = fstart;
5106 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5109 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5112 * Interrupts will be enabled in ironlake_irq_postinstall
5115 I915_WRITE(VIDSTART, vstart);
5116 POSTING_READ(VIDSTART);
5118 rgvmodectl |= MEMMODE_SWMODE_EN;
5119 I915_WRITE(MEMMODECTL, rgvmodectl);
5121 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5123 DRM_ERROR("stuck trying to change perf mode\n");
5130 ironlake_set_drps(dev, fstart);
5132 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5134 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5135 dev_priv->last_count2 = I915_READ(0x112f4);
5136 getrawmonotonic(&dev_priv->last_time2);
5139 void ironlake_disable_drps(struct drm_device *dev)
5141 struct drm_i915_private *dev_priv = dev->dev_private;
5142 u16 rgvswctl = I915_READ16(MEMSWCTL);
5144 /* Ack interrupts, disable EFC interrupt */
5145 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5146 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5147 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5148 I915_WRITE(DEIIR, DE_PCU_EVENT);
5149 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5151 /* Go back to the starting frequency */
5152 ironlake_set_drps(dev, dev_priv->fstart);
5154 rgvswctl |= MEMCTL_CMD_STS;
5155 I915_WRITE(MEMSWCTL, rgvswctl);
5160 static unsigned long intel_pxfreq(u32 vidfreq)
5163 int div = (vidfreq & 0x3f0000) >> 16;
5164 int post = (vidfreq & 0x3000) >> 12;
5165 int pre = (vidfreq & 0x7);
5170 freq = ((div * 133333) / ((1<<post) * pre));
5175 void intel_init_emon(struct drm_device *dev)
5177 struct drm_i915_private *dev_priv = dev->dev_private;
5182 /* Disable to program */
5186 /* Program energy weights for various events */
5187 I915_WRITE(SDEW, 0x15040d00);
5188 I915_WRITE(CSIEW0, 0x007f0000);
5189 I915_WRITE(CSIEW1, 0x1e220004);
5190 I915_WRITE(CSIEW2, 0x04000004);
5192 for (i = 0; i < 5; i++)
5193 I915_WRITE(PEW + (i * 4), 0);
5194 for (i = 0; i < 3; i++)
5195 I915_WRITE(DEW + (i * 4), 0);
5197 /* Program P-state weights to account for frequency power adjustment */
5198 for (i = 0; i < 16; i++) {
5199 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5200 unsigned long freq = intel_pxfreq(pxvidfreq);
5201 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5206 val *= (freq / 1000);
5208 val /= (127*127*900);
5210 DRM_ERROR("bad pxval: %ld\n", val);
5213 /* Render standby states get 0 weight */
5217 for (i = 0; i < 4; i++) {
5218 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5219 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5220 I915_WRITE(PXW + (i * 4), val);
5223 /* Adjust magic regs to magic values (more experimental results) */
5224 I915_WRITE(OGW0, 0);
5225 I915_WRITE(OGW1, 0);
5226 I915_WRITE(EG0, 0x00007f00);
5227 I915_WRITE(EG1, 0x0000000e);
5228 I915_WRITE(EG2, 0x000e0000);
5229 I915_WRITE(EG3, 0x68000300);
5230 I915_WRITE(EG4, 0x42000000);
5231 I915_WRITE(EG5, 0x00140031);
5235 for (i = 0; i < 8; i++)
5236 I915_WRITE(PXWL + (i * 4), 0);
5238 /* Enable PMON + select events */
5239 I915_WRITE(ECR, 0x80000019);
5241 lcfuse = I915_READ(LCFUSE02);
5243 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5246 void intel_init_clock_gating(struct drm_device *dev)
5248 struct drm_i915_private *dev_priv = dev->dev_private;
5251 * Disable clock gating reported to work incorrectly according to the
5252 * specs, but enable as much else as we can.
5254 if (HAS_PCH_SPLIT(dev)) {
5255 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5257 if (IS_IRONLAKE(dev)) {
5258 /* Required for FBC */
5259 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5260 /* Required for CxSR */
5261 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5263 I915_WRITE(PCH_3DCGDIS0,
5264 MARIUNIT_CLOCK_GATE_DISABLE |
5265 SVSMUNIT_CLOCK_GATE_DISABLE);
5268 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5271 * According to the spec the following bits should be set in
5272 * order to enable memory self-refresh
5273 * The bit 22/21 of 0x42004
5274 * The bit 5 of 0x42020
5275 * The bit 15 of 0x45000
5277 if (IS_IRONLAKE(dev)) {
5278 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5279 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5280 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5281 I915_WRITE(ILK_DSPCLK_GATE,
5282 (I915_READ(ILK_DSPCLK_GATE) |
5283 ILK_DPARB_CLK_GATE));
5284 I915_WRITE(DISP_ARB_CTL,
5285 (I915_READ(DISP_ARB_CTL) |
5289 } else if (IS_G4X(dev)) {
5290 uint32_t dspclk_gate;
5291 I915_WRITE(RENCLK_GATE_D1, 0);
5292 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5293 GS_UNIT_CLOCK_GATE_DISABLE |
5294 CL_UNIT_CLOCK_GATE_DISABLE);
5295 I915_WRITE(RAMCLK_GATE_D, 0);
5296 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5297 OVRUNIT_CLOCK_GATE_DISABLE |
5298 OVCUNIT_CLOCK_GATE_DISABLE;
5300 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5301 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5302 } else if (IS_I965GM(dev)) {
5303 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5304 I915_WRITE(RENCLK_GATE_D2, 0);
5305 I915_WRITE(DSPCLK_GATE_D, 0);
5306 I915_WRITE(RAMCLK_GATE_D, 0);
5307 I915_WRITE16(DEUC, 0);
5308 } else if (IS_I965G(dev)) {
5309 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5310 I965_RCC_CLOCK_GATE_DISABLE |
5311 I965_RCPB_CLOCK_GATE_DISABLE |
5312 I965_ISC_CLOCK_GATE_DISABLE |
5313 I965_FBC_CLOCK_GATE_DISABLE);
5314 I915_WRITE(RENCLK_GATE_D2, 0);
5315 } else if (IS_I9XX(dev)) {
5316 u32 dstate = I915_READ(D_STATE);
5318 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5319 DSTATE_DOT_CLOCK_GATING;
5320 I915_WRITE(D_STATE, dstate);
5321 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5322 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5323 } else if (IS_I830(dev)) {
5324 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5328 * GPU can automatically power down the render unit if given a page
5331 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5332 struct drm_i915_gem_object *obj_priv = NULL;
5334 if (dev_priv->pwrctx) {
5335 obj_priv = to_intel_bo(dev_priv->pwrctx);
5337 struct drm_gem_object *pwrctx;
5339 pwrctx = intel_alloc_power_context(dev);
5341 dev_priv->pwrctx = pwrctx;
5342 obj_priv = to_intel_bo(pwrctx);
5347 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5348 I915_WRITE(MCHBAR_RENDER_STANDBY,
5349 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5354 /* Set up chip specific display functions */
5355 static void intel_init_display(struct drm_device *dev)
5357 struct drm_i915_private *dev_priv = dev->dev_private;
5359 /* We always want a DPMS function */
5360 if (HAS_PCH_SPLIT(dev))
5361 dev_priv->display.dpms = ironlake_crtc_dpms;
5363 dev_priv->display.dpms = i9xx_crtc_dpms;
5365 if (I915_HAS_FBC(dev)) {
5367 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5368 dev_priv->display.enable_fbc = g4x_enable_fbc;
5369 dev_priv->display.disable_fbc = g4x_disable_fbc;
5370 } else if (IS_I965GM(dev)) {
5371 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5372 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5373 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5375 /* 855GM needs testing */
5378 /* Returns the core display clock speed */
5379 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5380 dev_priv->display.get_display_clock_speed =
5381 i945_get_display_clock_speed;
5382 else if (IS_I915G(dev))
5383 dev_priv->display.get_display_clock_speed =
5384 i915_get_display_clock_speed;
5385 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5386 dev_priv->display.get_display_clock_speed =
5387 i9xx_misc_get_display_clock_speed;
5388 else if (IS_I915GM(dev))
5389 dev_priv->display.get_display_clock_speed =
5390 i915gm_get_display_clock_speed;
5391 else if (IS_I865G(dev))
5392 dev_priv->display.get_display_clock_speed =
5393 i865_get_display_clock_speed;
5394 else if (IS_I85X(dev))
5395 dev_priv->display.get_display_clock_speed =
5396 i855_get_display_clock_speed;
5398 dev_priv->display.get_display_clock_speed =
5399 i830_get_display_clock_speed;
5401 /* For FIFO watermark updates */
5402 if (HAS_PCH_SPLIT(dev)) {
5403 if (IS_IRONLAKE(dev)) {
5404 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5405 dev_priv->display.update_wm = ironlake_update_wm;
5407 DRM_DEBUG_KMS("Failed to get proper latency. "
5409 dev_priv->display.update_wm = NULL;
5412 dev_priv->display.update_wm = NULL;
5413 } else if (IS_PINEVIEW(dev)) {
5414 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5416 dev_priv->mem_freq)) {
5417 DRM_INFO("failed to find known CxSR latency "
5418 "(found fsb freq %d, mem freq %d), "
5420 dev_priv->fsb_freq, dev_priv->mem_freq);
5421 /* Disable CxSR and never update its watermark again */
5422 pineview_disable_cxsr(dev);
5423 dev_priv->display.update_wm = NULL;
5425 dev_priv->display.update_wm = pineview_update_wm;
5426 } else if (IS_G4X(dev))
5427 dev_priv->display.update_wm = g4x_update_wm;
5428 else if (IS_I965G(dev))
5429 dev_priv->display.update_wm = i965_update_wm;
5430 else if (IS_I9XX(dev)) {
5431 dev_priv->display.update_wm = i9xx_update_wm;
5432 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5433 } else if (IS_I85X(dev)) {
5434 dev_priv->display.update_wm = i9xx_update_wm;
5435 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5437 dev_priv->display.update_wm = i830_update_wm;
5439 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5441 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5445 void intel_modeset_init(struct drm_device *dev)
5447 struct drm_i915_private *dev_priv = dev->dev_private;
5451 drm_mode_config_init(dev);
5453 dev->mode_config.min_width = 0;
5454 dev->mode_config.min_height = 0;
5456 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5458 intel_init_display(dev);
5460 if (IS_I965G(dev)) {
5461 dev->mode_config.max_width = 8192;
5462 dev->mode_config.max_height = 8192;
5463 } else if (IS_I9XX(dev)) {
5464 dev->mode_config.max_width = 4096;
5465 dev->mode_config.max_height = 4096;
5467 dev->mode_config.max_width = 2048;
5468 dev->mode_config.max_height = 2048;
5471 /* set memory base */
5473 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5475 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5477 if (IS_MOBILE(dev) || IS_I9XX(dev))
5481 DRM_DEBUG_KMS("%d display pipe%s available.\n",
5482 num_pipe, num_pipe > 1 ? "s" : "");
5484 for (i = 0; i < num_pipe; i++) {
5485 intel_crtc_init(dev, i);
5488 intel_setup_outputs(dev);
5490 intel_init_clock_gating(dev);
5492 if (IS_IRONLAKE_M(dev)) {
5493 ironlake_enable_drps(dev);
5494 intel_init_emon(dev);
5497 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5498 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5499 (unsigned long)dev);
5501 intel_setup_overlay(dev);
5504 void intel_modeset_cleanup(struct drm_device *dev)
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507 struct drm_crtc *crtc;
5508 struct intel_crtc *intel_crtc;
5510 mutex_lock(&dev->struct_mutex);
5512 drm_kms_helper_poll_fini(dev);
5513 intel_fbdev_fini(dev);
5515 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5516 /* Skip inactive CRTCs */
5520 intel_crtc = to_intel_crtc(crtc);
5521 intel_increase_pllclock(crtc, false);
5522 del_timer_sync(&intel_crtc->idle_timer);
5525 del_timer_sync(&dev_priv->idle_timer);
5527 if (dev_priv->display.disable_fbc)
5528 dev_priv->display.disable_fbc(dev);
5530 if (dev_priv->pwrctx) {
5531 struct drm_i915_gem_object *obj_priv;
5533 obj_priv = to_intel_bo(dev_priv->pwrctx);
5534 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5536 i915_gem_object_unpin(dev_priv->pwrctx);
5537 drm_gem_object_unreference(dev_priv->pwrctx);
5540 if (IS_IRONLAKE_M(dev))
5541 ironlake_disable_drps(dev);
5543 mutex_unlock(&dev->struct_mutex);
5545 drm_mode_config_cleanup(dev);
5550 * Return which encoder is currently attached for connector.
5552 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5554 struct drm_mode_object *obj;
5555 struct drm_encoder *encoder;
5558 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5559 if (connector->encoder_ids[i] == 0)
5562 obj = drm_mode_object_find(connector->dev,
5563 connector->encoder_ids[i],
5564 DRM_MODE_OBJECT_ENCODER);
5568 encoder = obj_to_encoder(obj);
5575 * set vga decode state - true == enable VGA decode
5577 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5579 struct drm_i915_private *dev_priv = dev->dev_private;
5582 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5584 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5586 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5587 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);