drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 710                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711                      clock.m1++) {
 712                         for (clock.m2 = limit->m2.min;
 713                              clock.m2 <= limit->m2.max; clock.m2++) {
 714                                 /* m1 is always 0 in IGD */
 715                                 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 716                                         break;
 717                                 for (clock.n = limit->n.min;
 718                                      clock.n <= limit->n.max; clock.n++) {
 719                                         int this_err;
 720
 721                                         intel_clock(dev, refclk, &clock);
 722
 723                                         if (!intel_PLL_is_valid(crtc, &clock))
 724                                                 continue;
 725
 726                                         this_err = abs(clock.dot - target);
 727                                         if (this_err < err) {
 728                                                 *best_clock = clock;
 729                                                 err = this_err;
 730                                         }
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         return (err != target);
 737 }
 738
 739
 740 static bool
 741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                             int target, int refclk, intel_clock_t *best_clock)
 743
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         intel_clock_t clock;
 747         int err = target;
 748         bool found = false;
 749
 750         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 751
 752         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 753                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 754                         /* m1 is always 0 in IGD */
 755                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 756                                 break;
 757                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 758                              clock.n++) {
 759                                 int this_err;
 760
 761                                 intel_clock(dev, refclk, &clock);
 762
 763                                 if (!intel_PLL_is_valid(crtc, &clock))
 764                                         continue;
 765
 766                                 this_err = abs(clock.dot - target);
 767                                 if (this_err < err) {
 768                                         *best_clock = clock;
 769                                         err = this_err;
 770                                         found = true;
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return found;
 777 }
 778
 779 static bool
 780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 781                         int target, int refclk, intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->dev;
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         intel_clock_t clock;
 786         int max_n;
 787         bool found;
 788         /* approximately equals target * 0.00488 */
 789         int err_most = (target >> 8) + (target >> 10);
 790         found = false;
 791
 792         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 793                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 794                     LVDS_CLKB_POWER_UP)
 795                         clock.p2 = limit->p2.p2_fast;
 796                 else
 797                         clock.p2 = limit->p2.p2_slow;
 798         } else {
 799                 if (target < limit->p2.dot_limit)
 800                         clock.p2 = limit->p2.p2_slow;
 801                 else
 802                         clock.p2 = limit->p2.p2_fast;
 803         }
 804
 805         memset(best_clock, 0, sizeof(*best_clock));
 806         max_n = limit->n.max;
 807         /* based on hardware requriment prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirment prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         intel_clock(dev, refclk, &clock);
 819                                         if (!intel_PLL_is_valid(crtc, &clock))
 820                                                 continue;
 821                                         this_err = abs(clock.dot - target) ;
 822                                         if (this_err < err_most) {
 823                                                 *best_clock = clock;
 824                                                 err_most = this_err;
 825                                                 max_n = clock.n;
 826                                                 found = true;
 827                                         }
 828                                 }
 829                         }
 830                 }
 831         }
 832         return found;
 833 }
 834
 835 static bool
 836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *best_clock)
 838 {
 839         struct drm_device *dev = crtc->dev;
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.n = 1;
 843                 clock.p1 = 2;
 844                 clock.p2 = 10;
 845                 clock.m1 = 12;
 846                 clock.m2 = 9;
 847         } else {
 848                 clock.n = 2;
 849                 clock.p1 = 1;
 850                 clock.p2 = 10;
 851                 clock.m1 = 14;
 852                 clock.m2 = 8;
 853         }
 854         intel_clock(dev, refclk, &clock);
 855         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 856         return true;
 857 }
 858
 859 static bool
 860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 861                         int target, int refclk, intel_clock_t *best_clock)
 862 {
 863         struct drm_device *dev = crtc->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found;
 868         int err_most = 47;
 869         found = false;
 870
 871         /* eDP has only 2 clock choice, no n/m/p setting */
 872         if (HAS_eDP)
 873                 return true;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 876                 return intel_find_pll_igdng_dp(limit, crtc, target,
 877                                                refclk, best_clock);
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 881                     LVDS_CLKB_POWER_UP)
 882                         clock.p2 = limit->p2.p2_fast;
 883                 else
 884                         clock.p2 = limit->p2.p2_slow;
 885         } else {
 886                 if (target < limit->p2.dot_limit)
 887                         clock.p2 = limit->p2.p2_slow;
 888                 else
 889                         clock.p2 = limit->p2.p2_fast;
 890         }
 891
 892         memset(best_clock, 0, sizeof(*best_clock));
 893         max_n = limit->n.max;
 894         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 895                 /* based on hardware requriment prefer smaller n to precision */
 896                 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 897                         /* based on hardware requirment prefere larger m1,m2 */
 898                         for (clock.m1 = limit->m1.max;
 899                              clock.m1 >= limit->m1.min; clock.m1--) {
 900                                 for (clock.m2 = limit->m2.max;
 901                                      clock.m2 >= limit->m2.min; clock.m2--) {
 902                                         int this_err;
 903
 904                                         intel_clock(dev, refclk, &clock);
 905                                         if (!intel_PLL_is_valid(crtc, &clock))
 906                                                 continue;
 907                                         this_err = abs((10000 - (target*10000/clock.dot)));
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                                 /* found on first matching */
 914                                                 goto out;
 915                                         }
 916                                 }
 917                         }
 918                 }
 919         }
 920 out:
 921         return found;
 922 }
 923
 924 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 925 static bool
 926 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 927                       int target, int refclk, intel_clock_t *best_clock)
 928 {
 929     intel_clock_t clock;
 930     if (target < 200000) {
 931         clock.p1 = 2;
 932         clock.p2 = 10;
 933         clock.n = 2;
 934         clock.m1 = 23;
 935         clock.m2 = 8;
 936     } else {
 937         clock.p1 = 1;
 938         clock.p2 = 10;
 939         clock.n = 1;
 940         clock.m1 = 14;
 941         clock.m2 = 2;
 942     }
 943     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 944     clock.p = (clock.p1 * clock.p2);
 945     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 946     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 947     return true;
 948 }
 949
 950 void
 951 intel_wait_for_vblank(struct drm_device *dev)
 952 {
 953         /* Wait for 20ms, i.e. one cycle at 50hz. */
 954         mdelay(20);
 955 }
 956
 957 /* Parameters have changed, update FBC info */
 958 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 959 {
 960         struct drm_device *dev = crtc->dev;
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         struct drm_framebuffer *fb = crtc->fb;
 963         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 964         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 966         int plane, i;
 967         u32 fbc_ctl, fbc_ctl2;
 968
 969         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 970
 971         if (fb->pitch < dev_priv->cfb_pitch)
 972                 dev_priv->cfb_pitch = fb->pitch;
 973
 974         /* FBC_CTL wants 64B units */
 975         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 976         dev_priv->cfb_fence = obj_priv->fence_reg;
 977         dev_priv->cfb_plane = intel_crtc->plane;
 978         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 979
 980         /* Clear old tags */
 981         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 982                 I915_WRITE(FBC_TAG + (i * 4), 0);
 983
 984         /* Set it up... */
 985         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 986         if (obj_priv->tiling_mode != I915_TILING_NONE)
 987                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 988         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 989         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 990
 991         /* enable it... */
 992         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 993         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 994         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 995         if (obj_priv->tiling_mode != I915_TILING_NONE)
 996                 fbc_ctl |= dev_priv->cfb_fence;
 997         I915_WRITE(FBC_CONTROL, fbc_ctl);
 998
 999         DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1000                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1001 }
1002
1003 void i8xx_disable_fbc(struct drm_device *dev)
1004 {
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         u32 fbc_ctl;
1007
1008         if (!I915_HAS_FBC(dev))
1009                 return;
1010
1011         /* Disable compression */
1012         fbc_ctl = I915_READ(FBC_CONTROL);
1013         fbc_ctl &= ~FBC_CTL_EN;
1014         I915_WRITE(FBC_CONTROL, fbc_ctl);
1015
1016         /* Wait for compressing bit to clear */
1017         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1018                 ; /* nothing */
1019
1020         intel_wait_for_vblank(dev);
1021
1022         DRM_DEBUG("disabled FBC\n");
1023 }
1024
1025 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1026 {
1027         struct drm_device *dev = crtc->dev;
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029
1030         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1031 }
1032
1033 /**
1034  * intel_update_fbc - enable/disable FBC as needed
1035  * @crtc: CRTC to point the compressor at
1036  * @mode: mode in use
1037  *
1038  * Set up the framebuffer compression hardware at mode set time.  We
1039  * enable it if possible:
1040  *   - plane A only (on pre-965)
1041  *   - no pixel mulitply/line duplication
1042  *   - no alpha buffer discard
1043  *   - no dual wide
1044  *   - framebuffer <= 2048 in width, 1536 in height
1045  *
1046  * We can't assume that any compression will take place (worst case),
1047  * so the compressed buffer has to be the same size as the uncompressed
1048  * one.  It also must reside (along with the line length buffer) in
1049  * stolen memory.
1050  *
1051  * We need to enable/disable FBC on a global basis.
1052  */
1053 static void intel_update_fbc(struct drm_crtc *crtc,
1054                              struct drm_display_mode *mode)
1055 {
1056         struct drm_device *dev = crtc->dev;
1057         struct drm_i915_private *dev_priv = dev->dev_private;
1058         struct drm_framebuffer *fb = crtc->fb;
1059         struct intel_framebuffer *intel_fb;
1060         struct drm_i915_gem_object *obj_priv;
1061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1062         int plane = intel_crtc->plane;
1063
1064         if (!i915_powersave)
1065                 return;
1066
1067         if (!dev_priv->display.fbc_enabled ||
1068             !dev_priv->display.enable_fbc ||
1069             !dev_priv->display.disable_fbc)
1070                 return;
1071
1072         if (!crtc->fb)
1073                 return;
1074
1075         intel_fb = to_intel_framebuffer(fb);
1076         obj_priv = intel_fb->obj->driver_private;
1077
1078         /*
1079          * If FBC is already on, we just have to verify that we can
1080          * keep it that way...
1081          * Need to disable if:
1082          *   - changing FBC params (stride, fence, mode)
1083          *   - new fb is too large to fit in compressed buffer
1084          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1085          */
1086         if (intel_fb->obj->size > dev_priv->cfb_size) {
1087                 DRM_DEBUG("framebuffer too large, disabling compression\n");
1088                 goto out_disable;
1089         }
1090         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1091             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1092                 DRM_DEBUG("mode incompatible with compression, disabling\n");
1093                 goto out_disable;
1094         }
1095         if ((mode->hdisplay > 2048) ||
1096             (mode->vdisplay > 1536)) {
1097                 DRM_DEBUG("mode too large for compression, disabling\n");
1098                 goto out_disable;
1099         }
1100         if (IS_I9XX(dev) && plane != 0) {
1101                 DRM_DEBUG("plane not 0, disabling compression\n");
1102                 goto out_disable;
1103         }
1104         if (obj_priv->tiling_mode != I915_TILING_X) {
1105                 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1106                 goto out_disable;
1107         }
1108
1109         if (dev_priv->display.fbc_enabled(crtc)) {
1110                 /* We can re-enable it in this case, but need to update pitch */
1111                 if (fb->pitch > dev_priv->cfb_pitch)
1112                         dev_priv->display.disable_fbc(dev);
1113                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1114                         dev_priv->display.disable_fbc(dev);
1115                 if (plane != dev_priv->cfb_plane)
1116                         dev_priv->display.disable_fbc(dev);
1117         }
1118
1119         if (!dev_priv->display.fbc_enabled(crtc)) {
1120                 /* Now try to turn it back on if possible */
1121                 dev_priv->display.enable_fbc(crtc, 500);
1122         }
1123
1124         return;
1125
1126 out_disable:
1127         DRM_DEBUG("unsupported config, disabling FBC\n");
1128         /* Multiple disables should be harmless */
1129         if (dev_priv->display.fbc_enabled(crtc))
1130                 dev_priv->display.disable_fbc(dev);
1131 }
1132
1133 static int
1134 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1135                     struct drm_framebuffer *old_fb)
1136 {
1137         struct drm_device *dev = crtc->dev;
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139         struct drm_i915_master_private *master_priv;
1140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1141         struct intel_framebuffer *intel_fb;
1142         struct drm_i915_gem_object *obj_priv;
1143         struct drm_gem_object *obj;
1144         int pipe = intel_crtc->pipe;
1145         int plane = intel_crtc->plane;
1146         unsigned long Start, Offset;
1147         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1148         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1149         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1150         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1151         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1152         u32 dspcntr, alignment;
1153         int ret;
1154
1155         /* no fb bound */
1156         if (!crtc->fb) {
1157                 DRM_DEBUG("No FB bound\n");
1158                 return 0;
1159         }
1160
1161         switch (plane) {
1162         case 0:
1163         case 1:
1164                 break;
1165         default:
1166                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1167                 return -EINVAL;
1168         }
1169
1170         intel_fb = to_intel_framebuffer(crtc->fb);
1171         obj = intel_fb->obj;
1172         obj_priv = obj->driver_private;
1173
1174         switch (obj_priv->tiling_mode) {
1175         case I915_TILING_NONE:
1176                 alignment = 64 * 1024;
1177                 break;
1178         case I915_TILING_X:
1179                 /* pin() will align the object as required by fence */
1180                 alignment = 0;
1181                 break;
1182         case I915_TILING_Y:
1183                 /* FIXME: Is this true? */
1184                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1185                 return -EINVAL;
1186         default:
1187                 BUG();
1188         }
1189
1190         mutex_lock(&dev->struct_mutex);
1191         ret = i915_gem_object_pin(obj, alignment);
1192         if (ret != 0) {
1193                 mutex_unlock(&dev->struct_mutex);
1194                 return ret;
1195         }
1196
1197         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1198         if (ret != 0) {
1199                 i915_gem_object_unpin(obj);
1200                 mutex_unlock(&dev->struct_mutex);
1201                 return ret;
1202         }
1203
1204         /* Pre-i965 needs to install a fence for tiled scan-out */
1205         if (!IS_I965G(dev) &&
1206             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1207             obj_priv->tiling_mode != I915_TILING_NONE) {
1208                 ret = i915_gem_object_get_fence_reg(obj);
1209                 if (ret != 0) {
1210                         i915_gem_object_unpin(obj);
1211                         mutex_unlock(&dev->struct_mutex);
1212                         return ret;
1213                 }
1214         }
1215
1216         dspcntr = I915_READ(dspcntr_reg);
1217         /* Mask out pixel format bits in case we change it */
1218         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1219         switch (crtc->fb->bits_per_pixel) {
1220         case 8:
1221                 dspcntr |= DISPPLANE_8BPP;
1222                 break;
1223         case 16:
1224                 if (crtc->fb->depth == 15)
1225                         dspcntr |= DISPPLANE_15_16BPP;
1226                 else
1227                         dspcntr |= DISPPLANE_16BPP;
1228                 break;
1229         case 24:
1230         case 32:
1231                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1232                 break;
1233         default:
1234                 DRM_ERROR("Unknown color depth\n");
1235                 i915_gem_object_unpin(obj);
1236                 mutex_unlock(&dev->struct_mutex);
1237                 return -EINVAL;
1238         }
1239         if (IS_I965G(dev)) {
1240                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1241                         dspcntr |= DISPPLANE_TILED;
1242                 else
1243                         dspcntr &= ~DISPPLANE_TILED;
1244         }
1245
1246         if (IS_IGDNG(dev))
1247                 /* must disable */
1248                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1249
1250         I915_WRITE(dspcntr_reg, dspcntr);
1251
1252         Start = obj_priv->gtt_offset;
1253         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1254
1255         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1256         I915_WRITE(dspstride, crtc->fb->pitch);
1257         if (IS_I965G(dev)) {
1258                 I915_WRITE(dspbase, Offset);
1259                 I915_READ(dspbase);
1260                 I915_WRITE(dspsurf, Start);
1261                 I915_READ(dspsurf);
1262                 I915_WRITE(dsptileoff, (y << 16) | x);
1263         } else {
1264                 I915_WRITE(dspbase, Start + Offset);
1265                 I915_READ(dspbase);
1266         }
1267
1268         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
1269                 intel_update_fbc(crtc, &crtc->mode);
1270
1271         intel_wait_for_vblank(dev);
1272
1273         if (old_fb) {
1274                 intel_fb = to_intel_framebuffer(old_fb);
1275                 obj_priv = intel_fb->obj->driver_private;
1276                 i915_gem_object_unpin(intel_fb->obj);
1277         }
1278         intel_increase_pllclock(crtc, true);
1279
1280         mutex_unlock(&dev->struct_mutex);
1281
1282         if (!dev->primary->master)
1283                 return 0;
1284
1285         master_priv = dev->primary->master->driver_priv;
1286         if (!master_priv->sarea_priv)
1287                 return 0;
1288
1289         if (pipe) {
1290                 master_priv->sarea_priv->pipeB_x = x;
1291                 master_priv->sarea_priv->pipeB_y = y;
1292         } else {
1293                 master_priv->sarea_priv->pipeA_x = x;
1294                 master_priv->sarea_priv->pipeA_y = y;
1295         }
1296
1297         return 0;
1298 }
1299
1300 /* Disable the VGA plane that we never use */
1301 static void i915_disable_vga (struct drm_device *dev)
1302 {
1303         struct drm_i915_private *dev_priv = dev->dev_private;
1304         u8 sr1;
1305         u32 vga_reg;
1306
1307         if (IS_IGDNG(dev))
1308                 vga_reg = CPU_VGACNTRL;
1309         else
1310                 vga_reg = VGACNTRL;
1311
1312         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1313                 return;
1314
1315         I915_WRITE8(VGA_SR_INDEX, 1);
1316         sr1 = I915_READ8(VGA_SR_DATA);
1317         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1318         udelay(100);
1319
1320         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1321 }
1322
1323 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1324 {
1325         struct drm_device *dev = crtc->dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         u32 dpa_ctl;
1328
1329         DRM_DEBUG("\n");
1330         dpa_ctl = I915_READ(DP_A);
1331         dpa_ctl &= ~DP_PLL_ENABLE;
1332         I915_WRITE(DP_A, dpa_ctl);
1333 }
1334
1335 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1336 {
1337         struct drm_device *dev = crtc->dev;
1338         struct drm_i915_private *dev_priv = dev->dev_private;
1339         u32 dpa_ctl;
1340
1341         dpa_ctl = I915_READ(DP_A);
1342         dpa_ctl |= DP_PLL_ENABLE;
1343         I915_WRITE(DP_A, dpa_ctl);
1344         udelay(200);
1345 }
1346
1347
1348 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1349 {
1350         struct drm_device *dev = crtc->dev;
1351         struct drm_i915_private *dev_priv = dev->dev_private;
1352         u32 dpa_ctl;
1353
1354         DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1355         dpa_ctl = I915_READ(DP_A);
1356         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1357
1358         if (clock < 200000) {
1359                 u32 temp;
1360                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1361                 /* workaround for 160Mhz:
1362                    1) program 0x4600c bits 15:0 = 0x8124
1363                    2) program 0x46010 bit 0 = 1
1364                    3) program 0x46034 bit 24 = 1
1365                    4) program 0x64000 bit 14 = 1
1366                    */
1367                 temp = I915_READ(0x4600c);
1368                 temp &= 0xffff0000;
1369                 I915_WRITE(0x4600c, temp | 0x8124);
1370
1371                 temp = I915_READ(0x46010);
1372                 I915_WRITE(0x46010, temp | 1);
1373
1374                 temp = I915_READ(0x46034);
1375                 I915_WRITE(0x46034, temp | (1 << 24));
1376         } else {
1377                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1378         }
1379         I915_WRITE(DP_A, dpa_ctl);
1380
1381         udelay(500);
1382 }
1383
1384 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1385 {
1386         struct drm_device *dev = crtc->dev;
1387         struct drm_i915_private *dev_priv = dev->dev_private;
1388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1389         int pipe = intel_crtc->pipe;
1390         int plane = intel_crtc->plane;
1391         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1392         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1393         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1394         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1395         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1396         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1397         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1398         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1399         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1400         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1401         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1402         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1403         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1404         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1405         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1406         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1407         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1408         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1409         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1410         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1411         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1412         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1413         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1414         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1415         u32 temp;
1416         int tries = 5, j, n;
1417
1418         /* XXX: When our outputs are all unaware of DPMS modes other than off
1419          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1420          */
1421         switch (mode) {
1422         case DRM_MODE_DPMS_ON:
1423         case DRM_MODE_DPMS_STANDBY:
1424         case DRM_MODE_DPMS_SUSPEND:
1425                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1426                 if (HAS_eDP) {
1427                         /* enable eDP PLL */
1428                         igdng_enable_pll_edp(crtc);
1429                 } else {
1430                         /* enable PCH DPLL */
1431                         temp = I915_READ(pch_dpll_reg);
1432                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1433                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1434                                 I915_READ(pch_dpll_reg);
1435                         }
1436
1437                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1438                         temp = I915_READ(fdi_rx_reg);
1439                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1440                                         FDI_SEL_PCDCLK |
1441                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1442                         I915_READ(fdi_rx_reg);
1443                         udelay(200);
1444
1445                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1446                         temp = I915_READ(fdi_tx_reg);
1447                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1448                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1449                                 I915_READ(fdi_tx_reg);
1450                                 udelay(100);
1451                         }
1452                 }
1453
1454                 /* Enable panel fitting for LVDS */
1455                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1456                         temp = I915_READ(pf_ctl_reg);
1457                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);
1458
1459                         /* currently full aspect */
1460                         I915_WRITE(pf_win_pos, 0);
1461
1462                         I915_WRITE(pf_win_size,
1463                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1464                                    (dev_priv->panel_fixed_mode->vdisplay));
1465                 }
1466
1467                 /* Enable CPU pipe */
1468                 temp = I915_READ(pipeconf_reg);
1469                 if ((temp & PIPEACONF_ENABLE) == 0) {
1470                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1471                         I915_READ(pipeconf_reg);
1472                         udelay(100);
1473                 }
1474
1475                 /* configure and enable CPU plane */
1476                 temp = I915_READ(dspcntr_reg);
1477                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1478                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1479                         /* Flush the plane changes */
1480                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1481                 }
1482
1483                 if (!HAS_eDP) {
1484                         /* enable CPU FDI TX and PCH FDI RX */
1485                         temp = I915_READ(fdi_tx_reg);
1486                         temp |= FDI_TX_ENABLE;
1487                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1488                         temp &= ~FDI_LINK_TRAIN_NONE;
1489                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1490                         I915_WRITE(fdi_tx_reg, temp);
1491                         I915_READ(fdi_tx_reg);
1492
1493                         temp = I915_READ(fdi_rx_reg);
1494                         temp &= ~FDI_LINK_TRAIN_NONE;
1495                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1496                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1497                         I915_READ(fdi_rx_reg);
1498
1499                         udelay(150);
1500
1501                         /* Train FDI. */
1502                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1503                            for train result */
1504                         temp = I915_READ(fdi_rx_imr_reg);
1505                         temp &= ~FDI_RX_SYMBOL_LOCK;
1506                         temp &= ~FDI_RX_BIT_LOCK;
1507                         I915_WRITE(fdi_rx_imr_reg, temp);
1508                         I915_READ(fdi_rx_imr_reg);
1509                         udelay(150);
1510
1511                         temp = I915_READ(fdi_rx_iir_reg);
1512                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1513
1514                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1515                                 for (j = 0; j < tries; j++) {
1516                                         temp = I915_READ(fdi_rx_iir_reg);
1517                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1518                                         if (temp & FDI_RX_BIT_LOCK)
1519                                                 break;
1520                                         udelay(200);
1521                                 }
1522                                 if (j != tries)
1523                                         I915_WRITE(fdi_rx_iir_reg,
1524                                                         temp | FDI_RX_BIT_LOCK);
1525                                 else
1526                                         DRM_DEBUG("train 1 fail\n");
1527                         } else {
1528                                 I915_WRITE(fdi_rx_iir_reg,
1529                                                 temp | FDI_RX_BIT_LOCK);
1530                                 DRM_DEBUG("train 1 ok 2!\n");
1531                         }
1532                         temp = I915_READ(fdi_tx_reg);
1533                         temp &= ~FDI_LINK_TRAIN_NONE;
1534                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1535                         I915_WRITE(fdi_tx_reg, temp);
1536
1537                         temp = I915_READ(fdi_rx_reg);
1538                         temp &= ~FDI_LINK_TRAIN_NONE;
1539                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1540                         I915_WRITE(fdi_rx_reg, temp);
1541
1542                         udelay(150);
1543
1544                         temp = I915_READ(fdi_rx_iir_reg);
1545                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1546
1547                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1548                                 for (j = 0; j < tries; j++) {
1549                                         temp = I915_READ(fdi_rx_iir_reg);
1550                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1551                                         if (temp & FDI_RX_SYMBOL_LOCK)
1552                                                 break;
1553                                         udelay(200);
1554                                 }
1555                                 if (j != tries) {
1556                                         I915_WRITE(fdi_rx_iir_reg,
1557                                                         temp | FDI_RX_SYMBOL_LOCK);
1558                                         DRM_DEBUG("train 2 ok 1!\n");
1559                                 } else
1560                                         DRM_DEBUG("train 2 fail\n");
1561                         } else {
1562                                 I915_WRITE(fdi_rx_iir_reg,
1563                                                 temp | FDI_RX_SYMBOL_LOCK);
1564                                 DRM_DEBUG("train 2 ok 2!\n");
1565                         }
1566                         DRM_DEBUG("train done\n");
1567
1568                         /* set transcoder timing */
1569                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1570                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1571                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1572
1573                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1574                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1575                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1576
1577                         /* enable PCH transcoder */
1578                         temp = I915_READ(transconf_reg);
1579                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1580                         I915_READ(transconf_reg);
1581
1582                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1583                                 ;
1584
1585                         /* enable normal */
1586
1587                         temp = I915_READ(fdi_tx_reg);
1588                         temp &= ~FDI_LINK_TRAIN_NONE;
1589                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1590                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1591                         I915_READ(fdi_tx_reg);
1592
1593                         temp = I915_READ(fdi_rx_reg);
1594                         temp &= ~FDI_LINK_TRAIN_NONE;
1595                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1596                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1597                         I915_READ(fdi_rx_reg);
1598
1599                         /* wait one idle pattern time */
1600                         udelay(100);
1601
1602                 }
1603
1604                 intel_crtc_load_lut(crtc);
1605
1606         break;
1607         case DRM_MODE_DPMS_OFF:
1608                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1609
1610                 i915_disable_vga(dev);
1611
1612                 /* Disable display plane */
1613                 temp = I915_READ(dspcntr_reg);
1614                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1615                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1616                         /* Flush the plane changes */
1617                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1618                         I915_READ(dspbase_reg);
1619                 }
1620
1621                 /* disable cpu pipe, disable after all planes disabled */
1622                 temp = I915_READ(pipeconf_reg);
1623                 if ((temp & PIPEACONF_ENABLE) != 0) {
1624                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1625                         I915_READ(pipeconf_reg);
1626                         n = 0;
1627                         /* wait for cpu pipe off, pipe state */
1628                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1629                                 n++;
1630                                 if (n < 60) {
1631                                         udelay(500);
1632                                         continue;
1633                                 } else {
1634                                         DRM_DEBUG("pipe %d off delay\n", pipe);
1635                                         break;
1636                                 }
1637                         }
1638                 } else
1639                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1640
1641                 if (HAS_eDP) {
1642                         igdng_disable_pll_edp(crtc);
1643                 }
1644
1645                 /* disable CPU FDI tx and PCH FDI rx */
1646                 temp = I915_READ(fdi_tx_reg);
1647                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1648                 I915_READ(fdi_tx_reg);
1649
1650                 temp = I915_READ(fdi_rx_reg);
1651                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1652                 I915_READ(fdi_rx_reg);
1653
1654                 udelay(100);
1655
1656                 /* still set train pattern 1 */
1657                 temp = I915_READ(fdi_tx_reg);
1658                 temp &= ~FDI_LINK_TRAIN_NONE;
1659                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1660                 I915_WRITE(fdi_tx_reg, temp);
1661
1662                 temp = I915_READ(fdi_rx_reg);
1663                 temp &= ~FDI_LINK_TRAIN_NONE;
1664                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1665                 I915_WRITE(fdi_rx_reg, temp);
1666
1667                 udelay(100);
1668
1669                 /* disable PCH transcoder */
1670                 temp = I915_READ(transconf_reg);
1671                 if ((temp & TRANS_ENABLE) != 0) {
1672                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1673                         I915_READ(transconf_reg);
1674                         n = 0;
1675                         /* wait for PCH transcoder off, transcoder state */
1676                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1677                                 n++;
1678                                 if (n < 60) {
1679                                         udelay(500);
1680                                         continue;
1681                                 } else {
1682                                         DRM_DEBUG("transcoder %d off delay\n", pipe);
1683                                         break;
1684                                 }
1685                         }
1686                 }
1687
1688                 /* disable PCH DPLL */
1689                 temp = I915_READ(pch_dpll_reg);
1690                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1691                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1692                         I915_READ(pch_dpll_reg);
1693                 }
1694
1695                 temp = I915_READ(fdi_rx_reg);
1696                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1697                         temp &= ~FDI_SEL_PCDCLK;
1698                         temp &= ~FDI_RX_PLL_ENABLE;
1699                         I915_WRITE(fdi_rx_reg, temp);
1700                         I915_READ(fdi_rx_reg);
1701                 }
1702
1703                 /* Disable CPU FDI TX PLL */
1704                 temp = I915_READ(fdi_tx_reg);
1705                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1706                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1707                         I915_READ(fdi_tx_reg);
1708                         udelay(100);
1709                 }
1710
1711                 /* Disable PF */
1712                 temp = I915_READ(pf_ctl_reg);
1713                 if ((temp & PF_ENABLE) != 0) {
1714                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1715                         I915_READ(pf_ctl_reg);
1716                 }
1717                 I915_WRITE(pf_win_size, 0);
1718
1719                 /* Wait for the clocks to turn off. */
1720                 udelay(150);
1721                 break;
1722         }
1723 }
1724
1725 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1726 {
1727         struct drm_device *dev = crtc->dev;
1728         struct drm_i915_private *dev_priv = dev->dev_private;
1729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1730         int pipe = intel_crtc->pipe;
1731         int plane = intel_crtc->plane;
1732         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1733         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1734         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1735         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1736         u32 temp;
1737
1738         /* XXX: When our outputs are all unaware of DPMS modes other than off
1739          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1740          */
1741         switch (mode) {
1742         case DRM_MODE_DPMS_ON:
1743         case DRM_MODE_DPMS_STANDBY:
1744         case DRM_MODE_DPMS_SUSPEND:
1745                 /* Enable the DPLL */
1746                 temp = I915_READ(dpll_reg);
1747                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1748                         I915_WRITE(dpll_reg, temp);
1749                         I915_READ(dpll_reg);
1750                         /* Wait for the clocks to stabilize. */
1751                         udelay(150);
1752                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1753                         I915_READ(dpll_reg);
1754                         /* Wait for the clocks to stabilize. */
1755                         udelay(150);
1756                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1757                         I915_READ(dpll_reg);
1758                         /* Wait for the clocks to stabilize. */
1759                         udelay(150);
1760                 }
1761
1762                 /* Enable the pipe */
1763                 temp = I915_READ(pipeconf_reg);
1764                 if ((temp & PIPEACONF_ENABLE) == 0)
1765                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1766
1767                 /* Enable the plane */
1768                 temp = I915_READ(dspcntr_reg);
1769                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1770                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1771                         /* Flush the plane changes */
1772                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1773                 }
1774
1775                 intel_crtc_load_lut(crtc);
1776
1777                 intel_update_fbc(crtc, &crtc->mode);
1778
1779                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1780                 //intel_crtc_dpms_video(crtc, true); TODO
1781                 intel_update_watermarks(dev);
1782         break;
1783         case DRM_MODE_DPMS_OFF:
1784                 intel_update_watermarks(dev);
1785                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1786                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1787
1788                 if (dev_priv->cfb_plane == plane &&
1789                     dev_priv->display.disable_fbc)
1790                         dev_priv->display.disable_fbc(dev);
1791
1792                 /* Disable the VGA plane that we never use */
1793                 i915_disable_vga(dev);
1794
1795                 /* Disable display plane */
1796                 temp = I915_READ(dspcntr_reg);
1797                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1798                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1799                         /* Flush the plane changes */
1800                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1801                         I915_READ(dspbase_reg);
1802                 }
1803
1804                 if (!IS_I9XX(dev)) {
1805                         /* Wait for vblank for the disable to take effect */
1806                         intel_wait_for_vblank(dev);
1807                 }
1808
1809                 /* Next, disable display pipes */
1810                 temp = I915_READ(pipeconf_reg);
1811                 if ((temp & PIPEACONF_ENABLE) != 0) {
1812                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1813                         I915_READ(pipeconf_reg);
1814                 }
1815
1816                 /* Wait for vblank for the disable to take effect. */
1817                 intel_wait_for_vblank(dev);
1818
1819                 temp = I915_READ(dpll_reg);
1820                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1821                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1822                         I915_READ(dpll_reg);
1823                 }
1824
1825                 /* Wait for the clocks to turn off. */
1826                 udelay(150);
1827                 break;
1828         }
1829 }
1830
1831 /**
1832  * Sets the power management mode of the pipe and plane.
1833  *
1834  * This code should probably grow support for turning the cursor off and back
1835  * on appropriately at the same time as we're turning the pipe off/on.
1836  */
1837 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1838 {
1839         struct drm_device *dev = crtc->dev;
1840         struct drm_i915_private *dev_priv = dev->dev_private;
1841         struct drm_i915_master_private *master_priv;
1842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1843         int pipe = intel_crtc->pipe;
1844         bool enabled;
1845
1846         dev_priv->display.dpms(crtc, mode);
1847
1848         intel_crtc->dpms_mode = mode;
1849
1850         if (!dev->primary->master)
1851                 return;
1852
1853         master_priv = dev->primary->master->driver_priv;
1854         if (!master_priv->sarea_priv)
1855                 return;
1856
1857         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1858
1859         switch (pipe) {
1860         case 0:
1861                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1862                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1863                 break;
1864         case 1:
1865                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1866                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1867                 break;
1868         default:
1869                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1870                 break;
1871         }
1872 }
1873
1874 static void intel_crtc_prepare (struct drm_crtc *crtc)
1875 {
1876         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1877         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1878 }
1879
1880 static void intel_crtc_commit (struct drm_crtc *crtc)
1881 {
1882         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1883         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1884 }
1885
1886 void intel_encoder_prepare (struct drm_encoder *encoder)
1887 {
1888         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1889         /* lvds has its own version of prepare see intel_lvds_prepare */
1890         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1891 }
1892
1893 void intel_encoder_commit (struct drm_encoder *encoder)
1894 {
1895         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1896         /* lvds has its own version of commit see intel_lvds_commit */
1897         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1898 }
1899
1900 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1901                                   struct drm_display_mode *mode,
1902                                   struct drm_display_mode *adjusted_mode)
1903 {
1904         struct drm_device *dev = crtc->dev;
1905         if (IS_IGDNG(dev)) {
1906                 /* FDI link clock is fixed at 2.7G */
1907                 if (mode->clock * 3 > 27000 * 4)
1908                         return MODE_CLOCK_HIGH;
1909         }
1910         return true;
1911 }
1912
1913 static int i945_get_display_clock_speed(struct drm_device *dev)
1914 {
1915         return 400000;
1916 }
1917
1918 static int i915_get_display_clock_speed(struct drm_device *dev)
1919 {
1920         return 333000;
1921 }
1922
1923 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
1924 {
1925         return 200000;
1926 }
1927
1928 static int i915gm_get_display_clock_speed(struct drm_device *dev)
1929 {
1930         u16 gcfgc = 0;
1931
1932         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1933
1934         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1935                 return 133000;
1936         else {
1937                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1938                 case GC_DISPLAY_CLOCK_333_MHZ:
1939                         return 333000;
1940                 default:
1941                 case GC_DISPLAY_CLOCK_190_200_MHZ:
1942                         return 190000;
1943                 }
1944         }
1945 }
1946
1947 static int i865_get_display_clock_speed(struct drm_device *dev)
1948 {
1949         return 266000;
1950 }
1951
1952 static int i855_get_display_clock_speed(struct drm_device *dev)
1953 {
1954         u16 hpllcc = 0;
1955         /* Assume that the hardware is in the high speed state.  This
1956          * should be the default.
1957          */
1958         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1959         case GC_CLOCK_133_200:
1960         case GC_CLOCK_100_200:
1961                 return 200000;
1962         case GC_CLOCK_166_250:
1963                 return 250000;
1964         case GC_CLOCK_100_133:
1965                 return 133000;
1966         }
1967
1968         /* Shouldn't happen */
1969         return 0;
1970 }
1971
1972 static int i830_get_display_clock_speed(struct drm_device *dev)
1973 {
1974         return 133000;
1975 }
1976
1977 /**
1978  * Return the pipe currently connected to the panel fitter,
1979  * or -1 if the panel fitter is not present or not in use
1980  */
1981 static int intel_panel_fitter_pipe (struct drm_device *dev)
1982 {
1983         struct drm_i915_private *dev_priv = dev->dev_private;
1984         u32  pfit_control;
1985
1986         /* i830 doesn't have a panel fitter */
1987         if (IS_I830(dev))
1988                 return -1;
1989
1990         pfit_control = I915_READ(PFIT_CONTROL);
1991
1992         /* See if the panel fitter is in use */
1993         if ((pfit_control & PFIT_ENABLE) == 0)
1994                 return -1;
1995
1996         /* 965 can place panel fitter on either pipe */
1997         if (IS_I965G(dev))
1998                 return (pfit_control >> 29) & 0x3;
1999
2000         /* older chips can only use pipe 1 */
2001         return 1;
2002 }
2003
2004 struct fdi_m_n {
2005         u32        tu;
2006         u32        gmch_m;
2007         u32        gmch_n;
2008         u32        link_m;
2009         u32        link_n;
2010 };
2011
2012 static void
2013 fdi_reduce_ratio(u32 *num, u32 *den)
2014 {
2015         while (*num > 0xffffff || *den > 0xffffff) {
2016                 *num >>= 1;
2017                 *den >>= 1;
2018         }
2019 }
2020
2021 #define DATA_N 0x800000
2022 #define LINK_N 0x80000
2023
2024 static void
2025 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
2026                 int pixel_clock, int link_clock,
2027                 struct fdi_m_n *m_n)
2028 {
2029         u64 temp;
2030
2031         m_n->tu = 64; /* default size */
2032
2033         temp = (u64) DATA_N * pixel_clock;
2034         temp = div_u64(temp, link_clock);
2035         m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
2036         m_n->gmch_n = DATA_N;
2037         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2038
2039         temp = (u64) LINK_N * pixel_clock;
2040         m_n->link_m = div_u64(temp, link_clock);
2041         m_n->link_n = LINK_N;
2042         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2043 }
2044
2045
2046 struct intel_watermark_params {
2047         unsigned long fifo_size;
2048         unsigned long max_wm;
2049         unsigned long default_wm;
2050         unsigned long guard_size;
2051         unsigned long cacheline_size;
2052 };
2053
2054 /* IGD has different values for various configs */
2055 static struct intel_watermark_params igd_display_wm = {
2056         IGD_DISPLAY_FIFO,
2057         IGD_MAX_WM,
2058         IGD_DFT_WM,
2059         IGD_GUARD_WM,
2060         IGD_FIFO_LINE_SIZE
2061 };
2062 static struct intel_watermark_params igd_display_hplloff_wm = {
2063         IGD_DISPLAY_FIFO,
2064         IGD_MAX_WM,
2065         IGD_DFT_HPLLOFF_WM,
2066         IGD_GUARD_WM,
2067         IGD_FIFO_LINE_SIZE
2068 };
2069 static struct intel_watermark_params igd_cursor_wm = {
2070         IGD_CURSOR_FIFO,
2071         IGD_CURSOR_MAX_WM,
2072         IGD_CURSOR_DFT_WM,
2073         IGD_CURSOR_GUARD_WM,
2074         IGD_FIFO_LINE_SIZE,
2075 };
2076 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2077         IGD_CURSOR_FIFO,
2078         IGD_CURSOR_MAX_WM,
2079         IGD_CURSOR_DFT_WM,
2080         IGD_CURSOR_GUARD_WM,
2081         IGD_FIFO_LINE_SIZE
2082 };
2083 static struct intel_watermark_params i945_wm_info = {
2084         I945_FIFO_SIZE,
2085         I915_MAX_WM,
2086         1,
2087         2,
2088         I915_FIFO_LINE_SIZE
2089 };
2090 static struct intel_watermark_params i915_wm_info = {
2091         I915_FIFO_SIZE,
2092         I915_MAX_WM,
2093         1,
2094         2,
2095         I915_FIFO_LINE_SIZE
2096 };
2097 static struct intel_watermark_params i855_wm_info = {
2098         I855GM_FIFO_SIZE,
2099         I915_MAX_WM,
2100         1,
2101         2,
2102         I830_FIFO_LINE_SIZE
2103 };
2104 static struct intel_watermark_params i830_wm_info = {
2105         I830_FIFO_SIZE,
2106         I915_MAX_WM,
2107         1,
2108         2,
2109         I830_FIFO_LINE_SIZE
2110 };
2111
2112 /**
2113  * intel_calculate_wm - calculate watermark level
2114  * @clock_in_khz: pixel clock
2115  * @wm: chip FIFO params
2116  * @pixel_size: display pixel size
2117  * @latency_ns: memory latency for the platform
2118  *
2119  * Calculate the watermark level (the level at which the display plane will
2120  * start fetching from memory again).  Each chip has a different display
2121  * FIFO size and allocation, so the caller needs to figure that out and pass
2122  * in the correct intel_watermark_params structure.
2123  *
2124  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2125  * on the pixel size.  When it reaches the watermark level, it'll start
2126  * fetching FIFO line sized based chunks from memory until the FIFO fills
2127  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2128  * will occur, and a display engine hang could result.
2129  */
2130 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2131                                         struct intel_watermark_params *wm,
2132                                         int pixel_size,
2133                                         unsigned long latency_ns)
2134 {
2135         long entries_required, wm_size;
2136
2137         /*
2138          * Note: we need to make sure we don't overflow for various clock &
2139          * latency values.
2140          * clocks go from a few thousand to several hundred thousand.
2141          * latency is usually a few thousand
2142          */
2143         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2144                 1000;
2145         entries_required /= wm->cacheline_size;
2146
2147         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2148
2149         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2150
2151         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2152
2153         /* Don't promote wm_size to unsigned... */
2154         if (wm_size > (long)wm->max_wm)
2155                 wm_size = wm->max_wm;
2156         if (wm_size <= 0)
2157                 wm_size = wm->default_wm;
2158         return wm_size;
2159 }
2160
2161 struct cxsr_latency {
2162         int is_desktop;
2163         unsigned long fsb_freq;
2164         unsigned long mem_freq;
2165         unsigned long display_sr;
2166         unsigned long display_hpll_disable;
2167         unsigned long cursor_sr;
2168         unsigned long cursor_hpll_disable;
2169 };
2170
2171 static struct cxsr_latency cxsr_latency_table[] = {
2172         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2173         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2174         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2175
2176         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2177         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2178         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2179
2180         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2181         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2182         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2183
2184         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2185         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2186         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2187
2188         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2189         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2190         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2191
2192         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2193         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2194         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2195 };
2196
2197 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2198                                                    int mem)
2199 {
2200         int i;
2201         struct cxsr_latency *latency;
2202
2203         if (fsb == 0 || mem == 0)
2204                 return NULL;
2205
2206         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2207                 latency = &cxsr_latency_table[i];
2208                 if (is_desktop == latency->is_desktop &&
2209                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2210                         return latency;
2211         }
2212
2213         DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2214
2215         return NULL;
2216 }
2217
2218 static void igd_disable_cxsr(struct drm_device *dev)
2219 {
2220         struct drm_i915_private *dev_priv = dev->dev_private;
2221         u32 reg;
2222
2223         /* deactivate cxsr */
2224         reg = I915_READ(DSPFW3);
2225         reg &= ~(IGD_SELF_REFRESH_EN);
2226         I915_WRITE(DSPFW3, reg);
2227         DRM_INFO("Big FIFO is disabled\n");
2228 }
2229
2230 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2231                             int pixel_size)
2232 {
2233         struct drm_i915_private *dev_priv = dev->dev_private;
2234         u32 reg;
2235         unsigned long wm;
2236         struct cxsr_latency *latency;
2237
2238         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2239                 dev_priv->mem_freq);
2240         if (!latency) {
2241                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2242                 igd_disable_cxsr(dev);
2243                 return;
2244         }
2245
2246         /* Display SR */
2247         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2248                                 latency->display_sr);
2249         reg = I915_READ(DSPFW1);
2250         reg &= 0x7fffff;
2251         reg |= wm << 23;
2252         I915_WRITE(DSPFW1, reg);
2253         DRM_DEBUG("DSPFW1 register is %x\n", reg);
2254
2255         /* cursor SR */
2256         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2257                                 latency->cursor_sr);
2258         reg = I915_READ(DSPFW3);
2259         reg &= ~(0x3f << 24);
2260         reg |= (wm & 0x3f) << 24;
2261         I915_WRITE(DSPFW3, reg);
2262
2263         /* Display HPLL off SR */
2264         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2265                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2266         reg = I915_READ(DSPFW3);
2267         reg &= 0xfffffe00;
2268         reg |= wm & 0x1ff;
2269         I915_WRITE(DSPFW3, reg);
2270
2271         /* cursor HPLL off SR */
2272         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2273                                 latency->cursor_hpll_disable);
2274         reg = I915_READ(DSPFW3);
2275         reg &= ~(0x3f << 16);
2276         reg |= (wm & 0x3f) << 16;
2277         I915_WRITE(DSPFW3, reg);
2278         DRM_DEBUG("DSPFW3 register is %x\n", reg);
2279
2280         /* activate cxsr */
2281         reg = I915_READ(DSPFW3);
2282         reg |= IGD_SELF_REFRESH_EN;
2283         I915_WRITE(DSPFW3, reg);
2284
2285         DRM_INFO("Big FIFO is enabled\n");
2286
2287         return;
2288 }
2289
2290 /*
2291  * Latency for FIFO fetches is dependent on several factors:
2292  *   - memory configuration (speed, channels)
2293  *   - chipset
2294  *   - current MCH state
2295  * It can be fairly high in some situations, so here we assume a fairly
2296  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2297  * set this value too high, the FIFO will fetch frequently to stay full)
2298  * and power consumption (set it too low to save power and we might see
2299  * FIFO underruns and display "flicker").
2300  *
2301  * A value of 5us seems to be a good balance; safe for very low end
2302  * platforms but not overly aggressive on lower latency configs.
2303  */
2304 const static int latency_ns = 5000;
2305
2306 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2307 {
2308         struct drm_i915_private *dev_priv = dev->dev_private;
2309         uint32_t dsparb = I915_READ(DSPARB);
2310         int size;
2311
2312         if (plane == 0)
2313                 size = dsparb & 0x7f;
2314         else
2315                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2316                         (dsparb & 0x7f);
2317
2318         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2319                   size);
2320
2321         return size;
2322 }
2323
2324 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2325 {
2326         struct drm_i915_private *dev_priv = dev->dev_private;
2327         uint32_t dsparb = I915_READ(DSPARB);
2328         int size;
2329
2330         if (plane == 0)
2331                 size = dsparb & 0x1ff;
2332         else
2333                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2334                         (dsparb & 0x1ff);
2335         size >>= 1; /* Convert to cachelines */
2336
2337         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2338                   size);
2339
2340         return size;
2341 }
2342
2343 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2344 {
2345         struct drm_i915_private *dev_priv = dev->dev_private;
2346         uint32_t dsparb = I915_READ(DSPARB);
2347         int size;
2348
2349         size = dsparb & 0x7f;
2350         size >>= 2; /* Convert to cachelines */
2351
2352         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2353                   size);
2354
2355         return size;
2356 }
2357
2358 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2359 {
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         uint32_t dsparb = I915_READ(DSPARB);
2362         int size;
2363
2364         size = dsparb & 0x7f;
2365         size >>= 1; /* Convert to cachelines */
2366
2367         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2368                   size);
2369
2370         return size;
2371 }
2372
2373 static void g4x_update_wm(struct drm_device *dev, int unused, int unused2,
2374                           int unused3, int unused4)
2375 {
2376         struct drm_i915_private *dev_priv = dev->dev_private;
2377         u32 fw_blc_self = I915_READ(FW_BLC_SELF);
2378
2379         if (i915_powersave)
2380                 fw_blc_self |= FW_BLC_SELF_EN;
2381         else
2382                 fw_blc_self &= ~FW_BLC_SELF_EN;
2383         I915_WRITE(FW_BLC_SELF, fw_blc_self);
2384 }
2385
2386 static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
2387                            int unused3, int unused4)
2388 {
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390
2391         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2392
2393         /* 965 has limitations... */
2394         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2395         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2396 }
2397
2398 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2399                            int planeb_clock, int sr_hdisplay, int pixel_size)
2400 {
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         uint32_t fwater_lo;
2403         uint32_t fwater_hi;
2404         int total_size, cacheline_size, cwm, srwm = 1;
2405         int planea_wm, planeb_wm;
2406         struct intel_watermark_params planea_params, planeb_params;
2407         unsigned long line_time_us;
2408         int sr_clock, sr_entries = 0;
2409
2410         /* Create copies of the base settings for each pipe */
2411         if (IS_I965GM(dev) || IS_I945GM(dev))
2412                 planea_params = planeb_params = i945_wm_info;
2413         else if (IS_I9XX(dev))
2414                 planea_params = planeb_params = i915_wm_info;
2415         else
2416                 planea_params = planeb_params = i855_wm_info;
2417
2418         /* Grab a couple of global values before we overwrite them */
2419         total_size = planea_params.fifo_size;
2420         cacheline_size = planea_params.cacheline_size;
2421
2422         /* Update per-plane FIFO sizes */
2423         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2424         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2425
2426         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2427                                        pixel_size, latency_ns);
2428         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2429                                        pixel_size, latency_ns);
2430         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2431
2432         /*
2433          * Overlay gets an aggressive default since video jitter is bad.
2434          */
2435         cwm = 2;
2436
2437         /* Calc sr entries for one plane configs */
2438         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2439             (!planea_clock || !planeb_clock)) {
2440                 /* self-refresh has much higher latency */
2441                 const static int sr_latency_ns = 6000;
2442
2443                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2444                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2445
2446                 /* Use ns/us then divide to preserve precision */
2447                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2448                               pixel_size * sr_hdisplay) / 1000;
2449                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2450                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2451                 srwm = total_size - sr_entries;
2452                 if (srwm < 0)
2453                         srwm = 1;
2454                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2455         }
2456
2457         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2458                   planea_wm, planeb_wm, cwm, srwm);
2459
2460         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2461         fwater_hi = (cwm & 0x1f);
2462
2463         /* Set request length to 8 cachelines per fetch */
2464         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2465         fwater_hi = fwater_hi | (1 << 8);
2466
2467         I915_WRITE(FW_BLC, fwater_lo);
2468         I915_WRITE(FW_BLC2, fwater_hi);
2469 }
2470
2471 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2472                            int unused2, int pixel_size)
2473 {
2474         struct drm_i915_private *dev_priv = dev->dev_private;
2475         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2476         int planea_wm;
2477
2478         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2479
2480         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2481                                        pixel_size, latency_ns);
2482         fwater_lo |= (3<<8) | planea_wm;
2483
2484         DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2485
2486         I915_WRITE(FW_BLC, fwater_lo);
2487 }
2488
2489 /**
2490  * intel_update_watermarks - update FIFO watermark values based on current modes
2491  *
2492  * Calculate watermark values for the various WM regs based on current mode
2493  * and plane configuration.
2494  *
2495  * There are several cases to deal with here:
2496  *   - normal (i.e. non-self-refresh)
2497  *   - self-refresh (SR) mode
2498  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2499  *   - lines are small relative to FIFO size (buffer can hold more than 2
2500  *     lines), so need to account for TLB latency
2501  *
2502  *   The normal calculation is:
2503  *     watermark = dotclock * bytes per pixel * latency
2504  *   where latency is platform & configuration dependent (we assume pessimal
2505  *   values here).
2506  *
2507  *   The SR calculation is:
2508  *     watermark = (trunc(latency/line time)+1) * surface width *
2509  *       bytes per pixel
2510  *   where
2511  *     line time = htotal / dotclock
2512  *   and latency is assumed to be high, as above.
2513  *
2514  * The final value programmed to the register should always be rounded up,
2515  * and include an extra 2 entries to account for clock crossings.
2516  *
2517  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2518  * to set the non-SR watermarks to 8.
2519   */
2520 static void intel_update_watermarks(struct drm_device *dev)
2521 {
2522         struct drm_i915_private *dev_priv = dev->dev_private;
2523         struct drm_crtc *crtc;
2524         struct intel_crtc *intel_crtc;
2525         int sr_hdisplay = 0;
2526         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2527         int enabled = 0, pixel_size = 0;
2528
2529         /* Get the clock config from both planes */
2530         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2531                 intel_crtc = to_intel_crtc(crtc);
2532                 if (crtc->enabled) {
2533                         enabled++;
2534                         if (intel_crtc->plane == 0) {
2535                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2536                                           intel_crtc->pipe, crtc->mode.clock);
2537                                 planea_clock = crtc->mode.clock;
2538                         } else {
2539                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2540                                           intel_crtc->pipe, crtc->mode.clock);
2541                                 planeb_clock = crtc->mode.clock;
2542                         }
2543                         sr_hdisplay = crtc->mode.hdisplay;
2544                         sr_clock = crtc->mode.clock;
2545                         if (crtc->fb)
2546                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2547                         else
2548                                 pixel_size = 4; /* by default */
2549                 }
2550         }
2551
2552         if (enabled <= 0)
2553                 return;
2554
2555         /* Single plane configs can enable self refresh */
2556         if (enabled == 1 && IS_IGD(dev))
2557                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2558         else if (IS_IGD(dev))
2559                 igd_disable_cxsr(dev);
2560
2561         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2562                                     sr_hdisplay, pixel_size);
2563 }
2564
2565 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2566                                struct drm_display_mode *mode,
2567                                struct drm_display_mode *adjusted_mode,
2568                                int x, int y,
2569                                struct drm_framebuffer *old_fb)
2570 {
2571         struct drm_device *dev = crtc->dev;
2572         struct drm_i915_private *dev_priv = dev->dev_private;
2573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2574         int pipe = intel_crtc->pipe;
2575         int plane = intel_crtc->plane;
2576         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2577         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2578         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2579         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2580         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2581         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2582         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2583         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2584         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2585         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2586         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2587         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2588         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2589         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2590         int refclk, num_outputs = 0;
2591         intel_clock_t clock, reduced_clock;
2592         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2593         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2594         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2595         bool is_edp = false;
2596         struct drm_mode_config *mode_config = &dev->mode_config;
2597         struct drm_connector *connector;
2598         const intel_limit_t *limit;
2599         int ret;
2600         struct fdi_m_n m_n = {0};
2601         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2602         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2603         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2604         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2605         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2606         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2607         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2608         int lvds_reg = LVDS;
2609         u32 temp;
2610         int sdvo_pixel_multiply;
2611         int target_clock;
2612
2613         drm_vblank_pre_modeset(dev, pipe);
2614
2615         list_for_each_entry(connector, &mode_config->connector_list, head) {
2616                 struct intel_output *intel_output = to_intel_output(connector);
2617
2618                 if (!connector->encoder || connector->encoder->crtc != crtc)
2619                         continue;
2620
2621                 switch (intel_output->type) {
2622                 case INTEL_OUTPUT_LVDS:
2623                         is_lvds = true;
2624                         break;
2625                 case INTEL_OUTPUT_SDVO:
2626                 case INTEL_OUTPUT_HDMI:
2627                         is_sdvo = true;
2628                         if (intel_output->needs_tv_clock)
2629                                 is_tv = true;
2630                         break;
2631                 case INTEL_OUTPUT_DVO:
2632                         is_dvo = true;
2633                         break;
2634                 case INTEL_OUTPUT_TVOUT:
2635                         is_tv = true;
2636                         break;
2637                 case INTEL_OUTPUT_ANALOG:
2638                         is_crt = true;
2639                         break;
2640                 case INTEL_OUTPUT_DISPLAYPORT:
2641                         is_dp = true;
2642                         break;
2643                 case INTEL_OUTPUT_EDP:
2644                         is_edp = true;
2645                         break;
2646                 }
2647
2648                 num_outputs++;
2649         }
2650
2651         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2652                 refclk = dev_priv->lvds_ssc_freq * 1000;
2653                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2654         } else if (IS_I9XX(dev)) {
2655                 refclk = 96000;
2656                 if (IS_IGDNG(dev))
2657                         refclk = 120000; /* 120Mhz refclk */
2658         } else {
2659                 refclk = 48000;
2660         }
2661
2662
2663         /*
2664          * Returns a set of divisors for the desired target clock with the given
2665          * refclk, or FALSE.  The returned values represent the clock equation:
2666          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2667          */
2668         limit = intel_limit(crtc);
2669         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2670         if (!ok) {
2671                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2672                 drm_vblank_post_modeset(dev, pipe);
2673                 return -EINVAL;
2674         }
2675
2676         if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2677                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2678                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2679                                                             (adjusted_mode->clock*3/4),
2680                                                             refclk,
2681                                                             &reduced_clock);
2682         }
2683
2684         /* SDVO TV has fixed PLL values depend on its clock range,
2685            this mirrors vbios setting. */
2686         if (is_sdvo && is_tv) {
2687                 if (adjusted_mode->clock >= 100000
2688                                 && adjusted_mode->clock < 140500) {
2689                         clock.p1 = 2;
2690                         clock.p2 = 10;
2691                         clock.n = 3;
2692                         clock.m1 = 16;
2693                         clock.m2 = 8;
2694                 } else if (adjusted_mode->clock >= 140500
2695                                 && adjusted_mode->clock <= 200000) {
2696                         clock.p1 = 1;
2697                         clock.p2 = 10;
2698                         clock.n = 6;
2699                         clock.m1 = 12;
2700                         clock.m2 = 8;
2701                 }
2702         }
2703
2704         /* FDI link */
2705         if (IS_IGDNG(dev)) {
2706                 int lane, link_bw;
2707                 /* eDP doesn't require FDI link, so just set DP M/N
2708                    according to current link config */
2709                 if (is_edp) {
2710                         struct drm_connector *edp;
2711                         target_clock = mode->clock;
2712                         edp = intel_pipe_get_output(crtc);
2713                         intel_edp_link_config(to_intel_output(edp),
2714                                         &lane, &link_bw);
2715                 } else {
2716                         /* DP over FDI requires target mode clock
2717                            instead of link clock */
2718                         if (is_dp)
2719                                 target_clock = mode->clock;
2720                         else
2721                                 target_clock = adjusted_mode->clock;
2722                         lane = 4;
2723                         link_bw = 270000;
2724                 }
2725                 igdng_compute_m_n(3, lane, target_clock,
2726                                   link_bw, &m_n);
2727         }
2728
2729         if (IS_IGD(dev)) {
2730                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2731                 if (has_reduced_clock)
2732                         fp2 = (1 << reduced_clock.n) << 16 |
2733                                 reduced_clock.m1 << 8 | reduced_clock.m2;
2734         } else {
2735                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2736                 if (has_reduced_clock)
2737                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2738                                 reduced_clock.m2;
2739         }
2740
2741         if (!IS_IGDNG(dev))
2742                 dpll = DPLL_VGA_MODE_DIS;
2743
2744         if (IS_I9XX(dev)) {
2745                 if (is_lvds)
2746                         dpll |= DPLLB_MODE_LVDS;
2747                 else
2748                         dpll |= DPLLB_MODE_DAC_SERIAL;
2749                 if (is_sdvo) {
2750                         dpll |= DPLL_DVO_HIGH_SPEED;
2751                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2752                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2753                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2754                         else if (IS_IGDNG(dev))
2755                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2756                 }
2757                 if (is_dp)
2758                         dpll |= DPLL_DVO_HIGH_SPEED;
2759
2760                 /* compute bitmask from p1 value */
2761                 if (IS_IGD(dev))
2762                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2763                 else {
2764                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2765                         /* also FPA1 */
2766                         if (IS_IGDNG(dev))
2767                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2768                         if (IS_G4X(dev) && has_reduced_clock)
2769                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2770                 }
2771                 switch (clock.p2) {
2772                 case 5:
2773                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2774                         break;
2775                 case 7:
2776                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2777                         break;
2778                 case 10:
2779                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2780                         break;
2781                 case 14:
2782                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2783                         break;
2784                 }
2785                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2786                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2787         } else {
2788                 if (is_lvds) {
2789                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2790                 } else {
2791                         if (clock.p1 == 2)
2792                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
2793                         else
2794                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2795                         if (clock.p2 == 4)
2796                                 dpll |= PLL_P2_DIVIDE_BY_4;
2797                 }
2798         }
2799
2800         if (is_sdvo && is_tv)
2801                 dpll |= PLL_REF_INPUT_TVCLKINBC;
2802         else if (is_tv)
2803                 /* XXX: just matching BIOS for now */
2804                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
2805                 dpll |= 3;
2806         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2807                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2808         else
2809                 dpll |= PLL_REF_INPUT_DREFCLK;
2810
2811         /* setup pipeconf */
2812         pipeconf = I915_READ(pipeconf_reg);
2813
2814         /* Set up the display plane register */
2815         dspcntr = DISPPLANE_GAMMA_ENABLE;
2816
2817         /* IGDNG's plane is forced to pipe, bit 24 is to
2818            enable color space conversion */
2819         if (!IS_IGDNG(dev)) {
2820                 if (pipe == 0)
2821                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
2822                 else
2823                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2824         }
2825
2826         if (pipe == 0 && !IS_I965G(dev)) {
2827                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2828                  * core speed.
2829                  *
2830                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2831                  * pipe == 0 check?
2832                  */
2833                 if (mode->clock >
2834                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
2835                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
2836                 else
2837                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2838         }
2839
2840         dspcntr |= DISPLAY_PLANE_ENABLE;
2841         pipeconf |= PIPEACONF_ENABLE;
2842         dpll |= DPLL_VCO_ENABLE;
2843
2844
2845         /* Disable the panel fitter if it was on our pipe */
2846         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2847                 I915_WRITE(PFIT_CONTROL, 0);
2848
2849         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2850         drm_mode_debug_printmodeline(mode);
2851
2852         /* assign to IGDNG registers */
2853         if (IS_IGDNG(dev)) {
2854                 fp_reg = pch_fp_reg;
2855                 dpll_reg = pch_dpll_reg;
2856         }
2857
2858         if (is_edp) {
2859                 igdng_disable_pll_edp(crtc);
2860         } else if ((dpll & DPLL_VCO_ENABLE)) {
2861                 I915_WRITE(fp_reg, fp);
2862                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2863                 I915_READ(dpll_reg);
2864                 udelay(150);
2865         }
2866
2867         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2868          * This is an exception to the general rule that mode_set doesn't turn
2869          * things on.
2870          */
2871         if (is_lvds) {
2872                 u32 lvds;
2873
2874                 if (IS_IGDNG(dev))
2875                         lvds_reg = PCH_LVDS;
2876
2877                 lvds = I915_READ(lvds_reg);
2878                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2879                 /* Set the B0-B3 data pairs corresponding to whether we're going to
2880                  * set the DPLLs for dual-channel mode or not.
2881                  */
2882                 if (clock.p2 == 7)
2883                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2884                 else
2885                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2886
2887                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2888                  * appropriately here, but we need to look more thoroughly into how
2889                  * panels behave in the two modes.
2890                  */
2891
2892                 I915_WRITE(lvds_reg, lvds);
2893                 I915_READ(lvds_reg);
2894         }
2895         if (is_dp)
2896                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2897
2898         if (!is_edp) {
2899                 I915_WRITE(fp_reg, fp);
2900                 I915_WRITE(dpll_reg, dpll);
2901                 I915_READ(dpll_reg);
2902                 /* Wait for the clocks to stabilize. */
2903                 udelay(150);
2904
2905                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2906                         if (is_sdvo) {
2907                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2908                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2909                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2910                         } else
2911                                 I915_WRITE(dpll_md_reg, 0);
2912                 } else {
2913                         /* write it again -- the BIOS does, after all */
2914                         I915_WRITE(dpll_reg, dpll);
2915                 }
2916                 I915_READ(dpll_reg);
2917                 /* Wait for the clocks to stabilize. */
2918                 udelay(150);
2919         }
2920
2921         if (is_lvds && has_reduced_clock && i915_powersave) {
2922                 I915_WRITE(fp_reg + 4, fp2);
2923                 intel_crtc->lowfreq_avail = true;
2924                 if (HAS_PIPE_CXSR(dev)) {
2925                         DRM_DEBUG("enabling CxSR downclocking\n");
2926                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
2927                 }
2928         } else {
2929                 I915_WRITE(fp_reg + 4, fp);
2930                 intel_crtc->lowfreq_avail = false;
2931                 if (HAS_PIPE_CXSR(dev)) {
2932                         DRM_DEBUG("disabling CxSR downclocking\n");
2933                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
2934                 }
2935         }
2936
2937         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2938                    ((adjusted_mode->crtc_htotal - 1) << 16));
2939         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2940                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
2941         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2942                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
2943         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2944                    ((adjusted_mode->crtc_vtotal - 1) << 16));
2945         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2946                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
2947         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2948                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
2949         /* pipesrc and dspsize control the size that is scaled from, which should
2950          * always be the user's requested size.
2951          */
2952         if (!IS_IGDNG(dev)) {
2953                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2954                                 (mode->hdisplay - 1));
2955                 I915_WRITE(dsppos_reg, 0);
2956         }
2957         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2958
2959         if (IS_IGDNG(dev)) {
2960                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2961                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2962                 I915_WRITE(link_m1_reg, m_n.link_m);
2963                 I915_WRITE(link_n1_reg, m_n.link_n);
2964
2965                 if (is_edp) {
2966                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
2967                 } else {
2968                         /* enable FDI RX PLL too */
2969                         temp = I915_READ(fdi_rx_reg);
2970                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2971                         udelay(200);
2972                 }
2973         }
2974
2975         I915_WRITE(pipeconf_reg, pipeconf);
2976         I915_READ(pipeconf_reg);
2977
2978         intel_wait_for_vblank(dev);
2979
2980         if (IS_IGDNG(dev)) {
2981                 /* enable address swizzle for tiling buffer */
2982                 temp = I915_READ(DISP_ARB_CTL);
2983                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
2984         }
2985
2986         I915_WRITE(dspcntr_reg, dspcntr);
2987
2988         /* Flush the plane changes */
2989         ret = intel_pipe_set_base(crtc, x, y, old_fb);
2990
2991         intel_update_fbc(crtc, &crtc->mode);
2992
2993         intel_update_watermarks(dev);
2994
2995         drm_vblank_post_modeset(dev, pipe);
2996
2997         return ret;
2998 }
2999
3000 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3001 void intel_crtc_load_lut(struct drm_crtc *crtc)
3002 {
3003         struct drm_device *dev = crtc->dev;
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3006         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3007         int i;
3008
3009         /* The clocks have to be on to load the palette. */
3010         if (!crtc->enabled)
3011                 return;
3012
3013         /* use legacy palette for IGDNG */
3014         if (IS_IGDNG(dev))
3015                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3016                                                    LGC_PALETTE_B;
3017
3018         for (i = 0; i < 256; i++) {
3019                 I915_WRITE(palreg + 4 * i,
3020                            (intel_crtc->lut_r[i] << 16) |
3021                            (intel_crtc->lut_g[i] << 8) |
3022                            intel_crtc->lut_b[i]);
3023         }
3024 }
3025
3026 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3027                                  struct drm_file *file_priv,
3028                                  uint32_t handle,
3029                                  uint32_t width, uint32_t height)
3030 {
3031         struct drm_device *dev = crtc->dev;
3032         struct drm_i915_private *dev_priv = dev->dev_private;
3033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3034         struct drm_gem_object *bo;
3035         struct drm_i915_gem_object *obj_priv;
3036         int pipe = intel_crtc->pipe;
3037         int plane = intel_crtc->plane;
3038         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3039         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3040         uint32_t temp = I915_READ(control);
3041         size_t addr;
3042         int ret;
3043
3044         DRM_DEBUG("\n");
3045
3046         /* if we want to turn off the cursor ignore width and height */
3047         if (!handle) {
3048                 DRM_DEBUG("cursor off\n");
3049                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3050                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3051                         temp |= CURSOR_MODE_DISABLE;
3052                 } else {
3053                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3054                 }
3055                 addr = 0;
3056                 bo = NULL;
3057                 mutex_lock(&dev->struct_mutex);
3058                 goto finish;
3059         }
3060
3061         /* Currently we only support 64x64 cursors */
3062         if (width != 64 || height != 64) {
3063                 DRM_ERROR("we currently only support 64x64 cursors\n");
3064                 return -EINVAL;
3065         }
3066
3067         bo = drm_gem_object_lookup(dev, file_priv, handle);
3068         if (!bo)
3069                 return -ENOENT;
3070
3071         obj_priv = bo->driver_private;
3072
3073         if (bo->size < width * height * 4) {
3074                 DRM_ERROR("buffer is to small\n");
3075                 ret = -ENOMEM;
3076                 goto fail;
3077         }
3078
3079         /* we only need to pin inside GTT if cursor is non-phy */
3080         mutex_lock(&dev->struct_mutex);
3081         if (!dev_priv->cursor_needs_physical) {
3082                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3083                 if (ret) {
3084                         DRM_ERROR("failed to pin cursor bo\n");
3085                         goto fail_locked;
3086                 }
3087                 addr = obj_priv->gtt_offset;
3088         } else {
3089                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3090                 if (ret) {
3091                         DRM_ERROR("failed to attach phys object\n");
3092                         goto fail_locked;
3093                 }
3094                 addr = obj_priv->phys_obj->handle->busaddr;
3095         }
3096
3097         if (!IS_I9XX(dev))
3098                 I915_WRITE(CURSIZE, (height << 12) | width);
3099
3100         /* Hooray for CUR*CNTR differences */
3101         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3102                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3103                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3104                 temp |= (pipe << 28); /* Connect to correct pipe */
3105         } else {
3106                 temp &= ~(CURSOR_FORMAT_MASK);
3107                 temp |= CURSOR_ENABLE;
3108                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3109         }
3110
3111  finish:
3112         I915_WRITE(control, temp);
3113         I915_WRITE(base, addr);
3114
3115         if (intel_crtc->cursor_bo) {
3116                 if (dev_priv->cursor_needs_physical) {
3117                         if (intel_crtc->cursor_bo != bo)
3118                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3119                 } else
3120                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3121                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3122         }
3123
3124         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
3125                 intel_update_fbc(crtc, &crtc->mode);
3126
3127         mutex_unlock(&dev->struct_mutex);
3128
3129         intel_crtc->cursor_addr = addr;
3130         intel_crtc->cursor_bo = bo;
3131
3132         return 0;
3133 fail:
3134         mutex_lock(&dev->struct_mutex);
3135 fail_locked:
3136         drm_gem_object_unreference(bo);
3137         mutex_unlock(&dev->struct_mutex);
3138         return ret;
3139 }
3140
3141 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3142 {
3143         struct drm_device *dev = crtc->dev;
3144         struct drm_i915_private *dev_priv = dev->dev_private;
3145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3146         struct intel_framebuffer *intel_fb;
3147         int pipe = intel_crtc->pipe;
3148         uint32_t temp = 0;
3149         uint32_t adder;
3150
3151         if (crtc->fb) {
3152                 intel_fb = to_intel_framebuffer(crtc->fb);
3153                 intel_mark_busy(dev, intel_fb->obj);
3154         }
3155
3156         if (x < 0) {
3157                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3158                 x = -x;
3159         }
3160         if (y < 0) {
3161                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3162                 y = -y;
3163         }
3164
3165         temp |= x << CURSOR_X_SHIFT;
3166         temp |= y << CURSOR_Y_SHIFT;
3167
3168         adder = intel_crtc->cursor_addr;
3169         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3170         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3171
3172         return 0;
3173 }
3174
3175 /** Sets the color ramps on behalf of RandR */
3176 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3177                                  u16 blue, int regno)
3178 {
3179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3180
3181         intel_crtc->lut_r[regno] = red >> 8;
3182         intel_crtc->lut_g[regno] = green >> 8;
3183         intel_crtc->lut_b[regno] = blue >> 8;
3184 }
3185
3186 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3187                                  u16 *blue, uint32_t size)
3188 {
3189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3190         int i;
3191
3192         if (size != 256)
3193                 return;
3194
3195         for (i = 0; i < 256; i++) {
3196                 intel_crtc->lut_r[i] = red[i] >> 8;
3197                 intel_crtc->lut_g[i] = green[i] >> 8;
3198                 intel_crtc->lut_b[i] = blue[i] >> 8;
3199         }
3200
3201         intel_crtc_load_lut(crtc);
3202 }
3203
3204 /**
3205  * Get a pipe with a simple mode set on it for doing load-based monitor
3206  * detection.
3207  *
3208  * It will be up to the load-detect code to adjust the pipe as appropriate for
3209  * its requirements.  The pipe will be connected to no other outputs.
3210  *
3211  * Currently this code will only succeed if there is a pipe with no outputs
3212  * configured for it.  In the future, it could choose to temporarily disable
3213  * some outputs to free up a pipe for its use.
3214  *
3215  * \return crtc, or NULL if no pipes are available.
3216  */
3217
3218 /* VESA 640x480x72Hz mode to set on the pipe */
3219 static struct drm_display_mode load_detect_mode = {
3220         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3221                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3222 };
3223
3224 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3225                                             struct drm_display_mode *mode,
3226                                             int *dpms_mode)
3227 {
3228         struct intel_crtc *intel_crtc;
3229         struct drm_crtc *possible_crtc;
3230         struct drm_crtc *supported_crtc =NULL;
3231         struct drm_encoder *encoder = &intel_output->enc;
3232         struct drm_crtc *crtc = NULL;
3233         struct drm_device *dev = encoder->dev;
3234         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3235         struct drm_crtc_helper_funcs *crtc_funcs;
3236         int i = -1;
3237
3238         /*
3239          * Algorithm gets a little messy:
3240          *   - if the connector already has an assigned crtc, use it (but make
3241          *     sure it's on first)
3242          *   - try to find the first unused crtc that can drive this connector,
3243          *     and use that if we find one
3244          *   - if there are no unused crtcs available, try to use the first
3245          *     one we found that supports the connector
3246          */
3247
3248         /* See if we already have a CRTC for this connector */
3249         if (encoder->crtc) {
3250                 crtc = encoder->crtc;
3251                 /* Make sure the crtc and connector are running */
3252                 intel_crtc = to_intel_crtc(crtc);
3253                 *dpms_mode = intel_crtc->dpms_mode;
3254                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3255                         crtc_funcs = crtc->helper_private;
3256                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3257                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3258                 }
3259                 return crtc;
3260         }
3261
3262         /* Find an unused one (if possible) */
3263         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3264                 i++;
3265                 if (!(encoder->possible_crtcs & (1 << i)))
3266                         continue;
3267                 if (!possible_crtc->enabled) {
3268                         crtc = possible_crtc;
3269                         break;
3270                 }
3271                 if (!supported_crtc)
3272                         supported_crtc = possible_crtc;
3273         }
3274
3275         /*
3276          * If we didn't find an unused CRTC, don't use any.
3277          */
3278         if (!crtc) {
3279                 return NULL;
3280         }
3281
3282         encoder->crtc = crtc;
3283         intel_output->base.encoder = encoder;
3284         intel_output->load_detect_temp = true;
3285
3286         intel_crtc = to_intel_crtc(crtc);
3287         *dpms_mode = intel_crtc->dpms_mode;
3288
3289         if (!crtc->enabled) {
3290                 if (!mode)
3291                         mode = &load_detect_mode;
3292                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3293         } else {
3294                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3295                         crtc_funcs = crtc->helper_private;
3296                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3297                 }
3298
3299                 /* Add this connector to the crtc */
3300                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3301                 encoder_funcs->commit(encoder);
3302         }
3303         /* let the connector get through one full cycle before testing */
3304         intel_wait_for_vblank(dev);
3305
3306         return crtc;
3307 }
3308
3309 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3310 {
3311         struct drm_encoder *encoder = &intel_output->enc;
3312         struct drm_device *dev = encoder->dev;
3313         struct drm_crtc *crtc = encoder->crtc;
3314         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3315         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3316
3317         if (intel_output->load_detect_temp) {
3318                 encoder->crtc = NULL;
3319                 intel_output->base.encoder = NULL;
3320                 intel_output->load_detect_temp = false;
3321                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3322                 drm_helper_disable_unused_functions(dev);
3323         }
3324
3325         /* Switch crtc and output back off if necessary */
3326         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3327                 if (encoder->crtc == crtc)
3328                         encoder_funcs->dpms(encoder, dpms_mode);
3329                 crtc_funcs->dpms(crtc, dpms_mode);
3330         }
3331 }
3332
3333 /* Returns the clock of the currently programmed mode of the given pipe. */
3334 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3335 {
3336         struct drm_i915_private *dev_priv = dev->dev_private;
3337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338         int pipe = intel_crtc->pipe;
3339         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3340         u32 fp;
3341         intel_clock_t clock;
3342
3343         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3344                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3345         else
3346                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3347
3348         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3349         if (IS_IGD(dev)) {
3350                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3351                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3352         } else {
3353                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3354                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3355         }
3356
3357         if (IS_I9XX(dev)) {
3358                 if (IS_IGD(dev))
3359                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3360                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3361                 else
3362                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3363                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3364
3365                 switch (dpll & DPLL_MODE_MASK) {
3366                 case DPLLB_MODE_DAC_SERIAL:
3367                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3368                                 5 : 10;
3369                         break;
3370                 case DPLLB_MODE_LVDS:
3371                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3372                                 7 : 14;
3373                         break;
3374                 default:
3375                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3376                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3377                         return 0;
3378                 }
3379
3380                 /* XXX: Handle the 100Mhz refclk */
3381                 intel_clock(dev, 96000, &clock);
3382         } else {
3383                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3384
3385                 if (is_lvds) {
3386                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3387                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3388                         clock.p2 = 14;
3389
3390                         if ((dpll & PLL_REF_INPUT_MASK) ==
3391                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3392                                 /* XXX: might not be 66MHz */
3393                                 intel_clock(dev, 66000, &clock);
3394                         } else
3395                                 intel_clock(dev, 48000, &clock);
3396                 } else {
3397                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3398                                 clock.p1 = 2;
3399                         else {
3400                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3401                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3402                         }
3403                         if (dpll & PLL_P2_DIVIDE_BY_4)
3404                                 clock.p2 = 4;
3405                         else
3406                                 clock.p2 = 2;
3407
3408                         intel_clock(dev, 48000, &clock);
3409                 }
3410         }
3411
3412         /* XXX: It would be nice to validate the clocks, but we can't reuse
3413          * i830PllIsValid() because it relies on the xf86_config connector
3414          * configuration being accurate, which it isn't necessarily.
3415          */
3416
3417         return clock.dot;
3418 }
3419
3420 /** Returns the currently programmed mode of the given pipe. */
3421 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3422                                              struct drm_crtc *crtc)
3423 {
3424         struct drm_i915_private *dev_priv = dev->dev_private;
3425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426         int pipe = intel_crtc->pipe;
3427         struct drm_display_mode *mode;
3428         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3429         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3430         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3431         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3432
3433         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3434         if (!mode)
3435                 return NULL;
3436
3437         mode->clock = intel_crtc_clock_get(dev, crtc);
3438         mode->hdisplay = (htot & 0xffff) + 1;
3439         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3440         mode->hsync_start = (hsync & 0xffff) + 1;
3441         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3442         mode->vdisplay = (vtot & 0xffff) + 1;
3443         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3444         mode->vsync_start = (vsync & 0xffff) + 1;
3445         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3446
3447         drm_mode_set_name(mode);
3448         drm_mode_set_crtcinfo(mode, 0);
3449
3450         return mode;
3451 }
3452
3453 #define GPU_IDLE_TIMEOUT 500 /* ms */
3454
3455 /* When this timer fires, we've been idle for awhile */
3456 static void intel_gpu_idle_timer(unsigned long arg)
3457 {
3458         struct drm_device *dev = (struct drm_device *)arg;
3459         drm_i915_private_t *dev_priv = dev->dev_private;
3460
3461         DRM_DEBUG("idle timer fired, downclocking\n");
3462
3463         dev_priv->busy = false;
3464
3465         queue_work(dev_priv->wq, &dev_priv->idle_work);
3466 }
3467
3468 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3469 {
3470         drm_i915_private_t *dev_priv = dev->dev_private;
3471
3472         if (IS_IGDNG(dev))
3473                 return;
3474
3475         if (!dev_priv->render_reclock_avail) {
3476                 DRM_DEBUG("not reclocking render clock\n");
3477                 return;
3478         }
3479
3480         /* Restore render clock frequency to original value */
3481         if (IS_G4X(dev) || IS_I9XX(dev))
3482                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3483         else if (IS_I85X(dev))
3484                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3485         DRM_DEBUG("increasing render clock frequency\n");
3486
3487         /* Schedule downclock */
3488         if (schedule)
3489                 mod_timer(&dev_priv->idle_timer, jiffies +
3490                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3491 }
3492
3493 void intel_decrease_renderclock(struct drm_device *dev)
3494 {
3495         drm_i915_private_t *dev_priv = dev->dev_private;
3496
3497         if (IS_IGDNG(dev))
3498                 return;
3499
3500         if (!dev_priv->render_reclock_avail) {
3501                 DRM_DEBUG("not reclocking render clock\n");
3502                 return;
3503         }
3504
3505         if (IS_G4X(dev)) {
3506                 u16 gcfgc;
3507
3508                 /* Adjust render clock... */
3509                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3510
3511                 /* Down to minimum... */
3512                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3513                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3514
3515                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3516         } else if (IS_I965G(dev)) {
3517                 u16 gcfgc;
3518
3519                 /* Adjust render clock... */
3520                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3521
3522                 /* Down to minimum... */
3523                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3524                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3525
3526                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3527         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3528                 u16 gcfgc;
3529
3530                 /* Adjust render clock... */
3531                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3532
3533                 /* Down to minimum... */
3534                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3535                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3536
3537                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3538         } else if (IS_I915G(dev)) {
3539                 u16 gcfgc;
3540
3541                 /* Adjust render clock... */
3542                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3543
3544                 /* Down to minimum... */
3545                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3546                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3547
3548                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3549         } else if (IS_I85X(dev)) {
3550                 u16 hpllcc;
3551
3552                 /* Adjust render clock... */
3553                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3554
3555                 /* Up to maximum... */
3556                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3557                 hpllcc |= GC_CLOCK_133_200;
3558
3559                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3560         }
3561         DRM_DEBUG("decreasing render clock frequency\n");
3562 }
3563
3564 /* Note that no increase function is needed for this - increase_renderclock()
3565  *  will also rewrite these bits
3566  */
3567 void intel_decrease_displayclock(struct drm_device *dev)
3568 {
3569         if (IS_IGDNG(dev))
3570                 return;
3571
3572         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3573             IS_I915GM(dev)) {
3574                 u16 gcfgc;
3575
3576                 /* Adjust render clock... */
3577                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3578
3579                 /* Down to minimum... */
3580                 gcfgc &= ~0xf0;
3581                 gcfgc |= 0x80;
3582
3583                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3584         }
3585 }
3586
3587 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3588
3589 static void intel_crtc_idle_timer(unsigned long arg)
3590 {
3591         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3592         struct drm_crtc *crtc = &intel_crtc->base;
3593         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3594
3595         DRM_DEBUG("idle timer fired, downclocking\n");
3596
3597         intel_crtc->busy = false;
3598
3599         queue_work(dev_priv->wq, &dev_priv->idle_work);
3600 }
3601
3602 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3603 {
3604         struct drm_device *dev = crtc->dev;
3605         drm_i915_private_t *dev_priv = dev->dev_private;
3606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3607         int pipe = intel_crtc->pipe;
3608         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3609         int dpll = I915_READ(dpll_reg);
3610
3611         if (IS_IGDNG(dev))
3612                 return;
3613
3614         if (!dev_priv->lvds_downclock_avail)
3615                 return;
3616
3617         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3618                 DRM_DEBUG("upclocking LVDS\n");
3619
3620                 /* Unlock panel regs */
3621                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3622
3623                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3624                 I915_WRITE(dpll_reg, dpll);
3625                 dpll = I915_READ(dpll_reg);
3626                 intel_wait_for_vblank(dev);
3627                 dpll = I915_READ(dpll_reg);
3628                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3629                         DRM_DEBUG("failed to upclock LVDS!\n");
3630
3631                 /* ...and lock them again */
3632                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3633         }
3634
3635         /* Schedule downclock */
3636         if (schedule)
3637                 mod_timer(&intel_crtc->idle_timer, jiffies +
3638                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3639 }
3640
3641 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3642 {
3643         struct drm_device *dev = crtc->dev;
3644         drm_i915_private_t *dev_priv = dev->dev_private;
3645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646         int pipe = intel_crtc->pipe;
3647         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3648         int dpll = I915_READ(dpll_reg);
3649
3650         if (IS_IGDNG(dev))
3651                 return;
3652
3653         if (!dev_priv->lvds_downclock_avail)
3654                 return;
3655
3656         /*
3657          * Since this is called by a timer, we should never get here in
3658          * the manual case.
3659          */
3660         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3661                 DRM_DEBUG("downclocking LVDS\n");
3662
3663                 /* Unlock panel regs */
3664                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3665
3666                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3667                 I915_WRITE(dpll_reg, dpll);
3668                 dpll = I915_READ(dpll_reg);
3669                 intel_wait_for_vblank(dev);
3670                 dpll = I915_READ(dpll_reg);
3671                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3672                         DRM_DEBUG("failed to downclock LVDS!\n");
3673
3674                 /* ...and lock them again */
3675                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3676         }
3677
3678 }
3679
3680 /**
3681  * intel_idle_update - adjust clocks for idleness
3682  * @work: work struct
3683  *
3684  * Either the GPU or display (or both) went idle.  Check the busy status
3685  * here and adjust the CRTC and GPU clocks as necessary.
3686  */
3687 static void intel_idle_update(struct work_struct *work)
3688 {
3689         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3690                                                     idle_work);
3691         struct drm_device *dev = dev_priv->dev;
3692         struct drm_crtc *crtc;
3693         struct intel_crtc *intel_crtc;
3694
3695         if (!i915_powersave)
3696                 return;
3697
3698         mutex_lock(&dev->struct_mutex);
3699
3700         /* GPU isn't processing, downclock it. */
3701         if (!dev_priv->busy) {
3702                 intel_decrease_renderclock(dev);
3703                 intel_decrease_displayclock(dev);
3704         }
3705
3706         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3707                 /* Skip inactive CRTCs */
3708                 if (!crtc->fb)
3709                         continue;
3710
3711                 intel_crtc = to_intel_crtc(crtc);
3712                 if (!intel_crtc->busy)
3713                         intel_decrease_pllclock(crtc);
3714         }
3715
3716         mutex_unlock(&dev->struct_mutex);
3717 }
3718
3719 /**
3720  * intel_mark_busy - mark the GPU and possibly the display busy
3721  * @dev: drm device
3722  * @obj: object we're operating on
3723  *
3724  * Callers can use this function to indicate that the GPU is busy processing
3725  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3726  * buffer), we'll also mark the display as busy, so we know to increase its
3727  * clock frequency.
3728  */
3729 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3730 {
3731         drm_i915_private_t *dev_priv = dev->dev_private;
3732         struct drm_crtc *crtc = NULL;
3733         struct intel_framebuffer *intel_fb;
3734         struct intel_crtc *intel_crtc;
3735
3736         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3737                 return;
3738
3739         dev_priv->busy = true;
3740         intel_increase_renderclock(dev, true);
3741
3742         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3743                 if (!crtc->fb)
3744                         continue;
3745
3746                 intel_crtc = to_intel_crtc(crtc);
3747                 intel_fb = to_intel_framebuffer(crtc->fb);
3748                 if (intel_fb->obj == obj) {
3749                         if (!intel_crtc->busy) {
3750                                 /* Non-busy -> busy, upclock */
3751                                 intel_increase_pllclock(crtc, true);
3752                                 intel_crtc->busy = true;
3753                         } else {
3754                                 /* Busy -> busy, put off timer */
3755                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3756                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3757                         }
3758                 }
3759         }
3760 }
3761
3762 static void intel_crtc_destroy(struct drm_crtc *crtc)
3763 {
3764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3765
3766         drm_crtc_cleanup(crtc);
3767         kfree(intel_crtc);
3768 }
3769
3770 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3771         .dpms = intel_crtc_dpms,
3772         .mode_fixup = intel_crtc_mode_fixup,
3773         .mode_set = intel_crtc_mode_set,
3774         .mode_set_base = intel_pipe_set_base,
3775         .prepare = intel_crtc_prepare,
3776         .commit = intel_crtc_commit,
3777 };
3778
3779 static const struct drm_crtc_funcs intel_crtc_funcs = {
3780         .cursor_set = intel_crtc_cursor_set,
3781         .cursor_move = intel_crtc_cursor_move,
3782         .gamma_set = intel_crtc_gamma_set,
3783         .set_config = drm_crtc_helper_set_config,
3784         .destroy = intel_crtc_destroy,
3785 };
3786
3787
3788 static void intel_crtc_init(struct drm_device *dev, int pipe)
3789 {
3790         struct intel_crtc *intel_crtc;
3791         int i;
3792
3793         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3794         if (intel_crtc == NULL)
3795                 return;
3796
3797         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
3798
3799         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
3800         intel_crtc->pipe = pipe;
3801         intel_crtc->plane = pipe;
3802         for (i = 0; i < 256; i++) {
3803                 intel_crtc->lut_r[i] = i;
3804                 intel_crtc->lut_g[i] = i;
3805                 intel_crtc->lut_b[i] = i;
3806         }
3807
3808         /* Swap pipes & planes for FBC on pre-965 */
3809         intel_crtc->pipe = pipe;
3810         intel_crtc->plane = pipe;
3811         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
3812                 DRM_DEBUG("swapping pipes & planes for FBC\n");
3813                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
3814         }
3815
3816         intel_crtc->cursor_addr = 0;
3817         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
3818         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
3819
3820         intel_crtc->busy = false;
3821
3822         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
3823                     (unsigned long)intel_crtc);
3824 }
3825
3826 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
3827                                 struct drm_file *file_priv)
3828 {
3829         drm_i915_private_t *dev_priv = dev->dev_private;
3830         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
3831         struct drm_mode_object *drmmode_obj;
3832         struct intel_crtc *crtc;
3833
3834         if (!dev_priv) {
3835                 DRM_ERROR("called with no initialization\n");
3836                 return -EINVAL;
3837         }
3838
3839         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
3840                         DRM_MODE_OBJECT_CRTC);
3841
3842         if (!drmmode_obj) {
3843                 DRM_ERROR("no such CRTC id\n");
3844                 return -EINVAL;
3845         }
3846
3847         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
3848         pipe_from_crtc_id->pipe = crtc->pipe;
3849
3850         return 0;
3851 }
3852
3853 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
3854 {
3855         struct drm_crtc *crtc = NULL;
3856
3857         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3858                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3859                 if (intel_crtc->pipe == pipe)
3860                         break;
3861         }
3862         return crtc;
3863 }
3864
3865 static int intel_connector_clones(struct drm_device *dev, int type_mask)
3866 {
3867         int index_mask = 0;
3868         struct drm_connector *connector;
3869         int entry = 0;
3870
3871         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3872                 struct intel_output *intel_output = to_intel_output(connector);
3873                 if (type_mask & intel_output->clone_mask)
3874                         index_mask |= (1 << entry);
3875                 entry++;
3876         }
3877         return index_mask;
3878 }
3879
3880
3881 static void intel_setup_outputs(struct drm_device *dev)
3882 {
3883         struct drm_i915_private *dev_priv = dev->dev_private;
3884         struct drm_connector *connector;
3885
3886         intel_crt_init(dev);
3887
3888         /* Set up integrated LVDS */
3889         if (IS_MOBILE(dev) && !IS_I830(dev))
3890                 intel_lvds_init(dev);
3891
3892         if (IS_IGDNG(dev)) {
3893                 int found;
3894
3895                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
3896                         intel_dp_init(dev, DP_A);
3897
3898                 if (I915_READ(HDMIB) & PORT_DETECTED) {
3899                         /* check SDVOB */
3900                         /* found = intel_sdvo_init(dev, HDMIB); */
3901                         found = 0;
3902                         if (!found)
3903                                 intel_hdmi_init(dev, HDMIB);
3904                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3905                                 intel_dp_init(dev, PCH_DP_B);
3906                 }
3907
3908                 if (I915_READ(HDMIC) & PORT_DETECTED)
3909                         intel_hdmi_init(dev, HDMIC);
3910
3911                 if (I915_READ(HDMID) & PORT_DETECTED)
3912                         intel_hdmi_init(dev, HDMID);
3913
3914                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
3915                         intel_dp_init(dev, PCH_DP_C);
3916
3917                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
3918                         intel_dp_init(dev, PCH_DP_D);
3919
3920         } else if (IS_I9XX(dev)) {
3921                 bool found = false;
3922
3923                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3924                         found = intel_sdvo_init(dev, SDVOB);
3925                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3926                                 intel_hdmi_init(dev, SDVOB);
3927
3928                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
3929                                 intel_dp_init(dev, DP_B);
3930                 }
3931
3932                 /* Before G4X SDVOC doesn't have its own detect register */
3933
3934                 if (I915_READ(SDVOB) & SDVO_DETECTED)
3935                         found = intel_sdvo_init(dev, SDVOC);
3936
3937                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
3938
3939                         if (SUPPORTS_INTEGRATED_HDMI(dev))
3940                                 intel_hdmi_init(dev, SDVOC);
3941                         if (SUPPORTS_INTEGRATED_DP(dev))
3942                                 intel_dp_init(dev, DP_C);
3943                 }
3944
3945                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3946                         intel_dp_init(dev, DP_D);
3947         } else
3948                 intel_dvo_init(dev);
3949
3950         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
3951                 intel_tv_init(dev);
3952
3953         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3954                 struct intel_output *intel_output = to_intel_output(connector);
3955                 struct drm_encoder *encoder = &intel_output->enc;
3956
3957                 encoder->possible_crtcs = intel_output->crtc_mask;
3958                 encoder->possible_clones = intel_connector_clones(dev,
3959                                                 intel_output->clone_mask);
3960         }
3961 }
3962
3963 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3964 {
3965         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3966         struct drm_device *dev = fb->dev;
3967
3968         if (fb->fbdev)
3969                 intelfb_remove(dev, fb);
3970
3971         drm_framebuffer_cleanup(fb);
3972         mutex_lock(&dev->struct_mutex);
3973         drm_gem_object_unreference(intel_fb->obj);
3974         mutex_unlock(&dev->struct_mutex);
3975
3976         kfree(intel_fb);
3977 }
3978
3979 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3980                                                 struct drm_file *file_priv,
3981                                                 unsigned int *handle)
3982 {
3983         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3984         struct drm_gem_object *object = intel_fb->obj;
3985
3986         return drm_gem_handle_create(file_priv, object, handle);
3987 }
3988
3989 static const struct drm_framebuffer_funcs intel_fb_funcs = {
3990         .destroy = intel_user_framebuffer_destroy,
3991         .create_handle = intel_user_framebuffer_create_handle,
3992 };
3993
3994 int intel_framebuffer_create(struct drm_device *dev,
3995                              struct drm_mode_fb_cmd *mode_cmd,
3996                              struct drm_framebuffer **fb,
3997                              struct drm_gem_object *obj)
3998 {
3999         struct intel_framebuffer *intel_fb;
4000         int ret;
4001
4002         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4003         if (!intel_fb)
4004                 return -ENOMEM;
4005
4006         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4007         if (ret) {
4008                 DRM_ERROR("framebuffer init failed %d\n", ret);
4009                 return ret;
4010         }
4011
4012         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4013
4014         intel_fb->obj = obj;
4015
4016         *fb = &intel_fb->base;
4017
4018         return 0;
4019 }
4020
4021
4022 static struct drm_framebuffer *
4023 intel_user_framebuffer_create(struct drm_device *dev,
4024                               struct drm_file *filp,
4025                               struct drm_mode_fb_cmd *mode_cmd)
4026 {
4027         struct drm_gem_object *obj;
4028         struct drm_framebuffer *fb;
4029         int ret;
4030
4031         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4032         if (!obj)
4033                 return NULL;
4034
4035         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4036         if (ret) {
4037                 mutex_lock(&dev->struct_mutex);
4038                 drm_gem_object_unreference(obj);
4039                 mutex_unlock(&dev->struct_mutex);
4040                 return NULL;
4041         }
4042
4043         return fb;
4044 }
4045
4046 static const struct drm_mode_config_funcs intel_mode_funcs = {
4047         .fb_create = intel_user_framebuffer_create,
4048         .fb_changed = intelfb_probe,
4049 };
4050
4051 void intel_init_clock_gating(struct drm_device *dev)
4052 {
4053         struct drm_i915_private *dev_priv = dev->dev_private;
4054
4055         /*
4056          * Disable clock gating reported to work incorrectly according to the
4057          * specs, but enable as much else as we can.
4058          */
4059         if (IS_G4X(dev)) {
4060                 uint32_t dspclk_gate;
4061                 I915_WRITE(RENCLK_GATE_D1, 0);
4062                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4063                        GS_UNIT_CLOCK_GATE_DISABLE |
4064                        CL_UNIT_CLOCK_GATE_DISABLE);
4065                 I915_WRITE(RAMCLK_GATE_D, 0);
4066                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4067                         OVRUNIT_CLOCK_GATE_DISABLE |
4068                         OVCUNIT_CLOCK_GATE_DISABLE;
4069                 if (IS_GM45(dev))
4070                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4071                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4072         } else if (IS_I965GM(dev)) {
4073                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4074                 I915_WRITE(RENCLK_GATE_D2, 0);
4075                 I915_WRITE(DSPCLK_GATE_D, 0);
4076                 I915_WRITE(RAMCLK_GATE_D, 0);
4077                 I915_WRITE16(DEUC, 0);
4078         } else if (IS_I965G(dev)) {
4079                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4080                        I965_RCC_CLOCK_GATE_DISABLE |
4081                        I965_RCPB_CLOCK_GATE_DISABLE |
4082                        I965_ISC_CLOCK_GATE_DISABLE |
4083                        I965_FBC_CLOCK_GATE_DISABLE);
4084                 I915_WRITE(RENCLK_GATE_D2, 0);
4085         } else if (IS_I9XX(dev)) {
4086                 u32 dstate = I915_READ(D_STATE);
4087
4088                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4089                         DSTATE_DOT_CLOCK_GATING;
4090                 I915_WRITE(D_STATE, dstate);
4091         } else if (IS_I855(dev) || IS_I865G(dev)) {
4092                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4093         } else if (IS_I830(dev)) {
4094                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4095         }
4096 }
4097
4098 /* Set up chip specific display functions */
4099 static void intel_init_display(struct drm_device *dev)
4100 {
4101         struct drm_i915_private *dev_priv = dev->dev_private;
4102
4103         /* We always want a DPMS function */
4104         if (IS_IGDNG(dev))
4105                 dev_priv->display.dpms = igdng_crtc_dpms;
4106         else
4107                 dev_priv->display.dpms = i9xx_crtc_dpms;
4108
4109         /* Only mobile has FBC, leave pointers NULL for other chips */
4110         if (IS_MOBILE(dev)) {
4111                 /* 855GM needs testing */
4112                 if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4113                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4114                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4115                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4116                 }
4117         }
4118
4119         /* Returns the core display clock speed */
4120         if (IS_I945G(dev))
4121                 dev_priv->display.get_display_clock_speed =
4122                         i945_get_display_clock_speed;
4123         else if (IS_I915G(dev))
4124                 dev_priv->display.get_display_clock_speed =
4125                         i915_get_display_clock_speed;
4126         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4127                 dev_priv->display.get_display_clock_speed =
4128                         i9xx_misc_get_display_clock_speed;
4129         else if (IS_I915GM(dev))
4130                 dev_priv->display.get_display_clock_speed =
4131                         i915gm_get_display_clock_speed;
4132         else if (IS_I865G(dev))
4133                 dev_priv->display.get_display_clock_speed =
4134                         i865_get_display_clock_speed;
4135         else if (IS_I855(dev))
4136                 dev_priv->display.get_display_clock_speed =
4137                         i855_get_display_clock_speed;
4138         else /* 852, 830 */
4139                 dev_priv->display.get_display_clock_speed =
4140                         i830_get_display_clock_speed;
4141
4142         /* For FIFO watermark updates */
4143         if (IS_G4X(dev))
4144                 dev_priv->display.update_wm = g4x_update_wm;
4145         else if (IS_I965G(dev))
4146                 dev_priv->display.update_wm = i965_update_wm;
4147         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4148                 dev_priv->display.update_wm = i9xx_update_wm;
4149                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4150         } else {
4151                 if (IS_I85X(dev))
4152                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4153                 else if (IS_845G(dev))
4154                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4155                 else
4156                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4157                 dev_priv->display.update_wm = i830_update_wm;
4158         }
4159 }
4160
4161 void intel_modeset_init(struct drm_device *dev)
4162 {
4163         struct drm_i915_private *dev_priv = dev->dev_private;
4164         int num_pipe;
4165         int i;
4166
4167         drm_mode_config_init(dev);
4168
4169         dev->mode_config.min_width = 0;
4170         dev->mode_config.min_height = 0;
4171
4172         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4173
4174         intel_init_display(dev);
4175
4176         if (IS_I965G(dev)) {
4177                 dev->mode_config.max_width = 8192;
4178                 dev->mode_config.max_height = 8192;
4179         } else if (IS_I9XX(dev)) {
4180                 dev->mode_config.max_width = 4096;
4181                 dev->mode_config.max_height = 4096;
4182         } else {
4183                 dev->mode_config.max_width = 2048;
4184                 dev->mode_config.max_height = 2048;
4185         }
4186
4187         /* set memory base */
4188         if (IS_I9XX(dev))
4189                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4190         else
4191                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4192
4193         if (IS_MOBILE(dev) || IS_I9XX(dev))
4194                 num_pipe = 2;
4195         else
4196                 num_pipe = 1;
4197         DRM_DEBUG("%d display pipe%s available.\n",
4198                   num_pipe, num_pipe > 1 ? "s" : "");
4199
4200         if (IS_I85X(dev))
4201                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4202         else if (IS_I9XX(dev) || IS_G4X(dev))
4203                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4204
4205         for (i = 0; i < num_pipe; i++) {
4206                 intel_crtc_init(dev, i);
4207         }
4208
4209         intel_setup_outputs(dev);
4210
4211         intel_init_clock_gating(dev);
4212
4213         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4214         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4215                     (unsigned long)dev);
4216 }
4217
4218 void intel_modeset_cleanup(struct drm_device *dev)
4219 {
4220         struct drm_i915_private *dev_priv = dev->dev_private;
4221         struct drm_crtc *crtc;
4222         struct intel_crtc *intel_crtc;
4223
4224         mutex_lock(&dev->struct_mutex);
4225
4226         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4227                 /* Skip inactive CRTCs */
4228                 if (!crtc->fb)
4229                         continue;
4230
4231                 intel_crtc = to_intel_crtc(crtc);
4232                 intel_increase_pllclock(crtc, false);
4233                 del_timer_sync(&intel_crtc->idle_timer);
4234         }
4235
4236         intel_increase_renderclock(dev, false);
4237         del_timer_sync(&dev_priv->idle_timer);
4238
4239         mutex_unlock(&dev->struct_mutex);
4240
4241         if (dev_priv->display.disable_fbc)
4242                 dev_priv->display.disable_fbc(dev);
4243
4244         drm_mode_config_cleanup(dev);
4245 }
4246
4247
4248 /* current intel driver doesn't take advantage of encoders
4249    always give back the encoder for the connector
4250 */
4251 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4252 {
4253         struct intel_output *intel_output = to_intel_output(connector);
4254
4255         return &intel_output->enc;
4256 }