drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include "drmP.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "drm_dp_helper.h"
  38
  39 #include "drm_crtc_helper.h"
  40
  41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  42
  43 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  44 static void intel_update_watermarks(struct drm_device *dev);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  46
  47 typedef struct {
  48     /* given values */
  49     int n;
  50     int m1, m2;
  51     int p1, p2;
  52     /* derived values */
  53     int dot;
  54     int vco;
  55     int m;
  56     int p;
  57 } intel_clock_t;
  58
  59 typedef struct {
  60     int min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64     int dot_limit;
  65     int p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 #define INTEL_P2_NUM                  2
  69 typedef struct intel_limit intel_limit_t;
  70 struct intel_limit {
  71     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  72     intel_p2_t      p2;
  73     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  74                       int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define PINEVIEW_VCO_MIN                1700000
 106 #define PINEVIEW_VCO_MAX                3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* Pineview's Ncounter is a ring counter */
 110 #define PINEVIEW_N_MIN                3
 111 #define PINEVIEW_N_MAX                6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define PINEVIEW_M_MIN                2
 115 #define PINEVIEW_M_MAX              256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* Pineview M1 is reserved, and must be 0 */
 121 #define PINEVIEW_M1_MIN               0
 122 #define PINEVIEW_M1_MAX               0
 123 #define PINEVIEW_M2_MIN               0
 124 #define PINEVIEW_M2_MAX               254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define PINEVIEW_P_LVDS_MIN                   7
 130 #define PINEVIEW_P_LVDS_MAX                  112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* Ironlake / Sandybridge */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IRONLAKE_DOT_MIN         25000
 242 #define IRONLAKE_DOT_MAX         350000
 243 #define IRONLAKE_VCO_MIN         1760000
 244 #define IRONLAKE_VCO_MAX         3510000
 245 #define IRONLAKE_M1_MIN          12
 246 #define IRONLAKE_M1_MAX          22
 247 #define IRONLAKE_M2_MIN          5
 248 #define IRONLAKE_M2_MAX          9
 249 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 250
 251 /* We have parameter ranges for different type of outputs. */
 252
 253 /* DAC & HDMI Refclk 120Mhz */
 254 #define IRONLAKE_DAC_N_MIN      1
 255 #define IRONLAKE_DAC_N_MAX      5
 256 #define IRONLAKE_DAC_M_MIN      79
 257 #define IRONLAKE_DAC_M_MAX      127
 258 #define IRONLAKE_DAC_P_MIN      5
 259 #define IRONLAKE_DAC_P_MAX      80
 260 #define IRONLAKE_DAC_P1_MIN     1
 261 #define IRONLAKE_DAC_P1_MAX     8
 262 #define IRONLAKE_DAC_P2_SLOW    10
 263 #define IRONLAKE_DAC_P2_FAST    5
 264
 265 /* LVDS single-channel 120Mhz refclk */
 266 #define IRONLAKE_LVDS_S_N_MIN   1
 267 #define IRONLAKE_LVDS_S_N_MAX   3
 268 #define IRONLAKE_LVDS_S_M_MIN   79
 269 #define IRONLAKE_LVDS_S_M_MAX   118
 270 #define IRONLAKE_LVDS_S_P_MIN   28
 271 #define IRONLAKE_LVDS_S_P_MAX   112
 272 #define IRONLAKE_LVDS_S_P1_MIN  2
 273 #define IRONLAKE_LVDS_S_P1_MAX  8
 274 #define IRONLAKE_LVDS_S_P2_SLOW 14
 275 #define IRONLAKE_LVDS_S_P2_FAST 14
 276
 277 /* LVDS dual-channel 120Mhz refclk */
 278 #define IRONLAKE_LVDS_D_N_MIN   1
 279 #define IRONLAKE_LVDS_D_N_MAX   3
 280 #define IRONLAKE_LVDS_D_M_MIN   79
 281 #define IRONLAKE_LVDS_D_M_MAX   127
 282 #define IRONLAKE_LVDS_D_P_MIN   14
 283 #define IRONLAKE_LVDS_D_P_MAX   56
 284 #define IRONLAKE_LVDS_D_P1_MIN  2
 285 #define IRONLAKE_LVDS_D_P1_MAX  8
 286 #define IRONLAKE_LVDS_D_P2_SLOW 7
 287 #define IRONLAKE_LVDS_D_P2_FAST 7
 288
 289 /* LVDS single-channel 100Mhz refclk */
 290 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 291 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 292 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 293 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 294 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 295 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 296 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 297 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 298 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 299 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 300
 301 /* LVDS dual-channel 100Mhz refclk */
 302 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 303 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 304 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 305 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 306 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 307 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 308 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 309 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 310 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 311 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 312
 313 /* DisplayPort */
 314 #define IRONLAKE_DP_N_MIN               1
 315 #define IRONLAKE_DP_N_MAX               2
 316 #define IRONLAKE_DP_M_MIN               81
 317 #define IRONLAKE_DP_M_MAX               90
 318 #define IRONLAKE_DP_P_MIN               10
 319 #define IRONLAKE_DP_P_MAX               20
 320 #define IRONLAKE_DP_P2_FAST             10
 321 #define IRONLAKE_DP_P2_SLOW             10
 322 #define IRONLAKE_DP_P2_LIMIT            0
 323 #define IRONLAKE_DP_P1_MIN              1
 324 #define IRONLAKE_DP_P1_MAX              2
 325
 326 /* FDI */
 327 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 328
 329 static bool
 330 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 331                     int target, int refclk, intel_clock_t *best_clock);
 332 static bool
 333 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 334                         int target, int refclk, intel_clock_t *best_clock);
 335
 336 static bool
 337 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 338                       int target, int refclk, intel_clock_t *best_clock);
 339 static bool
 340 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 341                            int target, int refclk, intel_clock_t *best_clock);
 342
 343 static const intel_limit_t intel_limits_i8xx_dvo = {
 344         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 345         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 346         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 347         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 348         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 349         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 350         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 351         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 352         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 353                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 354         .find_pll = intel_find_best_PLL,
 355 };
 356
 357 static const intel_limit_t intel_limits_i8xx_lvds = {
 358         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 359         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 360         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 361         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 362         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 363         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 364         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 365         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 366         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 367                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 368         .find_pll = intel_find_best_PLL,
 369 };
 370
 371 static const intel_limit_t intel_limits_i9xx_sdvo = {
 372         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 373         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 374         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 375         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 376         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 377         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 378         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 379         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 380         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 381                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 382         .find_pll = intel_find_best_PLL,
 383 };
 384
 385 static const intel_limit_t intel_limits_i9xx_lvds = {
 386         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 387         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 388         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 389         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 390         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 391         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 392         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 393         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 394         /* The single-channel range is 25-112Mhz, and dual-channel
 395          * is 80-224Mhz.  Prefer single channel as much as possible.
 396          */
 397         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 398                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 399         .find_pll = intel_find_best_PLL,
 400 };
 401
 402     /* below parameter and function is for G4X Chipset Family*/
 403 static const intel_limit_t intel_limits_g4x_sdvo = {
 404         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 405         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 406         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 407         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 408         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 409         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 410         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 411         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 412         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 413                  .p2_slow = G4X_P2_SDVO_SLOW,
 414                  .p2_fast = G4X_P2_SDVO_FAST
 415         },
 416         .find_pll = intel_g4x_find_best_PLL,
 417 };
 418
 419 static const intel_limit_t intel_limits_g4x_hdmi = {
 420         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 421         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 422         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 423         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 424         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 425         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 426         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 427         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 428         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 429                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 430                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 431         },
 432         .find_pll = intel_g4x_find_best_PLL,
 433 };
 434
 435 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 436         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 437                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 438         .vco = { .min = G4X_VCO_MIN,
 439                  .max = G4X_VCO_MAX },
 440         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 441                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 442         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 444         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 446         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 448         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 450         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 451                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 452         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 453                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 454                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 455         },
 456         .find_pll = intel_g4x_find_best_PLL,
 457 };
 458
 459 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 460         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 461                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 462         .vco = { .min = G4X_VCO_MIN,
 463                  .max = G4X_VCO_MAX },
 464         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 465                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 466         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 468         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 470         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 472         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 474         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 475                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 476         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 477                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 478                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 479         },
 480         .find_pll = intel_g4x_find_best_PLL,
 481 };
 482
 483 static const intel_limit_t intel_limits_g4x_display_port = {
 484         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 485                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 486         .vco = { .min = G4X_VCO_MIN,
 487                  .max = G4X_VCO_MAX},
 488         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 489                  .max = G4X_N_DISPLAY_PORT_MAX },
 490         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 491                  .max = G4X_M_DISPLAY_PORT_MAX },
 492         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 493                  .max = G4X_M1_DISPLAY_PORT_MAX },
 494         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 495                  .max = G4X_M2_DISPLAY_PORT_MAX },
 496         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 497                  .max = G4X_P_DISPLAY_PORT_MAX },
 498         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 499                  .max = G4X_P1_DISPLAY_PORT_MAX},
 500         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 501                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 502                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 503         .find_pll = intel_find_pll_g4x_dp,
 504 };
 505
 506 static const intel_limit_t intel_limits_pineview_sdvo = {
 507         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 508         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 509         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 510         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 511         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 512         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 513         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 514         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 515         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 516                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 517         .find_pll = intel_find_best_PLL,
 518 };
 519
 520 static const intel_limit_t intel_limits_pineview_lvds = {
 521         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 522         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 523         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 524         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 525         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 526         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 527         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 528         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 529         /* Pineview only supports single-channel mode. */
 530         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 531                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 532         .find_pll = intel_find_best_PLL,
 533 };
 534
 535 static const intel_limit_t intel_limits_ironlake_dac = {
 536         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 537         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 538         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 539         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 540         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 541         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 542         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 543         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 544         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 545                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 546                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 547         .find_pll = intel_g4x_find_best_PLL,
 548 };
 549
 550 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 551         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 552         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 553         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 554         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 555         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 556         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 557         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 558         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 559         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 560                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 561                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 562         .find_pll = intel_g4x_find_best_PLL,
 563 };
 564
 565 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 566         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 567         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 568         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 569         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 570         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 571         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 572         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 573         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 574         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 575                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 576                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 577         .find_pll = intel_g4x_find_best_PLL,
 578 };
 579
 580 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 581         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 582         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 583         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 584         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 585         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 586         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 587         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 588         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 589         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 590                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 591                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 592         .find_pll = intel_g4x_find_best_PLL,
 593 };
 594
 595 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 596         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 597         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 598         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 599         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 600         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 601         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 602         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 603         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 604         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 605                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 606                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 607         .find_pll = intel_g4x_find_best_PLL,
 608 };
 609
 610 static const intel_limit_t intel_limits_ironlake_display_port = {
 611         .dot = { .min = IRONLAKE_DOT_MIN,
 612                  .max = IRONLAKE_DOT_MAX },
 613         .vco = { .min = IRONLAKE_VCO_MIN,
 614                  .max = IRONLAKE_VCO_MAX},
 615         .n   = { .min = IRONLAKE_DP_N_MIN,
 616                  .max = IRONLAKE_DP_N_MAX },
 617         .m   = { .min = IRONLAKE_DP_M_MIN,
 618                  .max = IRONLAKE_DP_M_MAX },
 619         .m1  = { .min = IRONLAKE_M1_MIN,
 620                  .max = IRONLAKE_M1_MAX },
 621         .m2  = { .min = IRONLAKE_M2_MIN,
 622                  .max = IRONLAKE_M2_MAX },
 623         .p   = { .min = IRONLAKE_DP_P_MIN,
 624                  .max = IRONLAKE_DP_P_MAX },
 625         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 626                  .max = IRONLAKE_DP_P1_MAX},
 627         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 628                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 629                  .p2_fast = IRONLAKE_DP_P2_FAST },
 630         .find_pll = intel_find_pll_ironlake_dp,
 631 };
 632
 633 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 634 {
 635         struct drm_device *dev = crtc->dev;
 636         struct drm_i915_private *dev_priv = dev->dev_private;
 637         const intel_limit_t *limit;
 638         int refclk = 120;
 639
 640         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 641                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 642                         refclk = 100;
 643
 644                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 645                     LVDS_CLKB_POWER_UP) {
 646                         /* LVDS dual channel */
 647                         if (refclk == 100)
 648                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 649                         else
 650                                 limit = &intel_limits_ironlake_dual_lvds;
 651                 } else {
 652                         if (refclk == 100)
 653                                 limit = &intel_limits_ironlake_single_lvds_100m;
 654                         else
 655                                 limit = &intel_limits_ironlake_single_lvds;
 656                 }
 657         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 658                         HAS_eDP)
 659                 limit = &intel_limits_ironlake_display_port;
 660         else
 661                 limit = &intel_limits_ironlake_dac;
 662
 663         return limit;
 664 }
 665
 666 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 667 {
 668         struct drm_device *dev = crtc->dev;
 669         struct drm_i915_private *dev_priv = dev->dev_private;
 670         const intel_limit_t *limit;
 671
 672         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 673                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 674                     LVDS_CLKB_POWER_UP)
 675                         /* LVDS with dual channel */
 676                         limit = &intel_limits_g4x_dual_channel_lvds;
 677                 else
 678                         /* LVDS with dual channel */
 679                         limit = &intel_limits_g4x_single_channel_lvds;
 680         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 681                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 682                 limit = &intel_limits_g4x_hdmi;
 683         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 684                 limit = &intel_limits_g4x_sdvo;
 685         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 686                 limit = &intel_limits_g4x_display_port;
 687         } else /* The option is for other outputs */
 688                 limit = &intel_limits_i9xx_sdvo;
 689
 690         return limit;
 691 }
 692
 693 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 694 {
 695         struct drm_device *dev = crtc->dev;
 696         const intel_limit_t *limit;
 697
 698         if (HAS_PCH_SPLIT(dev))
 699                 limit = intel_ironlake_limit(crtc);
 700         else if (IS_G4X(dev)) {
 701                 limit = intel_g4x_limit(crtc);
 702         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 703                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 704                         limit = &intel_limits_i9xx_lvds;
 705                 else
 706                         limit = &intel_limits_i9xx_sdvo;
 707         } else if (IS_PINEVIEW(dev)) {
 708                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 709                         limit = &intel_limits_pineview_lvds;
 710                 else
 711                         limit = &intel_limits_pineview_sdvo;
 712         } else {
 713                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 714                         limit = &intel_limits_i8xx_lvds;
 715                 else
 716                         limit = &intel_limits_i8xx_dvo;
 717         }
 718         return limit;
 719 }
 720
 721 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 722 static void pineview_clock(int refclk, intel_clock_t *clock)
 723 {
 724         clock->m = clock->m2 + 2;
 725         clock->p = clock->p1 * clock->p2;
 726         clock->vco = refclk * clock->m / clock->n;
 727         clock->dot = clock->vco / clock->p;
 728 }
 729
 730 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 731 {
 732         if (IS_PINEVIEW(dev)) {
 733                 pineview_clock(refclk, clock);
 734                 return;
 735         }
 736         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 737         clock->p = clock->p1 * clock->p2;
 738         clock->vco = refclk * clock->m / (clock->n + 2);
 739         clock->dot = clock->vco / clock->p;
 740 }
 741
 742 /**
 743  * Returns whether any output on the specified pipe is of the specified type
 744  */
 745 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 746 {
 747     struct drm_device *dev = crtc->dev;
 748     struct drm_mode_config *mode_config = &dev->mode_config;
 749     struct drm_encoder *l_entry;
 750
 751     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 752             if (l_entry && l_entry->crtc == crtc) {
 753                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 754                     if (intel_encoder->type == type)
 755                             return true;
 756             }
 757     }
 758     return false;
 759 }
 760
 761 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 762 /**
 763  * Returns whether the given set of divisors are valid for a given refclk with
 764  * the given connectors.
 765  */
 766
 767 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 768 {
 769         const intel_limit_t *limit = intel_limit (crtc);
 770         struct drm_device *dev = crtc->dev;
 771
 772         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 773                 INTELPllInvalid ("p1 out of range\n");
 774         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 775                 INTELPllInvalid ("p out of range\n");
 776         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 777                 INTELPllInvalid ("m2 out of range\n");
 778         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 779                 INTELPllInvalid ("m1 out of range\n");
 780         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 781                 INTELPllInvalid ("m1 <= m2\n");
 782         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 783                 INTELPllInvalid ("m out of range\n");
 784         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 785                 INTELPllInvalid ("n out of range\n");
 786         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 787                 INTELPllInvalid ("vco out of range\n");
 788         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 789          * connector, etc., rather than just a single range.
 790          */
 791         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 792                 INTELPllInvalid ("dot out of range\n");
 793
 794         return true;
 795 }
 796
 797 static bool
 798 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 799                     int target, int refclk, intel_clock_t *best_clock)
 800
 801 {
 802         struct drm_device *dev = crtc->dev;
 803         struct drm_i915_private *dev_priv = dev->dev_private;
 804         intel_clock_t clock;
 805         int err = target;
 806
 807         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 808             (I915_READ(LVDS)) != 0) {
 809                 /*
 810                  * For LVDS, if the panel is on, just rely on its current
 811                  * settings for dual-channel.  We haven't figured out how to
 812                  * reliably set up different single/dual channel state, if we
 813                  * even can.
 814                  */
 815                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 816                     LVDS_CLKB_POWER_UP)
 817                         clock.p2 = limit->p2.p2_fast;
 818                 else
 819                         clock.p2 = limit->p2.p2_slow;
 820         } else {
 821                 if (target < limit->p2.dot_limit)
 822                         clock.p2 = limit->p2.p2_slow;
 823                 else
 824                         clock.p2 = limit->p2.p2_fast;
 825         }
 826
 827         memset (best_clock, 0, sizeof (*best_clock));
 828
 829         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 830              clock.m1++) {
 831                 for (clock.m2 = limit->m2.min;
 832                      clock.m2 <= limit->m2.max; clock.m2++) {
 833                         /* m1 is always 0 in Pineview */
 834                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 835                                 break;
 836                         for (clock.n = limit->n.min;
 837                              clock.n <= limit->n.max; clock.n++) {
 838                                 for (clock.p1 = limit->p1.min;
 839                                         clock.p1 <= limit->p1.max; clock.p1++) {
 840                                         int this_err;
 841
 842                                         intel_clock(dev, refclk, &clock);
 843
 844                                         if (!intel_PLL_is_valid(crtc, &clock))
 845                                                 continue;
 846
 847                                         this_err = abs(clock.dot - target);
 848                                         if (this_err < err) {
 849                                                 *best_clock = clock;
 850                                                 err = this_err;
 851                                         }
 852                                 }
 853                         }
 854                 }
 855         }
 856
 857         return (err != target);
 858 }
 859
 860 static bool
 861 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 862                         int target, int refclk, intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc->dev;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         intel_clock_t clock;
 867         int max_n;
 868         bool found;
 869         /* approximately equals target * 0.00488 */
 870         int err_most = (target >> 8) + (target >> 10);
 871         found = false;
 872
 873         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 874                 int lvds_reg;
 875
 876                 if (HAS_PCH_SPLIT(dev))
 877                         lvds_reg = PCH_LVDS;
 878                 else
 879                         lvds_reg = LVDS;
 880                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 881                     LVDS_CLKB_POWER_UP)
 882                         clock.p2 = limit->p2.p2_fast;
 883                 else
 884                         clock.p2 = limit->p2.p2_slow;
 885         } else {
 886                 if (target < limit->p2.dot_limit)
 887                         clock.p2 = limit->p2.p2_slow;
 888                 else
 889                         clock.p2 = limit->p2.p2_fast;
 890         }
 891
 892         memset(best_clock, 0, sizeof(*best_clock));
 893         max_n = limit->n.max;
 894         /* based on hardware requirement, prefer smaller n to precision */
 895         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 896                 /* based on hardware requirement, prefere larger m1,m2 */
 897                 for (clock.m1 = limit->m1.max;
 898                      clock.m1 >= limit->m1.min; clock.m1--) {
 899                         for (clock.m2 = limit->m2.max;
 900                              clock.m2 >= limit->m2.min; clock.m2--) {
 901                                 for (clock.p1 = limit->p1.max;
 902                                      clock.p1 >= limit->p1.min; clock.p1--) {
 903                                         int this_err;
 904
 905                                         intel_clock(dev, refclk, &clock);
 906                                         if (!intel_PLL_is_valid(crtc, &clock))
 907                                                 continue;
 908                                         this_err = abs(clock.dot - target) ;
 909                                         if (this_err < err_most) {
 910                                                 *best_clock = clock;
 911                                                 err_most = this_err;
 912                                                 max_n = clock.n;
 913                                                 found = true;
 914                                         }
 915                                 }
 916                         }
 917                 }
 918         }
 919         return found;
 920 }
 921
 922 static bool
 923 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 924                            int target, int refclk, intel_clock_t *best_clock)
 925 {
 926         struct drm_device *dev = crtc->dev;
 927         intel_clock_t clock;
 928
 929         /* return directly when it is eDP */
 930         if (HAS_eDP)
 931                 return true;
 932
 933         if (target < 200000) {
 934                 clock.n = 1;
 935                 clock.p1 = 2;
 936                 clock.p2 = 10;
 937                 clock.m1 = 12;
 938                 clock.m2 = 9;
 939         } else {
 940                 clock.n = 2;
 941                 clock.p1 = 1;
 942                 clock.p2 = 10;
 943                 clock.m1 = 14;
 944                 clock.m2 = 8;
 945         }
 946         intel_clock(dev, refclk, &clock);
 947         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 948         return true;
 949 }
 950
 951 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 952 static bool
 953 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 954                       int target, int refclk, intel_clock_t *best_clock)
 955 {
 956     intel_clock_t clock;
 957     if (target < 200000) {
 958         clock.p1 = 2;
 959         clock.p2 = 10;
 960         clock.n = 2;
 961         clock.m1 = 23;
 962         clock.m2 = 8;
 963     } else {
 964         clock.p1 = 1;
 965         clock.p2 = 10;
 966         clock.n = 1;
 967         clock.m1 = 14;
 968         clock.m2 = 2;
 969     }
 970     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 971     clock.p = (clock.p1 * clock.p2);
 972     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 973     clock.vco = 0;
 974     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 975     return true;
 976 }
 977
 978 void
 979 intel_wait_for_vblank(struct drm_device *dev)
 980 {
 981         /* Wait for 20ms, i.e. one cycle at 50hz. */
 982         msleep(20);
 983 }
 984
 985 /* Parameters have changed, update FBC info */
 986 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 987 {
 988         struct drm_device *dev = crtc->dev;
 989         struct drm_i915_private *dev_priv = dev->dev_private;
 990         struct drm_framebuffer *fb = crtc->fb;
 991         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 992         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 994         int plane, i;
 995         u32 fbc_ctl, fbc_ctl2;
 996
 997         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 998
 999         if (fb->pitch < dev_priv->cfb_pitch)
1000                 dev_priv->cfb_pitch = fb->pitch;
1001
1002         /* FBC_CTL wants 64B units */
1003         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1004         dev_priv->cfb_fence = obj_priv->fence_reg;
1005         dev_priv->cfb_plane = intel_crtc->plane;
1006         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1007
1008         /* Clear old tags */
1009         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1010                 I915_WRITE(FBC_TAG + (i * 4), 0);
1011
1012         /* Set it up... */
1013         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1014         if (obj_priv->tiling_mode != I915_TILING_NONE)
1015                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1016         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1017         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1018
1019         /* enable it... */
1020         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1021         if (IS_I945GM(dev))
1022                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1023         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1024         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1025         if (obj_priv->tiling_mode != I915_TILING_NONE)
1026                 fbc_ctl |= dev_priv->cfb_fence;
1027         I915_WRITE(FBC_CONTROL, fbc_ctl);
1028
1029         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1030                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1031 }
1032
1033 void i8xx_disable_fbc(struct drm_device *dev)
1034 {
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1037         u32 fbc_ctl;
1038
1039         if (!I915_HAS_FBC(dev))
1040                 return;
1041
1042         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1043                 return; /* Already off, just return */
1044
1045         /* Disable compression */
1046         fbc_ctl = I915_READ(FBC_CONTROL);
1047         fbc_ctl &= ~FBC_CTL_EN;
1048         I915_WRITE(FBC_CONTROL, fbc_ctl);
1049
1050         /* Wait for compressing bit to clear */
1051         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1052                 if (time_after(jiffies, timeout)) {
1053                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1054                         break;
1055                 }
1056                 ; /* do nothing */
1057         }
1058
1059         intel_wait_for_vblank(dev);
1060
1061         DRM_DEBUG_KMS("disabled FBC\n");
1062 }
1063
1064 static bool i8xx_fbc_enabled(struct drm_device *dev)
1065 {
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067
1068         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1069 }
1070
1071 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1072 {
1073         struct drm_device *dev = crtc->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         struct drm_framebuffer *fb = crtc->fb;
1076         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1077         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1079         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1080                      DPFC_CTL_PLANEB);
1081         unsigned long stall_watermark = 200;
1082         u32 dpfc_ctl;
1083
1084         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1085         dev_priv->cfb_fence = obj_priv->fence_reg;
1086         dev_priv->cfb_plane = intel_crtc->plane;
1087
1088         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1089         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1090                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1091                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1092         } else {
1093                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1094         }
1095
1096         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1097         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1098                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1099                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1100         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1101
1102         /* enable it... */
1103         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1104
1105         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1106 }
1107
1108 void g4x_disable_fbc(struct drm_device *dev)
1109 {
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         u32 dpfc_ctl;
1112
1113         /* Disable compression */
1114         dpfc_ctl = I915_READ(DPFC_CONTROL);
1115         dpfc_ctl &= ~DPFC_CTL_EN;
1116         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1117         intel_wait_for_vblank(dev);
1118
1119         DRM_DEBUG_KMS("disabled FBC\n");
1120 }
1121
1122 static bool g4x_fbc_enabled(struct drm_device *dev)
1123 {
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125
1126         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1127 }
1128
1129 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1130 {
1131         struct drm_device *dev = crtc->dev;
1132         struct drm_i915_private *dev_priv = dev->dev_private;
1133         struct drm_framebuffer *fb = crtc->fb;
1134         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1135         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1137         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1138                                                DPFC_CTL_PLANEB;
1139         unsigned long stall_watermark = 200;
1140         u32 dpfc_ctl;
1141
1142         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1143         dev_priv->cfb_fence = obj_priv->fence_reg;
1144         dev_priv->cfb_plane = intel_crtc->plane;
1145
1146         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1147         dpfc_ctl &= DPFC_RESERVED;
1148         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1149         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1150                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1151                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1152         } else {
1153                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1154         }
1155
1156         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1157         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1158                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1159                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1160         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1161         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1162         /* enable it... */
1163         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1164                    DPFC_CTL_EN);
1165
1166         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1167 }
1168
1169 void ironlake_disable_fbc(struct drm_device *dev)
1170 {
1171         struct drm_i915_private *dev_priv = dev->dev_private;
1172         u32 dpfc_ctl;
1173
1174         /* Disable compression */
1175         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1176         dpfc_ctl &= ~DPFC_CTL_EN;
1177         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1178         intel_wait_for_vblank(dev);
1179
1180         DRM_DEBUG_KMS("disabled FBC\n");
1181 }
1182
1183 static bool ironlake_fbc_enabled(struct drm_device *dev)
1184 {
1185         struct drm_i915_private *dev_priv = dev->dev_private;
1186
1187         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1188 }
1189
1190 bool intel_fbc_enabled(struct drm_device *dev)
1191 {
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193
1194         if (!dev_priv->display.fbc_enabled)
1195                 return false;
1196
1197         return dev_priv->display.fbc_enabled(dev);
1198 }
1199
1200 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1201 {
1202         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1203
1204         if (!dev_priv->display.enable_fbc)
1205                 return;
1206
1207         dev_priv->display.enable_fbc(crtc, interval);
1208 }
1209
1210 void intel_disable_fbc(struct drm_device *dev)
1211 {
1212         struct drm_i915_private *dev_priv = dev->dev_private;
1213
1214         if (!dev_priv->display.disable_fbc)
1215                 return;
1216
1217         dev_priv->display.disable_fbc(dev);
1218 }
1219
1220 /**
1221  * intel_update_fbc - enable/disable FBC as needed
1222  * @crtc: CRTC to point the compressor at
1223  * @mode: mode in use
1224  *
1225  * Set up the framebuffer compression hardware at mode set time.  We
1226  * enable it if possible:
1227  *   - plane A only (on pre-965)
1228  *   - no pixel mulitply/line duplication
1229  *   - no alpha buffer discard
1230  *   - no dual wide
1231  *   - framebuffer <= 2048 in width, 1536 in height
1232  *
1233  * We can't assume that any compression will take place (worst case),
1234  * so the compressed buffer has to be the same size as the uncompressed
1235  * one.  It also must reside (along with the line length buffer) in
1236  * stolen memory.
1237  *
1238  * We need to enable/disable FBC on a global basis.
1239  */
1240 static void intel_update_fbc(struct drm_crtc *crtc,
1241                              struct drm_display_mode *mode)
1242 {
1243         struct drm_device *dev = crtc->dev;
1244         struct drm_i915_private *dev_priv = dev->dev_private;
1245         struct drm_framebuffer *fb = crtc->fb;
1246         struct intel_framebuffer *intel_fb;
1247         struct drm_i915_gem_object *obj_priv;
1248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1249         int plane = intel_crtc->plane;
1250
1251         if (!i915_powersave)
1252                 return;
1253
1254         if (!I915_HAS_FBC(dev))
1255                 return;
1256
1257         if (!crtc->fb)
1258                 return;
1259
1260         intel_fb = to_intel_framebuffer(fb);
1261         obj_priv = to_intel_bo(intel_fb->obj);
1262
1263         /*
1264          * If FBC is already on, we just have to verify that we can
1265          * keep it that way...
1266          * Need to disable if:
1267          *   - changing FBC params (stride, fence, mode)
1268          *   - new fb is too large to fit in compressed buffer
1269          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1270          */
1271         if (intel_fb->obj->size > dev_priv->cfb_size) {
1272                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1273                                 "compression\n");
1274                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1275                 goto out_disable;
1276         }
1277         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1278             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1279                 DRM_DEBUG_KMS("mode incompatible with compression, "
1280                                 "disabling\n");
1281                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1282                 goto out_disable;
1283         }
1284         if ((mode->hdisplay > 2048) ||
1285             (mode->vdisplay > 1536)) {
1286                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1287                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1288                 goto out_disable;
1289         }
1290         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1291                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1292                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1293                 goto out_disable;
1294         }
1295         if (obj_priv->tiling_mode != I915_TILING_X) {
1296                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1297                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1298                 goto out_disable;
1299         }
1300
1301         if (intel_fbc_enabled(dev)) {
1302                 /* We can re-enable it in this case, but need to update pitch */
1303                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1304                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1305                     (plane != dev_priv->cfb_plane))
1306                         intel_disable_fbc(dev);
1307         }
1308
1309         /* Now try to turn it back on if possible */
1310         if (!intel_fbc_enabled(dev))
1311                 intel_enable_fbc(crtc, 500);
1312
1313         return;
1314
1315 out_disable:
1316         /* Multiple disables should be harmless */
1317         if (intel_fbc_enabled(dev)) {
1318                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1319                 intel_disable_fbc(dev);
1320         }
1321 }
1322
1323 static int
1324 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1325 {
1326         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1327         u32 alignment;
1328         int ret;
1329
1330         switch (obj_priv->tiling_mode) {
1331         case I915_TILING_NONE:
1332                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1333                         alignment = 128 * 1024;
1334                 else if (IS_I965G(dev))
1335                         alignment = 4 * 1024;
1336                 else
1337                         alignment = 64 * 1024;
1338                 break;
1339         case I915_TILING_X:
1340                 /* pin() will align the object as required by fence */
1341                 alignment = 0;
1342                 break;
1343         case I915_TILING_Y:
1344                 /* FIXME: Is this true? */
1345                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1346                 return -EINVAL;
1347         default:
1348                 BUG();
1349         }
1350
1351         ret = i915_gem_object_pin(obj, alignment);
1352         if (ret != 0)
1353                 return ret;
1354
1355         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1356          * fence, whereas 965+ only requires a fence if using
1357          * framebuffer compression.  For simplicity, we always install
1358          * a fence as the cost is not that onerous.
1359          */
1360         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1361             obj_priv->tiling_mode != I915_TILING_NONE) {
1362                 ret = i915_gem_object_get_fence_reg(obj);
1363                 if (ret != 0) {
1364                         i915_gem_object_unpin(obj);
1365                         return ret;
1366                 }
1367         }
1368
1369         return 0;
1370 }
1371
1372 static int
1373 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1374                     struct drm_framebuffer *old_fb)
1375 {
1376         struct drm_device *dev = crtc->dev;
1377         struct drm_i915_private *dev_priv = dev->dev_private;
1378         struct drm_i915_master_private *master_priv;
1379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1380         struct intel_framebuffer *intel_fb;
1381         struct drm_i915_gem_object *obj_priv;
1382         struct drm_gem_object *obj;
1383         int pipe = intel_crtc->pipe;
1384         int plane = intel_crtc->plane;
1385         unsigned long Start, Offset;
1386         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1387         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1388         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1389         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1390         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1391         u32 dspcntr;
1392         int ret;
1393
1394         /* no fb bound */
1395         if (!crtc->fb) {
1396                 DRM_DEBUG_KMS("No FB bound\n");
1397                 return 0;
1398         }
1399
1400         switch (plane) {
1401         case 0:
1402         case 1:
1403                 break;
1404         default:
1405                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1406                 return -EINVAL;
1407         }
1408
1409         intel_fb = to_intel_framebuffer(crtc->fb);
1410         obj = intel_fb->obj;
1411         obj_priv = to_intel_bo(obj);
1412
1413         mutex_lock(&dev->struct_mutex);
1414         ret = intel_pin_and_fence_fb_obj(dev, obj);
1415         if (ret != 0) {
1416                 mutex_unlock(&dev->struct_mutex);
1417                 return ret;
1418         }
1419
1420         ret = i915_gem_object_set_to_display_plane(obj);
1421         if (ret != 0) {
1422                 i915_gem_object_unpin(obj);
1423                 mutex_unlock(&dev->struct_mutex);
1424                 return ret;
1425         }
1426
1427         dspcntr = I915_READ(dspcntr_reg);
1428         /* Mask out pixel format bits in case we change it */
1429         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1430         switch (crtc->fb->bits_per_pixel) {
1431         case 8:
1432                 dspcntr |= DISPPLANE_8BPP;
1433                 break;
1434         case 16:
1435                 if (crtc->fb->depth == 15)
1436                         dspcntr |= DISPPLANE_15_16BPP;
1437                 else
1438                         dspcntr |= DISPPLANE_16BPP;
1439                 break;
1440         case 24:
1441         case 32:
1442                 if (crtc->fb->depth == 30)
1443                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1444                 else
1445                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1446                 break;
1447         default:
1448                 DRM_ERROR("Unknown color depth\n");
1449                 i915_gem_object_unpin(obj);
1450                 mutex_unlock(&dev->struct_mutex);
1451                 return -EINVAL;
1452         }
1453         if (IS_I965G(dev)) {
1454                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1455                         dspcntr |= DISPPLANE_TILED;
1456                 else
1457                         dspcntr &= ~DISPPLANE_TILED;
1458         }
1459
1460         if (HAS_PCH_SPLIT(dev))
1461                 /* must disable */
1462                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1463
1464         I915_WRITE(dspcntr_reg, dspcntr);
1465
1466         Start = obj_priv->gtt_offset;
1467         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1468
1469         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1470                       Start, Offset, x, y, crtc->fb->pitch);
1471         I915_WRITE(dspstride, crtc->fb->pitch);
1472         if (IS_I965G(dev)) {
1473                 I915_WRITE(dspbase, Offset);
1474                 I915_READ(dspbase);
1475                 I915_WRITE(dspsurf, Start);
1476                 I915_READ(dspsurf);
1477                 I915_WRITE(dsptileoff, (y << 16) | x);
1478         } else {
1479                 I915_WRITE(dspbase, Start + Offset);
1480                 I915_READ(dspbase);
1481         }
1482
1483         if ((IS_I965G(dev) || plane == 0))
1484                 intel_update_fbc(crtc, &crtc->mode);
1485
1486         intel_wait_for_vblank(dev);
1487
1488         if (old_fb) {
1489                 intel_fb = to_intel_framebuffer(old_fb);
1490                 obj_priv = to_intel_bo(intel_fb->obj);
1491                 i915_gem_object_unpin(intel_fb->obj);
1492         }
1493         intel_increase_pllclock(crtc, true);
1494
1495         mutex_unlock(&dev->struct_mutex);
1496
1497         if (!dev->primary->master)
1498                 return 0;
1499
1500         master_priv = dev->primary->master->driver_priv;
1501         if (!master_priv->sarea_priv)
1502                 return 0;
1503
1504         if (pipe) {
1505                 master_priv->sarea_priv->pipeB_x = x;
1506                 master_priv->sarea_priv->pipeB_y = y;
1507         } else {
1508                 master_priv->sarea_priv->pipeA_x = x;
1509                 master_priv->sarea_priv->pipeA_y = y;
1510         }
1511
1512         return 0;
1513 }
1514
1515 /* Disable the VGA plane that we never use */
1516 static void i915_disable_vga (struct drm_device *dev)
1517 {
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519         u8 sr1;
1520         u32 vga_reg;
1521
1522         if (HAS_PCH_SPLIT(dev))
1523                 vga_reg = CPU_VGACNTRL;
1524         else
1525                 vga_reg = VGACNTRL;
1526
1527         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1528                 return;
1529
1530         I915_WRITE8(VGA_SR_INDEX, 1);
1531         sr1 = I915_READ8(VGA_SR_DATA);
1532         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1533         udelay(100);
1534
1535         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1536 }
1537
1538 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1539 {
1540         struct drm_device *dev = crtc->dev;
1541         struct drm_i915_private *dev_priv = dev->dev_private;
1542         u32 dpa_ctl;
1543
1544         DRM_DEBUG_KMS("\n");
1545         dpa_ctl = I915_READ(DP_A);
1546         dpa_ctl &= ~DP_PLL_ENABLE;
1547         I915_WRITE(DP_A, dpa_ctl);
1548 }
1549
1550 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1551 {
1552         struct drm_device *dev = crtc->dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         u32 dpa_ctl;
1555
1556         dpa_ctl = I915_READ(DP_A);
1557         dpa_ctl |= DP_PLL_ENABLE;
1558         I915_WRITE(DP_A, dpa_ctl);
1559         udelay(200);
1560 }
1561
1562
1563 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1564 {
1565         struct drm_device *dev = crtc->dev;
1566         struct drm_i915_private *dev_priv = dev->dev_private;
1567         u32 dpa_ctl;
1568
1569         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1570         dpa_ctl = I915_READ(DP_A);
1571         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1572
1573         if (clock < 200000) {
1574                 u32 temp;
1575                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1576                 /* workaround for 160Mhz:
1577                    1) program 0x4600c bits 15:0 = 0x8124
1578                    2) program 0x46010 bit 0 = 1
1579                    3) program 0x46034 bit 24 = 1
1580                    4) program 0x64000 bit 14 = 1
1581                    */
1582                 temp = I915_READ(0x4600c);
1583                 temp &= 0xffff0000;
1584                 I915_WRITE(0x4600c, temp | 0x8124);
1585
1586                 temp = I915_READ(0x46010);
1587                 I915_WRITE(0x46010, temp | 1);
1588
1589                 temp = I915_READ(0x46034);
1590                 I915_WRITE(0x46034, temp | (1 << 24));
1591         } else {
1592                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1593         }
1594         I915_WRITE(DP_A, dpa_ctl);
1595
1596         udelay(500);
1597 }
1598
1599 /* The FDI link training functions for ILK/Ibexpeak. */
1600 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1601 {
1602         struct drm_device *dev = crtc->dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1605         int pipe = intel_crtc->pipe;
1606         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1607         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1608         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1609         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1610         u32 temp, tries = 0;
1611
1612         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1613            for train result */
1614         temp = I915_READ(fdi_rx_imr_reg);
1615         temp &= ~FDI_RX_SYMBOL_LOCK;
1616         temp &= ~FDI_RX_BIT_LOCK;
1617         I915_WRITE(fdi_rx_imr_reg, temp);
1618         I915_READ(fdi_rx_imr_reg);
1619         udelay(150);
1620
1621         /* enable CPU FDI TX and PCH FDI RX */
1622         temp = I915_READ(fdi_tx_reg);
1623         temp |= FDI_TX_ENABLE;
1624         temp &= ~(7 << 19);
1625         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1626         temp &= ~FDI_LINK_TRAIN_NONE;
1627         temp |= FDI_LINK_TRAIN_PATTERN_1;
1628         I915_WRITE(fdi_tx_reg, temp);
1629         I915_READ(fdi_tx_reg);
1630
1631         temp = I915_READ(fdi_rx_reg);
1632         temp &= ~FDI_LINK_TRAIN_NONE;
1633         temp |= FDI_LINK_TRAIN_PATTERN_1;
1634         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1635         I915_READ(fdi_rx_reg);
1636         udelay(150);
1637
1638         for (tries = 0; tries < 5; tries++) {
1639                 temp = I915_READ(fdi_rx_iir_reg);
1640                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1641
1642                 if ((temp & FDI_RX_BIT_LOCK)) {
1643                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1644                         I915_WRITE(fdi_rx_iir_reg,
1645                                    temp | FDI_RX_BIT_LOCK);
1646                         break;
1647                 }
1648         }
1649         if (tries == 5)
1650                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1651
1652         /* Train 2 */
1653         temp = I915_READ(fdi_tx_reg);
1654         temp &= ~FDI_LINK_TRAIN_NONE;
1655         temp |= FDI_LINK_TRAIN_PATTERN_2;
1656         I915_WRITE(fdi_tx_reg, temp);
1657
1658         temp = I915_READ(fdi_rx_reg);
1659         temp &= ~FDI_LINK_TRAIN_NONE;
1660         temp |= FDI_LINK_TRAIN_PATTERN_2;
1661         I915_WRITE(fdi_rx_reg, temp);
1662         udelay(150);
1663
1664         tries = 0;
1665
1666         for (tries = 0; tries < 5; tries++) {
1667                 temp = I915_READ(fdi_rx_iir_reg);
1668                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1669
1670                 if (temp & FDI_RX_SYMBOL_LOCK) {
1671                         I915_WRITE(fdi_rx_iir_reg,
1672                                    temp | FDI_RX_SYMBOL_LOCK);
1673                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1674                         break;
1675                 }
1676         }
1677         if (tries == 5)
1678                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1679
1680         DRM_DEBUG_KMS("FDI train done\n");
1681 }
1682
1683 static int snb_b_fdi_train_param [] = {
1684         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1685         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1686         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1687         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1688 };
1689
1690 /* The FDI link training functions for SNB/Cougarpoint. */
1691 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1692 {
1693         struct drm_device *dev = crtc->dev;
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1696         int pipe = intel_crtc->pipe;
1697         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1698         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1699         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1700         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1701         u32 temp, i;
1702
1703         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1704            for train result */
1705         temp = I915_READ(fdi_rx_imr_reg);
1706         temp &= ~FDI_RX_SYMBOL_LOCK;
1707         temp &= ~FDI_RX_BIT_LOCK;
1708         I915_WRITE(fdi_rx_imr_reg, temp);
1709         I915_READ(fdi_rx_imr_reg);
1710         udelay(150);
1711
1712         /* enable CPU FDI TX and PCH FDI RX */
1713         temp = I915_READ(fdi_tx_reg);
1714         temp |= FDI_TX_ENABLE;
1715         temp &= ~(7 << 19);
1716         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1717         temp &= ~FDI_LINK_TRAIN_NONE;
1718         temp |= FDI_LINK_TRAIN_PATTERN_1;
1719         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1720         /* SNB-B */
1721         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1722         I915_WRITE(fdi_tx_reg, temp);
1723         I915_READ(fdi_tx_reg);
1724
1725         temp = I915_READ(fdi_rx_reg);
1726         if (HAS_PCH_CPT(dev)) {
1727                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1728                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1729         } else {
1730                 temp &= ~FDI_LINK_TRAIN_NONE;
1731                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1732         }
1733         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1734         I915_READ(fdi_rx_reg);
1735         udelay(150);
1736
1737         for (i = 0; i < 4; i++ ) {
1738                 temp = I915_READ(fdi_tx_reg);
1739                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1740                 temp |= snb_b_fdi_train_param[i];
1741                 I915_WRITE(fdi_tx_reg, temp);
1742                 udelay(500);
1743
1744                 temp = I915_READ(fdi_rx_iir_reg);
1745                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1746
1747                 if (temp & FDI_RX_BIT_LOCK) {
1748                         I915_WRITE(fdi_rx_iir_reg,
1749                                    temp | FDI_RX_BIT_LOCK);
1750                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1751                         break;
1752                 }
1753         }
1754         if (i == 4)
1755                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1756
1757         /* Train 2 */
1758         temp = I915_READ(fdi_tx_reg);
1759         temp &= ~FDI_LINK_TRAIN_NONE;
1760         temp |= FDI_LINK_TRAIN_PATTERN_2;
1761         if (IS_GEN6(dev)) {
1762                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1763                 /* SNB-B */
1764                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1765         }
1766         I915_WRITE(fdi_tx_reg, temp);
1767
1768         temp = I915_READ(fdi_rx_reg);
1769         if (HAS_PCH_CPT(dev)) {
1770                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1771                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1772         } else {
1773                 temp &= ~FDI_LINK_TRAIN_NONE;
1774                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1775         }
1776         I915_WRITE(fdi_rx_reg, temp);
1777         udelay(150);
1778
1779         for (i = 0; i < 4; i++ ) {
1780                 temp = I915_READ(fdi_tx_reg);
1781                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1782                 temp |= snb_b_fdi_train_param[i];
1783                 I915_WRITE(fdi_tx_reg, temp);
1784                 udelay(500);
1785
1786                 temp = I915_READ(fdi_rx_iir_reg);
1787                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1788
1789                 if (temp & FDI_RX_SYMBOL_LOCK) {
1790                         I915_WRITE(fdi_rx_iir_reg,
1791                                    temp | FDI_RX_SYMBOL_LOCK);
1792                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1793                         break;
1794                 }
1795         }
1796         if (i == 4)
1797                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1798
1799         DRM_DEBUG_KMS("FDI train done.\n");
1800 }
1801
1802 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1803 {
1804         struct drm_device *dev = crtc->dev;
1805         struct drm_i915_private *dev_priv = dev->dev_private;
1806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1807         int pipe = intel_crtc->pipe;
1808         int plane = intel_crtc->plane;
1809         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1810         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1811         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1812         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1813         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1814         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1815         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1816         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1817         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1818         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1819         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1820         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1821         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1822         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1823         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1824         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1825         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1826         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1827         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1828         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1829         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1830         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1831         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1832         u32 temp;
1833         int n;
1834         u32 pipe_bpc;
1835
1836         temp = I915_READ(pipeconf_reg);
1837         pipe_bpc = temp & PIPE_BPC_MASK;
1838
1839         /* XXX: When our outputs are all unaware of DPMS modes other than off
1840          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1841          */
1842         switch (mode) {
1843         case DRM_MODE_DPMS_ON:
1844         case DRM_MODE_DPMS_STANDBY:
1845         case DRM_MODE_DPMS_SUSPEND:
1846                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1847
1848                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1849                         temp = I915_READ(PCH_LVDS);
1850                         if ((temp & LVDS_PORT_EN) == 0) {
1851                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1852                                 POSTING_READ(PCH_LVDS);
1853                         }
1854                 }
1855
1856                 if (HAS_eDP) {
1857                         /* enable eDP PLL */
1858                         ironlake_enable_pll_edp(crtc);
1859                 } else {
1860
1861                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1862                         temp = I915_READ(fdi_rx_reg);
1863                         /*
1864                          * make the BPC in FDI Rx be consistent with that in
1865                          * pipeconf reg.
1866                          */
1867                         temp &= ~(0x7 << 16);
1868                         temp |= (pipe_bpc << 11);
1869                         temp &= ~(7 << 19);
1870                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1871                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1872                         I915_READ(fdi_rx_reg);
1873                         udelay(200);
1874
1875                         /* Switch from Rawclk to PCDclk */
1876                         temp = I915_READ(fdi_rx_reg);
1877                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1878                         I915_READ(fdi_rx_reg);
1879                         udelay(200);
1880
1881                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1882                         temp = I915_READ(fdi_tx_reg);
1883                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1884                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1885                                 I915_READ(fdi_tx_reg);
1886                                 udelay(100);
1887                         }
1888                 }
1889
1890                 /* Enable panel fitting for LVDS */
1891                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1892                         temp = I915_READ(pf_ctl_reg);
1893                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1894
1895                         /* currently full aspect */
1896                         I915_WRITE(pf_win_pos, 0);
1897
1898                         I915_WRITE(pf_win_size,
1899                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1900                                    (dev_priv->panel_fixed_mode->vdisplay));
1901                 }
1902
1903                 /* Enable CPU pipe */
1904                 temp = I915_READ(pipeconf_reg);
1905                 if ((temp & PIPEACONF_ENABLE) == 0) {
1906                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1907                         I915_READ(pipeconf_reg);
1908                         udelay(100);
1909                 }
1910
1911                 /* configure and enable CPU plane */
1912                 temp = I915_READ(dspcntr_reg);
1913                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1914                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1915                         /* Flush the plane changes */
1916                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1917                 }
1918
1919                 if (!HAS_eDP) {
1920                         /* For PCH output, training FDI link */
1921                         if (IS_GEN6(dev))
1922                                 gen6_fdi_link_train(crtc);
1923                         else
1924                                 ironlake_fdi_link_train(crtc);
1925
1926                         /* enable PCH DPLL */
1927                         temp = I915_READ(pch_dpll_reg);
1928                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1929                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1930                                 I915_READ(pch_dpll_reg);
1931                         }
1932                         udelay(200);
1933
1934                         if (HAS_PCH_CPT(dev)) {
1935                                 /* Be sure PCH DPLL SEL is set */
1936                                 temp = I915_READ(PCH_DPLL_SEL);
1937                                 if (trans_dpll_sel == 0 &&
1938                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1939                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1940                                 else if (trans_dpll_sel == 1 &&
1941                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1942                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1943                                 I915_WRITE(PCH_DPLL_SEL, temp);
1944                                 I915_READ(PCH_DPLL_SEL);
1945                         }
1946
1947                         /* set transcoder timing */
1948                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1949                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1950                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1951
1952                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1953                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1954                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1955
1956                         /* enable normal train */
1957                         temp = I915_READ(fdi_tx_reg);
1958                         temp &= ~FDI_LINK_TRAIN_NONE;
1959                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1960                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1961                         I915_READ(fdi_tx_reg);
1962
1963                         temp = I915_READ(fdi_rx_reg);
1964                         if (HAS_PCH_CPT(dev)) {
1965                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1966                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1967                         } else {
1968                                 temp &= ~FDI_LINK_TRAIN_NONE;
1969                                 temp |= FDI_LINK_TRAIN_NONE;
1970                         }
1971                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1972                         I915_READ(fdi_rx_reg);
1973
1974                         /* wait one idle pattern time */
1975                         udelay(100);
1976
1977                         /* For PCH DP, enable TRANS_DP_CTL */
1978                         if (HAS_PCH_CPT(dev) &&
1979                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1980                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1981                                 int reg;
1982
1983                                 reg = I915_READ(trans_dp_ctl);
1984                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
1985                                 reg = TRANS_DP_OUTPUT_ENABLE |
1986                                       TRANS_DP_ENH_FRAMING |
1987                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
1988                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
1989
1990                                 switch (intel_trans_dp_port_sel(crtc)) {
1991                                 case PCH_DP_B:
1992                                         reg |= TRANS_DP_PORT_SEL_B;
1993                                         break;
1994                                 case PCH_DP_C:
1995                                         reg |= TRANS_DP_PORT_SEL_C;
1996                                         break;
1997                                 case PCH_DP_D:
1998                                         reg |= TRANS_DP_PORT_SEL_D;
1999                                         break;
2000                                 default:
2001                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2002                                         reg |= TRANS_DP_PORT_SEL_B;
2003                                         break;
2004                                 }
2005
2006                                 I915_WRITE(trans_dp_ctl, reg);
2007                                 POSTING_READ(trans_dp_ctl);
2008                         }
2009
2010                         /* enable PCH transcoder */
2011                         temp = I915_READ(transconf_reg);
2012                         /*
2013                          * make the BPC in transcoder be consistent with
2014                          * that in pipeconf reg.
2015                          */
2016                         temp &= ~PIPE_BPC_MASK;
2017                         temp |= pipe_bpc;
2018                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2019                         I915_READ(transconf_reg);
2020
2021                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2022                                 ;
2023
2024                 }
2025
2026                 intel_crtc_load_lut(crtc);
2027
2028                 intel_update_fbc(crtc, &crtc->mode);
2029
2030         break;
2031         case DRM_MODE_DPMS_OFF:
2032                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2033
2034                 drm_vblank_off(dev, pipe);
2035                 /* Disable display plane */
2036                 temp = I915_READ(dspcntr_reg);
2037                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2038                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2039                         /* Flush the plane changes */
2040                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2041                         I915_READ(dspbase_reg);
2042                 }
2043
2044                 if (dev_priv->cfb_plane == plane &&
2045                     dev_priv->display.disable_fbc)
2046                         dev_priv->display.disable_fbc(dev);
2047
2048                 i915_disable_vga(dev);
2049
2050                 /* disable cpu pipe, disable after all planes disabled */
2051                 temp = I915_READ(pipeconf_reg);
2052                 if ((temp & PIPEACONF_ENABLE) != 0) {
2053                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2054                         I915_READ(pipeconf_reg);
2055                         n = 0;
2056                         /* wait for cpu pipe off, pipe state */
2057                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2058                                 n++;
2059                                 if (n < 60) {
2060                                         udelay(500);
2061                                         continue;
2062                                 } else {
2063                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2064                                                                 pipe);
2065                                         break;
2066                                 }
2067                         }
2068                 } else
2069                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2070
2071                 udelay(100);
2072
2073                 /* Disable PF */
2074                 temp = I915_READ(pf_ctl_reg);
2075                 if ((temp & PF_ENABLE) != 0) {
2076                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2077                         I915_READ(pf_ctl_reg);
2078                 }
2079                 I915_WRITE(pf_win_size, 0);
2080                 POSTING_READ(pf_win_size);
2081
2082
2083                 /* disable CPU FDI tx and PCH FDI rx */
2084                 temp = I915_READ(fdi_tx_reg);
2085                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2086                 I915_READ(fdi_tx_reg);
2087
2088                 temp = I915_READ(fdi_rx_reg);
2089                 /* BPC in FDI rx is consistent with that in pipeconf */
2090                 temp &= ~(0x07 << 16);
2091                 temp |= (pipe_bpc << 11);
2092                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2093                 I915_READ(fdi_rx_reg);
2094
2095                 udelay(100);
2096
2097                 /* still set train pattern 1 */
2098                 temp = I915_READ(fdi_tx_reg);
2099                 temp &= ~FDI_LINK_TRAIN_NONE;
2100                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2101                 I915_WRITE(fdi_tx_reg, temp);
2102                 POSTING_READ(fdi_tx_reg);
2103
2104                 temp = I915_READ(fdi_rx_reg);
2105                 if (HAS_PCH_CPT(dev)) {
2106                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2107                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2108                 } else {
2109                         temp &= ~FDI_LINK_TRAIN_NONE;
2110                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2111                 }
2112                 I915_WRITE(fdi_rx_reg, temp);
2113                 POSTING_READ(fdi_rx_reg);
2114
2115                 udelay(100);
2116
2117                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2118                         temp = I915_READ(PCH_LVDS);
2119                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2120                         I915_READ(PCH_LVDS);
2121                         udelay(100);
2122                 }
2123
2124                 /* disable PCH transcoder */
2125                 temp = I915_READ(transconf_reg);
2126                 if ((temp & TRANS_ENABLE) != 0) {
2127                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2128                         I915_READ(transconf_reg);
2129                         n = 0;
2130                         /* wait for PCH transcoder off, transcoder state */
2131                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2132                                 n++;
2133                                 if (n < 60) {
2134                                         udelay(500);
2135                                         continue;
2136                                 } else {
2137                                         DRM_DEBUG_KMS("transcoder %d off "
2138                                                         "delay\n", pipe);
2139                                         break;
2140                                 }
2141                         }
2142                 }
2143
2144                 temp = I915_READ(transconf_reg);
2145                 /* BPC in transcoder is consistent with that in pipeconf */
2146                 temp &= ~PIPE_BPC_MASK;
2147                 temp |= pipe_bpc;
2148                 I915_WRITE(transconf_reg, temp);
2149                 I915_READ(transconf_reg);
2150                 udelay(100);
2151
2152                 if (HAS_PCH_CPT(dev)) {
2153                         /* disable TRANS_DP_CTL */
2154                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2155                         int reg;
2156
2157                         reg = I915_READ(trans_dp_ctl);
2158                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2159                         I915_WRITE(trans_dp_ctl, reg);
2160                         POSTING_READ(trans_dp_ctl);
2161
2162                         /* disable DPLL_SEL */
2163                         temp = I915_READ(PCH_DPLL_SEL);
2164                         if (trans_dpll_sel == 0)
2165                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2166                         else
2167                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2168                         I915_WRITE(PCH_DPLL_SEL, temp);
2169                         I915_READ(PCH_DPLL_SEL);
2170
2171                 }
2172
2173                 /* disable PCH DPLL */
2174                 temp = I915_READ(pch_dpll_reg);
2175                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2176                 I915_READ(pch_dpll_reg);
2177
2178                 if (HAS_eDP) {
2179                         ironlake_disable_pll_edp(crtc);
2180                 }
2181
2182                 /* Switch from PCDclk to Rawclk */
2183                 temp = I915_READ(fdi_rx_reg);
2184                 temp &= ~FDI_SEL_PCDCLK;
2185                 I915_WRITE(fdi_rx_reg, temp);
2186                 I915_READ(fdi_rx_reg);
2187
2188                 /* Disable CPU FDI TX PLL */
2189                 temp = I915_READ(fdi_tx_reg);
2190                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2191                 I915_READ(fdi_tx_reg);
2192                 udelay(100);
2193
2194                 temp = I915_READ(fdi_rx_reg);
2195                 temp &= ~FDI_RX_PLL_ENABLE;
2196                 I915_WRITE(fdi_rx_reg, temp);
2197                 I915_READ(fdi_rx_reg);
2198
2199                 /* Wait for the clocks to turn off. */
2200                 udelay(100);
2201                 break;
2202         }
2203 }
2204
2205 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2206 {
2207         struct intel_overlay *overlay;
2208         int ret;
2209
2210         if (!enable && intel_crtc->overlay) {
2211                 overlay = intel_crtc->overlay;
2212                 mutex_lock(&overlay->dev->struct_mutex);
2213                 for (;;) {
2214                         ret = intel_overlay_switch_off(overlay);
2215                         if (ret == 0)
2216                                 break;
2217
2218                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2219                         if (ret != 0) {
2220                                 /* overlay doesn't react anymore. Usually
2221                                  * results in a black screen and an unkillable
2222                                  * X server. */
2223                                 BUG();
2224                                 overlay->hw_wedged = HW_WEDGED;
2225                                 break;
2226                         }
2227                 }
2228                 mutex_unlock(&overlay->dev->struct_mutex);
2229         }
2230         /* Let userspace switch the overlay on again. In most cases userspace
2231          * has to recompute where to put it anyway. */
2232
2233         return;
2234 }
2235
2236 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2237 {
2238         struct drm_device *dev = crtc->dev;
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2241         int pipe = intel_crtc->pipe;
2242         int plane = intel_crtc->plane;
2243         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2244         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2245         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2246         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2247         u32 temp;
2248
2249         /* XXX: When our outputs are all unaware of DPMS modes other than off
2250          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2251          */
2252         switch (mode) {
2253         case DRM_MODE_DPMS_ON:
2254         case DRM_MODE_DPMS_STANDBY:
2255         case DRM_MODE_DPMS_SUSPEND:
2256                 intel_update_watermarks(dev);
2257
2258                 /* Enable the DPLL */
2259                 temp = I915_READ(dpll_reg);
2260                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2261                         I915_WRITE(dpll_reg, temp);
2262                         I915_READ(dpll_reg);
2263                         /* Wait for the clocks to stabilize. */
2264                         udelay(150);
2265                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2266                         I915_READ(dpll_reg);
2267                         /* Wait for the clocks to stabilize. */
2268                         udelay(150);
2269                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2270                         I915_READ(dpll_reg);
2271                         /* Wait for the clocks to stabilize. */
2272                         udelay(150);
2273                 }
2274
2275                 /* Enable the pipe */
2276                 temp = I915_READ(pipeconf_reg);
2277                 if ((temp & PIPEACONF_ENABLE) == 0)
2278                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2279
2280                 /* Enable the plane */
2281                 temp = I915_READ(dspcntr_reg);
2282                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2283                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2284                         /* Flush the plane changes */
2285                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2286                 }
2287
2288                 intel_crtc_load_lut(crtc);
2289
2290                 if ((IS_I965G(dev) || plane == 0))
2291                         intel_update_fbc(crtc, &crtc->mode);
2292
2293                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2294                 intel_crtc_dpms_overlay(intel_crtc, true);
2295         break;
2296         case DRM_MODE_DPMS_OFF:
2297                 intel_update_watermarks(dev);
2298
2299                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2300                 intel_crtc_dpms_overlay(intel_crtc, false);
2301                 drm_vblank_off(dev, pipe);
2302
2303                 if (dev_priv->cfb_plane == plane &&
2304                     dev_priv->display.disable_fbc)
2305                         dev_priv->display.disable_fbc(dev);
2306
2307                 /* Disable the VGA plane that we never use */
2308                 i915_disable_vga(dev);
2309
2310                 /* Disable display plane */
2311                 temp = I915_READ(dspcntr_reg);
2312                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2313                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2314                         /* Flush the plane changes */
2315                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2316                         I915_READ(dspbase_reg);
2317                 }
2318
2319                 if (!IS_I9XX(dev)) {
2320                         /* Wait for vblank for the disable to take effect */
2321                         intel_wait_for_vblank(dev);
2322                 }
2323
2324                 /* Next, disable display pipes */
2325                 temp = I915_READ(pipeconf_reg);
2326                 if ((temp & PIPEACONF_ENABLE) != 0) {
2327                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2328                         I915_READ(pipeconf_reg);
2329                 }
2330
2331                 /* Wait for vblank for the disable to take effect. */
2332                 intel_wait_for_vblank(dev);
2333
2334                 temp = I915_READ(dpll_reg);
2335                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2336                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2337                         I915_READ(dpll_reg);
2338                 }
2339
2340                 /* Wait for the clocks to turn off. */
2341                 udelay(150);
2342                 break;
2343         }
2344 }
2345
2346 /**
2347  * Sets the power management mode of the pipe and plane.
2348  *
2349  * This code should probably grow support for turning the cursor off and back
2350  * on appropriately at the same time as we're turning the pipe off/on.
2351  */
2352 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2353 {
2354         struct drm_device *dev = crtc->dev;
2355         struct drm_i915_private *dev_priv = dev->dev_private;
2356         struct drm_i915_master_private *master_priv;
2357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2358         int pipe = intel_crtc->pipe;
2359         bool enabled;
2360
2361         dev_priv->display.dpms(crtc, mode);
2362
2363         intel_crtc->dpms_mode = mode;
2364
2365         if (!dev->primary->master)
2366                 return;
2367
2368         master_priv = dev->primary->master->driver_priv;
2369         if (!master_priv->sarea_priv)
2370                 return;
2371
2372         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2373
2374         switch (pipe) {
2375         case 0:
2376                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2377                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2378                 break;
2379         case 1:
2380                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2381                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2382                 break;
2383         default:
2384                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2385                 break;
2386         }
2387 }
2388
2389 static void intel_crtc_prepare (struct drm_crtc *crtc)
2390 {
2391         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2392         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2393 }
2394
2395 static void intel_crtc_commit (struct drm_crtc *crtc)
2396 {
2397         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2398         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2399 }
2400
2401 void intel_encoder_prepare (struct drm_encoder *encoder)
2402 {
2403         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2404         /* lvds has its own version of prepare see intel_lvds_prepare */
2405         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2406 }
2407
2408 void intel_encoder_commit (struct drm_encoder *encoder)
2409 {
2410         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2411         /* lvds has its own version of commit see intel_lvds_commit */
2412         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2413 }
2414
2415 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2416                                   struct drm_display_mode *mode,
2417                                   struct drm_display_mode *adjusted_mode)
2418 {
2419         struct drm_device *dev = crtc->dev;
2420         if (HAS_PCH_SPLIT(dev)) {
2421                 /* FDI link clock is fixed at 2.7G */
2422                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2423                         return false;
2424         }
2425
2426         drm_mode_set_crtcinfo(adjusted_mode, 0);
2427         return true;
2428 }
2429
2430 static int i945_get_display_clock_speed(struct drm_device *dev)
2431 {
2432         return 400000;
2433 }
2434
2435 static int i915_get_display_clock_speed(struct drm_device *dev)
2436 {
2437         return 333000;
2438 }
2439
2440 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2441 {
2442         return 200000;
2443 }
2444
2445 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2446 {
2447         u16 gcfgc = 0;
2448
2449         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2450
2451         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2452                 return 133000;
2453         else {
2454                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2455                 case GC_DISPLAY_CLOCK_333_MHZ:
2456                         return 333000;
2457                 default:
2458                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2459                         return 190000;
2460                 }
2461         }
2462 }
2463
2464 static int i865_get_display_clock_speed(struct drm_device *dev)
2465 {
2466         return 266000;
2467 }
2468
2469 static int i855_get_display_clock_speed(struct drm_device *dev)
2470 {
2471         u16 hpllcc = 0;
2472         /* Assume that the hardware is in the high speed state.  This
2473          * should be the default.
2474          */
2475         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2476         case GC_CLOCK_133_200:
2477         case GC_CLOCK_100_200:
2478                 return 200000;
2479         case GC_CLOCK_166_250:
2480                 return 250000;
2481         case GC_CLOCK_100_133:
2482                 return 133000;
2483         }
2484
2485         /* Shouldn't happen */
2486         return 0;
2487 }
2488
2489 static int i830_get_display_clock_speed(struct drm_device *dev)
2490 {
2491         return 133000;
2492 }
2493
2494 /**
2495  * Return the pipe currently connected to the panel fitter,
2496  * or -1 if the panel fitter is not present or not in use
2497  */
2498 int intel_panel_fitter_pipe (struct drm_device *dev)
2499 {
2500         struct drm_i915_private *dev_priv = dev->dev_private;
2501         u32  pfit_control;
2502
2503         /* i830 doesn't have a panel fitter */
2504         if (IS_I830(dev))
2505                 return -1;
2506
2507         pfit_control = I915_READ(PFIT_CONTROL);
2508
2509         /* See if the panel fitter is in use */
2510         if ((pfit_control & PFIT_ENABLE) == 0)
2511                 return -1;
2512
2513         /* 965 can place panel fitter on either pipe */
2514         if (IS_I965G(dev))
2515                 return (pfit_control >> 29) & 0x3;
2516
2517         /* older chips can only use pipe 1 */
2518         return 1;
2519 }
2520
2521 struct fdi_m_n {
2522         u32        tu;
2523         u32        gmch_m;
2524         u32        gmch_n;
2525         u32        link_m;
2526         u32        link_n;
2527 };
2528
2529 static void
2530 fdi_reduce_ratio(u32 *num, u32 *den)
2531 {
2532         while (*num > 0xffffff || *den > 0xffffff) {
2533                 *num >>= 1;
2534                 *den >>= 1;
2535         }
2536 }
2537
2538 #define DATA_N 0x800000
2539 #define LINK_N 0x80000
2540
2541 static void
2542 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2543                      int link_clock, struct fdi_m_n *m_n)
2544 {
2545         u64 temp;
2546
2547         m_n->tu = 64; /* default size */
2548
2549         temp = (u64) DATA_N * pixel_clock;
2550         temp = div_u64(temp, link_clock);
2551         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2552         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2553         m_n->gmch_n = DATA_N;
2554         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2555
2556         temp = (u64) LINK_N * pixel_clock;
2557         m_n->link_m = div_u64(temp, link_clock);
2558         m_n->link_n = LINK_N;
2559         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2560 }
2561
2562
2563 struct intel_watermark_params {
2564         unsigned long fifo_size;
2565         unsigned long max_wm;
2566         unsigned long default_wm;
2567         unsigned long guard_size;
2568         unsigned long cacheline_size;
2569 };
2570
2571 /* Pineview has different values for various configs */
2572 static struct intel_watermark_params pineview_display_wm = {
2573         PINEVIEW_DISPLAY_FIFO,
2574         PINEVIEW_MAX_WM,
2575         PINEVIEW_DFT_WM,
2576         PINEVIEW_GUARD_WM,
2577         PINEVIEW_FIFO_LINE_SIZE
2578 };
2579 static struct intel_watermark_params pineview_display_hplloff_wm = {
2580         PINEVIEW_DISPLAY_FIFO,
2581         PINEVIEW_MAX_WM,
2582         PINEVIEW_DFT_HPLLOFF_WM,
2583         PINEVIEW_GUARD_WM,
2584         PINEVIEW_FIFO_LINE_SIZE
2585 };
2586 static struct intel_watermark_params pineview_cursor_wm = {
2587         PINEVIEW_CURSOR_FIFO,
2588         PINEVIEW_CURSOR_MAX_WM,
2589         PINEVIEW_CURSOR_DFT_WM,
2590         PINEVIEW_CURSOR_GUARD_WM,
2591         PINEVIEW_FIFO_LINE_SIZE,
2592 };
2593 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2594         PINEVIEW_CURSOR_FIFO,
2595         PINEVIEW_CURSOR_MAX_WM,
2596         PINEVIEW_CURSOR_DFT_WM,
2597         PINEVIEW_CURSOR_GUARD_WM,
2598         PINEVIEW_FIFO_LINE_SIZE
2599 };
2600 static struct intel_watermark_params g4x_wm_info = {
2601         G4X_FIFO_SIZE,
2602         G4X_MAX_WM,
2603         G4X_MAX_WM,
2604         2,
2605         G4X_FIFO_LINE_SIZE,
2606 };
2607 static struct intel_watermark_params g4x_cursor_wm_info = {
2608         I965_CURSOR_FIFO,
2609         I965_CURSOR_MAX_WM,
2610         I965_CURSOR_DFT_WM,
2611         2,
2612         G4X_FIFO_LINE_SIZE,
2613 };
2614 static struct intel_watermark_params i965_cursor_wm_info = {
2615         I965_CURSOR_FIFO,
2616         I965_CURSOR_MAX_WM,
2617         I965_CURSOR_DFT_WM,
2618         2,
2619         I915_FIFO_LINE_SIZE,
2620 };
2621 static struct intel_watermark_params i945_wm_info = {
2622         I945_FIFO_SIZE,
2623         I915_MAX_WM,
2624         1,
2625         2,
2626         I915_FIFO_LINE_SIZE
2627 };
2628 static struct intel_watermark_params i915_wm_info = {
2629         I915_FIFO_SIZE,
2630         I915_MAX_WM,
2631         1,
2632         2,
2633         I915_FIFO_LINE_SIZE
2634 };
2635 static struct intel_watermark_params i855_wm_info = {
2636         I855GM_FIFO_SIZE,
2637         I915_MAX_WM,
2638         1,
2639         2,
2640         I830_FIFO_LINE_SIZE
2641 };
2642 static struct intel_watermark_params i830_wm_info = {
2643         I830_FIFO_SIZE,
2644         I915_MAX_WM,
2645         1,
2646         2,
2647         I830_FIFO_LINE_SIZE
2648 };
2649
2650 static struct intel_watermark_params ironlake_display_wm_info = {
2651         ILK_DISPLAY_FIFO,
2652         ILK_DISPLAY_MAXWM,
2653         ILK_DISPLAY_DFTWM,
2654         2,
2655         ILK_FIFO_LINE_SIZE
2656 };
2657
2658 static struct intel_watermark_params ironlake_cursor_wm_info = {
2659         ILK_CURSOR_FIFO,
2660         ILK_CURSOR_MAXWM,
2661         ILK_CURSOR_DFTWM,
2662         2,
2663         ILK_FIFO_LINE_SIZE
2664 };
2665
2666 static struct intel_watermark_params ironlake_display_srwm_info = {
2667         ILK_DISPLAY_SR_FIFO,
2668         ILK_DISPLAY_MAX_SRWM,
2669         ILK_DISPLAY_DFT_SRWM,
2670         2,
2671         ILK_FIFO_LINE_SIZE
2672 };
2673
2674 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2675         ILK_CURSOR_SR_FIFO,
2676         ILK_CURSOR_MAX_SRWM,
2677         ILK_CURSOR_DFT_SRWM,
2678         2,
2679         ILK_FIFO_LINE_SIZE
2680 };
2681
2682 /**
2683  * intel_calculate_wm - calculate watermark level
2684  * @clock_in_khz: pixel clock
2685  * @wm: chip FIFO params
2686  * @pixel_size: display pixel size
2687  * @latency_ns: memory latency for the platform
2688  *
2689  * Calculate the watermark level (the level at which the display plane will
2690  * start fetching from memory again).  Each chip has a different display
2691  * FIFO size and allocation, so the caller needs to figure that out and pass
2692  * in the correct intel_watermark_params structure.
2693  *
2694  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2695  * on the pixel size.  When it reaches the watermark level, it'll start
2696  * fetching FIFO line sized based chunks from memory until the FIFO fills
2697  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2698  * will occur, and a display engine hang could result.
2699  */
2700 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2701                                         struct intel_watermark_params *wm,
2702                                         int pixel_size,
2703                                         unsigned long latency_ns)
2704 {
2705         long entries_required, wm_size;
2706
2707         /*
2708          * Note: we need to make sure we don't overflow for various clock &
2709          * latency values.
2710          * clocks go from a few thousand to several hundred thousand.
2711          * latency is usually a few thousand
2712          */
2713         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2714                 1000;
2715         entries_required /= wm->cacheline_size;
2716
2717         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2718
2719         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2720
2721         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2722
2723         /* Don't promote wm_size to unsigned... */
2724         if (wm_size > (long)wm->max_wm)
2725                 wm_size = wm->max_wm;
2726         if (wm_size <= 0)
2727                 wm_size = wm->default_wm;
2728         return wm_size;
2729 }
2730
2731 struct cxsr_latency {
2732         int is_desktop;
2733         int is_ddr3;
2734         unsigned long fsb_freq;
2735         unsigned long mem_freq;
2736         unsigned long display_sr;
2737         unsigned long display_hpll_disable;
2738         unsigned long cursor_sr;
2739         unsigned long cursor_hpll_disable;
2740 };
2741
2742 static struct cxsr_latency cxsr_latency_table[] = {
2743         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2744         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2745         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2746         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2747         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2748
2749         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2750         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2751         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2752         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2753         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2754
2755         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2756         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2757         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2758         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2759         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2760
2761         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2762         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2763         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2764         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2765         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2766
2767         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2768         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2769         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2770         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2771         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2772
2773         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2774         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2775         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2776         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2777         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2778 };
2779
2780 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2781                                                    int fsb, int mem)
2782 {
2783         int i;
2784         struct cxsr_latency *latency;
2785
2786         if (fsb == 0 || mem == 0)
2787                 return NULL;
2788
2789         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2790                 latency = &cxsr_latency_table[i];
2791                 if (is_desktop == latency->is_desktop &&
2792                     is_ddr3 == latency->is_ddr3 &&
2793                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2794                         return latency;
2795         }
2796
2797         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2798
2799         return NULL;
2800 }
2801
2802 static void pineview_disable_cxsr(struct drm_device *dev)
2803 {
2804         struct drm_i915_private *dev_priv = dev->dev_private;
2805         u32 reg;
2806
2807         /* deactivate cxsr */
2808         reg = I915_READ(DSPFW3);
2809         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2810         I915_WRITE(DSPFW3, reg);
2811         DRM_INFO("Big FIFO is disabled\n");
2812 }
2813
2814 /*
2815  * Latency for FIFO fetches is dependent on several factors:
2816  *   - memory configuration (speed, channels)
2817  *   - chipset
2818  *   - current MCH state
2819  * It can be fairly high in some situations, so here we assume a fairly
2820  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2821  * set this value too high, the FIFO will fetch frequently to stay full)
2822  * and power consumption (set it too low to save power and we might see
2823  * FIFO underruns and display "flicker").
2824  *
2825  * A value of 5us seems to be a good balance; safe for very low end
2826  * platforms but not overly aggressive on lower latency configs.
2827  */
2828 static const int latency_ns = 5000;
2829
2830 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2831 {
2832         struct drm_i915_private *dev_priv = dev->dev_private;
2833         uint32_t dsparb = I915_READ(DSPARB);
2834         int size;
2835
2836         if (plane == 0)
2837                 size = dsparb & 0x7f;
2838         else
2839                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2840                         (dsparb & 0x7f);
2841
2842         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2843                         plane ? "B" : "A", size);
2844
2845         return size;
2846 }
2847
2848 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2849 {
2850         struct drm_i915_private *dev_priv = dev->dev_private;
2851         uint32_t dsparb = I915_READ(DSPARB);
2852         int size;
2853
2854         if (plane == 0)
2855                 size = dsparb & 0x1ff;
2856         else
2857                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2858                         (dsparb & 0x1ff);
2859         size >>= 1; /* Convert to cachelines */
2860
2861         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2862                         plane ? "B" : "A", size);
2863
2864         return size;
2865 }
2866
2867 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2868 {
2869         struct drm_i915_private *dev_priv = dev->dev_private;
2870         uint32_t dsparb = I915_READ(DSPARB);
2871         int size;
2872
2873         size = dsparb & 0x7f;
2874         size >>= 2; /* Convert to cachelines */
2875
2876         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2877                         plane ? "B" : "A",
2878                   size);
2879
2880         return size;
2881 }
2882
2883 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2884 {
2885         struct drm_i915_private *dev_priv = dev->dev_private;
2886         uint32_t dsparb = I915_READ(DSPARB);
2887         int size;
2888
2889         size = dsparb & 0x7f;
2890         size >>= 1; /* Convert to cachelines */
2891
2892         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2893                         plane ? "B" : "A", size);
2894
2895         return size;
2896 }
2897
2898 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2899                           int planeb_clock, int sr_hdisplay, int unused,
2900                           int pixel_size)
2901 {
2902         struct drm_i915_private *dev_priv = dev->dev_private;
2903         u32 reg;
2904         unsigned long wm;
2905         struct cxsr_latency *latency;
2906         int sr_clock;
2907
2908         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2909                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2910         if (!latency) {
2911                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2912                 pineview_disable_cxsr(dev);
2913                 return;
2914         }
2915
2916         if (!planea_clock || !planeb_clock) {
2917                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2918
2919                 /* Display SR */
2920                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2921                                         pixel_size, latency->display_sr);
2922                 reg = I915_READ(DSPFW1);
2923                 reg &= ~DSPFW_SR_MASK;
2924                 reg |= wm << DSPFW_SR_SHIFT;
2925                 I915_WRITE(DSPFW1, reg);
2926                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2927
2928                 /* cursor SR */
2929                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2930                                         pixel_size, latency->cursor_sr);
2931                 reg = I915_READ(DSPFW3);
2932                 reg &= ~DSPFW_CURSOR_SR_MASK;
2933                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2934                 I915_WRITE(DSPFW3, reg);
2935
2936                 /* Display HPLL off SR */
2937                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2938                                         pixel_size, latency->display_hpll_disable);
2939                 reg = I915_READ(DSPFW3);
2940                 reg &= ~DSPFW_HPLL_SR_MASK;
2941                 reg |= wm & DSPFW_HPLL_SR_MASK;
2942                 I915_WRITE(DSPFW3, reg);
2943
2944                 /* cursor HPLL off SR */
2945                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2946                                         pixel_size, latency->cursor_hpll_disable);
2947                 reg = I915_READ(DSPFW3);
2948                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2949                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2950                 I915_WRITE(DSPFW3, reg);
2951                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2952
2953                 /* activate cxsr */
2954                 reg = I915_READ(DSPFW3);
2955                 reg |= PINEVIEW_SELF_REFRESH_EN;
2956                 I915_WRITE(DSPFW3, reg);
2957                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2958         } else {
2959                 pineview_disable_cxsr(dev);
2960                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2961         }
2962 }
2963
2964 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2965                           int planeb_clock, int sr_hdisplay, int sr_htotal,
2966                           int pixel_size)
2967 {
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         int total_size, cacheline_size;
2970         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2971         struct intel_watermark_params planea_params, planeb_params;
2972         unsigned long line_time_us;
2973         int sr_clock, sr_entries = 0, entries_required;
2974
2975         /* Create copies of the base settings for each pipe */
2976         planea_params = planeb_params = g4x_wm_info;
2977
2978         /* Grab a couple of global values before we overwrite them */
2979         total_size = planea_params.fifo_size;
2980         cacheline_size = planea_params.cacheline_size;
2981
2982         /*
2983          * Note: we need to make sure we don't overflow for various clock &
2984          * latency values.
2985          * clocks go from a few thousand to several hundred thousand.
2986          * latency is usually a few thousand
2987          */
2988         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2989                 1000;
2990         entries_required /= G4X_FIFO_LINE_SIZE;
2991         planea_wm = entries_required + planea_params.guard_size;
2992
2993         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2994                 1000;
2995         entries_required /= G4X_FIFO_LINE_SIZE;
2996         planeb_wm = entries_required + planeb_params.guard_size;
2997
2998         cursora_wm = cursorb_wm = 16;
2999         cursor_sr = 32;
3000
3001         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3002
3003         /* Calc sr entries for one plane configs */
3004         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3005                 /* self-refresh has much higher latency */
3006                 static const int sr_latency_ns = 12000;
3007
3008                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3009                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3010
3011                 /* Use ns/us then divide to preserve precision */
3012                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3013                               pixel_size * sr_hdisplay;
3014                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3015
3016                 entries_required = (((sr_latency_ns / line_time_us) +
3017                                      1000) / 1000) * pixel_size * 64;
3018                 entries_required = roundup(entries_required /
3019                                            g4x_cursor_wm_info.cacheline_size, 1);
3020                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3021
3022                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3023                         cursor_sr = g4x_cursor_wm_info.max_wm;
3024                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3025                               "cursor %d\n", sr_entries, cursor_sr);
3026
3027                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3028         } else {
3029                 /* Turn off self refresh if both pipes are enabled */
3030                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3031                                         & ~FW_BLC_SELF_EN);
3032         }
3033
3034         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3035                   planea_wm, planeb_wm, sr_entries);
3036
3037         planea_wm &= 0x3f;
3038         planeb_wm &= 0x3f;
3039
3040         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3041                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3042                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3043         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3044                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3045         /* HPLL off in SR has some issues on G4x... disable it */
3046         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3047                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3048 }
3049
3050 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3051                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3052                            int pixel_size)
3053 {
3054         struct drm_i915_private *dev_priv = dev->dev_private;
3055         unsigned long line_time_us;
3056         int sr_clock, sr_entries, srwm = 1;
3057         int cursor_sr = 16;
3058
3059         /* Calc sr entries for one plane configs */
3060         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3061                 /* self-refresh has much higher latency */
3062                 static const int sr_latency_ns = 12000;
3063
3064                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3065                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3066
3067                 /* Use ns/us then divide to preserve precision */
3068                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3069                               pixel_size * sr_hdisplay;
3070                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
3071                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3072                 srwm = I965_FIFO_SIZE - sr_entries;
3073                 if (srwm < 0)
3074                         srwm = 1;
3075                 srwm &= 0x1ff;
3076
3077                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3078                              pixel_size * 64;
3079                 sr_entries = roundup(sr_entries /
3080                                      i965_cursor_wm_info.cacheline_size, 1);
3081                 cursor_sr = i965_cursor_wm_info.fifo_size -
3082                             (sr_entries + i965_cursor_wm_info.guard_size);
3083
3084                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3085                         cursor_sr = i965_cursor_wm_info.max_wm;
3086
3087                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3088                               "cursor %d\n", srwm, cursor_sr);
3089
3090                 if (IS_I965GM(dev))
3091                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3092         } else {
3093                 /* Turn off self refresh if both pipes are enabled */
3094                 if (IS_I965GM(dev))
3095                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3096                                    & ~FW_BLC_SELF_EN);
3097         }
3098
3099         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3100                       srwm);
3101
3102         /* 965 has limitations... */
3103         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3104                    (8 << 0));
3105         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3106         /* update cursor SR watermark */
3107         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3108 }
3109
3110 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3111                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3112                            int pixel_size)
3113 {
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         uint32_t fwater_lo;
3116         uint32_t fwater_hi;
3117         int total_size, cacheline_size, cwm, srwm = 1;
3118         int planea_wm, planeb_wm;
3119         struct intel_watermark_params planea_params, planeb_params;
3120         unsigned long line_time_us;
3121         int sr_clock, sr_entries = 0;
3122
3123         /* Create copies of the base settings for each pipe */
3124         if (IS_I965GM(dev) || IS_I945GM(dev))
3125                 planea_params = planeb_params = i945_wm_info;
3126         else if (IS_I9XX(dev))
3127                 planea_params = planeb_params = i915_wm_info;
3128         else
3129                 planea_params = planeb_params = i855_wm_info;
3130
3131         /* Grab a couple of global values before we overwrite them */
3132         total_size = planea_params.fifo_size;
3133         cacheline_size = planea_params.cacheline_size;
3134
3135         /* Update per-plane FIFO sizes */
3136         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3137         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3138
3139         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3140                                        pixel_size, latency_ns);
3141         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3142                                        pixel_size, latency_ns);
3143         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3144
3145         /*
3146          * Overlay gets an aggressive default since video jitter is bad.
3147          */
3148         cwm = 2;
3149
3150         /* Calc sr entries for one plane configs */
3151         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3152             (!planea_clock || !planeb_clock)) {
3153                 /* self-refresh has much higher latency */
3154                 static const int sr_latency_ns = 6000;
3155
3156                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3157                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3158
3159                 /* Use ns/us then divide to preserve precision */
3160                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3161                               pixel_size * sr_hdisplay;
3162                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3163                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3164                 srwm = total_size - sr_entries;
3165                 if (srwm < 0)
3166                         srwm = 1;
3167
3168                 if (IS_I945G(dev) || IS_I945GM(dev))
3169                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3170                 else if (IS_I915GM(dev)) {
3171                         /* 915M has a smaller SRWM field */
3172                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3173                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3174                 }
3175         } else {
3176                 /* Turn off self refresh if both pipes are enabled */
3177                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3178                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3179                                    & ~FW_BLC_SELF_EN);
3180                 } else if (IS_I915GM(dev)) {
3181                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3182                 }
3183         }
3184
3185         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3186                   planea_wm, planeb_wm, cwm, srwm);
3187
3188         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3189         fwater_hi = (cwm & 0x1f);
3190
3191         /* Set request length to 8 cachelines per fetch */
3192         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3193         fwater_hi = fwater_hi | (1 << 8);
3194
3195         I915_WRITE(FW_BLC, fwater_lo);
3196         I915_WRITE(FW_BLC2, fwater_hi);
3197 }
3198
3199 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3200                            int unused2, int unused3, int pixel_size)
3201 {
3202         struct drm_i915_private *dev_priv = dev->dev_private;
3203         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3204         int planea_wm;
3205
3206         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3207
3208         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3209                                        pixel_size, latency_ns);
3210         fwater_lo |= (3<<8) | planea_wm;
3211
3212         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3213
3214         I915_WRITE(FW_BLC, fwater_lo);
3215 }
3216
3217 #define ILK_LP0_PLANE_LATENCY           700
3218 #define ILK_LP0_CURSOR_LATENCY          1300
3219
3220 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3221                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3222                        int pixel_size)
3223 {
3224         struct drm_i915_private *dev_priv = dev->dev_private;
3225         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3226         int sr_wm, cursor_wm;
3227         unsigned long line_time_us;
3228         int sr_clock, entries_required;
3229         u32 reg_value;
3230         int line_count;
3231         int planea_htotal = 0, planeb_htotal = 0;
3232         struct drm_crtc *crtc;
3233         struct intel_crtc *intel_crtc;
3234
3235         /* Need htotal for all active display plane */
3236         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3237                 intel_crtc = to_intel_crtc(crtc);
3238                 if (crtc->enabled) {
3239                         if (intel_crtc->plane == 0)
3240                                 planea_htotal = crtc->mode.htotal;
3241                         else
3242                                 planeb_htotal = crtc->mode.htotal;
3243                 }
3244         }
3245
3246         /* Calculate and update the watermark for plane A */
3247         if (planea_clock) {
3248                 entries_required = ((planea_clock / 1000) * pixel_size *
3249                                      ILK_LP0_PLANE_LATENCY) / 1000;
3250                 entries_required = DIV_ROUND_UP(entries_required,
3251                                    ironlake_display_wm_info.cacheline_size);
3252                 planea_wm = entries_required +
3253                             ironlake_display_wm_info.guard_size;
3254
3255                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3256                         planea_wm = ironlake_display_wm_info.max_wm;
3257
3258                 /* Use the large buffer method to calculate cursor watermark */
3259                 line_time_us = (planea_htotal * 1000) / planea_clock;
3260
3261                 /* Use ns/us then divide to preserve precision */
3262                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3263
3264                 /* calculate the cursor watermark for cursor A */
3265                 entries_required = line_count * 64 * pixel_size;
3266                 entries_required = DIV_ROUND_UP(entries_required,
3267                                                 ironlake_cursor_wm_info.cacheline_size);
3268                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3269                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3270                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3271
3272                 reg_value = I915_READ(WM0_PIPEA_ILK);
3273                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3274                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3275                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3276                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3277                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3278                                 "cursor: %d\n", planea_wm, cursora_wm);
3279         }
3280         /* Calculate and update the watermark for plane B */
3281         if (planeb_clock) {
3282                 entries_required = ((planeb_clock / 1000) * pixel_size *
3283                                      ILK_LP0_PLANE_LATENCY) / 1000;
3284                 entries_required = DIV_ROUND_UP(entries_required,
3285                                    ironlake_display_wm_info.cacheline_size);
3286                 planeb_wm = entries_required +
3287                             ironlake_display_wm_info.guard_size;
3288
3289                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3290                         planeb_wm = ironlake_display_wm_info.max_wm;
3291
3292                 /* Use the large buffer method to calculate cursor watermark */
3293                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3294
3295                 /* Use ns/us then divide to preserve precision */
3296                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3297
3298                 /* calculate the cursor watermark for cursor B */
3299                 entries_required = line_count * 64 * pixel_size;
3300                 entries_required = DIV_ROUND_UP(entries_required,
3301                                                 ironlake_cursor_wm_info.cacheline_size);
3302                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3303                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3304                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3305
3306                 reg_value = I915_READ(WM0_PIPEB_ILK);
3307                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3308                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3309                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3310                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3311                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3312                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3313         }
3314
3315         /*
3316          * Calculate and update the self-refresh watermark only when one
3317          * display plane is used.
3318          */
3319         if (!planea_clock || !planeb_clock) {
3320
3321                 /* Read the self-refresh latency. The unit is 0.5us */
3322                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3323
3324                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3325                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3326
3327                 /* Use ns/us then divide to preserve precision */
3328                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3329                                / 1000;
3330
3331                 /* calculate the self-refresh watermark for display plane */
3332                 entries_required = line_count * sr_hdisplay * pixel_size;
3333                 entries_required = DIV_ROUND_UP(entries_required,
3334                                    ironlake_display_srwm_info.cacheline_size);
3335                 sr_wm = entries_required +
3336                         ironlake_display_srwm_info.guard_size;
3337
3338                 /* calculate the self-refresh watermark for display cursor */
3339                 entries_required = line_count * pixel_size * 64;
3340                 entries_required = DIV_ROUND_UP(entries_required,
3341                                    ironlake_cursor_srwm_info.cacheline_size);
3342                 cursor_wm = entries_required +
3343                             ironlake_cursor_srwm_info.guard_size;
3344
3345                 /* configure watermark and enable self-refresh */
3346                 reg_value = I915_READ(WM1_LP_ILK);
3347                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3348                                WM1_LP_CURSOR_MASK);
3349                 reg_value |= WM1_LP_SR_EN |
3350                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3351                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3352
3353                 I915_WRITE(WM1_LP_ILK, reg_value);
3354                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3355                                 "cursor %d\n", sr_wm, cursor_wm);
3356
3357         } else {
3358                 /* Turn off self refresh if both pipes are enabled */
3359                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3360         }
3361 }
3362 /**
3363  * intel_update_watermarks - update FIFO watermark values based on current modes
3364  *
3365  * Calculate watermark values for the various WM regs based on current mode
3366  * and plane configuration.
3367  *
3368  * There are several cases to deal with here:
3369  *   - normal (i.e. non-self-refresh)
3370  *   - self-refresh (SR) mode
3371  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3372  *   - lines are small relative to FIFO size (buffer can hold more than 2
3373  *     lines), so need to account for TLB latency
3374  *
3375  *   The normal calculation is:
3376  *     watermark = dotclock * bytes per pixel * latency
3377  *   where latency is platform & configuration dependent (we assume pessimal
3378  *   values here).
3379  *
3380  *   The SR calculation is:
3381  *     watermark = (trunc(latency/line time)+1) * surface width *
3382  *       bytes per pixel
3383  *   where
3384  *     line time = htotal / dotclock
3385  *     surface width = hdisplay for normal plane and 64 for cursor
3386  *   and latency is assumed to be high, as above.
3387  *
3388  * The final value programmed to the register should always be rounded up,
3389  * and include an extra 2 entries to account for clock crossings.
3390  *
3391  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3392  * to set the non-SR watermarks to 8.
3393   */
3394 static void intel_update_watermarks(struct drm_device *dev)
3395 {
3396         struct drm_i915_private *dev_priv = dev->dev_private;
3397         struct drm_crtc *crtc;
3398         struct intel_crtc *intel_crtc;
3399         int sr_hdisplay = 0;
3400         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3401         int enabled = 0, pixel_size = 0;
3402         int sr_htotal = 0;
3403
3404         if (!dev_priv->display.update_wm)
3405                 return;
3406
3407         /* Get the clock config from both planes */
3408         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3409                 intel_crtc = to_intel_crtc(crtc);
3410                 if (crtc->enabled) {
3411                         enabled++;
3412                         if (intel_crtc->plane == 0) {
3413                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3414                                           intel_crtc->pipe, crtc->mode.clock);
3415                                 planea_clock = crtc->mode.clock;
3416                         } else {
3417                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3418                                           intel_crtc->pipe, crtc->mode.clock);
3419                                 planeb_clock = crtc->mode.clock;
3420                         }
3421                         sr_hdisplay = crtc->mode.hdisplay;
3422                         sr_clock = crtc->mode.clock;
3423                         sr_htotal = crtc->mode.htotal;
3424                         if (crtc->fb)
3425                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3426                         else
3427                                 pixel_size = 4; /* by default */
3428                 }
3429         }
3430
3431         if (enabled <= 0)
3432                 return;
3433
3434         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3435                                     sr_hdisplay, sr_htotal, pixel_size);
3436 }
3437
3438 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3439                                struct drm_display_mode *mode,
3440                                struct drm_display_mode *adjusted_mode,
3441                                int x, int y,
3442                                struct drm_framebuffer *old_fb)
3443 {
3444         struct drm_device *dev = crtc->dev;
3445         struct drm_i915_private *dev_priv = dev->dev_private;
3446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3447         int pipe = intel_crtc->pipe;
3448         int plane = intel_crtc->plane;
3449         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3450         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3451         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3452         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3453         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3454         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3455         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3456         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3457         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3458         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3459         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3460         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3461         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3462         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3463         int refclk, num_connectors = 0;
3464         intel_clock_t clock, reduced_clock;
3465         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3466         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3467         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3468         bool is_edp = false;
3469         struct drm_mode_config *mode_config = &dev->mode_config;
3470         struct drm_encoder *encoder;
3471         struct intel_encoder *intel_encoder = NULL;
3472         const intel_limit_t *limit;
3473         int ret;
3474         struct fdi_m_n m_n = {0};
3475         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3476         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3477         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3478         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3479         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3480         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3481         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3482         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3483         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3484         int lvds_reg = LVDS;
3485         u32 temp;
3486         int sdvo_pixel_multiply;
3487         int target_clock;
3488
3489         drm_vblank_pre_modeset(dev, pipe);
3490
3491         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3492
3493                 if (!encoder || encoder->crtc != crtc)
3494                         continue;
3495
3496                 intel_encoder = enc_to_intel_encoder(encoder);
3497
3498                 switch (intel_encoder->type) {
3499                 case INTEL_OUTPUT_LVDS:
3500                         is_lvds = true;
3501                         break;
3502                 case INTEL_OUTPUT_SDVO:
3503                 case INTEL_OUTPUT_HDMI:
3504                         is_sdvo = true;
3505                         if (intel_encoder->needs_tv_clock)
3506                                 is_tv = true;
3507                         break;
3508                 case INTEL_OUTPUT_DVO:
3509                         is_dvo = true;
3510                         break;
3511                 case INTEL_OUTPUT_TVOUT:
3512                         is_tv = true;
3513                         break;
3514                 case INTEL_OUTPUT_ANALOG:
3515                         is_crt = true;
3516                         break;
3517                 case INTEL_OUTPUT_DISPLAYPORT:
3518                         is_dp = true;
3519                         break;
3520                 case INTEL_OUTPUT_EDP:
3521                         is_edp = true;
3522                         break;
3523                 }
3524
3525                 num_connectors++;
3526         }
3527
3528         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3529                 refclk = dev_priv->lvds_ssc_freq * 1000;
3530                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3531                                         refclk / 1000);
3532         } else if (IS_I9XX(dev)) {
3533                 refclk = 96000;
3534                 if (HAS_PCH_SPLIT(dev))
3535                         refclk = 120000; /* 120Mhz refclk */
3536         } else {
3537                 refclk = 48000;
3538         }
3539
3540
3541         /*
3542          * Returns a set of divisors for the desired target clock with the given
3543          * refclk, or FALSE.  The returned values represent the clock equation:
3544          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3545          */
3546         limit = intel_limit(crtc);
3547         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3548         if (!ok) {
3549                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3550                 drm_vblank_post_modeset(dev, pipe);
3551                 return -EINVAL;
3552         }
3553
3554         if (is_lvds && dev_priv->lvds_downclock_avail) {
3555                 has_reduced_clock = limit->find_pll(limit, crtc,
3556                                                             dev_priv->lvds_downclock,
3557                                                             refclk,
3558                                                             &reduced_clock);
3559                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3560                         /*
3561                          * If the different P is found, it means that we can't
3562                          * switch the display clock by using the FP0/FP1.
3563                          * In such case we will disable the LVDS downclock
3564                          * feature.
3565                          */
3566                         DRM_DEBUG_KMS("Different P is found for "
3567                                                 "LVDS clock/downclock\n");
3568                         has_reduced_clock = 0;
3569                 }
3570         }
3571         /* SDVO TV has fixed PLL values depend on its clock range,
3572            this mirrors vbios setting. */
3573         if (is_sdvo && is_tv) {
3574                 if (adjusted_mode->clock >= 100000
3575                                 && adjusted_mode->clock < 140500) {
3576                         clock.p1 = 2;
3577                         clock.p2 = 10;
3578                         clock.n = 3;
3579                         clock.m1 = 16;
3580                         clock.m2 = 8;
3581                 } else if (adjusted_mode->clock >= 140500
3582                                 && adjusted_mode->clock <= 200000) {
3583                         clock.p1 = 1;
3584                         clock.p2 = 10;
3585                         clock.n = 6;
3586                         clock.m1 = 12;
3587                         clock.m2 = 8;
3588                 }
3589         }
3590
3591         /* FDI link */
3592         if (HAS_PCH_SPLIT(dev)) {
3593                 int lane = 0, link_bw, bpp;
3594                 /* eDP doesn't require FDI link, so just set DP M/N
3595                    according to current link config */
3596                 if (is_edp) {
3597                         target_clock = mode->clock;
3598                         intel_edp_link_config(intel_encoder,
3599                                         &lane, &link_bw);
3600                 } else {
3601                         /* DP over FDI requires target mode clock
3602                            instead of link clock */
3603                         if (is_dp)
3604                                 target_clock = mode->clock;
3605                         else
3606                                 target_clock = adjusted_mode->clock;
3607                         link_bw = 270000;
3608                 }
3609
3610                 /* determine panel color depth */
3611                 temp = I915_READ(pipeconf_reg);
3612                 temp &= ~PIPE_BPC_MASK;
3613                 if (is_lvds) {
3614                         int lvds_reg = I915_READ(PCH_LVDS);
3615                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3616                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3617                                 temp |= PIPE_8BPC;
3618                         else
3619                                 temp |= PIPE_6BPC;
3620                 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3621                         switch (dev_priv->edp_bpp/3) {
3622                         case 8:
3623                                 temp |= PIPE_8BPC;
3624                                 break;
3625                         case 10:
3626                                 temp |= PIPE_10BPC;
3627                                 break;
3628                         case 6:
3629                                 temp |= PIPE_6BPC;
3630                                 break;
3631                         case 12:
3632                                 temp |= PIPE_12BPC;
3633                                 break;
3634                         }
3635                 } else
3636                         temp |= PIPE_8BPC;
3637                 I915_WRITE(pipeconf_reg, temp);
3638                 I915_READ(pipeconf_reg);
3639
3640                 switch (temp & PIPE_BPC_MASK) {
3641                 case PIPE_8BPC:
3642                         bpp = 24;
3643                         break;
3644                 case PIPE_10BPC:
3645                         bpp = 30;
3646                         break;
3647                 case PIPE_6BPC:
3648                         bpp = 18;
3649                         break;
3650                 case PIPE_12BPC:
3651                         bpp = 36;
3652                         break;
3653                 default:
3654                         DRM_ERROR("unknown pipe bpc value\n");
3655                         bpp = 24;
3656                 }
3657
3658                 if (!lane) {
3659                         /*
3660                          * Account for spread spectrum to avoid
3661                          * oversubscribing the link. Max center spread
3662                          * is 2.5%; use 5% for safety's sake.
3663                          */
3664                         u32 bps = target_clock * bpp * 21 / 20;
3665                         lane = bps / (link_bw * 8) + 1;
3666                 }
3667
3668                 intel_crtc->fdi_lanes = lane;
3669
3670                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3671         }
3672
3673         /* Ironlake: try to setup display ref clock before DPLL
3674          * enabling. This is only under driver's control after
3675          * PCH B stepping, previous chipset stepping should be
3676          * ignoring this setting.
3677          */
3678         if (HAS_PCH_SPLIT(dev)) {
3679                 temp = I915_READ(PCH_DREF_CONTROL);
3680                 /* Always enable nonspread source */
3681                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3682                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3683                 I915_WRITE(PCH_DREF_CONTROL, temp);
3684                 POSTING_READ(PCH_DREF_CONTROL);
3685
3686                 temp &= ~DREF_SSC_SOURCE_MASK;
3687                 temp |= DREF_SSC_SOURCE_ENABLE;
3688                 I915_WRITE(PCH_DREF_CONTROL, temp);
3689                 POSTING_READ(PCH_DREF_CONTROL);
3690
3691                 udelay(200);
3692
3693                 if (is_edp) {
3694                         if (dev_priv->lvds_use_ssc) {
3695                                 temp |= DREF_SSC1_ENABLE;
3696                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3697                                 POSTING_READ(PCH_DREF_CONTROL);
3698
3699                                 udelay(200);
3700
3701                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3702                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3703                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3704                                 POSTING_READ(PCH_DREF_CONTROL);
3705                         } else {
3706                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3707                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3708                                 POSTING_READ(PCH_DREF_CONTROL);
3709                         }
3710                 }
3711         }
3712
3713         if (IS_PINEVIEW(dev)) {
3714                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3715                 if (has_reduced_clock)
3716                         fp2 = (1 << reduced_clock.n) << 16 |
3717                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3718         } else {
3719                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3720                 if (has_reduced_clock)
3721                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3722                                 reduced_clock.m2;
3723         }
3724
3725         if (!HAS_PCH_SPLIT(dev))
3726                 dpll = DPLL_VGA_MODE_DIS;
3727
3728         if (IS_I9XX(dev)) {
3729                 if (is_lvds)
3730                         dpll |= DPLLB_MODE_LVDS;
3731                 else
3732                         dpll |= DPLLB_MODE_DAC_SERIAL;
3733                 if (is_sdvo) {
3734                         dpll |= DPLL_DVO_HIGH_SPEED;
3735                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3736                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3737                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3738                         else if (HAS_PCH_SPLIT(dev))
3739                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3740                 }
3741                 if (is_dp)
3742                         dpll |= DPLL_DVO_HIGH_SPEED;
3743
3744                 /* compute bitmask from p1 value */
3745                 if (IS_PINEVIEW(dev))
3746                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3747                 else {
3748                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3749                         /* also FPA1 */
3750                         if (HAS_PCH_SPLIT(dev))
3751                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3752                         if (IS_G4X(dev) && has_reduced_clock)
3753                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3754                 }
3755                 switch (clock.p2) {
3756                 case 5:
3757                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3758                         break;
3759                 case 7:
3760                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3761                         break;
3762                 case 10:
3763                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3764                         break;
3765                 case 14:
3766                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3767                         break;
3768                 }
3769                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3770                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3771         } else {
3772                 if (is_lvds) {
3773                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3774                 } else {
3775                         if (clock.p1 == 2)
3776                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3777                         else
3778                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3779                         if (clock.p2 == 4)
3780                                 dpll |= PLL_P2_DIVIDE_BY_4;
3781                 }
3782         }
3783
3784         if (is_sdvo && is_tv)
3785                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3786         else if (is_tv)
3787                 /* XXX: just matching BIOS for now */
3788                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3789                 dpll |= 3;
3790         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3791                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3792         else
3793                 dpll |= PLL_REF_INPUT_DREFCLK;
3794
3795         /* setup pipeconf */
3796         pipeconf = I915_READ(pipeconf_reg);
3797
3798         /* Set up the display plane register */
3799         dspcntr = DISPPLANE_GAMMA_ENABLE;
3800
3801         /* Ironlake's plane is forced to pipe, bit 24 is to
3802            enable color space conversion */
3803         if (!HAS_PCH_SPLIT(dev)) {
3804                 if (pipe == 0)
3805                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3806                 else
3807                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3808         }
3809
3810         if (pipe == 0 && !IS_I965G(dev)) {
3811                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3812                  * core speed.
3813                  *
3814                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3815                  * pipe == 0 check?
3816                  */
3817                 if (mode->clock >
3818                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3819                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3820                 else
3821                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3822         }
3823
3824         dspcntr |= DISPLAY_PLANE_ENABLE;
3825         pipeconf |= PIPEACONF_ENABLE;
3826         dpll |= DPLL_VCO_ENABLE;
3827
3828
3829         /* Disable the panel fitter if it was on our pipe */
3830         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3831                 I915_WRITE(PFIT_CONTROL, 0);
3832
3833         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3834         drm_mode_debug_printmodeline(mode);
3835
3836         /* assign to Ironlake registers */
3837         if (HAS_PCH_SPLIT(dev)) {
3838                 fp_reg = pch_fp_reg;
3839                 dpll_reg = pch_dpll_reg;
3840         }
3841
3842         if (is_edp) {
3843                 ironlake_disable_pll_edp(crtc);
3844         } else if ((dpll & DPLL_VCO_ENABLE)) {
3845                 I915_WRITE(fp_reg, fp);
3846                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3847                 I915_READ(dpll_reg);
3848                 udelay(150);
3849         }
3850
3851         /* enable transcoder DPLL */
3852         if (HAS_PCH_CPT(dev)) {
3853                 temp = I915_READ(PCH_DPLL_SEL);
3854                 if (trans_dpll_sel == 0)
3855                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3856                 else
3857                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3858                 I915_WRITE(PCH_DPLL_SEL, temp);
3859                 I915_READ(PCH_DPLL_SEL);
3860                 udelay(150);
3861         }
3862
3863         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3864          * This is an exception to the general rule that mode_set doesn't turn
3865          * things on.
3866          */
3867         if (is_lvds) {
3868                 u32 lvds;
3869
3870                 if (HAS_PCH_SPLIT(dev))
3871                         lvds_reg = PCH_LVDS;
3872
3873                 lvds = I915_READ(lvds_reg);
3874                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3875                 if (pipe == 1) {
3876                         if (HAS_PCH_CPT(dev))
3877                                 lvds |= PORT_TRANS_B_SEL_CPT;
3878                         else
3879                                 lvds |= LVDS_PIPEB_SELECT;
3880                 } else {
3881                         if (HAS_PCH_CPT(dev))
3882                                 lvds &= ~PORT_TRANS_SEL_MASK;
3883                         else
3884                                 lvds &= ~LVDS_PIPEB_SELECT;
3885                 }
3886                 /* set the corresponsding LVDS_BORDER bit */
3887                 lvds |= dev_priv->lvds_border_bits;
3888                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3889                  * set the DPLLs for dual-channel mode or not.
3890                  */
3891                 if (clock.p2 == 7)
3892                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3893                 else
3894                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3895
3896                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3897                  * appropriately here, but we need to look more thoroughly into how
3898                  * panels behave in the two modes.
3899                  */
3900                 /* set the dithering flag */
3901                 if (IS_I965G(dev)) {
3902                         if (dev_priv->lvds_dither) {
3903                                 if (HAS_PCH_SPLIT(dev)) {
3904                                         pipeconf |= PIPE_ENABLE_DITHER;
3905                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
3906                                 } else
3907                                         lvds |= LVDS_ENABLE_DITHER;
3908                         } else {
3909                                 if (HAS_PCH_SPLIT(dev)) {
3910                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3911                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3912                                 } else
3913                                         lvds &= ~LVDS_ENABLE_DITHER;
3914                         }
3915                 }
3916                 I915_WRITE(lvds_reg, lvds);
3917                 I915_READ(lvds_reg);
3918         }
3919         if (is_dp)
3920                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3921         else if (HAS_PCH_SPLIT(dev)) {
3922                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3923                 if (pipe == 0) {
3924                         I915_WRITE(TRANSA_DATA_M1, 0);
3925                         I915_WRITE(TRANSA_DATA_N1, 0);
3926                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3927                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3928                 } else {
3929                         I915_WRITE(TRANSB_DATA_M1, 0);
3930                         I915_WRITE(TRANSB_DATA_N1, 0);
3931                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3932                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3933                 }
3934         }
3935
3936         if (!is_edp) {
3937                 I915_WRITE(fp_reg, fp);
3938                 I915_WRITE(dpll_reg, dpll);
3939                 I915_READ(dpll_reg);
3940                 /* Wait for the clocks to stabilize. */
3941                 udelay(150);
3942
3943                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3944                         if (is_sdvo) {
3945                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3946                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3947                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3948                         } else
3949                                 I915_WRITE(dpll_md_reg, 0);
3950                 } else {
3951                         /* write it again -- the BIOS does, after all */
3952                         I915_WRITE(dpll_reg, dpll);
3953                 }
3954                 I915_READ(dpll_reg);
3955                 /* Wait for the clocks to stabilize. */
3956                 udelay(150);
3957         }
3958
3959         if (is_lvds && has_reduced_clock && i915_powersave) {
3960                 I915_WRITE(fp_reg + 4, fp2);
3961                 intel_crtc->lowfreq_avail = true;
3962                 if (HAS_PIPE_CXSR(dev)) {
3963                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3964                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3965                 }
3966         } else {
3967                 I915_WRITE(fp_reg + 4, fp);
3968                 intel_crtc->lowfreq_avail = false;
3969                 if (HAS_PIPE_CXSR(dev)) {
3970                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3971                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3972                 }
3973         }
3974
3975         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3976                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3977                 /* the chip adds 2 halflines automatically */
3978                 adjusted_mode->crtc_vdisplay -= 1;
3979                 adjusted_mode->crtc_vtotal -= 1;
3980                 adjusted_mode->crtc_vblank_start -= 1;
3981                 adjusted_mode->crtc_vblank_end -= 1;
3982                 adjusted_mode->crtc_vsync_end -= 1;
3983                 adjusted_mode->crtc_vsync_start -= 1;
3984         } else
3985                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
3986
3987         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3988                    ((adjusted_mode->crtc_htotal - 1) << 16));
3989         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3990                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3991         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3992                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3993         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3994                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3995         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3996                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3997         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3998                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3999         /* pipesrc and dspsize control the size that is scaled from, which should
4000          * always be the user's requested size.
4001          */
4002         if (!HAS_PCH_SPLIT(dev)) {
4003                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4004                                 (mode->hdisplay - 1));
4005                 I915_WRITE(dsppos_reg, 0);
4006         }
4007         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4008
4009         if (HAS_PCH_SPLIT(dev)) {
4010                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4011                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4012                 I915_WRITE(link_m1_reg, m_n.link_m);
4013                 I915_WRITE(link_n1_reg, m_n.link_n);
4014
4015                 if (is_edp) {
4016                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4017                 } else {
4018                         /* enable FDI RX PLL too */
4019                         temp = I915_READ(fdi_rx_reg);
4020                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4021                         I915_READ(fdi_rx_reg);
4022                         udelay(200);
4023
4024                         /* enable FDI TX PLL too */
4025                         temp = I915_READ(fdi_tx_reg);
4026                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4027                         I915_READ(fdi_tx_reg);
4028
4029                         /* enable FDI RX PCDCLK */
4030                         temp = I915_READ(fdi_rx_reg);
4031                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4032                         I915_READ(fdi_rx_reg);
4033                         udelay(200);
4034                 }
4035         }
4036
4037         I915_WRITE(pipeconf_reg, pipeconf);
4038         I915_READ(pipeconf_reg);
4039
4040         intel_wait_for_vblank(dev);
4041
4042         if (IS_IRONLAKE(dev)) {
4043                 /* enable address swizzle for tiling buffer */
4044                 temp = I915_READ(DISP_ARB_CTL);
4045                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4046         }
4047
4048         I915_WRITE(dspcntr_reg, dspcntr);
4049
4050         /* Flush the plane changes */
4051         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4052
4053         if ((IS_I965G(dev) || plane == 0))
4054                 intel_update_fbc(crtc, &crtc->mode);
4055
4056         intel_update_watermarks(dev);
4057
4058         drm_vblank_post_modeset(dev, pipe);
4059
4060         return ret;
4061 }
4062
4063 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4064 void intel_crtc_load_lut(struct drm_crtc *crtc)
4065 {
4066         struct drm_device *dev = crtc->dev;
4067         struct drm_i915_private *dev_priv = dev->dev_private;
4068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4070         int i;
4071
4072         /* The clocks have to be on to load the palette. */
4073         if (!crtc->enabled)
4074                 return;
4075
4076         /* use legacy palette for Ironlake */
4077         if (HAS_PCH_SPLIT(dev))
4078                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4079                                                    LGC_PALETTE_B;
4080
4081         for (i = 0; i < 256; i++) {
4082                 I915_WRITE(palreg + 4 * i,
4083                            (intel_crtc->lut_r[i] << 16) |
4084                            (intel_crtc->lut_g[i] << 8) |
4085                            intel_crtc->lut_b[i]);
4086         }
4087 }
4088
4089 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4090                                  struct drm_file *file_priv,
4091                                  uint32_t handle,
4092                                  uint32_t width, uint32_t height)
4093 {
4094         struct drm_device *dev = crtc->dev;
4095         struct drm_i915_private *dev_priv = dev->dev_private;
4096         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4097         struct drm_gem_object *bo;
4098         struct drm_i915_gem_object *obj_priv;
4099         int pipe = intel_crtc->pipe;
4100         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
4101         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
4102         uint32_t temp = I915_READ(control);
4103         size_t addr;
4104         int ret;
4105
4106         DRM_DEBUG_KMS("\n");
4107
4108         /* if we want to turn off the cursor ignore width and height */
4109         if (!handle) {
4110                 DRM_DEBUG_KMS("cursor off\n");
4111                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4112                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4113                         temp |= CURSOR_MODE_DISABLE;
4114                 } else {
4115                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4116                 }
4117                 addr = 0;
4118                 bo = NULL;
4119                 mutex_lock(&dev->struct_mutex);
4120                 goto finish;
4121         }
4122
4123         /* Currently we only support 64x64 cursors */
4124         if (width != 64 || height != 64) {
4125                 DRM_ERROR("we currently only support 64x64 cursors\n");
4126                 return -EINVAL;
4127         }
4128
4129         bo = drm_gem_object_lookup(dev, file_priv, handle);
4130         if (!bo)
4131                 return -ENOENT;
4132
4133         obj_priv = to_intel_bo(bo);
4134
4135         if (bo->size < width * height * 4) {
4136                 DRM_ERROR("buffer is to small\n");
4137                 ret = -ENOMEM;
4138                 goto fail;
4139         }
4140
4141         /* we only need to pin inside GTT if cursor is non-phy */
4142         mutex_lock(&dev->struct_mutex);
4143         if (!dev_priv->info->cursor_needs_physical) {
4144                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4145                 if (ret) {
4146                         DRM_ERROR("failed to pin cursor bo\n");
4147                         goto fail_locked;
4148                 }
4149
4150                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4151                 if (ret) {
4152                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4153                         goto fail_unpin;
4154                 }
4155
4156                 addr = obj_priv->gtt_offset;
4157         } else {
4158                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4159                 if (ret) {
4160                         DRM_ERROR("failed to attach phys object\n");
4161                         goto fail_locked;
4162                 }
4163                 addr = obj_priv->phys_obj->handle->busaddr;
4164         }
4165
4166         if (!IS_I9XX(dev))
4167                 I915_WRITE(CURSIZE, (height << 12) | width);
4168
4169         /* Hooray for CUR*CNTR differences */
4170         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4171                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4172                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4173                 temp |= (pipe << 28); /* Connect to correct pipe */
4174         } else {
4175                 temp &= ~(CURSOR_FORMAT_MASK);
4176                 temp |= CURSOR_ENABLE;
4177                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4178         }
4179
4180  finish:
4181         I915_WRITE(control, temp);
4182         I915_WRITE(base, addr);
4183
4184         if (intel_crtc->cursor_bo) {
4185                 if (dev_priv->info->cursor_needs_physical) {
4186                         if (intel_crtc->cursor_bo != bo)
4187                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4188                 } else
4189                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4190                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4191         }
4192
4193         mutex_unlock(&dev->struct_mutex);
4194
4195         intel_crtc->cursor_addr = addr;
4196         intel_crtc->cursor_bo = bo;
4197
4198         return 0;
4199 fail_unpin:
4200         i915_gem_object_unpin(bo);
4201 fail_locked:
4202         mutex_unlock(&dev->struct_mutex);
4203 fail:
4204         drm_gem_object_unreference_unlocked(bo);
4205         return ret;
4206 }
4207
4208 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4209 {
4210         struct drm_device *dev = crtc->dev;
4211         struct drm_i915_private *dev_priv = dev->dev_private;
4212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4213         struct intel_framebuffer *intel_fb;
4214         int pipe = intel_crtc->pipe;
4215         uint32_t temp = 0;
4216         uint32_t adder;
4217
4218         if (crtc->fb) {
4219                 intel_fb = to_intel_framebuffer(crtc->fb);
4220                 intel_mark_busy(dev, intel_fb->obj);
4221         }
4222
4223         if (x < 0) {
4224                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4225                 x = -x;
4226         }
4227         if (y < 0) {
4228                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4229                 y = -y;
4230         }
4231
4232         temp |= x << CURSOR_X_SHIFT;
4233         temp |= y << CURSOR_Y_SHIFT;
4234
4235         adder = intel_crtc->cursor_addr;
4236         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4237         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4238
4239         return 0;
4240 }
4241
4242 /** Sets the color ramps on behalf of RandR */
4243 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4244                                  u16 blue, int regno)
4245 {
4246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4247
4248         intel_crtc->lut_r[regno] = red >> 8;
4249         intel_crtc->lut_g[regno] = green >> 8;
4250         intel_crtc->lut_b[regno] = blue >> 8;
4251 }
4252
4253 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4254                              u16 *blue, int regno)
4255 {
4256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4257
4258         *red = intel_crtc->lut_r[regno] << 8;
4259         *green = intel_crtc->lut_g[regno] << 8;
4260         *blue = intel_crtc->lut_b[regno] << 8;
4261 }
4262
4263 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4264                                  u16 *blue, uint32_t size)
4265 {
4266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4267         int i;
4268
4269         if (size != 256)
4270                 return;
4271
4272         for (i = 0; i < 256; i++) {
4273                 intel_crtc->lut_r[i] = red[i] >> 8;
4274                 intel_crtc->lut_g[i] = green[i] >> 8;
4275                 intel_crtc->lut_b[i] = blue[i] >> 8;
4276         }
4277
4278         intel_crtc_load_lut(crtc);
4279 }
4280
4281 /**
4282  * Get a pipe with a simple mode set on it for doing load-based monitor
4283  * detection.
4284  *
4285  * It will be up to the load-detect code to adjust the pipe as appropriate for
4286  * its requirements.  The pipe will be connected to no other encoders.
4287  *
4288  * Currently this code will only succeed if there is a pipe with no encoders
4289  * configured for it.  In the future, it could choose to temporarily disable
4290  * some outputs to free up a pipe for its use.
4291  *
4292  * \return crtc, or NULL if no pipes are available.
4293  */
4294
4295 /* VESA 640x480x72Hz mode to set on the pipe */
4296 static struct drm_display_mode load_detect_mode = {
4297         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4298                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4299 };
4300
4301 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4302                                             struct drm_connector *connector,
4303                                             struct drm_display_mode *mode,
4304                                             int *dpms_mode)
4305 {
4306         struct intel_crtc *intel_crtc;
4307         struct drm_crtc *possible_crtc;
4308         struct drm_crtc *supported_crtc =NULL;
4309         struct drm_encoder *encoder = &intel_encoder->enc;
4310         struct drm_crtc *crtc = NULL;
4311         struct drm_device *dev = encoder->dev;
4312         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4313         struct drm_crtc_helper_funcs *crtc_funcs;
4314         int i = -1;
4315
4316         /*
4317          * Algorithm gets a little messy:
4318          *   - if the connector already has an assigned crtc, use it (but make
4319          *     sure it's on first)
4320          *   - try to find the first unused crtc that can drive this connector,
4321          *     and use that if we find one
4322          *   - if there are no unused crtcs available, try to use the first
4323          *     one we found that supports the connector
4324          */
4325
4326         /* See if we already have a CRTC for this connector */
4327         if (encoder->crtc) {
4328                 crtc = encoder->crtc;
4329                 /* Make sure the crtc and connector are running */
4330                 intel_crtc = to_intel_crtc(crtc);
4331                 *dpms_mode = intel_crtc->dpms_mode;
4332                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4333                         crtc_funcs = crtc->helper_private;
4334                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4335                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4336                 }
4337                 return crtc;
4338         }
4339
4340         /* Find an unused one (if possible) */
4341         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4342                 i++;
4343                 if (!(encoder->possible_crtcs & (1 << i)))
4344                         continue;
4345                 if (!possible_crtc->enabled) {
4346                         crtc = possible_crtc;
4347                         break;
4348                 }
4349                 if (!supported_crtc)
4350                         supported_crtc = possible_crtc;
4351         }
4352
4353         /*
4354          * If we didn't find an unused CRTC, don't use any.
4355          */
4356         if (!crtc) {
4357                 return NULL;
4358         }
4359
4360         encoder->crtc = crtc;
4361         connector->encoder = encoder;
4362         intel_encoder->load_detect_temp = true;
4363
4364         intel_crtc = to_intel_crtc(crtc);
4365         *dpms_mode = intel_crtc->dpms_mode;
4366
4367         if (!crtc->enabled) {
4368                 if (!mode)
4369                         mode = &load_detect_mode;
4370                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4371         } else {
4372                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4373                         crtc_funcs = crtc->helper_private;
4374                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4375                 }
4376
4377                 /* Add this connector to the crtc */
4378                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4379                 encoder_funcs->commit(encoder);
4380         }
4381         /* let the connector get through one full cycle before testing */
4382         intel_wait_for_vblank(dev);
4383
4384         return crtc;
4385 }
4386
4387 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4388                                     struct drm_connector *connector, int dpms_mode)
4389 {
4390         struct drm_encoder *encoder = &intel_encoder->enc;
4391         struct drm_device *dev = encoder->dev;
4392         struct drm_crtc *crtc = encoder->crtc;
4393         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4394         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4395
4396         if (intel_encoder->load_detect_temp) {
4397                 encoder->crtc = NULL;
4398                 connector->encoder = NULL;
4399                 intel_encoder->load_detect_temp = false;
4400                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4401                 drm_helper_disable_unused_functions(dev);
4402         }
4403
4404         /* Switch crtc and encoder back off if necessary */
4405         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4406                 if (encoder->crtc == crtc)
4407                         encoder_funcs->dpms(encoder, dpms_mode);
4408                 crtc_funcs->dpms(crtc, dpms_mode);
4409         }
4410 }
4411
4412 /* Returns the clock of the currently programmed mode of the given pipe. */
4413 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4414 {
4415         struct drm_i915_private *dev_priv = dev->dev_private;
4416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4417         int pipe = intel_crtc->pipe;
4418         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4419         u32 fp;
4420         intel_clock_t clock;
4421
4422         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4423                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4424         else
4425                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4426
4427         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4428         if (IS_PINEVIEW(dev)) {
4429                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4430                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4431         } else {
4432                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4433                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4434         }
4435
4436         if (IS_I9XX(dev)) {
4437                 if (IS_PINEVIEW(dev))
4438                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4439                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4440                 else
4441                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4442                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4443
4444                 switch (dpll & DPLL_MODE_MASK) {
4445                 case DPLLB_MODE_DAC_SERIAL:
4446                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4447                                 5 : 10;
4448                         break;
4449                 case DPLLB_MODE_LVDS:
4450                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4451                                 7 : 14;
4452                         break;
4453                 default:
4454                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4455                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4456                         return 0;
4457                 }
4458
4459                 /* XXX: Handle the 100Mhz refclk */
4460                 intel_clock(dev, 96000, &clock);
4461         } else {
4462                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4463
4464                 if (is_lvds) {
4465                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4466                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4467                         clock.p2 = 14;
4468
4469                         if ((dpll & PLL_REF_INPUT_MASK) ==
4470                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4471                                 /* XXX: might not be 66MHz */
4472                                 intel_clock(dev, 66000, &clock);
4473                         } else
4474                                 intel_clock(dev, 48000, &clock);
4475                 } else {
4476                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4477                                 clock.p1 = 2;
4478                         else {
4479                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4480                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4481                         }
4482                         if (dpll & PLL_P2_DIVIDE_BY_4)
4483                                 clock.p2 = 4;
4484                         else
4485                                 clock.p2 = 2;
4486
4487                         intel_clock(dev, 48000, &clock);
4488                 }
4489         }
4490
4491         /* XXX: It would be nice to validate the clocks, but we can't reuse
4492          * i830PllIsValid() because it relies on the xf86_config connector
4493          * configuration being accurate, which it isn't necessarily.
4494          */
4495
4496         return clock.dot;
4497 }
4498
4499 /** Returns the currently programmed mode of the given pipe. */
4500 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4501                                              struct drm_crtc *crtc)
4502 {
4503         struct drm_i915_private *dev_priv = dev->dev_private;
4504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4505         int pipe = intel_crtc->pipe;
4506         struct drm_display_mode *mode;
4507         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4508         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4509         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4510         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4511
4512         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4513         if (!mode)
4514                 return NULL;
4515
4516         mode->clock = intel_crtc_clock_get(dev, crtc);
4517         mode->hdisplay = (htot & 0xffff) + 1;
4518         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4519         mode->hsync_start = (hsync & 0xffff) + 1;
4520         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4521         mode->vdisplay = (vtot & 0xffff) + 1;
4522         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4523         mode->vsync_start = (vsync & 0xffff) + 1;
4524         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4525
4526         drm_mode_set_name(mode);
4527         drm_mode_set_crtcinfo(mode, 0);
4528
4529         return mode;
4530 }
4531
4532 #define GPU_IDLE_TIMEOUT 500 /* ms */
4533
4534 /* When this timer fires, we've been idle for awhile */
4535 static void intel_gpu_idle_timer(unsigned long arg)
4536 {
4537         struct drm_device *dev = (struct drm_device *)arg;
4538         drm_i915_private_t *dev_priv = dev->dev_private;
4539
4540         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4541
4542         dev_priv->busy = false;
4543
4544         queue_work(dev_priv->wq, &dev_priv->idle_work);
4545 }
4546
4547 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4548
4549 static void intel_crtc_idle_timer(unsigned long arg)
4550 {
4551         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4552         struct drm_crtc *crtc = &intel_crtc->base;
4553         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4554
4555         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4556
4557         intel_crtc->busy = false;
4558
4559         queue_work(dev_priv->wq, &dev_priv->idle_work);
4560 }
4561
4562 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4563 {
4564         struct drm_device *dev = crtc->dev;
4565         drm_i915_private_t *dev_priv = dev->dev_private;
4566         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4567         int pipe = intel_crtc->pipe;
4568         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4569         int dpll = I915_READ(dpll_reg);
4570
4571         if (HAS_PCH_SPLIT(dev))
4572                 return;
4573
4574         if (!dev_priv->lvds_downclock_avail)
4575                 return;
4576
4577         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4578                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4579
4580                 /* Unlock panel regs */
4581                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4582
4583                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4584                 I915_WRITE(dpll_reg, dpll);
4585                 dpll = I915_READ(dpll_reg);
4586                 intel_wait_for_vblank(dev);
4587                 dpll = I915_READ(dpll_reg);
4588                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4589                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4590
4591                 /* ...and lock them again */
4592                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4593         }
4594
4595         /* Schedule downclock */
4596         if (schedule)
4597                 mod_timer(&intel_crtc->idle_timer, jiffies +
4598                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4599 }
4600
4601 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4602 {
4603         struct drm_device *dev = crtc->dev;
4604         drm_i915_private_t *dev_priv = dev->dev_private;
4605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4606         int pipe = intel_crtc->pipe;
4607         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4608         int dpll = I915_READ(dpll_reg);
4609
4610         if (HAS_PCH_SPLIT(dev))
4611                 return;
4612
4613         if (!dev_priv->lvds_downclock_avail)
4614                 return;
4615
4616         /*
4617          * Since this is called by a timer, we should never get here in
4618          * the manual case.
4619          */
4620         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4621                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4622
4623                 /* Unlock panel regs */
4624                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4625
4626                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4627                 I915_WRITE(dpll_reg, dpll);
4628                 dpll = I915_READ(dpll_reg);
4629                 intel_wait_for_vblank(dev);
4630                 dpll = I915_READ(dpll_reg);
4631                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4632                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4633
4634                 /* ...and lock them again */
4635                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4636         }
4637
4638 }
4639
4640 /**
4641  * intel_idle_update - adjust clocks for idleness
4642  * @work: work struct
4643  *
4644  * Either the GPU or display (or both) went idle.  Check the busy status
4645  * here and adjust the CRTC and GPU clocks as necessary.
4646  */
4647 static void intel_idle_update(struct work_struct *work)
4648 {
4649         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4650                                                     idle_work);
4651         struct drm_device *dev = dev_priv->dev;
4652         struct drm_crtc *crtc;
4653         struct intel_crtc *intel_crtc;
4654         int enabled = 0;
4655
4656         if (!i915_powersave)
4657                 return;
4658
4659         mutex_lock(&dev->struct_mutex);
4660
4661         i915_update_gfx_val(dev_priv);
4662
4663         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4664                 /* Skip inactive CRTCs */
4665                 if (!crtc->fb)
4666                         continue;
4667
4668                 enabled++;
4669                 intel_crtc = to_intel_crtc(crtc);
4670                 if (!intel_crtc->busy)
4671                         intel_decrease_pllclock(crtc);
4672         }
4673
4674         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4675                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4676                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4677         }
4678
4679         mutex_unlock(&dev->struct_mutex);
4680 }
4681
4682 /**
4683  * intel_mark_busy - mark the GPU and possibly the display busy
4684  * @dev: drm device
4685  * @obj: object we're operating on
4686  *
4687  * Callers can use this function to indicate that the GPU is busy processing
4688  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4689  * buffer), we'll also mark the display as busy, so we know to increase its
4690  * clock frequency.
4691  */
4692 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4693 {
4694         drm_i915_private_t *dev_priv = dev->dev_private;
4695         struct drm_crtc *crtc = NULL;
4696         struct intel_framebuffer *intel_fb;
4697         struct intel_crtc *intel_crtc;
4698
4699         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4700                 return;
4701
4702         if (!dev_priv->busy) {
4703                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4704                         u32 fw_blc_self;
4705
4706                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4707                         fw_blc_self = I915_READ(FW_BLC_SELF);
4708                         fw_blc_self &= ~FW_BLC_SELF_EN;
4709                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4710                 }
4711                 dev_priv->busy = true;
4712         } else
4713                 mod_timer(&dev_priv->idle_timer, jiffies +
4714                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4715
4716         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4717                 if (!crtc->fb)
4718                         continue;
4719
4720                 intel_crtc = to_intel_crtc(crtc);
4721                 intel_fb = to_intel_framebuffer(crtc->fb);
4722                 if (intel_fb->obj == obj) {
4723                         if (!intel_crtc->busy) {
4724                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4725                                         u32 fw_blc_self;
4726
4727                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4728                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4729                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4730                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4731                                 }
4732                                 /* Non-busy -> busy, upclock */
4733                                 intel_increase_pllclock(crtc, true);
4734                                 intel_crtc->busy = true;
4735                         } else {
4736                                 /* Busy -> busy, put off timer */
4737                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4738                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4739                         }
4740                 }
4741         }
4742 }
4743
4744 static void intel_crtc_destroy(struct drm_crtc *crtc)
4745 {
4746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4747
4748         drm_crtc_cleanup(crtc);
4749         kfree(intel_crtc);
4750 }
4751
4752 struct intel_unpin_work {
4753         struct work_struct work;
4754         struct drm_device *dev;
4755         struct drm_gem_object *old_fb_obj;
4756         struct drm_gem_object *pending_flip_obj;
4757         struct drm_pending_vblank_event *event;
4758         int pending;
4759 };
4760
4761 static void intel_unpin_work_fn(struct work_struct *__work)
4762 {
4763         struct intel_unpin_work *work =
4764                 container_of(__work, struct intel_unpin_work, work);
4765
4766         mutex_lock(&work->dev->struct_mutex);
4767         i915_gem_object_unpin(work->old_fb_obj);
4768         drm_gem_object_unreference(work->pending_flip_obj);
4769         drm_gem_object_unreference(work->old_fb_obj);
4770         mutex_unlock(&work->dev->struct_mutex);
4771         kfree(work);
4772 }
4773
4774 static void do_intel_finish_page_flip(struct drm_device *dev,
4775                                       struct drm_crtc *crtc)
4776 {
4777         drm_i915_private_t *dev_priv = dev->dev_private;
4778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4779         struct intel_unpin_work *work;
4780         struct drm_i915_gem_object *obj_priv;
4781         struct drm_pending_vblank_event *e;
4782         struct timeval now;
4783         unsigned long flags;
4784
4785         /* Ignore early vblank irqs */
4786         if (intel_crtc == NULL)
4787                 return;
4788
4789         spin_lock_irqsave(&dev->event_lock, flags);
4790         work = intel_crtc->unpin_work;
4791         if (work == NULL || !work->pending) {
4792                 spin_unlock_irqrestore(&dev->event_lock, flags);
4793                 return;
4794         }
4795
4796         intel_crtc->unpin_work = NULL;
4797         drm_vblank_put(dev, intel_crtc->pipe);
4798
4799         if (work->event) {
4800                 e = work->event;
4801                 do_gettimeofday(&now);
4802                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4803                 e->event.tv_sec = now.tv_sec;
4804                 e->event.tv_usec = now.tv_usec;
4805                 list_add_tail(&e->base.link,
4806                               &e->base.file_priv->event_list);
4807                 wake_up_interruptible(&e->base.file_priv->event_wait);
4808         }
4809
4810         spin_unlock_irqrestore(&dev->event_lock, flags);
4811
4812         obj_priv = to_intel_bo(work->pending_flip_obj);
4813
4814         /* Initial scanout buffer will have a 0 pending flip count */
4815         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4816             atomic_dec_and_test(&obj_priv->pending_flip))
4817                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4818         schedule_work(&work->work);
4819
4820         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4821 }
4822
4823 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4824 {
4825         drm_i915_private_t *dev_priv = dev->dev_private;
4826         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4827
4828         do_intel_finish_page_flip(dev, crtc);
4829 }
4830
4831 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4832 {
4833         drm_i915_private_t *dev_priv = dev->dev_private;
4834         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4835
4836         do_intel_finish_page_flip(dev, crtc);
4837 }
4838
4839 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4840 {
4841         drm_i915_private_t *dev_priv = dev->dev_private;
4842         struct intel_crtc *intel_crtc =
4843                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4844         unsigned long flags;
4845
4846         spin_lock_irqsave(&dev->event_lock, flags);
4847         if (intel_crtc->unpin_work) {
4848                 intel_crtc->unpin_work->pending = 1;
4849         } else {
4850                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4851         }
4852         spin_unlock_irqrestore(&dev->event_lock, flags);
4853 }
4854
4855 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4856                                 struct drm_framebuffer *fb,
4857                                 struct drm_pending_vblank_event *event)
4858 {
4859         struct drm_device *dev = crtc->dev;
4860         struct drm_i915_private *dev_priv = dev->dev_private;
4861         struct intel_framebuffer *intel_fb;
4862         struct drm_i915_gem_object *obj_priv;
4863         struct drm_gem_object *obj;
4864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4865         struct intel_unpin_work *work;
4866         unsigned long flags;
4867         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4868         int ret, pipesrc;
4869         u32 flip_mask;
4870
4871         work = kzalloc(sizeof *work, GFP_KERNEL);
4872         if (work == NULL)
4873                 return -ENOMEM;
4874
4875         work->event = event;
4876         work->dev = crtc->dev;
4877         intel_fb = to_intel_framebuffer(crtc->fb);
4878         work->old_fb_obj = intel_fb->obj;
4879         INIT_WORK(&work->work, intel_unpin_work_fn);
4880
4881         /* We borrow the event spin lock for protecting unpin_work */
4882         spin_lock_irqsave(&dev->event_lock, flags);
4883         if (intel_crtc->unpin_work) {
4884                 spin_unlock_irqrestore(&dev->event_lock, flags);
4885                 kfree(work);
4886
4887                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4888                 return -EBUSY;
4889         }
4890         intel_crtc->unpin_work = work;
4891         spin_unlock_irqrestore(&dev->event_lock, flags);
4892
4893         intel_fb = to_intel_framebuffer(fb);
4894         obj = intel_fb->obj;
4895
4896         mutex_lock(&dev->struct_mutex);
4897         ret = intel_pin_and_fence_fb_obj(dev, obj);
4898         if (ret)
4899                 goto cleanup_work;
4900
4901         /* Reference the objects for the scheduled work. */
4902         drm_gem_object_reference(work->old_fb_obj);
4903         drm_gem_object_reference(obj);
4904
4905         crtc->fb = fb;
4906         ret = i915_gem_object_flush_write_domain(obj);
4907         if (ret)
4908                 goto cleanup_objs;
4909
4910         ret = drm_vblank_get(dev, intel_crtc->pipe);
4911         if (ret)
4912                 goto cleanup_objs;
4913
4914         obj_priv = to_intel_bo(obj);
4915         atomic_inc(&obj_priv->pending_flip);
4916         work->pending_flip_obj = obj;
4917
4918         if (intel_crtc->plane)
4919                 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4920         else
4921                 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
4922
4923         /* Wait for any previous flip to finish */
4924         if (IS_GEN3(dev))
4925                 while (I915_READ(ISR) & flip_mask)
4926                         ;
4927
4928         BEGIN_LP_RING(4);
4929         if (IS_I965G(dev)) {
4930                 OUT_RING(MI_DISPLAY_FLIP |
4931                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4932                 OUT_RING(fb->pitch);
4933                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4934                 pipesrc = I915_READ(pipesrc_reg);
4935                 OUT_RING(pipesrc & 0x0fff0fff);
4936         } else {
4937                 OUT_RING(MI_DISPLAY_FLIP_I915 |
4938                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4939                 OUT_RING(fb->pitch);
4940                 OUT_RING(obj_priv->gtt_offset);
4941                 OUT_RING(MI_NOOP);
4942         }
4943         ADVANCE_LP_RING();
4944
4945         mutex_unlock(&dev->struct_mutex);
4946
4947         trace_i915_flip_request(intel_crtc->plane, obj);
4948
4949         return 0;
4950
4951 cleanup_objs:
4952         drm_gem_object_unreference(work->old_fb_obj);
4953         drm_gem_object_unreference(obj);
4954 cleanup_work:
4955         mutex_unlock(&dev->struct_mutex);
4956
4957         spin_lock_irqsave(&dev->event_lock, flags);
4958         intel_crtc->unpin_work = NULL;
4959         spin_unlock_irqrestore(&dev->event_lock, flags);
4960
4961         kfree(work);
4962
4963         return ret;
4964 }
4965
4966 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4967         .dpms = intel_crtc_dpms,
4968         .mode_fixup = intel_crtc_mode_fixup,
4969         .mode_set = intel_crtc_mode_set,
4970         .mode_set_base = intel_pipe_set_base,
4971         .prepare = intel_crtc_prepare,
4972         .commit = intel_crtc_commit,
4973         .load_lut = intel_crtc_load_lut,
4974 };
4975
4976 static const struct drm_crtc_funcs intel_crtc_funcs = {
4977         .cursor_set = intel_crtc_cursor_set,
4978         .cursor_move = intel_crtc_cursor_move,
4979         .gamma_set = intel_crtc_gamma_set,
4980         .set_config = drm_crtc_helper_set_config,
4981         .destroy = intel_crtc_destroy,
4982         .page_flip = intel_crtc_page_flip,
4983 };
4984
4985
4986 static void intel_crtc_init(struct drm_device *dev, int pipe)
4987 {
4988         drm_i915_private_t *dev_priv = dev->dev_private;
4989         struct intel_crtc *intel_crtc;
4990         int i;
4991
4992         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4993         if (intel_crtc == NULL)
4994                 return;
4995
4996         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4997
4998         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4999         intel_crtc->pipe = pipe;
5000         intel_crtc->plane = pipe;
5001         for (i = 0; i < 256; i++) {
5002                 intel_crtc->lut_r[i] = i;
5003                 intel_crtc->lut_g[i] = i;
5004                 intel_crtc->lut_b[i] = i;
5005         }
5006
5007         /* Swap pipes & planes for FBC on pre-965 */
5008         intel_crtc->pipe = pipe;
5009         intel_crtc->plane = pipe;
5010         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5011                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5012                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5013         }
5014
5015         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5016                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5017         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5018         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5019
5020         intel_crtc->cursor_addr = 0;
5021         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5022         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5023
5024         intel_crtc->busy = false;
5025
5026         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5027                     (unsigned long)intel_crtc);
5028 }
5029
5030 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5031                                 struct drm_file *file_priv)
5032 {
5033         drm_i915_private_t *dev_priv = dev->dev_private;
5034         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5035         struct drm_mode_object *drmmode_obj;
5036         struct intel_crtc *crtc;
5037
5038         if (!dev_priv) {
5039                 DRM_ERROR("called with no initialization\n");
5040                 return -EINVAL;
5041         }
5042
5043         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5044                         DRM_MODE_OBJECT_CRTC);
5045
5046         if (!drmmode_obj) {
5047                 DRM_ERROR("no such CRTC id\n");
5048                 return -EINVAL;
5049         }
5050
5051         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5052         pipe_from_crtc_id->pipe = crtc->pipe;
5053
5054         return 0;
5055 }
5056
5057 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5058 {
5059         struct drm_crtc *crtc = NULL;
5060
5061         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5062                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5063                 if (intel_crtc->pipe == pipe)
5064                         break;
5065         }
5066         return crtc;
5067 }
5068
5069 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5070 {
5071         int index_mask = 0;
5072         struct drm_encoder *encoder;
5073         int entry = 0;
5074
5075         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5076                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5077                 if (type_mask & intel_encoder->clone_mask)
5078                         index_mask |= (1 << entry);
5079                 entry++;
5080         }
5081         return index_mask;
5082 }
5083
5084
5085 static void intel_setup_outputs(struct drm_device *dev)
5086 {
5087         struct drm_i915_private *dev_priv = dev->dev_private;
5088         struct drm_encoder *encoder;
5089
5090         intel_crt_init(dev);
5091
5092         /* Set up integrated LVDS */
5093         if (IS_MOBILE(dev) && !IS_I830(dev))
5094                 intel_lvds_init(dev);
5095
5096         if (HAS_PCH_SPLIT(dev)) {
5097                 int found;
5098
5099                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5100                         intel_dp_init(dev, DP_A);
5101
5102                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5103                         /* PCH SDVOB multiplex with HDMIB */
5104                         found = intel_sdvo_init(dev, PCH_SDVOB);
5105                         if (!found)
5106                                 intel_hdmi_init(dev, HDMIB);
5107                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5108                                 intel_dp_init(dev, PCH_DP_B);
5109                 }
5110
5111                 if (I915_READ(HDMIC) & PORT_DETECTED)
5112                         intel_hdmi_init(dev, HDMIC);
5113
5114                 if (I915_READ(HDMID) & PORT_DETECTED)
5115                         intel_hdmi_init(dev, HDMID);
5116
5117                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5118                         intel_dp_init(dev, PCH_DP_C);
5119
5120                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
5121                         intel_dp_init(dev, PCH_DP_D);
5122
5123         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5124                 bool found = false;
5125
5126                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5127                         DRM_DEBUG_KMS("probing SDVOB\n");
5128                         found = intel_sdvo_init(dev, SDVOB);
5129                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5130                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5131                                 intel_hdmi_init(dev, SDVOB);
5132                         }
5133
5134                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5135                                 DRM_DEBUG_KMS("probing DP_B\n");
5136                                 intel_dp_init(dev, DP_B);
5137                         }
5138                 }
5139
5140                 /* Before G4X SDVOC doesn't have its own detect register */
5141
5142                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5143                         DRM_DEBUG_KMS("probing SDVOC\n");
5144                         found = intel_sdvo_init(dev, SDVOC);
5145                 }
5146
5147                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5148
5149                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5150                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5151                                 intel_hdmi_init(dev, SDVOC);
5152                         }
5153                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5154                                 DRM_DEBUG_KMS("probing DP_C\n");
5155                                 intel_dp_init(dev, DP_C);
5156                         }
5157                 }
5158
5159                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5160                     (I915_READ(DP_D) & DP_DETECTED)) {
5161                         DRM_DEBUG_KMS("probing DP_D\n");
5162                         intel_dp_init(dev, DP_D);
5163                 }
5164         } else if (IS_GEN2(dev))
5165                 intel_dvo_init(dev);
5166
5167         if (SUPPORTS_TV(dev))
5168                 intel_tv_init(dev);
5169
5170         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5171                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5172
5173                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5174                 encoder->possible_clones = intel_encoder_clones(dev,
5175                                                 intel_encoder->clone_mask);
5176         }
5177 }
5178
5179 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5180 {
5181         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5182
5183         drm_framebuffer_cleanup(fb);
5184         drm_gem_object_unreference_unlocked(intel_fb->obj);
5185
5186         kfree(intel_fb);
5187 }
5188
5189 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5190                                                 struct drm_file *file_priv,
5191                                                 unsigned int *handle)
5192 {
5193         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5194         struct drm_gem_object *object = intel_fb->obj;
5195
5196         return drm_gem_handle_create(file_priv, object, handle);
5197 }
5198
5199 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5200         .destroy = intel_user_framebuffer_destroy,
5201         .create_handle = intel_user_framebuffer_create_handle,
5202 };
5203
5204 int intel_framebuffer_init(struct drm_device *dev,
5205                            struct intel_framebuffer *intel_fb,
5206                            struct drm_mode_fb_cmd *mode_cmd,
5207                            struct drm_gem_object *obj)
5208 {
5209         int ret;
5210
5211         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5212         if (ret) {
5213                 DRM_ERROR("framebuffer init failed %d\n", ret);
5214                 return ret;
5215         }
5216
5217         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5218         intel_fb->obj = obj;
5219         return 0;
5220 }
5221
5222 static struct drm_framebuffer *
5223 intel_user_framebuffer_create(struct drm_device *dev,
5224                               struct drm_file *filp,
5225                               struct drm_mode_fb_cmd *mode_cmd)
5226 {
5227         struct drm_gem_object *obj;
5228         struct intel_framebuffer *intel_fb;
5229         int ret;
5230
5231         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5232         if (!obj)
5233                 return NULL;
5234
5235         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5236         if (!intel_fb)
5237                 return NULL;
5238
5239         ret = intel_framebuffer_init(dev, intel_fb,
5240                                      mode_cmd, obj);
5241         if (ret) {
5242                 drm_gem_object_unreference_unlocked(obj);
5243                 kfree(intel_fb);
5244                 return NULL;
5245         }
5246
5247         return &intel_fb->base;
5248 }
5249
5250 static const struct drm_mode_config_funcs intel_mode_funcs = {
5251         .fb_create = intel_user_framebuffer_create,
5252         .output_poll_changed = intel_fb_output_poll_changed,
5253 };
5254
5255 static struct drm_gem_object *
5256 intel_alloc_power_context(struct drm_device *dev)
5257 {
5258         struct drm_gem_object *pwrctx;
5259         int ret;
5260
5261         pwrctx = i915_gem_alloc_object(dev, 4096);
5262         if (!pwrctx) {
5263                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5264                 return NULL;
5265         }
5266
5267         mutex_lock(&dev->struct_mutex);
5268         ret = i915_gem_object_pin(pwrctx, 4096);
5269         if (ret) {
5270                 DRM_ERROR("failed to pin power context: %d\n", ret);
5271                 goto err_unref;
5272         }
5273
5274         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5275         if (ret) {
5276                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5277                 goto err_unpin;
5278         }
5279         mutex_unlock(&dev->struct_mutex);
5280
5281         return pwrctx;
5282
5283 err_unpin:
5284         i915_gem_object_unpin(pwrctx);
5285 err_unref:
5286         drm_gem_object_unreference(pwrctx);
5287         mutex_unlock(&dev->struct_mutex);
5288         return NULL;
5289 }
5290
5291 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5292 {
5293         struct drm_i915_private *dev_priv = dev->dev_private;
5294         u16 rgvswctl;
5295
5296         rgvswctl = I915_READ16(MEMSWCTL);
5297         if (rgvswctl & MEMCTL_CMD_STS) {
5298                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5299                 return false; /* still busy with another command */
5300         }
5301
5302         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5303                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5304         I915_WRITE16(MEMSWCTL, rgvswctl);
5305         POSTING_READ16(MEMSWCTL);
5306
5307         rgvswctl |= MEMCTL_CMD_STS;
5308         I915_WRITE16(MEMSWCTL, rgvswctl);
5309
5310         return true;
5311 }
5312
5313 void ironlake_enable_drps(struct drm_device *dev)
5314 {
5315         struct drm_i915_private *dev_priv = dev->dev_private;
5316         u32 rgvmodectl = I915_READ(MEMMODECTL);
5317         u8 fmax, fmin, fstart, vstart;
5318         int i = 0;
5319
5320         /* 100ms RC evaluation intervals */
5321         I915_WRITE(RCUPEI, 100000);
5322         I915_WRITE(RCDNEI, 100000);
5323
5324         /* Set max/min thresholds to 90ms and 80ms respectively */
5325         I915_WRITE(RCBMAXAVG, 90000);
5326         I915_WRITE(RCBMINAVG, 80000);
5327
5328         I915_WRITE(MEMIHYST, 1);
5329
5330         /* Set up min, max, and cur for interrupt handling */
5331         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5332         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5333         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5334                 MEMMODE_FSTART_SHIFT;
5335         fstart = fmax;
5336
5337         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5338                 PXVFREQ_PX_SHIFT;
5339
5340         dev_priv->fmax = fstart; /* IPS callback will increase this */
5341         dev_priv->fstart = fstart;
5342
5343         dev_priv->max_delay = fmax;
5344         dev_priv->min_delay = fmin;
5345         dev_priv->cur_delay = fstart;
5346
5347         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5348                          fstart);
5349
5350         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5351
5352         /*
5353          * Interrupts will be enabled in ironlake_irq_postinstall
5354          */
5355
5356         I915_WRITE(VIDSTART, vstart);
5357         POSTING_READ(VIDSTART);
5358
5359         rgvmodectl |= MEMMODE_SWMODE_EN;
5360         I915_WRITE(MEMMODECTL, rgvmodectl);
5361
5362         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5363                 if (i++ > 100) {
5364                         DRM_ERROR("stuck trying to change perf mode\n");
5365                         break;
5366                 }
5367                 msleep(1);
5368         }
5369         msleep(1);
5370
5371         ironlake_set_drps(dev, fstart);
5372
5373         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5374                 I915_READ(0x112e0);
5375         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5376         dev_priv->last_count2 = I915_READ(0x112f4);
5377         getrawmonotonic(&dev_priv->last_time2);
5378 }
5379
5380 void ironlake_disable_drps(struct drm_device *dev)
5381 {
5382         struct drm_i915_private *dev_priv = dev->dev_private;
5383         u16 rgvswctl = I915_READ16(MEMSWCTL);
5384
5385         /* Ack interrupts, disable EFC interrupt */
5386         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5387         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5388         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5389         I915_WRITE(DEIIR, DE_PCU_EVENT);
5390         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5391
5392         /* Go back to the starting frequency */
5393         ironlake_set_drps(dev, dev_priv->fstart);
5394         msleep(1);
5395         rgvswctl |= MEMCTL_CMD_STS;
5396         I915_WRITE(MEMSWCTL, rgvswctl);
5397         msleep(1);
5398
5399 }
5400
5401 static unsigned long intel_pxfreq(u32 vidfreq)
5402 {
5403         unsigned long freq;
5404         int div = (vidfreq & 0x3f0000) >> 16;
5405         int post = (vidfreq & 0x3000) >> 12;
5406         int pre = (vidfreq & 0x7);
5407
5408         if (!pre)
5409                 return 0;
5410
5411         freq = ((div * 133333) / ((1<<post) * pre));
5412
5413         return freq;
5414 }
5415
5416 void intel_init_emon(struct drm_device *dev)
5417 {
5418         struct drm_i915_private *dev_priv = dev->dev_private;
5419         u32 lcfuse;
5420         u8 pxw[16];
5421         int i;
5422
5423         /* Disable to program */
5424         I915_WRITE(ECR, 0);
5425         POSTING_READ(ECR);
5426
5427         /* Program energy weights for various events */
5428         I915_WRITE(SDEW, 0x15040d00);
5429         I915_WRITE(CSIEW0, 0x007f0000);
5430         I915_WRITE(CSIEW1, 0x1e220004);
5431         I915_WRITE(CSIEW2, 0x04000004);
5432
5433         for (i = 0; i < 5; i++)
5434                 I915_WRITE(PEW + (i * 4), 0);
5435         for (i = 0; i < 3; i++)
5436                 I915_WRITE(DEW + (i * 4), 0);
5437
5438         /* Program P-state weights to account for frequency power adjustment */
5439         for (i = 0; i < 16; i++) {
5440                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5441                 unsigned long freq = intel_pxfreq(pxvidfreq);
5442                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5443                         PXVFREQ_PX_SHIFT;
5444                 unsigned long val;
5445
5446                 val = vid * vid;
5447                 val *= (freq / 1000);
5448                 val *= 255;
5449                 val /= (127*127*900);
5450                 if (val > 0xff)
5451                         DRM_ERROR("bad pxval: %ld\n", val);
5452                 pxw[i] = val;
5453         }
5454         /* Render standby states get 0 weight */
5455         pxw[14] = 0;
5456         pxw[15] = 0;
5457
5458         for (i = 0; i < 4; i++) {
5459                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5460                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5461                 I915_WRITE(PXW + (i * 4), val);
5462         }
5463
5464         /* Adjust magic regs to magic values (more experimental results) */
5465         I915_WRITE(OGW0, 0);
5466         I915_WRITE(OGW1, 0);
5467         I915_WRITE(EG0, 0x00007f00);
5468         I915_WRITE(EG1, 0x0000000e);
5469         I915_WRITE(EG2, 0x000e0000);
5470         I915_WRITE(EG3, 0x68000300);
5471         I915_WRITE(EG4, 0x42000000);
5472         I915_WRITE(EG5, 0x00140031);
5473         I915_WRITE(EG6, 0);
5474         I915_WRITE(EG7, 0);
5475
5476         for (i = 0; i < 8; i++)
5477                 I915_WRITE(PXWL + (i * 4), 0);
5478
5479         /* Enable PMON + select events */
5480         I915_WRITE(ECR, 0x80000019);
5481
5482         lcfuse = I915_READ(LCFUSE02);
5483
5484         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5485 }
5486
5487 void intel_init_clock_gating(struct drm_device *dev)
5488 {
5489         struct drm_i915_private *dev_priv = dev->dev_private;
5490
5491         /*
5492          * Disable clock gating reported to work incorrectly according to the
5493          * specs, but enable as much else as we can.
5494          */
5495         if (HAS_PCH_SPLIT(dev)) {
5496                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5497
5498                 if (IS_IRONLAKE(dev)) {
5499                         /* Required for FBC */
5500                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5501                         /* Required for CxSR */
5502                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5503
5504                         I915_WRITE(PCH_3DCGDIS0,
5505                                    MARIUNIT_CLOCK_GATE_DISABLE |
5506                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5507                 }
5508
5509                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5510
5511                 /*
5512                  * According to the spec the following bits should be set in
5513                  * order to enable memory self-refresh
5514                  * The bit 22/21 of 0x42004
5515                  * The bit 5 of 0x42020
5516                  * The bit 15 of 0x45000
5517                  */
5518                 if (IS_IRONLAKE(dev)) {
5519                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5520                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5521                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5522                         I915_WRITE(ILK_DSPCLK_GATE,
5523                                         (I915_READ(ILK_DSPCLK_GATE) |
5524                                                 ILK_DPARB_CLK_GATE));
5525                         I915_WRITE(DISP_ARB_CTL,
5526                                         (I915_READ(DISP_ARB_CTL) |
5527                                                 DISP_FBC_WM_DIS));
5528                 }
5529                 /*
5530                  * Based on the document from hardware guys the following bits
5531                  * should be set unconditionally in order to enable FBC.
5532                  * The bit 22 of 0x42000
5533                  * The bit 22 of 0x42004
5534                  * The bit 7,8,9 of 0x42020.
5535                  */
5536                 if (IS_IRONLAKE_M(dev)) {
5537                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5538                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5539                                    ILK_FBCQ_DIS);
5540                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5541                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5542                                    ILK_DPARB_GATE);
5543                         I915_WRITE(ILK_DSPCLK_GATE,
5544                                    I915_READ(ILK_DSPCLK_GATE) |
5545                                    ILK_DPFC_DIS1 |
5546                                    ILK_DPFC_DIS2 |
5547                                    ILK_CLK_FBC);
5548                 }
5549                 return;
5550         } else if (IS_G4X(dev)) {
5551                 uint32_t dspclk_gate;
5552                 I915_WRITE(RENCLK_GATE_D1, 0);
5553                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5554                        GS_UNIT_CLOCK_GATE_DISABLE |
5555                        CL_UNIT_CLOCK_GATE_DISABLE);
5556                 I915_WRITE(RAMCLK_GATE_D, 0);
5557                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5558                         OVRUNIT_CLOCK_GATE_DISABLE |
5559                         OVCUNIT_CLOCK_GATE_DISABLE;
5560                 if (IS_GM45(dev))
5561                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5562                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5563         } else if (IS_I965GM(dev)) {
5564                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5565                 I915_WRITE(RENCLK_GATE_D2, 0);
5566                 I915_WRITE(DSPCLK_GATE_D, 0);
5567                 I915_WRITE(RAMCLK_GATE_D, 0);
5568                 I915_WRITE16(DEUC, 0);
5569         } else if (IS_I965G(dev)) {
5570                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5571                        I965_RCC_CLOCK_GATE_DISABLE |
5572                        I965_RCPB_CLOCK_GATE_DISABLE |
5573                        I965_ISC_CLOCK_GATE_DISABLE |
5574                        I965_FBC_CLOCK_GATE_DISABLE);
5575                 I915_WRITE(RENCLK_GATE_D2, 0);
5576         } else if (IS_I9XX(dev)) {
5577                 u32 dstate = I915_READ(D_STATE);
5578
5579                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5580                         DSTATE_DOT_CLOCK_GATING;
5581                 I915_WRITE(D_STATE, dstate);
5582         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5583                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5584         } else if (IS_I830(dev)) {
5585                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5586         }
5587
5588         /*
5589          * GPU can automatically power down the render unit if given a page
5590          * to save state.
5591          */
5592         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5593                 struct drm_i915_gem_object *obj_priv = NULL;
5594
5595                 if (dev_priv->pwrctx) {
5596                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5597                 } else {
5598                         struct drm_gem_object *pwrctx;
5599
5600                         pwrctx = intel_alloc_power_context(dev);
5601                         if (pwrctx) {
5602                                 dev_priv->pwrctx = pwrctx;
5603                                 obj_priv = to_intel_bo(pwrctx);
5604                         }
5605                 }
5606
5607                 if (obj_priv) {
5608                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5609                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5610                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5611                 }
5612         }
5613 }
5614
5615 /* Set up chip specific display functions */
5616 static void intel_init_display(struct drm_device *dev)
5617 {
5618         struct drm_i915_private *dev_priv = dev->dev_private;
5619
5620         /* We always want a DPMS function */
5621         if (HAS_PCH_SPLIT(dev))
5622                 dev_priv->display.dpms = ironlake_crtc_dpms;
5623         else
5624                 dev_priv->display.dpms = i9xx_crtc_dpms;
5625
5626         if (I915_HAS_FBC(dev)) {
5627                 if (IS_IRONLAKE_M(dev)) {
5628                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5629                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5630                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5631                 } else if (IS_GM45(dev)) {
5632                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5633                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5634                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5635                 } else if (IS_I965GM(dev)) {
5636                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5637                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5638                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5639                 }
5640                 /* 855GM needs testing */
5641         }
5642
5643         /* Returns the core display clock speed */
5644         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5645                 dev_priv->display.get_display_clock_speed =
5646                         i945_get_display_clock_speed;
5647         else if (IS_I915G(dev))
5648                 dev_priv->display.get_display_clock_speed =
5649                         i915_get_display_clock_speed;
5650         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5651                 dev_priv->display.get_display_clock_speed =
5652                         i9xx_misc_get_display_clock_speed;
5653         else if (IS_I915GM(dev))
5654                 dev_priv->display.get_display_clock_speed =
5655                         i915gm_get_display_clock_speed;
5656         else if (IS_I865G(dev))
5657                 dev_priv->display.get_display_clock_speed =
5658                         i865_get_display_clock_speed;
5659         else if (IS_I85X(dev))
5660                 dev_priv->display.get_display_clock_speed =
5661                         i855_get_display_clock_speed;
5662         else /* 852, 830 */
5663                 dev_priv->display.get_display_clock_speed =
5664                         i830_get_display_clock_speed;
5665
5666         /* For FIFO watermark updates */
5667         if (HAS_PCH_SPLIT(dev)) {
5668                 if (IS_IRONLAKE(dev)) {
5669                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5670                                 dev_priv->display.update_wm = ironlake_update_wm;
5671                         else {
5672                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5673                                               "Disable CxSR\n");
5674                                 dev_priv->display.update_wm = NULL;
5675                         }
5676                 } else
5677                         dev_priv->display.update_wm = NULL;
5678         } else if (IS_PINEVIEW(dev)) {
5679                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5680                                             dev_priv->is_ddr3,
5681                                             dev_priv->fsb_freq,
5682                                             dev_priv->mem_freq)) {
5683                         DRM_INFO("failed to find known CxSR latency "
5684                                  "(found ddr%s fsb freq %d, mem freq %d), "
5685                                  "disabling CxSR\n",
5686                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5687                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5688                         /* Disable CxSR and never update its watermark again */
5689                         pineview_disable_cxsr(dev);
5690                         dev_priv->display.update_wm = NULL;
5691                 } else
5692                         dev_priv->display.update_wm = pineview_update_wm;
5693         } else if (IS_G4X(dev))
5694                 dev_priv->display.update_wm = g4x_update_wm;
5695         else if (IS_I965G(dev))
5696                 dev_priv->display.update_wm = i965_update_wm;
5697         else if (IS_I9XX(dev)) {
5698                 dev_priv->display.update_wm = i9xx_update_wm;
5699                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5700         } else if (IS_I85X(dev)) {
5701                 dev_priv->display.update_wm = i9xx_update_wm;
5702                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5703         } else {
5704                 dev_priv->display.update_wm = i830_update_wm;
5705                 if (IS_845G(dev))
5706                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5707                 else
5708                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5709         }
5710 }
5711
5712 void intel_modeset_init(struct drm_device *dev)
5713 {
5714         struct drm_i915_private *dev_priv = dev->dev_private;
5715         int i;
5716
5717         drm_mode_config_init(dev);
5718
5719         dev->mode_config.min_width = 0;
5720         dev->mode_config.min_height = 0;
5721
5722         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5723
5724         intel_init_display(dev);
5725
5726         if (IS_I965G(dev)) {
5727                 dev->mode_config.max_width = 8192;
5728                 dev->mode_config.max_height = 8192;
5729         } else if (IS_I9XX(dev)) {
5730                 dev->mode_config.max_width = 4096;
5731                 dev->mode_config.max_height = 4096;
5732         } else {
5733                 dev->mode_config.max_width = 2048;
5734                 dev->mode_config.max_height = 2048;
5735         }
5736
5737         /* set memory base */
5738         if (IS_I9XX(dev))
5739                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5740         else
5741                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5742
5743         if (IS_MOBILE(dev) || IS_I9XX(dev))
5744                 dev_priv->num_pipe = 2;
5745         else
5746                 dev_priv->num_pipe = 1;
5747         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5748                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5749
5750         for (i = 0; i < dev_priv->num_pipe; i++) {
5751                 intel_crtc_init(dev, i);
5752         }
5753
5754         intel_setup_outputs(dev);
5755
5756         intel_init_clock_gating(dev);
5757
5758         if (IS_IRONLAKE_M(dev)) {
5759                 ironlake_enable_drps(dev);
5760                 intel_init_emon(dev);
5761         }
5762
5763         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5764         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5765                     (unsigned long)dev);
5766
5767         intel_setup_overlay(dev);
5768 }
5769
5770 void intel_modeset_cleanup(struct drm_device *dev)
5771 {
5772         struct drm_i915_private *dev_priv = dev->dev_private;
5773         struct drm_crtc *crtc;
5774         struct intel_crtc *intel_crtc;
5775
5776         mutex_lock(&dev->struct_mutex);
5777
5778         drm_kms_helper_poll_fini(dev);
5779         intel_fbdev_fini(dev);
5780
5781         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5782                 /* Skip inactive CRTCs */
5783                 if (!crtc->fb)
5784                         continue;
5785
5786                 intel_crtc = to_intel_crtc(crtc);
5787                 intel_increase_pllclock(crtc, false);
5788                 del_timer_sync(&intel_crtc->idle_timer);
5789         }
5790
5791         del_timer_sync(&dev_priv->idle_timer);
5792
5793         if (dev_priv->display.disable_fbc)
5794                 dev_priv->display.disable_fbc(dev);
5795
5796         if (dev_priv->pwrctx) {
5797                 struct drm_i915_gem_object *obj_priv;
5798
5799                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5800                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5801                 I915_READ(PWRCTXA);
5802                 i915_gem_object_unpin(dev_priv->pwrctx);
5803                 drm_gem_object_unreference(dev_priv->pwrctx);
5804         }
5805
5806         if (IS_IRONLAKE_M(dev))
5807                 ironlake_disable_drps(dev);
5808
5809         mutex_unlock(&dev->struct_mutex);
5810
5811         drm_mode_config_cleanup(dev);
5812 }
5813
5814
5815 /*
5816  * Return which encoder is currently attached for connector.
5817  */
5818 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5819 {
5820         struct drm_mode_object *obj;
5821         struct drm_encoder *encoder;
5822         int i;
5823
5824         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5825                 if (connector->encoder_ids[i] == 0)
5826                         break;
5827
5828                 obj = drm_mode_object_find(connector->dev,
5829                                            connector->encoder_ids[i],
5830                                            DRM_MODE_OBJECT_ENCODER);
5831                 if (!obj)
5832                         continue;
5833
5834                 encoder = obj_to_encoder(obj);
5835                 return encoder;
5836         }
5837         return NULL;
5838 }
5839
5840 /*
5841  * set vga decode state - true == enable VGA decode
5842  */
5843 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5844 {
5845         struct drm_i915_private *dev_priv = dev->dev_private;
5846         u16 gmch_ctrl;
5847
5848         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5849         if (state)
5850                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5851         else
5852                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5853         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5854         return 0;
5855 }