drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 710                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711                      clock.m1++) {
 712                         for (clock.m2 = limit->m2.min;
 713                              clock.m2 <= limit->m2.max; clock.m2++) {
 714                                 /* m1 is always 0 in IGD */
 715                                 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 716                                         break;
 717                                 for (clock.n = limit->n.min;
 718                                      clock.n <= limit->n.max; clock.n++) {
 719                                         int this_err;
 720
 721                                         intel_clock(dev, refclk, &clock);
 722
 723                                         if (!intel_PLL_is_valid(crtc, &clock))
 724                                                 continue;
 725
 726                                         this_err = abs(clock.dot - target);
 727                                         if (this_err < err) {
 728                                                 *best_clock = clock;
 729                                                 err = this_err;
 730                                         }
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         return (err != target);
 737 }
 738
 739
 740 static bool
 741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                             int target, int refclk, intel_clock_t *best_clock)
 743
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         intel_clock_t clock;
 747         int err = target;
 748         bool found = false;
 749
 750         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 751
 752         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 753                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 754                         /* m1 is always 0 in IGD */
 755                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 756                                 break;
 757                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 758                              clock.n++) {
 759                                 int this_err;
 760
 761                                 intel_clock(dev, refclk, &clock);
 762
 763                                 if (!intel_PLL_is_valid(crtc, &clock))
 764                                         continue;
 765
 766                                 this_err = abs(clock.dot - target);
 767                                 if (this_err < err) {
 768                                         *best_clock = clock;
 769                                         err = this_err;
 770                                         found = true;
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return found;
 777 }
 778
 779 static bool
 780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 781                         int target, int refclk, intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->dev;
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         intel_clock_t clock;
 786         int max_n;
 787         bool found;
 788         /* approximately equals target * 0.00488 */
 789         int err_most = (target >> 8) + (target >> 10);
 790         found = false;
 791
 792         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 793                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 794                     LVDS_CLKB_POWER_UP)
 795                         clock.p2 = limit->p2.p2_fast;
 796                 else
 797                         clock.p2 = limit->p2.p2_slow;
 798         } else {
 799                 if (target < limit->p2.dot_limit)
 800                         clock.p2 = limit->p2.p2_slow;
 801                 else
 802                         clock.p2 = limit->p2.p2_fast;
 803         }
 804
 805         memset(best_clock, 0, sizeof(*best_clock));
 806         max_n = limit->n.max;
 807         /* based on hardware requriment prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirment prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         intel_clock(dev, refclk, &clock);
 819                                         if (!intel_PLL_is_valid(crtc, &clock))
 820                                                 continue;
 821                                         this_err = abs(clock.dot - target) ;
 822                                         if (this_err < err_most) {
 823                                                 *best_clock = clock;
 824                                                 err_most = this_err;
 825                                                 max_n = clock.n;
 826                                                 found = true;
 827                                         }
 828                                 }
 829                         }
 830                 }
 831         }
 832         return found;
 833 }
 834
 835 static bool
 836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *best_clock)
 838 {
 839         struct drm_device *dev = crtc->dev;
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.n = 1;
 843                 clock.p1 = 2;
 844                 clock.p2 = 10;
 845                 clock.m1 = 12;
 846                 clock.m2 = 9;
 847         } else {
 848                 clock.n = 2;
 849                 clock.p1 = 1;
 850                 clock.p2 = 10;
 851                 clock.m1 = 14;
 852                 clock.m2 = 8;
 853         }
 854         intel_clock(dev, refclk, &clock);
 855         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 856         return true;
 857 }
 858
 859 static bool
 860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 861                         int target, int refclk, intel_clock_t *best_clock)
 862 {
 863         struct drm_device *dev = crtc->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found;
 868         int err_most = 47;
 869         found = false;
 870
 871         /* eDP has only 2 clock choice, no n/m/p setting */
 872         if (HAS_eDP)
 873                 return true;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 876                 return intel_find_pll_igdng_dp(limit, crtc, target,
 877                                                refclk, best_clock);
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 881                     LVDS_CLKB_POWER_UP)
 882                         clock.p2 = limit->p2.p2_fast;
 883                 else
 884                         clock.p2 = limit->p2.p2_slow;
 885         } else {
 886                 if (target < limit->p2.dot_limit)
 887                         clock.p2 = limit->p2.p2_slow;
 888                 else
 889                         clock.p2 = limit->p2.p2_fast;
 890         }
 891
 892         memset(best_clock, 0, sizeof(*best_clock));
 893         max_n = limit->n.max;
 894         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 895                 /* based on hardware requriment prefer smaller n to precision */
 896                 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 897                         /* based on hardware requirment prefere larger m1,m2 */
 898                         for (clock.m1 = limit->m1.max;
 899                              clock.m1 >= limit->m1.min; clock.m1--) {
 900                                 for (clock.m2 = limit->m2.max;
 901                                      clock.m2 >= limit->m2.min; clock.m2--) {
 902                                         int this_err;
 903
 904                                         intel_clock(dev, refclk, &clock);
 905                                         if (!intel_PLL_is_valid(crtc, &clock))
 906                                                 continue;
 907                                         this_err = abs((10000 - (target*10000/clock.dot)));
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                                 /* found on first matching */
 914                                                 goto out;
 915                                         }
 916                                 }
 917                         }
 918                 }
 919         }
 920 out:
 921         return found;
 922 }
 923
 924 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 925 static bool
 926 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 927                       int target, int refclk, intel_clock_t *best_clock)
 928 {
 929     intel_clock_t clock;
 930     if (target < 200000) {
 931         clock.p1 = 2;
 932         clock.p2 = 10;
 933         clock.n = 2;
 934         clock.m1 = 23;
 935         clock.m2 = 8;
 936     } else {
 937         clock.p1 = 1;
 938         clock.p2 = 10;
 939         clock.n = 1;
 940         clock.m1 = 14;
 941         clock.m2 = 2;
 942     }
 943     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 944     clock.p = (clock.p1 * clock.p2);
 945     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 946     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 947     return true;
 948 }
 949
 950 void
 951 intel_wait_for_vblank(struct drm_device *dev)
 952 {
 953         /* Wait for 20ms, i.e. one cycle at 50hz. */
 954         mdelay(20);
 955 }
 956
 957 /* Parameters have changed, update FBC info */
 958 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 959 {
 960         struct drm_device *dev = crtc->dev;
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         struct drm_framebuffer *fb = crtc->fb;
 963         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 964         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 966         int plane, i;
 967         u32 fbc_ctl, fbc_ctl2;
 968
 969         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 970
 971         if (fb->pitch < dev_priv->cfb_pitch)
 972                 dev_priv->cfb_pitch = fb->pitch;
 973
 974         /* FBC_CTL wants 64B units */
 975         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 976         dev_priv->cfb_fence = obj_priv->fence_reg;
 977         dev_priv->cfb_plane = intel_crtc->plane;
 978         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 979
 980         /* Clear old tags */
 981         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 982                 I915_WRITE(FBC_TAG + (i * 4), 0);
 983
 984         /* Set it up... */
 985         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 986         if (obj_priv->tiling_mode != I915_TILING_NONE)
 987                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 988         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 989         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 990
 991         /* enable it... */
 992         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 993         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 994         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 995         if (obj_priv->tiling_mode != I915_TILING_NONE)
 996                 fbc_ctl |= dev_priv->cfb_fence;
 997         I915_WRITE(FBC_CONTROL, fbc_ctl);
 998
 999         DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1000                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1001 }
1002
1003 void i8xx_disable_fbc(struct drm_device *dev)
1004 {
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         u32 fbc_ctl;
1007
1008         /* Disable compression */
1009         fbc_ctl = I915_READ(FBC_CONTROL);
1010         fbc_ctl &= ~FBC_CTL_EN;
1011         I915_WRITE(FBC_CONTROL, fbc_ctl);
1012
1013         /* Wait for compressing bit to clear */
1014         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1015                 ; /* nothing */
1016
1017         intel_wait_for_vblank(dev);
1018
1019         DRM_DEBUG("disabled FBC\n");
1020 }
1021
1022 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1023 {
1024         struct drm_device *dev = crtc->dev;
1025         struct drm_i915_private *dev_priv = dev->dev_private;
1026
1027         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1028 }
1029
1030 /**
1031  * intel_update_fbc - enable/disable FBC as needed
1032  * @crtc: CRTC to point the compressor at
1033  * @mode: mode in use
1034  *
1035  * Set up the framebuffer compression hardware at mode set time.  We
1036  * enable it if possible:
1037  *   - plane A only (on pre-965)
1038  *   - no pixel mulitply/line duplication
1039  *   - no alpha buffer discard
1040  *   - no dual wide
1041  *   - framebuffer <= 2048 in width, 1536 in height
1042  *
1043  * We can't assume that any compression will take place (worst case),
1044  * so the compressed buffer has to be the same size as the uncompressed
1045  * one.  It also must reside (along with the line length buffer) in
1046  * stolen memory.
1047  *
1048  * We need to enable/disable FBC on a global basis.
1049  */
1050 static void intel_update_fbc(struct drm_crtc *crtc,
1051                              struct drm_display_mode *mode)
1052 {
1053         struct drm_device *dev = crtc->dev;
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055         struct drm_framebuffer *fb = crtc->fb;
1056         struct intel_framebuffer *intel_fb;
1057         struct drm_i915_gem_object *obj_priv;
1058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1059         int plane = intel_crtc->plane;
1060
1061         if (!i915_powersave)
1062                 return;
1063
1064         if (!crtc->fb)
1065                 return;
1066
1067         intel_fb = to_intel_framebuffer(fb);
1068         obj_priv = intel_fb->obj->driver_private;
1069
1070         /*
1071          * If FBC is already on, we just have to verify that we can
1072          * keep it that way...
1073          * Need to disable if:
1074          *   - changing FBC params (stride, fence, mode)
1075          *   - new fb is too large to fit in compressed buffer
1076          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1077          */
1078         if (intel_fb->obj->size > dev_priv->cfb_size) {
1079                 DRM_DEBUG("framebuffer too large, disabling compression\n");
1080                 goto out_disable;
1081         }
1082         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1083             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1084                 DRM_DEBUG("mode incompatible with compression, disabling\n");
1085                 goto out_disable;
1086         }
1087         if ((mode->hdisplay > 2048) ||
1088             (mode->vdisplay > 1536)) {
1089                 DRM_DEBUG("mode too large for compression, disabling\n");
1090                 goto out_disable;
1091         }
1092         if (IS_I9XX(dev) && plane != 0) {
1093                 DRM_DEBUG("plane not 0, disabling compression\n");
1094                 goto out_disable;
1095         }
1096         if (obj_priv->tiling_mode != I915_TILING_X) {
1097                 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1098                 goto out_disable;
1099         }
1100
1101         if (i8xx_fbc_enabled(crtc)) {
1102                 /* We can re-enable it in this case, but need to update pitch */
1103                 if (fb->pitch > dev_priv->cfb_pitch)
1104                         i8xx_disable_fbc(dev);
1105                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1106                         i8xx_disable_fbc(dev);
1107                 if (plane != dev_priv->cfb_plane)
1108                         i8xx_disable_fbc(dev);
1109         }
1110
1111         if (!i8xx_fbc_enabled(crtc)) {
1112                 /* Now try to turn it back on if possible */
1113                 i8xx_enable_fbc(crtc, 500);
1114         }
1115
1116         return;
1117
1118 out_disable:
1119         DRM_DEBUG("unsupported config, disabling FBC\n");
1120         /* Multiple disables should be harmless */
1121         if (i8xx_fbc_enabled(crtc))
1122                 i8xx_disable_fbc(dev);
1123 }
1124
1125 static int
1126 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1127                     struct drm_framebuffer *old_fb)
1128 {
1129         struct drm_device *dev = crtc->dev;
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131         struct drm_i915_master_private *master_priv;
1132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1133         struct intel_framebuffer *intel_fb;
1134         struct drm_i915_gem_object *obj_priv;
1135         struct drm_gem_object *obj;
1136         int pipe = intel_crtc->pipe;
1137         int plane = intel_crtc->plane;
1138         unsigned long Start, Offset;
1139         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1140         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1141         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1142         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1143         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1144         u32 dspcntr, alignment;
1145         int ret;
1146
1147         /* no fb bound */
1148         if (!crtc->fb) {
1149                 DRM_DEBUG("No FB bound\n");
1150                 return 0;
1151         }
1152
1153         switch (plane) {
1154         case 0:
1155         case 1:
1156                 break;
1157         default:
1158                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1159                 return -EINVAL;
1160         }
1161
1162         intel_fb = to_intel_framebuffer(crtc->fb);
1163         obj = intel_fb->obj;
1164         obj_priv = obj->driver_private;
1165
1166         switch (obj_priv->tiling_mode) {
1167         case I915_TILING_NONE:
1168                 alignment = 64 * 1024;
1169                 break;
1170         case I915_TILING_X:
1171                 /* pin() will align the object as required by fence */
1172                 alignment = 0;
1173                 break;
1174         case I915_TILING_Y:
1175                 /* FIXME: Is this true? */
1176                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1177                 return -EINVAL;
1178         default:
1179                 BUG();
1180         }
1181
1182         mutex_lock(&dev->struct_mutex);
1183         ret = i915_gem_object_pin(obj, alignment);
1184         if (ret != 0) {
1185                 mutex_unlock(&dev->struct_mutex);
1186                 return ret;
1187         }
1188
1189         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1190         if (ret != 0) {
1191                 i915_gem_object_unpin(obj);
1192                 mutex_unlock(&dev->struct_mutex);
1193                 return ret;
1194         }
1195
1196         /* Pre-i965 needs to install a fence for tiled scan-out */
1197         if (!IS_I965G(dev) &&
1198             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1199             obj_priv->tiling_mode != I915_TILING_NONE) {
1200                 ret = i915_gem_object_get_fence_reg(obj);
1201                 if (ret != 0) {
1202                         i915_gem_object_unpin(obj);
1203                         mutex_unlock(&dev->struct_mutex);
1204                         return ret;
1205                 }
1206         }
1207
1208         dspcntr = I915_READ(dspcntr_reg);
1209         /* Mask out pixel format bits in case we change it */
1210         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1211         switch (crtc->fb->bits_per_pixel) {
1212         case 8:
1213                 dspcntr |= DISPPLANE_8BPP;
1214                 break;
1215         case 16:
1216                 if (crtc->fb->depth == 15)
1217                         dspcntr |= DISPPLANE_15_16BPP;
1218                 else
1219                         dspcntr |= DISPPLANE_16BPP;
1220                 break;
1221         case 24:
1222         case 32:
1223                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1224                 break;
1225         default:
1226                 DRM_ERROR("Unknown color depth\n");
1227                 i915_gem_object_unpin(obj);
1228                 mutex_unlock(&dev->struct_mutex);
1229                 return -EINVAL;
1230         }
1231         if (IS_I965G(dev)) {
1232                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1233                         dspcntr |= DISPPLANE_TILED;
1234                 else
1235                         dspcntr &= ~DISPPLANE_TILED;
1236         }
1237
1238         if (IS_IGDNG(dev))
1239                 /* must disable */
1240                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1241
1242         I915_WRITE(dspcntr_reg, dspcntr);
1243
1244         Start = obj_priv->gtt_offset;
1245         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1246
1247         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1248         I915_WRITE(dspstride, crtc->fb->pitch);
1249         if (IS_I965G(dev)) {
1250                 I915_WRITE(dspbase, Offset);
1251                 I915_READ(dspbase);
1252                 I915_WRITE(dspsurf, Start);
1253                 I915_READ(dspsurf);
1254                 I915_WRITE(dsptileoff, (y << 16) | x);
1255         } else {
1256                 I915_WRITE(dspbase, Start + Offset);
1257                 I915_READ(dspbase);
1258         }
1259
1260         intel_wait_for_vblank(dev);
1261
1262         if (old_fb) {
1263                 intel_fb = to_intel_framebuffer(old_fb);
1264                 obj_priv = intel_fb->obj->driver_private;
1265                 i915_gem_object_unpin(intel_fb->obj);
1266         }
1267         intel_increase_pllclock(crtc, true);
1268
1269         mutex_unlock(&dev->struct_mutex);
1270
1271         if (!dev->primary->master)
1272                 return 0;
1273
1274         master_priv = dev->primary->master->driver_priv;
1275         if (!master_priv->sarea_priv)
1276                 return 0;
1277
1278         if (pipe) {
1279                 master_priv->sarea_priv->pipeB_x = x;
1280                 master_priv->sarea_priv->pipeB_y = y;
1281         } else {
1282                 master_priv->sarea_priv->pipeA_x = x;
1283                 master_priv->sarea_priv->pipeA_y = y;
1284         }
1285
1286         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
1287                 intel_update_fbc(crtc, &crtc->mode);
1288
1289         return 0;
1290 }
1291
1292 /* Disable the VGA plane that we never use */
1293 static void i915_disable_vga (struct drm_device *dev)
1294 {
1295         struct drm_i915_private *dev_priv = dev->dev_private;
1296         u8 sr1;
1297         u32 vga_reg;
1298
1299         if (IS_IGDNG(dev))
1300                 vga_reg = CPU_VGACNTRL;
1301         else
1302                 vga_reg = VGACNTRL;
1303
1304         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1305                 return;
1306
1307         I915_WRITE8(VGA_SR_INDEX, 1);
1308         sr1 = I915_READ8(VGA_SR_DATA);
1309         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1310         udelay(100);
1311
1312         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1313 }
1314
1315 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1316 {
1317         struct drm_device *dev = crtc->dev;
1318         struct drm_i915_private *dev_priv = dev->dev_private;
1319         u32 dpa_ctl;
1320
1321         DRM_DEBUG("\n");
1322         dpa_ctl = I915_READ(DP_A);
1323         dpa_ctl &= ~DP_PLL_ENABLE;
1324         I915_WRITE(DP_A, dpa_ctl);
1325 }
1326
1327 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1328 {
1329         struct drm_device *dev = crtc->dev;
1330         struct drm_i915_private *dev_priv = dev->dev_private;
1331         u32 dpa_ctl;
1332
1333         dpa_ctl = I915_READ(DP_A);
1334         dpa_ctl |= DP_PLL_ENABLE;
1335         I915_WRITE(DP_A, dpa_ctl);
1336         udelay(200);
1337 }
1338
1339
1340 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1341 {
1342         struct drm_device *dev = crtc->dev;
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         u32 dpa_ctl;
1345
1346         DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1347         dpa_ctl = I915_READ(DP_A);
1348         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1349
1350         if (clock < 200000) {
1351                 u32 temp;
1352                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1353                 /* workaround for 160Mhz:
1354                    1) program 0x4600c bits 15:0 = 0x8124
1355                    2) program 0x46010 bit 0 = 1
1356                    3) program 0x46034 bit 24 = 1
1357                    4) program 0x64000 bit 14 = 1
1358                    */
1359                 temp = I915_READ(0x4600c);
1360                 temp &= 0xffff0000;
1361                 I915_WRITE(0x4600c, temp | 0x8124);
1362
1363                 temp = I915_READ(0x46010);
1364                 I915_WRITE(0x46010, temp | 1);
1365
1366                 temp = I915_READ(0x46034);
1367                 I915_WRITE(0x46034, temp | (1 << 24));
1368         } else {
1369                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1370         }
1371         I915_WRITE(DP_A, dpa_ctl);
1372
1373         udelay(500);
1374 }
1375
1376 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1377 {
1378         struct drm_device *dev = crtc->dev;
1379         struct drm_i915_private *dev_priv = dev->dev_private;
1380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1381         int pipe = intel_crtc->pipe;
1382         int plane = intel_crtc->plane;
1383         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1384         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1385         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1386         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1387         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1388         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1389         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1390         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1391         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1392         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1393         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1394         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1395         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1396         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1397         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1398         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1399         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1400         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1401         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1402         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1403         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1404         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1405         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1406         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1407         u32 temp;
1408         int tries = 5, j, n;
1409
1410         /* XXX: When our outputs are all unaware of DPMS modes other than off
1411          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1412          */
1413         switch (mode) {
1414         case DRM_MODE_DPMS_ON:
1415         case DRM_MODE_DPMS_STANDBY:
1416         case DRM_MODE_DPMS_SUSPEND:
1417                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1418                 if (HAS_eDP) {
1419                         /* enable eDP PLL */
1420                         igdng_enable_pll_edp(crtc);
1421                 } else {
1422                         /* enable PCH DPLL */
1423                         temp = I915_READ(pch_dpll_reg);
1424                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1425                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1426                                 I915_READ(pch_dpll_reg);
1427                         }
1428
1429                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1430                         temp = I915_READ(fdi_rx_reg);
1431                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1432                                         FDI_SEL_PCDCLK |
1433                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1434                         I915_READ(fdi_rx_reg);
1435                         udelay(200);
1436
1437                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1438                         temp = I915_READ(fdi_tx_reg);
1439                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1440                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1441                                 I915_READ(fdi_tx_reg);
1442                                 udelay(100);
1443                         }
1444                 }
1445
1446                 /* Enable panel fitting for LVDS */
1447                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1448                         temp = I915_READ(pf_ctl_reg);
1449                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);
1450
1451                         /* currently full aspect */
1452                         I915_WRITE(pf_win_pos, 0);
1453
1454                         I915_WRITE(pf_win_size,
1455                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1456                                    (dev_priv->panel_fixed_mode->vdisplay));
1457                 }
1458
1459                 /* Enable CPU pipe */
1460                 temp = I915_READ(pipeconf_reg);
1461                 if ((temp & PIPEACONF_ENABLE) == 0) {
1462                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1463                         I915_READ(pipeconf_reg);
1464                         udelay(100);
1465                 }
1466
1467                 /* configure and enable CPU plane */
1468                 temp = I915_READ(dspcntr_reg);
1469                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1470                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1471                         /* Flush the plane changes */
1472                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1473                 }
1474
1475                 if (!HAS_eDP) {
1476                         /* enable CPU FDI TX and PCH FDI RX */
1477                         temp = I915_READ(fdi_tx_reg);
1478                         temp |= FDI_TX_ENABLE;
1479                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1480                         temp &= ~FDI_LINK_TRAIN_NONE;
1481                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1482                         I915_WRITE(fdi_tx_reg, temp);
1483                         I915_READ(fdi_tx_reg);
1484
1485                         temp = I915_READ(fdi_rx_reg);
1486                         temp &= ~FDI_LINK_TRAIN_NONE;
1487                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1488                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1489                         I915_READ(fdi_rx_reg);
1490
1491                         udelay(150);
1492
1493                         /* Train FDI. */
1494                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1495                            for train result */
1496                         temp = I915_READ(fdi_rx_imr_reg);
1497                         temp &= ~FDI_RX_SYMBOL_LOCK;
1498                         temp &= ~FDI_RX_BIT_LOCK;
1499                         I915_WRITE(fdi_rx_imr_reg, temp);
1500                         I915_READ(fdi_rx_imr_reg);
1501                         udelay(150);
1502
1503                         temp = I915_READ(fdi_rx_iir_reg);
1504                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1505
1506                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1507                                 for (j = 0; j < tries; j++) {
1508                                         temp = I915_READ(fdi_rx_iir_reg);
1509                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1510                                         if (temp & FDI_RX_BIT_LOCK)
1511                                                 break;
1512                                         udelay(200);
1513                                 }
1514                                 if (j != tries)
1515                                         I915_WRITE(fdi_rx_iir_reg,
1516                                                         temp | FDI_RX_BIT_LOCK);
1517                                 else
1518                                         DRM_DEBUG("train 1 fail\n");
1519                         } else {
1520                                 I915_WRITE(fdi_rx_iir_reg,
1521                                                 temp | FDI_RX_BIT_LOCK);
1522                                 DRM_DEBUG("train 1 ok 2!\n");
1523                         }
1524                         temp = I915_READ(fdi_tx_reg);
1525                         temp &= ~FDI_LINK_TRAIN_NONE;
1526                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1527                         I915_WRITE(fdi_tx_reg, temp);
1528
1529                         temp = I915_READ(fdi_rx_reg);
1530                         temp &= ~FDI_LINK_TRAIN_NONE;
1531                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1532                         I915_WRITE(fdi_rx_reg, temp);
1533
1534                         udelay(150);
1535
1536                         temp = I915_READ(fdi_rx_iir_reg);
1537                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1538
1539                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1540                                 for (j = 0; j < tries; j++) {
1541                                         temp = I915_READ(fdi_rx_iir_reg);
1542                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1543                                         if (temp & FDI_RX_SYMBOL_LOCK)
1544                                                 break;
1545                                         udelay(200);
1546                                 }
1547                                 if (j != tries) {
1548                                         I915_WRITE(fdi_rx_iir_reg,
1549                                                         temp | FDI_RX_SYMBOL_LOCK);
1550                                         DRM_DEBUG("train 2 ok 1!\n");
1551                                 } else
1552                                         DRM_DEBUG("train 2 fail\n");
1553                         } else {
1554                                 I915_WRITE(fdi_rx_iir_reg,
1555                                                 temp | FDI_RX_SYMBOL_LOCK);
1556                                 DRM_DEBUG("train 2 ok 2!\n");
1557                         }
1558                         DRM_DEBUG("train done\n");
1559
1560                         /* set transcoder timing */
1561                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1562                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1563                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1564
1565                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1566                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1567                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1568
1569                         /* enable PCH transcoder */
1570                         temp = I915_READ(transconf_reg);
1571                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1572                         I915_READ(transconf_reg);
1573
1574                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1575                                 ;
1576
1577                         /* enable normal */
1578
1579                         temp = I915_READ(fdi_tx_reg);
1580                         temp &= ~FDI_LINK_TRAIN_NONE;
1581                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1582                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1583                         I915_READ(fdi_tx_reg);
1584
1585                         temp = I915_READ(fdi_rx_reg);
1586                         temp &= ~FDI_LINK_TRAIN_NONE;
1587                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1588                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1589                         I915_READ(fdi_rx_reg);
1590
1591                         /* wait one idle pattern time */
1592                         udelay(100);
1593
1594                 }
1595
1596                 intel_crtc_load_lut(crtc);
1597
1598         break;
1599         case DRM_MODE_DPMS_OFF:
1600                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1601
1602                 i915_disable_vga(dev);
1603
1604                 /* Disable display plane */
1605                 temp = I915_READ(dspcntr_reg);
1606                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1607                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1608                         /* Flush the plane changes */
1609                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1610                         I915_READ(dspbase_reg);
1611                 }
1612
1613                 /* disable cpu pipe, disable after all planes disabled */
1614                 temp = I915_READ(pipeconf_reg);
1615                 if ((temp & PIPEACONF_ENABLE) != 0) {
1616                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1617                         I915_READ(pipeconf_reg);
1618                         n = 0;
1619                         /* wait for cpu pipe off, pipe state */
1620                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1621                                 n++;
1622                                 if (n < 60) {
1623                                         udelay(500);
1624                                         continue;
1625                                 } else {
1626                                         DRM_DEBUG("pipe %d off delay\n", pipe);
1627                                         break;
1628                                 }
1629                         }
1630                 } else
1631                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1632
1633                 if (HAS_eDP) {
1634                         igdng_disable_pll_edp(crtc);
1635                 }
1636
1637                 /* disable CPU FDI tx and PCH FDI rx */
1638                 temp = I915_READ(fdi_tx_reg);
1639                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1640                 I915_READ(fdi_tx_reg);
1641
1642                 temp = I915_READ(fdi_rx_reg);
1643                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1644                 I915_READ(fdi_rx_reg);
1645
1646                 udelay(100);
1647
1648                 /* still set train pattern 1 */
1649                 temp = I915_READ(fdi_tx_reg);
1650                 temp &= ~FDI_LINK_TRAIN_NONE;
1651                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1652                 I915_WRITE(fdi_tx_reg, temp);
1653
1654                 temp = I915_READ(fdi_rx_reg);
1655                 temp &= ~FDI_LINK_TRAIN_NONE;
1656                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1657                 I915_WRITE(fdi_rx_reg, temp);
1658
1659                 udelay(100);
1660
1661                 /* disable PCH transcoder */
1662                 temp = I915_READ(transconf_reg);
1663                 if ((temp & TRANS_ENABLE) != 0) {
1664                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1665                         I915_READ(transconf_reg);
1666                         n = 0;
1667                         /* wait for PCH transcoder off, transcoder state */
1668                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1669                                 n++;
1670                                 if (n < 60) {
1671                                         udelay(500);
1672                                         continue;
1673                                 } else {
1674                                         DRM_DEBUG("transcoder %d off delay\n", pipe);
1675                                         break;
1676                                 }
1677                         }
1678                 }
1679
1680                 /* disable PCH DPLL */
1681                 temp = I915_READ(pch_dpll_reg);
1682                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1683                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1684                         I915_READ(pch_dpll_reg);
1685                 }
1686
1687                 temp = I915_READ(fdi_rx_reg);
1688                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1689                         temp &= ~FDI_SEL_PCDCLK;
1690                         temp &= ~FDI_RX_PLL_ENABLE;
1691                         I915_WRITE(fdi_rx_reg, temp);
1692                         I915_READ(fdi_rx_reg);
1693                 }
1694
1695                 /* Disable CPU FDI TX PLL */
1696                 temp = I915_READ(fdi_tx_reg);
1697                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1698                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1699                         I915_READ(fdi_tx_reg);
1700                         udelay(100);
1701                 }
1702
1703                 /* Disable PF */
1704                 temp = I915_READ(pf_ctl_reg);
1705                 if ((temp & PF_ENABLE) != 0) {
1706                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1707                         I915_READ(pf_ctl_reg);
1708                 }
1709                 I915_WRITE(pf_win_size, 0);
1710
1711                 /* Wait for the clocks to turn off. */
1712                 udelay(150);
1713                 break;
1714         }
1715 }
1716
1717 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1718 {
1719         struct drm_device *dev = crtc->dev;
1720         struct drm_i915_private *dev_priv = dev->dev_private;
1721         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1722         int pipe = intel_crtc->pipe;
1723         int plane = intel_crtc->plane;
1724         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1725         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1726         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1727         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1728         u32 temp;
1729
1730         /* XXX: When our outputs are all unaware of DPMS modes other than off
1731          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1732          */
1733         switch (mode) {
1734         case DRM_MODE_DPMS_ON:
1735         case DRM_MODE_DPMS_STANDBY:
1736         case DRM_MODE_DPMS_SUSPEND:
1737                 /* Enable the DPLL */
1738                 temp = I915_READ(dpll_reg);
1739                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1740                         I915_WRITE(dpll_reg, temp);
1741                         I915_READ(dpll_reg);
1742                         /* Wait for the clocks to stabilize. */
1743                         udelay(150);
1744                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1745                         I915_READ(dpll_reg);
1746                         /* Wait for the clocks to stabilize. */
1747                         udelay(150);
1748                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1749                         I915_READ(dpll_reg);
1750                         /* Wait for the clocks to stabilize. */
1751                         udelay(150);
1752                 }
1753
1754                 /* Enable the pipe */
1755                 temp = I915_READ(pipeconf_reg);
1756                 if ((temp & PIPEACONF_ENABLE) == 0)
1757                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1758
1759                 /* Enable the plane */
1760                 temp = I915_READ(dspcntr_reg);
1761                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1762                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1763                         /* Flush the plane changes */
1764                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1765                 }
1766
1767                 intel_crtc_load_lut(crtc);
1768
1769                 if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
1770                         intel_update_fbc(crtc, &crtc->mode);
1771
1772                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1773                 //intel_crtc_dpms_video(crtc, true); TODO
1774                 intel_update_watermarks(dev);
1775         break;
1776         case DRM_MODE_DPMS_OFF:
1777                 intel_update_watermarks(dev);
1778                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1779                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1780
1781                 if (dev_priv->cfb_plane == plane)
1782                         i8xx_disable_fbc(dev);
1783
1784                 /* Disable the VGA plane that we never use */
1785                 i915_disable_vga(dev);
1786
1787                 /* Disable display plane */
1788                 temp = I915_READ(dspcntr_reg);
1789                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1790                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1791                         /* Flush the plane changes */
1792                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1793                         I915_READ(dspbase_reg);
1794                 }
1795
1796                 if (!IS_I9XX(dev)) {
1797                         /* Wait for vblank for the disable to take effect */
1798                         intel_wait_for_vblank(dev);
1799                 }
1800
1801                 /* Next, disable display pipes */
1802                 temp = I915_READ(pipeconf_reg);
1803                 if ((temp & PIPEACONF_ENABLE) != 0) {
1804                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1805                         I915_READ(pipeconf_reg);
1806                 }
1807
1808                 /* Wait for vblank for the disable to take effect. */
1809                 intel_wait_for_vblank(dev);
1810
1811                 temp = I915_READ(dpll_reg);
1812                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1813                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1814                         I915_READ(dpll_reg);
1815                 }
1816
1817                 /* Wait for the clocks to turn off. */
1818                 udelay(150);
1819                 break;
1820         }
1821 }
1822
1823 /**
1824  * Sets the power management mode of the pipe and plane.
1825  *
1826  * This code should probably grow support for turning the cursor off and back
1827  * on appropriately at the same time as we're turning the pipe off/on.
1828  */
1829 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1830 {
1831         struct drm_device *dev = crtc->dev;
1832         struct drm_i915_master_private *master_priv;
1833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1834         int pipe = intel_crtc->pipe;
1835         bool enabled;
1836
1837         if (IS_IGDNG(dev))
1838                 igdng_crtc_dpms(crtc, mode);
1839         else
1840                 i9xx_crtc_dpms(crtc, mode);
1841
1842         intel_crtc->dpms_mode = mode;
1843
1844         if (!dev->primary->master)
1845                 return;
1846
1847         master_priv = dev->primary->master->driver_priv;
1848         if (!master_priv->sarea_priv)
1849                 return;
1850
1851         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1852
1853         switch (pipe) {
1854         case 0:
1855                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1856                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1857                 break;
1858         case 1:
1859                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1860                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1861                 break;
1862         default:
1863                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1864                 break;
1865         }
1866 }
1867
1868 static void intel_crtc_prepare (struct drm_crtc *crtc)
1869 {
1870         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1871         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1872 }
1873
1874 static void intel_crtc_commit (struct drm_crtc *crtc)
1875 {
1876         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1877         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1878 }
1879
1880 void intel_encoder_prepare (struct drm_encoder *encoder)
1881 {
1882         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1883         /* lvds has its own version of prepare see intel_lvds_prepare */
1884         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1885 }
1886
1887 void intel_encoder_commit (struct drm_encoder *encoder)
1888 {
1889         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1890         /* lvds has its own version of commit see intel_lvds_commit */
1891         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1892 }
1893
1894 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1895                                   struct drm_display_mode *mode,
1896                                   struct drm_display_mode *adjusted_mode)
1897 {
1898         struct drm_device *dev = crtc->dev;
1899         if (IS_IGDNG(dev)) {
1900                 /* FDI link clock is fixed at 2.7G */
1901                 if (mode->clock * 3 > 27000 * 4)
1902                         return MODE_CLOCK_HIGH;
1903         }
1904         return true;
1905 }
1906
1907
1908 /** Returns the core display clock speed for i830 - i945 */
1909 static int intel_get_core_clock_speed(struct drm_device *dev)
1910 {
1911
1912         /* Core clock values taken from the published datasheets.
1913          * The 830 may go up to 166 Mhz, which we should check.
1914          */
1915         if (IS_I945G(dev))
1916                 return 400000;
1917         else if (IS_I915G(dev))
1918                 return 333000;
1919         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1920                 return 200000;
1921         else if (IS_I915GM(dev)) {
1922                 u16 gcfgc = 0;
1923
1924                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1925
1926                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1927                         return 133000;
1928                 else {
1929                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1930                         case GC_DISPLAY_CLOCK_333_MHZ:
1931                                 return 333000;
1932                         default:
1933                         case GC_DISPLAY_CLOCK_190_200_MHZ:
1934                                 return 190000;
1935                         }
1936                 }
1937         } else if (IS_I865G(dev))
1938                 return 266000;
1939         else if (IS_I855(dev)) {
1940                 u16 hpllcc = 0;
1941                 /* Assume that the hardware is in the high speed state.  This
1942                  * should be the default.
1943                  */
1944                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1945                 case GC_CLOCK_133_200:
1946                 case GC_CLOCK_100_200:
1947                         return 200000;
1948                 case GC_CLOCK_166_250:
1949                         return 250000;
1950                 case GC_CLOCK_100_133:
1951                         return 133000;
1952                 }
1953         } else /* 852, 830 */
1954                 return 133000;
1955
1956         return 0; /* Silence gcc warning */
1957 }
1958
1959 /**
1960  * Return the pipe currently connected to the panel fitter,
1961  * or -1 if the panel fitter is not present or not in use
1962  */
1963 static int intel_panel_fitter_pipe (struct drm_device *dev)
1964 {
1965         struct drm_i915_private *dev_priv = dev->dev_private;
1966         u32  pfit_control;
1967
1968         /* i830 doesn't have a panel fitter */
1969         if (IS_I830(dev))
1970                 return -1;
1971
1972         pfit_control = I915_READ(PFIT_CONTROL);
1973
1974         /* See if the panel fitter is in use */
1975         if ((pfit_control & PFIT_ENABLE) == 0)
1976                 return -1;
1977
1978         /* 965 can place panel fitter on either pipe */
1979         if (IS_I965G(dev))
1980                 return (pfit_control >> 29) & 0x3;
1981
1982         /* older chips can only use pipe 1 */
1983         return 1;
1984 }
1985
1986 struct fdi_m_n {
1987         u32        tu;
1988         u32        gmch_m;
1989         u32        gmch_n;
1990         u32        link_m;
1991         u32        link_n;
1992 };
1993
1994 static void
1995 fdi_reduce_ratio(u32 *num, u32 *den)
1996 {
1997         while (*num > 0xffffff || *den > 0xffffff) {
1998                 *num >>= 1;
1999                 *den >>= 1;
2000         }
2001 }
2002
2003 #define DATA_N 0x800000
2004 #define LINK_N 0x80000
2005
2006 static void
2007 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
2008                 int pixel_clock, int link_clock,
2009                 struct fdi_m_n *m_n)
2010 {
2011         u64 temp;
2012
2013         m_n->tu = 64; /* default size */
2014
2015         temp = (u64) DATA_N * pixel_clock;
2016         temp = div_u64(temp, link_clock);
2017         m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
2018         m_n->gmch_n = DATA_N;
2019         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2020
2021         temp = (u64) LINK_N * pixel_clock;
2022         m_n->link_m = div_u64(temp, link_clock);
2023         m_n->link_n = LINK_N;
2024         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2025 }
2026
2027
2028 struct intel_watermark_params {
2029         unsigned long fifo_size;
2030         unsigned long max_wm;
2031         unsigned long default_wm;
2032         unsigned long guard_size;
2033         unsigned long cacheline_size;
2034 };
2035
2036 /* IGD has different values for various configs */
2037 static struct intel_watermark_params igd_display_wm = {
2038         IGD_DISPLAY_FIFO,
2039         IGD_MAX_WM,
2040         IGD_DFT_WM,
2041         IGD_GUARD_WM,
2042         IGD_FIFO_LINE_SIZE
2043 };
2044 static struct intel_watermark_params igd_display_hplloff_wm = {
2045         IGD_DISPLAY_FIFO,
2046         IGD_MAX_WM,
2047         IGD_DFT_HPLLOFF_WM,
2048         IGD_GUARD_WM,
2049         IGD_FIFO_LINE_SIZE
2050 };
2051 static struct intel_watermark_params igd_cursor_wm = {
2052         IGD_CURSOR_FIFO,
2053         IGD_CURSOR_MAX_WM,
2054         IGD_CURSOR_DFT_WM,
2055         IGD_CURSOR_GUARD_WM,
2056         IGD_FIFO_LINE_SIZE,
2057 };
2058 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2059         IGD_CURSOR_FIFO,
2060         IGD_CURSOR_MAX_WM,
2061         IGD_CURSOR_DFT_WM,
2062         IGD_CURSOR_GUARD_WM,
2063         IGD_FIFO_LINE_SIZE
2064 };
2065 static struct intel_watermark_params i945_wm_info = {
2066         I945_FIFO_SIZE,
2067         I915_MAX_WM,
2068         1,
2069         2,
2070         I915_FIFO_LINE_SIZE
2071 };
2072 static struct intel_watermark_params i915_wm_info = {
2073         I915_FIFO_SIZE,
2074         I915_MAX_WM,
2075         1,
2076         2,
2077         I915_FIFO_LINE_SIZE
2078 };
2079 static struct intel_watermark_params i855_wm_info = {
2080         I855GM_FIFO_SIZE,
2081         I915_MAX_WM,
2082         1,
2083         2,
2084         I830_FIFO_LINE_SIZE
2085 };
2086 static struct intel_watermark_params i830_wm_info = {
2087         I830_FIFO_SIZE,
2088         I915_MAX_WM,
2089         1,
2090         2,
2091         I830_FIFO_LINE_SIZE
2092 };
2093
2094 /**
2095  * intel_calculate_wm - calculate watermark level
2096  * @clock_in_khz: pixel clock
2097  * @wm: chip FIFO params
2098  * @pixel_size: display pixel size
2099  * @latency_ns: memory latency for the platform
2100  *
2101  * Calculate the watermark level (the level at which the display plane will
2102  * start fetching from memory again).  Each chip has a different display
2103  * FIFO size and allocation, so the caller needs to figure that out and pass
2104  * in the correct intel_watermark_params structure.
2105  *
2106  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2107  * on the pixel size.  When it reaches the watermark level, it'll start
2108  * fetching FIFO line sized based chunks from memory until the FIFO fills
2109  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2110  * will occur, and a display engine hang could result.
2111  */
2112 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2113                                         struct intel_watermark_params *wm,
2114                                         int pixel_size,
2115                                         unsigned long latency_ns)
2116 {
2117         long entries_required, wm_size;
2118
2119         entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
2120         entries_required /= wm->cacheline_size;
2121
2122         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2123
2124         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2125
2126         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2127
2128         /* Don't promote wm_size to unsigned... */
2129         if (wm_size > (long)wm->max_wm)
2130                 wm_size = wm->max_wm;
2131         if (wm_size <= 0)
2132                 wm_size = wm->default_wm;
2133         return wm_size;
2134 }
2135
2136 struct cxsr_latency {
2137         int is_desktop;
2138         unsigned long fsb_freq;
2139         unsigned long mem_freq;
2140         unsigned long display_sr;
2141         unsigned long display_hpll_disable;
2142         unsigned long cursor_sr;
2143         unsigned long cursor_hpll_disable;
2144 };
2145
2146 static struct cxsr_latency cxsr_latency_table[] = {
2147         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2148         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2149         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2150
2151         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2152         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2153         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2154
2155         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2156         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2157         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2158
2159         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2160         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2161         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2162
2163         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2164         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2165         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2166
2167         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2168         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2169         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2170 };
2171
2172 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2173                                                    int mem)
2174 {
2175         int i;
2176         struct cxsr_latency *latency;
2177
2178         if (fsb == 0 || mem == 0)
2179                 return NULL;
2180
2181         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2182                 latency = &cxsr_latency_table[i];
2183                 if (is_desktop == latency->is_desktop &&
2184                         fsb == latency->fsb_freq && mem == latency->mem_freq)
2185                         break;
2186         }
2187         if (i >= ARRAY_SIZE(cxsr_latency_table)) {
2188                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2189                 return NULL;
2190         }
2191         return latency;
2192 }
2193
2194 static void igd_disable_cxsr(struct drm_device *dev)
2195 {
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197         u32 reg;
2198
2199         /* deactivate cxsr */
2200         reg = I915_READ(DSPFW3);
2201         reg &= ~(IGD_SELF_REFRESH_EN);
2202         I915_WRITE(DSPFW3, reg);
2203         DRM_INFO("Big FIFO is disabled\n");
2204 }
2205
2206 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2207                             int pixel_size)
2208 {
2209         struct drm_i915_private *dev_priv = dev->dev_private;
2210         u32 reg;
2211         unsigned long wm;
2212         struct cxsr_latency *latency;
2213
2214         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2215                 dev_priv->mem_freq);
2216         if (!latency) {
2217                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2218                 igd_disable_cxsr(dev);
2219                 return;
2220         }
2221
2222         /* Display SR */
2223         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2224                                 latency->display_sr);
2225         reg = I915_READ(DSPFW1);
2226         reg &= 0x7fffff;
2227         reg |= wm << 23;
2228         I915_WRITE(DSPFW1, reg);
2229         DRM_DEBUG("DSPFW1 register is %x\n", reg);
2230
2231         /* cursor SR */
2232         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2233                                 latency->cursor_sr);
2234         reg = I915_READ(DSPFW3);
2235         reg &= ~(0x3f << 24);
2236         reg |= (wm & 0x3f) << 24;
2237         I915_WRITE(DSPFW3, reg);
2238
2239         /* Display HPLL off SR */
2240         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2241                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2242         reg = I915_READ(DSPFW3);
2243         reg &= 0xfffffe00;
2244         reg |= wm & 0x1ff;
2245         I915_WRITE(DSPFW3, reg);
2246
2247         /* cursor HPLL off SR */
2248         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2249                                 latency->cursor_hpll_disable);
2250         reg = I915_READ(DSPFW3);
2251         reg &= ~(0x3f << 16);
2252         reg |= (wm & 0x3f) << 16;
2253         I915_WRITE(DSPFW3, reg);
2254         DRM_DEBUG("DSPFW3 register is %x\n", reg);
2255
2256         /* activate cxsr */
2257         reg = I915_READ(DSPFW3);
2258         reg |= IGD_SELF_REFRESH_EN;
2259         I915_WRITE(DSPFW3, reg);
2260
2261         DRM_INFO("Big FIFO is enabled\n");
2262
2263         return;
2264 }
2265
2266 /*
2267  * Latency for FIFO fetches is dependent on several factors:
2268  *   - memory configuration (speed, channels)
2269  *   - chipset
2270  *   - current MCH state
2271  * It can be fairly high in some situations, so here we assume a fairly
2272  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2273  * set this value too high, the FIFO will fetch frequently to stay full)
2274  * and power consumption (set it too low to save power and we might see
2275  * FIFO underruns and display "flicker").
2276  *
2277  * A value of 5us seems to be a good balance; safe for very low end
2278  * platforms but not overly aggressive on lower latency configs.
2279  */
2280 const static int latency_ns = 5000;
2281
2282 static int intel_get_fifo_size(struct drm_device *dev, int plane)
2283 {
2284         struct drm_i915_private *dev_priv = dev->dev_private;
2285         uint32_t dsparb = I915_READ(DSPARB);
2286         int size;
2287
2288         if (IS_I9XX(dev)) {
2289                 if (plane == 0)
2290                         size = dsparb & 0x7f;
2291                 else
2292                         size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2293                                 (dsparb & 0x7f);
2294         } else if (IS_I85X(dev)) {
2295                 if (plane == 0)
2296                         size = dsparb & 0x1ff;
2297                 else
2298                         size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2299                                 (dsparb & 0x1ff);
2300                 size >>= 1; /* Convert to cachelines */
2301         } else if (IS_845G(dev)) {
2302                 size = dsparb & 0x7f;
2303                 size >>= 2; /* Convert to cachelines */
2304         } else {
2305                 size = dsparb & 0x7f;
2306                 size >>= 1; /* Convert to cachelines */
2307         }
2308
2309         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2310                   size);
2311
2312         return size;
2313 }
2314
2315 static void g4x_update_wm(struct drm_device *dev)
2316 {
2317         struct drm_i915_private *dev_priv = dev->dev_private;
2318         u32 fw_blc_self = I915_READ(FW_BLC_SELF);
2319
2320         if (i915_powersave)
2321                 fw_blc_self |= FW_BLC_SELF_EN;
2322         else
2323                 fw_blc_self &= ~FW_BLC_SELF_EN;
2324         I915_WRITE(FW_BLC_SELF, fw_blc_self);
2325 }
2326
2327 static void i965_update_wm(struct drm_device *dev)
2328 {
2329         struct drm_i915_private *dev_priv = dev->dev_private;
2330
2331         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2332
2333         /* 965 has limitations... */
2334         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2335         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2336 }
2337
2338 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2339                            int planeb_clock, int sr_hdisplay, int pixel_size)
2340 {
2341         struct drm_i915_private *dev_priv = dev->dev_private;
2342         uint32_t fwater_lo;
2343         uint32_t fwater_hi;
2344         int total_size, cacheline_size, cwm, srwm = 1;
2345         int planea_wm, planeb_wm;
2346         struct intel_watermark_params planea_params, planeb_params;
2347         unsigned long line_time_us;
2348         int sr_clock, sr_entries = 0;
2349
2350         /* Create copies of the base settings for each pipe */
2351         if (IS_I965GM(dev) || IS_I945GM(dev))
2352                 planea_params = planeb_params = i945_wm_info;
2353         else if (IS_I9XX(dev))
2354                 planea_params = planeb_params = i915_wm_info;
2355         else
2356                 planea_params = planeb_params = i855_wm_info;
2357
2358         /* Grab a couple of global values before we overwrite them */
2359         total_size = planea_params.fifo_size;
2360         cacheline_size = planea_params.cacheline_size;
2361
2362         /* Update per-plane FIFO sizes */
2363         planea_params.fifo_size = intel_get_fifo_size(dev, 0);
2364         planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
2365
2366         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2367                                        pixel_size, latency_ns);
2368         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2369                                        pixel_size, latency_ns);
2370         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2371
2372         /*
2373          * Overlay gets an aggressive default since video jitter is bad.
2374          */
2375         cwm = 2;
2376
2377         /* Calc sr entries for one plane configs */
2378         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2379             (!planea_clock || !planeb_clock)) {
2380                 /* self-refresh has much higher latency */
2381                 const static int sr_latency_ns = 6000;
2382
2383                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2384                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2385
2386                 /* Use ns/us then divide to preserve precision */
2387                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2388                               pixel_size * sr_hdisplay) / 1000;
2389                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2390                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2391                 srwm = total_size - sr_entries;
2392                 if (srwm < 0)
2393                         srwm = 1;
2394                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2395         }
2396
2397         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2398                   planea_wm, planeb_wm, cwm, srwm);
2399
2400         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2401         fwater_hi = (cwm & 0x1f);
2402
2403         /* Set request length to 8 cachelines per fetch */
2404         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2405         fwater_hi = fwater_hi | (1 << 8);
2406
2407         I915_WRITE(FW_BLC, fwater_lo);
2408         I915_WRITE(FW_BLC2, fwater_hi);
2409 }
2410
2411 static void i830_update_wm(struct drm_device *dev, int planea_clock,
2412                            int pixel_size)
2413 {
2414         struct drm_i915_private *dev_priv = dev->dev_private;
2415         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2416         int planea_wm;
2417
2418         i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
2419
2420         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2421                                        pixel_size, latency_ns);
2422         fwater_lo |= (3<<8) | planea_wm;
2423
2424         DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2425
2426         I915_WRITE(FW_BLC, fwater_lo);
2427 }
2428
2429 /**
2430  * intel_update_watermarks - update FIFO watermark values based on current modes
2431  *
2432  * Calculate watermark values for the various WM regs based on current mode
2433  * and plane configuration.
2434  *
2435  * There are several cases to deal with here:
2436  *   - normal (i.e. non-self-refresh)
2437  *   - self-refresh (SR) mode
2438  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2439  *   - lines are small relative to FIFO size (buffer can hold more than 2
2440  *     lines), so need to account for TLB latency
2441  *
2442  *   The normal calculation is:
2443  *     watermark = dotclock * bytes per pixel * latency
2444  *   where latency is platform & configuration dependent (we assume pessimal
2445  *   values here).
2446  *
2447  *   The SR calculation is:
2448  *     watermark = (trunc(latency/line time)+1) * surface width *
2449  *       bytes per pixel
2450  *   where
2451  *     line time = htotal / dotclock
2452  *   and latency is assumed to be high, as above.
2453  *
2454  * The final value programmed to the register should always be rounded up,
2455  * and include an extra 2 entries to account for clock crossings.
2456  *
2457  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2458  * to set the non-SR watermarks to 8.
2459   */
2460 static void intel_update_watermarks(struct drm_device *dev)
2461 {
2462         struct drm_crtc *crtc;
2463         struct intel_crtc *intel_crtc;
2464         int sr_hdisplay = 0;
2465         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2466         int enabled = 0, pixel_size = 0;
2467
2468         /* Get the clock config from both planes */
2469         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2470                 intel_crtc = to_intel_crtc(crtc);
2471                 if (crtc->enabled) {
2472                         enabled++;
2473                         if (intel_crtc->plane == 0) {
2474                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2475                                           intel_crtc->pipe, crtc->mode.clock);
2476                                 planea_clock = crtc->mode.clock;
2477                         } else {
2478                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2479                                           intel_crtc->pipe, crtc->mode.clock);
2480                                 planeb_clock = crtc->mode.clock;
2481                         }
2482                         sr_hdisplay = crtc->mode.hdisplay;
2483                         sr_clock = crtc->mode.clock;
2484                         if (crtc->fb)
2485                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2486                         else
2487                                 pixel_size = 4; /* by default */
2488                 }
2489         }
2490
2491         if (enabled <= 0)
2492                 return;
2493
2494         /* Single plane configs can enable self refresh */
2495         if (enabled == 1 && IS_IGD(dev))
2496                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2497         else if (IS_IGD(dev))
2498                 igd_disable_cxsr(dev);
2499
2500         if (IS_G4X(dev))
2501                 g4x_update_wm(dev);
2502         else if (IS_I965G(dev))
2503                 i965_update_wm(dev);
2504         else if (IS_I9XX(dev) || IS_MOBILE(dev))
2505                 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
2506                                pixel_size);
2507         else
2508                 i830_update_wm(dev, planea_clock, pixel_size);
2509 }
2510
2511 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2512                                struct drm_display_mode *mode,
2513                                struct drm_display_mode *adjusted_mode,
2514                                int x, int y,
2515                                struct drm_framebuffer *old_fb)
2516 {
2517         struct drm_device *dev = crtc->dev;
2518         struct drm_i915_private *dev_priv = dev->dev_private;
2519         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2520         int pipe = intel_crtc->pipe;
2521         int plane = intel_crtc->plane;
2522         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2523         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2524         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2525         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2526         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2527         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2528         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2529         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2530         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2531         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2532         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2533         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2534         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2535         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2536         int refclk, num_outputs = 0;
2537         intel_clock_t clock, reduced_clock;
2538         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2539         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2540         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2541         bool is_edp = false;
2542         struct drm_mode_config *mode_config = &dev->mode_config;
2543         struct drm_connector *connector;
2544         const intel_limit_t *limit;
2545         int ret;
2546         struct fdi_m_n m_n = {0};
2547         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2548         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2549         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2550         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2551         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2552         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2553         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2554         int lvds_reg = LVDS;
2555         u32 temp;
2556         int sdvo_pixel_multiply;
2557         int target_clock;
2558
2559         drm_vblank_pre_modeset(dev, pipe);
2560
2561         list_for_each_entry(connector, &mode_config->connector_list, head) {
2562                 struct intel_output *intel_output = to_intel_output(connector);
2563
2564                 if (!connector->encoder || connector->encoder->crtc != crtc)
2565                         continue;
2566
2567                 switch (intel_output->type) {
2568                 case INTEL_OUTPUT_LVDS:
2569                         is_lvds = true;
2570                         break;
2571                 case INTEL_OUTPUT_SDVO:
2572                 case INTEL_OUTPUT_HDMI:
2573                         is_sdvo = true;
2574                         if (intel_output->needs_tv_clock)
2575                                 is_tv = true;
2576                         break;
2577                 case INTEL_OUTPUT_DVO:
2578                         is_dvo = true;
2579                         break;
2580                 case INTEL_OUTPUT_TVOUT:
2581                         is_tv = true;
2582                         break;
2583                 case INTEL_OUTPUT_ANALOG:
2584                         is_crt = true;
2585                         break;
2586                 case INTEL_OUTPUT_DISPLAYPORT:
2587                         is_dp = true;
2588                         break;
2589                 case INTEL_OUTPUT_EDP:
2590                         is_edp = true;
2591                         break;
2592                 }
2593
2594                 num_outputs++;
2595         }
2596
2597         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2598                 refclk = dev_priv->lvds_ssc_freq * 1000;
2599                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2600         } else if (IS_I9XX(dev)) {
2601                 refclk = 96000;
2602                 if (IS_IGDNG(dev))
2603                         refclk = 120000; /* 120Mhz refclk */
2604         } else {
2605                 refclk = 48000;
2606         }
2607
2608
2609         /*
2610          * Returns a set of divisors for the desired target clock with the given
2611          * refclk, or FALSE.  The returned values represent the clock equation:
2612          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2613          */
2614         limit = intel_limit(crtc);
2615         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2616         if (!ok) {
2617                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2618                 drm_vblank_post_modeset(dev, pipe);
2619                 return -EINVAL;
2620         }
2621
2622         if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2623                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2624                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2625                                                             (adjusted_mode->clock*3/4),
2626                                                             refclk,
2627                                                             &reduced_clock);
2628         }
2629
2630         /* SDVO TV has fixed PLL values depend on its clock range,
2631            this mirrors vbios setting. */
2632         if (is_sdvo && is_tv) {
2633                 if (adjusted_mode->clock >= 100000
2634                                 && adjusted_mode->clock < 140500) {
2635                         clock.p1 = 2;
2636                         clock.p2 = 10;
2637                         clock.n = 3;
2638                         clock.m1 = 16;
2639                         clock.m2 = 8;
2640                 } else if (adjusted_mode->clock >= 140500
2641                                 && adjusted_mode->clock <= 200000) {
2642                         clock.p1 = 1;
2643                         clock.p2 = 10;
2644                         clock.n = 6;
2645                         clock.m1 = 12;
2646                         clock.m2 = 8;
2647                 }
2648         }
2649
2650         /* FDI link */
2651         if (IS_IGDNG(dev)) {
2652                 int lane, link_bw;
2653                 /* eDP doesn't require FDI link, so just set DP M/N
2654                    according to current link config */
2655                 if (is_edp) {
2656                         struct drm_connector *edp;
2657                         target_clock = mode->clock;
2658                         edp = intel_pipe_get_output(crtc);
2659                         intel_edp_link_config(to_intel_output(edp),
2660                                         &lane, &link_bw);
2661                 } else {
2662                         /* DP over FDI requires target mode clock
2663                            instead of link clock */
2664                         if (is_dp)
2665                                 target_clock = mode->clock;
2666                         else
2667                                 target_clock = adjusted_mode->clock;
2668                         lane = 4;
2669                         link_bw = 270000;
2670                 }
2671                 igdng_compute_m_n(3, lane, target_clock,
2672                                   link_bw, &m_n);
2673         }
2674
2675         if (IS_IGD(dev)) {
2676                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2677                 if (has_reduced_clock)
2678                         fp2 = (1 << reduced_clock.n) << 16 |
2679                                 reduced_clock.m1 << 8 | reduced_clock.m2;
2680         } else {
2681                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2682                 if (has_reduced_clock)
2683                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2684                                 reduced_clock.m2;
2685         }
2686
2687         if (!IS_IGDNG(dev))
2688                 dpll = DPLL_VGA_MODE_DIS;
2689
2690         if (IS_I9XX(dev)) {
2691                 if (is_lvds)
2692                         dpll |= DPLLB_MODE_LVDS;
2693                 else
2694                         dpll |= DPLLB_MODE_DAC_SERIAL;
2695                 if (is_sdvo) {
2696                         dpll |= DPLL_DVO_HIGH_SPEED;
2697                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2698                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2699                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2700                         else if (IS_IGDNG(dev))
2701                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2702                 }
2703                 if (is_dp)
2704                         dpll |= DPLL_DVO_HIGH_SPEED;
2705
2706                 /* compute bitmask from p1 value */
2707                 if (IS_IGD(dev))
2708                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2709                 else {
2710                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2711                         /* also FPA1 */
2712                         if (IS_IGDNG(dev))
2713                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2714                         if (IS_G4X(dev) && has_reduced_clock)
2715                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2716                 }
2717                 switch (clock.p2) {
2718                 case 5:
2719                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2720                         break;
2721                 case 7:
2722                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2723                         break;
2724                 case 10:
2725                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2726                         break;
2727                 case 14:
2728                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2729                         break;
2730                 }
2731                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2732                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2733         } else {
2734                 if (is_lvds) {
2735                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2736                 } else {
2737                         if (clock.p1 == 2)
2738                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
2739                         else
2740                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2741                         if (clock.p2 == 4)
2742                                 dpll |= PLL_P2_DIVIDE_BY_4;
2743                 }
2744         }
2745
2746         if (is_sdvo && is_tv)
2747                 dpll |= PLL_REF_INPUT_TVCLKINBC;
2748         else if (is_tv)
2749                 /* XXX: just matching BIOS for now */
2750                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
2751                 dpll |= 3;
2752         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2753                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2754         else
2755                 dpll |= PLL_REF_INPUT_DREFCLK;
2756
2757         /* setup pipeconf */
2758         pipeconf = I915_READ(pipeconf_reg);
2759
2760         /* Set up the display plane register */
2761         dspcntr = DISPPLANE_GAMMA_ENABLE;
2762
2763         /* IGDNG's plane is forced to pipe, bit 24 is to
2764            enable color space conversion */
2765         if (!IS_IGDNG(dev)) {
2766                 if (pipe == 0)
2767                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
2768                 else
2769                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2770         }
2771
2772         if (pipe == 0 && !IS_I965G(dev)) {
2773                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2774                  * core speed.
2775                  *
2776                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2777                  * pipe == 0 check?
2778                  */
2779                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2780                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
2781                 else
2782                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2783         }
2784
2785         dspcntr |= DISPLAY_PLANE_ENABLE;
2786         pipeconf |= PIPEACONF_ENABLE;
2787         dpll |= DPLL_VCO_ENABLE;
2788
2789
2790         /* Disable the panel fitter if it was on our pipe */
2791         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2792                 I915_WRITE(PFIT_CONTROL, 0);
2793
2794         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2795         drm_mode_debug_printmodeline(mode);
2796
2797         /* assign to IGDNG registers */
2798         if (IS_IGDNG(dev)) {
2799                 fp_reg = pch_fp_reg;
2800                 dpll_reg = pch_dpll_reg;
2801         }
2802
2803         if (is_edp) {
2804                 igdng_disable_pll_edp(crtc);
2805         } else if ((dpll & DPLL_VCO_ENABLE)) {
2806                 I915_WRITE(fp_reg, fp);
2807                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2808                 I915_READ(dpll_reg);
2809                 udelay(150);
2810         }
2811
2812         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2813          * This is an exception to the general rule that mode_set doesn't turn
2814          * things on.
2815          */
2816         if (is_lvds) {
2817                 u32 lvds;
2818
2819                 if (IS_IGDNG(dev))
2820                         lvds_reg = PCH_LVDS;
2821
2822                 lvds = I915_READ(lvds_reg);
2823                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2824                 /* Set the B0-B3 data pairs corresponding to whether we're going to
2825                  * set the DPLLs for dual-channel mode or not.
2826                  */
2827                 if (clock.p2 == 7)
2828                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2829                 else
2830                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2831
2832                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2833                  * appropriately here, but we need to look more thoroughly into how
2834                  * panels behave in the two modes.
2835                  */
2836
2837                 I915_WRITE(lvds_reg, lvds);
2838                 I915_READ(lvds_reg);
2839         }
2840         if (is_dp)
2841                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2842
2843         if (!is_edp) {
2844                 I915_WRITE(fp_reg, fp);
2845                 I915_WRITE(dpll_reg, dpll);
2846                 I915_READ(dpll_reg);
2847                 /* Wait for the clocks to stabilize. */
2848                 udelay(150);
2849
2850                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2851                         if (is_sdvo) {
2852                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2853                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2854                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2855                         } else
2856                                 I915_WRITE(dpll_md_reg, 0);
2857                 } else {
2858                         /* write it again -- the BIOS does, after all */
2859                         I915_WRITE(dpll_reg, dpll);
2860                 }
2861                 I915_READ(dpll_reg);
2862                 /* Wait for the clocks to stabilize. */
2863                 udelay(150);
2864         }
2865
2866         if (is_lvds && has_reduced_clock && i915_powersave) {
2867                 I915_WRITE(fp_reg + 4, fp2);
2868                 intel_crtc->lowfreq_avail = true;
2869                 if (HAS_PIPE_CXSR(dev)) {
2870                         DRM_DEBUG("enabling CxSR downclocking\n");
2871                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
2872                 }
2873         } else {
2874                 I915_WRITE(fp_reg + 4, fp);
2875                 intel_crtc->lowfreq_avail = false;
2876                 if (HAS_PIPE_CXSR(dev)) {
2877                         DRM_DEBUG("disabling CxSR downclocking\n");
2878                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
2879                 }
2880         }
2881
2882         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2883                    ((adjusted_mode->crtc_htotal - 1) << 16));
2884         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2885                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
2886         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2887                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
2888         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2889                    ((adjusted_mode->crtc_vtotal - 1) << 16));
2890         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2891                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
2892         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2893                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
2894         /* pipesrc and dspsize control the size that is scaled from, which should
2895          * always be the user's requested size.
2896          */
2897         if (!IS_IGDNG(dev)) {
2898                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2899                                 (mode->hdisplay - 1));
2900                 I915_WRITE(dsppos_reg, 0);
2901         }
2902         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2903
2904         if (IS_IGDNG(dev)) {
2905                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2906                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2907                 I915_WRITE(link_m1_reg, m_n.link_m);
2908                 I915_WRITE(link_n1_reg, m_n.link_n);
2909
2910                 if (is_edp) {
2911                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
2912                 } else {
2913                         /* enable FDI RX PLL too */
2914                         temp = I915_READ(fdi_rx_reg);
2915                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2916                         udelay(200);
2917                 }
2918         }
2919
2920         I915_WRITE(pipeconf_reg, pipeconf);
2921         I915_READ(pipeconf_reg);
2922
2923         intel_wait_for_vblank(dev);
2924
2925         if (IS_IGDNG(dev)) {
2926                 /* enable address swizzle for tiling buffer */
2927                 temp = I915_READ(DISP_ARB_CTL);
2928                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
2929         }
2930
2931         I915_WRITE(dspcntr_reg, dspcntr);
2932
2933         /* Flush the plane changes */
2934         ret = intel_pipe_set_base(crtc, x, y, old_fb);
2935
2936         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
2937                 intel_update_fbc(crtc, &crtc->mode);
2938         intel_update_watermarks(dev);
2939
2940         drm_vblank_post_modeset(dev, pipe);
2941
2942         return ret;
2943 }
2944
2945 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2946 void intel_crtc_load_lut(struct drm_crtc *crtc)
2947 {
2948         struct drm_device *dev = crtc->dev;
2949         struct drm_i915_private *dev_priv = dev->dev_private;
2950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2951         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2952         int i;
2953
2954         /* The clocks have to be on to load the palette. */
2955         if (!crtc->enabled)
2956                 return;
2957
2958         /* use legacy palette for IGDNG */
2959         if (IS_IGDNG(dev))
2960                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2961                                                    LGC_PALETTE_B;
2962
2963         for (i = 0; i < 256; i++) {
2964                 I915_WRITE(palreg + 4 * i,
2965                            (intel_crtc->lut_r[i] << 16) |
2966                            (intel_crtc->lut_g[i] << 8) |
2967                            intel_crtc->lut_b[i]);
2968         }
2969 }
2970
2971 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2972                                  struct drm_file *file_priv,
2973                                  uint32_t handle,
2974                                  uint32_t width, uint32_t height)
2975 {
2976         struct drm_device *dev = crtc->dev;
2977         struct drm_i915_private *dev_priv = dev->dev_private;
2978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2979         struct drm_gem_object *bo;
2980         struct drm_i915_gem_object *obj_priv;
2981         int pipe = intel_crtc->pipe;
2982         int plane = intel_crtc->plane;
2983         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2984         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
2985         uint32_t temp = I915_READ(control);
2986         size_t addr;
2987         int ret;
2988
2989         DRM_DEBUG("\n");
2990
2991         /* if we want to turn off the cursor ignore width and height */
2992         if (!handle) {
2993                 DRM_DEBUG("cursor off\n");
2994                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2995                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2996                         temp |= CURSOR_MODE_DISABLE;
2997                 } else {
2998                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2999                 }
3000                 addr = 0;
3001                 bo = NULL;
3002                 mutex_lock(&dev->struct_mutex);
3003                 goto finish;
3004         }
3005
3006         /* Currently we only support 64x64 cursors */
3007         if (width != 64 || height != 64) {
3008                 DRM_ERROR("we currently only support 64x64 cursors\n");
3009                 return -EINVAL;
3010         }
3011
3012         bo = drm_gem_object_lookup(dev, file_priv, handle);
3013         if (!bo)
3014                 return -ENOENT;
3015
3016         obj_priv = bo->driver_private;
3017
3018         if (bo->size < width * height * 4) {
3019                 DRM_ERROR("buffer is to small\n");
3020                 ret = -ENOMEM;
3021                 goto fail;
3022         }
3023
3024         /* we only need to pin inside GTT if cursor is non-phy */
3025         mutex_lock(&dev->struct_mutex);
3026         if (!dev_priv->cursor_needs_physical) {
3027                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3028                 if (ret) {
3029                         DRM_ERROR("failed to pin cursor bo\n");
3030                         goto fail_locked;
3031                 }
3032                 addr = obj_priv->gtt_offset;
3033         } else {
3034                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3035                 if (ret) {
3036                         DRM_ERROR("failed to attach phys object\n");
3037                         goto fail_locked;
3038                 }
3039                 addr = obj_priv->phys_obj->handle->busaddr;
3040         }
3041
3042         if (!IS_I9XX(dev))
3043                 I915_WRITE(CURSIZE, (height << 12) | width);
3044
3045         /* Hooray for CUR*CNTR differences */
3046         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3047                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3048                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3049                 temp |= (pipe << 28); /* Connect to correct pipe */
3050         } else {
3051                 temp &= ~(CURSOR_FORMAT_MASK);
3052                 temp |= CURSOR_ENABLE;
3053                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3054         }
3055
3056  finish:
3057         I915_WRITE(control, temp);
3058         I915_WRITE(base, addr);
3059
3060         if (intel_crtc->cursor_bo) {
3061                 if (dev_priv->cursor_needs_physical) {
3062                         if (intel_crtc->cursor_bo != bo)
3063                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3064                 } else
3065                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3066                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3067         }
3068
3069         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
3070                 intel_update_fbc(crtc, &crtc->mode);
3071
3072         mutex_unlock(&dev->struct_mutex);
3073
3074         intel_crtc->cursor_addr = addr;
3075         intel_crtc->cursor_bo = bo;
3076
3077         return 0;
3078 fail:
3079         mutex_lock(&dev->struct_mutex);
3080 fail_locked:
3081         drm_gem_object_unreference(bo);
3082         mutex_unlock(&dev->struct_mutex);
3083         return ret;
3084 }
3085
3086 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3087 {
3088         struct drm_device *dev = crtc->dev;
3089         struct drm_i915_private *dev_priv = dev->dev_private;
3090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3091         struct intel_framebuffer *intel_fb;
3092         int pipe = intel_crtc->pipe;
3093         uint32_t temp = 0;
3094         uint32_t adder;
3095
3096         if (crtc->fb) {
3097                 intel_fb = to_intel_framebuffer(crtc->fb);
3098                 intel_mark_busy(dev, intel_fb->obj);
3099         }
3100
3101         if (x < 0) {
3102                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3103                 x = -x;
3104         }
3105         if (y < 0) {
3106                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3107                 y = -y;
3108         }
3109
3110         temp |= x << CURSOR_X_SHIFT;
3111         temp |= y << CURSOR_Y_SHIFT;
3112
3113         adder = intel_crtc->cursor_addr;
3114         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3115         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3116
3117         return 0;
3118 }
3119
3120 /** Sets the color ramps on behalf of RandR */
3121 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3122                                  u16 blue, int regno)
3123 {
3124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3125
3126         intel_crtc->lut_r[regno] = red >> 8;
3127         intel_crtc->lut_g[regno] = green >> 8;
3128         intel_crtc->lut_b[regno] = blue >> 8;
3129 }
3130
3131 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3132                                  u16 *blue, uint32_t size)
3133 {
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3135         int i;
3136
3137         if (size != 256)
3138                 return;
3139
3140         for (i = 0; i < 256; i++) {
3141                 intel_crtc->lut_r[i] = red[i] >> 8;
3142                 intel_crtc->lut_g[i] = green[i] >> 8;
3143                 intel_crtc->lut_b[i] = blue[i] >> 8;
3144         }
3145
3146         intel_crtc_load_lut(crtc);
3147 }
3148
3149 /**
3150  * Get a pipe with a simple mode set on it for doing load-based monitor
3151  * detection.
3152  *
3153  * It will be up to the load-detect code to adjust the pipe as appropriate for
3154  * its requirements.  The pipe will be connected to no other outputs.
3155  *
3156  * Currently this code will only succeed if there is a pipe with no outputs
3157  * configured for it.  In the future, it could choose to temporarily disable
3158  * some outputs to free up a pipe for its use.
3159  *
3160  * \return crtc, or NULL if no pipes are available.
3161  */
3162
3163 /* VESA 640x480x72Hz mode to set on the pipe */
3164 static struct drm_display_mode load_detect_mode = {
3165         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3166                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3167 };
3168
3169 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3170                                             struct drm_display_mode *mode,
3171                                             int *dpms_mode)
3172 {
3173         struct intel_crtc *intel_crtc;
3174         struct drm_crtc *possible_crtc;
3175         struct drm_crtc *supported_crtc =NULL;
3176         struct drm_encoder *encoder = &intel_output->enc;
3177         struct drm_crtc *crtc = NULL;
3178         struct drm_device *dev = encoder->dev;
3179         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3180         struct drm_crtc_helper_funcs *crtc_funcs;
3181         int i = -1;
3182
3183         /*
3184          * Algorithm gets a little messy:
3185          *   - if the connector already has an assigned crtc, use it (but make
3186          *     sure it's on first)
3187          *   - try to find the first unused crtc that can drive this connector,
3188          *     and use that if we find one
3189          *   - if there are no unused crtcs available, try to use the first
3190          *     one we found that supports the connector
3191          */
3192
3193         /* See if we already have a CRTC for this connector */
3194         if (encoder->crtc) {
3195                 crtc = encoder->crtc;
3196                 /* Make sure the crtc and connector are running */
3197                 intel_crtc = to_intel_crtc(crtc);
3198                 *dpms_mode = intel_crtc->dpms_mode;
3199                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3200                         crtc_funcs = crtc->helper_private;
3201                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3202                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3203                 }
3204                 return crtc;
3205         }
3206
3207         /* Find an unused one (if possible) */
3208         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3209                 i++;
3210                 if (!(encoder->possible_crtcs & (1 << i)))
3211                         continue;
3212                 if (!possible_crtc->enabled) {
3213                         crtc = possible_crtc;
3214                         break;
3215                 }
3216                 if (!supported_crtc)
3217                         supported_crtc = possible_crtc;
3218         }
3219
3220         /*
3221          * If we didn't find an unused CRTC, don't use any.
3222          */
3223         if (!crtc) {
3224                 return NULL;
3225         }
3226
3227         encoder->crtc = crtc;
3228         intel_output->base.encoder = encoder;
3229         intel_output->load_detect_temp = true;
3230
3231         intel_crtc = to_intel_crtc(crtc);
3232         *dpms_mode = intel_crtc->dpms_mode;
3233
3234         if (!crtc->enabled) {
3235                 if (!mode)
3236                         mode = &load_detect_mode;
3237                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3238         } else {
3239                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3240                         crtc_funcs = crtc->helper_private;
3241                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3242                 }
3243
3244                 /* Add this connector to the crtc */
3245                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3246                 encoder_funcs->commit(encoder);
3247         }
3248         /* let the connector get through one full cycle before testing */
3249         intel_wait_for_vblank(dev);
3250
3251         return crtc;
3252 }
3253
3254 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3255 {
3256         struct drm_encoder *encoder = &intel_output->enc;
3257         struct drm_device *dev = encoder->dev;
3258         struct drm_crtc *crtc = encoder->crtc;
3259         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3260         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3261
3262         if (intel_output->load_detect_temp) {
3263                 encoder->crtc = NULL;
3264                 intel_output->base.encoder = NULL;
3265                 intel_output->load_detect_temp = false;
3266                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3267                 drm_helper_disable_unused_functions(dev);
3268         }
3269
3270         /* Switch crtc and output back off if necessary */
3271         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3272                 if (encoder->crtc == crtc)
3273                         encoder_funcs->dpms(encoder, dpms_mode);
3274                 crtc_funcs->dpms(crtc, dpms_mode);
3275         }
3276 }
3277
3278 /* Returns the clock of the currently programmed mode of the given pipe. */
3279 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3280 {
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3283         int pipe = intel_crtc->pipe;
3284         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3285         u32 fp;
3286         intel_clock_t clock;
3287
3288         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3289                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3290         else
3291                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3292
3293         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3294         if (IS_IGD(dev)) {
3295                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3296                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3297         } else {
3298                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3299                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3300         }
3301
3302         if (IS_I9XX(dev)) {
3303                 if (IS_IGD(dev))
3304                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3305                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3306                 else
3307                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3308                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3309
3310                 switch (dpll & DPLL_MODE_MASK) {
3311                 case DPLLB_MODE_DAC_SERIAL:
3312                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3313                                 5 : 10;
3314                         break;
3315                 case DPLLB_MODE_LVDS:
3316                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3317                                 7 : 14;
3318                         break;
3319                 default:
3320                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3321                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3322                         return 0;
3323                 }
3324
3325                 /* XXX: Handle the 100Mhz refclk */
3326                 intel_clock(dev, 96000, &clock);
3327         } else {
3328                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3329
3330                 if (is_lvds) {
3331                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3332                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3333                         clock.p2 = 14;
3334
3335                         if ((dpll & PLL_REF_INPUT_MASK) ==
3336                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3337                                 /* XXX: might not be 66MHz */
3338                                 intel_clock(dev, 66000, &clock);
3339                         } else
3340                                 intel_clock(dev, 48000, &clock);
3341                 } else {
3342                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3343                                 clock.p1 = 2;
3344                         else {
3345                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3346                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3347                         }
3348                         if (dpll & PLL_P2_DIVIDE_BY_4)
3349                                 clock.p2 = 4;
3350                         else
3351                                 clock.p2 = 2;
3352
3353                         intel_clock(dev, 48000, &clock);
3354                 }
3355         }
3356
3357         /* XXX: It would be nice to validate the clocks, but we can't reuse
3358          * i830PllIsValid() because it relies on the xf86_config connector
3359          * configuration being accurate, which it isn't necessarily.
3360          */
3361
3362         return clock.dot;
3363 }
3364
3365 /** Returns the currently programmed mode of the given pipe. */
3366 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3367                                              struct drm_crtc *crtc)
3368 {
3369         struct drm_i915_private *dev_priv = dev->dev_private;
3370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3371         int pipe = intel_crtc->pipe;
3372         struct drm_display_mode *mode;
3373         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3374         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3375         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3376         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3377
3378         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3379         if (!mode)
3380                 return NULL;
3381
3382         mode->clock = intel_crtc_clock_get(dev, crtc);
3383         mode->hdisplay = (htot & 0xffff) + 1;
3384         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3385         mode->hsync_start = (hsync & 0xffff) + 1;
3386         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3387         mode->vdisplay = (vtot & 0xffff) + 1;
3388         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3389         mode->vsync_start = (vsync & 0xffff) + 1;
3390         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3391
3392         drm_mode_set_name(mode);
3393         drm_mode_set_crtcinfo(mode, 0);
3394
3395         return mode;
3396 }
3397
3398 #define GPU_IDLE_TIMEOUT 500 /* ms */
3399
3400 /* When this timer fires, we've been idle for awhile */
3401 static void intel_gpu_idle_timer(unsigned long arg)
3402 {
3403         struct drm_device *dev = (struct drm_device *)arg;
3404         drm_i915_private_t *dev_priv = dev->dev_private;
3405
3406         DRM_DEBUG("idle timer fired, downclocking\n");
3407
3408         dev_priv->busy = false;
3409
3410         queue_work(dev_priv->wq, &dev_priv->idle_work);
3411 }
3412
3413 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3414 {
3415         drm_i915_private_t *dev_priv = dev->dev_private;
3416
3417         if (IS_IGDNG(dev))
3418                 return;
3419
3420         if (!dev_priv->render_reclock_avail) {
3421                 DRM_DEBUG("not reclocking render clock\n");
3422                 return;
3423         }
3424
3425         /* Restore render clock frequency to original value */
3426         if (IS_G4X(dev) || IS_I9XX(dev))
3427                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3428         else if (IS_I85X(dev))
3429                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3430         DRM_DEBUG("increasing render clock frequency\n");
3431
3432         /* Schedule downclock */
3433         if (schedule)
3434                 mod_timer(&dev_priv->idle_timer, jiffies +
3435                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3436 }
3437
3438 void intel_decrease_renderclock(struct drm_device *dev)
3439 {
3440         drm_i915_private_t *dev_priv = dev->dev_private;
3441
3442         if (IS_IGDNG(dev))
3443                 return;
3444
3445         if (!dev_priv->render_reclock_avail) {
3446                 DRM_DEBUG("not reclocking render clock\n");
3447                 return;
3448         }
3449
3450         if (IS_G4X(dev)) {
3451                 u16 gcfgc;
3452
3453                 /* Adjust render clock... */
3454                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3455
3456                 /* Down to minimum... */
3457                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3458                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3459
3460                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3461         } else if (IS_I965G(dev)) {
3462                 u16 gcfgc;
3463
3464                 /* Adjust render clock... */
3465                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3466
3467                 /* Down to minimum... */
3468                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3469                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3470
3471                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3472         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3473                 u16 gcfgc;
3474
3475                 /* Adjust render clock... */
3476                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3477
3478                 /* Down to minimum... */
3479                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3480                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3481
3482                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3483         } else if (IS_I915G(dev)) {
3484                 u16 gcfgc;
3485
3486                 /* Adjust render clock... */
3487                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3488
3489                 /* Down to minimum... */
3490                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3491                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3492
3493                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3494         } else if (IS_I85X(dev)) {
3495                 u16 hpllcc;
3496
3497                 /* Adjust render clock... */
3498                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3499
3500                 /* Up to maximum... */
3501                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3502                 hpllcc |= GC_CLOCK_133_200;
3503
3504                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3505         }
3506         DRM_DEBUG("decreasing render clock frequency\n");
3507 }
3508
3509 /* Note that no increase function is needed for this - increase_renderclock()
3510  *  will also rewrite these bits
3511  */
3512 void intel_decrease_displayclock(struct drm_device *dev)
3513 {
3514         if (IS_IGDNG(dev))
3515                 return;
3516
3517         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3518             IS_I915GM(dev)) {
3519                 u16 gcfgc;
3520
3521                 /* Adjust render clock... */
3522                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3523
3524                 /* Down to minimum... */
3525                 gcfgc &= ~0xf0;
3526                 gcfgc |= 0x80;
3527
3528                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3529         }
3530 }
3531
3532 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3533
3534 static void intel_crtc_idle_timer(unsigned long arg)
3535 {
3536         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3537         struct drm_crtc *crtc = &intel_crtc->base;
3538         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3539
3540         DRM_DEBUG("idle timer fired, downclocking\n");
3541
3542         intel_crtc->busy = false;
3543
3544         queue_work(dev_priv->wq, &dev_priv->idle_work);
3545 }
3546
3547 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3548 {
3549         struct drm_device *dev = crtc->dev;
3550         drm_i915_private_t *dev_priv = dev->dev_private;
3551         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3552         int pipe = intel_crtc->pipe;
3553         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3554         int dpll = I915_READ(dpll_reg);
3555
3556         if (IS_IGDNG(dev))
3557                 return;
3558
3559         if (!dev_priv->lvds_downclock_avail)
3560                 return;
3561
3562         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3563                 DRM_DEBUG("upclocking LVDS\n");
3564
3565                 /* Unlock panel regs */
3566                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3567
3568                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3569                 I915_WRITE(dpll_reg, dpll);
3570                 dpll = I915_READ(dpll_reg);
3571                 intel_wait_for_vblank(dev);
3572                 dpll = I915_READ(dpll_reg);
3573                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3574                         DRM_DEBUG("failed to upclock LVDS!\n");
3575
3576                 /* ...and lock them again */
3577                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3578         }
3579
3580         /* Schedule downclock */
3581         if (schedule)
3582                 mod_timer(&intel_crtc->idle_timer, jiffies +
3583                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3584 }
3585
3586 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3587 {
3588         struct drm_device *dev = crtc->dev;
3589         drm_i915_private_t *dev_priv = dev->dev_private;
3590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3591         int pipe = intel_crtc->pipe;
3592         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3593         int dpll = I915_READ(dpll_reg);
3594
3595         if (IS_IGDNG(dev))
3596                 return;
3597
3598         if (!dev_priv->lvds_downclock_avail)
3599                 return;
3600
3601         /*
3602          * Since this is called by a timer, we should never get here in
3603          * the manual case.
3604          */
3605         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3606                 DRM_DEBUG("downclocking LVDS\n");
3607
3608                 /* Unlock panel regs */
3609                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3610
3611                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3612                 I915_WRITE(dpll_reg, dpll);
3613                 dpll = I915_READ(dpll_reg);
3614                 intel_wait_for_vblank(dev);
3615                 dpll = I915_READ(dpll_reg);
3616                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3617                         DRM_DEBUG("failed to downclock LVDS!\n");
3618
3619                 /* ...and lock them again */
3620                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3621         }
3622
3623 }
3624
3625 /**
3626  * intel_idle_update - adjust clocks for idleness
3627  * @work: work struct
3628  *
3629  * Either the GPU or display (or both) went idle.  Check the busy status
3630  * here and adjust the CRTC and GPU clocks as necessary.
3631  */
3632 static void intel_idle_update(struct work_struct *work)
3633 {
3634         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3635                                                     idle_work);
3636         struct drm_device *dev = dev_priv->dev;
3637         struct drm_crtc *crtc;
3638         struct intel_crtc *intel_crtc;
3639
3640         if (!i915_powersave)
3641                 return;
3642
3643         mutex_lock(&dev->struct_mutex);
3644
3645         /* GPU isn't processing, downclock it. */
3646         if (!dev_priv->busy) {
3647                 intel_decrease_renderclock(dev);
3648                 intel_decrease_displayclock(dev);
3649         }
3650
3651         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3652                 /* Skip inactive CRTCs */
3653                 if (!crtc->fb)
3654                         continue;
3655
3656                 intel_crtc = to_intel_crtc(crtc);
3657                 if (!intel_crtc->busy)
3658                         intel_decrease_pllclock(crtc);
3659         }
3660
3661         mutex_unlock(&dev->struct_mutex);
3662 }
3663
3664 /**
3665  * intel_mark_busy - mark the GPU and possibly the display busy
3666  * @dev: drm device
3667  * @obj: object we're operating on
3668  *
3669  * Callers can use this function to indicate that the GPU is busy processing
3670  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3671  * buffer), we'll also mark the display as busy, so we know to increase its
3672  * clock frequency.
3673  */
3674 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3675 {
3676         drm_i915_private_t *dev_priv = dev->dev_private;
3677         struct drm_crtc *crtc = NULL;
3678         struct intel_framebuffer *intel_fb;
3679         struct intel_crtc *intel_crtc;
3680
3681         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3682                 return;
3683
3684         dev_priv->busy = true;
3685         intel_increase_renderclock(dev, true);
3686
3687         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3688                 if (!crtc->fb)
3689                         continue;
3690
3691                 intel_crtc = to_intel_crtc(crtc);
3692                 intel_fb = to_intel_framebuffer(crtc->fb);
3693                 if (intel_fb->obj == obj) {
3694                         if (!intel_crtc->busy) {
3695                                 /* Non-busy -> busy, upclock */
3696                                 intel_increase_pllclock(crtc, true);
3697                                 intel_crtc->busy = true;
3698                         } else {
3699                                 /* Busy -> busy, put off timer */
3700                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3701                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3702                         }
3703                 }
3704         }
3705 }
3706
3707 static void intel_crtc_destroy(struct drm_crtc *crtc)
3708 {
3709         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3710
3711         drm_crtc_cleanup(crtc);
3712         kfree(intel_crtc);
3713 }
3714
3715 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3716         .dpms = intel_crtc_dpms,
3717         .mode_fixup = intel_crtc_mode_fixup,
3718         .mode_set = intel_crtc_mode_set,
3719         .mode_set_base = intel_pipe_set_base,
3720         .prepare = intel_crtc_prepare,
3721         .commit = intel_crtc_commit,
3722 };
3723
3724 static const struct drm_crtc_funcs intel_crtc_funcs = {
3725         .cursor_set = intel_crtc_cursor_set,
3726         .cursor_move = intel_crtc_cursor_move,
3727         .gamma_set = intel_crtc_gamma_set,
3728         .set_config = drm_crtc_helper_set_config,
3729         .destroy = intel_crtc_destroy,
3730 };
3731
3732
3733 static void intel_crtc_init(struct drm_device *dev, int pipe)
3734 {
3735         struct intel_crtc *intel_crtc;
3736         int i;
3737
3738         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3739         if (intel_crtc == NULL)
3740                 return;
3741
3742         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
3743
3744         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
3745         intel_crtc->pipe = pipe;
3746         intel_crtc->plane = pipe;
3747         for (i = 0; i < 256; i++) {
3748                 intel_crtc->lut_r[i] = i;
3749                 intel_crtc->lut_g[i] = i;
3750                 intel_crtc->lut_b[i] = i;
3751         }
3752
3753         /* Swap pipes & planes for FBC on pre-965 */
3754         intel_crtc->pipe = pipe;
3755         intel_crtc->plane = pipe;
3756         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
3757                 DRM_DEBUG("swapping pipes & planes for FBC\n");
3758                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
3759         }
3760
3761         intel_crtc->cursor_addr = 0;
3762         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
3763         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
3764
3765         intel_crtc->busy = false;
3766
3767         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
3768                     (unsigned long)intel_crtc);
3769 }
3770
3771 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
3772                                 struct drm_file *file_priv)
3773 {
3774         drm_i915_private_t *dev_priv = dev->dev_private;
3775         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
3776         struct drm_mode_object *drmmode_obj;
3777         struct intel_crtc *crtc;
3778
3779         if (!dev_priv) {
3780                 DRM_ERROR("called with no initialization\n");
3781                 return -EINVAL;
3782         }
3783
3784         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
3785                         DRM_MODE_OBJECT_CRTC);
3786
3787         if (!drmmode_obj) {
3788                 DRM_ERROR("no such CRTC id\n");
3789                 return -EINVAL;
3790         }
3791
3792         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
3793         pipe_from_crtc_id->pipe = crtc->pipe;
3794
3795         return 0;
3796 }
3797
3798 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
3799 {
3800         struct drm_crtc *crtc = NULL;
3801
3802         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3803                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3804                 if (intel_crtc->pipe == pipe)
3805                         break;
3806         }
3807         return crtc;
3808 }
3809
3810 static int intel_connector_clones(struct drm_device *dev, int type_mask)
3811 {
3812         int index_mask = 0;
3813         struct drm_connector *connector;
3814         int entry = 0;
3815
3816         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3817                 struct intel_output *intel_output = to_intel_output(connector);
3818                 if (type_mask & intel_output->clone_mask)
3819                         index_mask |= (1 << entry);
3820                 entry++;
3821         }
3822         return index_mask;
3823 }
3824
3825
3826 static void intel_setup_outputs(struct drm_device *dev)
3827 {
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct drm_connector *connector;
3830
3831         intel_crt_init(dev);
3832
3833         /* Set up integrated LVDS */
3834         if (IS_MOBILE(dev) && !IS_I830(dev))
3835                 intel_lvds_init(dev);
3836
3837         if (IS_IGDNG(dev)) {
3838                 int found;
3839
3840                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
3841                         intel_dp_init(dev, DP_A);
3842
3843                 if (I915_READ(HDMIB) & PORT_DETECTED) {
3844                         /* check SDVOB */
3845                         /* found = intel_sdvo_init(dev, HDMIB); */
3846                         found = 0;
3847                         if (!found)
3848                                 intel_hdmi_init(dev, HDMIB);
3849                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3850                                 intel_dp_init(dev, PCH_DP_B);
3851                 }
3852
3853                 if (I915_READ(HDMIC) & PORT_DETECTED)
3854                         intel_hdmi_init(dev, HDMIC);
3855
3856                 if (I915_READ(HDMID) & PORT_DETECTED)
3857                         intel_hdmi_init(dev, HDMID);
3858
3859                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
3860                         intel_dp_init(dev, PCH_DP_C);
3861
3862                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
3863                         intel_dp_init(dev, PCH_DP_D);
3864
3865         } else if (IS_I9XX(dev)) {
3866                 bool found = false;
3867
3868                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3869                         found = intel_sdvo_init(dev, SDVOB);
3870                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3871                                 intel_hdmi_init(dev, SDVOB);
3872
3873                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
3874                                 intel_dp_init(dev, DP_B);
3875                 }
3876
3877                 /* Before G4X SDVOC doesn't have its own detect register */
3878
3879                 if (I915_READ(SDVOB) & SDVO_DETECTED)
3880                         found = intel_sdvo_init(dev, SDVOC);
3881
3882                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
3883
3884                         if (SUPPORTS_INTEGRATED_HDMI(dev))
3885                                 intel_hdmi_init(dev, SDVOC);
3886                         if (SUPPORTS_INTEGRATED_DP(dev))
3887                                 intel_dp_init(dev, DP_C);
3888                 }
3889
3890                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3891                         intel_dp_init(dev, DP_D);
3892         } else
3893                 intel_dvo_init(dev);
3894
3895         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
3896                 intel_tv_init(dev);
3897
3898         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3899                 struct intel_output *intel_output = to_intel_output(connector);
3900                 struct drm_encoder *encoder = &intel_output->enc;
3901
3902                 encoder->possible_crtcs = intel_output->crtc_mask;
3903                 encoder->possible_clones = intel_connector_clones(dev,
3904                                                 intel_output->clone_mask);
3905         }
3906 }
3907
3908 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3909 {
3910         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3911         struct drm_device *dev = fb->dev;
3912
3913         if (fb->fbdev)
3914                 intelfb_remove(dev, fb);
3915
3916         drm_framebuffer_cleanup(fb);
3917         mutex_lock(&dev->struct_mutex);
3918         drm_gem_object_unreference(intel_fb->obj);
3919         mutex_unlock(&dev->struct_mutex);
3920
3921         kfree(intel_fb);
3922 }
3923
3924 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3925                                                 struct drm_file *file_priv,
3926                                                 unsigned int *handle)
3927 {
3928         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3929         struct drm_gem_object *object = intel_fb->obj;
3930
3931         return drm_gem_handle_create(file_priv, object, handle);
3932 }
3933
3934 static const struct drm_framebuffer_funcs intel_fb_funcs = {
3935         .destroy = intel_user_framebuffer_destroy,
3936         .create_handle = intel_user_framebuffer_create_handle,
3937 };
3938
3939 int intel_framebuffer_create(struct drm_device *dev,
3940                              struct drm_mode_fb_cmd *mode_cmd,
3941                              struct drm_framebuffer **fb,
3942                              struct drm_gem_object *obj)
3943 {
3944         struct intel_framebuffer *intel_fb;
3945         int ret;
3946
3947         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3948         if (!intel_fb)
3949                 return -ENOMEM;
3950
3951         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3952         if (ret) {
3953                 DRM_ERROR("framebuffer init failed %d\n", ret);
3954                 return ret;
3955         }
3956
3957         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3958
3959         intel_fb->obj = obj;
3960
3961         *fb = &intel_fb->base;
3962
3963         return 0;
3964 }
3965
3966
3967 static struct drm_framebuffer *
3968 intel_user_framebuffer_create(struct drm_device *dev,
3969                               struct drm_file *filp,
3970                               struct drm_mode_fb_cmd *mode_cmd)
3971 {
3972         struct drm_gem_object *obj;
3973         struct drm_framebuffer *fb;
3974         int ret;
3975
3976         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3977         if (!obj)
3978                 return NULL;
3979
3980         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3981         if (ret) {
3982                 mutex_lock(&dev->struct_mutex);
3983                 drm_gem_object_unreference(obj);
3984                 mutex_unlock(&dev->struct_mutex);
3985                 return NULL;
3986         }
3987
3988         return fb;
3989 }
3990
3991 static const struct drm_mode_config_funcs intel_mode_funcs = {
3992         .fb_create = intel_user_framebuffer_create,
3993         .fb_changed = intelfb_probe,
3994 };
3995
3996 void intel_init_clock_gating(struct drm_device *dev)
3997 {
3998         struct drm_i915_private *dev_priv = dev->dev_private;
3999
4000         /*
4001          * Disable clock gating reported to work incorrectly according to the
4002          * specs, but enable as much else as we can.
4003          */
4004         if (IS_G4X(dev)) {
4005                 uint32_t dspclk_gate;
4006                 I915_WRITE(RENCLK_GATE_D1, 0);
4007                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4008                        GS_UNIT_CLOCK_GATE_DISABLE |
4009                        CL_UNIT_CLOCK_GATE_DISABLE);
4010                 I915_WRITE(RAMCLK_GATE_D, 0);
4011                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4012                         OVRUNIT_CLOCK_GATE_DISABLE |
4013                         OVCUNIT_CLOCK_GATE_DISABLE;
4014                 if (IS_GM45(dev))
4015                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4016                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4017         } else if (IS_I965GM(dev)) {
4018                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4019                 I915_WRITE(RENCLK_GATE_D2, 0);
4020                 I915_WRITE(DSPCLK_GATE_D, 0);
4021                 I915_WRITE(RAMCLK_GATE_D, 0);
4022                 I915_WRITE16(DEUC, 0);
4023         } else if (IS_I965G(dev)) {
4024                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4025                        I965_RCC_CLOCK_GATE_DISABLE |
4026                        I965_RCPB_CLOCK_GATE_DISABLE |
4027                        I965_ISC_CLOCK_GATE_DISABLE |
4028                        I965_FBC_CLOCK_GATE_DISABLE);
4029                 I915_WRITE(RENCLK_GATE_D2, 0);
4030         } else if (IS_I9XX(dev)) {
4031                 u32 dstate = I915_READ(D_STATE);
4032
4033                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4034                         DSTATE_DOT_CLOCK_GATING;
4035                 I915_WRITE(D_STATE, dstate);
4036         } else if (IS_I855(dev) || IS_I865G(dev)) {
4037                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4038         } else if (IS_I830(dev)) {
4039                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4040         }
4041 }
4042
4043 void intel_modeset_init(struct drm_device *dev)
4044 {
4045         struct drm_i915_private *dev_priv = dev->dev_private;
4046         int num_pipe;
4047         int i;
4048
4049         drm_mode_config_init(dev);
4050
4051         dev->mode_config.min_width = 0;
4052         dev->mode_config.min_height = 0;
4053
4054         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4055
4056         if (IS_I965G(dev)) {
4057                 dev->mode_config.max_width = 8192;
4058                 dev->mode_config.max_height = 8192;
4059         } else if (IS_I9XX(dev)) {
4060                 dev->mode_config.max_width = 4096;
4061                 dev->mode_config.max_height = 4096;
4062         } else {
4063                 dev->mode_config.max_width = 2048;
4064                 dev->mode_config.max_height = 2048;
4065         }
4066
4067         /* set memory base */
4068         if (IS_I9XX(dev))
4069                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4070         else
4071                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4072
4073         if (IS_MOBILE(dev) || IS_I9XX(dev))
4074                 num_pipe = 2;
4075         else
4076                 num_pipe = 1;
4077         DRM_DEBUG("%d display pipe%s available.\n",
4078                   num_pipe, num_pipe > 1 ? "s" : "");
4079
4080         if (IS_I85X(dev))
4081                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4082         else if (IS_I9XX(dev) || IS_G4X(dev))
4083                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4084
4085         for (i = 0; i < num_pipe; i++) {
4086                 intel_crtc_init(dev, i);
4087         }
4088
4089         intel_setup_outputs(dev);
4090
4091         intel_init_clock_gating(dev);
4092
4093         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4094         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4095                     (unsigned long)dev);
4096 }
4097
4098 void intel_modeset_cleanup(struct drm_device *dev)
4099 {
4100         struct drm_i915_private *dev_priv = dev->dev_private;
4101         struct drm_crtc *crtc;
4102         struct intel_crtc *intel_crtc;
4103
4104         mutex_lock(&dev->struct_mutex);
4105
4106         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4107                 /* Skip inactive CRTCs */
4108                 if (!crtc->fb)
4109                         continue;
4110
4111                 intel_crtc = to_intel_crtc(crtc);
4112                 intel_increase_pllclock(crtc, false);
4113                 del_timer_sync(&intel_crtc->idle_timer);
4114         }
4115
4116         intel_increase_renderclock(dev, false);
4117         del_timer_sync(&dev_priv->idle_timer);
4118
4119         mutex_unlock(&dev->struct_mutex);
4120
4121         i8xx_disable_fbc(dev);
4122         drm_mode_config_cleanup(dev);
4123 }
4124
4125
4126 /* current intel driver doesn't take advantage of encoders
4127    always give back the encoder for the connector
4128 */
4129 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4130 {
4131         struct intel_output *intel_output = to_intel_output(connector);
4132
4133         return &intel_output->enc;
4134 }