1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory.
32 #define INTEL_GMCH_CTRL 0x52
33 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
34 #define INTEL_GMCH_ENABLED 0x4
35 #define INTEL_GMCH_MEM_MASK 0x1
36 #define INTEL_GMCH_MEM_64M 0x1
37 #define INTEL_GMCH_MEM_128M 0
39 #define INTEL_GMCH_GMS_MASK (0xf << 4)
40 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
41 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
42 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
45 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
47 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
48 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
49 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
50 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
51 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
52 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
53 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
54 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
56 #define SNB_GMCH_CTRL 0x50
57 #define SNB_GMCH_GMS_STOLEN_MASK 0xF8
58 #define SNB_GMCH_GMS_STOLEN_32M (1 << 3)
59 #define SNB_GMCH_GMS_STOLEN_64M (2 << 3)
60 #define SNB_GMCH_GMS_STOLEN_96M (3 << 3)
61 #define SNB_GMCH_GMS_STOLEN_128M (4 << 3)
62 #define SNB_GMCH_GMS_STOLEN_160M (5 << 3)
63 #define SNB_GMCH_GMS_STOLEN_192M (6 << 3)
64 #define SNB_GMCH_GMS_STOLEN_224M (7 << 3)
65 #define SNB_GMCH_GMS_STOLEN_256M (8 << 3)
66 #define SNB_GMCH_GMS_STOLEN_288M (9 << 3)
67 #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
68 #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
69 #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
70 #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
71 #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
72 #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
73 #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
75 /* PCI config space */
77 #define HPLLCC 0xc0 /* 855 only */
78 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
79 #define GC_CLOCK_133_200 (0 << 0)
80 #define GC_CLOCK_100_200 (1 << 0)
81 #define GC_CLOCK_100_133 (2 << 0)
82 #define GC_CLOCK_166_250 (3 << 0)
84 #define GCFGC 0xf0 /* 915+ only */
85 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
86 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
87 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
88 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
89 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
90 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
91 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
92 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
93 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
94 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
95 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
96 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
97 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
98 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
99 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
100 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
101 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
102 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
103 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
104 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
105 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
106 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
107 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
110 #define GDRST_FULL (0<<2)
111 #define GDRST_RENDER (1<<2)
112 #define GDRST_MEDIA (3<<2)
116 #define VGA_ST01_MDA 0x3ba
117 #define VGA_ST01_CGA 0x3da
119 #define VGA_MSR_WRITE 0x3c2
120 #define VGA_MSR_READ 0x3cc
121 #define VGA_MSR_MEM_EN (1<<1)
122 #define VGA_MSR_CGA_MODE (1<<0)
124 #define VGA_SR_INDEX 0x3c4
125 #define VGA_SR_DATA 0x3c5
127 #define VGA_AR_INDEX 0x3c0
128 #define VGA_AR_VID_EN (1<<5)
129 #define VGA_AR_DATA_WRITE 0x3c0
130 #define VGA_AR_DATA_READ 0x3c1
132 #define VGA_GR_INDEX 0x3ce
133 #define VGA_GR_DATA 0x3cf
135 #define VGA_GR_MEM_READ_MODE_SHIFT 3
136 #define VGA_GR_MEM_READ_MODE_PLANE 1
138 #define VGA_GR_MEM_MODE_MASK 0xc
139 #define VGA_GR_MEM_MODE_SHIFT 2
140 #define VGA_GR_MEM_A0000_AFFFF 0
141 #define VGA_GR_MEM_A0000_BFFFF 1
142 #define VGA_GR_MEM_B0000_B7FFF 2
143 #define VGA_GR_MEM_B0000_BFFFF 3
145 #define VGA_DACMASK 0x3c6
146 #define VGA_DACRX 0x3c7
147 #define VGA_DACWX 0x3c8
148 #define VGA_DACDATA 0x3c9
150 #define VGA_CR_INDEX_MDA 0x3b4
151 #define VGA_CR_DATA_MDA 0x3b5
152 #define VGA_CR_INDEX_CGA 0x3d4
153 #define VGA_CR_DATA_CGA 0x3d5
156 * Memory interface instructions used by the kernel
158 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
160 #define MI_NOOP MI_INSTR(0, 0)
161 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
162 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
163 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
164 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
165 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
166 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
167 #define MI_FLUSH MI_INSTR(0x04, 0)
168 #define MI_READ_FLUSH (1 << 0)
169 #define MI_EXE_FLUSH (1 << 1)
170 #define MI_NO_WRITE_FLUSH (1 << 2)
171 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
172 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
173 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
174 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
175 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
176 #define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
177 #define MI_OVERLAY_CONTINUE (0x0<<21)
178 #define MI_OVERLAY_ON (0x1<<21)
179 #define MI_OVERLAY_OFF (0x2<<21)
180 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
181 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
182 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
183 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
184 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
185 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
186 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
187 #define MI_STORE_DWORD_INDEX_SHIFT 2
188 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
189 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
190 #define MI_BATCH_NON_SECURE (1)
191 #define MI_BATCH_NON_SECURE_I965 (1<<8)
192 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
195 * 3D instructions used by the kernel
197 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
199 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
200 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
201 #define SC_UPDATE_SCISSOR (0x1<<1)
202 #define SC_ENABLE_MASK (0x1<<0)
203 #define SC_ENABLE (0x1<<0)
204 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
205 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
206 #define SCI_YMIN_MASK (0xffff<<16)
207 #define SCI_XMIN_MASK (0xffff<<0)
208 #define SCI_YMAX_MASK (0xffff<<16)
209 #define SCI_XMAX_MASK (0xffff<<0)
210 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
211 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
212 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
213 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
214 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
215 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
216 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
217 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
218 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
219 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
220 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
221 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
222 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
223 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
224 #define BLT_DEPTH_8 (0<<24)
225 #define BLT_DEPTH_16_565 (1<<24)
226 #define BLT_DEPTH_16_1555 (2<<24)
227 #define BLT_DEPTH_32 (3<<24)
228 #define BLT_ROP_GXCOPY (0xcc<<16)
229 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
230 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
231 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
232 #define ASYNC_FLIP (1<<22)
233 #define DISPLAY_PLANE_A (0<<20)
234 #define DISPLAY_PLANE_B (1<<20)
235 #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
236 #define PIPE_CONTROL_QW_WRITE (1<<14)
237 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
238 #define PIPE_CONTROL_WC_FLUSH (1<<12)
239 #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
240 #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
241 #define PIPE_CONTROL_ISP_DIS (1<<9)
242 #define PIPE_CONTROL_NOTIFY (1<<8)
243 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
244 #define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
249 #define FENCE_REG_830_0 0x2000
250 #define FENCE_REG_945_8 0x3000
251 #define I830_FENCE_START_MASK 0x07f80000
252 #define I830_FENCE_TILING_Y_SHIFT 12
253 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
254 #define I830_FENCE_PITCH_SHIFT 4
255 #define I830_FENCE_REG_VALID (1<<0)
256 #define I915_FENCE_MAX_PITCH_VAL 4
257 #define I830_FENCE_MAX_PITCH_VAL 6
258 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
260 #define I915_FENCE_START_MASK 0x0ff00000
261 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
263 #define FENCE_REG_965_0 0x03000
264 #define I965_FENCE_PITCH_SHIFT 2
265 #define I965_FENCE_TILING_Y_SHIFT 1
266 #define I965_FENCE_REG_VALID (1<<0)
267 #define I965_FENCE_MAX_PITCH_VAL 0x0400
269 #define FENCE_REG_SANDYBRIDGE_0 0x100000
270 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
273 * Instruction and interrupt control regs
275 #define PGTBL_ER 0x02024
276 #define PRB0_TAIL 0x02030
277 #define PRB0_HEAD 0x02034
278 #define PRB0_START 0x02038
279 #define PRB0_CTL 0x0203c
280 #define TAIL_ADDR 0x001FFFF8
281 #define HEAD_WRAP_COUNT 0xFFE00000
282 #define HEAD_WRAP_ONE 0x00200000
283 #define HEAD_ADDR 0x001FFFFC
284 #define RING_NR_PAGES 0x001FF000
285 #define RING_REPORT_MASK 0x00000006
286 #define RING_REPORT_64K 0x00000002
287 #define RING_REPORT_128K 0x00000004
288 #define RING_NO_REPORT 0x00000000
289 #define RING_VALID_MASK 0x00000001
290 #define RING_VALID 0x00000001
291 #define RING_INVALID 0x00000000
292 #define PRB1_TAIL 0x02040 /* 915+ only */
293 #define PRB1_HEAD 0x02044 /* 915+ only */
294 #define PRB1_START 0x02048 /* 915+ only */
295 #define PRB1_CTL 0x0204c /* 915+ only */
296 #define IPEIR_I965 0x02064
297 #define IPEHR_I965 0x02068
298 #define INSTDONE_I965 0x0206c
299 #define INSTPS 0x02070 /* 965+ only */
300 #define INSTDONE1 0x0207c /* 965+ only */
301 #define ACTHD_I965 0x02074
302 #define HWS_PGA 0x02080
303 #define HWS_PGA_GEN6 0x04080
304 #define HWS_ADDRESS_MASK 0xfffff000
305 #define HWS_START_ADDRESS_SHIFT 4
306 #define PWRCTXA 0x2088 /* 965GM+ only */
307 #define PWRCTX_EN (1<<0)
308 #define IPEIR 0x02088
309 #define IPEHR 0x0208c
310 #define INSTDONE 0x02090
311 #define NOPID 0x02094
312 #define HWSTAM 0x02098
314 #define MI_MODE 0x0209c
315 # define VS_TIMER_DISPATCH (1 << 6)
317 #define SCPD0 0x0209c /* 915+ only */
322 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
323 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
324 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
325 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
326 #define I915_HWB_OOM_INTERRUPT (1<<13)
327 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
328 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
329 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
330 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
331 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
332 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
333 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
334 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
335 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
336 #define I915_DEBUG_INTERRUPT (1<<2)
337 #define I915_USER_INTERRUPT (1<<1)
338 #define I915_ASLE_INTERRUPT (1<<0)
339 #define I915_BSD_USER_INTERRUPT (1<<25)
343 #define GM45_ERROR_PAGE_TABLE (1<<5)
344 #define GM45_ERROR_MEM_PRIV (1<<4)
345 #define I915_ERROR_PAGE_TABLE (1<<4)
346 #define GM45_ERROR_CP_PRIV (1<<3)
347 #define I915_ERROR_MEMORY_REFRESH (1<<1)
348 #define I915_ERROR_INSTRUCTION (1<<0)
349 #define INSTPM 0x020c0
350 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
351 #define ACTHD 0x020c8
352 #define FW_BLC 0x020d8
353 #define FW_BLC2 0x020dc
354 #define FW_BLC_SELF 0x020e0 /* 915+ only */
355 #define FW_BLC_SELF_EN_MASK (1<<31)
356 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
357 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
358 #define MM_BURST_LENGTH 0x00700000
359 #define MM_FIFO_WATERMARK 0x0001F000
360 #define LM_BURST_LENGTH 0x00000700
361 #define LM_FIFO_WATERMARK 0x0000001F
362 #define MI_ARB_STATE 0x020e4 /* 915+ only */
363 #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
365 /* Make render/texture TLB fetches lower priorty than associated data
366 * fetches. This is not turned on by default
368 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
370 /* Isoch request wait on GTT enable (Display A/B/C streams).
371 * Make isoch requests stall on the TLB update. May cause
372 * display underruns (test mode only)
374 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
376 /* Block grant count for isoch requests when block count is
377 * set to a finite value.
379 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
380 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
381 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
382 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
383 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
385 /* Enable render writes to complete in C2/C3/C4 power states.
386 * If this isn't enabled, render writes are prevented in low
387 * power states. That seems bad to me.
389 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
391 /* This acknowledges an async flip immediately instead
392 * of waiting for 2TLB fetches.
394 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
396 /* Enables non-sequential data reads through arbiter
398 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
400 /* Disable FSB snooping of cacheable write cycles from binner/render
403 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
405 /* Arbiter time slice for non-isoch streams */
406 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
407 #define MI_ARB_TIME_SLICE_1 (0 << 5)
408 #define MI_ARB_TIME_SLICE_2 (1 << 5)
409 #define MI_ARB_TIME_SLICE_4 (2 << 5)
410 #define MI_ARB_TIME_SLICE_6 (3 << 5)
411 #define MI_ARB_TIME_SLICE_8 (4 << 5)
412 #define MI_ARB_TIME_SLICE_10 (5 << 5)
413 #define MI_ARB_TIME_SLICE_14 (6 << 5)
414 #define MI_ARB_TIME_SLICE_16 (7 << 5)
416 /* Low priority grace period page size */
417 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
418 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
420 /* Disable display A/B trickle feed */
421 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
423 /* Set display plane priority */
424 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
425 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
427 #define CACHE_MODE_0 0x02120 /* 915+ only */
428 #define CM0_MASK_SHIFT 16
429 #define CM0_IZ_OPT_DISABLE (1<<6)
430 #define CM0_ZR_OPT_DISABLE (1<<5)
431 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
432 #define CM0_COLOR_EVICT_DISABLE (1<<3)
433 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
434 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
435 #define BB_ADDR 0x02140 /* 8 bytes */
436 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
437 #define ECOSKPD 0x021d0
438 #define ECO_GATING_CX_ONLY (1<<3)
439 #define ECO_FLIP_DONE (1<<0)
441 /* GEN6 interrupt control */
442 #define GEN6_RENDER_HWSTAM 0x2098
443 #define GEN6_RENDER_IMR 0x20a8
444 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
445 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
446 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
447 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
448 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
449 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
450 #define GEN6_RENDER_SYNC_STATUS (1 << 2)
451 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
452 #define GEN6_RENDER_USER_INTERRUPT (1 << 0)
454 #define GEN6_BLITTER_HWSTAM 0x22098
455 #define GEN6_BLITTER_IMR 0x220a8
456 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
457 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
458 #define GEN6_BLITTER_SYNC_STATUS (1 << 24)
459 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
461 * BSD (bit stream decoder instruction and interrupt control register defines
462 * (G4X and Ironlake only)
465 #define BSD_RING_TAIL 0x04030
466 #define BSD_RING_HEAD 0x04034
467 #define BSD_RING_START 0x04038
468 #define BSD_RING_CTL 0x0403c
469 #define BSD_RING_ACTHD 0x04074
470 #define BSD_HWS_PGA 0x04080
473 * Framebuffer compression (915+ only)
476 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
477 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
478 #define FBC_CONTROL 0x03208
479 #define FBC_CTL_EN (1<<31)
480 #define FBC_CTL_PERIODIC (1<<30)
481 #define FBC_CTL_INTERVAL_SHIFT (16)
482 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
483 #define FBC_CTL_C3_IDLE (1<<13)
484 #define FBC_CTL_STRIDE_SHIFT (5)
485 #define FBC_CTL_FENCENO (1<<0)
486 #define FBC_COMMAND 0x0320c
487 #define FBC_CMD_COMPRESS (1<<0)
488 #define FBC_STATUS 0x03210
489 #define FBC_STAT_COMPRESSING (1<<31)
490 #define FBC_STAT_COMPRESSED (1<<30)
491 #define FBC_STAT_MODIFIED (1<<29)
492 #define FBC_STAT_CURRENT_LINE (1<<0)
493 #define FBC_CONTROL2 0x03214
494 #define FBC_CTL_FENCE_DBL (0<<4)
495 #define FBC_CTL_IDLE_IMM (0<<2)
496 #define FBC_CTL_IDLE_FULL (1<<2)
497 #define FBC_CTL_IDLE_LINE (2<<2)
498 #define FBC_CTL_IDLE_DEBUG (3<<2)
499 #define FBC_CTL_CPU_FENCE (1<<1)
500 #define FBC_CTL_PLANEA (0<<0)
501 #define FBC_CTL_PLANEB (1<<0)
502 #define FBC_FENCE_OFF 0x0321b
503 #define FBC_TAG 0x03300
505 #define FBC_LL_SIZE (1536)
507 /* Framebuffer compression for GM45+ */
508 #define DPFC_CB_BASE 0x3200
509 #define DPFC_CONTROL 0x3208
510 #define DPFC_CTL_EN (1<<31)
511 #define DPFC_CTL_PLANEA (0<<30)
512 #define DPFC_CTL_PLANEB (1<<30)
513 #define DPFC_CTL_FENCE_EN (1<<29)
514 #define DPFC_SR_EN (1<<10)
515 #define DPFC_CTL_LIMIT_1X (0<<6)
516 #define DPFC_CTL_LIMIT_2X (1<<6)
517 #define DPFC_CTL_LIMIT_4X (2<<6)
518 #define DPFC_RECOMP_CTL 0x320c
519 #define DPFC_RECOMP_STALL_EN (1<<27)
520 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
521 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
522 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
523 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
524 #define DPFC_STATUS 0x3210
525 #define DPFC_INVAL_SEG_SHIFT (16)
526 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
527 #define DPFC_COMP_SEG_SHIFT (0)
528 #define DPFC_COMP_SEG_MASK (0x000003ff)
529 #define DPFC_STATUS2 0x3214
530 #define DPFC_FENCE_YOFF 0x3218
531 #define DPFC_CHICKEN 0x3224
532 #define DPFC_HT_MODIFY (1<<31)
534 /* Framebuffer compression for Ironlake */
535 #define ILK_DPFC_CB_BASE 0x43200
536 #define ILK_DPFC_CONTROL 0x43208
537 /* The bit 28-8 is reserved */
538 #define DPFC_RESERVED (0x1FFFFF00)
539 #define ILK_DPFC_RECOMP_CTL 0x4320c
540 #define ILK_DPFC_STATUS 0x43210
541 #define ILK_DPFC_FENCE_YOFF 0x43218
542 #define ILK_DPFC_CHICKEN 0x43224
543 #define ILK_FBC_RT_BASE 0x2128
544 #define ILK_FBC_RT_VALID (1<<0)
546 #define ILK_DISPLAY_CHICKEN1 0x42000
547 #define ILK_FBCQ_DIS (1<<22)
560 # define GPIO_CLOCK_DIR_MASK (1 << 0)
561 # define GPIO_CLOCK_DIR_IN (0 << 1)
562 # define GPIO_CLOCK_DIR_OUT (1 << 1)
563 # define GPIO_CLOCK_VAL_MASK (1 << 2)
564 # define GPIO_CLOCK_VAL_OUT (1 << 3)
565 # define GPIO_CLOCK_VAL_IN (1 << 4)
566 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
567 # define GPIO_DATA_DIR_MASK (1 << 8)
568 # define GPIO_DATA_DIR_IN (0 << 9)
569 # define GPIO_DATA_DIR_OUT (1 << 9)
570 # define GPIO_DATA_VAL_MASK (1 << 10)
571 # define GPIO_DATA_VAL_OUT (1 << 11)
572 # define GPIO_DATA_VAL_IN (1 << 12)
573 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
575 #define GMBUS0 0x5100
576 #define GMBUS1 0x5104
577 #define GMBUS2 0x5108
578 #define GMBUS3 0x510c
579 #define GMBUS4 0x5110
580 #define GMBUS5 0x5120
583 * Clock control & power management
588 #define VGA_PD 0x6010
589 #define VGA0_PD_P2_DIV_4 (1 << 7)
590 #define VGA0_PD_P1_DIV_2 (1 << 5)
591 #define VGA0_PD_P1_SHIFT 0
592 #define VGA0_PD_P1_MASK (0x1f << 0)
593 #define VGA1_PD_P2_DIV_4 (1 << 15)
594 #define VGA1_PD_P1_DIV_2 (1 << 13)
595 #define VGA1_PD_P1_SHIFT 8
596 #define VGA1_PD_P1_MASK (0x1f << 8)
597 #define DPLL_A 0x06014
598 #define DPLL_B 0x06018
599 #define DPLL_VCO_ENABLE (1 << 31)
600 #define DPLL_DVO_HIGH_SPEED (1 << 30)
601 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
602 #define DPLL_VGA_MODE_DIS (1 << 28)
603 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
604 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
605 #define DPLL_MODE_MASK (3 << 26)
606 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
607 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
608 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
609 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
610 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
611 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
612 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
614 #define SRX_INDEX 0x3c4
615 #define SRX_DATA 0x3c5
617 #define SR01_SCREEN_OFF (1<<5)
620 #define PPCR_ON (1<<0)
623 #define DVOB_ON (1<<31)
625 #define DVOC_ON (1<<31)
627 #define LVDS_ON (1<<31)
630 #define ADPA_DPMS_MASK (~(3<<10))
631 #define ADPA_DPMS_ON (0<<10)
632 #define ADPA_DPMS_SUSPEND (1<<10)
633 #define ADPA_DPMS_STANDBY (2<<10)
634 #define ADPA_DPMS_OFF (3<<10)
636 #define RING_TAIL 0x00
637 #define TAIL_ADDR 0x001FFFF8
638 #define RING_HEAD 0x04
639 #define HEAD_WRAP_COUNT 0xFFE00000
640 #define HEAD_WRAP_ONE 0x00200000
641 #define HEAD_ADDR 0x001FFFFC
642 #define RING_START 0x08
643 #define START_ADDR 0xFFFFF000
644 #define RING_LEN 0x0C
645 #define RING_NR_PAGES 0x001FF000
646 #define RING_REPORT_MASK 0x00000006
647 #define RING_REPORT_64K 0x00000002
648 #define RING_REPORT_128K 0x00000004
649 #define RING_NO_REPORT 0x00000000
650 #define RING_VALID_MASK 0x00000001
651 #define RING_VALID 0x00000001
652 #define RING_INVALID 0x00000000
654 /* Scratch pad debug 0 reg:
656 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
658 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
659 * this field (only one bit may be set).
661 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
662 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
663 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
664 /* i830, required in DVO non-gang */
665 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
666 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
667 #define PLL_REF_INPUT_DREFCLK (0 << 13)
668 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
669 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
670 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
671 #define PLL_REF_INPUT_MASK (3 << 13)
672 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
674 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
675 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
676 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
677 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
678 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
681 * Parallel to Serial Load Pulse phase selection.
682 * Selects the phase for the 10X DPLL clock for the PCIe
683 * digital display port. The range is 4 to 13; 10 or more
684 * is just a flip delay. The default is 6
686 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
687 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
689 * SDVO multiplier for 945G/GM. Not used on 965.
691 #define SDVO_MULTIPLIER_MASK 0x000000ff
692 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
693 #define SDVO_MULTIPLIER_SHIFT_VGA 0
694 #define DPLL_A_MD 0x0601c /* 965+ only */
696 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
698 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
700 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
701 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
702 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
703 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
704 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
706 * SDVO/UDI pixel multiplier.
708 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
709 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
710 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
711 * dummy bytes in the datastream at an increased clock rate, with both sides of
712 * the link knowing how many bytes are fill.
714 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
715 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
716 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
717 * through an SDVO command.
719 * This register field has values of multiplication factor minus 1, with
720 * a maximum multiplier of 5 for SDVO.
722 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
723 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
725 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
726 * This best be set to the default value (3) or the CRT won't work. No,
727 * I don't entirely understand what this does...
729 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
730 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
731 #define DPLL_B_MD 0x06020 /* 965+ only */
736 #define FP_N_DIV_MASK 0x003f0000
737 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
738 #define FP_N_DIV_SHIFT 16
739 #define FP_M1_DIV_MASK 0x00003f00
740 #define FP_M1_DIV_SHIFT 8
741 #define FP_M2_DIV_MASK 0x0000003f
742 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
743 #define FP_M2_DIV_SHIFT 0
744 #define DPLL_TEST 0x606c
745 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
746 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
747 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
748 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
749 #define DPLLB_TEST_N_BYPASS (1 << 19)
750 #define DPLLB_TEST_M_BYPASS (1 << 18)
751 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
752 #define DPLLA_TEST_N_BYPASS (1 << 3)
753 #define DPLLA_TEST_M_BYPASS (1 << 2)
754 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
755 #define D_STATE 0x6104
756 #define DSTATE_PLL_D3_OFF (1<<3)
757 #define DSTATE_GFX_CLOCK_GATING (1<<1)
758 #define DSTATE_DOT_CLOCK_GATING (1<<0)
759 #define DSPCLK_GATE_D 0x6200
760 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
761 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
762 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
763 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
764 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
765 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
766 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
767 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
768 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
769 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
770 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
771 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
772 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
773 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
774 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
775 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
776 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
777 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
778 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
779 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
780 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
781 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
782 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
783 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
784 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
785 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
786 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
787 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
789 * This bit must be set on the 830 to prevent hangs when turning off the
792 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
793 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
794 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
795 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
796 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
798 #define RENCLK_GATE_D1 0x6204
799 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
800 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
801 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
802 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
803 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
804 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
805 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
806 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
807 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
808 /** This bit must be unset on 855,865 */
809 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
810 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
811 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
812 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
813 /** This bit must be set on 855,865. */
814 # define SV_CLOCK_GATE_DISABLE (1 << 0)
815 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
816 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
817 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
818 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
819 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
820 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
821 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
822 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
823 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
824 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
825 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
826 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
827 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
828 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
829 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
830 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
831 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
833 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
834 /** This bit must always be set on 965G/965GM */
835 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
836 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
837 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
838 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
839 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
840 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
841 /** This bit must always be set on 965G */
842 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
843 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
844 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
845 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
846 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
847 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
848 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
849 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
850 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
851 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
852 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
853 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
854 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
855 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
856 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
857 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
858 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
859 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
860 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
862 #define RENCLK_GATE_D2 0x6208
863 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
864 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
865 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
866 #define RAMCLK_GATE_D 0x6210 /* CRL only */
867 #define DEUC 0x6214 /* CRL only */
873 #define PALETTE_A 0x0a000
874 #define PALETTE_B 0x0a800
881 * This mirrors the MCHBAR MMIO space whose location is determined by
882 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
883 * every way. It is not accessible from the CP register read instructions.
886 #define MCHBAR_MIRROR_BASE 0x10000
888 /** 915-945 and GM965 MCH register controlling DRAM channel access */
890 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
891 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
892 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
893 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
894 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
895 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
897 /** Pineview MCH register contains DDR3 setting */
898 #define CSHRDDR3CTL 0x101a8
899 #define CSHRDDR3CTL_DDR3 (1 << 2)
901 /** 965 MCH register controlling DRAM channel configuration */
902 #define C0DRB3 0x10206
903 #define C1DRB3 0x10606
905 /* Clocking configuration register */
906 #define CLKCFG 0x10c00
907 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
908 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
909 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
910 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
911 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
912 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
913 /* Note, below two are guess */
914 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
915 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
916 #define CLKCFG_FSB_MASK (7 << 0)
917 #define CLKCFG_MEM_533 (1 << 4)
918 #define CLKCFG_MEM_667 (2 << 4)
919 #define CLKCFG_MEM_800 (3 << 4)
920 #define CLKCFG_MEM_MASK (7 << 4)
924 #define TSFS_SLOPE_MASK 0x0000ff00
925 #define TSFS_SLOPE_SHIFT 8
926 #define TSFS_INTR_MASK 0x000000ff
928 #define CRSTANDVID 0x11100
929 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
930 #define PXVFREQ_PX_MASK 0x7f000000
931 #define PXVFREQ_PX_SHIFT 24
932 #define VIDFREQ_BASE 0x11110
933 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
934 #define VIDFREQ2 0x11114
935 #define VIDFREQ3 0x11118
936 #define VIDFREQ4 0x1111c
937 #define VIDFREQ_P0_MASK 0x1f000000
938 #define VIDFREQ_P0_SHIFT 24
939 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
940 #define VIDFREQ_P0_CSCLK_SHIFT 20
941 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
942 #define VIDFREQ_P0_CRCLK_SHIFT 16
943 #define VIDFREQ_P1_MASK 0x00001f00
944 #define VIDFREQ_P1_SHIFT 8
945 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
946 #define VIDFREQ_P1_CSCLK_SHIFT 4
947 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
948 #define INTTOEXT_BASE_ILK 0x11300
949 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
950 #define INTTOEXT_MAP3_SHIFT 24
951 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
952 #define INTTOEXT_MAP2_SHIFT 16
953 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
954 #define INTTOEXT_MAP1_SHIFT 8
955 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
956 #define INTTOEXT_MAP0_SHIFT 0
957 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
958 #define MEMSWCTL 0x11170 /* Ironlake only */
959 #define MEMCTL_CMD_MASK 0xe000
960 #define MEMCTL_CMD_SHIFT 13
961 #define MEMCTL_CMD_RCLK_OFF 0
962 #define MEMCTL_CMD_RCLK_ON 1
963 #define MEMCTL_CMD_CHFREQ 2
964 #define MEMCTL_CMD_CHVID 3
965 #define MEMCTL_CMD_VMMOFF 4
966 #define MEMCTL_CMD_VMMON 5
967 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
968 when command complete */
969 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
970 #define MEMCTL_FREQ_SHIFT 8
971 #define MEMCTL_SFCAVM (1<<7)
972 #define MEMCTL_TGT_VID_MASK 0x007f
973 #define MEMIHYST 0x1117c
974 #define MEMINTREN 0x11180 /* 16 bits */
975 #define MEMINT_RSEXIT_EN (1<<8)
976 #define MEMINT_CX_SUPR_EN (1<<7)
977 #define MEMINT_CONT_BUSY_EN (1<<6)
978 #define MEMINT_AVG_BUSY_EN (1<<5)
979 #define MEMINT_EVAL_CHG_EN (1<<4)
980 #define MEMINT_MON_IDLE_EN (1<<3)
981 #define MEMINT_UP_EVAL_EN (1<<2)
982 #define MEMINT_DOWN_EVAL_EN (1<<1)
983 #define MEMINT_SW_CMD_EN (1<<0)
984 #define MEMINTRSTR 0x11182 /* 16 bits */
985 #define MEM_RSEXIT_MASK 0xc000
986 #define MEM_RSEXIT_SHIFT 14
987 #define MEM_CONT_BUSY_MASK 0x3000
988 #define MEM_CONT_BUSY_SHIFT 12
989 #define MEM_AVG_BUSY_MASK 0x0c00
990 #define MEM_AVG_BUSY_SHIFT 10
991 #define MEM_EVAL_CHG_MASK 0x0300
992 #define MEM_EVAL_BUSY_SHIFT 8
993 #define MEM_MON_IDLE_MASK 0x00c0
994 #define MEM_MON_IDLE_SHIFT 6
995 #define MEM_UP_EVAL_MASK 0x0030
996 #define MEM_UP_EVAL_SHIFT 4
997 #define MEM_DOWN_EVAL_MASK 0x000c
998 #define MEM_DOWN_EVAL_SHIFT 2
999 #define MEM_SW_CMD_MASK 0x0003
1000 #define MEM_INT_STEER_GFX 0
1001 #define MEM_INT_STEER_CMR 1
1002 #define MEM_INT_STEER_SMI 2
1003 #define MEM_INT_STEER_SCI 3
1004 #define MEMINTRSTS 0x11184
1005 #define MEMINT_RSEXIT (1<<7)
1006 #define MEMINT_CONT_BUSY (1<<6)
1007 #define MEMINT_AVG_BUSY (1<<5)
1008 #define MEMINT_EVAL_CHG (1<<4)
1009 #define MEMINT_MON_IDLE (1<<3)
1010 #define MEMINT_UP_EVAL (1<<2)
1011 #define MEMINT_DOWN_EVAL (1<<1)
1012 #define MEMINT_SW_CMD (1<<0)
1013 #define MEMMODECTL 0x11190
1014 #define MEMMODE_BOOST_EN (1<<31)
1015 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1016 #define MEMMODE_BOOST_FREQ_SHIFT 24
1017 #define MEMMODE_IDLE_MODE_MASK 0x00030000
1018 #define MEMMODE_IDLE_MODE_SHIFT 16
1019 #define MEMMODE_IDLE_MODE_EVAL 0
1020 #define MEMMODE_IDLE_MODE_CONT 1
1021 #define MEMMODE_HWIDLE_EN (1<<15)
1022 #define MEMMODE_SWMODE_EN (1<<14)
1023 #define MEMMODE_RCLK_GATE (1<<13)
1024 #define MEMMODE_HW_UPDATE (1<<12)
1025 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1026 #define MEMMODE_FSTART_SHIFT 8
1027 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1028 #define MEMMODE_FMAX_SHIFT 4
1029 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1030 #define RCBMAXAVG 0x1119c
1031 #define MEMSWCTL2 0x1119e /* Cantiga only */
1032 #define SWMEMCMD_RENDER_OFF (0 << 13)
1033 #define SWMEMCMD_RENDER_ON (1 << 13)
1034 #define SWMEMCMD_SWFREQ (2 << 13)
1035 #define SWMEMCMD_TARVID (3 << 13)
1036 #define SWMEMCMD_VRM_OFF (4 << 13)
1037 #define SWMEMCMD_VRM_ON (5 << 13)
1038 #define CMDSTS (1<<12)
1039 #define SFCAVM (1<<11)
1040 #define SWFREQ_MASK 0x0380 /* P0-7 */
1041 #define SWFREQ_SHIFT 7
1042 #define TARVID_MASK 0x001f
1043 #define MEMSTAT_CTG 0x111a0
1044 #define RCBMINAVG 0x111a0
1045 #define RCUPEI 0x111b0
1046 #define RCDNEI 0x111b4
1047 #define MCHBAR_RENDER_STANDBY 0x111b8
1048 #define RCX_SW_EXIT (1<<23)
1049 #define RSX_STATUS_MASK 0x00700000
1050 #define VIDCTL 0x111c0
1051 #define VIDSTS 0x111c8
1052 #define VIDSTART 0x111cc /* 8 bits */
1053 #define MEMSTAT_ILK 0x111f8
1054 #define MEMSTAT_VID_MASK 0x7f00
1055 #define MEMSTAT_VID_SHIFT 8
1056 #define MEMSTAT_PSTATE_MASK 0x00f8
1057 #define MEMSTAT_PSTATE_SHIFT 3
1058 #define MEMSTAT_MON_ACTV (1<<2)
1059 #define MEMSTAT_SRC_CTL_MASK 0x0003
1060 #define MEMSTAT_SRC_CTL_CORE 0
1061 #define MEMSTAT_SRC_CTL_TRB 1
1062 #define MEMSTAT_SRC_CTL_THM 2
1063 #define MEMSTAT_SRC_CTL_STDBY 3
1064 #define RCPREVBSYTUPAVG 0x113b8
1065 #define RCPREVBSYTDNAVG 0x113bc
1066 #define SDEW 0x1124c
1067 #define CSIEW0 0x11250
1068 #define CSIEW1 0x11254
1069 #define CSIEW2 0x11258
1072 #define MCHAFE 0x112c0
1073 #define CSIEC 0x112e0
1074 #define DMIEC 0x112e4
1075 #define DDREC 0x112e8
1076 #define PEG0EC 0x112ec
1077 #define PEG1EC 0x112f0
1078 #define GFXEC 0x112f4
1079 #define RPPREVBSYTUPAVG 0x113b8
1080 #define RPPREVBSYTDNAVG 0x113bc
1082 #define ECR_GPFE (1<<31)
1083 #define ECR_IMONE (1<<30)
1084 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1085 #define OGW0 0x11608
1086 #define OGW1 0x1160c
1096 #define PXWL 0x11680
1097 #define LCFUSE02 0x116c0
1098 #define LCFUSE_HIV_MASK 0x000000ff
1099 #define CSIPLL0 0x12c10
1100 #define DDRMPLL1 0X12c20
1101 #define PEG_BAND_GAP_DATA 0x14d68
1107 #define OVADD 0x30000
1108 #define DOVSTA 0x30008
1109 #define OC_BUF (0x3<<20)
1110 #define OGAMC5 0x30010
1111 #define OGAMC4 0x30014
1112 #define OGAMC3 0x30018
1113 #define OGAMC2 0x3001c
1114 #define OGAMC1 0x30020
1115 #define OGAMC0 0x30024
1118 * Display engine regs
1121 /* Pipe A timing regs */
1122 #define HTOTAL_A 0x60000
1123 #define HBLANK_A 0x60004
1124 #define HSYNC_A 0x60008
1125 #define VTOTAL_A 0x6000c
1126 #define VBLANK_A 0x60010
1127 #define VSYNC_A 0x60014
1128 #define PIPEASRC 0x6001c
1129 #define BCLRPAT_A 0x60020
1131 /* Pipe B timing regs */
1132 #define HTOTAL_B 0x61000
1133 #define HBLANK_B 0x61004
1134 #define HSYNC_B 0x61008
1135 #define VTOTAL_B 0x6100c
1136 #define VBLANK_B 0x61010
1137 #define VSYNC_B 0x61014
1138 #define PIPEBSRC 0x6101c
1139 #define BCLRPAT_B 0x61020
1141 /* VGA port control */
1142 #define ADPA 0x61100
1143 #define ADPA_DAC_ENABLE (1<<31)
1144 #define ADPA_DAC_DISABLE 0
1145 #define ADPA_PIPE_SELECT_MASK (1<<30)
1146 #define ADPA_PIPE_A_SELECT 0
1147 #define ADPA_PIPE_B_SELECT (1<<30)
1148 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1149 #define ADPA_SETS_HVPOLARITY 0
1150 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1151 #define ADPA_VSYNC_CNTL_ENABLE 0
1152 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1153 #define ADPA_HSYNC_CNTL_ENABLE 0
1154 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1155 #define ADPA_VSYNC_ACTIVE_LOW 0
1156 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1157 #define ADPA_HSYNC_ACTIVE_LOW 0
1158 #define ADPA_DPMS_MASK (~(3<<10))
1159 #define ADPA_DPMS_ON (0<<10)
1160 #define ADPA_DPMS_SUSPEND (1<<10)
1161 #define ADPA_DPMS_STANDBY (2<<10)
1162 #define ADPA_DPMS_OFF (3<<10)
1164 /* Hotplug control (945+ only) */
1165 #define PORT_HOTPLUG_EN 0x61110
1166 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
1167 #define DPB_HOTPLUG_INT_EN (1 << 29)
1168 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
1169 #define DPC_HOTPLUG_INT_EN (1 << 28)
1170 #define HDMID_HOTPLUG_INT_EN (1 << 27)
1171 #define DPD_HOTPLUG_INT_EN (1 << 27)
1172 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1173 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1174 #define TV_HOTPLUG_INT_EN (1 << 18)
1175 #define CRT_HOTPLUG_INT_EN (1 << 9)
1176 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1177 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1178 /* must use period 64 on GM45 according to docs */
1179 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1180 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1181 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1182 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1183 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1184 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1185 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1186 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1187 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1188 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1189 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1190 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1192 #define PORT_HOTPLUG_STAT 0x61114
1193 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1194 #define DPB_HOTPLUG_INT_STATUS (1 << 29)
1195 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1196 #define DPC_HOTPLUG_INT_STATUS (1 << 28)
1197 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1198 #define DPD_HOTPLUG_INT_STATUS (1 << 27)
1199 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1200 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1201 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1202 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1203 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1204 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1205 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1206 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1208 /* SDVO port control */
1209 #define SDVOB 0x61140
1210 #define SDVOC 0x61160
1211 #define SDVO_ENABLE (1 << 31)
1212 #define SDVO_PIPE_B_SELECT (1 << 30)
1213 #define SDVO_STALL_SELECT (1 << 29)
1214 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1216 * 915G/GM SDVO pixel multiplier.
1218 * Programmed value is multiplier - 1, up to 5x.
1220 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1222 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1223 #define SDVO_PORT_MULTIPLY_SHIFT 23
1224 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1225 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1226 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1227 #define SDVOC_GANG_MODE (1 << 16)
1228 #define SDVO_ENCODING_SDVO (0x0 << 10)
1229 #define SDVO_ENCODING_HDMI (0x2 << 10)
1230 /** Requird for HDMI operation */
1231 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1232 #define SDVO_BORDER_ENABLE (1 << 7)
1233 #define SDVO_AUDIO_ENABLE (1 << 6)
1234 /** New with 965, default is to be set */
1235 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1236 /** New with 965, default is to be set */
1237 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1238 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1239 #define SDVO_DETECTED (1 << 2)
1240 /* Bits to be preserved when writing */
1241 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1242 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1244 /* DVO port control */
1245 #define DVOA 0x61120
1246 #define DVOB 0x61140
1247 #define DVOC 0x61160
1248 #define DVO_ENABLE (1 << 31)
1249 #define DVO_PIPE_B_SELECT (1 << 30)
1250 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1251 #define DVO_PIPE_STALL (1 << 28)
1252 #define DVO_PIPE_STALL_TV (2 << 28)
1253 #define DVO_PIPE_STALL_MASK (3 << 28)
1254 #define DVO_USE_VGA_SYNC (1 << 15)
1255 #define DVO_DATA_ORDER_I740 (0 << 14)
1256 #define DVO_DATA_ORDER_FP (1 << 14)
1257 #define DVO_VSYNC_DISABLE (1 << 11)
1258 #define DVO_HSYNC_DISABLE (1 << 10)
1259 #define DVO_VSYNC_TRISTATE (1 << 9)
1260 #define DVO_HSYNC_TRISTATE (1 << 8)
1261 #define DVO_BORDER_ENABLE (1 << 7)
1262 #define DVO_DATA_ORDER_GBRG (1 << 6)
1263 #define DVO_DATA_ORDER_RGGB (0 << 6)
1264 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1265 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1266 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1267 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1268 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1269 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1270 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1271 #define DVO_PRESERVE_MASK (0x7<<24)
1272 #define DVOA_SRCDIM 0x61124
1273 #define DVOB_SRCDIM 0x61144
1274 #define DVOC_SRCDIM 0x61164
1275 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1276 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1278 /* LVDS port control */
1279 #define LVDS 0x61180
1281 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1282 * the DPLL semantics change when the LVDS is assigned to that pipe.
1284 #define LVDS_PORT_EN (1 << 31)
1285 /* Selects pipe B for LVDS data. Must be set on pre-965. */
1286 #define LVDS_PIPEB_SELECT (1 << 30)
1287 /* LVDS dithering flag on 965/g4x platform */
1288 #define LVDS_ENABLE_DITHER (1 << 25)
1289 /* Enable border for unscaled (or aspect-scaled) display */
1290 #define LVDS_BORDER_ENABLE (1 << 15)
1292 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1295 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1296 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1297 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1299 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1300 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1303 #define LVDS_A3_POWER_MASK (3 << 6)
1304 #define LVDS_A3_POWER_DOWN (0 << 6)
1305 #define LVDS_A3_POWER_UP (3 << 6)
1307 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1310 #define LVDS_CLKB_POWER_MASK (3 << 4)
1311 #define LVDS_CLKB_POWER_DOWN (0 << 4)
1312 #define LVDS_CLKB_POWER_UP (3 << 4)
1314 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1315 * setting for whether we are in dual-channel mode. The B3 pair will
1316 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1318 #define LVDS_B0B3_POWER_MASK (3 << 2)
1319 #define LVDS_B0B3_POWER_DOWN (0 << 2)
1320 #define LVDS_B0B3_POWER_UP (3 << 2)
1322 /* Panel power sequencing */
1323 #define PP_STATUS 0x61200
1324 #define PP_ON (1 << 31)
1326 * Indicates that all dependencies of the panel are on:
1330 * - LVDS/DVOB/DVOC on
1332 #define PP_READY (1 << 30)
1333 #define PP_SEQUENCE_NONE (0 << 28)
1334 #define PP_SEQUENCE_ON (1 << 28)
1335 #define PP_SEQUENCE_OFF (2 << 28)
1336 #define PP_SEQUENCE_MASK 0x30000000
1337 #define PP_CONTROL 0x61204
1338 #define POWER_TARGET_ON (1 << 0)
1339 #define PP_ON_DELAYS 0x61208
1340 #define PP_OFF_DELAYS 0x6120c
1341 #define PP_DIVISOR 0x61210
1344 #define PFIT_CONTROL 0x61230
1345 #define PFIT_ENABLE (1 << 31)
1346 #define PFIT_PIPE_MASK (3 << 29)
1347 #define PFIT_PIPE_SHIFT 29
1348 #define VERT_INTERP_DISABLE (0 << 10)
1349 #define VERT_INTERP_BILINEAR (1 << 10)
1350 #define VERT_INTERP_MASK (3 << 10)
1351 #define VERT_AUTO_SCALE (1 << 9)
1352 #define HORIZ_INTERP_DISABLE (0 << 6)
1353 #define HORIZ_INTERP_BILINEAR (1 << 6)
1354 #define HORIZ_INTERP_MASK (3 << 6)
1355 #define HORIZ_AUTO_SCALE (1 << 5)
1356 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1357 #define PFIT_FILTER_FUZZY (0 << 24)
1358 #define PFIT_SCALING_AUTO (0 << 26)
1359 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1360 #define PFIT_SCALING_PILLAR (2 << 26)
1361 #define PFIT_SCALING_LETTER (3 << 26)
1362 #define PFIT_PGM_RATIOS 0x61234
1363 #define PFIT_VERT_SCALE_MASK 0xfff00000
1364 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1366 #define PFIT_VERT_SCALE_SHIFT 20
1367 #define PFIT_VERT_SCALE_MASK 0xfff00000
1368 #define PFIT_HORIZ_SCALE_SHIFT 4
1369 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1371 #define PFIT_VERT_SCALE_SHIFT_965 16
1372 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1373 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1374 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1376 #define PFIT_AUTO_RATIOS 0x61238
1378 /* Backlight control */
1379 #define BLC_PWM_CTL 0x61254
1380 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1381 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1382 #define BLM_COMBINATION_MODE (1 << 30)
1384 * This is the most significant 15 bits of the number of backlight cycles in a
1385 * complete cycle of the modulated backlight control.
1387 * The actual value is this field multiplied by two.
1389 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1390 #define BLM_LEGACY_MODE (1 << 16)
1392 * This is the number of cycles out of the backlight modulation cycle for which
1393 * the backlight is on.
1395 * This field must be no greater than the number of cycles in the complete
1396 * backlight modulation cycle.
1398 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1399 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1401 #define BLC_HIST_CTL 0x61260
1403 /* TV port control */
1404 #define TV_CTL 0x68000
1405 /** Enables the TV encoder */
1406 # define TV_ENC_ENABLE (1 << 31)
1407 /** Sources the TV encoder input from pipe B instead of A. */
1408 # define TV_ENC_PIPEB_SELECT (1 << 30)
1409 /** Outputs composite video (DAC A only) */
1410 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1411 /** Outputs SVideo video (DAC B/C) */
1412 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1413 /** Outputs Component video (DAC A/B/C) */
1414 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1415 /** Outputs Composite and SVideo (DAC A/B/C) */
1416 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1417 # define TV_TRILEVEL_SYNC (1 << 21)
1418 /** Enables slow sync generation (945GM only) */
1419 # define TV_SLOW_SYNC (1 << 20)
1420 /** Selects 4x oversampling for 480i and 576p */
1421 # define TV_OVERSAMPLE_4X (0 << 18)
1422 /** Selects 2x oversampling for 720p and 1080i */
1423 # define TV_OVERSAMPLE_2X (1 << 18)
1424 /** Selects no oversampling for 1080p */
1425 # define TV_OVERSAMPLE_NONE (2 << 18)
1426 /** Selects 8x oversampling */
1427 # define TV_OVERSAMPLE_8X (3 << 18)
1428 /** Selects progressive mode rather than interlaced */
1429 # define TV_PROGRESSIVE (1 << 17)
1430 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1431 # define TV_PAL_BURST (1 << 16)
1432 /** Field for setting delay of Y compared to C */
1433 # define TV_YC_SKEW_MASK (7 << 12)
1434 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1435 # define TV_ENC_SDP_FIX (1 << 11)
1437 * Enables a fix for the 915GM only.
1439 * Not sure what it does.
1441 # define TV_ENC_C0_FIX (1 << 10)
1442 /** Bits that must be preserved by software */
1443 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1444 # define TV_FUSE_STATE_MASK (3 << 4)
1445 /** Read-only state that reports all features enabled */
1446 # define TV_FUSE_STATE_ENABLED (0 << 4)
1447 /** Read-only state that reports that Macrovision is disabled in hardware*/
1448 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1449 /** Read-only state that reports that TV-out is disabled in hardware. */
1450 # define TV_FUSE_STATE_DISABLED (2 << 4)
1451 /** Normal operation */
1452 # define TV_TEST_MODE_NORMAL (0 << 0)
1453 /** Encoder test pattern 1 - combo pattern */
1454 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
1455 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1456 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
1457 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1458 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
1459 /** Encoder test pattern 4 - random noise */
1460 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
1461 /** Encoder test pattern 5 - linear color ramps */
1462 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
1464 * This test mode forces the DACs to 50% of full output.
1466 * This is used for load detection in combination with TVDAC_SENSE_MASK
1468 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1469 # define TV_TEST_MODE_MASK (7 << 0)
1471 #define TV_DAC 0x68004
1473 * Reports that DAC state change logic has reported change (RO).
1475 * This gets cleared when TV_DAC_STATE_EN is cleared
1477 # define TVDAC_STATE_CHG (1 << 31)
1478 # define TVDAC_SENSE_MASK (7 << 28)
1479 /** Reports that DAC A voltage is above the detect threshold */
1480 # define TVDAC_A_SENSE (1 << 30)
1481 /** Reports that DAC B voltage is above the detect threshold */
1482 # define TVDAC_B_SENSE (1 << 29)
1483 /** Reports that DAC C voltage is above the detect threshold */
1484 # define TVDAC_C_SENSE (1 << 28)
1486 * Enables DAC state detection logic, for load-based TV detection.
1488 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1489 * to off, for load detection to work.
1491 # define TVDAC_STATE_CHG_EN (1 << 27)
1492 /** Sets the DAC A sense value to high */
1493 # define TVDAC_A_SENSE_CTL (1 << 26)
1494 /** Sets the DAC B sense value to high */
1495 # define TVDAC_B_SENSE_CTL (1 << 25)
1496 /** Sets the DAC C sense value to high */
1497 # define TVDAC_C_SENSE_CTL (1 << 24)
1498 /** Overrides the ENC_ENABLE and DAC voltage levels */
1499 # define DAC_CTL_OVERRIDE (1 << 7)
1500 /** Sets the slew rate. Must be preserved in software */
1501 # define ENC_TVDAC_SLEW_FAST (1 << 6)
1502 # define DAC_A_1_3_V (0 << 4)
1503 # define DAC_A_1_1_V (1 << 4)
1504 # define DAC_A_0_7_V (2 << 4)
1505 # define DAC_A_MASK (3 << 4)
1506 # define DAC_B_1_3_V (0 << 2)
1507 # define DAC_B_1_1_V (1 << 2)
1508 # define DAC_B_0_7_V (2 << 2)
1509 # define DAC_B_MASK (3 << 2)
1510 # define DAC_C_1_3_V (0 << 0)
1511 # define DAC_C_1_1_V (1 << 0)
1512 # define DAC_C_0_7_V (2 << 0)
1513 # define DAC_C_MASK (3 << 0)
1516 * CSC coefficients are stored in a floating point format with 9 bits of
1517 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1518 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1519 * -1 (0x3) being the only legal negative value.
1521 #define TV_CSC_Y 0x68010
1522 # define TV_RY_MASK 0x07ff0000
1523 # define TV_RY_SHIFT 16
1524 # define TV_GY_MASK 0x00000fff
1525 # define TV_GY_SHIFT 0
1527 #define TV_CSC_Y2 0x68014
1528 # define TV_BY_MASK 0x07ff0000
1529 # define TV_BY_SHIFT 16
1531 * Y attenuation for component video.
1533 * Stored in 1.9 fixed point.
1535 # define TV_AY_MASK 0x000003ff
1536 # define TV_AY_SHIFT 0
1538 #define TV_CSC_U 0x68018
1539 # define TV_RU_MASK 0x07ff0000
1540 # define TV_RU_SHIFT 16
1541 # define TV_GU_MASK 0x000007ff
1542 # define TV_GU_SHIFT 0
1544 #define TV_CSC_U2 0x6801c
1545 # define TV_BU_MASK 0x07ff0000
1546 # define TV_BU_SHIFT 16
1548 * U attenuation for component video.
1550 * Stored in 1.9 fixed point.
1552 # define TV_AU_MASK 0x000003ff
1553 # define TV_AU_SHIFT 0
1555 #define TV_CSC_V 0x68020
1556 # define TV_RV_MASK 0x0fff0000
1557 # define TV_RV_SHIFT 16
1558 # define TV_GV_MASK 0x000007ff
1559 # define TV_GV_SHIFT 0
1561 #define TV_CSC_V2 0x68024
1562 # define TV_BV_MASK 0x07ff0000
1563 # define TV_BV_SHIFT 16
1565 * V attenuation for component video.
1567 * Stored in 1.9 fixed point.
1569 # define TV_AV_MASK 0x000007ff
1570 # define TV_AV_SHIFT 0
1572 #define TV_CLR_KNOBS 0x68028
1573 /** 2s-complement brightness adjustment */
1574 # define TV_BRIGHTNESS_MASK 0xff000000
1575 # define TV_BRIGHTNESS_SHIFT 24
1576 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1577 # define TV_CONTRAST_MASK 0x00ff0000
1578 # define TV_CONTRAST_SHIFT 16
1579 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1580 # define TV_SATURATION_MASK 0x0000ff00
1581 # define TV_SATURATION_SHIFT 8
1582 /** Hue adjustment, as an integer phase angle in degrees */
1583 # define TV_HUE_MASK 0x000000ff
1584 # define TV_HUE_SHIFT 0
1586 #define TV_CLR_LEVEL 0x6802c
1587 /** Controls the DAC level for black */
1588 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1589 # define TV_BLACK_LEVEL_SHIFT 16
1590 /** Controls the DAC level for blanking */
1591 # define TV_BLANK_LEVEL_MASK 0x000001ff
1592 # define TV_BLANK_LEVEL_SHIFT 0
1594 #define TV_H_CTL_1 0x68030
1595 /** Number of pixels in the hsync. */
1596 # define TV_HSYNC_END_MASK 0x1fff0000
1597 # define TV_HSYNC_END_SHIFT 16
1598 /** Total number of pixels minus one in the line (display and blanking). */
1599 # define TV_HTOTAL_MASK 0x00001fff
1600 # define TV_HTOTAL_SHIFT 0
1602 #define TV_H_CTL_2 0x68034
1603 /** Enables the colorburst (needed for non-component color) */
1604 # define TV_BURST_ENA (1 << 31)
1605 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1606 # define TV_HBURST_START_SHIFT 16
1607 # define TV_HBURST_START_MASK 0x1fff0000
1608 /** Length of the colorburst */
1609 # define TV_HBURST_LEN_SHIFT 0
1610 # define TV_HBURST_LEN_MASK 0x0001fff
1612 #define TV_H_CTL_3 0x68038
1613 /** End of hblank, measured in pixels minus one from start of hsync */
1614 # define TV_HBLANK_END_SHIFT 16
1615 # define TV_HBLANK_END_MASK 0x1fff0000
1616 /** Start of hblank, measured in pixels minus one from start of hsync */
1617 # define TV_HBLANK_START_SHIFT 0
1618 # define TV_HBLANK_START_MASK 0x0001fff
1620 #define TV_V_CTL_1 0x6803c
1622 # define TV_NBR_END_SHIFT 16
1623 # define TV_NBR_END_MASK 0x07ff0000
1625 # define TV_VI_END_F1_SHIFT 8
1626 # define TV_VI_END_F1_MASK 0x00003f00
1628 # define TV_VI_END_F2_SHIFT 0
1629 # define TV_VI_END_F2_MASK 0x0000003f
1631 #define TV_V_CTL_2 0x68040
1632 /** Length of vsync, in half lines */
1633 # define TV_VSYNC_LEN_MASK 0x07ff0000
1634 # define TV_VSYNC_LEN_SHIFT 16
1635 /** Offset of the start of vsync in field 1, measured in one less than the
1636 * number of half lines.
1638 # define TV_VSYNC_START_F1_MASK 0x00007f00
1639 # define TV_VSYNC_START_F1_SHIFT 8
1641 * Offset of the start of vsync in field 2, measured in one less than the
1642 * number of half lines.
1644 # define TV_VSYNC_START_F2_MASK 0x0000007f
1645 # define TV_VSYNC_START_F2_SHIFT 0
1647 #define TV_V_CTL_3 0x68044
1648 /** Enables generation of the equalization signal */
1649 # define TV_EQUAL_ENA (1 << 31)
1650 /** Length of vsync, in half lines */
1651 # define TV_VEQ_LEN_MASK 0x007f0000
1652 # define TV_VEQ_LEN_SHIFT 16
1653 /** Offset of the start of equalization in field 1, measured in one less than
1654 * the number of half lines.
1656 # define TV_VEQ_START_F1_MASK 0x0007f00
1657 # define TV_VEQ_START_F1_SHIFT 8
1659 * Offset of the start of equalization in field 2, measured in one less than
1660 * the number of half lines.
1662 # define TV_VEQ_START_F2_MASK 0x000007f
1663 # define TV_VEQ_START_F2_SHIFT 0
1665 #define TV_V_CTL_4 0x68048
1667 * Offset to start of vertical colorburst, measured in one less than the
1668 * number of lines from vertical start.
1670 # define TV_VBURST_START_F1_MASK 0x003f0000
1671 # define TV_VBURST_START_F1_SHIFT 16
1673 * Offset to the end of vertical colorburst, measured in one less than the
1674 * number of lines from the start of NBR.
1676 # define TV_VBURST_END_F1_MASK 0x000000ff
1677 # define TV_VBURST_END_F1_SHIFT 0
1679 #define TV_V_CTL_5 0x6804c
1681 * Offset to start of vertical colorburst, measured in one less than the
1682 * number of lines from vertical start.
1684 # define TV_VBURST_START_F2_MASK 0x003f0000
1685 # define TV_VBURST_START_F2_SHIFT 16
1687 * Offset to the end of vertical colorburst, measured in one less than the
1688 * number of lines from the start of NBR.
1690 # define TV_VBURST_END_F2_MASK 0x000000ff
1691 # define TV_VBURST_END_F2_SHIFT 0
1693 #define TV_V_CTL_6 0x68050
1695 * Offset to start of vertical colorburst, measured in one less than the
1696 * number of lines from vertical start.
1698 # define TV_VBURST_START_F3_MASK 0x003f0000
1699 # define TV_VBURST_START_F3_SHIFT 16
1701 * Offset to the end of vertical colorburst, measured in one less than the
1702 * number of lines from the start of NBR.
1704 # define TV_VBURST_END_F3_MASK 0x000000ff
1705 # define TV_VBURST_END_F3_SHIFT 0
1707 #define TV_V_CTL_7 0x68054
1709 * Offset to start of vertical colorburst, measured in one less than the
1710 * number of lines from vertical start.
1712 # define TV_VBURST_START_F4_MASK 0x003f0000
1713 # define TV_VBURST_START_F4_SHIFT 16
1715 * Offset to the end of vertical colorburst, measured in one less than the
1716 * number of lines from the start of NBR.
1718 # define TV_VBURST_END_F4_MASK 0x000000ff
1719 # define TV_VBURST_END_F4_SHIFT 0
1721 #define TV_SC_CTL_1 0x68060
1722 /** Turns on the first subcarrier phase generation DDA */
1723 # define TV_SC_DDA1_EN (1 << 31)
1724 /** Turns on the first subcarrier phase generation DDA */
1725 # define TV_SC_DDA2_EN (1 << 30)
1726 /** Turns on the first subcarrier phase generation DDA */
1727 # define TV_SC_DDA3_EN (1 << 29)
1728 /** Sets the subcarrier DDA to reset frequency every other field */
1729 # define TV_SC_RESET_EVERY_2 (0 << 24)
1730 /** Sets the subcarrier DDA to reset frequency every fourth field */
1731 # define TV_SC_RESET_EVERY_4 (1 << 24)
1732 /** Sets the subcarrier DDA to reset frequency every eighth field */
1733 # define TV_SC_RESET_EVERY_8 (2 << 24)
1734 /** Sets the subcarrier DDA to never reset the frequency */
1735 # define TV_SC_RESET_NEVER (3 << 24)
1736 /** Sets the peak amplitude of the colorburst.*/
1737 # define TV_BURST_LEVEL_MASK 0x00ff0000
1738 # define TV_BURST_LEVEL_SHIFT 16
1739 /** Sets the increment of the first subcarrier phase generation DDA */
1740 # define TV_SCDDA1_INC_MASK 0x00000fff
1741 # define TV_SCDDA1_INC_SHIFT 0
1743 #define TV_SC_CTL_2 0x68064
1744 /** Sets the rollover for the second subcarrier phase generation DDA */
1745 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1746 # define TV_SCDDA2_SIZE_SHIFT 16
1747 /** Sets the increent of the second subcarrier phase generation DDA */
1748 # define TV_SCDDA2_INC_MASK 0x00007fff
1749 # define TV_SCDDA2_INC_SHIFT 0
1751 #define TV_SC_CTL_3 0x68068
1752 /** Sets the rollover for the third subcarrier phase generation DDA */
1753 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1754 # define TV_SCDDA3_SIZE_SHIFT 16
1755 /** Sets the increent of the third subcarrier phase generation DDA */
1756 # define TV_SCDDA3_INC_MASK 0x00007fff
1757 # define TV_SCDDA3_INC_SHIFT 0
1759 #define TV_WIN_POS 0x68070
1760 /** X coordinate of the display from the start of horizontal active */
1761 # define TV_XPOS_MASK 0x1fff0000
1762 # define TV_XPOS_SHIFT 16
1763 /** Y coordinate of the display from the start of vertical active (NBR) */
1764 # define TV_YPOS_MASK 0x00000fff
1765 # define TV_YPOS_SHIFT 0
1767 #define TV_WIN_SIZE 0x68074
1768 /** Horizontal size of the display window, measured in pixels*/
1769 # define TV_XSIZE_MASK 0x1fff0000
1770 # define TV_XSIZE_SHIFT 16
1772 * Vertical size of the display window, measured in pixels.
1774 * Must be even for interlaced modes.
1776 # define TV_YSIZE_MASK 0x00000fff
1777 # define TV_YSIZE_SHIFT 0
1779 #define TV_FILTER_CTL_1 0x68080
1781 * Enables automatic scaling calculation.
1783 * If set, the rest of the registers are ignored, and the calculated values can
1784 * be read back from the register.
1786 # define TV_AUTO_SCALE (1 << 31)
1788 * Disables the vertical filter.
1790 * This is required on modes more than 1024 pixels wide */
1791 # define TV_V_FILTER_BYPASS (1 << 29)
1792 /** Enables adaptive vertical filtering */
1793 # define TV_VADAPT (1 << 28)
1794 # define TV_VADAPT_MODE_MASK (3 << 26)
1795 /** Selects the least adaptive vertical filtering mode */
1796 # define TV_VADAPT_MODE_LEAST (0 << 26)
1797 /** Selects the moderately adaptive vertical filtering mode */
1798 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1799 /** Selects the most adaptive vertical filtering mode */
1800 # define TV_VADAPT_MODE_MOST (3 << 26)
1802 * Sets the horizontal scaling factor.
1804 * This should be the fractional part of the horizontal scaling factor divided
1805 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1807 * (src width - 1) / ((oversample * dest width) - 1)
1809 # define TV_HSCALE_FRAC_MASK 0x00003fff
1810 # define TV_HSCALE_FRAC_SHIFT 0
1812 #define TV_FILTER_CTL_2 0x68084
1814 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1816 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1818 # define TV_VSCALE_INT_MASK 0x00038000
1819 # define TV_VSCALE_INT_SHIFT 15
1821 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1823 * \sa TV_VSCALE_INT_MASK
1825 # define TV_VSCALE_FRAC_MASK 0x00007fff
1826 # define TV_VSCALE_FRAC_SHIFT 0
1828 #define TV_FILTER_CTL_3 0x68088
1830 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1832 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1834 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1836 # define TV_VSCALE_IP_INT_MASK 0x00038000
1837 # define TV_VSCALE_IP_INT_SHIFT 15
1839 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1841 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1843 * \sa TV_VSCALE_IP_INT_MASK
1845 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1846 # define TV_VSCALE_IP_FRAC_SHIFT 0
1848 #define TV_CC_CONTROL 0x68090
1849 # define TV_CC_ENABLE (1 << 31)
1851 * Specifies which field to send the CC data in.
1853 * CC data is usually sent in field 0.
1855 # define TV_CC_FID_MASK (1 << 27)
1856 # define TV_CC_FID_SHIFT 27
1857 /** Sets the horizontal position of the CC data. Usually 135. */
1858 # define TV_CC_HOFF_MASK 0x03ff0000
1859 # define TV_CC_HOFF_SHIFT 16
1860 /** Sets the vertical position of the CC data. Usually 21 */
1861 # define TV_CC_LINE_MASK 0x0000003f
1862 # define TV_CC_LINE_SHIFT 0
1864 #define TV_CC_DATA 0x68094
1865 # define TV_CC_RDY (1 << 31)
1866 /** Second word of CC data to be transmitted. */
1867 # define TV_CC_DATA_2_MASK 0x007f0000
1868 # define TV_CC_DATA_2_SHIFT 16
1869 /** First word of CC data to be transmitted. */
1870 # define TV_CC_DATA_1_MASK 0x0000007f
1871 # define TV_CC_DATA_1_SHIFT 0
1873 #define TV_H_LUMA_0 0x68100
1874 #define TV_H_LUMA_59 0x681ec
1875 #define TV_H_CHROMA_0 0x68200
1876 #define TV_H_CHROMA_59 0x682ec
1877 #define TV_V_LUMA_0 0x68300
1878 #define TV_V_LUMA_42 0x683a8
1879 #define TV_V_CHROMA_0 0x68400
1880 #define TV_V_CHROMA_42 0x684a8
1883 #define DP_A 0x64000 /* eDP */
1884 #define DP_B 0x64100
1885 #define DP_C 0x64200
1886 #define DP_D 0x64300
1888 #define DP_PORT_EN (1 << 31)
1889 #define DP_PIPEB_SELECT (1 << 30)
1891 /* Link training mode - select a suitable mode for each stage */
1892 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
1893 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
1894 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1895 #define DP_LINK_TRAIN_OFF (3 << 28)
1896 #define DP_LINK_TRAIN_MASK (3 << 28)
1897 #define DP_LINK_TRAIN_SHIFT 28
1899 /* CPT Link training mode */
1900 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
1901 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
1902 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
1903 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
1904 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
1905 #define DP_LINK_TRAIN_SHIFT_CPT 8
1907 /* Signal voltages. These are mostly controlled by the other end */
1908 #define DP_VOLTAGE_0_4 (0 << 25)
1909 #define DP_VOLTAGE_0_6 (1 << 25)
1910 #define DP_VOLTAGE_0_8 (2 << 25)
1911 #define DP_VOLTAGE_1_2 (3 << 25)
1912 #define DP_VOLTAGE_MASK (7 << 25)
1913 #define DP_VOLTAGE_SHIFT 25
1915 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1918 #define DP_PRE_EMPHASIS_0 (0 << 22)
1919 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
1920 #define DP_PRE_EMPHASIS_6 (2 << 22)
1921 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
1922 #define DP_PRE_EMPHASIS_MASK (7 << 22)
1923 #define DP_PRE_EMPHASIS_SHIFT 22
1925 /* How many wires to use. I guess 3 was too hard */
1926 #define DP_PORT_WIDTH_1 (0 << 19)
1927 #define DP_PORT_WIDTH_2 (1 << 19)
1928 #define DP_PORT_WIDTH_4 (3 << 19)
1929 #define DP_PORT_WIDTH_MASK (7 << 19)
1931 /* Mystic DPCD version 1.1 special mode */
1932 #define DP_ENHANCED_FRAMING (1 << 18)
1935 #define DP_PLL_FREQ_270MHZ (0 << 16)
1936 #define DP_PLL_FREQ_160MHZ (1 << 16)
1937 #define DP_PLL_FREQ_MASK (3 << 16)
1939 /** locked once port is enabled */
1940 #define DP_PORT_REVERSAL (1 << 15)
1943 #define DP_PLL_ENABLE (1 << 14)
1945 /** sends the clock on lane 15 of the PEG for debug */
1946 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1948 #define DP_SCRAMBLING_DISABLE (1 << 12)
1949 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
1951 /** limit RGB values to avoid confusing TVs */
1952 #define DP_COLOR_RANGE_16_235 (1 << 8)
1954 /** Turn on the audio link */
1955 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1957 /** vs and hs sync polarity */
1958 #define DP_SYNC_VS_HIGH (1 << 4)
1959 #define DP_SYNC_HS_HIGH (1 << 3)
1962 #define DP_DETECTED (1 << 2)
1964 /** The aux channel provides a way to talk to the
1965 * signal sink for DDC etc. Max packet size supported
1966 * is 20 bytes in each direction, hence the 5 fixed
1969 #define DPA_AUX_CH_CTL 0x64010
1970 #define DPA_AUX_CH_DATA1 0x64014
1971 #define DPA_AUX_CH_DATA2 0x64018
1972 #define DPA_AUX_CH_DATA3 0x6401c
1973 #define DPA_AUX_CH_DATA4 0x64020
1974 #define DPA_AUX_CH_DATA5 0x64024
1976 #define DPB_AUX_CH_CTL 0x64110
1977 #define DPB_AUX_CH_DATA1 0x64114
1978 #define DPB_AUX_CH_DATA2 0x64118
1979 #define DPB_AUX_CH_DATA3 0x6411c
1980 #define DPB_AUX_CH_DATA4 0x64120
1981 #define DPB_AUX_CH_DATA5 0x64124
1983 #define DPC_AUX_CH_CTL 0x64210
1984 #define DPC_AUX_CH_DATA1 0x64214
1985 #define DPC_AUX_CH_DATA2 0x64218
1986 #define DPC_AUX_CH_DATA3 0x6421c
1987 #define DPC_AUX_CH_DATA4 0x64220
1988 #define DPC_AUX_CH_DATA5 0x64224
1990 #define DPD_AUX_CH_CTL 0x64310
1991 #define DPD_AUX_CH_DATA1 0x64314
1992 #define DPD_AUX_CH_DATA2 0x64318
1993 #define DPD_AUX_CH_DATA3 0x6431c
1994 #define DPD_AUX_CH_DATA4 0x64320
1995 #define DPD_AUX_CH_DATA5 0x64324
1997 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
1998 #define DP_AUX_CH_CTL_DONE (1 << 30)
1999 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2000 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2001 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2002 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2003 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2004 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2005 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2006 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2007 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2008 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2009 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2010 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2011 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2012 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2013 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2014 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2015 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2016 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2017 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2020 * Computing GMCH M and N values for the Display Port link
2022 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2024 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2026 * The GMCH value is used internally
2028 * bytes_per_pixel is the number of bytes coming out of the plane,
2029 * which is after the LUTs, so we want the bytes for our color format.
2030 * For our current usage, this is always 3, one byte for R, G and B.
2032 #define PIPEA_GMCH_DATA_M 0x70050
2033 #define PIPEB_GMCH_DATA_M 0x71050
2035 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2036 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2037 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2039 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
2041 #define PIPEA_GMCH_DATA_N 0x70054
2042 #define PIPEB_GMCH_DATA_N 0x71054
2043 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
2046 * Computing Link M and N values for the Display Port link
2048 * Link M / N = pixel_clock / ls_clk
2050 * (the DP spec calls pixel_clock the 'strm_clk')
2052 * The Link value is transmitted in the Main Stream
2053 * Attributes and VB-ID.
2056 #define PIPEA_DP_LINK_M 0x70060
2057 #define PIPEB_DP_LINK_M 0x71060
2058 #define PIPEA_DP_LINK_M_MASK (0xffffff)
2060 #define PIPEA_DP_LINK_N 0x70064
2061 #define PIPEB_DP_LINK_N 0x71064
2062 #define PIPEA_DP_LINK_N_MASK (0xffffff)
2064 /* Display & cursor control */
2066 /* dithering flag on Ironlake */
2067 #define PIPE_ENABLE_DITHER (1 << 4)
2068 #define PIPE_DITHER_TYPE_MASK (3 << 2)
2069 #define PIPE_DITHER_TYPE_SPATIAL (0 << 2)
2070 #define PIPE_DITHER_TYPE_ST01 (1 << 2)
2072 #define PIPEADSL 0x70000
2073 #define PIPEACONF 0x70008
2074 #define PIPEACONF_ENABLE (1<<31)
2075 #define PIPEACONF_DISABLE 0
2076 #define PIPEACONF_DOUBLE_WIDE (1<<30)
2077 #define I965_PIPECONF_ACTIVE (1<<30)
2078 #define PIPEACONF_SINGLE_WIDE 0
2079 #define PIPEACONF_PIPE_UNLOCKED 0
2080 #define PIPEACONF_PIPE_LOCKED (1<<25)
2081 #define PIPEACONF_PALETTE 0
2082 #define PIPEACONF_GAMMA (1<<24)
2083 #define PIPECONF_FORCE_BORDER (1<<25)
2084 #define PIPECONF_PROGRESSIVE (0 << 21)
2085 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2086 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2087 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2088 #define PIPEASTAT 0x70024
2089 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2090 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2091 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
2092 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2093 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2094 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2095 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2096 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2097 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2098 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2099 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2100 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2101 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2102 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2103 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2104 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2105 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2106 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2107 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2108 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2109 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2110 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
2111 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2112 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2113 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2114 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2115 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2116 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2117 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2118 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2119 #define PIPE_8BPC (0 << 5)
2120 #define PIPE_10BPC (1 << 5)
2121 #define PIPE_6BPC (2 << 5)
2122 #define PIPE_12BPC (3 << 5)
2124 #define DSPARB 0x70030
2125 #define DSPARB_CSTART_MASK (0x7f << 7)
2126 #define DSPARB_CSTART_SHIFT 7
2127 #define DSPARB_BSTART_MASK (0x7f)
2128 #define DSPARB_BSTART_SHIFT 0
2129 #define DSPARB_BEND_SHIFT 9 /* on 855 */
2130 #define DSPARB_AEND_SHIFT 0
2132 #define DSPFW1 0x70034
2133 #define DSPFW_SR_SHIFT 23
2134 #define DSPFW_SR_MASK (0x1ff<<23)
2135 #define DSPFW_CURSORB_SHIFT 16
2136 #define DSPFW_CURSORB_MASK (0x3f<<16)
2137 #define DSPFW_PLANEB_SHIFT 8
2138 #define DSPFW_PLANEB_MASK (0x7f<<8)
2139 #define DSPFW_PLANEA_MASK (0x7f)
2140 #define DSPFW2 0x70038
2141 #define DSPFW_CURSORA_MASK 0x00003f00
2142 #define DSPFW_CURSORA_SHIFT 8
2143 #define DSPFW_PLANEC_MASK (0x7f)
2144 #define DSPFW3 0x7003c
2145 #define DSPFW_HPLL_SR_EN (1<<31)
2146 #define DSPFW_CURSOR_SR_SHIFT 24
2147 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
2148 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2149 #define DSPFW_HPLL_CURSOR_SHIFT 16
2150 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2151 #define DSPFW_HPLL_SR_MASK (0x1ff)
2153 /* FIFO watermark sizes etc */
2154 #define G4X_FIFO_LINE_SIZE 64
2155 #define I915_FIFO_LINE_SIZE 64
2156 #define I830_FIFO_LINE_SIZE 32
2158 #define G4X_FIFO_SIZE 127
2159 #define I965_FIFO_SIZE 512
2160 #define I945_FIFO_SIZE 127
2161 #define I915_FIFO_SIZE 95
2162 #define I855GM_FIFO_SIZE 127 /* In cachelines */
2163 #define I830_FIFO_SIZE 95
2165 #define G4X_MAX_WM 0x3f
2166 #define I915_MAX_WM 0x3f
2168 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2169 #define PINEVIEW_FIFO_LINE_SIZE 64
2170 #define PINEVIEW_MAX_WM 0x1ff
2171 #define PINEVIEW_DFT_WM 0x3f
2172 #define PINEVIEW_DFT_HPLLOFF_WM 0
2173 #define PINEVIEW_GUARD_WM 10
2174 #define PINEVIEW_CURSOR_FIFO 64
2175 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2176 #define PINEVIEW_CURSOR_DFT_WM 0
2177 #define PINEVIEW_CURSOR_GUARD_WM 5
2179 #define I965_CURSOR_FIFO 64
2180 #define I965_CURSOR_MAX_WM 32
2181 #define I965_CURSOR_DFT_WM 8
2183 /* define the Watermark register on Ironlake */
2184 #define WM0_PIPEA_ILK 0x45100
2185 #define WM0_PIPE_PLANE_MASK (0x7f<<16)
2186 #define WM0_PIPE_PLANE_SHIFT 16
2187 #define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2188 #define WM0_PIPE_SPRITE_SHIFT 8
2189 #define WM0_PIPE_CURSOR_MASK (0x1f)
2191 #define WM0_PIPEB_ILK 0x45104
2192 #define WM1_LP_ILK 0x45108
2193 #define WM1_LP_SR_EN (1<<31)
2194 #define WM1_LP_LATENCY_SHIFT 24
2195 #define WM1_LP_LATENCY_MASK (0x7f<<24)
2196 #define WM1_LP_SR_MASK (0x1ff<<8)
2197 #define WM1_LP_SR_SHIFT 8
2198 #define WM1_LP_CURSOR_MASK (0x3f)
2200 /* Memory latency timer register */
2201 #define MLTR_ILK 0x11222
2202 /* the unit of memory self-refresh latency time is 0.5us */
2203 #define ILK_SRLT_MASK 0x3f
2205 /* define the fifo size on Ironlake */
2206 #define ILK_DISPLAY_FIFO 128
2207 #define ILK_DISPLAY_MAXWM 64
2208 #define ILK_DISPLAY_DFTWM 8
2209 #define ILK_CURSOR_FIFO 32
2210 #define ILK_CURSOR_MAXWM 16
2211 #define ILK_CURSOR_DFTWM 8
2213 #define ILK_DISPLAY_SR_FIFO 512
2214 #define ILK_DISPLAY_MAX_SRWM 0x1ff
2215 #define ILK_DISPLAY_DFT_SRWM 0x3f
2216 #define ILK_CURSOR_SR_FIFO 64
2217 #define ILK_CURSOR_MAX_SRWM 0x3f
2218 #define ILK_CURSOR_DFT_SRWM 8
2220 #define ILK_FIFO_LINE_SIZE 64
2223 * The two pipe frame counter registers are not synchronized, so
2224 * reading a stable value is somewhat tricky. The following code
2228 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2229 * PIPE_FRAME_HIGH_SHIFT;
2230 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2231 * PIPE_FRAME_LOW_SHIFT);
2232 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2233 * PIPE_FRAME_HIGH_SHIFT);
2234 * } while (high1 != high2);
2235 * frame = (high1 << 8) | low1;
2237 #define PIPEAFRAMEHIGH 0x70040
2238 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2239 #define PIPE_FRAME_HIGH_SHIFT 0
2240 #define PIPEAFRAMEPIXEL 0x70044
2241 #define PIPE_FRAME_LOW_MASK 0xff000000
2242 #define PIPE_FRAME_LOW_SHIFT 24
2243 #define PIPE_PIXEL_MASK 0x00ffffff
2244 #define PIPE_PIXEL_SHIFT 0
2245 /* GM45+ just has to be different */
2246 #define PIPEA_FRMCOUNT_GM45 0x70040
2247 #define PIPEA_FLIPCOUNT_GM45 0x70044
2249 /* Cursor A & B regs */
2250 #define CURACNTR 0x70080
2251 /* Old style CUR*CNTR flags (desktop 8xx) */
2252 #define CURSOR_ENABLE 0x80000000
2253 #define CURSOR_GAMMA_ENABLE 0x40000000
2254 #define CURSOR_STRIDE_MASK 0x30000000
2255 #define CURSOR_FORMAT_SHIFT 24
2256 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2257 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2258 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2259 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2260 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2261 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2262 /* New style CUR*CNTR flags */
2263 #define CURSOR_MODE 0x27
2264 #define CURSOR_MODE_DISABLE 0x00
2265 #define CURSOR_MODE_64_32B_AX 0x07
2266 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2267 #define MCURSOR_PIPE_SELECT (1 << 28)
2268 #define MCURSOR_PIPE_A 0x00
2269 #define MCURSOR_PIPE_B (1 << 28)
2270 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2271 #define CURABASE 0x70084
2272 #define CURAPOS 0x70088
2273 #define CURSOR_POS_MASK 0x007FF
2274 #define CURSOR_POS_SIGN 0x8000
2275 #define CURSOR_X_SHIFT 0
2276 #define CURSOR_Y_SHIFT 16
2277 #define CURSIZE 0x700a0
2278 #define CURBCNTR 0x700c0
2279 #define CURBBASE 0x700c4
2280 #define CURBPOS 0x700c8
2282 /* Display A control */
2283 #define DSPACNTR 0x70180
2284 #define DISPLAY_PLANE_ENABLE (1<<31)
2285 #define DISPLAY_PLANE_DISABLE 0
2286 #define DISPPLANE_GAMMA_ENABLE (1<<30)
2287 #define DISPPLANE_GAMMA_DISABLE 0
2288 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2289 #define DISPPLANE_8BPP (0x2<<26)
2290 #define DISPPLANE_15_16BPP (0x4<<26)
2291 #define DISPPLANE_16BPP (0x5<<26)
2292 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2293 #define DISPPLANE_32BPP (0x7<<26)
2294 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2295 #define DISPPLANE_STEREO_ENABLE (1<<25)
2296 #define DISPPLANE_STEREO_DISABLE 0
2297 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
2298 #define DISPPLANE_SEL_PIPE_A 0
2299 #define DISPPLANE_SEL_PIPE_B (1<<24)
2300 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2301 #define DISPPLANE_SRC_KEY_DISABLE 0
2302 #define DISPPLANE_LINE_DOUBLE (1<<20)
2303 #define DISPPLANE_NO_LINE_DOUBLE 0
2304 #define DISPPLANE_STEREO_POLARITY_FIRST 0
2305 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2306 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2307 #define DISPPLANE_TILED (1<<10)
2308 #define DSPAADDR 0x70184
2309 #define DSPASTRIDE 0x70188
2310 #define DSPAPOS 0x7018C /* reserved */
2311 #define DSPASIZE 0x70190
2312 #define DSPASURF 0x7019C /* 965+ only */
2313 #define DSPATILEOFF 0x701A4 /* 965+ only */
2316 #define SWF00 0x71410
2317 #define SWF01 0x71414
2318 #define SWF02 0x71418
2319 #define SWF03 0x7141c
2320 #define SWF04 0x71420
2321 #define SWF05 0x71424
2322 #define SWF06 0x71428
2323 #define SWF10 0x70410
2324 #define SWF11 0x70414
2325 #define SWF14 0x71420
2326 #define SWF30 0x72414
2327 #define SWF31 0x72418
2328 #define SWF32 0x7241c
2331 #define PIPEBDSL 0x71000
2332 #define PIPEBCONF 0x71008
2333 #define PIPEBSTAT 0x71024
2334 #define PIPEBFRAMEHIGH 0x71040
2335 #define PIPEBFRAMEPIXEL 0x71044
2336 #define PIPEB_FRMCOUNT_GM45 0x71040
2337 #define PIPEB_FLIPCOUNT_GM45 0x71044
2340 /* Display B control */
2341 #define DSPBCNTR 0x71180
2342 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2343 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
2344 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2345 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2346 #define DSPBADDR 0x71184
2347 #define DSPBSTRIDE 0x71188
2348 #define DSPBPOS 0x7118C
2349 #define DSPBSIZE 0x71190
2350 #define DSPBSURF 0x7119C
2351 #define DSPBTILEOFF 0x711A4
2354 #define VGACNTRL 0x71400
2355 # define VGA_DISP_DISABLE (1 << 31)
2356 # define VGA_2X_MODE (1 << 30)
2357 # define VGA_PIPE_B_SELECT (1 << 29)
2361 #define CPU_VGACNTRL 0x41000
2363 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2364 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2365 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2366 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2367 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2368 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2369 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
2370 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2371 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2373 /* refresh rate hardware control */
2374 #define RR_HW_CTL 0x45300
2375 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2376 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2378 #define FDI_PLL_BIOS_0 0x46000
2379 #define FDI_PLL_BIOS_1 0x46004
2380 #define FDI_PLL_BIOS_2 0x46008
2381 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2382 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
2383 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
2385 #define PCH_DSPCLK_GATE_D 0x42020
2386 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2387 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2389 #define PCH_3DCGDIS0 0x46020
2390 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2391 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2393 #define FDI_PLL_FREQ_CTL 0x46030
2394 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2395 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2396 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2399 #define PIPEA_DATA_M1 0x60030
2400 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2401 #define TU_SIZE_MASK 0x7e000000
2402 #define PIPEA_DATA_M1_OFFSET 0
2403 #define PIPEA_DATA_N1 0x60034
2404 #define PIPEA_DATA_N1_OFFSET 0
2406 #define PIPEA_DATA_M2 0x60038
2407 #define PIPEA_DATA_M2_OFFSET 0
2408 #define PIPEA_DATA_N2 0x6003c
2409 #define PIPEA_DATA_N2_OFFSET 0
2411 #define PIPEA_LINK_M1 0x60040
2412 #define PIPEA_LINK_M1_OFFSET 0
2413 #define PIPEA_LINK_N1 0x60044
2414 #define PIPEA_LINK_N1_OFFSET 0
2416 #define PIPEA_LINK_M2 0x60048
2417 #define PIPEA_LINK_M2_OFFSET 0
2418 #define PIPEA_LINK_N2 0x6004c
2419 #define PIPEA_LINK_N2_OFFSET 0
2421 /* PIPEB timing regs are same start from 0x61000 */
2423 #define PIPEB_DATA_M1 0x61030
2424 #define PIPEB_DATA_M1_OFFSET 0
2425 #define PIPEB_DATA_N1 0x61034
2426 #define PIPEB_DATA_N1_OFFSET 0
2428 #define PIPEB_DATA_M2 0x61038
2429 #define PIPEB_DATA_M2_OFFSET 0
2430 #define PIPEB_DATA_N2 0x6103c
2431 #define PIPEB_DATA_N2_OFFSET 0
2433 #define PIPEB_LINK_M1 0x61040
2434 #define PIPEB_LINK_M1_OFFSET 0
2435 #define PIPEB_LINK_N1 0x61044
2436 #define PIPEB_LINK_N1_OFFSET 0
2438 #define PIPEB_LINK_M2 0x61048
2439 #define PIPEB_LINK_M2_OFFSET 0
2440 #define PIPEB_LINK_N2 0x6104c
2441 #define PIPEB_LINK_N2_OFFSET 0
2443 /* CPU panel fitter */
2444 #define PFA_CTL_1 0x68080
2445 #define PFB_CTL_1 0x68880
2446 #define PF_ENABLE (1<<31)
2447 #define PF_FILTER_MASK (3<<23)
2448 #define PF_FILTER_PROGRAMMED (0<<23)
2449 #define PF_FILTER_MED_3x3 (1<<23)
2450 #define PF_FILTER_EDGE_ENHANCE (2<<23)
2451 #define PF_FILTER_EDGE_SOFTEN (3<<23)
2452 #define PFA_WIN_SZ 0x68074
2453 #define PFB_WIN_SZ 0x68874
2454 #define PFA_WIN_POS 0x68070
2455 #define PFB_WIN_POS 0x68870
2457 /* legacy palette */
2458 #define LGC_PALETTE_A 0x4a000
2459 #define LGC_PALETTE_B 0x4a800
2462 #define DE_MASTER_IRQ_CONTROL (1 << 31)
2463 #define DE_SPRITEB_FLIP_DONE (1 << 29)
2464 #define DE_SPRITEA_FLIP_DONE (1 << 28)
2465 #define DE_PLANEB_FLIP_DONE (1 << 27)
2466 #define DE_PLANEA_FLIP_DONE (1 << 26)
2467 #define DE_PCU_EVENT (1 << 25)
2468 #define DE_GTT_FAULT (1 << 24)
2469 #define DE_POISON (1 << 23)
2470 #define DE_PERFORM_COUNTER (1 << 22)
2471 #define DE_PCH_EVENT (1 << 21)
2472 #define DE_AUX_CHANNEL_A (1 << 20)
2473 #define DE_DP_A_HOTPLUG (1 << 19)
2474 #define DE_GSE (1 << 18)
2475 #define DE_PIPEB_VBLANK (1 << 15)
2476 #define DE_PIPEB_EVEN_FIELD (1 << 14)
2477 #define DE_PIPEB_ODD_FIELD (1 << 13)
2478 #define DE_PIPEB_LINE_COMPARE (1 << 12)
2479 #define DE_PIPEB_VSYNC (1 << 11)
2480 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2481 #define DE_PIPEA_VBLANK (1 << 7)
2482 #define DE_PIPEA_EVEN_FIELD (1 << 6)
2483 #define DE_PIPEA_ODD_FIELD (1 << 5)
2484 #define DE_PIPEA_LINE_COMPARE (1 << 4)
2485 #define DE_PIPEA_VSYNC (1 << 3)
2486 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2488 #define DEISR 0x44000
2489 #define DEIMR 0x44004
2490 #define DEIIR 0x44008
2491 #define DEIER 0x4400c
2494 #define GT_PIPE_NOTIFY (1 << 4)
2495 #define GT_SYNC_STATUS (1 << 2)
2496 #define GT_USER_INTERRUPT (1 << 0)
2497 #define GT_BSD_USER_INTERRUPT (1 << 5)
2500 #define GTISR 0x44010
2501 #define GTIMR 0x44014
2502 #define GTIIR 0x44018
2503 #define GTIER 0x4401c
2505 #define ILK_DISPLAY_CHICKEN2 0x42004
2506 #define ILK_DPARB_GATE (1<<22)
2507 #define ILK_VSDPFD_FULL (1<<21)
2508 #define ILK_DSPCLK_GATE 0x42020
2509 #define ILK_DPARB_CLK_GATE (1<<5)
2510 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
2511 #define ILK_CLK_FBC (1<<7)
2512 #define ILK_DPFC_DIS1 (1<<8)
2513 #define ILK_DPFC_DIS2 (1<<9)
2515 #define DISP_ARB_CTL 0x45000
2516 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2517 #define DISP_FBC_WM_DIS (1<<15)
2521 /* south display engine interrupt */
2522 #define SDE_CRT_HOTPLUG (1 << 11)
2523 #define SDE_PORTD_HOTPLUG (1 << 10)
2524 #define SDE_PORTC_HOTPLUG (1 << 9)
2525 #define SDE_PORTB_HOTPLUG (1 << 8)
2526 #define SDE_SDVOB_HOTPLUG (1 << 6)
2527 #define SDE_HOTPLUG_MASK (0xf << 8)
2529 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
2530 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2531 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2532 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2534 #define SDEISR 0xc4000
2535 #define SDEIMR 0xc4004
2536 #define SDEIIR 0xc4008
2537 #define SDEIER 0xc400c
2539 /* digital port hotplug */
2540 #define PCH_PORT_HOTPLUG 0xc4030
2541 #define PORTD_HOTPLUG_ENABLE (1 << 20)
2542 #define PORTD_PULSE_DURATION_2ms (0)
2543 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2544 #define PORTD_PULSE_DURATION_6ms (2 << 18)
2545 #define PORTD_PULSE_DURATION_100ms (3 << 18)
2546 #define PORTD_HOTPLUG_NO_DETECT (0)
2547 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2548 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2549 #define PORTC_HOTPLUG_ENABLE (1 << 12)
2550 #define PORTC_PULSE_DURATION_2ms (0)
2551 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2552 #define PORTC_PULSE_DURATION_6ms (2 << 10)
2553 #define PORTC_PULSE_DURATION_100ms (3 << 10)
2554 #define PORTC_HOTPLUG_NO_DETECT (0)
2555 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2556 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2557 #define PORTB_HOTPLUG_ENABLE (1 << 4)
2558 #define PORTB_PULSE_DURATION_2ms (0)
2559 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2560 #define PORTB_PULSE_DURATION_6ms (2 << 2)
2561 #define PORTB_PULSE_DURATION_100ms (3 << 2)
2562 #define PORTB_HOTPLUG_NO_DETECT (0)
2563 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2564 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2566 #define PCH_GPIOA 0xc5010
2567 #define PCH_GPIOB 0xc5014
2568 #define PCH_GPIOC 0xc5018
2569 #define PCH_GPIOD 0xc501c
2570 #define PCH_GPIOE 0xc5020
2571 #define PCH_GPIOF 0xc5024
2573 #define PCH_GMBUS0 0xc5100
2574 #define PCH_GMBUS1 0xc5104
2575 #define PCH_GMBUS2 0xc5108
2576 #define PCH_GMBUS3 0xc510c
2577 #define PCH_GMBUS4 0xc5110
2578 #define PCH_GMBUS5 0xc5120
2580 #define PCH_DPLL_A 0xc6014
2581 #define PCH_DPLL_B 0xc6018
2583 #define PCH_FPA0 0xc6040
2584 #define PCH_FPA1 0xc6044
2585 #define PCH_FPB0 0xc6048
2586 #define PCH_FPB1 0xc604c
2588 #define PCH_DPLL_TEST 0xc606c
2590 #define PCH_DREF_CONTROL 0xC6200
2591 #define DREF_CONTROL_MASK 0x7fc3
2592 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2593 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2594 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2595 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2596 #define DREF_SSC_SOURCE_DISABLE (0<<11)
2597 #define DREF_SSC_SOURCE_ENABLE (2<<11)
2598 #define DREF_SSC_SOURCE_MASK (3<<11)
2599 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2600 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2601 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2602 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2603 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2604 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2605 #define DREF_SSC4_DOWNSPREAD (0<<6)
2606 #define DREF_SSC4_CENTERSPREAD (1<<6)
2607 #define DREF_SSC1_DISABLE (0<<1)
2608 #define DREF_SSC1_ENABLE (1<<1)
2609 #define DREF_SSC4_DISABLE (0)
2610 #define DREF_SSC4_ENABLE (1)
2612 #define PCH_RAWCLK_FREQ 0xc6204
2613 #define FDL_TP1_TIMER_SHIFT 12
2614 #define FDL_TP1_TIMER_MASK (3<<12)
2615 #define FDL_TP2_TIMER_SHIFT 10
2616 #define FDL_TP2_TIMER_MASK (3<<10)
2617 #define RAWCLK_FREQ_MASK 0x3ff
2619 #define PCH_DPLL_TMR_CFG 0xc6208
2621 #define PCH_SSC4_PARMS 0xc6210
2622 #define PCH_SSC4_AUX_PARMS 0xc6214
2624 #define PCH_DPLL_SEL 0xc7000
2625 #define TRANSA_DPLL_ENABLE (1<<3)
2626 #define TRANSA_DPLLB_SEL (1<<0)
2627 #define TRANSA_DPLLA_SEL 0
2628 #define TRANSB_DPLL_ENABLE (1<<7)
2629 #define TRANSB_DPLLB_SEL (1<<4)
2630 #define TRANSB_DPLLA_SEL (0)
2631 #define TRANSC_DPLL_ENABLE (1<<11)
2632 #define TRANSC_DPLLB_SEL (1<<8)
2633 #define TRANSC_DPLLA_SEL (0)
2637 #define TRANS_HTOTAL_A 0xe0000
2638 #define TRANS_HTOTAL_SHIFT 16
2639 #define TRANS_HACTIVE_SHIFT 0
2640 #define TRANS_HBLANK_A 0xe0004
2641 #define TRANS_HBLANK_END_SHIFT 16
2642 #define TRANS_HBLANK_START_SHIFT 0
2643 #define TRANS_HSYNC_A 0xe0008
2644 #define TRANS_HSYNC_END_SHIFT 16
2645 #define TRANS_HSYNC_START_SHIFT 0
2646 #define TRANS_VTOTAL_A 0xe000c
2647 #define TRANS_VTOTAL_SHIFT 16
2648 #define TRANS_VACTIVE_SHIFT 0
2649 #define TRANS_VBLANK_A 0xe0010
2650 #define TRANS_VBLANK_END_SHIFT 16
2651 #define TRANS_VBLANK_START_SHIFT 0
2652 #define TRANS_VSYNC_A 0xe0014
2653 #define TRANS_VSYNC_END_SHIFT 16
2654 #define TRANS_VSYNC_START_SHIFT 0
2656 #define TRANSA_DATA_M1 0xe0030
2657 #define TRANSA_DATA_N1 0xe0034
2658 #define TRANSA_DATA_M2 0xe0038
2659 #define TRANSA_DATA_N2 0xe003c
2660 #define TRANSA_DP_LINK_M1 0xe0040
2661 #define TRANSA_DP_LINK_N1 0xe0044
2662 #define TRANSA_DP_LINK_M2 0xe0048
2663 #define TRANSA_DP_LINK_N2 0xe004c
2665 #define TRANS_HTOTAL_B 0xe1000
2666 #define TRANS_HBLANK_B 0xe1004
2667 #define TRANS_HSYNC_B 0xe1008
2668 #define TRANS_VTOTAL_B 0xe100c
2669 #define TRANS_VBLANK_B 0xe1010
2670 #define TRANS_VSYNC_B 0xe1014
2672 #define TRANSB_DATA_M1 0xe1030
2673 #define TRANSB_DATA_N1 0xe1034
2674 #define TRANSB_DATA_M2 0xe1038
2675 #define TRANSB_DATA_N2 0xe103c
2676 #define TRANSB_DP_LINK_M1 0xe1040
2677 #define TRANSB_DP_LINK_N1 0xe1044
2678 #define TRANSB_DP_LINK_M2 0xe1048
2679 #define TRANSB_DP_LINK_N2 0xe104c
2681 #define TRANSACONF 0xf0008
2682 #define TRANSBCONF 0xf1008
2683 #define TRANS_DISABLE (0<<31)
2684 #define TRANS_ENABLE (1<<31)
2685 #define TRANS_STATE_MASK (1<<30)
2686 #define TRANS_STATE_DISABLE (0<<30)
2687 #define TRANS_STATE_ENABLE (1<<30)
2688 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
2689 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
2690 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
2691 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
2692 #define TRANS_DP_AUDIO_ONLY (1<<26)
2693 #define TRANS_DP_VIDEO_AUDIO (0<<26)
2694 #define TRANS_PROGRESSIVE (0<<21)
2695 #define TRANS_8BPC (0<<5)
2696 #define TRANS_10BPC (1<<5)
2697 #define TRANS_6BPC (2<<5)
2698 #define TRANS_12BPC (3<<5)
2700 #define FDI_RXA_CHICKEN 0xc200c
2701 #define FDI_RXB_CHICKEN 0xc2010
2702 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
2705 #define FDI_TXA_CTL 0x60100
2706 #define FDI_TXB_CTL 0x61100
2707 #define FDI_TX_DISABLE (0<<31)
2708 #define FDI_TX_ENABLE (1<<31)
2709 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
2710 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
2711 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
2712 #define FDI_LINK_TRAIN_NONE (3<<28)
2713 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
2714 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
2715 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
2716 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
2717 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
2718 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
2719 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
2720 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
2721 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
2722 SNB has different settings. */
2723 /* SNB A-stepping */
2724 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
2725 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
2726 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
2727 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
2728 /* SNB B-stepping */
2729 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
2730 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
2731 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
2732 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
2733 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
2734 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
2735 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
2736 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
2737 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
2738 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
2739 /* Ironlake: hardwired to 1 */
2740 #define FDI_TX_PLL_ENABLE (1<<14)
2741 /* both Tx and Rx */
2742 #define FDI_SCRAMBLING_ENABLE (0<<7)
2743 #define FDI_SCRAMBLING_DISABLE (1<<7)
2745 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
2746 #define FDI_RXA_CTL 0xf000c
2747 #define FDI_RXB_CTL 0xf100c
2748 #define FDI_RX_ENABLE (1<<31)
2749 #define FDI_RX_DISABLE (0<<31)
2750 /* train, dp width same as FDI_TX */
2751 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
2752 #define FDI_8BPC (0<<16)
2753 #define FDI_10BPC (1<<16)
2754 #define FDI_6BPC (2<<16)
2755 #define FDI_12BPC (3<<16)
2756 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
2757 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
2758 #define FDI_RX_PLL_ENABLE (1<<13)
2759 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
2760 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
2761 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
2762 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
2763 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2764 #define FDI_SEL_RAWCLK (0<<4)
2765 #define FDI_SEL_PCDCLK (1<<4)
2767 #define FDI_AUTO_TRAINING (1<<10)
2768 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
2769 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
2770 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
2771 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
2772 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
2774 #define FDI_RXA_MISC 0xf0010
2775 #define FDI_RXB_MISC 0xf1010
2776 #define FDI_RXA_TUSIZE1 0xf0030
2777 #define FDI_RXA_TUSIZE2 0xf0038
2778 #define FDI_RXB_TUSIZE1 0xf1030
2779 #define FDI_RXB_TUSIZE2 0xf1038
2781 /* FDI_RX interrupt register format */
2782 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
2783 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
2784 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
2785 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
2786 #define FDI_RX_FS_CODE_ERR (1<<6)
2787 #define FDI_RX_FE_CODE_ERR (1<<5)
2788 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
2789 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
2790 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
2791 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
2792 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
2794 #define FDI_RXA_IIR 0xf0014
2795 #define FDI_RXA_IMR 0xf0018
2796 #define FDI_RXB_IIR 0xf1014
2797 #define FDI_RXB_IMR 0xf1018
2799 #define FDI_PLL_CTL_1 0xfe000
2800 #define FDI_PLL_CTL_2 0xfe004
2803 #define PCH_ADPA 0xe1100
2804 #define ADPA_TRANS_SELECT_MASK (1<<30)
2805 #define ADPA_TRANS_A_SELECT 0
2806 #define ADPA_TRANS_B_SELECT (1<<30)
2807 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2808 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2809 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2810 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2811 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2812 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2813 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2814 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2815 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2816 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2817 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2818 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2819 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2820 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2821 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2822 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2823 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2824 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2825 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2828 #define HDMIB 0xe1140
2829 #define PORT_ENABLE (1 << 31)
2830 #define TRANSCODER_A (0)
2831 #define TRANSCODER_B (1 << 30)
2832 #define COLOR_FORMAT_8bpc (0)
2833 #define COLOR_FORMAT_12bpc (3 << 26)
2834 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
2835 #define SDVO_ENCODING (0)
2836 #define TMDS_ENCODING (2 << 10)
2837 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
2839 #define HDMI_MODE_SELECT (1 << 9)
2840 #define DVI_MODE_SELECT (0)
2841 #define SDVOB_BORDER_ENABLE (1 << 7)
2842 #define AUDIO_ENABLE (1 << 6)
2843 #define VSYNC_ACTIVE_HIGH (1 << 4)
2844 #define HSYNC_ACTIVE_HIGH (1 << 3)
2845 #define PORT_DETECTED (1 << 2)
2847 /* PCH SDVOB multiplex with HDMIB */
2848 #define PCH_SDVOB HDMIB
2850 #define HDMIC 0xe1150
2851 #define HDMID 0xe1160
2853 #define PCH_LVDS 0xe1180
2854 #define LVDS_DETECTED (1 << 1)
2856 #define BLC_PWM_CPU_CTL2 0x48250
2857 #define PWM_ENABLE (1 << 31)
2858 #define PWM_PIPE_A (0 << 29)
2859 #define PWM_PIPE_B (1 << 29)
2860 #define BLC_PWM_CPU_CTL 0x48254
2862 #define BLC_PWM_PCH_CTL1 0xc8250
2863 #define PWM_PCH_ENABLE (1 << 31)
2864 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
2865 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
2866 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
2867 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
2869 #define BLC_PWM_PCH_CTL2 0xc8254
2871 #define PCH_PP_STATUS 0xc7200
2872 #define PCH_PP_CONTROL 0xc7204
2873 #define PANEL_UNLOCK_REGS (0xabcd << 16)
2874 #define EDP_FORCE_VDD (1 << 3)
2875 #define EDP_BLC_ENABLE (1 << 2)
2876 #define PANEL_POWER_RESET (1 << 1)
2877 #define PANEL_POWER_OFF (0 << 0)
2878 #define PANEL_POWER_ON (1 << 0)
2879 #define PCH_PP_ON_DELAYS 0xc7208
2880 #define EDP_PANEL (1 << 30)
2881 #define PCH_PP_OFF_DELAYS 0xc720c
2882 #define PCH_PP_DIVISOR 0xc7210
2884 #define PCH_DP_B 0xe4100
2885 #define PCH_DPB_AUX_CH_CTL 0xe4110
2886 #define PCH_DPB_AUX_CH_DATA1 0xe4114
2887 #define PCH_DPB_AUX_CH_DATA2 0xe4118
2888 #define PCH_DPB_AUX_CH_DATA3 0xe411c
2889 #define PCH_DPB_AUX_CH_DATA4 0xe4120
2890 #define PCH_DPB_AUX_CH_DATA5 0xe4124
2892 #define PCH_DP_C 0xe4200
2893 #define PCH_DPC_AUX_CH_CTL 0xe4210
2894 #define PCH_DPC_AUX_CH_DATA1 0xe4214
2895 #define PCH_DPC_AUX_CH_DATA2 0xe4218
2896 #define PCH_DPC_AUX_CH_DATA3 0xe421c
2897 #define PCH_DPC_AUX_CH_DATA4 0xe4220
2898 #define PCH_DPC_AUX_CH_DATA5 0xe4224
2900 #define PCH_DP_D 0xe4300
2901 #define PCH_DPD_AUX_CH_CTL 0xe4310
2902 #define PCH_DPD_AUX_CH_DATA1 0xe4314
2903 #define PCH_DPD_AUX_CH_DATA2 0xe4318
2904 #define PCH_DPD_AUX_CH_DATA3 0xe431c
2905 #define PCH_DPD_AUX_CH_DATA4 0xe4320
2906 #define PCH_DPD_AUX_CH_DATA5 0xe4324
2909 #define PORT_TRANS_A_SEL_CPT 0
2910 #define PORT_TRANS_B_SEL_CPT (1<<29)
2911 #define PORT_TRANS_C_SEL_CPT (2<<29)
2912 #define PORT_TRANS_SEL_MASK (3<<29)
2914 #define TRANS_DP_CTL_A 0xe0300
2915 #define TRANS_DP_CTL_B 0xe1300
2916 #define TRANS_DP_CTL_C 0xe2300
2917 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
2918 #define TRANS_DP_PORT_SEL_B (0<<29)
2919 #define TRANS_DP_PORT_SEL_C (1<<29)
2920 #define TRANS_DP_PORT_SEL_D (2<<29)
2921 #define TRANS_DP_PORT_SEL_MASK (3<<29)
2922 #define TRANS_DP_AUDIO_ONLY (1<<26)
2923 #define TRANS_DP_ENH_FRAMING (1<<18)
2924 #define TRANS_DP_8BPC (0<<9)
2925 #define TRANS_DP_10BPC (1<<9)
2926 #define TRANS_DP_6BPC (2<<9)
2927 #define TRANS_DP_12BPC (3<<9)
2928 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
2929 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
2930 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
2931 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
2932 #define TRANS_DP_SYNC_MASK (3<<3)
2934 /* SNB eDP training params */
2935 /* SNB A-stepping */
2936 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
2937 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
2938 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
2939 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
2940 /* SNB B-stepping */
2941 #define EDP_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
2942 #define EDP_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
2943 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
2944 #define EDP_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
2945 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
2947 #endif /* _I915_REG_H_ */