1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory.
32 #define INTEL_GMCH_CTRL 0x52
33 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
34 #define INTEL_GMCH_ENABLED 0x4
35 #define INTEL_GMCH_MEM_MASK 0x1
36 #define INTEL_GMCH_MEM_64M 0x1
37 #define INTEL_GMCH_MEM_128M 0
39 #define INTEL_GMCH_GMS_MASK (0xf << 4)
40 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
41 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
42 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
45 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
47 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
48 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
49 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
50 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
51 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
52 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
53 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
54 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
56 #define SNB_GMCH_CTRL 0x50
57 #define SNB_GMCH_GMS_STOLEN_MASK 0xF8
58 #define SNB_GMCH_GMS_STOLEN_32M (1 << 3)
59 #define SNB_GMCH_GMS_STOLEN_64M (2 << 3)
60 #define SNB_GMCH_GMS_STOLEN_96M (3 << 3)
61 #define SNB_GMCH_GMS_STOLEN_128M (4 << 3)
62 #define SNB_GMCH_GMS_STOLEN_160M (5 << 3)
63 #define SNB_GMCH_GMS_STOLEN_192M (6 << 3)
64 #define SNB_GMCH_GMS_STOLEN_224M (7 << 3)
65 #define SNB_GMCH_GMS_STOLEN_256M (8 << 3)
66 #define SNB_GMCH_GMS_STOLEN_288M (9 << 3)
67 #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
68 #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
69 #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
70 #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
71 #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
72 #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
73 #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
75 /* PCI config space */
77 #define HPLLCC 0xc0 /* 855 only */
78 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
79 #define GC_CLOCK_133_200 (0 << 0)
80 #define GC_CLOCK_100_200 (1 << 0)
81 #define GC_CLOCK_100_133 (2 << 0)
82 #define GC_CLOCK_166_250 (3 << 0)
84 #define GCFGC 0xf0 /* 915+ only */
85 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
86 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
87 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
88 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
89 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
90 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
91 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
92 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
93 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
94 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
95 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
96 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
97 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
98 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
99 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
100 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
101 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
102 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
103 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
104 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
105 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
106 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
107 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
110 #define GDRST_FULL (0<<2)
111 #define GDRST_RENDER (1<<2)
112 #define GDRST_MEDIA (3<<2)
116 #define VGA_ST01_MDA 0x3ba
117 #define VGA_ST01_CGA 0x3da
119 #define VGA_MSR_WRITE 0x3c2
120 #define VGA_MSR_READ 0x3cc
121 #define VGA_MSR_MEM_EN (1<<1)
122 #define VGA_MSR_CGA_MODE (1<<0)
124 #define VGA_SR_INDEX 0x3c4
125 #define VGA_SR_DATA 0x3c5
127 #define VGA_AR_INDEX 0x3c0
128 #define VGA_AR_VID_EN (1<<5)
129 #define VGA_AR_DATA_WRITE 0x3c0
130 #define VGA_AR_DATA_READ 0x3c1
132 #define VGA_GR_INDEX 0x3ce
133 #define VGA_GR_DATA 0x3cf
135 #define VGA_GR_MEM_READ_MODE_SHIFT 3
136 #define VGA_GR_MEM_READ_MODE_PLANE 1
138 #define VGA_GR_MEM_MODE_MASK 0xc
139 #define VGA_GR_MEM_MODE_SHIFT 2
140 #define VGA_GR_MEM_A0000_AFFFF 0
141 #define VGA_GR_MEM_A0000_BFFFF 1
142 #define VGA_GR_MEM_B0000_B7FFF 2
143 #define VGA_GR_MEM_B0000_BFFFF 3
145 #define VGA_DACMASK 0x3c6
146 #define VGA_DACRX 0x3c7
147 #define VGA_DACWX 0x3c8
148 #define VGA_DACDATA 0x3c9
150 #define VGA_CR_INDEX_MDA 0x3b4
151 #define VGA_CR_DATA_MDA 0x3b5
152 #define VGA_CR_INDEX_CGA 0x3d4
153 #define VGA_CR_DATA_CGA 0x3d5
156 * Memory interface instructions used by the kernel
158 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
160 #define MI_NOOP MI_INSTR(0, 0)
161 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
162 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
163 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
164 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
165 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
166 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
167 #define MI_FLUSH MI_INSTR(0x04, 0)
168 #define MI_READ_FLUSH (1 << 0)
169 #define MI_EXE_FLUSH (1 << 1)
170 #define MI_NO_WRITE_FLUSH (1 << 2)
171 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
172 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
173 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
174 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
175 #define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
176 #define MI_OVERLAY_CONTINUE (0x0<<21)
177 #define MI_OVERLAY_ON (0x1<<21)
178 #define MI_OVERLAY_OFF (0x2<<21)
179 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
180 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
181 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
182 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
183 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
184 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
185 #define MI_STORE_DWORD_INDEX_SHIFT 2
186 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
187 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
188 #define MI_BATCH_NON_SECURE (1)
189 #define MI_BATCH_NON_SECURE_I965 (1<<8)
190 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
193 * 3D instructions used by the kernel
195 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
197 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
198 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
199 #define SC_UPDATE_SCISSOR (0x1<<1)
200 #define SC_ENABLE_MASK (0x1<<0)
201 #define SC_ENABLE (0x1<<0)
202 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
203 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
204 #define SCI_YMIN_MASK (0xffff<<16)
205 #define SCI_XMIN_MASK (0xffff<<0)
206 #define SCI_YMAX_MASK (0xffff<<16)
207 #define SCI_XMAX_MASK (0xffff<<0)
208 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
209 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
210 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
211 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
212 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
213 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
214 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
215 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
216 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
217 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
218 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
219 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
220 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
221 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
222 #define BLT_DEPTH_8 (0<<24)
223 #define BLT_DEPTH_16_565 (1<<24)
224 #define BLT_DEPTH_16_1555 (2<<24)
225 #define BLT_DEPTH_32 (3<<24)
226 #define BLT_ROP_GXCOPY (0xcc<<16)
227 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
228 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
229 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
230 #define ASYNC_FLIP (1<<22)
231 #define DISPLAY_PLANE_A (0<<20)
232 #define DISPLAY_PLANE_B (1<<20)
233 #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
234 #define PIPE_CONTROL_QW_WRITE (1<<14)
235 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
236 #define PIPE_CONTROL_WC_FLUSH (1<<12)
237 #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
238 #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
239 #define PIPE_CONTROL_ISP_DIS (1<<9)
240 #define PIPE_CONTROL_NOTIFY (1<<8)
241 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
242 #define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
247 #define FENCE_REG_830_0 0x2000
248 #define FENCE_REG_945_8 0x3000
249 #define I830_FENCE_START_MASK 0x07f80000
250 #define I830_FENCE_TILING_Y_SHIFT 12
251 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
252 #define I830_FENCE_PITCH_SHIFT 4
253 #define I830_FENCE_REG_VALID (1<<0)
254 #define I915_FENCE_MAX_PITCH_VAL 4
255 #define I830_FENCE_MAX_PITCH_VAL 6
256 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
258 #define I915_FENCE_START_MASK 0x0ff00000
259 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
261 #define FENCE_REG_965_0 0x03000
262 #define I965_FENCE_PITCH_SHIFT 2
263 #define I965_FENCE_TILING_Y_SHIFT 1
264 #define I965_FENCE_REG_VALID (1<<0)
265 #define I965_FENCE_MAX_PITCH_VAL 0x0400
267 #define FENCE_REG_SANDYBRIDGE_0 0x100000
268 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
271 * Instruction and interrupt control regs
273 #define PGTBL_ER 0x02024
274 #define PRB0_TAIL 0x02030
275 #define PRB0_HEAD 0x02034
276 #define PRB0_START 0x02038
277 #define PRB0_CTL 0x0203c
278 #define TAIL_ADDR 0x001FFFF8
279 #define HEAD_WRAP_COUNT 0xFFE00000
280 #define HEAD_WRAP_ONE 0x00200000
281 #define HEAD_ADDR 0x001FFFFC
282 #define RING_NR_PAGES 0x001FF000
283 #define RING_REPORT_MASK 0x00000006
284 #define RING_REPORT_64K 0x00000002
285 #define RING_REPORT_128K 0x00000004
286 #define RING_NO_REPORT 0x00000000
287 #define RING_VALID_MASK 0x00000001
288 #define RING_VALID 0x00000001
289 #define RING_INVALID 0x00000000
290 #define PRB1_TAIL 0x02040 /* 915+ only */
291 #define PRB1_HEAD 0x02044 /* 915+ only */
292 #define PRB1_START 0x02048 /* 915+ only */
293 #define PRB1_CTL 0x0204c /* 915+ only */
294 #define IPEIR_I965 0x02064
295 #define IPEHR_I965 0x02068
296 #define INSTDONE_I965 0x0206c
297 #define INSTPS 0x02070 /* 965+ only */
298 #define INSTDONE1 0x0207c /* 965+ only */
299 #define ACTHD_I965 0x02074
300 #define HWS_PGA 0x02080
301 #define HWS_PGA_GEN6 0x04080
302 #define HWS_ADDRESS_MASK 0xfffff000
303 #define HWS_START_ADDRESS_SHIFT 4
304 #define PWRCTXA 0x2088 /* 965GM+ only */
305 #define PWRCTX_EN (1<<0)
306 #define IPEIR 0x02088
307 #define IPEHR 0x0208c
308 #define INSTDONE 0x02090
309 #define NOPID 0x02094
310 #define HWSTAM 0x02098
312 #define MI_MODE 0x0209c
313 # define VS_TIMER_DISPATCH (1 << 6)
315 #define SCPD0 0x0209c /* 915+ only */
320 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
321 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
322 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
323 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
324 #define I915_HWB_OOM_INTERRUPT (1<<13)
325 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
326 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
327 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
328 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
329 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
330 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
331 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
332 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
333 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
334 #define I915_DEBUG_INTERRUPT (1<<2)
335 #define I915_USER_INTERRUPT (1<<1)
336 #define I915_ASLE_INTERRUPT (1<<0)
337 #define I915_BSD_USER_INTERRUPT (1<<25)
341 #define GM45_ERROR_PAGE_TABLE (1<<5)
342 #define GM45_ERROR_MEM_PRIV (1<<4)
343 #define I915_ERROR_PAGE_TABLE (1<<4)
344 #define GM45_ERROR_CP_PRIV (1<<3)
345 #define I915_ERROR_MEMORY_REFRESH (1<<1)
346 #define I915_ERROR_INSTRUCTION (1<<0)
347 #define INSTPM 0x020c0
348 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
349 #define ACTHD 0x020c8
350 #define FW_BLC 0x020d8
351 #define FW_BLC2 0x020dc
352 #define FW_BLC_SELF 0x020e0 /* 915+ only */
353 #define FW_BLC_SELF_EN_MASK (1<<31)
354 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
355 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
356 #define MM_BURST_LENGTH 0x00700000
357 #define MM_FIFO_WATERMARK 0x0001F000
358 #define LM_BURST_LENGTH 0x00000700
359 #define LM_FIFO_WATERMARK 0x0000001F
360 #define MI_ARB_STATE 0x020e4 /* 915+ only */
361 #define CACHE_MODE_0 0x02120 /* 915+ only */
362 #define CM0_MASK_SHIFT 16
363 #define CM0_IZ_OPT_DISABLE (1<<6)
364 #define CM0_ZR_OPT_DISABLE (1<<5)
365 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
366 #define CM0_COLOR_EVICT_DISABLE (1<<3)
367 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
368 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
369 #define BB_ADDR 0x02140 /* 8 bytes */
370 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
373 * BSD (bit stream decoder instruction and interrupt control register defines
374 * (G4X and Ironlake only)
377 #define BSD_RING_TAIL 0x04030
378 #define BSD_RING_HEAD 0x04034
379 #define BSD_RING_START 0x04038
380 #define BSD_RING_CTL 0x0403c
381 #define BSD_RING_ACTHD 0x04074
382 #define BSD_HWS_PGA 0x04080
385 * Framebuffer compression (915+ only)
388 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
389 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
390 #define FBC_CONTROL 0x03208
391 #define FBC_CTL_EN (1<<31)
392 #define FBC_CTL_PERIODIC (1<<30)
393 #define FBC_CTL_INTERVAL_SHIFT (16)
394 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
395 #define FBC_CTL_C3_IDLE (1<<13)
396 #define FBC_CTL_STRIDE_SHIFT (5)
397 #define FBC_CTL_FENCENO (1<<0)
398 #define FBC_COMMAND 0x0320c
399 #define FBC_CMD_COMPRESS (1<<0)
400 #define FBC_STATUS 0x03210
401 #define FBC_STAT_COMPRESSING (1<<31)
402 #define FBC_STAT_COMPRESSED (1<<30)
403 #define FBC_STAT_MODIFIED (1<<29)
404 #define FBC_STAT_CURRENT_LINE (1<<0)
405 #define FBC_CONTROL2 0x03214
406 #define FBC_CTL_FENCE_DBL (0<<4)
407 #define FBC_CTL_IDLE_IMM (0<<2)
408 #define FBC_CTL_IDLE_FULL (1<<2)
409 #define FBC_CTL_IDLE_LINE (2<<2)
410 #define FBC_CTL_IDLE_DEBUG (3<<2)
411 #define FBC_CTL_CPU_FENCE (1<<1)
412 #define FBC_CTL_PLANEA (0<<0)
413 #define FBC_CTL_PLANEB (1<<0)
414 #define FBC_FENCE_OFF 0x0321b
415 #define FBC_TAG 0x03300
417 #define FBC_LL_SIZE (1536)
419 /* Framebuffer compression for GM45+ */
420 #define DPFC_CB_BASE 0x3200
421 #define DPFC_CONTROL 0x3208
422 #define DPFC_CTL_EN (1<<31)
423 #define DPFC_CTL_PLANEA (0<<30)
424 #define DPFC_CTL_PLANEB (1<<30)
425 #define DPFC_CTL_FENCE_EN (1<<29)
426 #define DPFC_SR_EN (1<<10)
427 #define DPFC_CTL_LIMIT_1X (0<<6)
428 #define DPFC_CTL_LIMIT_2X (1<<6)
429 #define DPFC_CTL_LIMIT_4X (2<<6)
430 #define DPFC_RECOMP_CTL 0x320c
431 #define DPFC_RECOMP_STALL_EN (1<<27)
432 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
433 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
434 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
435 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
436 #define DPFC_STATUS 0x3210
437 #define DPFC_INVAL_SEG_SHIFT (16)
438 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
439 #define DPFC_COMP_SEG_SHIFT (0)
440 #define DPFC_COMP_SEG_MASK (0x000003ff)
441 #define DPFC_STATUS2 0x3214
442 #define DPFC_FENCE_YOFF 0x3218
443 #define DPFC_CHICKEN 0x3224
444 #define DPFC_HT_MODIFY (1<<31)
457 # define GPIO_CLOCK_DIR_MASK (1 << 0)
458 # define GPIO_CLOCK_DIR_IN (0 << 1)
459 # define GPIO_CLOCK_DIR_OUT (1 << 1)
460 # define GPIO_CLOCK_VAL_MASK (1 << 2)
461 # define GPIO_CLOCK_VAL_OUT (1 << 3)
462 # define GPIO_CLOCK_VAL_IN (1 << 4)
463 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
464 # define GPIO_DATA_DIR_MASK (1 << 8)
465 # define GPIO_DATA_DIR_IN (0 << 9)
466 # define GPIO_DATA_DIR_OUT (1 << 9)
467 # define GPIO_DATA_VAL_MASK (1 << 10)
468 # define GPIO_DATA_VAL_OUT (1 << 11)
469 # define GPIO_DATA_VAL_IN (1 << 12)
470 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
472 #define GMBUS0 0x5100
473 #define GMBUS1 0x5104
474 #define GMBUS2 0x5108
475 #define GMBUS3 0x510c
476 #define GMBUS4 0x5110
477 #define GMBUS5 0x5120
480 * Clock control & power management
485 #define VGA_PD 0x6010
486 #define VGA0_PD_P2_DIV_4 (1 << 7)
487 #define VGA0_PD_P1_DIV_2 (1 << 5)
488 #define VGA0_PD_P1_SHIFT 0
489 #define VGA0_PD_P1_MASK (0x1f << 0)
490 #define VGA1_PD_P2_DIV_4 (1 << 15)
491 #define VGA1_PD_P1_DIV_2 (1 << 13)
492 #define VGA1_PD_P1_SHIFT 8
493 #define VGA1_PD_P1_MASK (0x1f << 8)
494 #define DPLL_A 0x06014
495 #define DPLL_B 0x06018
496 #define DPLL_VCO_ENABLE (1 << 31)
497 #define DPLL_DVO_HIGH_SPEED (1 << 30)
498 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
499 #define DPLL_VGA_MODE_DIS (1 << 28)
500 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
501 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
502 #define DPLL_MODE_MASK (3 << 26)
503 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
504 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
505 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
506 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
507 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
508 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
509 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
511 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
512 #define I915_CRC_ERROR_ENABLE (1UL<<29)
513 #define I915_CRC_DONE_ENABLE (1UL<<28)
514 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
515 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
516 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
517 #define I915_DPST_EVENT_ENABLE (1UL<<23)
518 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
519 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
520 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
521 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
522 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
523 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
524 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
525 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
526 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
527 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
528 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
529 #define I915_DPST_EVENT_STATUS (1UL<<7)
530 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
531 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
532 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
533 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
534 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
535 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
537 #define SRX_INDEX 0x3c4
538 #define SRX_DATA 0x3c5
540 #define SR01_SCREEN_OFF (1<<5)
543 #define PPCR_ON (1<<0)
546 #define DVOB_ON (1<<31)
548 #define DVOC_ON (1<<31)
550 #define LVDS_ON (1<<31)
553 #define ADPA_DPMS_MASK (~(3<<10))
554 #define ADPA_DPMS_ON (0<<10)
555 #define ADPA_DPMS_SUSPEND (1<<10)
556 #define ADPA_DPMS_STANDBY (2<<10)
557 #define ADPA_DPMS_OFF (3<<10)
559 #define RING_TAIL 0x00
560 #define TAIL_ADDR 0x001FFFF8
561 #define RING_HEAD 0x04
562 #define HEAD_WRAP_COUNT 0xFFE00000
563 #define HEAD_WRAP_ONE 0x00200000
564 #define HEAD_ADDR 0x001FFFFC
565 #define RING_START 0x08
566 #define START_ADDR 0xFFFFF000
567 #define RING_LEN 0x0C
568 #define RING_NR_PAGES 0x001FF000
569 #define RING_REPORT_MASK 0x00000006
570 #define RING_REPORT_64K 0x00000002
571 #define RING_REPORT_128K 0x00000004
572 #define RING_NO_REPORT 0x00000000
573 #define RING_VALID_MASK 0x00000001
574 #define RING_VALID 0x00000001
575 #define RING_INVALID 0x00000000
577 /* Scratch pad debug 0 reg:
579 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
581 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
582 * this field (only one bit may be set).
584 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
585 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
586 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
587 /* i830, required in DVO non-gang */
588 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
589 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
590 #define PLL_REF_INPUT_DREFCLK (0 << 13)
591 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
592 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
593 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
594 #define PLL_REF_INPUT_MASK (3 << 13)
595 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
597 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
598 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
599 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
600 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
601 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
604 * Parallel to Serial Load Pulse phase selection.
605 * Selects the phase for the 10X DPLL clock for the PCIe
606 * digital display port. The range is 4 to 13; 10 or more
607 * is just a flip delay. The default is 6
609 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
610 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
612 * SDVO multiplier for 945G/GM. Not used on 965.
614 #define SDVO_MULTIPLIER_MASK 0x000000ff
615 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
616 #define SDVO_MULTIPLIER_SHIFT_VGA 0
617 #define DPLL_A_MD 0x0601c /* 965+ only */
619 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
621 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
623 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
624 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
625 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
626 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
627 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
629 * SDVO/UDI pixel multiplier.
631 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
632 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
633 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
634 * dummy bytes in the datastream at an increased clock rate, with both sides of
635 * the link knowing how many bytes are fill.
637 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
638 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
639 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
640 * through an SDVO command.
642 * This register field has values of multiplication factor minus 1, with
643 * a maximum multiplier of 5 for SDVO.
645 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
646 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
648 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
649 * This best be set to the default value (3) or the CRT won't work. No,
650 * I don't entirely understand what this does...
652 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
653 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
654 #define DPLL_B_MD 0x06020 /* 965+ only */
659 #define FP_N_DIV_MASK 0x003f0000
660 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
661 #define FP_N_DIV_SHIFT 16
662 #define FP_M1_DIV_MASK 0x00003f00
663 #define FP_M1_DIV_SHIFT 8
664 #define FP_M2_DIV_MASK 0x0000003f
665 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
666 #define FP_M2_DIV_SHIFT 0
667 #define DPLL_TEST 0x606c
668 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
669 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
670 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
671 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
672 #define DPLLB_TEST_N_BYPASS (1 << 19)
673 #define DPLLB_TEST_M_BYPASS (1 << 18)
674 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
675 #define DPLLA_TEST_N_BYPASS (1 << 3)
676 #define DPLLA_TEST_M_BYPASS (1 << 2)
677 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
678 #define D_STATE 0x6104
679 #define DSTATE_PLL_D3_OFF (1<<3)
680 #define DSTATE_GFX_CLOCK_GATING (1<<1)
681 #define DSTATE_DOT_CLOCK_GATING (1<<0)
682 #define DSPCLK_GATE_D 0x6200
683 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
684 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
685 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
686 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
687 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
688 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
689 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
690 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
691 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
692 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
693 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
694 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
695 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
696 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
697 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
698 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
699 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
700 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
701 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
702 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
703 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
704 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
705 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
706 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
707 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
708 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
709 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
710 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
712 * This bit must be set on the 830 to prevent hangs when turning off the
715 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
716 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
717 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
718 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
719 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
721 #define RENCLK_GATE_D1 0x6204
722 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
723 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
724 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
725 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
726 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
727 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
728 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
729 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
730 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
731 /** This bit must be unset on 855,865 */
732 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
733 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
734 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
735 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
736 /** This bit must be set on 855,865. */
737 # define SV_CLOCK_GATE_DISABLE (1 << 0)
738 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
739 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
740 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
741 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
742 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
743 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
744 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
745 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
746 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
747 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
748 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
749 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
750 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
751 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
752 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
753 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
754 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
756 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
757 /** This bit must always be set on 965G/965GM */
758 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
759 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
760 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
761 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
762 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
763 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
764 /** This bit must always be set on 965G */
765 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
766 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
767 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
768 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
769 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
770 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
771 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
772 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
773 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
774 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
775 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
776 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
777 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
778 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
779 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
780 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
781 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
782 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
783 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
785 #define RENCLK_GATE_D2 0x6208
786 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
787 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
788 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
789 #define RAMCLK_GATE_D 0x6210 /* CRL only */
790 #define DEUC 0x6214 /* CRL only */
796 #define PALETTE_A 0x0a000
797 #define PALETTE_B 0x0a800
804 * This mirrors the MCHBAR MMIO space whose location is determined by
805 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
806 * every way. It is not accessible from the CP register read instructions.
809 #define MCHBAR_MIRROR_BASE 0x10000
811 /** 915-945 and GM965 MCH register controlling DRAM channel access */
813 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
814 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
815 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
816 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
817 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
818 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
820 /** 965 MCH register controlling DRAM channel configuration */
821 #define C0DRB3 0x10206
822 #define C1DRB3 0x10606
824 /* Clocking configuration register */
825 #define CLKCFG 0x10c00
826 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
827 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
828 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
829 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
830 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
831 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
832 /* Note, below two are guess */
833 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
834 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
835 #define CLKCFG_FSB_MASK (7 << 0)
836 #define CLKCFG_MEM_533 (1 << 4)
837 #define CLKCFG_MEM_667 (2 << 4)
838 #define CLKCFG_MEM_800 (3 << 4)
839 #define CLKCFG_MEM_MASK (7 << 4)
841 #define CRSTANDVID 0x11100
842 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
843 #define PXVFREQ_PX_MASK 0x7f000000
844 #define PXVFREQ_PX_SHIFT 24
845 #define VIDFREQ_BASE 0x11110
846 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
847 #define VIDFREQ2 0x11114
848 #define VIDFREQ3 0x11118
849 #define VIDFREQ4 0x1111c
850 #define VIDFREQ_P0_MASK 0x1f000000
851 #define VIDFREQ_P0_SHIFT 24
852 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
853 #define VIDFREQ_P0_CSCLK_SHIFT 20
854 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
855 #define VIDFREQ_P0_CRCLK_SHIFT 16
856 #define VIDFREQ_P1_MASK 0x00001f00
857 #define VIDFREQ_P1_SHIFT 8
858 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
859 #define VIDFREQ_P1_CSCLK_SHIFT 4
860 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
861 #define INTTOEXT_BASE_ILK 0x11300
862 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
863 #define INTTOEXT_MAP3_SHIFT 24
864 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
865 #define INTTOEXT_MAP2_SHIFT 16
866 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
867 #define INTTOEXT_MAP1_SHIFT 8
868 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
869 #define INTTOEXT_MAP0_SHIFT 0
870 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
871 #define MEMSWCTL 0x11170 /* Ironlake only */
872 #define MEMCTL_CMD_MASK 0xe000
873 #define MEMCTL_CMD_SHIFT 13
874 #define MEMCTL_CMD_RCLK_OFF 0
875 #define MEMCTL_CMD_RCLK_ON 1
876 #define MEMCTL_CMD_CHFREQ 2
877 #define MEMCTL_CMD_CHVID 3
878 #define MEMCTL_CMD_VMMOFF 4
879 #define MEMCTL_CMD_VMMON 5
880 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
881 when command complete */
882 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
883 #define MEMCTL_FREQ_SHIFT 8
884 #define MEMCTL_SFCAVM (1<<7)
885 #define MEMCTL_TGT_VID_MASK 0x007f
886 #define MEMIHYST 0x1117c
887 #define MEMINTREN 0x11180 /* 16 bits */
888 #define MEMINT_RSEXIT_EN (1<<8)
889 #define MEMINT_CX_SUPR_EN (1<<7)
890 #define MEMINT_CONT_BUSY_EN (1<<6)
891 #define MEMINT_AVG_BUSY_EN (1<<5)
892 #define MEMINT_EVAL_CHG_EN (1<<4)
893 #define MEMINT_MON_IDLE_EN (1<<3)
894 #define MEMINT_UP_EVAL_EN (1<<2)
895 #define MEMINT_DOWN_EVAL_EN (1<<1)
896 #define MEMINT_SW_CMD_EN (1<<0)
897 #define MEMINTRSTR 0x11182 /* 16 bits */
898 #define MEM_RSEXIT_MASK 0xc000
899 #define MEM_RSEXIT_SHIFT 14
900 #define MEM_CONT_BUSY_MASK 0x3000
901 #define MEM_CONT_BUSY_SHIFT 12
902 #define MEM_AVG_BUSY_MASK 0x0c00
903 #define MEM_AVG_BUSY_SHIFT 10
904 #define MEM_EVAL_CHG_MASK 0x0300
905 #define MEM_EVAL_BUSY_SHIFT 8
906 #define MEM_MON_IDLE_MASK 0x00c0
907 #define MEM_MON_IDLE_SHIFT 6
908 #define MEM_UP_EVAL_MASK 0x0030
909 #define MEM_UP_EVAL_SHIFT 4
910 #define MEM_DOWN_EVAL_MASK 0x000c
911 #define MEM_DOWN_EVAL_SHIFT 2
912 #define MEM_SW_CMD_MASK 0x0003
913 #define MEM_INT_STEER_GFX 0
914 #define MEM_INT_STEER_CMR 1
915 #define MEM_INT_STEER_SMI 2
916 #define MEM_INT_STEER_SCI 3
917 #define MEMINTRSTS 0x11184
918 #define MEMINT_RSEXIT (1<<7)
919 #define MEMINT_CONT_BUSY (1<<6)
920 #define MEMINT_AVG_BUSY (1<<5)
921 #define MEMINT_EVAL_CHG (1<<4)
922 #define MEMINT_MON_IDLE (1<<3)
923 #define MEMINT_UP_EVAL (1<<2)
924 #define MEMINT_DOWN_EVAL (1<<1)
925 #define MEMINT_SW_CMD (1<<0)
926 #define MEMMODECTL 0x11190
927 #define MEMMODE_BOOST_EN (1<<31)
928 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
929 #define MEMMODE_BOOST_FREQ_SHIFT 24
930 #define MEMMODE_IDLE_MODE_MASK 0x00030000
931 #define MEMMODE_IDLE_MODE_SHIFT 16
932 #define MEMMODE_IDLE_MODE_EVAL 0
933 #define MEMMODE_IDLE_MODE_CONT 1
934 #define MEMMODE_HWIDLE_EN (1<<15)
935 #define MEMMODE_SWMODE_EN (1<<14)
936 #define MEMMODE_RCLK_GATE (1<<13)
937 #define MEMMODE_HW_UPDATE (1<<12)
938 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
939 #define MEMMODE_FSTART_SHIFT 8
940 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
941 #define MEMMODE_FMAX_SHIFT 4
942 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
943 #define RCBMAXAVG 0x1119c
944 #define MEMSWCTL2 0x1119e /* Cantiga only */
945 #define SWMEMCMD_RENDER_OFF (0 << 13)
946 #define SWMEMCMD_RENDER_ON (1 << 13)
947 #define SWMEMCMD_SWFREQ (2 << 13)
948 #define SWMEMCMD_TARVID (3 << 13)
949 #define SWMEMCMD_VRM_OFF (4 << 13)
950 #define SWMEMCMD_VRM_ON (5 << 13)
951 #define CMDSTS (1<<12)
952 #define SFCAVM (1<<11)
953 #define SWFREQ_MASK 0x0380 /* P0-7 */
954 #define SWFREQ_SHIFT 7
955 #define TARVID_MASK 0x001f
956 #define MEMSTAT_CTG 0x111a0
957 #define RCBMINAVG 0x111a0
958 #define RCUPEI 0x111b0
959 #define RCDNEI 0x111b4
960 #define MCHBAR_RENDER_STANDBY 0x111b8
961 #define RCX_SW_EXIT (1<<23)
962 #define RSX_STATUS_MASK 0x00700000
963 #define VIDCTL 0x111c0
964 #define VIDSTS 0x111c8
965 #define VIDSTART 0x111cc /* 8 bits */
966 #define MEMSTAT_ILK 0x111f8
967 #define MEMSTAT_VID_MASK 0x7f00
968 #define MEMSTAT_VID_SHIFT 8
969 #define MEMSTAT_PSTATE_MASK 0x00f8
970 #define MEMSTAT_PSTATE_SHIFT 3
971 #define MEMSTAT_MON_ACTV (1<<2)
972 #define MEMSTAT_SRC_CTL_MASK 0x0003
973 #define MEMSTAT_SRC_CTL_CORE 0
974 #define MEMSTAT_SRC_CTL_TRB 1
975 #define MEMSTAT_SRC_CTL_THM 2
976 #define MEMSTAT_SRC_CTL_STDBY 3
977 #define RCPREVBSYTUPAVG 0x113b8
978 #define RCPREVBSYTDNAVG 0x113bc
979 #define PEG_BAND_GAP_DATA 0x14d68
985 #define OVADD 0x30000
986 #define DOVSTA 0x30008
987 #define OC_BUF (0x3<<20)
988 #define OGAMC5 0x30010
989 #define OGAMC4 0x30014
990 #define OGAMC3 0x30018
991 #define OGAMC2 0x3001c
992 #define OGAMC1 0x30020
993 #define OGAMC0 0x30024
996 * Display engine regs
999 /* Pipe A timing regs */
1000 #define HTOTAL_A 0x60000
1001 #define HBLANK_A 0x60004
1002 #define HSYNC_A 0x60008
1003 #define VTOTAL_A 0x6000c
1004 #define VBLANK_A 0x60010
1005 #define VSYNC_A 0x60014
1006 #define PIPEASRC 0x6001c
1007 #define BCLRPAT_A 0x60020
1009 /* Pipe B timing regs */
1010 #define HTOTAL_B 0x61000
1011 #define HBLANK_B 0x61004
1012 #define HSYNC_B 0x61008
1013 #define VTOTAL_B 0x6100c
1014 #define VBLANK_B 0x61010
1015 #define VSYNC_B 0x61014
1016 #define PIPEBSRC 0x6101c
1017 #define BCLRPAT_B 0x61020
1019 /* VGA port control */
1020 #define ADPA 0x61100
1021 #define ADPA_DAC_ENABLE (1<<31)
1022 #define ADPA_DAC_DISABLE 0
1023 #define ADPA_PIPE_SELECT_MASK (1<<30)
1024 #define ADPA_PIPE_A_SELECT 0
1025 #define ADPA_PIPE_B_SELECT (1<<30)
1026 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1027 #define ADPA_SETS_HVPOLARITY 0
1028 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1029 #define ADPA_VSYNC_CNTL_ENABLE 0
1030 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1031 #define ADPA_HSYNC_CNTL_ENABLE 0
1032 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1033 #define ADPA_VSYNC_ACTIVE_LOW 0
1034 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1035 #define ADPA_HSYNC_ACTIVE_LOW 0
1036 #define ADPA_DPMS_MASK (~(3<<10))
1037 #define ADPA_DPMS_ON (0<<10)
1038 #define ADPA_DPMS_SUSPEND (1<<10)
1039 #define ADPA_DPMS_STANDBY (2<<10)
1040 #define ADPA_DPMS_OFF (3<<10)
1042 /* Hotplug control (945+ only) */
1043 #define PORT_HOTPLUG_EN 0x61110
1044 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
1045 #define DPB_HOTPLUG_INT_EN (1 << 29)
1046 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
1047 #define DPC_HOTPLUG_INT_EN (1 << 28)
1048 #define HDMID_HOTPLUG_INT_EN (1 << 27)
1049 #define DPD_HOTPLUG_INT_EN (1 << 27)
1050 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1051 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1052 #define TV_HOTPLUG_INT_EN (1 << 18)
1053 #define CRT_HOTPLUG_INT_EN (1 << 9)
1054 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1055 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1056 /* must use period 64 on GM45 according to docs */
1057 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1058 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1059 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1060 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1061 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1062 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1063 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1064 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1065 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1066 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1067 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1068 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1069 #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
1071 #define PORT_HOTPLUG_STAT 0x61114
1072 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1073 #define DPB_HOTPLUG_INT_STATUS (1 << 29)
1074 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1075 #define DPC_HOTPLUG_INT_STATUS (1 << 28)
1076 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1077 #define DPD_HOTPLUG_INT_STATUS (1 << 27)
1078 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1079 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1080 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1081 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1082 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1083 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1084 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1085 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1087 /* SDVO port control */
1088 #define SDVOB 0x61140
1089 #define SDVOC 0x61160
1090 #define SDVO_ENABLE (1 << 31)
1091 #define SDVO_PIPE_B_SELECT (1 << 30)
1092 #define SDVO_STALL_SELECT (1 << 29)
1093 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1095 * 915G/GM SDVO pixel multiplier.
1097 * Programmed value is multiplier - 1, up to 5x.
1099 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1101 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1102 #define SDVO_PORT_MULTIPLY_SHIFT 23
1103 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1104 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1105 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1106 #define SDVOC_GANG_MODE (1 << 16)
1107 #define SDVO_ENCODING_SDVO (0x0 << 10)
1108 #define SDVO_ENCODING_HDMI (0x2 << 10)
1109 /** Requird for HDMI operation */
1110 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1111 #define SDVO_BORDER_ENABLE (1 << 7)
1112 #define SDVO_AUDIO_ENABLE (1 << 6)
1113 /** New with 965, default is to be set */
1114 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1115 /** New with 965, default is to be set */
1116 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1117 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1118 #define SDVO_DETECTED (1 << 2)
1119 /* Bits to be preserved when writing */
1120 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1121 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1123 /* DVO port control */
1124 #define DVOA 0x61120
1125 #define DVOB 0x61140
1126 #define DVOC 0x61160
1127 #define DVO_ENABLE (1 << 31)
1128 #define DVO_PIPE_B_SELECT (1 << 30)
1129 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1130 #define DVO_PIPE_STALL (1 << 28)
1131 #define DVO_PIPE_STALL_TV (2 << 28)
1132 #define DVO_PIPE_STALL_MASK (3 << 28)
1133 #define DVO_USE_VGA_SYNC (1 << 15)
1134 #define DVO_DATA_ORDER_I740 (0 << 14)
1135 #define DVO_DATA_ORDER_FP (1 << 14)
1136 #define DVO_VSYNC_DISABLE (1 << 11)
1137 #define DVO_HSYNC_DISABLE (1 << 10)
1138 #define DVO_VSYNC_TRISTATE (1 << 9)
1139 #define DVO_HSYNC_TRISTATE (1 << 8)
1140 #define DVO_BORDER_ENABLE (1 << 7)
1141 #define DVO_DATA_ORDER_GBRG (1 << 6)
1142 #define DVO_DATA_ORDER_RGGB (0 << 6)
1143 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1144 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1145 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1146 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1147 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1148 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1149 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1150 #define DVO_PRESERVE_MASK (0x7<<24)
1151 #define DVOA_SRCDIM 0x61124
1152 #define DVOB_SRCDIM 0x61144
1153 #define DVOC_SRCDIM 0x61164
1154 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1155 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1157 /* LVDS port control */
1158 #define LVDS 0x61180
1160 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1161 * the DPLL semantics change when the LVDS is assigned to that pipe.
1163 #define LVDS_PORT_EN (1 << 31)
1164 /* Selects pipe B for LVDS data. Must be set on pre-965. */
1165 #define LVDS_PIPEB_SELECT (1 << 30)
1166 /* LVDS dithering flag on 965/g4x platform */
1167 #define LVDS_ENABLE_DITHER (1 << 25)
1168 /* Enable border for unscaled (or aspect-scaled) display */
1169 #define LVDS_BORDER_ENABLE (1 << 15)
1171 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1174 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1175 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1176 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1178 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1179 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1182 #define LVDS_A3_POWER_MASK (3 << 6)
1183 #define LVDS_A3_POWER_DOWN (0 << 6)
1184 #define LVDS_A3_POWER_UP (3 << 6)
1186 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1189 #define LVDS_CLKB_POWER_MASK (3 << 4)
1190 #define LVDS_CLKB_POWER_DOWN (0 << 4)
1191 #define LVDS_CLKB_POWER_UP (3 << 4)
1193 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1194 * setting for whether we are in dual-channel mode. The B3 pair will
1195 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1197 #define LVDS_B0B3_POWER_MASK (3 << 2)
1198 #define LVDS_B0B3_POWER_DOWN (0 << 2)
1199 #define LVDS_B0B3_POWER_UP (3 << 2)
1201 /* Panel power sequencing */
1202 #define PP_STATUS 0x61200
1203 #define PP_ON (1 << 31)
1205 * Indicates that all dependencies of the panel are on:
1209 * - LVDS/DVOB/DVOC on
1211 #define PP_READY (1 << 30)
1212 #define PP_SEQUENCE_NONE (0 << 28)
1213 #define PP_SEQUENCE_ON (1 << 28)
1214 #define PP_SEQUENCE_OFF (2 << 28)
1215 #define PP_SEQUENCE_MASK 0x30000000
1216 #define PP_CONTROL 0x61204
1217 #define POWER_TARGET_ON (1 << 0)
1218 #define PP_ON_DELAYS 0x61208
1219 #define PP_OFF_DELAYS 0x6120c
1220 #define PP_DIVISOR 0x61210
1223 #define PFIT_CONTROL 0x61230
1224 #define PFIT_ENABLE (1 << 31)
1225 #define PFIT_PIPE_MASK (3 << 29)
1226 #define PFIT_PIPE_SHIFT 29
1227 #define VERT_INTERP_DISABLE (0 << 10)
1228 #define VERT_INTERP_BILINEAR (1 << 10)
1229 #define VERT_INTERP_MASK (3 << 10)
1230 #define VERT_AUTO_SCALE (1 << 9)
1231 #define HORIZ_INTERP_DISABLE (0 << 6)
1232 #define HORIZ_INTERP_BILINEAR (1 << 6)
1233 #define HORIZ_INTERP_MASK (3 << 6)
1234 #define HORIZ_AUTO_SCALE (1 << 5)
1235 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1236 #define PFIT_FILTER_FUZZY (0 << 24)
1237 #define PFIT_SCALING_AUTO (0 << 26)
1238 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1239 #define PFIT_SCALING_PILLAR (2 << 26)
1240 #define PFIT_SCALING_LETTER (3 << 26)
1241 #define PFIT_PGM_RATIOS 0x61234
1242 #define PFIT_VERT_SCALE_MASK 0xfff00000
1243 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1245 #define PFIT_VERT_SCALE_SHIFT 20
1246 #define PFIT_VERT_SCALE_MASK 0xfff00000
1247 #define PFIT_HORIZ_SCALE_SHIFT 4
1248 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1250 #define PFIT_VERT_SCALE_SHIFT_965 16
1251 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1252 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1253 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1255 #define PFIT_AUTO_RATIOS 0x61238
1257 /* Backlight control */
1258 #define BLC_PWM_CTL 0x61254
1259 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1260 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1261 #define BLM_COMBINATION_MODE (1 << 30)
1263 * This is the most significant 15 bits of the number of backlight cycles in a
1264 * complete cycle of the modulated backlight control.
1266 * The actual value is this field multiplied by two.
1268 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1269 #define BLM_LEGACY_MODE (1 << 16)
1271 * This is the number of cycles out of the backlight modulation cycle for which
1272 * the backlight is on.
1274 * This field must be no greater than the number of cycles in the complete
1275 * backlight modulation cycle.
1277 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1278 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1280 #define BLC_HIST_CTL 0x61260
1282 /* TV port control */
1283 #define TV_CTL 0x68000
1284 /** Enables the TV encoder */
1285 # define TV_ENC_ENABLE (1 << 31)
1286 /** Sources the TV encoder input from pipe B instead of A. */
1287 # define TV_ENC_PIPEB_SELECT (1 << 30)
1288 /** Outputs composite video (DAC A only) */
1289 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1290 /** Outputs SVideo video (DAC B/C) */
1291 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1292 /** Outputs Component video (DAC A/B/C) */
1293 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1294 /** Outputs Composite and SVideo (DAC A/B/C) */
1295 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1296 # define TV_TRILEVEL_SYNC (1 << 21)
1297 /** Enables slow sync generation (945GM only) */
1298 # define TV_SLOW_SYNC (1 << 20)
1299 /** Selects 4x oversampling for 480i and 576p */
1300 # define TV_OVERSAMPLE_4X (0 << 18)
1301 /** Selects 2x oversampling for 720p and 1080i */
1302 # define TV_OVERSAMPLE_2X (1 << 18)
1303 /** Selects no oversampling for 1080p */
1304 # define TV_OVERSAMPLE_NONE (2 << 18)
1305 /** Selects 8x oversampling */
1306 # define TV_OVERSAMPLE_8X (3 << 18)
1307 /** Selects progressive mode rather than interlaced */
1308 # define TV_PROGRESSIVE (1 << 17)
1309 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1310 # define TV_PAL_BURST (1 << 16)
1311 /** Field for setting delay of Y compared to C */
1312 # define TV_YC_SKEW_MASK (7 << 12)
1313 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1314 # define TV_ENC_SDP_FIX (1 << 11)
1316 * Enables a fix for the 915GM only.
1318 * Not sure what it does.
1320 # define TV_ENC_C0_FIX (1 << 10)
1321 /** Bits that must be preserved by software */
1322 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1323 # define TV_FUSE_STATE_MASK (3 << 4)
1324 /** Read-only state that reports all features enabled */
1325 # define TV_FUSE_STATE_ENABLED (0 << 4)
1326 /** Read-only state that reports that Macrovision is disabled in hardware*/
1327 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1328 /** Read-only state that reports that TV-out is disabled in hardware. */
1329 # define TV_FUSE_STATE_DISABLED (2 << 4)
1330 /** Normal operation */
1331 # define TV_TEST_MODE_NORMAL (0 << 0)
1332 /** Encoder test pattern 1 - combo pattern */
1333 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
1334 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1335 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
1336 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1337 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
1338 /** Encoder test pattern 4 - random noise */
1339 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
1340 /** Encoder test pattern 5 - linear color ramps */
1341 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
1343 * This test mode forces the DACs to 50% of full output.
1345 * This is used for load detection in combination with TVDAC_SENSE_MASK
1347 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1348 # define TV_TEST_MODE_MASK (7 << 0)
1350 #define TV_DAC 0x68004
1352 * Reports that DAC state change logic has reported change (RO).
1354 * This gets cleared when TV_DAC_STATE_EN is cleared
1356 # define TVDAC_STATE_CHG (1 << 31)
1357 # define TVDAC_SENSE_MASK (7 << 28)
1358 /** Reports that DAC A voltage is above the detect threshold */
1359 # define TVDAC_A_SENSE (1 << 30)
1360 /** Reports that DAC B voltage is above the detect threshold */
1361 # define TVDAC_B_SENSE (1 << 29)
1362 /** Reports that DAC C voltage is above the detect threshold */
1363 # define TVDAC_C_SENSE (1 << 28)
1365 * Enables DAC state detection logic, for load-based TV detection.
1367 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1368 * to off, for load detection to work.
1370 # define TVDAC_STATE_CHG_EN (1 << 27)
1371 /** Sets the DAC A sense value to high */
1372 # define TVDAC_A_SENSE_CTL (1 << 26)
1373 /** Sets the DAC B sense value to high */
1374 # define TVDAC_B_SENSE_CTL (1 << 25)
1375 /** Sets the DAC C sense value to high */
1376 # define TVDAC_C_SENSE_CTL (1 << 24)
1377 /** Overrides the ENC_ENABLE and DAC voltage levels */
1378 # define DAC_CTL_OVERRIDE (1 << 7)
1379 /** Sets the slew rate. Must be preserved in software */
1380 # define ENC_TVDAC_SLEW_FAST (1 << 6)
1381 # define DAC_A_1_3_V (0 << 4)
1382 # define DAC_A_1_1_V (1 << 4)
1383 # define DAC_A_0_7_V (2 << 4)
1384 # define DAC_A_MASK (3 << 4)
1385 # define DAC_B_1_3_V (0 << 2)
1386 # define DAC_B_1_1_V (1 << 2)
1387 # define DAC_B_0_7_V (2 << 2)
1388 # define DAC_B_MASK (3 << 2)
1389 # define DAC_C_1_3_V (0 << 0)
1390 # define DAC_C_1_1_V (1 << 0)
1391 # define DAC_C_0_7_V (2 << 0)
1392 # define DAC_C_MASK (3 << 0)
1395 * CSC coefficients are stored in a floating point format with 9 bits of
1396 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1397 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1398 * -1 (0x3) being the only legal negative value.
1400 #define TV_CSC_Y 0x68010
1401 # define TV_RY_MASK 0x07ff0000
1402 # define TV_RY_SHIFT 16
1403 # define TV_GY_MASK 0x00000fff
1404 # define TV_GY_SHIFT 0
1406 #define TV_CSC_Y2 0x68014
1407 # define TV_BY_MASK 0x07ff0000
1408 # define TV_BY_SHIFT 16
1410 * Y attenuation for component video.
1412 * Stored in 1.9 fixed point.
1414 # define TV_AY_MASK 0x000003ff
1415 # define TV_AY_SHIFT 0
1417 #define TV_CSC_U 0x68018
1418 # define TV_RU_MASK 0x07ff0000
1419 # define TV_RU_SHIFT 16
1420 # define TV_GU_MASK 0x000007ff
1421 # define TV_GU_SHIFT 0
1423 #define TV_CSC_U2 0x6801c
1424 # define TV_BU_MASK 0x07ff0000
1425 # define TV_BU_SHIFT 16
1427 * U attenuation for component video.
1429 * Stored in 1.9 fixed point.
1431 # define TV_AU_MASK 0x000003ff
1432 # define TV_AU_SHIFT 0
1434 #define TV_CSC_V 0x68020
1435 # define TV_RV_MASK 0x0fff0000
1436 # define TV_RV_SHIFT 16
1437 # define TV_GV_MASK 0x000007ff
1438 # define TV_GV_SHIFT 0
1440 #define TV_CSC_V2 0x68024
1441 # define TV_BV_MASK 0x07ff0000
1442 # define TV_BV_SHIFT 16
1444 * V attenuation for component video.
1446 * Stored in 1.9 fixed point.
1448 # define TV_AV_MASK 0x000007ff
1449 # define TV_AV_SHIFT 0
1451 #define TV_CLR_KNOBS 0x68028
1452 /** 2s-complement brightness adjustment */
1453 # define TV_BRIGHTNESS_MASK 0xff000000
1454 # define TV_BRIGHTNESS_SHIFT 24
1455 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1456 # define TV_CONTRAST_MASK 0x00ff0000
1457 # define TV_CONTRAST_SHIFT 16
1458 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1459 # define TV_SATURATION_MASK 0x0000ff00
1460 # define TV_SATURATION_SHIFT 8
1461 /** Hue adjustment, as an integer phase angle in degrees */
1462 # define TV_HUE_MASK 0x000000ff
1463 # define TV_HUE_SHIFT 0
1465 #define TV_CLR_LEVEL 0x6802c
1466 /** Controls the DAC level for black */
1467 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1468 # define TV_BLACK_LEVEL_SHIFT 16
1469 /** Controls the DAC level for blanking */
1470 # define TV_BLANK_LEVEL_MASK 0x000001ff
1471 # define TV_BLANK_LEVEL_SHIFT 0
1473 #define TV_H_CTL_1 0x68030
1474 /** Number of pixels in the hsync. */
1475 # define TV_HSYNC_END_MASK 0x1fff0000
1476 # define TV_HSYNC_END_SHIFT 16
1477 /** Total number of pixels minus one in the line (display and blanking). */
1478 # define TV_HTOTAL_MASK 0x00001fff
1479 # define TV_HTOTAL_SHIFT 0
1481 #define TV_H_CTL_2 0x68034
1482 /** Enables the colorburst (needed for non-component color) */
1483 # define TV_BURST_ENA (1 << 31)
1484 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1485 # define TV_HBURST_START_SHIFT 16
1486 # define TV_HBURST_START_MASK 0x1fff0000
1487 /** Length of the colorburst */
1488 # define TV_HBURST_LEN_SHIFT 0
1489 # define TV_HBURST_LEN_MASK 0x0001fff
1491 #define TV_H_CTL_3 0x68038
1492 /** End of hblank, measured in pixels minus one from start of hsync */
1493 # define TV_HBLANK_END_SHIFT 16
1494 # define TV_HBLANK_END_MASK 0x1fff0000
1495 /** Start of hblank, measured in pixels minus one from start of hsync */
1496 # define TV_HBLANK_START_SHIFT 0
1497 # define TV_HBLANK_START_MASK 0x0001fff
1499 #define TV_V_CTL_1 0x6803c
1501 # define TV_NBR_END_SHIFT 16
1502 # define TV_NBR_END_MASK 0x07ff0000
1504 # define TV_VI_END_F1_SHIFT 8
1505 # define TV_VI_END_F1_MASK 0x00003f00
1507 # define TV_VI_END_F2_SHIFT 0
1508 # define TV_VI_END_F2_MASK 0x0000003f
1510 #define TV_V_CTL_2 0x68040
1511 /** Length of vsync, in half lines */
1512 # define TV_VSYNC_LEN_MASK 0x07ff0000
1513 # define TV_VSYNC_LEN_SHIFT 16
1514 /** Offset of the start of vsync in field 1, measured in one less than the
1515 * number of half lines.
1517 # define TV_VSYNC_START_F1_MASK 0x00007f00
1518 # define TV_VSYNC_START_F1_SHIFT 8
1520 * Offset of the start of vsync in field 2, measured in one less than the
1521 * number of half lines.
1523 # define TV_VSYNC_START_F2_MASK 0x0000007f
1524 # define TV_VSYNC_START_F2_SHIFT 0
1526 #define TV_V_CTL_3 0x68044
1527 /** Enables generation of the equalization signal */
1528 # define TV_EQUAL_ENA (1 << 31)
1529 /** Length of vsync, in half lines */
1530 # define TV_VEQ_LEN_MASK 0x007f0000
1531 # define TV_VEQ_LEN_SHIFT 16
1532 /** Offset of the start of equalization in field 1, measured in one less than
1533 * the number of half lines.
1535 # define TV_VEQ_START_F1_MASK 0x0007f00
1536 # define TV_VEQ_START_F1_SHIFT 8
1538 * Offset of the start of equalization in field 2, measured in one less than
1539 * the number of half lines.
1541 # define TV_VEQ_START_F2_MASK 0x000007f
1542 # define TV_VEQ_START_F2_SHIFT 0
1544 #define TV_V_CTL_4 0x68048
1546 * Offset to start of vertical colorburst, measured in one less than the
1547 * number of lines from vertical start.
1549 # define TV_VBURST_START_F1_MASK 0x003f0000
1550 # define TV_VBURST_START_F1_SHIFT 16
1552 * Offset to the end of vertical colorburst, measured in one less than the
1553 * number of lines from the start of NBR.
1555 # define TV_VBURST_END_F1_MASK 0x000000ff
1556 # define TV_VBURST_END_F1_SHIFT 0
1558 #define TV_V_CTL_5 0x6804c
1560 * Offset to start of vertical colorburst, measured in one less than the
1561 * number of lines from vertical start.
1563 # define TV_VBURST_START_F2_MASK 0x003f0000
1564 # define TV_VBURST_START_F2_SHIFT 16
1566 * Offset to the end of vertical colorburst, measured in one less than the
1567 * number of lines from the start of NBR.
1569 # define TV_VBURST_END_F2_MASK 0x000000ff
1570 # define TV_VBURST_END_F2_SHIFT 0
1572 #define TV_V_CTL_6 0x68050
1574 * Offset to start of vertical colorburst, measured in one less than the
1575 * number of lines from vertical start.
1577 # define TV_VBURST_START_F3_MASK 0x003f0000
1578 # define TV_VBURST_START_F3_SHIFT 16
1580 * Offset to the end of vertical colorburst, measured in one less than the
1581 * number of lines from the start of NBR.
1583 # define TV_VBURST_END_F3_MASK 0x000000ff
1584 # define TV_VBURST_END_F3_SHIFT 0
1586 #define TV_V_CTL_7 0x68054
1588 * Offset to start of vertical colorburst, measured in one less than the
1589 * number of lines from vertical start.
1591 # define TV_VBURST_START_F4_MASK 0x003f0000
1592 # define TV_VBURST_START_F4_SHIFT 16
1594 * Offset to the end of vertical colorburst, measured in one less than the
1595 * number of lines from the start of NBR.
1597 # define TV_VBURST_END_F4_MASK 0x000000ff
1598 # define TV_VBURST_END_F4_SHIFT 0
1600 #define TV_SC_CTL_1 0x68060
1601 /** Turns on the first subcarrier phase generation DDA */
1602 # define TV_SC_DDA1_EN (1 << 31)
1603 /** Turns on the first subcarrier phase generation DDA */
1604 # define TV_SC_DDA2_EN (1 << 30)
1605 /** Turns on the first subcarrier phase generation DDA */
1606 # define TV_SC_DDA3_EN (1 << 29)
1607 /** Sets the subcarrier DDA to reset frequency every other field */
1608 # define TV_SC_RESET_EVERY_2 (0 << 24)
1609 /** Sets the subcarrier DDA to reset frequency every fourth field */
1610 # define TV_SC_RESET_EVERY_4 (1 << 24)
1611 /** Sets the subcarrier DDA to reset frequency every eighth field */
1612 # define TV_SC_RESET_EVERY_8 (2 << 24)
1613 /** Sets the subcarrier DDA to never reset the frequency */
1614 # define TV_SC_RESET_NEVER (3 << 24)
1615 /** Sets the peak amplitude of the colorburst.*/
1616 # define TV_BURST_LEVEL_MASK 0x00ff0000
1617 # define TV_BURST_LEVEL_SHIFT 16
1618 /** Sets the increment of the first subcarrier phase generation DDA */
1619 # define TV_SCDDA1_INC_MASK 0x00000fff
1620 # define TV_SCDDA1_INC_SHIFT 0
1622 #define TV_SC_CTL_2 0x68064
1623 /** Sets the rollover for the second subcarrier phase generation DDA */
1624 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1625 # define TV_SCDDA2_SIZE_SHIFT 16
1626 /** Sets the increent of the second subcarrier phase generation DDA */
1627 # define TV_SCDDA2_INC_MASK 0x00007fff
1628 # define TV_SCDDA2_INC_SHIFT 0
1630 #define TV_SC_CTL_3 0x68068
1631 /** Sets the rollover for the third subcarrier phase generation DDA */
1632 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1633 # define TV_SCDDA3_SIZE_SHIFT 16
1634 /** Sets the increent of the third subcarrier phase generation DDA */
1635 # define TV_SCDDA3_INC_MASK 0x00007fff
1636 # define TV_SCDDA3_INC_SHIFT 0
1638 #define TV_WIN_POS 0x68070
1639 /** X coordinate of the display from the start of horizontal active */
1640 # define TV_XPOS_MASK 0x1fff0000
1641 # define TV_XPOS_SHIFT 16
1642 /** Y coordinate of the display from the start of vertical active (NBR) */
1643 # define TV_YPOS_MASK 0x00000fff
1644 # define TV_YPOS_SHIFT 0
1646 #define TV_WIN_SIZE 0x68074
1647 /** Horizontal size of the display window, measured in pixels*/
1648 # define TV_XSIZE_MASK 0x1fff0000
1649 # define TV_XSIZE_SHIFT 16
1651 * Vertical size of the display window, measured in pixels.
1653 * Must be even for interlaced modes.
1655 # define TV_YSIZE_MASK 0x00000fff
1656 # define TV_YSIZE_SHIFT 0
1658 #define TV_FILTER_CTL_1 0x68080
1660 * Enables automatic scaling calculation.
1662 * If set, the rest of the registers are ignored, and the calculated values can
1663 * be read back from the register.
1665 # define TV_AUTO_SCALE (1 << 31)
1667 * Disables the vertical filter.
1669 * This is required on modes more than 1024 pixels wide */
1670 # define TV_V_FILTER_BYPASS (1 << 29)
1671 /** Enables adaptive vertical filtering */
1672 # define TV_VADAPT (1 << 28)
1673 # define TV_VADAPT_MODE_MASK (3 << 26)
1674 /** Selects the least adaptive vertical filtering mode */
1675 # define TV_VADAPT_MODE_LEAST (0 << 26)
1676 /** Selects the moderately adaptive vertical filtering mode */
1677 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1678 /** Selects the most adaptive vertical filtering mode */
1679 # define TV_VADAPT_MODE_MOST (3 << 26)
1681 * Sets the horizontal scaling factor.
1683 * This should be the fractional part of the horizontal scaling factor divided
1684 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1686 * (src width - 1) / ((oversample * dest width) - 1)
1688 # define TV_HSCALE_FRAC_MASK 0x00003fff
1689 # define TV_HSCALE_FRAC_SHIFT 0
1691 #define TV_FILTER_CTL_2 0x68084
1693 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1695 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1697 # define TV_VSCALE_INT_MASK 0x00038000
1698 # define TV_VSCALE_INT_SHIFT 15
1700 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1702 * \sa TV_VSCALE_INT_MASK
1704 # define TV_VSCALE_FRAC_MASK 0x00007fff
1705 # define TV_VSCALE_FRAC_SHIFT 0
1707 #define TV_FILTER_CTL_3 0x68088
1709 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1711 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1713 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1715 # define TV_VSCALE_IP_INT_MASK 0x00038000
1716 # define TV_VSCALE_IP_INT_SHIFT 15
1718 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1720 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1722 * \sa TV_VSCALE_IP_INT_MASK
1724 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1725 # define TV_VSCALE_IP_FRAC_SHIFT 0
1727 #define TV_CC_CONTROL 0x68090
1728 # define TV_CC_ENABLE (1 << 31)
1730 * Specifies which field to send the CC data in.
1732 * CC data is usually sent in field 0.
1734 # define TV_CC_FID_MASK (1 << 27)
1735 # define TV_CC_FID_SHIFT 27
1736 /** Sets the horizontal position of the CC data. Usually 135. */
1737 # define TV_CC_HOFF_MASK 0x03ff0000
1738 # define TV_CC_HOFF_SHIFT 16
1739 /** Sets the vertical position of the CC data. Usually 21 */
1740 # define TV_CC_LINE_MASK 0x0000003f
1741 # define TV_CC_LINE_SHIFT 0
1743 #define TV_CC_DATA 0x68094
1744 # define TV_CC_RDY (1 << 31)
1745 /** Second word of CC data to be transmitted. */
1746 # define TV_CC_DATA_2_MASK 0x007f0000
1747 # define TV_CC_DATA_2_SHIFT 16
1748 /** First word of CC data to be transmitted. */
1749 # define TV_CC_DATA_1_MASK 0x0000007f
1750 # define TV_CC_DATA_1_SHIFT 0
1752 #define TV_H_LUMA_0 0x68100
1753 #define TV_H_LUMA_59 0x681ec
1754 #define TV_H_CHROMA_0 0x68200
1755 #define TV_H_CHROMA_59 0x682ec
1756 #define TV_V_LUMA_0 0x68300
1757 #define TV_V_LUMA_42 0x683a8
1758 #define TV_V_CHROMA_0 0x68400
1759 #define TV_V_CHROMA_42 0x684a8
1762 #define DP_A 0x64000 /* eDP */
1763 #define DP_B 0x64100
1764 #define DP_C 0x64200
1765 #define DP_D 0x64300
1767 #define DP_PORT_EN (1 << 31)
1768 #define DP_PIPEB_SELECT (1 << 30)
1770 /* Link training mode - select a suitable mode for each stage */
1771 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
1772 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
1773 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1774 #define DP_LINK_TRAIN_OFF (3 << 28)
1775 #define DP_LINK_TRAIN_MASK (3 << 28)
1776 #define DP_LINK_TRAIN_SHIFT 28
1778 /* CPT Link training mode */
1779 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
1780 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
1781 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
1782 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
1783 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
1784 #define DP_LINK_TRAIN_SHIFT_CPT 8
1786 /* Signal voltages. These are mostly controlled by the other end */
1787 #define DP_VOLTAGE_0_4 (0 << 25)
1788 #define DP_VOLTAGE_0_6 (1 << 25)
1789 #define DP_VOLTAGE_0_8 (2 << 25)
1790 #define DP_VOLTAGE_1_2 (3 << 25)
1791 #define DP_VOLTAGE_MASK (7 << 25)
1792 #define DP_VOLTAGE_SHIFT 25
1794 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1797 #define DP_PRE_EMPHASIS_0 (0 << 22)
1798 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
1799 #define DP_PRE_EMPHASIS_6 (2 << 22)
1800 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
1801 #define DP_PRE_EMPHASIS_MASK (7 << 22)
1802 #define DP_PRE_EMPHASIS_SHIFT 22
1804 /* How many wires to use. I guess 3 was too hard */
1805 #define DP_PORT_WIDTH_1 (0 << 19)
1806 #define DP_PORT_WIDTH_2 (1 << 19)
1807 #define DP_PORT_WIDTH_4 (3 << 19)
1808 #define DP_PORT_WIDTH_MASK (7 << 19)
1810 /* Mystic DPCD version 1.1 special mode */
1811 #define DP_ENHANCED_FRAMING (1 << 18)
1814 #define DP_PLL_FREQ_270MHZ (0 << 16)
1815 #define DP_PLL_FREQ_160MHZ (1 << 16)
1816 #define DP_PLL_FREQ_MASK (3 << 16)
1818 /** locked once port is enabled */
1819 #define DP_PORT_REVERSAL (1 << 15)
1822 #define DP_PLL_ENABLE (1 << 14)
1824 /** sends the clock on lane 15 of the PEG for debug */
1825 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1827 #define DP_SCRAMBLING_DISABLE (1 << 12)
1828 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
1830 /** limit RGB values to avoid confusing TVs */
1831 #define DP_COLOR_RANGE_16_235 (1 << 8)
1833 /** Turn on the audio link */
1834 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1836 /** vs and hs sync polarity */
1837 #define DP_SYNC_VS_HIGH (1 << 4)
1838 #define DP_SYNC_HS_HIGH (1 << 3)
1841 #define DP_DETECTED (1 << 2)
1843 /** The aux channel provides a way to talk to the
1844 * signal sink for DDC etc. Max packet size supported
1845 * is 20 bytes in each direction, hence the 5 fixed
1848 #define DPA_AUX_CH_CTL 0x64010
1849 #define DPA_AUX_CH_DATA1 0x64014
1850 #define DPA_AUX_CH_DATA2 0x64018
1851 #define DPA_AUX_CH_DATA3 0x6401c
1852 #define DPA_AUX_CH_DATA4 0x64020
1853 #define DPA_AUX_CH_DATA5 0x64024
1855 #define DPB_AUX_CH_CTL 0x64110
1856 #define DPB_AUX_CH_DATA1 0x64114
1857 #define DPB_AUX_CH_DATA2 0x64118
1858 #define DPB_AUX_CH_DATA3 0x6411c
1859 #define DPB_AUX_CH_DATA4 0x64120
1860 #define DPB_AUX_CH_DATA5 0x64124
1862 #define DPC_AUX_CH_CTL 0x64210
1863 #define DPC_AUX_CH_DATA1 0x64214
1864 #define DPC_AUX_CH_DATA2 0x64218
1865 #define DPC_AUX_CH_DATA3 0x6421c
1866 #define DPC_AUX_CH_DATA4 0x64220
1867 #define DPC_AUX_CH_DATA5 0x64224
1869 #define DPD_AUX_CH_CTL 0x64310
1870 #define DPD_AUX_CH_DATA1 0x64314
1871 #define DPD_AUX_CH_DATA2 0x64318
1872 #define DPD_AUX_CH_DATA3 0x6431c
1873 #define DPD_AUX_CH_DATA4 0x64320
1874 #define DPD_AUX_CH_DATA5 0x64324
1876 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
1877 #define DP_AUX_CH_CTL_DONE (1 << 30)
1878 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
1879 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
1880 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
1881 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
1882 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
1883 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
1884 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
1885 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
1886 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
1887 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
1888 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
1889 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
1890 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
1891 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
1892 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
1893 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
1894 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
1895 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1896 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
1899 * Computing GMCH M and N values for the Display Port link
1901 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1903 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1905 * The GMCH value is used internally
1907 * bytes_per_pixel is the number of bytes coming out of the plane,
1908 * which is after the LUTs, so we want the bytes for our color format.
1909 * For our current usage, this is always 3, one byte for R, G and B.
1911 #define PIPEA_GMCH_DATA_M 0x70050
1912 #define PIPEB_GMCH_DATA_M 0x71050
1914 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1915 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
1916 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
1918 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
1920 #define PIPEA_GMCH_DATA_N 0x70054
1921 #define PIPEB_GMCH_DATA_N 0x71054
1922 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
1925 * Computing Link M and N values for the Display Port link
1927 * Link M / N = pixel_clock / ls_clk
1929 * (the DP spec calls pixel_clock the 'strm_clk')
1931 * The Link value is transmitted in the Main Stream
1932 * Attributes and VB-ID.
1935 #define PIPEA_DP_LINK_M 0x70060
1936 #define PIPEB_DP_LINK_M 0x71060
1937 #define PIPEA_DP_LINK_M_MASK (0xffffff)
1939 #define PIPEA_DP_LINK_N 0x70064
1940 #define PIPEB_DP_LINK_N 0x71064
1941 #define PIPEA_DP_LINK_N_MASK (0xffffff)
1943 /* Display & cursor control */
1945 /* dithering flag on Ironlake */
1946 #define PIPE_ENABLE_DITHER (1 << 4)
1947 #define PIPE_DITHER_TYPE_MASK (3 << 2)
1948 #define PIPE_DITHER_TYPE_SPATIAL (0 << 2)
1949 #define PIPE_DITHER_TYPE_ST01 (1 << 2)
1951 #define PIPEADSL 0x70000
1952 #define PIPEACONF 0x70008
1953 #define PIPEACONF_ENABLE (1<<31)
1954 #define PIPEACONF_DISABLE 0
1955 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1956 #define I965_PIPECONF_ACTIVE (1<<30)
1957 #define PIPEACONF_SINGLE_WIDE 0
1958 #define PIPEACONF_PIPE_UNLOCKED 0
1959 #define PIPEACONF_PIPE_LOCKED (1<<25)
1960 #define PIPEACONF_PALETTE 0
1961 #define PIPEACONF_GAMMA (1<<24)
1962 #define PIPECONF_FORCE_BORDER (1<<25)
1963 #define PIPECONF_PROGRESSIVE (0 << 21)
1964 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1965 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1966 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
1967 #define PIPEASTAT 0x70024
1968 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1969 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1970 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
1971 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1972 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1973 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1974 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1975 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1976 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1977 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1978 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1979 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1980 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1981 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1982 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1983 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1984 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1985 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1986 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1987 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1988 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1989 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
1990 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1991 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1992 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1993 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1994 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1995 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1996 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1997 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
1998 #define PIPE_8BPC (0 << 5)
1999 #define PIPE_10BPC (1 << 5)
2000 #define PIPE_6BPC (2 << 5)
2001 #define PIPE_12BPC (3 << 5)
2003 #define DSPARB 0x70030
2004 #define DSPARB_CSTART_MASK (0x7f << 7)
2005 #define DSPARB_CSTART_SHIFT 7
2006 #define DSPARB_BSTART_MASK (0x7f)
2007 #define DSPARB_BSTART_SHIFT 0
2008 #define DSPARB_BEND_SHIFT 9 /* on 855 */
2009 #define DSPARB_AEND_SHIFT 0
2011 #define DSPFW1 0x70034
2012 #define DSPFW_SR_SHIFT 23
2013 #define DSPFW_SR_MASK (0x1ff<<23)
2014 #define DSPFW_CURSORB_SHIFT 16
2015 #define DSPFW_CURSORB_MASK (0x3f<<16)
2016 #define DSPFW_PLANEB_SHIFT 8
2017 #define DSPFW_PLANEB_MASK (0x7f<<8)
2018 #define DSPFW_PLANEA_MASK (0x7f)
2019 #define DSPFW2 0x70038
2020 #define DSPFW_CURSORA_MASK 0x00003f00
2021 #define DSPFW_CURSORA_SHIFT 8
2022 #define DSPFW_PLANEC_MASK (0x7f)
2023 #define DSPFW3 0x7003c
2024 #define DSPFW_HPLL_SR_EN (1<<31)
2025 #define DSPFW_CURSOR_SR_SHIFT 24
2026 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
2027 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2028 #define DSPFW_HPLL_CURSOR_SHIFT 16
2029 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2030 #define DSPFW_HPLL_SR_MASK (0x1ff)
2032 /* FIFO watermark sizes etc */
2033 #define G4X_FIFO_LINE_SIZE 64
2034 #define I915_FIFO_LINE_SIZE 64
2035 #define I830_FIFO_LINE_SIZE 32
2037 #define G4X_FIFO_SIZE 127
2038 #define I945_FIFO_SIZE 127 /* 945 & 965 */
2039 #define I915_FIFO_SIZE 95
2040 #define I855GM_FIFO_SIZE 127 /* In cachelines */
2041 #define I830_FIFO_SIZE 95
2043 #define G4X_MAX_WM 0x3f
2044 #define I915_MAX_WM 0x3f
2046 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2047 #define PINEVIEW_FIFO_LINE_SIZE 64
2048 #define PINEVIEW_MAX_WM 0x1ff
2049 #define PINEVIEW_DFT_WM 0x3f
2050 #define PINEVIEW_DFT_HPLLOFF_WM 0
2051 #define PINEVIEW_GUARD_WM 10
2052 #define PINEVIEW_CURSOR_FIFO 64
2053 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2054 #define PINEVIEW_CURSOR_DFT_WM 0
2055 #define PINEVIEW_CURSOR_GUARD_WM 5
2058 /* define the Watermark register on Ironlake */
2059 #define WM0_PIPEA_ILK 0x45100
2060 #define WM0_PIPE_PLANE_MASK (0x7f<<16)
2061 #define WM0_PIPE_PLANE_SHIFT 16
2062 #define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2063 #define WM0_PIPE_SPRITE_SHIFT 8
2064 #define WM0_PIPE_CURSOR_MASK (0x1f)
2066 #define WM0_PIPEB_ILK 0x45104
2067 #define WM1_LP_ILK 0x45108
2068 #define WM1_LP_SR_EN (1<<31)
2069 #define WM1_LP_LATENCY_SHIFT 24
2070 #define WM1_LP_LATENCY_MASK (0x7f<<24)
2071 #define WM1_LP_SR_MASK (0x1ff<<8)
2072 #define WM1_LP_SR_SHIFT 8
2073 #define WM1_LP_CURSOR_MASK (0x3f)
2075 /* Memory latency timer register */
2076 #define MLTR_ILK 0x11222
2077 /* the unit of memory self-refresh latency time is 0.5us */
2078 #define ILK_SRLT_MASK 0x3f
2080 /* define the fifo size on Ironlake */
2081 #define ILK_DISPLAY_FIFO 128
2082 #define ILK_DISPLAY_MAXWM 64
2083 #define ILK_DISPLAY_DFTWM 8
2085 #define ILK_DISPLAY_SR_FIFO 512
2086 #define ILK_DISPLAY_MAX_SRWM 0x1ff
2087 #define ILK_DISPLAY_DFT_SRWM 0x3f
2088 #define ILK_CURSOR_SR_FIFO 64
2089 #define ILK_CURSOR_MAX_SRWM 0x3f
2090 #define ILK_CURSOR_DFT_SRWM 8
2092 #define ILK_FIFO_LINE_SIZE 64
2095 * The two pipe frame counter registers are not synchronized, so
2096 * reading a stable value is somewhat tricky. The following code
2100 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2101 * PIPE_FRAME_HIGH_SHIFT;
2102 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2103 * PIPE_FRAME_LOW_SHIFT);
2104 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2105 * PIPE_FRAME_HIGH_SHIFT);
2106 * } while (high1 != high2);
2107 * frame = (high1 << 8) | low1;
2109 #define PIPEAFRAMEHIGH 0x70040
2110 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2111 #define PIPE_FRAME_HIGH_SHIFT 0
2112 #define PIPEAFRAMEPIXEL 0x70044
2113 #define PIPE_FRAME_LOW_MASK 0xff000000
2114 #define PIPE_FRAME_LOW_SHIFT 24
2115 #define PIPE_PIXEL_MASK 0x00ffffff
2116 #define PIPE_PIXEL_SHIFT 0
2117 /* GM45+ just has to be different */
2118 #define PIPEA_FRMCOUNT_GM45 0x70040
2119 #define PIPEA_FLIPCOUNT_GM45 0x70044
2121 /* Cursor A & B regs */
2122 #define CURACNTR 0x70080
2123 /* Old style CUR*CNTR flags (desktop 8xx) */
2124 #define CURSOR_ENABLE 0x80000000
2125 #define CURSOR_GAMMA_ENABLE 0x40000000
2126 #define CURSOR_STRIDE_MASK 0x30000000
2127 #define CURSOR_FORMAT_SHIFT 24
2128 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2129 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2130 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2131 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2132 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2133 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2134 /* New style CUR*CNTR flags */
2135 #define CURSOR_MODE 0x27
2136 #define CURSOR_MODE_DISABLE 0x00
2137 #define CURSOR_MODE_64_32B_AX 0x07
2138 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2139 #define MCURSOR_PIPE_SELECT (1 << 28)
2140 #define MCURSOR_PIPE_A 0x00
2141 #define MCURSOR_PIPE_B (1 << 28)
2142 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2143 #define CURABASE 0x70084
2144 #define CURAPOS 0x70088
2145 #define CURSOR_POS_MASK 0x007FF
2146 #define CURSOR_POS_SIGN 0x8000
2147 #define CURSOR_X_SHIFT 0
2148 #define CURSOR_Y_SHIFT 16
2149 #define CURSIZE 0x700a0
2150 #define CURBCNTR 0x700c0
2151 #define CURBBASE 0x700c4
2152 #define CURBPOS 0x700c8
2154 /* Display A control */
2155 #define DSPACNTR 0x70180
2156 #define DISPLAY_PLANE_ENABLE (1<<31)
2157 #define DISPLAY_PLANE_DISABLE 0
2158 #define DISPPLANE_GAMMA_ENABLE (1<<30)
2159 #define DISPPLANE_GAMMA_DISABLE 0
2160 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2161 #define DISPPLANE_8BPP (0x2<<26)
2162 #define DISPPLANE_15_16BPP (0x4<<26)
2163 #define DISPPLANE_16BPP (0x5<<26)
2164 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2165 #define DISPPLANE_32BPP (0x7<<26)
2166 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2167 #define DISPPLANE_STEREO_ENABLE (1<<25)
2168 #define DISPPLANE_STEREO_DISABLE 0
2169 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
2170 #define DISPPLANE_SEL_PIPE_A 0
2171 #define DISPPLANE_SEL_PIPE_B (1<<24)
2172 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2173 #define DISPPLANE_SRC_KEY_DISABLE 0
2174 #define DISPPLANE_LINE_DOUBLE (1<<20)
2175 #define DISPPLANE_NO_LINE_DOUBLE 0
2176 #define DISPPLANE_STEREO_POLARITY_FIRST 0
2177 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2178 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2179 #define DISPPLANE_TILED (1<<10)
2180 #define DSPAADDR 0x70184
2181 #define DSPASTRIDE 0x70188
2182 #define DSPAPOS 0x7018C /* reserved */
2183 #define DSPASIZE 0x70190
2184 #define DSPASURF 0x7019C /* 965+ only */
2185 #define DSPATILEOFF 0x701A4 /* 965+ only */
2188 #define SWF00 0x71410
2189 #define SWF01 0x71414
2190 #define SWF02 0x71418
2191 #define SWF03 0x7141c
2192 #define SWF04 0x71420
2193 #define SWF05 0x71424
2194 #define SWF06 0x71428
2195 #define SWF10 0x70410
2196 #define SWF11 0x70414
2197 #define SWF14 0x71420
2198 #define SWF30 0x72414
2199 #define SWF31 0x72418
2200 #define SWF32 0x7241c
2203 #define PIPEBDSL 0x71000
2204 #define PIPEBCONF 0x71008
2205 #define PIPEBSTAT 0x71024
2206 #define PIPEBFRAMEHIGH 0x71040
2207 #define PIPEBFRAMEPIXEL 0x71044
2208 #define PIPEB_FRMCOUNT_GM45 0x71040
2209 #define PIPEB_FLIPCOUNT_GM45 0x71044
2212 /* Display B control */
2213 #define DSPBCNTR 0x71180
2214 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2215 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
2216 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2217 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2218 #define DSPBADDR 0x71184
2219 #define DSPBSTRIDE 0x71188
2220 #define DSPBPOS 0x7118C
2221 #define DSPBSIZE 0x71190
2222 #define DSPBSURF 0x7119C
2223 #define DSPBTILEOFF 0x711A4
2226 #define VGACNTRL 0x71400
2227 # define VGA_DISP_DISABLE (1 << 31)
2228 # define VGA_2X_MODE (1 << 30)
2229 # define VGA_PIPE_B_SELECT (1 << 29)
2233 #define CPU_VGACNTRL 0x41000
2235 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2236 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2237 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2238 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2239 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2240 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2241 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
2242 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2243 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2245 /* refresh rate hardware control */
2246 #define RR_HW_CTL 0x45300
2247 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2248 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2250 #define FDI_PLL_BIOS_0 0x46000
2251 #define FDI_PLL_BIOS_1 0x46004
2252 #define FDI_PLL_BIOS_2 0x46008
2253 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2254 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
2255 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
2257 #define PCH_DSPCLK_GATE_D 0x42020
2258 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2259 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2261 #define PCH_3DCGDIS0 0x46020
2262 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2263 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2265 #define FDI_PLL_FREQ_CTL 0x46030
2266 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2267 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2268 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2271 #define PIPEA_DATA_M1 0x60030
2272 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2273 #define TU_SIZE_MASK 0x7e000000
2274 #define PIPEA_DATA_M1_OFFSET 0
2275 #define PIPEA_DATA_N1 0x60034
2276 #define PIPEA_DATA_N1_OFFSET 0
2278 #define PIPEA_DATA_M2 0x60038
2279 #define PIPEA_DATA_M2_OFFSET 0
2280 #define PIPEA_DATA_N2 0x6003c
2281 #define PIPEA_DATA_N2_OFFSET 0
2283 #define PIPEA_LINK_M1 0x60040
2284 #define PIPEA_LINK_M1_OFFSET 0
2285 #define PIPEA_LINK_N1 0x60044
2286 #define PIPEA_LINK_N1_OFFSET 0
2288 #define PIPEA_LINK_M2 0x60048
2289 #define PIPEA_LINK_M2_OFFSET 0
2290 #define PIPEA_LINK_N2 0x6004c
2291 #define PIPEA_LINK_N2_OFFSET 0
2293 /* PIPEB timing regs are same start from 0x61000 */
2295 #define PIPEB_DATA_M1 0x61030
2296 #define PIPEB_DATA_M1_OFFSET 0
2297 #define PIPEB_DATA_N1 0x61034
2298 #define PIPEB_DATA_N1_OFFSET 0
2300 #define PIPEB_DATA_M2 0x61038
2301 #define PIPEB_DATA_M2_OFFSET 0
2302 #define PIPEB_DATA_N2 0x6103c
2303 #define PIPEB_DATA_N2_OFFSET 0
2305 #define PIPEB_LINK_M1 0x61040
2306 #define PIPEB_LINK_M1_OFFSET 0
2307 #define PIPEB_LINK_N1 0x61044
2308 #define PIPEB_LINK_N1_OFFSET 0
2310 #define PIPEB_LINK_M2 0x61048
2311 #define PIPEB_LINK_M2_OFFSET 0
2312 #define PIPEB_LINK_N2 0x6104c
2313 #define PIPEB_LINK_N2_OFFSET 0
2315 /* CPU panel fitter */
2316 #define PFA_CTL_1 0x68080
2317 #define PFB_CTL_1 0x68880
2318 #define PF_ENABLE (1<<31)
2319 #define PF_FILTER_MASK (3<<23)
2320 #define PF_FILTER_PROGRAMMED (0<<23)
2321 #define PF_FILTER_MED_3x3 (1<<23)
2322 #define PF_FILTER_EDGE_ENHANCE (2<<23)
2323 #define PF_FILTER_EDGE_SOFTEN (3<<23)
2324 #define PFA_WIN_SZ 0x68074
2325 #define PFB_WIN_SZ 0x68874
2326 #define PFA_WIN_POS 0x68070
2327 #define PFB_WIN_POS 0x68870
2329 /* legacy palette */
2330 #define LGC_PALETTE_A 0x4a000
2331 #define LGC_PALETTE_B 0x4a800
2334 #define DE_MASTER_IRQ_CONTROL (1 << 31)
2335 #define DE_SPRITEB_FLIP_DONE (1 << 29)
2336 #define DE_SPRITEA_FLIP_DONE (1 << 28)
2337 #define DE_PLANEB_FLIP_DONE (1 << 27)
2338 #define DE_PLANEA_FLIP_DONE (1 << 26)
2339 #define DE_PCU_EVENT (1 << 25)
2340 #define DE_GTT_FAULT (1 << 24)
2341 #define DE_POISON (1 << 23)
2342 #define DE_PERFORM_COUNTER (1 << 22)
2343 #define DE_PCH_EVENT (1 << 21)
2344 #define DE_AUX_CHANNEL_A (1 << 20)
2345 #define DE_DP_A_HOTPLUG (1 << 19)
2346 #define DE_GSE (1 << 18)
2347 #define DE_PIPEB_VBLANK (1 << 15)
2348 #define DE_PIPEB_EVEN_FIELD (1 << 14)
2349 #define DE_PIPEB_ODD_FIELD (1 << 13)
2350 #define DE_PIPEB_LINE_COMPARE (1 << 12)
2351 #define DE_PIPEB_VSYNC (1 << 11)
2352 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2353 #define DE_PIPEA_VBLANK (1 << 7)
2354 #define DE_PIPEA_EVEN_FIELD (1 << 6)
2355 #define DE_PIPEA_ODD_FIELD (1 << 5)
2356 #define DE_PIPEA_LINE_COMPARE (1 << 4)
2357 #define DE_PIPEA_VSYNC (1 << 3)
2358 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2360 #define DEISR 0x44000
2361 #define DEIMR 0x44004
2362 #define DEIIR 0x44008
2363 #define DEIER 0x4400c
2366 #define GT_PIPE_NOTIFY (1 << 4)
2367 #define GT_SYNC_STATUS (1 << 2)
2368 #define GT_USER_INTERRUPT (1 << 0)
2369 #define GT_BSD_USER_INTERRUPT (1 << 5)
2372 #define GTISR 0x44010
2373 #define GTIMR 0x44014
2374 #define GTIIR 0x44018
2375 #define GTIER 0x4401c
2377 #define ILK_DISPLAY_CHICKEN2 0x42004
2378 #define ILK_DPARB_GATE (1<<22)
2379 #define ILK_VSDPFD_FULL (1<<21)
2380 #define ILK_DSPCLK_GATE 0x42020
2381 #define ILK_DPARB_CLK_GATE (1<<5)
2383 #define DISP_ARB_CTL 0x45000
2384 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2385 #define DISP_FBC_WM_DIS (1<<15)
2389 /* south display engine interrupt */
2390 #define SDE_CRT_HOTPLUG (1 << 11)
2391 #define SDE_PORTD_HOTPLUG (1 << 10)
2392 #define SDE_PORTC_HOTPLUG (1 << 9)
2393 #define SDE_PORTB_HOTPLUG (1 << 8)
2394 #define SDE_SDVOB_HOTPLUG (1 << 6)
2395 #define SDE_HOTPLUG_MASK (0xf << 8)
2397 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
2398 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2399 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2400 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2402 #define SDEISR 0xc4000
2403 #define SDEIMR 0xc4004
2404 #define SDEIIR 0xc4008
2405 #define SDEIER 0xc400c
2407 /* digital port hotplug */
2408 #define PCH_PORT_HOTPLUG 0xc4030
2409 #define PORTD_HOTPLUG_ENABLE (1 << 20)
2410 #define PORTD_PULSE_DURATION_2ms (0)
2411 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2412 #define PORTD_PULSE_DURATION_6ms (2 << 18)
2413 #define PORTD_PULSE_DURATION_100ms (3 << 18)
2414 #define PORTD_HOTPLUG_NO_DETECT (0)
2415 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2416 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2417 #define PORTC_HOTPLUG_ENABLE (1 << 12)
2418 #define PORTC_PULSE_DURATION_2ms (0)
2419 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2420 #define PORTC_PULSE_DURATION_6ms (2 << 10)
2421 #define PORTC_PULSE_DURATION_100ms (3 << 10)
2422 #define PORTC_HOTPLUG_NO_DETECT (0)
2423 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2424 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2425 #define PORTB_HOTPLUG_ENABLE (1 << 4)
2426 #define PORTB_PULSE_DURATION_2ms (0)
2427 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2428 #define PORTB_PULSE_DURATION_6ms (2 << 2)
2429 #define PORTB_PULSE_DURATION_100ms (3 << 2)
2430 #define PORTB_HOTPLUG_NO_DETECT (0)
2431 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2432 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2434 #define PCH_GPIOA 0xc5010
2435 #define PCH_GPIOB 0xc5014
2436 #define PCH_GPIOC 0xc5018
2437 #define PCH_GPIOD 0xc501c
2438 #define PCH_GPIOE 0xc5020
2439 #define PCH_GPIOF 0xc5024
2441 #define PCH_GMBUS0 0xc5100
2442 #define PCH_GMBUS1 0xc5104
2443 #define PCH_GMBUS2 0xc5108
2444 #define PCH_GMBUS3 0xc510c
2445 #define PCH_GMBUS4 0xc5110
2446 #define PCH_GMBUS5 0xc5120
2448 #define PCH_DPLL_A 0xc6014
2449 #define PCH_DPLL_B 0xc6018
2451 #define PCH_FPA0 0xc6040
2452 #define PCH_FPA1 0xc6044
2453 #define PCH_FPB0 0xc6048
2454 #define PCH_FPB1 0xc604c
2456 #define PCH_DPLL_TEST 0xc606c
2458 #define PCH_DREF_CONTROL 0xC6200
2459 #define DREF_CONTROL_MASK 0x7fc3
2460 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2461 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2462 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2463 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2464 #define DREF_SSC_SOURCE_DISABLE (0<<11)
2465 #define DREF_SSC_SOURCE_ENABLE (2<<11)
2466 #define DREF_SSC_SOURCE_MASK (3<<11)
2467 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2468 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2469 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2470 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2471 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2472 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2473 #define DREF_SSC4_DOWNSPREAD (0<<6)
2474 #define DREF_SSC4_CENTERSPREAD (1<<6)
2475 #define DREF_SSC1_DISABLE (0<<1)
2476 #define DREF_SSC1_ENABLE (1<<1)
2477 #define DREF_SSC4_DISABLE (0)
2478 #define DREF_SSC4_ENABLE (1)
2480 #define PCH_RAWCLK_FREQ 0xc6204
2481 #define FDL_TP1_TIMER_SHIFT 12
2482 #define FDL_TP1_TIMER_MASK (3<<12)
2483 #define FDL_TP2_TIMER_SHIFT 10
2484 #define FDL_TP2_TIMER_MASK (3<<10)
2485 #define RAWCLK_FREQ_MASK 0x3ff
2487 #define PCH_DPLL_TMR_CFG 0xc6208
2489 #define PCH_SSC4_PARMS 0xc6210
2490 #define PCH_SSC4_AUX_PARMS 0xc6214
2492 #define PCH_DPLL_SEL 0xc7000
2493 #define TRANSA_DPLL_ENABLE (1<<3)
2494 #define TRANSA_DPLLB_SEL (1<<0)
2495 #define TRANSA_DPLLA_SEL 0
2496 #define TRANSB_DPLL_ENABLE (1<<7)
2497 #define TRANSB_DPLLB_SEL (1<<4)
2498 #define TRANSB_DPLLA_SEL (0)
2499 #define TRANSC_DPLL_ENABLE (1<<11)
2500 #define TRANSC_DPLLB_SEL (1<<8)
2501 #define TRANSC_DPLLA_SEL (0)
2505 #define TRANS_HTOTAL_A 0xe0000
2506 #define TRANS_HTOTAL_SHIFT 16
2507 #define TRANS_HACTIVE_SHIFT 0
2508 #define TRANS_HBLANK_A 0xe0004
2509 #define TRANS_HBLANK_END_SHIFT 16
2510 #define TRANS_HBLANK_START_SHIFT 0
2511 #define TRANS_HSYNC_A 0xe0008
2512 #define TRANS_HSYNC_END_SHIFT 16
2513 #define TRANS_HSYNC_START_SHIFT 0
2514 #define TRANS_VTOTAL_A 0xe000c
2515 #define TRANS_VTOTAL_SHIFT 16
2516 #define TRANS_VACTIVE_SHIFT 0
2517 #define TRANS_VBLANK_A 0xe0010
2518 #define TRANS_VBLANK_END_SHIFT 16
2519 #define TRANS_VBLANK_START_SHIFT 0
2520 #define TRANS_VSYNC_A 0xe0014
2521 #define TRANS_VSYNC_END_SHIFT 16
2522 #define TRANS_VSYNC_START_SHIFT 0
2524 #define TRANSA_DATA_M1 0xe0030
2525 #define TRANSA_DATA_N1 0xe0034
2526 #define TRANSA_DATA_M2 0xe0038
2527 #define TRANSA_DATA_N2 0xe003c
2528 #define TRANSA_DP_LINK_M1 0xe0040
2529 #define TRANSA_DP_LINK_N1 0xe0044
2530 #define TRANSA_DP_LINK_M2 0xe0048
2531 #define TRANSA_DP_LINK_N2 0xe004c
2533 #define TRANS_HTOTAL_B 0xe1000
2534 #define TRANS_HBLANK_B 0xe1004
2535 #define TRANS_HSYNC_B 0xe1008
2536 #define TRANS_VTOTAL_B 0xe100c
2537 #define TRANS_VBLANK_B 0xe1010
2538 #define TRANS_VSYNC_B 0xe1014
2540 #define TRANSB_DATA_M1 0xe1030
2541 #define TRANSB_DATA_N1 0xe1034
2542 #define TRANSB_DATA_M2 0xe1038
2543 #define TRANSB_DATA_N2 0xe103c
2544 #define TRANSB_DP_LINK_M1 0xe1040
2545 #define TRANSB_DP_LINK_N1 0xe1044
2546 #define TRANSB_DP_LINK_M2 0xe1048
2547 #define TRANSB_DP_LINK_N2 0xe104c
2549 #define TRANSACONF 0xf0008
2550 #define TRANSBCONF 0xf1008
2551 #define TRANS_DISABLE (0<<31)
2552 #define TRANS_ENABLE (1<<31)
2553 #define TRANS_STATE_MASK (1<<30)
2554 #define TRANS_STATE_DISABLE (0<<30)
2555 #define TRANS_STATE_ENABLE (1<<30)
2556 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
2557 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
2558 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
2559 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
2560 #define TRANS_DP_AUDIO_ONLY (1<<26)
2561 #define TRANS_DP_VIDEO_AUDIO (0<<26)
2562 #define TRANS_PROGRESSIVE (0<<21)
2563 #define TRANS_8BPC (0<<5)
2564 #define TRANS_10BPC (1<<5)
2565 #define TRANS_6BPC (2<<5)
2566 #define TRANS_12BPC (3<<5)
2568 #define FDI_RXA_CHICKEN 0xc200c
2569 #define FDI_RXB_CHICKEN 0xc2010
2570 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
2573 #define FDI_TXA_CTL 0x60100
2574 #define FDI_TXB_CTL 0x61100
2575 #define FDI_TX_DISABLE (0<<31)
2576 #define FDI_TX_ENABLE (1<<31)
2577 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
2578 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
2579 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
2580 #define FDI_LINK_TRAIN_NONE (3<<28)
2581 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
2582 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
2583 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
2584 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
2585 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
2586 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
2587 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
2588 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
2589 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
2590 SNB has different settings. */
2591 /* SNB A-stepping */
2592 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
2593 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
2594 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
2595 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
2596 /* SNB B-stepping */
2597 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
2598 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
2599 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
2600 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
2601 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
2602 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
2603 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
2604 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
2605 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
2606 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
2607 /* Ironlake: hardwired to 1 */
2608 #define FDI_TX_PLL_ENABLE (1<<14)
2609 /* both Tx and Rx */
2610 #define FDI_SCRAMBLING_ENABLE (0<<7)
2611 #define FDI_SCRAMBLING_DISABLE (1<<7)
2613 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
2614 #define FDI_RXA_CTL 0xf000c
2615 #define FDI_RXB_CTL 0xf100c
2616 #define FDI_RX_ENABLE (1<<31)
2617 #define FDI_RX_DISABLE (0<<31)
2618 /* train, dp width same as FDI_TX */
2619 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
2620 #define FDI_8BPC (0<<16)
2621 #define FDI_10BPC (1<<16)
2622 #define FDI_6BPC (2<<16)
2623 #define FDI_12BPC (3<<16)
2624 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
2625 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
2626 #define FDI_RX_PLL_ENABLE (1<<13)
2627 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
2628 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
2629 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
2630 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
2631 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2632 #define FDI_SEL_RAWCLK (0<<4)
2633 #define FDI_SEL_PCDCLK (1<<4)
2635 #define FDI_AUTO_TRAINING (1<<10)
2636 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
2637 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
2638 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
2639 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
2640 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
2642 #define FDI_RXA_MISC 0xf0010
2643 #define FDI_RXB_MISC 0xf1010
2644 #define FDI_RXA_TUSIZE1 0xf0030
2645 #define FDI_RXA_TUSIZE2 0xf0038
2646 #define FDI_RXB_TUSIZE1 0xf1030
2647 #define FDI_RXB_TUSIZE2 0xf1038
2649 /* FDI_RX interrupt register format */
2650 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
2651 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
2652 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
2653 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
2654 #define FDI_RX_FS_CODE_ERR (1<<6)
2655 #define FDI_RX_FE_CODE_ERR (1<<5)
2656 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
2657 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
2658 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
2659 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
2660 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
2662 #define FDI_RXA_IIR 0xf0014
2663 #define FDI_RXA_IMR 0xf0018
2664 #define FDI_RXB_IIR 0xf1014
2665 #define FDI_RXB_IMR 0xf1018
2667 #define FDI_PLL_CTL_1 0xfe000
2668 #define FDI_PLL_CTL_2 0xfe004
2671 #define PCH_ADPA 0xe1100
2672 #define ADPA_TRANS_SELECT_MASK (1<<30)
2673 #define ADPA_TRANS_A_SELECT 0
2674 #define ADPA_TRANS_B_SELECT (1<<30)
2675 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2676 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2677 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2678 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2679 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2680 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2681 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2682 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2683 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2684 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2685 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2686 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2687 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2688 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2689 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2690 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2691 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2692 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2693 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2696 #define HDMIB 0xe1140
2697 #define PORT_ENABLE (1 << 31)
2698 #define TRANSCODER_A (0)
2699 #define TRANSCODER_B (1 << 30)
2700 #define COLOR_FORMAT_8bpc (0)
2701 #define COLOR_FORMAT_12bpc (3 << 26)
2702 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
2703 #define SDVO_ENCODING (0)
2704 #define TMDS_ENCODING (2 << 10)
2705 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
2706 #define SDVOB_BORDER_ENABLE (1 << 7)
2707 #define AUDIO_ENABLE (1 << 6)
2708 #define VSYNC_ACTIVE_HIGH (1 << 4)
2709 #define HSYNC_ACTIVE_HIGH (1 << 3)
2710 #define PORT_DETECTED (1 << 2)
2712 /* PCH SDVOB multiplex with HDMIB */
2713 #define PCH_SDVOB HDMIB
2715 #define HDMIC 0xe1150
2716 #define HDMID 0xe1160
2718 #define PCH_LVDS 0xe1180
2719 #define LVDS_DETECTED (1 << 1)
2721 #define BLC_PWM_CPU_CTL2 0x48250
2722 #define PWM_ENABLE (1 << 31)
2723 #define PWM_PIPE_A (0 << 29)
2724 #define PWM_PIPE_B (1 << 29)
2725 #define BLC_PWM_CPU_CTL 0x48254
2727 #define BLC_PWM_PCH_CTL1 0xc8250
2728 #define PWM_PCH_ENABLE (1 << 31)
2729 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
2730 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
2731 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
2732 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
2734 #define BLC_PWM_PCH_CTL2 0xc8254
2736 #define PCH_PP_STATUS 0xc7200
2737 #define PCH_PP_CONTROL 0xc7204
2738 #define EDP_FORCE_VDD (1 << 3)
2739 #define EDP_BLC_ENABLE (1 << 2)
2740 #define PANEL_POWER_RESET (1 << 1)
2741 #define PANEL_POWER_OFF (0 << 0)
2742 #define PANEL_POWER_ON (1 << 0)
2743 #define PCH_PP_ON_DELAYS 0xc7208
2744 #define EDP_PANEL (1 << 30)
2745 #define PCH_PP_OFF_DELAYS 0xc720c
2746 #define PCH_PP_DIVISOR 0xc7210
2748 #define PCH_DP_B 0xe4100
2749 #define PCH_DPB_AUX_CH_CTL 0xe4110
2750 #define PCH_DPB_AUX_CH_DATA1 0xe4114
2751 #define PCH_DPB_AUX_CH_DATA2 0xe4118
2752 #define PCH_DPB_AUX_CH_DATA3 0xe411c
2753 #define PCH_DPB_AUX_CH_DATA4 0xe4120
2754 #define PCH_DPB_AUX_CH_DATA5 0xe4124
2756 #define PCH_DP_C 0xe4200
2757 #define PCH_DPC_AUX_CH_CTL 0xe4210
2758 #define PCH_DPC_AUX_CH_DATA1 0xe4214
2759 #define PCH_DPC_AUX_CH_DATA2 0xe4218
2760 #define PCH_DPC_AUX_CH_DATA3 0xe421c
2761 #define PCH_DPC_AUX_CH_DATA4 0xe4220
2762 #define PCH_DPC_AUX_CH_DATA5 0xe4224
2764 #define PCH_DP_D 0xe4300
2765 #define PCH_DPD_AUX_CH_CTL 0xe4310
2766 #define PCH_DPD_AUX_CH_DATA1 0xe4314
2767 #define PCH_DPD_AUX_CH_DATA2 0xe4318
2768 #define PCH_DPD_AUX_CH_DATA3 0xe431c
2769 #define PCH_DPD_AUX_CH_DATA4 0xe4320
2770 #define PCH_DPD_AUX_CH_DATA5 0xe4324
2773 #define PORT_TRANS_A_SEL_CPT 0
2774 #define PORT_TRANS_B_SEL_CPT (1<<29)
2775 #define PORT_TRANS_C_SEL_CPT (2<<29)
2776 #define PORT_TRANS_SEL_MASK (3<<29)
2778 #define TRANS_DP_CTL_A 0xe0300
2779 #define TRANS_DP_CTL_B 0xe1300
2780 #define TRANS_DP_CTL_C 0xe2300
2781 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
2782 #define TRANS_DP_PORT_SEL_B (0<<29)
2783 #define TRANS_DP_PORT_SEL_C (1<<29)
2784 #define TRANS_DP_PORT_SEL_D (2<<29)
2785 #define TRANS_DP_PORT_SEL_MASK (3<<29)
2786 #define TRANS_DP_AUDIO_ONLY (1<<26)
2787 #define TRANS_DP_ENH_FRAMING (1<<18)
2788 #define TRANS_DP_8BPC (0<<9)
2789 #define TRANS_DP_10BPC (1<<9)
2790 #define TRANS_DP_6BPC (2<<9)
2791 #define TRANS_DP_12BPC (3<<9)
2792 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
2793 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
2794 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
2795 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
2797 /* SNB eDP training params */
2798 /* SNB A-stepping */
2799 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
2800 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
2801 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
2802 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
2803 /* SNB B-stepping */
2804 #define EDP_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
2805 #define EDP_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
2806 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
2807 #define EDP_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
2808 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
2810 #endif /* _I915_REG_H_ */