drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/pci.h>
  38 #include <linux/vgaarb.h>
  39 #include <linux/acpi.h>
  40 #include <linux/pnp.h>
  41 #include <linux/vga_switcheroo.h>
  42 #include <linux/slab.h>
  43
  44 extern int intel_max_stolen; /* from AGP driver */
  45
  46 /**
  47  * Sets up the hardware status page for devices that need a physical address
  48  * in the register.
  49  */
  50 static int i915_init_phys_hws(struct drm_device *dev)
  51 {
  52         drm_i915_private_t *dev_priv = dev->dev_private;
  53         /* Program Hardware Status Page */
  54         dev_priv->status_page_dmah =
  55                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  56
  57         if (!dev_priv->status_page_dmah) {
  58                 DRM_ERROR("Can not allocate hardware status page\n");
  59                 return -ENOMEM;
  60         }
  61         dev_priv->render_ring.status_page.page_addr
  62                 = dev_priv->status_page_dmah->vaddr;
  63         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  64
  65         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  66
  67         if (IS_I965G(dev))
  68                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  69                                              0xf0;
  70
  71         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  72         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  73         return 0;
  74 }
  75
  76 /**
  77  * Frees the hardware status page, whether it's a physical address or a virtual
  78  * address set up by the X Server.
  79  */
  80 static void i915_free_hws(struct drm_device *dev)
  81 {
  82         drm_i915_private_t *dev_priv = dev->dev_private;
  83         if (dev_priv->status_page_dmah) {
  84                 drm_pci_free(dev, dev_priv->status_page_dmah);
  85                 dev_priv->status_page_dmah = NULL;
  86         }
  87
  88         if (dev_priv->render_ring.status_page.gfx_addr) {
  89                 dev_priv->render_ring.status_page.gfx_addr = 0;
  90                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  91         }
  92
  93         /* Need to rewrite hardware status page */
  94         I915_WRITE(HWS_PGA, 0x1ffff000);
  95 }
  96
  97 void i915_kernel_lost_context(struct drm_device * dev)
  98 {
  99         drm_i915_private_t *dev_priv = dev->dev_private;
 100         struct drm_i915_master_private *master_priv;
 101         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 102
 103         /*
 104          * We should never lose context on the ring with modesetting
 105          * as we don't expose it to userspace
 106          */
 107         if (drm_core_check_feature(dev, DRIVER_MODESET))
 108                 return;
 109
 110         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 111         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 112         ring->space = ring->head - (ring->tail + 8);
 113         if (ring->space < 0)
 114                 ring->space += ring->size;
 115
 116         if (!dev->primary->master)
 117                 return;
 118
 119         master_priv = dev->primary->master->driver_priv;
 120         if (ring->head == ring->tail && master_priv->sarea_priv)
 121                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 122 }
 123
 124 static int i915_dma_cleanup(struct drm_device * dev)
 125 {
 126         drm_i915_private_t *dev_priv = dev->dev_private;
 127         /* Make sure interrupts are disabled here because the uninstall ioctl
 128          * may not have been called from userspace and after dev_private
 129          * is freed, it's too late.
 130          */
 131         if (dev->irq_enabled)
 132                 drm_irq_uninstall(dev);
 133
 134         mutex_lock(&dev->struct_mutex);
 135         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
 136         if (HAS_BSD(dev))
 137                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
 138         mutex_unlock(&dev->struct_mutex);
 139
 140         /* Clear the HWS virtual address at teardown */
 141         if (I915_NEED_GFX_HWS(dev))
 142                 i915_free_hws(dev);
 143
 144         return 0;
 145 }
 146
 147 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 148 {
 149         drm_i915_private_t *dev_priv = dev->dev_private;
 150         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 151
 152         master_priv->sarea = drm_getsarea(dev);
 153         if (master_priv->sarea) {
 154                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 155                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 156         } else {
 157                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 158         }
 159
 160         if (init->ring_size != 0) {
 161                 if (dev_priv->render_ring.gem_object != NULL) {
 162                         i915_dma_cleanup(dev);
 163                         DRM_ERROR("Client tried to initialize ringbuffer in "
 164                                   "GEM mode\n");
 165                         return -EINVAL;
 166                 }
 167
 168                 dev_priv->render_ring.size = init->ring_size;
 169
 170                 dev_priv->render_ring.map.offset = init->ring_start;
 171                 dev_priv->render_ring.map.size = init->ring_size;
 172                 dev_priv->render_ring.map.type = 0;
 173                 dev_priv->render_ring.map.flags = 0;
 174                 dev_priv->render_ring.map.mtrr = 0;
 175
 176                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
 177
 178                 if (dev_priv->render_ring.map.handle == NULL) {
 179                         i915_dma_cleanup(dev);
 180                         DRM_ERROR("can not ioremap virtual address for"
 181                                   " ring buffer\n");
 182                         return -ENOMEM;
 183                 }
 184         }
 185
 186         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
 187
 188         dev_priv->cpp = init->cpp;
 189         dev_priv->back_offset = init->back_offset;
 190         dev_priv->front_offset = init->front_offset;
 191         dev_priv->current_page = 0;
 192         if (master_priv->sarea_priv)
 193                 master_priv->sarea_priv->pf_current_page = 0;
 194
 195         /* Allow hardware batchbuffers unless told otherwise.
 196          */
 197         dev_priv->allow_batchbuffer = 1;
 198
 199         return 0;
 200 }
 201
 202 static int i915_dma_resume(struct drm_device * dev)
 203 {
 204         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 205
 206         struct intel_ring_buffer *ring;
 207         DRM_DEBUG_DRIVER("%s\n", __func__);
 208
 209         ring = &dev_priv->render_ring;
 210
 211         if (ring->map.handle == NULL) {
 212                 DRM_ERROR("can not ioremap virtual address for"
 213                           " ring buffer\n");
 214                 return -ENOMEM;
 215         }
 216
 217         /* Program Hardware Status Page */
 218         if (!ring->status_page.page_addr) {
 219                 DRM_ERROR("Can not find hardware status page\n");
 220                 return -EINVAL;
 221         }
 222         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 223                                 ring->status_page.page_addr);
 224         if (ring->status_page.gfx_addr != 0)
 225                 ring->setup_status_page(dev, ring);
 226         else
 227                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 228
 229         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 230
 231         return 0;
 232 }
 233
 234 static int i915_dma_init(struct drm_device *dev, void *data,
 235                          struct drm_file *file_priv)
 236 {
 237         drm_i915_init_t *init = data;
 238         int retcode = 0;
 239
 240         switch (init->func) {
 241         case I915_INIT_DMA:
 242                 retcode = i915_initialize(dev, init);
 243                 break;
 244         case I915_CLEANUP_DMA:
 245                 retcode = i915_dma_cleanup(dev);
 246                 break;
 247         case I915_RESUME_DMA:
 248                 retcode = i915_dma_resume(dev);
 249                 break;
 250         default:
 251                 retcode = -EINVAL;
 252                 break;
 253         }
 254
 255         return retcode;
 256 }
 257
 258 /* Implement basically the same security restrictions as hardware does
 259  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 260  *
 261  * Most of the calculations below involve calculating the size of a
 262  * particular instruction.  It's important to get the size right as
 263  * that tells us where the next instruction to check is.  Any illegal
 264  * instruction detected will be given a size of zero, which is a
 265  * signal to abort the rest of the buffer.
 266  */
 267 static int do_validate_cmd(int cmd)
 268 {
 269         switch (((cmd >> 29) & 0x7)) {
 270         case 0x0:
 271                 switch ((cmd >> 23) & 0x3f) {
 272                 case 0x0:
 273                         return 1;       /* MI_NOOP */
 274                 case 0x4:
 275                         return 1;       /* MI_FLUSH */
 276                 default:
 277                         return 0;       /* disallow everything else */
 278                 }
 279                 break;
 280         case 0x1:
 281                 return 0;       /* reserved */
 282         case 0x2:
 283                 return (cmd & 0xff) + 2;        /* 2d commands */
 284         case 0x3:
 285                 if (((cmd >> 24) & 0x1f) <= 0x18)
 286                         return 1;
 287
 288                 switch ((cmd >> 24) & 0x1f) {
 289                 case 0x1c:
 290                         return 1;
 291                 case 0x1d:
 292                         switch ((cmd >> 16) & 0xff) {
 293                         case 0x3:
 294                                 return (cmd & 0x1f) + 2;
 295                         case 0x4:
 296                                 return (cmd & 0xf) + 2;
 297                         default:
 298                                 return (cmd & 0xffff) + 2;
 299                         }
 300                 case 0x1e:
 301                         if (cmd & (1 << 23))
 302                                 return (cmd & 0xffff) + 1;
 303                         else
 304                                 return 1;
 305                 case 0x1f:
 306                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 307                                 return (cmd & 0x1ffff) + 2;
 308                         else if (cmd & (1 << 17))       /* indirect random */
 309                                 if ((cmd & 0xffff) == 0)
 310                                         return 0;       /* unknown length, too hard */
 311                                 else
 312                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 313                         else
 314                                 return 2;       /* indirect sequential */
 315                 default:
 316                         return 0;
 317                 }
 318         default:
 319                 return 0;
 320         }
 321
 322         return 0;
 323 }
 324
 325 static int validate_cmd(int cmd)
 326 {
 327         int ret = do_validate_cmd(cmd);
 328
 329 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 330
 331         return ret;
 332 }
 333
 334 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 335 {
 336         drm_i915_private_t *dev_priv = dev->dev_private;
 337         int i;
 338
 339         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
 340                 return -EINVAL;
 341
 342         BEGIN_LP_RING((dwords+1)&~1);
 343
 344         for (i = 0; i < dwords;) {
 345                 int cmd, sz;
 346
 347                 cmd = buffer[i];
 348
 349                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 350                         return -EINVAL;
 351
 352                 OUT_RING(cmd);
 353
 354                 while (++i, --sz) {
 355                         OUT_RING(buffer[i]);
 356                 }
 357         }
 358
 359         if (dwords & 1)
 360                 OUT_RING(0);
 361
 362         ADVANCE_LP_RING();
 363
 364         return 0;
 365 }
 366
 367 int
 368 i915_emit_box(struct drm_device *dev,
 369               struct drm_clip_rect *boxes,
 370               int i, int DR1, int DR4)
 371 {
 372         struct drm_clip_rect box = boxes[i];
 373
 374         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 375                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 376                           box.x1, box.y1, box.x2, box.y2);
 377                 return -EINVAL;
 378         }
 379
 380         if (IS_I965G(dev)) {
 381                 BEGIN_LP_RING(4);
 382                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 383                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 384                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 385                 OUT_RING(DR4);
 386                 ADVANCE_LP_RING();
 387         } else {
 388                 BEGIN_LP_RING(6);
 389                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 390                 OUT_RING(DR1);
 391                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 392                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 393                 OUT_RING(DR4);
 394                 OUT_RING(0);
 395                 ADVANCE_LP_RING();
 396         }
 397
 398         return 0;
 399 }
 400
 401 /* XXX: Emitting the counter should really be moved to part of the IRQ
 402  * emit. For now, do it in both places:
 403  */
 404
 405 static void i915_emit_breadcrumb(struct drm_device *dev)
 406 {
 407         drm_i915_private_t *dev_priv = dev->dev_private;
 408         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 409
 410         dev_priv->counter++;
 411         if (dev_priv->counter > 0x7FFFFFFFUL)
 412                 dev_priv->counter = 0;
 413         if (master_priv->sarea_priv)
 414                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 415
 416         BEGIN_LP_RING(4);
 417         OUT_RING(MI_STORE_DWORD_INDEX);
 418         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 419         OUT_RING(dev_priv->counter);
 420         OUT_RING(0);
 421         ADVANCE_LP_RING();
 422 }
 423
 424 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 425                                    drm_i915_cmdbuffer_t *cmd,
 426                                    struct drm_clip_rect *cliprects,
 427                                    void *cmdbuf)
 428 {
 429         int nbox = cmd->num_cliprects;
 430         int i = 0, count, ret;
 431
 432         if (cmd->sz & 0x3) {
 433                 DRM_ERROR("alignment");
 434                 return -EINVAL;
 435         }
 436
 437         i915_kernel_lost_context(dev);
 438
 439         count = nbox ? nbox : 1;
 440
 441         for (i = 0; i < count; i++) {
 442                 if (i < nbox) {
 443                         ret = i915_emit_box(dev, cliprects, i,
 444                                             cmd->DR1, cmd->DR4);
 445                         if (ret)
 446                                 return ret;
 447                 }
 448
 449                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 450                 if (ret)
 451                         return ret;
 452         }
 453
 454         i915_emit_breadcrumb(dev);
 455         return 0;
 456 }
 457
 458 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 459                                      drm_i915_batchbuffer_t * batch,
 460                                      struct drm_clip_rect *cliprects)
 461 {
 462         int nbox = batch->num_cliprects;
 463         int i = 0, count;
 464
 465         if ((batch->start | batch->used) & 0x7) {
 466                 DRM_ERROR("alignment");
 467                 return -EINVAL;
 468         }
 469
 470         i915_kernel_lost_context(dev);
 471
 472         count = nbox ? nbox : 1;
 473
 474         for (i = 0; i < count; i++) {
 475                 if (i < nbox) {
 476                         int ret = i915_emit_box(dev, cliprects, i,
 477                                                 batch->DR1, batch->DR4);
 478                         if (ret)
 479                                 return ret;
 480                 }
 481
 482                 if (!IS_I830(dev) && !IS_845G(dev)) {
 483                         BEGIN_LP_RING(2);
 484                         if (IS_I965G(dev)) {
 485                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 486                                 OUT_RING(batch->start);
 487                         } else {
 488                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 489                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 490                         }
 491                         ADVANCE_LP_RING();
 492                 } else {
 493                         BEGIN_LP_RING(4);
 494                         OUT_RING(MI_BATCH_BUFFER);
 495                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 496                         OUT_RING(batch->start + batch->used - 4);
 497                         OUT_RING(0);
 498                         ADVANCE_LP_RING();
 499                 }
 500         }
 501
 502
 503         if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
 504                 BEGIN_LP_RING(2);
 505                 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 506                 OUT_RING(MI_NOOP);
 507                 ADVANCE_LP_RING();
 508         }
 509         i915_emit_breadcrumb(dev);
 510
 511         return 0;
 512 }
 513
 514 static int i915_dispatch_flip(struct drm_device * dev)
 515 {
 516         drm_i915_private_t *dev_priv = dev->dev_private;
 517         struct drm_i915_master_private *master_priv =
 518                 dev->primary->master->driver_priv;
 519
 520         if (!master_priv->sarea_priv)
 521                 return -EINVAL;
 522
 523         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 524                           __func__,
 525                          dev_priv->current_page,
 526                          master_priv->sarea_priv->pf_current_page);
 527
 528         i915_kernel_lost_context(dev);
 529
 530         BEGIN_LP_RING(2);
 531         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 532         OUT_RING(0);
 533         ADVANCE_LP_RING();
 534
 535         BEGIN_LP_RING(6);
 536         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 537         OUT_RING(0);
 538         if (dev_priv->current_page == 0) {
 539                 OUT_RING(dev_priv->back_offset);
 540                 dev_priv->current_page = 1;
 541         } else {
 542                 OUT_RING(dev_priv->front_offset);
 543                 dev_priv->current_page = 0;
 544         }
 545         OUT_RING(0);
 546         ADVANCE_LP_RING();
 547
 548         BEGIN_LP_RING(2);
 549         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 550         OUT_RING(0);
 551         ADVANCE_LP_RING();
 552
 553         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 554
 555         BEGIN_LP_RING(4);
 556         OUT_RING(MI_STORE_DWORD_INDEX);
 557         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 558         OUT_RING(dev_priv->counter);
 559         OUT_RING(0);
 560         ADVANCE_LP_RING();
 561
 562         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 563         return 0;
 564 }
 565
 566 static int i915_quiescent(struct drm_device * dev)
 567 {
 568         drm_i915_private_t *dev_priv = dev->dev_private;
 569
 570         i915_kernel_lost_context(dev);
 571         return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
 572                                       dev_priv->render_ring.size - 8);
 573 }
 574
 575 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 576                             struct drm_file *file_priv)
 577 {
 578         int ret;
 579
 580         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 581
 582         mutex_lock(&dev->struct_mutex);
 583         ret = i915_quiescent(dev);
 584         mutex_unlock(&dev->struct_mutex);
 585
 586         return ret;
 587 }
 588
 589 static int i915_batchbuffer(struct drm_device *dev, void *data,
 590                             struct drm_file *file_priv)
 591 {
 592         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 593         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 594         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 595             master_priv->sarea_priv;
 596         drm_i915_batchbuffer_t *batch = data;
 597         int ret;
 598         struct drm_clip_rect *cliprects = NULL;
 599
 600         if (!dev_priv->allow_batchbuffer) {
 601                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 602                 return -EINVAL;
 603         }
 604
 605         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 606                         batch->start, batch->used, batch->num_cliprects);
 607
 608         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 609
 610         if (batch->num_cliprects < 0)
 611                 return -EINVAL;
 612
 613         if (batch->num_cliprects) {
 614                 cliprects = kcalloc(batch->num_cliprects,
 615                                     sizeof(struct drm_clip_rect),
 616                                     GFP_KERNEL);
 617                 if (cliprects == NULL)
 618                         return -ENOMEM;
 619
 620                 ret = copy_from_user(cliprects, batch->cliprects,
 621                                      batch->num_cliprects *
 622                                      sizeof(struct drm_clip_rect));
 623                 if (ret != 0)
 624                         goto fail_free;
 625         }
 626
 627         mutex_lock(&dev->struct_mutex);
 628         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 629         mutex_unlock(&dev->struct_mutex);
 630
 631         if (sarea_priv)
 632                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 633
 634 fail_free:
 635         kfree(cliprects);
 636
 637         return ret;
 638 }
 639
 640 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 641                           struct drm_file *file_priv)
 642 {
 643         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 644         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 645         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 646             master_priv->sarea_priv;
 647         drm_i915_cmdbuffer_t *cmdbuf = data;
 648         struct drm_clip_rect *cliprects = NULL;
 649         void *batch_data;
 650         int ret;
 651
 652         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 653                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 654
 655         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 656
 657         if (cmdbuf->num_cliprects < 0)
 658                 return -EINVAL;
 659
 660         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 661         if (batch_data == NULL)
 662                 return -ENOMEM;
 663
 664         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 665         if (ret != 0)
 666                 goto fail_batch_free;
 667
 668         if (cmdbuf->num_cliprects) {
 669                 cliprects = kcalloc(cmdbuf->num_cliprects,
 670                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 671                 if (cliprects == NULL) {
 672                         ret = -ENOMEM;
 673                         goto fail_batch_free;
 674                 }
 675
 676                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 677                                      cmdbuf->num_cliprects *
 678                                      sizeof(struct drm_clip_rect));
 679                 if (ret != 0)
 680                         goto fail_clip_free;
 681         }
 682
 683         mutex_lock(&dev->struct_mutex);
 684         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 685         mutex_unlock(&dev->struct_mutex);
 686         if (ret) {
 687                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 688                 goto fail_clip_free;
 689         }
 690
 691         if (sarea_priv)
 692                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 693
 694 fail_clip_free:
 695         kfree(cliprects);
 696 fail_batch_free:
 697         kfree(batch_data);
 698
 699         return ret;
 700 }
 701
 702 static int i915_flip_bufs(struct drm_device *dev, void *data,
 703                           struct drm_file *file_priv)
 704 {
 705         int ret;
 706
 707         DRM_DEBUG_DRIVER("%s\n", __func__);
 708
 709         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 710
 711         mutex_lock(&dev->struct_mutex);
 712         ret = i915_dispatch_flip(dev);
 713         mutex_unlock(&dev->struct_mutex);
 714
 715         return ret;
 716 }
 717
 718 static int i915_getparam(struct drm_device *dev, void *data,
 719                          struct drm_file *file_priv)
 720 {
 721         drm_i915_private_t *dev_priv = dev->dev_private;
 722         drm_i915_getparam_t *param = data;
 723         int value;
 724
 725         if (!dev_priv) {
 726                 DRM_ERROR("called with no initialization\n");
 727                 return -EINVAL;
 728         }
 729
 730         switch (param->param) {
 731         case I915_PARAM_IRQ_ACTIVE:
 732                 value = dev->pdev->irq ? 1 : 0;
 733                 break;
 734         case I915_PARAM_ALLOW_BATCHBUFFER:
 735                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 736                 break;
 737         case I915_PARAM_LAST_DISPATCH:
 738                 value = READ_BREADCRUMB(dev_priv);
 739                 break;
 740         case I915_PARAM_CHIPSET_ID:
 741                 value = dev->pci_device;
 742                 break;
 743         case I915_PARAM_HAS_GEM:
 744                 value = dev_priv->has_gem;
 745                 break;
 746         case I915_PARAM_NUM_FENCES_AVAIL:
 747                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 748                 break;
 749         case I915_PARAM_HAS_OVERLAY:
 750                 value = dev_priv->overlay ? 1 : 0;
 751                 break;
 752         case I915_PARAM_HAS_PAGEFLIPPING:
 753                 value = 1;
 754                 break;
 755         case I915_PARAM_HAS_EXECBUF2:
 756                 /* depends on GEM */
 757                 value = dev_priv->has_gem;
 758                 break;
 759         case I915_PARAM_HAS_BSD:
 760                 value = HAS_BSD(dev);
 761                 break;
 762         default:
 763                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 764                                  param->param);
 765                 return -EINVAL;
 766         }
 767
 768         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 769                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 770                 return -EFAULT;
 771         }
 772
 773         return 0;
 774 }
 775
 776 static int i915_setparam(struct drm_device *dev, void *data,
 777                          struct drm_file *file_priv)
 778 {
 779         drm_i915_private_t *dev_priv = dev->dev_private;
 780         drm_i915_setparam_t *param = data;
 781
 782         if (!dev_priv) {
 783                 DRM_ERROR("called with no initialization\n");
 784                 return -EINVAL;
 785         }
 786
 787         switch (param->param) {
 788         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 789                 break;
 790         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 791                 dev_priv->tex_lru_log_granularity = param->value;
 792                 break;
 793         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 794                 dev_priv->allow_batchbuffer = param->value;
 795                 break;
 796         case I915_SETPARAM_NUM_USED_FENCES:
 797                 if (param->value > dev_priv->num_fence_regs ||
 798                     param->value < 0)
 799                         return -EINVAL;
 800                 /* Userspace can use first N regs */
 801                 dev_priv->fence_reg_start = param->value;
 802                 break;
 803         default:
 804                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 805                                         param->param);
 806                 return -EINVAL;
 807         }
 808
 809         return 0;
 810 }
 811
 812 static int i915_set_status_page(struct drm_device *dev, void *data,
 813                                 struct drm_file *file_priv)
 814 {
 815         drm_i915_private_t *dev_priv = dev->dev_private;
 816         drm_i915_hws_addr_t *hws = data;
 817         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 818
 819         if (!I915_NEED_GFX_HWS(dev))
 820                 return -EINVAL;
 821
 822         if (!dev_priv) {
 823                 DRM_ERROR("called with no initialization\n");
 824                 return -EINVAL;
 825         }
 826
 827         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 828                 WARN(1, "tried to set status page when mode setting active\n");
 829                 return 0;
 830         }
 831
 832         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 833
 834         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 835
 836         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 837         dev_priv->hws_map.size = 4*1024;
 838         dev_priv->hws_map.type = 0;
 839         dev_priv->hws_map.flags = 0;
 840         dev_priv->hws_map.mtrr = 0;
 841
 842         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 843         if (dev_priv->hws_map.handle == NULL) {
 844                 i915_dma_cleanup(dev);
 845                 ring->status_page.gfx_addr = 0;
 846                 DRM_ERROR("can not ioremap virtual address for"
 847                                 " G33 hw status page\n");
 848                 return -ENOMEM;
 849         }
 850         ring->status_page.page_addr = dev_priv->hws_map.handle;
 851         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 852         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 853
 854         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 855                          ring->status_page.gfx_addr);
 856         DRM_DEBUG_DRIVER("load hws at %p\n",
 857                          ring->status_page.page_addr);
 858         return 0;
 859 }
 860
 861 static int i915_get_bridge_dev(struct drm_device *dev)
 862 {
 863         struct drm_i915_private *dev_priv = dev->dev_private;
 864
 865         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 866         if (!dev_priv->bridge_dev) {
 867                 DRM_ERROR("bridge device not found\n");
 868                 return -1;
 869         }
 870         return 0;
 871 }
 872
 873 #define MCHBAR_I915 0x44
 874 #define MCHBAR_I965 0x48
 875 #define MCHBAR_SIZE (4*4096)
 876
 877 #define DEVEN_REG 0x54
 878 #define   DEVEN_MCHBAR_EN (1 << 28)
 879
 880 /* Allocate space for the MCH regs if needed, return nonzero on error */
 881 static int
 882 intel_alloc_mchbar_resource(struct drm_device *dev)
 883 {
 884         drm_i915_private_t *dev_priv = dev->dev_private;
 885         int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 886         u32 temp_lo, temp_hi = 0;
 887         u64 mchbar_addr;
 888         int ret = 0;
 889
 890         if (IS_I965G(dev))
 891                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 892         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 893         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 894
 895         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 896 #ifdef CONFIG_PNP
 897         if (mchbar_addr &&
 898             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
 899                 ret = 0;
 900                 goto out;
 901         }
 902 #endif
 903
 904         /* Get some space for it */
 905         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
 906                                      MCHBAR_SIZE, MCHBAR_SIZE,
 907                                      PCIBIOS_MIN_MEM,
 908                                      0,   pcibios_align_resource,
 909                                      dev_priv->bridge_dev);
 910         if (ret) {
 911                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 912                 dev_priv->mch_res.start = 0;
 913                 goto out;
 914         }
 915
 916         if (IS_I965G(dev))
 917                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 918                                        upper_32_bits(dev_priv->mch_res.start));
 919
 920         pci_write_config_dword(dev_priv->bridge_dev, reg,
 921                                lower_32_bits(dev_priv->mch_res.start));
 922 out:
 923         return ret;
 924 }
 925
 926 /* Setup MCHBAR if possible, return true if we should disable it again */
 927 static void
 928 intel_setup_mchbar(struct drm_device *dev)
 929 {
 930         drm_i915_private_t *dev_priv = dev->dev_private;
 931         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 932         u32 temp;
 933         bool enabled;
 934
 935         dev_priv->mchbar_need_disable = false;
 936
 937         if (IS_I915G(dev) || IS_I915GM(dev)) {
 938                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 939                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 940         } else {
 941                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 942                 enabled = temp & 1;
 943         }
 944
 945         /* If it's already enabled, don't have to do anything */
 946         if (enabled)
 947                 return;
 948
 949         if (intel_alloc_mchbar_resource(dev))
 950                 return;
 951
 952         dev_priv->mchbar_need_disable = true;
 953
 954         /* Space is allocated or reserved, so enable it. */
 955         if (IS_I915G(dev) || IS_I915GM(dev)) {
 956                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 957                                        temp | DEVEN_MCHBAR_EN);
 958         } else {
 959                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 960                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 961         }
 962 }
 963
 964 static void
 965 intel_teardown_mchbar(struct drm_device *dev)
 966 {
 967         drm_i915_private_t *dev_priv = dev->dev_private;
 968         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 969         u32 temp;
 970
 971         if (dev_priv->mchbar_need_disable) {
 972                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 973                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 974                         temp &= ~DEVEN_MCHBAR_EN;
 975                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 976                 } else {
 977                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 978                         temp &= ~1;
 979                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 980                 }
 981         }
 982
 983         if (dev_priv->mch_res.start)
 984                 release_resource(&dev_priv->mch_res);
 985 }
 986
 987 /**
 988  * i915_probe_agp - get AGP bootup configuration
 989  * @pdev: PCI device
 990  * @aperture_size: returns AGP aperture configured size
 991  * @preallocated_size: returns size of BIOS preallocated AGP space
 992  *
 993  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 994  * some RAM for the framebuffer at early boot.  This code figures out
 995  * how much was set aside so we can use it for our own purposes.
 996  */
 997 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 998                           uint32_t *preallocated_size,
 999                           uint32_t *start)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002         u16 tmp = 0;
1003         unsigned long overhead;
1004         unsigned long stolen;
1005
1006         /* Get the fb aperture size and "stolen" memory amount. */
1007         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
1008
1009         *aperture_size = 1024 * 1024;
1010         *preallocated_size = 1024 * 1024;
1011
1012         switch (dev->pdev->device) {
1013         case PCI_DEVICE_ID_INTEL_82830_CGC:
1014         case PCI_DEVICE_ID_INTEL_82845G_IG:
1015         case PCI_DEVICE_ID_INTEL_82855GM_IG:
1016         case PCI_DEVICE_ID_INTEL_82865_IG:
1017                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1018                         *aperture_size *= 64;
1019                 else
1020                         *aperture_size *= 128;
1021                 break;
1022         default:
1023                 /* 9xx supports large sizes, just look at the length */
1024                 *aperture_size = pci_resource_len(dev->pdev, 2);
1025                 break;
1026         }
1027
1028         /*
1029          * Some of the preallocated space is taken by the GTT
1030          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
1031          */
1032         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1033                 overhead = 4096;
1034         else
1035                 overhead = (*aperture_size / 1024) + 4096;
1036
1037         if (IS_GEN6(dev)) {
1038                 /* SNB has memory control reg at 0x50.w */
1039                 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1040
1041                 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1042                 case INTEL_855_GMCH_GMS_DISABLED:
1043                         DRM_ERROR("video memory is disabled\n");
1044                         return -1;
1045                 case SNB_GMCH_GMS_STOLEN_32M:
1046                         stolen = 32 * 1024 * 1024;
1047                         break;
1048                 case SNB_GMCH_GMS_STOLEN_64M:
1049                         stolen = 64 * 1024 * 1024;
1050                         break;
1051                 case SNB_GMCH_GMS_STOLEN_96M:
1052                         stolen = 96 * 1024 * 1024;
1053                         break;
1054                 case SNB_GMCH_GMS_STOLEN_128M:
1055                         stolen = 128 * 1024 * 1024;
1056                         break;
1057                 case SNB_GMCH_GMS_STOLEN_160M:
1058                         stolen = 160 * 1024 * 1024;
1059                         break;
1060                 case SNB_GMCH_GMS_STOLEN_192M:
1061                         stolen = 192 * 1024 * 1024;
1062                         break;
1063                 case SNB_GMCH_GMS_STOLEN_224M:
1064                         stolen = 224 * 1024 * 1024;
1065                         break;
1066                 case SNB_GMCH_GMS_STOLEN_256M:
1067                         stolen = 256 * 1024 * 1024;
1068                         break;
1069                 case SNB_GMCH_GMS_STOLEN_288M:
1070                         stolen = 288 * 1024 * 1024;
1071                         break;
1072                 case SNB_GMCH_GMS_STOLEN_320M:
1073                         stolen = 320 * 1024 * 1024;
1074                         break;
1075                 case SNB_GMCH_GMS_STOLEN_352M:
1076                         stolen = 352 * 1024 * 1024;
1077                         break;
1078                 case SNB_GMCH_GMS_STOLEN_384M:
1079                         stolen = 384 * 1024 * 1024;
1080                         break;
1081                 case SNB_GMCH_GMS_STOLEN_416M:
1082                         stolen = 416 * 1024 * 1024;
1083                         break;
1084                 case SNB_GMCH_GMS_STOLEN_448M:
1085                         stolen = 448 * 1024 * 1024;
1086                         break;
1087                 case SNB_GMCH_GMS_STOLEN_480M:
1088                         stolen = 480 * 1024 * 1024;
1089                         break;
1090                 case SNB_GMCH_GMS_STOLEN_512M:
1091                         stolen = 512 * 1024 * 1024;
1092                         break;
1093                 default:
1094                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1095                                   tmp & SNB_GMCH_GMS_STOLEN_MASK);
1096                         return -1;
1097                 }
1098         } else {
1099                 switch (tmp & INTEL_GMCH_GMS_MASK) {
1100                 case INTEL_855_GMCH_GMS_DISABLED:
1101                         DRM_ERROR("video memory is disabled\n");
1102                         return -1;
1103                 case INTEL_855_GMCH_GMS_STOLEN_1M:
1104                         stolen = 1 * 1024 * 1024;
1105                         break;
1106                 case INTEL_855_GMCH_GMS_STOLEN_4M:
1107                         stolen = 4 * 1024 * 1024;
1108                         break;
1109                 case INTEL_855_GMCH_GMS_STOLEN_8M:
1110                         stolen = 8 * 1024 * 1024;
1111                         break;
1112                 case INTEL_855_GMCH_GMS_STOLEN_16M:
1113                         stolen = 16 * 1024 * 1024;
1114                         break;
1115                 case INTEL_855_GMCH_GMS_STOLEN_32M:
1116                         stolen = 32 * 1024 * 1024;
1117                         break;
1118                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1119                         stolen = 48 * 1024 * 1024;
1120                         break;
1121                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1122                         stolen = 64 * 1024 * 1024;
1123                         break;
1124                 case INTEL_GMCH_GMS_STOLEN_128M:
1125                         stolen = 128 * 1024 * 1024;
1126                         break;
1127                 case INTEL_GMCH_GMS_STOLEN_256M:
1128                         stolen = 256 * 1024 * 1024;
1129                         break;
1130                 case INTEL_GMCH_GMS_STOLEN_96M:
1131                         stolen = 96 * 1024 * 1024;
1132                         break;
1133                 case INTEL_GMCH_GMS_STOLEN_160M:
1134                         stolen = 160 * 1024 * 1024;
1135                         break;
1136                 case INTEL_GMCH_GMS_STOLEN_224M:
1137                         stolen = 224 * 1024 * 1024;
1138                         break;
1139                 case INTEL_GMCH_GMS_STOLEN_352M:
1140                         stolen = 352 * 1024 * 1024;
1141                         break;
1142                 default:
1143                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1144                                   tmp & INTEL_GMCH_GMS_MASK);
1145                         return -1;
1146                 }
1147         }
1148
1149         *preallocated_size = stolen - overhead;
1150         *start = overhead;
1151
1152         return 0;
1153 }
1154
1155 #define PTE_ADDRESS_MASK                0xfffff000
1156 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1157 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1158 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1159 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1160 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1161 #define PTE_VALID                       (1 << 0)
1162
1163 /**
1164  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1165  * @dev: drm device
1166  * @gtt_addr: address to translate
1167  *
1168  * Some chip functions require allocations from stolen space but need the
1169  * physical address of the memory in question.  We use this routine
1170  * to get a physical address suitable for register programming from a given
1171  * GTT address.
1172  */
1173 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1174                                       unsigned long gtt_addr)
1175 {
1176         unsigned long *gtt;
1177         unsigned long entry, phys;
1178         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1179         int gtt_offset, gtt_size;
1180
1181         if (IS_I965G(dev)) {
1182                 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1183                         gtt_offset = 2*1024*1024;
1184                         gtt_size = 2*1024*1024;
1185                 } else {
1186                         gtt_offset = 512*1024;
1187                         gtt_size = 512*1024;
1188                 }
1189         } else {
1190                 gtt_bar = 3;
1191                 gtt_offset = 0;
1192                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1193         }
1194
1195         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1196                          gtt_size);
1197         if (!gtt) {
1198                 DRM_ERROR("ioremap of GTT failed\n");
1199                 return 0;
1200         }
1201
1202         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1203
1204         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1205
1206         /* Mask out these reserved bits on this hardware. */
1207         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1208             IS_I945G(dev) || IS_I945GM(dev)) {
1209                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1210         }
1211
1212         /* If it's not a mapping type we know, then bail. */
1213         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1214             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1215                 iounmap(gtt);
1216                 return 0;
1217         }
1218
1219         if (!(entry & PTE_VALID)) {
1220                 DRM_ERROR("bad GTT entry in stolen space\n");
1221                 iounmap(gtt);
1222                 return 0;
1223         }
1224
1225         iounmap(gtt);
1226
1227         phys =(entry & PTE_ADDRESS_MASK) |
1228                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1229
1230         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1231
1232         return phys;
1233 }
1234
1235 static void i915_warn_stolen(struct drm_device *dev)
1236 {
1237         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1238         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1239 }
1240
1241 static void i915_setup_compression(struct drm_device *dev, int size)
1242 {
1243         struct drm_i915_private *dev_priv = dev->dev_private;
1244         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1245         unsigned long cfb_base;
1246         unsigned long ll_base = 0;
1247
1248         /* Leave 1M for line length buffer & misc. */
1249         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1250         if (!compressed_fb) {
1251                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1252                 i915_warn_stolen(dev);
1253                 return;
1254         }
1255
1256         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1257         if (!compressed_fb) {
1258                 i915_warn_stolen(dev);
1259                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1260                 return;
1261         }
1262
1263         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1264         if (!cfb_base) {
1265                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1266                 drm_mm_put_block(compressed_fb);
1267         }
1268
1269         if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
1270                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1271                                                     4096, 0);
1272                 if (!compressed_llb) {
1273                         i915_warn_stolen(dev);
1274                         return;
1275                 }
1276
1277                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1278                 if (!compressed_llb) {
1279                         i915_warn_stolen(dev);
1280                         return;
1281                 }
1282
1283                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1284                 if (!ll_base) {
1285                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1286                         drm_mm_put_block(compressed_fb);
1287                         drm_mm_put_block(compressed_llb);
1288                 }
1289         }
1290
1291         dev_priv->cfb_size = size;
1292
1293         intel_disable_fbc(dev);
1294         dev_priv->compressed_fb = compressed_fb;
1295         if (IS_IRONLAKE_M(dev))
1296                 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1297         else if (IS_GM45(dev)) {
1298                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1299         } else {
1300                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1301                 I915_WRITE(FBC_LL_BASE, ll_base);
1302                 dev_priv->compressed_llb = compressed_llb;
1303         }
1304
1305         DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1306                   ll_base, size >> 20);
1307 }
1308
1309 static void i915_cleanup_compression(struct drm_device *dev)
1310 {
1311         struct drm_i915_private *dev_priv = dev->dev_private;
1312
1313         drm_mm_put_block(dev_priv->compressed_fb);
1314         if (dev_priv->compressed_llb)
1315                 drm_mm_put_block(dev_priv->compressed_llb);
1316 }
1317
1318 /* true = enable decode, false = disable decoder */
1319 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1320 {
1321         struct drm_device *dev = cookie;
1322
1323         intel_modeset_vga_set_state(dev, state);
1324         if (state)
1325                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1326                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1327         else
1328                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1329 }
1330
1331 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1332 {
1333         struct drm_device *dev = pci_get_drvdata(pdev);
1334         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1335         if (state == VGA_SWITCHEROO_ON) {
1336                 printk(KERN_INFO "i915: switched on\n");
1337                 /* i915 resume handler doesn't set to D0 */
1338                 pci_set_power_state(dev->pdev, PCI_D0);
1339                 i915_resume(dev);
1340                 drm_kms_helper_poll_enable(dev);
1341         } else {
1342                 printk(KERN_ERR "i915: switched off\n");
1343                 drm_kms_helper_poll_disable(dev);
1344                 i915_suspend(dev, pmm);
1345         }
1346 }
1347
1348 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1349 {
1350         struct drm_device *dev = pci_get_drvdata(pdev);
1351         bool can_switch;
1352
1353         spin_lock(&dev->count_lock);
1354         can_switch = (dev->open_count == 0);
1355         spin_unlock(&dev->count_lock);
1356         return can_switch;
1357 }
1358
1359 static int i915_load_modeset_init(struct drm_device *dev,
1360                                   unsigned long prealloc_start,
1361                                   unsigned long prealloc_size,
1362                                   unsigned long agp_size)
1363 {
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1366         int ret = 0;
1367
1368         dev->mode_config.fb_base = pci_resource_start(dev->pdev, fb_bar) &
1369                 0xff000000;
1370
1371         /* Basic memrange allocator for stolen space (aka vram) */
1372         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1373         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1374
1375         /* We're off and running w/KMS */
1376         dev_priv->mm.suspended = 0;
1377
1378         /* Let GEM Manage from end of prealloc space to end of aperture.
1379          *
1380          * However, leave one page at the end still bound to the scratch page.
1381          * There are a number of places where the hardware apparently
1382          * prefetches past the end of the object, and we've seen multiple
1383          * hangs with the GPU head pointer stuck in a batchbuffer bound
1384          * at the last page of the aperture.  One page should be enough to
1385          * keep any prefetching inside of the aperture.
1386          */
1387         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1388
1389         mutex_lock(&dev->struct_mutex);
1390         ret = i915_gem_init_ringbuffer(dev);
1391         mutex_unlock(&dev->struct_mutex);
1392         if (ret)
1393                 goto out;
1394
1395         /* Try to set up FBC with a reasonable compressed buffer size */
1396         if (I915_HAS_FBC(dev) && i915_powersave) {
1397                 int cfb_size;
1398
1399                 /* Try to get an 8M buffer... */
1400                 if (prealloc_size > (9*1024*1024))
1401                         cfb_size = 8*1024*1024;
1402                 else /* fall back to 7/8 of the stolen space */
1403                         cfb_size = prealloc_size * 7 / 8;
1404                 i915_setup_compression(dev, cfb_size);
1405         }
1406
1407         /* Allow hardware batchbuffers unless told otherwise.
1408          */
1409         dev_priv->allow_batchbuffer = 1;
1410
1411         ret = intel_init_bios(dev);
1412         if (ret)
1413                 DRM_INFO("failed to find VBIOS tables\n");
1414
1415         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1416         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1417         if (ret)
1418                 goto cleanup_ringbuffer;
1419
1420         ret = vga_switcheroo_register_client(dev->pdev,
1421                                              i915_switcheroo_set_state,
1422                                              i915_switcheroo_can_switch);
1423         if (ret)
1424                 goto cleanup_vga_client;
1425
1426         /* IIR "flip pending" bit means done if this bit is set */
1427         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1428                 dev_priv->flip_pending_is_done = true;
1429
1430         intel_modeset_init(dev);
1431
1432         ret = drm_irq_install(dev);
1433         if (ret)
1434                 goto cleanup_vga_switcheroo;
1435
1436         /* Always safe in the mode setting case. */
1437         /* FIXME: do pre/post-mode set stuff in core KMS code */
1438         dev->vblank_disable_allowed = 1;
1439
1440         /*
1441          * Initialize the hardware status page IRQ location.
1442          */
1443
1444         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1445
1446         ret = intel_fbdev_init(dev);
1447         if (ret)
1448                 goto cleanup_irq;
1449
1450         drm_kms_helper_poll_init(dev);
1451         return 0;
1452
1453 cleanup_irq:
1454         drm_irq_uninstall(dev);
1455 cleanup_vga_switcheroo:
1456         vga_switcheroo_unregister_client(dev->pdev);
1457 cleanup_vga_client:
1458         vga_client_register(dev->pdev, NULL, NULL, NULL);
1459 cleanup_ringbuffer:
1460         mutex_lock(&dev->struct_mutex);
1461         i915_gem_cleanup_ringbuffer(dev);
1462         mutex_unlock(&dev->struct_mutex);
1463 out:
1464         return ret;
1465 }
1466
1467 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1468 {
1469         struct drm_i915_master_private *master_priv;
1470
1471         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1472         if (!master_priv)
1473                 return -ENOMEM;
1474
1475         master->driver_priv = master_priv;
1476         return 0;
1477 }
1478
1479 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1480 {
1481         struct drm_i915_master_private *master_priv = master->driver_priv;
1482
1483         if (!master_priv)
1484                 return;
1485
1486         kfree(master_priv);
1487
1488         master->driver_priv = NULL;
1489 }
1490
1491 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1492 {
1493         drm_i915_private_t *dev_priv = dev->dev_private;
1494         u32 tmp;
1495
1496         tmp = I915_READ(CLKCFG);
1497
1498         switch (tmp & CLKCFG_FSB_MASK) {
1499         case CLKCFG_FSB_533:
1500                 dev_priv->fsb_freq = 533; /* 133*4 */
1501                 break;
1502         case CLKCFG_FSB_800:
1503                 dev_priv->fsb_freq = 800; /* 200*4 */
1504                 break;
1505         case CLKCFG_FSB_667:
1506                 dev_priv->fsb_freq =  667; /* 167*4 */
1507                 break;
1508         case CLKCFG_FSB_400:
1509                 dev_priv->fsb_freq = 400; /* 100*4 */
1510                 break;
1511         }
1512
1513         switch (tmp & CLKCFG_MEM_MASK) {
1514         case CLKCFG_MEM_533:
1515                 dev_priv->mem_freq = 533;
1516                 break;
1517         case CLKCFG_MEM_667:
1518                 dev_priv->mem_freq = 667;
1519                 break;
1520         case CLKCFG_MEM_800:
1521                 dev_priv->mem_freq = 800;
1522                 break;
1523         }
1524
1525         /* detect pineview DDR3 setting */
1526         tmp = I915_READ(CSHRDDR3CTL);
1527         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1528 }
1529
1530 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1531 {
1532         drm_i915_private_t *dev_priv = dev->dev_private;
1533         u16 ddrpll, csipll;
1534
1535         ddrpll = I915_READ16(DDRMPLL1);
1536         csipll = I915_READ16(CSIPLL0);
1537
1538         switch (ddrpll & 0xff) {
1539         case 0xc:
1540                 dev_priv->mem_freq = 800;
1541                 break;
1542         case 0x10:
1543                 dev_priv->mem_freq = 1066;
1544                 break;
1545         case 0x14:
1546                 dev_priv->mem_freq = 1333;
1547                 break;
1548         case 0x18:
1549                 dev_priv->mem_freq = 1600;
1550                 break;
1551         default:
1552                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1553                                  ddrpll & 0xff);
1554                 dev_priv->mem_freq = 0;
1555                 break;
1556         }
1557
1558         dev_priv->r_t = dev_priv->mem_freq;
1559
1560         switch (csipll & 0x3ff) {
1561         case 0x00c:
1562                 dev_priv->fsb_freq = 3200;
1563                 break;
1564         case 0x00e:
1565                 dev_priv->fsb_freq = 3733;
1566                 break;
1567         case 0x010:
1568                 dev_priv->fsb_freq = 4266;
1569                 break;
1570         case 0x012:
1571                 dev_priv->fsb_freq = 4800;
1572                 break;
1573         case 0x014:
1574                 dev_priv->fsb_freq = 5333;
1575                 break;
1576         case 0x016:
1577                 dev_priv->fsb_freq = 5866;
1578                 break;
1579         case 0x018:
1580                 dev_priv->fsb_freq = 6400;
1581                 break;
1582         default:
1583                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1584                                  csipll & 0x3ff);
1585                 dev_priv->fsb_freq = 0;
1586                 break;
1587         }
1588
1589         if (dev_priv->fsb_freq == 3200) {
1590                 dev_priv->c_m = 0;
1591         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1592                 dev_priv->c_m = 1;
1593         } else {
1594                 dev_priv->c_m = 2;
1595         }
1596 }
1597
1598 struct v_table {
1599         u8 vid;
1600         unsigned long vd; /* in .1 mil */
1601         unsigned long vm; /* in .1 mil */
1602         u8 pvid;
1603 };
1604
1605 static struct v_table v_table[] = {
1606         { 0, 16125, 15000, 0x7f, },
1607         { 1, 16000, 14875, 0x7e, },
1608         { 2, 15875, 14750, 0x7d, },
1609         { 3, 15750, 14625, 0x7c, },
1610         { 4, 15625, 14500, 0x7b, },
1611         { 5, 15500, 14375, 0x7a, },
1612         { 6, 15375, 14250, 0x79, },
1613         { 7, 15250, 14125, 0x78, },
1614         { 8, 15125, 14000, 0x77, },
1615         { 9, 15000, 13875, 0x76, },
1616         { 10, 14875, 13750, 0x75, },
1617         { 11, 14750, 13625, 0x74, },
1618         { 12, 14625, 13500, 0x73, },
1619         { 13, 14500, 13375, 0x72, },
1620         { 14, 14375, 13250, 0x71, },
1621         { 15, 14250, 13125, 0x70, },
1622         { 16, 14125, 13000, 0x6f, },
1623         { 17, 14000, 12875, 0x6e, },
1624         { 18, 13875, 12750, 0x6d, },
1625         { 19, 13750, 12625, 0x6c, },
1626         { 20, 13625, 12500, 0x6b, },
1627         { 21, 13500, 12375, 0x6a, },
1628         { 22, 13375, 12250, 0x69, },
1629         { 23, 13250, 12125, 0x68, },
1630         { 24, 13125, 12000, 0x67, },
1631         { 25, 13000, 11875, 0x66, },
1632         { 26, 12875, 11750, 0x65, },
1633         { 27, 12750, 11625, 0x64, },
1634         { 28, 12625, 11500, 0x63, },
1635         { 29, 12500, 11375, 0x62, },
1636         { 30, 12375, 11250, 0x61, },
1637         { 31, 12250, 11125, 0x60, },
1638         { 32, 12125, 11000, 0x5f, },
1639         { 33, 12000, 10875, 0x5e, },
1640         { 34, 11875, 10750, 0x5d, },
1641         { 35, 11750, 10625, 0x5c, },
1642         { 36, 11625, 10500, 0x5b, },
1643         { 37, 11500, 10375, 0x5a, },
1644         { 38, 11375, 10250, 0x59, },
1645         { 39, 11250, 10125, 0x58, },
1646         { 40, 11125, 10000, 0x57, },
1647         { 41, 11000, 9875, 0x56, },
1648         { 42, 10875, 9750, 0x55, },
1649         { 43, 10750, 9625, 0x54, },
1650         { 44, 10625, 9500, 0x53, },
1651         { 45, 10500, 9375, 0x52, },
1652         { 46, 10375, 9250, 0x51, },
1653         { 47, 10250, 9125, 0x50, },
1654         { 48, 10125, 9000, 0x4f, },
1655         { 49, 10000, 8875, 0x4e, },
1656         { 50, 9875, 8750, 0x4d, },
1657         { 51, 9750, 8625, 0x4c, },
1658         { 52, 9625, 8500, 0x4b, },
1659         { 53, 9500, 8375, 0x4a, },
1660         { 54, 9375, 8250, 0x49, },
1661         { 55, 9250, 8125, 0x48, },
1662         { 56, 9125, 8000, 0x47, },
1663         { 57, 9000, 7875, 0x46, },
1664         { 58, 8875, 7750, 0x45, },
1665         { 59, 8750, 7625, 0x44, },
1666         { 60, 8625, 7500, 0x43, },
1667         { 61, 8500, 7375, 0x42, },
1668         { 62, 8375, 7250, 0x41, },
1669         { 63, 8250, 7125, 0x40, },
1670         { 64, 8125, 7000, 0x3f, },
1671         { 65, 8000, 6875, 0x3e, },
1672         { 66, 7875, 6750, 0x3d, },
1673         { 67, 7750, 6625, 0x3c, },
1674         { 68, 7625, 6500, 0x3b, },
1675         { 69, 7500, 6375, 0x3a, },
1676         { 70, 7375, 6250, 0x39, },
1677         { 71, 7250, 6125, 0x38, },
1678         { 72, 7125, 6000, 0x37, },
1679         { 73, 7000, 5875, 0x36, },
1680         { 74, 6875, 5750, 0x35, },
1681         { 75, 6750, 5625, 0x34, },
1682         { 76, 6625, 5500, 0x33, },
1683         { 77, 6500, 5375, 0x32, },
1684         { 78, 6375, 5250, 0x31, },
1685         { 79, 6250, 5125, 0x30, },
1686         { 80, 6125, 5000, 0x2f, },
1687         { 81, 6000, 4875, 0x2e, },
1688         { 82, 5875, 4750, 0x2d, },
1689         { 83, 5750, 4625, 0x2c, },
1690         { 84, 5625, 4500, 0x2b, },
1691         { 85, 5500, 4375, 0x2a, },
1692         { 86, 5375, 4250, 0x29, },
1693         { 87, 5250, 4125, 0x28, },
1694         { 88, 5125, 4000, 0x27, },
1695         { 89, 5000, 3875, 0x26, },
1696         { 90, 4875, 3750, 0x25, },
1697         { 91, 4750, 3625, 0x24, },
1698         { 92, 4625, 3500, 0x23, },
1699         { 93, 4500, 3375, 0x22, },
1700         { 94, 4375, 3250, 0x21, },
1701         { 95, 4250, 3125, 0x20, },
1702         { 96, 4125, 3000, 0x1f, },
1703         { 97, 4125, 3000, 0x1e, },
1704         { 98, 4125, 3000, 0x1d, },
1705         { 99, 4125, 3000, 0x1c, },
1706         { 100, 4125, 3000, 0x1b, },
1707         { 101, 4125, 3000, 0x1a, },
1708         { 102, 4125, 3000, 0x19, },
1709         { 103, 4125, 3000, 0x18, },
1710         { 104, 4125, 3000, 0x17, },
1711         { 105, 4125, 3000, 0x16, },
1712         { 106, 4125, 3000, 0x15, },
1713         { 107, 4125, 3000, 0x14, },
1714         { 108, 4125, 3000, 0x13, },
1715         { 109, 4125, 3000, 0x12, },
1716         { 110, 4125, 3000, 0x11, },
1717         { 111, 4125, 3000, 0x10, },
1718         { 112, 4125, 3000, 0x0f, },
1719         { 113, 4125, 3000, 0x0e, },
1720         { 114, 4125, 3000, 0x0d, },
1721         { 115, 4125, 3000, 0x0c, },
1722         { 116, 4125, 3000, 0x0b, },
1723         { 117, 4125, 3000, 0x0a, },
1724         { 118, 4125, 3000, 0x09, },
1725         { 119, 4125, 3000, 0x08, },
1726         { 120, 1125, 0, 0x07, },
1727         { 121, 1000, 0, 0x06, },
1728         { 122, 875, 0, 0x05, },
1729         { 123, 750, 0, 0x04, },
1730         { 124, 625, 0, 0x03, },
1731         { 125, 500, 0, 0x02, },
1732         { 126, 375, 0, 0x01, },
1733         { 127, 0, 0, 0x00, },
1734 };
1735
1736 struct cparams {
1737         int i;
1738         int t;
1739         int m;
1740         int c;
1741 };
1742
1743 static struct cparams cparams[] = {
1744         { 1, 1333, 301, 28664 },
1745         { 1, 1066, 294, 24460 },
1746         { 1, 800, 294, 25192 },
1747         { 0, 1333, 276, 27605 },
1748         { 0, 1066, 276, 27605 },
1749         { 0, 800, 231, 23784 },
1750 };
1751
1752 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1753 {
1754         u64 total_count, diff, ret;
1755         u32 count1, count2, count3, m = 0, c = 0;
1756         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1757         int i;
1758
1759         diff1 = now - dev_priv->last_time1;
1760
1761         count1 = I915_READ(DMIEC);
1762         count2 = I915_READ(DDREC);
1763         count3 = I915_READ(CSIEC);
1764
1765         total_count = count1 + count2 + count3;
1766
1767         /* FIXME: handle per-counter overflow */
1768         if (total_count < dev_priv->last_count1) {
1769                 diff = ~0UL - dev_priv->last_count1;
1770                 diff += total_count;
1771         } else {
1772                 diff = total_count - dev_priv->last_count1;
1773         }
1774
1775         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1776                 if (cparams[i].i == dev_priv->c_m &&
1777                     cparams[i].t == dev_priv->r_t) {
1778                         m = cparams[i].m;
1779                         c = cparams[i].c;
1780                         break;
1781                 }
1782         }
1783
1784         div_u64(diff, diff1);
1785         ret = ((m * diff) + c);
1786         div_u64(ret, 10);
1787
1788         dev_priv->last_count1 = total_count;
1789         dev_priv->last_time1 = now;
1790
1791         return ret;
1792 }
1793
1794 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1795 {
1796         unsigned long m, x, b;
1797         u32 tsfs;
1798
1799         tsfs = I915_READ(TSFS);
1800
1801         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1802         x = I915_READ8(TR1);
1803
1804         b = tsfs & TSFS_INTR_MASK;
1805
1806         return ((m * x) / 127) - b;
1807 }
1808
1809 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1810 {
1811         unsigned long val = 0;
1812         int i;
1813
1814         for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1815                 if (v_table[i].pvid == pxvid) {
1816                         if (IS_MOBILE(dev_priv->dev))
1817                                 val = v_table[i].vm;
1818                         else
1819                                 val = v_table[i].vd;
1820                 }
1821         }
1822
1823         return val;
1824 }
1825
1826 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1827 {
1828         struct timespec now, diff1;
1829         u64 diff;
1830         unsigned long diffms;
1831         u32 count;
1832
1833         getrawmonotonic(&now);
1834         diff1 = timespec_sub(now, dev_priv->last_time2);
1835
1836         /* Don't divide by 0 */
1837         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1838         if (!diffms)
1839                 return;
1840
1841         count = I915_READ(GFXEC);
1842
1843         if (count < dev_priv->last_count2) {
1844                 diff = ~0UL - dev_priv->last_count2;
1845                 diff += count;
1846         } else {
1847                 diff = count - dev_priv->last_count2;
1848         }
1849
1850         dev_priv->last_count2 = count;
1851         dev_priv->last_time2 = now;
1852
1853         /* More magic constants... */
1854         diff = diff * 1181;
1855         div_u64(diff, diffms * 10);
1856         dev_priv->gfx_power = diff;
1857 }
1858
1859 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1860 {
1861         unsigned long t, corr, state1, corr2, state2;
1862         u32 pxvid, ext_v;
1863
1864         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1865         pxvid = (pxvid >> 24) & 0x7f;
1866         ext_v = pvid_to_extvid(dev_priv, pxvid);
1867
1868         state1 = ext_v;
1869
1870         t = i915_mch_val(dev_priv);
1871
1872         /* Revel in the empirically derived constants */
1873
1874         /* Correction factor in 1/100000 units */
1875         if (t > 80)
1876                 corr = ((t * 2349) + 135940);
1877         else if (t >= 50)
1878                 corr = ((t * 964) + 29317);
1879         else /* < 50 */
1880                 corr = ((t * 301) + 1004);
1881
1882         corr = corr * ((150142 * state1) / 10000 - 78642);
1883         corr /= 100000;
1884         corr2 = (corr * dev_priv->corr);
1885
1886         state2 = (corr2 * state1) / 10000;
1887         state2 /= 100; /* convert to mW */
1888
1889         i915_update_gfx_val(dev_priv);
1890
1891         return dev_priv->gfx_power + state2;
1892 }
1893
1894 /* Global for IPS driver to get at the current i915 device */
1895 static struct drm_i915_private *i915_mch_dev;
1896 /*
1897  * Lock protecting IPS related data structures
1898  *   - i915_mch_dev
1899  *   - dev_priv->max_delay
1900  *   - dev_priv->min_delay
1901  *   - dev_priv->fmax
1902  *   - dev_priv->gpu_busy
1903  */
1904 DEFINE_SPINLOCK(mchdev_lock);
1905
1906 /**
1907  * i915_read_mch_val - return value for IPS use
1908  *
1909  * Calculate and return a value for the IPS driver to use when deciding whether
1910  * we have thermal and power headroom to increase CPU or GPU power budget.
1911  */
1912 unsigned long i915_read_mch_val(void)
1913 {
1914         struct drm_i915_private *dev_priv;
1915         unsigned long chipset_val, graphics_val, ret = 0;
1916
1917         spin_lock(&mchdev_lock);
1918         if (!i915_mch_dev)
1919                 goto out_unlock;
1920         dev_priv = i915_mch_dev;
1921
1922         chipset_val = i915_chipset_val(dev_priv);
1923         graphics_val = i915_gfx_val(dev_priv);
1924
1925         ret = chipset_val + graphics_val;
1926
1927 out_unlock:
1928         spin_unlock(&mchdev_lock);
1929
1930         return ret;
1931 }
1932 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1933
1934 /**
1935  * i915_gpu_raise - raise GPU frequency limit
1936  *
1937  * Raise the limit; IPS indicates we have thermal headroom.
1938  */
1939 bool i915_gpu_raise(void)
1940 {
1941         struct drm_i915_private *dev_priv;
1942         bool ret = true;
1943
1944         spin_lock(&mchdev_lock);
1945         if (!i915_mch_dev) {
1946                 ret = false;
1947                 goto out_unlock;
1948         }
1949         dev_priv = i915_mch_dev;
1950
1951         if (dev_priv->max_delay > dev_priv->fmax)
1952                 dev_priv->max_delay--;
1953
1954 out_unlock:
1955         spin_unlock(&mchdev_lock);
1956
1957         return ret;
1958 }
1959 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1960
1961 /**
1962  * i915_gpu_lower - lower GPU frequency limit
1963  *
1964  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1965  * frequency maximum.
1966  */
1967 bool i915_gpu_lower(void)
1968 {
1969         struct drm_i915_private *dev_priv;
1970         bool ret = true;
1971
1972         spin_lock(&mchdev_lock);
1973         if (!i915_mch_dev) {
1974                 ret = false;
1975                 goto out_unlock;
1976         }
1977         dev_priv = i915_mch_dev;
1978
1979         if (dev_priv->max_delay < dev_priv->min_delay)
1980                 dev_priv->max_delay++;
1981
1982 out_unlock:
1983         spin_unlock(&mchdev_lock);
1984
1985         return ret;
1986 }
1987 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1988
1989 /**
1990  * i915_gpu_busy - indicate GPU business to IPS
1991  *
1992  * Tell the IPS driver whether or not the GPU is busy.
1993  */
1994 bool i915_gpu_busy(void)
1995 {
1996         struct drm_i915_private *dev_priv;
1997         bool ret = false;
1998
1999         spin_lock(&mchdev_lock);
2000         if (!i915_mch_dev)
2001                 goto out_unlock;
2002         dev_priv = i915_mch_dev;
2003
2004         ret = dev_priv->busy;
2005
2006 out_unlock:
2007         spin_unlock(&mchdev_lock);
2008
2009         return ret;
2010 }
2011 EXPORT_SYMBOL_GPL(i915_gpu_busy);
2012
2013 /**
2014  * i915_gpu_turbo_disable - disable graphics turbo
2015  *
2016  * Disable graphics turbo by resetting the max frequency and setting the
2017  * current frequency to the default.
2018  */
2019 bool i915_gpu_turbo_disable(void)
2020 {
2021         struct drm_i915_private *dev_priv;
2022         bool ret = true;
2023
2024         spin_lock(&mchdev_lock);
2025         if (!i915_mch_dev) {
2026                 ret = false;
2027                 goto out_unlock;
2028         }
2029         dev_priv = i915_mch_dev;
2030
2031         dev_priv->max_delay = dev_priv->fstart;
2032
2033         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2034                 ret = false;
2035
2036 out_unlock:
2037         spin_unlock(&mchdev_lock);
2038
2039         return ret;
2040 }
2041 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2042
2043 /**
2044  * i915_driver_load - setup chip and create an initial config
2045  * @dev: DRM device
2046  * @flags: startup flags
2047  *
2048  * The driver load routine has to do several things:
2049  *   - drive output discovery via intel_modeset_init()
2050  *   - initialize the memory manager
2051  *   - allocate initial config memory
2052  *   - setup the DRM framebuffer with the allocated memory
2053  */
2054 int i915_driver_load(struct drm_device *dev, unsigned long flags)
2055 {
2056         struct drm_i915_private *dev_priv;
2057         resource_size_t base, size;
2058         int ret = 0, mmio_bar;
2059         uint32_t agp_size, prealloc_size, prealloc_start;
2060         /* i915 has 4 more counters */
2061         dev->counters += 4;
2062         dev->types[6] = _DRM_STAT_IRQ;
2063         dev->types[7] = _DRM_STAT_PRIMARY;
2064         dev->types[8] = _DRM_STAT_SECONDARY;
2065         dev->types[9] = _DRM_STAT_DMA;
2066
2067         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
2068         if (dev_priv == NULL)
2069                 return -ENOMEM;
2070
2071         dev->dev_private = (void *)dev_priv;
2072         dev_priv->dev = dev;
2073         dev_priv->info = (struct intel_device_info *) flags;
2074
2075         /* Add register map (needed for suspend/resume) */
2076         mmio_bar = IS_I9XX(dev) ? 0 : 1;
2077         base = pci_resource_start(dev->pdev, mmio_bar);
2078         size = pci_resource_len(dev->pdev, mmio_bar);
2079
2080         if (i915_get_bridge_dev(dev)) {
2081                 ret = -EIO;
2082                 goto free_priv;
2083         }
2084
2085         dev_priv->regs = ioremap(base, size);
2086         if (!dev_priv->regs) {
2087                 DRM_ERROR("failed to map registers\n");
2088                 ret = -EIO;
2089                 goto put_bridge;
2090         }
2091
2092         dev_priv->mm.gtt_mapping =
2093                 io_mapping_create_wc(dev->agp->base,
2094                                      dev->agp->agp_info.aper_size * 1024*1024);
2095         if (dev_priv->mm.gtt_mapping == NULL) {
2096                 ret = -EIO;
2097                 goto out_rmmap;
2098         }
2099
2100         /* Set up a WC MTRR for non-PAT systems.  This is more common than
2101          * one would think, because the kernel disables PAT on first
2102          * generation Core chips because WC PAT gets overridden by a UC
2103          * MTRR if present.  Even if a UC MTRR isn't present.
2104          */
2105         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2106                                          dev->agp->agp_info.aper_size *
2107                                          1024 * 1024,
2108                                          MTRR_TYPE_WRCOMB, 1);
2109         if (dev_priv->mm.gtt_mtrr < 0) {
2110                 DRM_INFO("MTRR allocation failed.  Graphics "
2111                          "performance may suffer.\n");
2112         }
2113
2114         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
2115         if (ret)
2116                 goto out_iomapfree;
2117
2118         if (prealloc_size > intel_max_stolen) {
2119                 DRM_INFO("detected %dM stolen memory, trimming to %dM\n",
2120                          prealloc_size >> 20, intel_max_stolen >> 20);
2121                 prealloc_size = intel_max_stolen;
2122         }
2123
2124         dev_priv->wq = create_singlethread_workqueue("i915");
2125         if (dev_priv->wq == NULL) {
2126                 DRM_ERROR("Failed to create our workqueue.\n");
2127                 ret = -ENOMEM;
2128                 goto out_iomapfree;
2129         }
2130
2131         /* enable GEM by default */
2132         dev_priv->has_gem = 1;
2133
2134         if (prealloc_size > agp_size * 3 / 4) {
2135                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2136                           "memory stolen.\n",
2137                           prealloc_size / 1024, agp_size / 1024);
2138                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2139                           "updating the BIOS to fix).\n");
2140                 dev_priv->has_gem = 0;
2141         }
2142
2143         if (dev_priv->has_gem == 0 &&
2144             drm_core_check_feature(dev, DRIVER_MODESET)) {
2145                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2146                 ret = -ENODEV;
2147                 goto out_iomapfree;
2148         }
2149
2150         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2151         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2152         if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
2153                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2154                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2155         }
2156
2157         /* Try to make sure MCHBAR is enabled before poking at it */
2158         intel_setup_mchbar(dev);
2159
2160         i915_gem_load(dev);
2161
2162         /* Init HWS */
2163         if (!I915_NEED_GFX_HWS(dev)) {
2164                 ret = i915_init_phys_hws(dev);
2165                 if (ret != 0)
2166                         goto out_workqueue_free;
2167         }
2168
2169         if (IS_PINEVIEW(dev))
2170                 i915_pineview_get_mem_freq(dev);
2171         else if (IS_IRONLAKE(dev))
2172                 i915_ironlake_get_mem_freq(dev);
2173
2174         /* On the 945G/GM, the chipset reports the MSI capability on the
2175          * integrated graphics even though the support isn't actually there
2176          * according to the published specs.  It doesn't appear to function
2177          * correctly in testing on 945G.
2178          * This may be a side effect of MSI having been made available for PEG
2179          * and the registers being closely associated.
2180          *
2181          * According to chipset errata, on the 965GM, MSI interrupts may
2182          * be lost or delayed, but we use them anyways to avoid
2183          * stuck interrupts on some machines.
2184          */
2185         if (!IS_I945G(dev) && !IS_I945GM(dev))
2186                 pci_enable_msi(dev->pdev);
2187
2188         spin_lock_init(&dev_priv->user_irq_lock);
2189         spin_lock_init(&dev_priv->error_lock);
2190         dev_priv->trace_irq_seqno = 0;
2191
2192         ret = drm_vblank_init(dev, I915_NUM_PIPE);
2193
2194         if (ret) {
2195                 (void) i915_driver_unload(dev);
2196                 return ret;
2197         }
2198
2199         /* Start out suspended */
2200         dev_priv->mm.suspended = 1;
2201
2202         intel_detect_pch(dev);
2203
2204         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2205                 ret = i915_load_modeset_init(dev, prealloc_start,
2206                                              prealloc_size, agp_size);
2207                 if (ret < 0) {
2208                         DRM_ERROR("failed to init modeset\n");
2209                         goto out_workqueue_free;
2210                 }
2211         }
2212
2213         /* Must be done after probing outputs */
2214         intel_opregion_init(dev, 0);
2215
2216         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2217                     (unsigned long) dev);
2218
2219         spin_lock(&mchdev_lock);
2220         i915_mch_dev = dev_priv;
2221         dev_priv->mchdev_lock = &mchdev_lock;
2222         spin_unlock(&mchdev_lock);
2223
2224         return 0;
2225
2226 out_workqueue_free:
2227         destroy_workqueue(dev_priv->wq);
2228 out_iomapfree:
2229         io_mapping_free(dev_priv->mm.gtt_mapping);
2230 out_rmmap:
2231         iounmap(dev_priv->regs);
2232 put_bridge:
2233         pci_dev_put(dev_priv->bridge_dev);
2234 free_priv:
2235         kfree(dev_priv);
2236         return ret;
2237 }
2238
2239 int i915_driver_unload(struct drm_device *dev)
2240 {
2241         struct drm_i915_private *dev_priv = dev->dev_private;
2242
2243         i915_destroy_error_state(dev);
2244
2245         spin_lock(&mchdev_lock);
2246         i915_mch_dev = NULL;
2247         spin_unlock(&mchdev_lock);
2248
2249         destroy_workqueue(dev_priv->wq);
2250         del_timer_sync(&dev_priv->hangcheck_timer);
2251
2252         io_mapping_free(dev_priv->mm.gtt_mapping);
2253         if (dev_priv->mm.gtt_mtrr >= 0) {
2254                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2255                          dev->agp->agp_info.aper_size * 1024 * 1024);
2256                 dev_priv->mm.gtt_mtrr = -1;
2257         }
2258
2259         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2260                 intel_modeset_cleanup(dev);
2261
2262                 /*
2263                  * free the memory space allocated for the child device
2264                  * config parsed from VBT
2265                  */
2266                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2267                         kfree(dev_priv->child_dev);
2268                         dev_priv->child_dev = NULL;
2269                         dev_priv->child_dev_num = 0;
2270                 }
2271                 drm_irq_uninstall(dev);
2272                 vga_switcheroo_unregister_client(dev->pdev);
2273                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2274         }
2275
2276         if (dev->pdev->msi_enabled)
2277                 pci_disable_msi(dev->pdev);
2278
2279         if (dev_priv->regs != NULL)
2280                 iounmap(dev_priv->regs);
2281
2282         intel_opregion_free(dev, 0);
2283
2284         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2285                 i915_gem_free_all_phys_object(dev);
2286
2287                 mutex_lock(&dev->struct_mutex);
2288                 i915_gem_cleanup_ringbuffer(dev);
2289                 mutex_unlock(&dev->struct_mutex);
2290                 if (I915_HAS_FBC(dev) && i915_powersave)
2291                         i915_cleanup_compression(dev);
2292                 drm_mm_takedown(&dev_priv->vram);
2293                 i915_gem_lastclose(dev);
2294
2295                 intel_cleanup_overlay(dev);
2296         }
2297
2298         intel_teardown_mchbar(dev);
2299
2300         pci_dev_put(dev_priv->bridge_dev);
2301         kfree(dev->dev_private);
2302
2303         return 0;
2304 }
2305
2306 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2307 {
2308         struct drm_i915_file_private *i915_file_priv;
2309
2310         DRM_DEBUG_DRIVER("\n");
2311         i915_file_priv = (struct drm_i915_file_private *)
2312             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
2313
2314         if (!i915_file_priv)
2315                 return -ENOMEM;
2316
2317         file_priv->driver_priv = i915_file_priv;
2318
2319         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
2320
2321         return 0;
2322 }
2323
2324 /**
2325  * i915_driver_lastclose - clean up after all DRM clients have exited
2326  * @dev: DRM device
2327  *
2328  * Take care of cleaning up after all DRM clients have exited.  In the
2329  * mode setting case, we want to restore the kernel's initial mode (just
2330  * in case the last client left us in a bad state).
2331  *
2332  * Additionally, in the non-mode setting case, we'll tear down the AGP
2333  * and DMA structures, since the kernel won't be using them, and clea
2334  * up any GEM state.
2335  */
2336 void i915_driver_lastclose(struct drm_device * dev)
2337 {
2338         drm_i915_private_t *dev_priv = dev->dev_private;
2339
2340         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2341                 drm_fb_helper_restore();
2342                 vga_switcheroo_process_delayed_switch();
2343                 return;
2344         }
2345
2346         i915_gem_lastclose(dev);
2347
2348         if (dev_priv->agp_heap)
2349                 i915_mem_takedown(&(dev_priv->agp_heap));
2350
2351         i915_dma_cleanup(dev);
2352 }
2353
2354 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2355 {
2356         drm_i915_private_t *dev_priv = dev->dev_private;
2357         i915_gem_release(dev, file_priv);
2358         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2359                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2360 }
2361
2362 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2363 {
2364         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2365
2366         kfree(i915_file_priv);
2367 }
2368
2369 struct drm_ioctl_desc i915_ioctls[] = {
2370         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2371         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2372         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2373         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2374         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2375         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2376         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2377         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2378         DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2379         DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2380         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2381         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2382         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2383         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2384         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2385         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2386         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2387         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2388         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2389         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2390         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2391         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2392         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2393         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2394         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2395         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2396         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2397         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2398         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2399         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2400         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2401         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2402         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2403         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2404         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2405         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2406         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2407         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2408         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2409         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2410 };
2411
2412 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2413
2414 /**
2415  * Determine if the device really is AGP or not.
2416  *
2417  * All Intel graphics chipsets are treated as AGP, even if they are really
2418  * PCI-e.
2419  *
2420  * \param dev   The device to be tested.
2421  *
2422  * \returns
2423  * A value of 1 is always retured to indictate every i9x5 is AGP.
2424  */
2425 int i915_driver_device_is_agp(struct drm_device * dev)
2426 {
2427         return 1;
2428 }