2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
41 #include <asm/byteorder.h>
43 #include <asm/system.h>
45 #ifdef CONFIG_PPC_PMAC
46 #include <asm/pmac_feature.h>
52 #define DESCRIPTOR_OUTPUT_MORE 0
53 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
54 #define DESCRIPTOR_INPUT_MORE (2 << 12)
55 #define DESCRIPTOR_INPUT_LAST (3 << 12)
56 #define DESCRIPTOR_STATUS (1 << 11)
57 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
58 #define DESCRIPTOR_PING (1 << 7)
59 #define DESCRIPTOR_YY (1 << 6)
60 #define DESCRIPTOR_NO_IRQ (0 << 4)
61 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
62 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
63 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
64 #define DESCRIPTOR_WAIT (3 << 0)
70 __le32 branch_address;
72 __le16 transfer_status;
73 } __attribute__((aligned(16)));
75 #define CONTROL_SET(regs) (regs)
76 #define CONTROL_CLEAR(regs) ((regs) + 4)
77 #define COMMAND_PTR(regs) ((regs) + 12)
78 #define CONTEXT_MATCH(regs) ((regs) + 16)
81 struct descriptor descriptor;
82 struct ar_buffer *next;
88 struct ar_buffer *current_buffer;
89 struct ar_buffer *last_buffer;
92 struct tasklet_struct tasklet;
97 typedef int (*descriptor_callback_t)(struct context *ctx,
99 struct descriptor *last);
102 * A buffer that contains a block of DMA-able coherent memory used for
103 * storing a portion of a DMA descriptor program.
105 struct descriptor_buffer {
106 struct list_head list;
107 dma_addr_t buffer_bus;
110 struct descriptor buffer[0];
114 struct fw_ohci *ohci;
116 int total_allocation;
119 * List of page-sized buffers for storing DMA descriptors.
120 * Head of list contains buffers in use and tail of list contains
123 struct list_head buffer_list;
126 * Pointer to a buffer inside buffer_list that contains the tail
127 * end of the current DMA program.
129 struct descriptor_buffer *buffer_tail;
132 * The descriptor containing the branch address of the first
133 * descriptor that has not yet been filled by the device.
135 struct descriptor *last;
138 * The last descriptor in the DMA program. It contains the branch
139 * address that must be updated upon appending a new descriptor.
141 struct descriptor *prev;
143 descriptor_callback_t callback;
145 struct tasklet_struct tasklet;
148 #define IT_HEADER_SY(v) ((v) << 0)
149 #define IT_HEADER_TCODE(v) ((v) << 4)
150 #define IT_HEADER_CHANNEL(v) ((v) << 8)
151 #define IT_HEADER_TAG(v) ((v) << 14)
152 #define IT_HEADER_SPEED(v) ((v) << 16)
153 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
156 struct fw_iso_context base;
157 struct context context;
160 size_t header_length;
163 #define CONFIG_ROM_SIZE 1024
168 __iomem char *registers;
171 int request_generation; /* for timestamping incoming requests */
176 * Spinlock for accessing fw_ohci data. Never call out of
177 * this driver with this lock held.
181 struct ar_context ar_request_ctx;
182 struct ar_context ar_response_ctx;
183 struct context at_request_ctx;
184 struct context at_response_ctx;
187 struct iso_context *it_context_list;
188 u64 ir_context_channels;
190 struct iso_context *ir_context_list;
193 dma_addr_t config_rom_bus;
194 __be32 *next_config_rom;
195 dma_addr_t next_config_rom_bus;
199 dma_addr_t self_id_bus;
200 struct tasklet_struct bus_reset_tasklet;
202 u32 self_id_buffer[512];
205 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
207 return container_of(card, struct fw_ohci, card);
210 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
211 #define IR_CONTEXT_BUFFER_FILL 0x80000000
212 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
213 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
214 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
215 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
217 #define CONTEXT_RUN 0x8000
218 #define CONTEXT_WAKE 0x1000
219 #define CONTEXT_DEAD 0x0800
220 #define CONTEXT_ACTIVE 0x0400
222 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
223 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
224 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
226 #define OHCI1394_REGISTER_SIZE 0x800
227 #define OHCI_LOOP_COUNT 500
228 #define OHCI1394_PCI_HCI_Control 0x40
229 #define SELF_ID_BUF_SIZE 0x800
230 #define OHCI_TCODE_PHY_PACKET 0x0e
231 #define OHCI_VERSION_1_1 0x010010
233 static char ohci_driver_name[] = KBUILD_MODNAME;
235 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
236 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
238 #define QUIRK_CYCLE_TIMER 1
239 #define QUIRK_RESET_PACKET 2
240 #define QUIRK_BE_HEADERS 4
241 #define QUIRK_NO_1394A 8
242 #define QUIRK_NO_MSI 16
244 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
245 static const struct {
246 unsigned short vendor, device, flags;
248 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
251 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
252 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
253 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
254 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
255 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
256 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
259 /* This overrides anything that was found in ohci_quirks[]. */
260 static int param_quirks;
261 module_param_named(quirks, param_quirks, int, 0644);
262 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
263 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
264 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
265 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
266 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
267 ", disable MSI = " __stringify(QUIRK_NO_MSI)
270 #define OHCI_PARAM_DEBUG_AT_AR 1
271 #define OHCI_PARAM_DEBUG_SELFIDS 2
272 #define OHCI_PARAM_DEBUG_IRQS 4
273 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
275 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
277 static int param_debug;
278 module_param_named(debug, param_debug, int, 0644);
279 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
280 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
281 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
282 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
283 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
284 ", or a combination, or all = -1)");
286 static void log_irqs(u32 evt)
288 if (likely(!(param_debug &
289 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
292 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
293 !(evt & OHCI1394_busReset))
296 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
297 evt & OHCI1394_selfIDComplete ? " selfID" : "",
298 evt & OHCI1394_RQPkt ? " AR_req" : "",
299 evt & OHCI1394_RSPkt ? " AR_resp" : "",
300 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
301 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
302 evt & OHCI1394_isochRx ? " IR" : "",
303 evt & OHCI1394_isochTx ? " IT" : "",
304 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
305 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
306 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
307 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
308 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
309 evt & OHCI1394_busReset ? " busReset" : "",
310 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
311 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
312 OHCI1394_respTxComplete | OHCI1394_isochRx |
313 OHCI1394_isochTx | OHCI1394_postedWriteErr |
314 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
315 OHCI1394_cycleInconsistent |
316 OHCI1394_regAccessFail | OHCI1394_busReset)
320 static const char *speed[] = {
321 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
323 static const char *power[] = {
324 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
325 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
327 static const char port[] = { '.', '-', 'p', 'c', };
329 static char _p(u32 *s, int shift)
331 return port[*s >> shift & 3];
334 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
336 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
339 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
340 self_id_count, generation, node_id);
342 for (; self_id_count--; ++s)
343 if ((*s & 1 << 23) == 0)
344 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
345 "%s gc=%d %s %s%s%s\n",
346 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
347 speed[*s >> 14 & 3], *s >> 16 & 63,
348 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
349 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
351 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
353 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
354 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
357 static const char *evts[] = {
358 [0x00] = "evt_no_status", [0x01] = "-reserved-",
359 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
360 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
361 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
362 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
363 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
364 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
365 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
366 [0x10] = "-reserved-", [0x11] = "ack_complete",
367 [0x12] = "ack_pending ", [0x13] = "-reserved-",
368 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
369 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
370 [0x18] = "-reserved-", [0x19] = "-reserved-",
371 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
372 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
373 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
374 [0x20] = "pending/cancelled",
376 static const char *tcodes[] = {
377 [0x0] = "QW req", [0x1] = "BW req",
378 [0x2] = "W resp", [0x3] = "-reserved-",
379 [0x4] = "QR req", [0x5] = "BR req",
380 [0x6] = "QR resp", [0x7] = "BR resp",
381 [0x8] = "cycle start", [0x9] = "Lk req",
382 [0xa] = "async stream packet", [0xb] = "Lk resp",
383 [0xc] = "-reserved-", [0xd] = "-reserved-",
384 [0xe] = "link internal", [0xf] = "-reserved-",
386 static const char *phys[] = {
387 [0x0] = "phy config packet", [0x1] = "link-on packet",
388 [0x2] = "self-id packet", [0x3] = "-reserved-",
391 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
393 int tcode = header[0] >> 4 & 0xf;
396 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
399 if (unlikely(evt >= ARRAY_SIZE(evts)))
402 if (evt == OHCI1394_evt_bus_reset) {
403 fw_notify("A%c evt_bus_reset, generation %d\n",
404 dir, (header[2] >> 16) & 0xff);
408 if (header[0] == ~header[1]) {
409 fw_notify("A%c %s, %s, %08x\n",
410 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
415 case 0x0: case 0x6: case 0x8:
416 snprintf(specific, sizeof(specific), " = %08x",
417 be32_to_cpu((__force __be32)header[3]));
419 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
420 snprintf(specific, sizeof(specific), " %x,%x",
421 header[3] >> 16, header[3] & 0xffff);
429 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
431 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
432 fw_notify("A%c spd %x tl %02x, "
435 dir, speed, header[0] >> 10 & 0x3f,
436 header[1] >> 16, header[0] >> 16, evts[evt],
437 tcodes[tcode], header[1] & 0xffff, header[2], specific);
440 fw_notify("A%c spd %x tl %02x, "
443 dir, speed, header[0] >> 10 & 0x3f,
444 header[1] >> 16, header[0] >> 16, evts[evt],
445 tcodes[tcode], specific);
451 #define param_debug 0
452 static inline void log_irqs(u32 evt) {}
453 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
454 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
456 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
458 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
460 writel(data, ohci->registers + offset);
463 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
465 return readl(ohci->registers + offset);
468 static inline void flush_writes(const struct fw_ohci *ohci)
470 /* Do a dummy read to flush writes. */
471 reg_read(ohci, OHCI1394_Version);
474 static int read_phy_reg(struct fw_ohci *ohci, int addr)
479 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
480 for (i = 0; i < 3 + 100; i++) {
481 val = reg_read(ohci, OHCI1394_PhyControl);
482 if (val & OHCI1394_PhyControl_ReadDone)
483 return OHCI1394_PhyControl_ReadData(val);
486 * Try a few times without waiting. Sleeping is necessary
487 * only when the link/PHY interface is busy.
492 fw_error("failed to read phy reg\n");
497 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
501 reg_write(ohci, OHCI1394_PhyControl,
502 OHCI1394_PhyControl_Write(addr, val));
503 for (i = 0; i < 3 + 100; i++) {
504 val = reg_read(ohci, OHCI1394_PhyControl);
505 if (!(val & OHCI1394_PhyControl_WritePending))
511 fw_error("failed to write phy reg\n");
516 static int ohci_update_phy_reg(struct fw_card *card, int addr,
517 int clear_bits, int set_bits)
519 struct fw_ohci *ohci = fw_ohci(card);
522 ret = read_phy_reg(ohci, addr);
527 * The interrupt status bits are cleared by writing a one bit.
528 * Avoid clearing them unless explicitly requested in set_bits.
531 clear_bits |= PHY_INT_STATUS_BITS;
533 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
536 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
540 ret = ohci_update_phy_reg(&ohci->card, 7, PHY_PAGE_SELECT, page << 5);
544 return read_phy_reg(ohci, addr);
547 static int ar_context_add_page(struct ar_context *ctx)
549 struct device *dev = ctx->ohci->card.device;
550 struct ar_buffer *ab;
551 dma_addr_t uninitialized_var(ab_bus);
554 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
559 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
560 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
562 DESCRIPTOR_BRANCH_ALWAYS);
563 offset = offsetof(struct ar_buffer, data);
564 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
565 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
566 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
567 ab->descriptor.branch_address = 0;
569 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
570 ctx->last_buffer->next = ab;
571 ctx->last_buffer = ab;
573 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
574 flush_writes(ctx->ohci);
579 static void ar_context_release(struct ar_context *ctx)
581 struct ar_buffer *ab, *ab_next;
585 for (ab = ctx->current_buffer; ab; ab = ab_next) {
587 offset = offsetof(struct ar_buffer, data);
588 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
589 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
594 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
595 #define cond_le32_to_cpu(v) \
596 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
598 #define cond_le32_to_cpu(v) le32_to_cpu(v)
601 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
603 struct fw_ohci *ohci = ctx->ohci;
605 u32 status, length, tcode;
608 p.header[0] = cond_le32_to_cpu(buffer[0]);
609 p.header[1] = cond_le32_to_cpu(buffer[1]);
610 p.header[2] = cond_le32_to_cpu(buffer[2]);
612 tcode = (p.header[0] >> 4) & 0x0f;
614 case TCODE_WRITE_QUADLET_REQUEST:
615 case TCODE_READ_QUADLET_RESPONSE:
616 p.header[3] = (__force __u32) buffer[3];
617 p.header_length = 16;
618 p.payload_length = 0;
621 case TCODE_READ_BLOCK_REQUEST :
622 p.header[3] = cond_le32_to_cpu(buffer[3]);
623 p.header_length = 16;
624 p.payload_length = 0;
627 case TCODE_WRITE_BLOCK_REQUEST:
628 case TCODE_READ_BLOCK_RESPONSE:
629 case TCODE_LOCK_REQUEST:
630 case TCODE_LOCK_RESPONSE:
631 p.header[3] = cond_le32_to_cpu(buffer[3]);
632 p.header_length = 16;
633 p.payload_length = p.header[3] >> 16;
636 case TCODE_WRITE_RESPONSE:
637 case TCODE_READ_QUADLET_REQUEST:
638 case OHCI_TCODE_PHY_PACKET:
639 p.header_length = 12;
640 p.payload_length = 0;
644 /* FIXME: Stop context, discard everything, and restart? */
646 p.payload_length = 0;
649 p.payload = (void *) buffer + p.header_length;
651 /* FIXME: What to do about evt_* errors? */
652 length = (p.header_length + p.payload_length + 3) / 4;
653 status = cond_le32_to_cpu(buffer[length]);
654 evt = (status >> 16) & 0x1f;
657 p.speed = (status >> 21) & 0x7;
658 p.timestamp = status & 0xffff;
659 p.generation = ohci->request_generation;
661 log_ar_at_event('R', p.speed, p.header, evt);
664 * The OHCI bus reset handler synthesizes a phy packet with
665 * the new generation number when a bus reset happens (see
666 * section 8.4.2.3). This helps us determine when a request
667 * was received and make sure we send the response in the same
668 * generation. We only need this for requests; for responses
669 * we use the unique tlabel for finding the matching
672 * Alas some chips sometimes emit bus reset packets with a
673 * wrong generation. We set the correct generation for these
674 * at a slightly incorrect time (in bus_reset_tasklet).
676 if (evt == OHCI1394_evt_bus_reset) {
677 if (!(ohci->quirks & QUIRK_RESET_PACKET))
678 ohci->request_generation = (p.header[2] >> 16) & 0xff;
679 } else if (ctx == &ohci->ar_request_ctx) {
680 fw_core_handle_request(&ohci->card, &p);
682 fw_core_handle_response(&ohci->card, &p);
685 return buffer + length + 1;
688 static void ar_context_tasklet(unsigned long data)
690 struct ar_context *ctx = (struct ar_context *)data;
691 struct fw_ohci *ohci = ctx->ohci;
692 struct ar_buffer *ab;
693 struct descriptor *d;
696 ab = ctx->current_buffer;
699 if (d->res_count == 0) {
700 size_t size, rest, offset;
701 dma_addr_t start_bus;
705 * This descriptor is finished and we may have a
706 * packet split across this and the next buffer. We
707 * reuse the page for reassembling the split packet.
710 offset = offsetof(struct ar_buffer, data);
712 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
716 size = buffer + PAGE_SIZE - ctx->pointer;
717 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
718 memmove(buffer, ctx->pointer, size);
719 memcpy(buffer + size, ab->data, rest);
720 ctx->current_buffer = ab;
721 ctx->pointer = (void *) ab->data + rest;
722 end = buffer + size + rest;
725 buffer = handle_ar_packet(ctx, buffer);
727 dma_free_coherent(ohci->card.device, PAGE_SIZE,
729 ar_context_add_page(ctx);
731 buffer = ctx->pointer;
733 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
736 buffer = handle_ar_packet(ctx, buffer);
740 static int ar_context_init(struct ar_context *ctx,
741 struct fw_ohci *ohci, u32 regs)
747 ctx->last_buffer = &ab;
748 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
750 ar_context_add_page(ctx);
751 ar_context_add_page(ctx);
752 ctx->current_buffer = ab.next;
753 ctx->pointer = ctx->current_buffer->data;
758 static void ar_context_run(struct ar_context *ctx)
760 struct ar_buffer *ab = ctx->current_buffer;
764 offset = offsetof(struct ar_buffer, data);
765 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
767 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
768 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
769 flush_writes(ctx->ohci);
772 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
776 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
777 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
779 /* figure out which descriptor the branch address goes in */
780 if (z == 2 && (b == 3 || key == 2))
786 static void context_tasklet(unsigned long data)
788 struct context *ctx = (struct context *) data;
789 struct descriptor *d, *last;
792 struct descriptor_buffer *desc;
794 desc = list_entry(ctx->buffer_list.next,
795 struct descriptor_buffer, list);
797 while (last->branch_address != 0) {
798 struct descriptor_buffer *old_desc = desc;
799 address = le32_to_cpu(last->branch_address);
803 /* If the branch address points to a buffer outside of the
804 * current buffer, advance to the next buffer. */
805 if (address < desc->buffer_bus ||
806 address >= desc->buffer_bus + desc->used)
807 desc = list_entry(desc->list.next,
808 struct descriptor_buffer, list);
809 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
810 last = find_branch_descriptor(d, z);
812 if (!ctx->callback(ctx, d, last))
815 if (old_desc != desc) {
816 /* If we've advanced to the next buffer, move the
817 * previous buffer to the free list. */
820 spin_lock_irqsave(&ctx->ohci->lock, flags);
821 list_move_tail(&old_desc->list, &ctx->buffer_list);
822 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
829 * Allocate a new buffer and add it to the list of free buffers for this
830 * context. Must be called with ohci->lock held.
832 static int context_add_buffer(struct context *ctx)
834 struct descriptor_buffer *desc;
835 dma_addr_t uninitialized_var(bus_addr);
839 * 16MB of descriptors should be far more than enough for any DMA
840 * program. This will catch run-away userspace or DoS attacks.
842 if (ctx->total_allocation >= 16*1024*1024)
845 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
846 &bus_addr, GFP_ATOMIC);
850 offset = (void *)&desc->buffer - (void *)desc;
851 desc->buffer_size = PAGE_SIZE - offset;
852 desc->buffer_bus = bus_addr + offset;
855 list_add_tail(&desc->list, &ctx->buffer_list);
856 ctx->total_allocation += PAGE_SIZE;
861 static int context_init(struct context *ctx, struct fw_ohci *ohci,
862 u32 regs, descriptor_callback_t callback)
866 ctx->total_allocation = 0;
868 INIT_LIST_HEAD(&ctx->buffer_list);
869 if (context_add_buffer(ctx) < 0)
872 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
873 struct descriptor_buffer, list);
875 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
876 ctx->callback = callback;
879 * We put a dummy descriptor in the buffer that has a NULL
880 * branch address and looks like it's been sent. That way we
881 * have a descriptor to append DMA programs to.
883 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
884 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
885 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
886 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
887 ctx->last = ctx->buffer_tail->buffer;
888 ctx->prev = ctx->buffer_tail->buffer;
893 static void context_release(struct context *ctx)
895 struct fw_card *card = &ctx->ohci->card;
896 struct descriptor_buffer *desc, *tmp;
898 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
899 dma_free_coherent(card->device, PAGE_SIZE, desc,
901 ((void *)&desc->buffer - (void *)desc));
904 /* Must be called with ohci->lock held */
905 static struct descriptor *context_get_descriptors(struct context *ctx,
906 int z, dma_addr_t *d_bus)
908 struct descriptor *d = NULL;
909 struct descriptor_buffer *desc = ctx->buffer_tail;
911 if (z * sizeof(*d) > desc->buffer_size)
914 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
915 /* No room for the descriptor in this buffer, so advance to the
918 if (desc->list.next == &ctx->buffer_list) {
919 /* If there is no free buffer next in the list,
921 if (context_add_buffer(ctx) < 0)
924 desc = list_entry(desc->list.next,
925 struct descriptor_buffer, list);
926 ctx->buffer_tail = desc;
929 d = desc->buffer + desc->used / sizeof(*d);
930 memset(d, 0, z * sizeof(*d));
931 *d_bus = desc->buffer_bus + desc->used;
936 static void context_run(struct context *ctx, u32 extra)
938 struct fw_ohci *ohci = ctx->ohci;
940 reg_write(ohci, COMMAND_PTR(ctx->regs),
941 le32_to_cpu(ctx->last->branch_address));
942 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
943 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
947 static void context_append(struct context *ctx,
948 struct descriptor *d, int z, int extra)
951 struct descriptor_buffer *desc = ctx->buffer_tail;
953 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
955 desc->used += (z + extra) * sizeof(*d);
956 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
957 ctx->prev = find_branch_descriptor(d, z);
959 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
960 flush_writes(ctx->ohci);
963 static void context_stop(struct context *ctx)
968 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
969 flush_writes(ctx->ohci);
971 for (i = 0; i < 10; i++) {
972 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
973 if ((reg & CONTEXT_ACTIVE) == 0)
978 fw_error("Error: DMA context still active (0x%08x)\n", reg);
982 struct fw_packet *packet;
986 * This function apppends a packet to the DMA queue for transmission.
987 * Must always be called with the ochi->lock held to ensure proper
988 * generation handling and locking around packet queue manipulation.
990 static int at_context_queue_packet(struct context *ctx,
991 struct fw_packet *packet)
993 struct fw_ohci *ohci = ctx->ohci;
994 dma_addr_t d_bus, uninitialized_var(payload_bus);
995 struct driver_data *driver_data;
996 struct descriptor *d, *last;
1001 d = context_get_descriptors(ctx, 4, &d_bus);
1003 packet->ack = RCODE_SEND_ERROR;
1007 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1008 d[0].res_count = cpu_to_le16(packet->timestamp);
1011 * The DMA format for asyncronous link packets is different
1012 * from the IEEE1394 layout, so shift the fields around
1013 * accordingly. If header_length is 8, it's a PHY packet, to
1014 * which we need to prepend an extra quadlet.
1017 header = (__le32 *) &d[1];
1018 switch (packet->header_length) {
1021 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1022 (packet->speed << 16));
1023 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1024 (packet->header[0] & 0xffff0000));
1025 header[2] = cpu_to_le32(packet->header[2]);
1027 tcode = (packet->header[0] >> 4) & 0x0f;
1028 if (TCODE_IS_BLOCK_PACKET(tcode))
1029 header[3] = cpu_to_le32(packet->header[3]);
1031 header[3] = (__force __le32) packet->header[3];
1033 d[0].req_count = cpu_to_le16(packet->header_length);
1037 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1038 (packet->speed << 16));
1039 header[1] = cpu_to_le32(packet->header[0]);
1040 header[2] = cpu_to_le32(packet->header[1]);
1041 d[0].req_count = cpu_to_le16(12);
1045 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1046 (packet->speed << 16));
1047 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1048 d[0].req_count = cpu_to_le16(8);
1053 packet->ack = RCODE_SEND_ERROR;
1057 driver_data = (struct driver_data *) &d[3];
1058 driver_data->packet = packet;
1059 packet->driver_data = driver_data;
1061 if (packet->payload_length > 0) {
1063 dma_map_single(ohci->card.device, packet->payload,
1064 packet->payload_length, DMA_TO_DEVICE);
1065 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1066 packet->ack = RCODE_SEND_ERROR;
1069 packet->payload_bus = payload_bus;
1070 packet->payload_mapped = true;
1072 d[2].req_count = cpu_to_le16(packet->payload_length);
1073 d[2].data_address = cpu_to_le32(payload_bus);
1081 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1082 DESCRIPTOR_IRQ_ALWAYS |
1083 DESCRIPTOR_BRANCH_ALWAYS);
1086 * If the controller and packet generations don't match, we need to
1087 * bail out and try again. If IntEvent.busReset is set, the AT context
1088 * is halted, so appending to the context and trying to run it is
1089 * futile. Most controllers do the right thing and just flush the AT
1090 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1091 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1092 * up stalling out. So we just bail out in software and try again
1093 * later, and everyone is happy.
1094 * FIXME: Document how the locking works.
1096 if (ohci->generation != packet->generation ||
1097 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1098 if (packet->payload_mapped)
1099 dma_unmap_single(ohci->card.device, payload_bus,
1100 packet->payload_length, DMA_TO_DEVICE);
1101 packet->ack = RCODE_GENERATION;
1105 context_append(ctx, d, z, 4 - z);
1107 /* If the context isn't already running, start it up. */
1108 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1109 if ((reg & CONTEXT_RUN) == 0)
1110 context_run(ctx, 0);
1115 static int handle_at_packet(struct context *context,
1116 struct descriptor *d,
1117 struct descriptor *last)
1119 struct driver_data *driver_data;
1120 struct fw_packet *packet;
1121 struct fw_ohci *ohci = context->ohci;
1124 if (last->transfer_status == 0)
1125 /* This descriptor isn't done yet, stop iteration. */
1128 driver_data = (struct driver_data *) &d[3];
1129 packet = driver_data->packet;
1131 /* This packet was cancelled, just continue. */
1134 if (packet->payload_mapped)
1135 dma_unmap_single(ohci->card.device, packet->payload_bus,
1136 packet->payload_length, DMA_TO_DEVICE);
1138 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1139 packet->timestamp = le16_to_cpu(last->res_count);
1141 log_ar_at_event('T', packet->speed, packet->header, evt);
1144 case OHCI1394_evt_timeout:
1145 /* Async response transmit timed out. */
1146 packet->ack = RCODE_CANCELLED;
1149 case OHCI1394_evt_flushed:
1151 * The packet was flushed should give same error as
1152 * when we try to use a stale generation count.
1154 packet->ack = RCODE_GENERATION;
1157 case OHCI1394_evt_missing_ack:
1159 * Using a valid (current) generation count, but the
1160 * node is not on the bus or not sending acks.
1162 packet->ack = RCODE_NO_ACK;
1165 case ACK_COMPLETE + 0x10:
1166 case ACK_PENDING + 0x10:
1167 case ACK_BUSY_X + 0x10:
1168 case ACK_BUSY_A + 0x10:
1169 case ACK_BUSY_B + 0x10:
1170 case ACK_DATA_ERROR + 0x10:
1171 case ACK_TYPE_ERROR + 0x10:
1172 packet->ack = evt - 0x10;
1176 packet->ack = RCODE_SEND_ERROR;
1180 packet->callback(packet, &ohci->card, packet->ack);
1185 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1186 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1187 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1188 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1189 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1191 static void handle_local_rom(struct fw_ohci *ohci,
1192 struct fw_packet *packet, u32 csr)
1194 struct fw_packet response;
1195 int tcode, length, i;
1197 tcode = HEADER_GET_TCODE(packet->header[0]);
1198 if (TCODE_IS_BLOCK_PACKET(tcode))
1199 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1203 i = csr - CSR_CONFIG_ROM;
1204 if (i + length > CONFIG_ROM_SIZE) {
1205 fw_fill_response(&response, packet->header,
1206 RCODE_ADDRESS_ERROR, NULL, 0);
1207 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1208 fw_fill_response(&response, packet->header,
1209 RCODE_TYPE_ERROR, NULL, 0);
1211 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1212 (void *) ohci->config_rom + i, length);
1215 fw_core_handle_response(&ohci->card, &response);
1218 static void handle_local_lock(struct fw_ohci *ohci,
1219 struct fw_packet *packet, u32 csr)
1221 struct fw_packet response;
1222 int tcode, length, ext_tcode, sel;
1223 __be32 *payload, lock_old;
1224 u32 lock_arg, lock_data;
1226 tcode = HEADER_GET_TCODE(packet->header[0]);
1227 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1228 payload = packet->payload;
1229 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1231 if (tcode == TCODE_LOCK_REQUEST &&
1232 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1233 lock_arg = be32_to_cpu(payload[0]);
1234 lock_data = be32_to_cpu(payload[1]);
1235 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1239 fw_fill_response(&response, packet->header,
1240 RCODE_TYPE_ERROR, NULL, 0);
1244 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1245 reg_write(ohci, OHCI1394_CSRData, lock_data);
1246 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1247 reg_write(ohci, OHCI1394_CSRControl, sel);
1249 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1250 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1252 fw_notify("swap not done yet\n");
1254 fw_fill_response(&response, packet->header,
1255 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1257 fw_core_handle_response(&ohci->card, &response);
1260 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1265 if (ctx == &ctx->ohci->at_request_ctx) {
1266 packet->ack = ACK_PENDING;
1267 packet->callback(packet, &ctx->ohci->card, packet->ack);
1271 ((unsigned long long)
1272 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1274 csr = offset - CSR_REGISTER_BASE;
1276 /* Handle config rom reads. */
1277 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1278 handle_local_rom(ctx->ohci, packet, csr);
1280 case CSR_BUS_MANAGER_ID:
1281 case CSR_BANDWIDTH_AVAILABLE:
1282 case CSR_CHANNELS_AVAILABLE_HI:
1283 case CSR_CHANNELS_AVAILABLE_LO:
1284 handle_local_lock(ctx->ohci, packet, csr);
1287 if (ctx == &ctx->ohci->at_request_ctx)
1288 fw_core_handle_request(&ctx->ohci->card, packet);
1290 fw_core_handle_response(&ctx->ohci->card, packet);
1294 if (ctx == &ctx->ohci->at_response_ctx) {
1295 packet->ack = ACK_COMPLETE;
1296 packet->callback(packet, &ctx->ohci->card, packet->ack);
1300 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1302 unsigned long flags;
1305 spin_lock_irqsave(&ctx->ohci->lock, flags);
1307 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1308 ctx->ohci->generation == packet->generation) {
1309 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1310 handle_local_request(ctx, packet);
1314 ret = at_context_queue_packet(ctx, packet);
1315 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1318 packet->callback(packet, &ctx->ohci->card, packet->ack);
1322 static u32 cycle_timer_ticks(u32 cycle_timer)
1326 ticks = cycle_timer & 0xfff;
1327 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1328 ticks += (3072 * 8000) * (cycle_timer >> 25);
1334 * Some controllers exhibit one or more of the following bugs when updating the
1335 * iso cycle timer register:
1336 * - When the lowest six bits are wrapping around to zero, a read that happens
1337 * at the same time will return garbage in the lowest ten bits.
1338 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1339 * not incremented for about 60 ns.
1340 * - Occasionally, the entire register reads zero.
1342 * To catch these, we read the register three times and ensure that the
1343 * difference between each two consecutive reads is approximately the same, i.e.
1344 * less than twice the other. Furthermore, any negative difference indicates an
1345 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1346 * execute, so we have enough precision to compute the ratio of the differences.)
1348 static u32 get_cycle_time(struct fw_ohci *ohci)
1355 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1357 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1360 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1364 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1365 t0 = cycle_timer_ticks(c0);
1366 t1 = cycle_timer_ticks(c1);
1367 t2 = cycle_timer_ticks(c2);
1370 } while ((diff01 <= 0 || diff12 <= 0 ||
1371 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1379 * This function has to be called at least every 64 seconds. The bus_time
1380 * field stores not only the upper 25 bits of the BUS_TIME register but also
1381 * the most significant bit of the cycle timer in bit 6 so that we can detect
1382 * changes in this bit.
1384 static u32 update_bus_time(struct fw_ohci *ohci)
1386 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1388 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1389 ohci->bus_time += 0x40;
1391 return ohci->bus_time | cycle_time_seconds;
1394 static void bus_reset_tasklet(unsigned long data)
1396 struct fw_ohci *ohci = (struct fw_ohci *)data;
1397 int self_id_count, i, j, reg;
1398 int generation, new_generation;
1399 unsigned long flags;
1400 void *free_rom = NULL;
1401 dma_addr_t free_rom_bus = 0;
1403 reg = reg_read(ohci, OHCI1394_NodeID);
1404 if (!(reg & OHCI1394_NodeID_idValid)) {
1405 fw_notify("node ID not valid, new bus reset in progress\n");
1408 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1409 fw_notify("malconfigured bus\n");
1412 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1413 OHCI1394_NodeID_nodeNumber);
1415 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1416 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1417 fw_notify("inconsistent self IDs\n");
1421 * The count in the SelfIDCount register is the number of
1422 * bytes in the self ID receive buffer. Since we also receive
1423 * the inverted quadlets and a header quadlet, we shift one
1424 * bit extra to get the actual number of self IDs.
1426 self_id_count = (reg >> 3) & 0xff;
1427 if (self_id_count == 0 || self_id_count > 252) {
1428 fw_notify("inconsistent self IDs\n");
1431 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1434 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1435 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1436 fw_notify("inconsistent self IDs\n");
1439 ohci->self_id_buffer[j] =
1440 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1445 * Check the consistency of the self IDs we just read. The
1446 * problem we face is that a new bus reset can start while we
1447 * read out the self IDs from the DMA buffer. If this happens,
1448 * the DMA buffer will be overwritten with new self IDs and we
1449 * will read out inconsistent data. The OHCI specification
1450 * (section 11.2) recommends a technique similar to
1451 * linux/seqlock.h, where we remember the generation of the
1452 * self IDs in the buffer before reading them out and compare
1453 * it to the current generation after reading them out. If
1454 * the two generations match we know we have a consistent set
1458 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1459 if (new_generation != generation) {
1460 fw_notify("recursive bus reset detected, "
1461 "discarding self ids\n");
1465 /* FIXME: Document how the locking works. */
1466 spin_lock_irqsave(&ohci->lock, flags);
1468 ohci->generation = generation;
1469 context_stop(&ohci->at_request_ctx);
1470 context_stop(&ohci->at_response_ctx);
1471 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1473 if (ohci->quirks & QUIRK_RESET_PACKET)
1474 ohci->request_generation = generation;
1477 * This next bit is unrelated to the AT context stuff but we
1478 * have to do it under the spinlock also. If a new config rom
1479 * was set up before this reset, the old one is now no longer
1480 * in use and we can free it. Update the config rom pointers
1481 * to point to the current config rom and clear the
1482 * next_config_rom pointer so a new udpate can take place.
1485 if (ohci->next_config_rom != NULL) {
1486 if (ohci->next_config_rom != ohci->config_rom) {
1487 free_rom = ohci->config_rom;
1488 free_rom_bus = ohci->config_rom_bus;
1490 ohci->config_rom = ohci->next_config_rom;
1491 ohci->config_rom_bus = ohci->next_config_rom_bus;
1492 ohci->next_config_rom = NULL;
1495 * Restore config_rom image and manually update
1496 * config_rom registers. Writing the header quadlet
1497 * will indicate that the config rom is ready, so we
1500 reg_write(ohci, OHCI1394_BusOptions,
1501 be32_to_cpu(ohci->config_rom[2]));
1502 ohci->config_rom[0] = ohci->next_header;
1503 reg_write(ohci, OHCI1394_ConfigROMhdr,
1504 be32_to_cpu(ohci->next_header));
1507 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1508 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1509 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1512 spin_unlock_irqrestore(&ohci->lock, flags);
1515 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1516 free_rom, free_rom_bus);
1518 log_selfids(ohci->node_id, generation,
1519 self_id_count, ohci->self_id_buffer);
1521 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1522 self_id_count, ohci->self_id_buffer);
1525 static irqreturn_t irq_handler(int irq, void *data)
1527 struct fw_ohci *ohci = data;
1528 u32 event, iso_event;
1531 event = reg_read(ohci, OHCI1394_IntEventClear);
1533 if (!event || !~event)
1536 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1537 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1540 if (event & OHCI1394_selfIDComplete)
1541 tasklet_schedule(&ohci->bus_reset_tasklet);
1543 if (event & OHCI1394_RQPkt)
1544 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1546 if (event & OHCI1394_RSPkt)
1547 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1549 if (event & OHCI1394_reqTxComplete)
1550 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1552 if (event & OHCI1394_respTxComplete)
1553 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1555 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1556 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1559 i = ffs(iso_event) - 1;
1560 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1561 iso_event &= ~(1 << i);
1564 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1565 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1568 i = ffs(iso_event) - 1;
1569 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1570 iso_event &= ~(1 << i);
1573 if (unlikely(event & OHCI1394_regAccessFail))
1574 fw_error("Register access failure - "
1575 "please notify linux1394-devel@lists.sf.net\n");
1577 if (unlikely(event & OHCI1394_postedWriteErr))
1578 fw_error("PCI posted write error\n");
1580 if (unlikely(event & OHCI1394_cycleTooLong)) {
1581 if (printk_ratelimit())
1582 fw_notify("isochronous cycle too long\n");
1583 reg_write(ohci, OHCI1394_LinkControlSet,
1584 OHCI1394_LinkControl_cycleMaster);
1587 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1589 * We need to clear this event bit in order to make
1590 * cycleMatch isochronous I/O work. In theory we should
1591 * stop active cycleMatch iso contexts now and restart
1592 * them at least two cycles later. (FIXME?)
1594 if (printk_ratelimit())
1595 fw_notify("isochronous cycle inconsistent\n");
1598 if (event & OHCI1394_cycle64Seconds) {
1599 spin_lock(&ohci->lock);
1600 update_bus_time(ohci);
1601 spin_unlock(&ohci->lock);
1607 static int software_reset(struct fw_ohci *ohci)
1611 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1613 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1614 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1615 OHCI1394_HCControl_softReset) == 0)
1623 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1625 size_t size = length * 4;
1627 memcpy(dest, src, size);
1628 if (size < CONFIG_ROM_SIZE)
1629 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1632 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1635 int ret, clear, set, offset;
1637 /* Check if the driver should configure link and PHY. */
1638 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1639 OHCI1394_HCControl_programPhyEnable))
1642 /* Paranoia: check whether the PHY supports 1394a, too. */
1643 enable_1394a = false;
1644 ret = read_phy_reg(ohci, 2);
1647 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1648 ret = read_paged_phy_reg(ohci, 1, 8);
1652 enable_1394a = true;
1655 if (ohci->quirks & QUIRK_NO_1394A)
1656 enable_1394a = false;
1658 /* Configure PHY and link consistently. */
1661 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1663 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1666 ret = ohci_update_phy_reg(&ohci->card, 5, clear, set);
1671 offset = OHCI1394_HCControlSet;
1673 offset = OHCI1394_HCControlClear;
1674 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1676 /* Clean up: configuration has been taken care of. */
1677 reg_write(ohci, OHCI1394_HCControlClear,
1678 OHCI1394_HCControl_programPhyEnable);
1683 static int ohci_enable(struct fw_card *card,
1684 const __be32 *config_rom, size_t length)
1686 struct fw_ohci *ohci = fw_ohci(card);
1687 struct pci_dev *dev = to_pci_dev(card->device);
1688 u32 lps, seconds, irqs;
1691 if (software_reset(ohci)) {
1692 fw_error("Failed to reset ohci card.\n");
1697 * Now enable LPS, which we need in order to start accessing
1698 * most of the registers. In fact, on some cards (ALI M5251),
1699 * accessing registers in the SClk domain without LPS enabled
1700 * will lock up the machine. Wait 50msec to make sure we have
1701 * full link enabled. However, with some cards (well, at least
1702 * a JMicron PCIe card), we have to try again sometimes.
1704 reg_write(ohci, OHCI1394_HCControlSet,
1705 OHCI1394_HCControl_LPS |
1706 OHCI1394_HCControl_postedWriteEnable);
1709 for (lps = 0, i = 0; !lps && i < 3; i++) {
1711 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1712 OHCI1394_HCControl_LPS;
1716 fw_error("Failed to set Link Power Status\n");
1720 reg_write(ohci, OHCI1394_HCControlClear,
1721 OHCI1394_HCControl_noByteSwapData);
1723 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1724 reg_write(ohci, OHCI1394_LinkControlClear,
1725 OHCI1394_LinkControl_rcvPhyPkt);
1726 reg_write(ohci, OHCI1394_LinkControlSet,
1727 OHCI1394_LinkControl_rcvSelfID |
1728 OHCI1394_LinkControl_cycleTimerEnable |
1729 OHCI1394_LinkControl_cycleMaster);
1731 reg_write(ohci, OHCI1394_ATRetries,
1732 OHCI1394_MAX_AT_REQ_RETRIES |
1733 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1734 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1737 seconds = lower_32_bits(get_seconds());
1738 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1739 ohci->bus_time = seconds & ~0x3f;
1741 ar_context_run(&ohci->ar_request_ctx);
1742 ar_context_run(&ohci->ar_response_ctx);
1744 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1745 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1746 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1748 ret = configure_1394a_enhancements(ohci);
1752 /* Activate link_on bit and contender bit in our self ID packets.*/
1753 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1758 * When the link is not yet enabled, the atomic config rom
1759 * update mechanism described below in ohci_set_config_rom()
1760 * is not active. We have to update ConfigRomHeader and
1761 * BusOptions manually, and the write to ConfigROMmap takes
1762 * effect immediately. We tie this to the enabling of the
1763 * link, so we have a valid config rom before enabling - the
1764 * OHCI requires that ConfigROMhdr and BusOptions have valid
1765 * values before enabling.
1767 * However, when the ConfigROMmap is written, some controllers
1768 * always read back quadlets 0 and 2 from the config rom to
1769 * the ConfigRomHeader and BusOptions registers on bus reset.
1770 * They shouldn't do that in this initial case where the link
1771 * isn't enabled. This means we have to use the same
1772 * workaround here, setting the bus header to 0 and then write
1773 * the right values in the bus reset tasklet.
1777 ohci->next_config_rom =
1778 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1779 &ohci->next_config_rom_bus,
1781 if (ohci->next_config_rom == NULL)
1784 copy_config_rom(ohci->next_config_rom, config_rom, length);
1787 * In the suspend case, config_rom is NULL, which
1788 * means that we just reuse the old config rom.
1790 ohci->next_config_rom = ohci->config_rom;
1791 ohci->next_config_rom_bus = ohci->config_rom_bus;
1794 ohci->next_header = ohci->next_config_rom[0];
1795 ohci->next_config_rom[0] = 0;
1796 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1797 reg_write(ohci, OHCI1394_BusOptions,
1798 be32_to_cpu(ohci->next_config_rom[2]));
1799 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1801 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1803 if (!(ohci->quirks & QUIRK_NO_MSI))
1804 pci_enable_msi(dev);
1805 if (request_irq(dev->irq, irq_handler,
1806 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1807 ohci_driver_name, ohci)) {
1808 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1809 pci_disable_msi(dev);
1810 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1811 ohci->config_rom, ohci->config_rom_bus);
1815 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1816 OHCI1394_RQPkt | OHCI1394_RSPkt |
1817 OHCI1394_isochTx | OHCI1394_isochRx |
1818 OHCI1394_postedWriteErr |
1819 OHCI1394_selfIDComplete |
1820 OHCI1394_regAccessFail |
1821 OHCI1394_cycle64Seconds |
1822 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1823 OHCI1394_masterIntEnable;
1824 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1825 irqs |= OHCI1394_busReset;
1826 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1828 reg_write(ohci, OHCI1394_HCControlSet,
1829 OHCI1394_HCControl_linkEnable |
1830 OHCI1394_HCControl_BIBimageValid);
1834 * We are ready to go, initiate bus reset to finish the
1838 fw_core_initiate_bus_reset(&ohci->card, 1);
1843 static int ohci_set_config_rom(struct fw_card *card,
1844 const __be32 *config_rom, size_t length)
1846 struct fw_ohci *ohci;
1847 unsigned long flags;
1849 __be32 *next_config_rom;
1850 dma_addr_t uninitialized_var(next_config_rom_bus);
1852 ohci = fw_ohci(card);
1855 * When the OHCI controller is enabled, the config rom update
1856 * mechanism is a bit tricky, but easy enough to use. See
1857 * section 5.5.6 in the OHCI specification.
1859 * The OHCI controller caches the new config rom address in a
1860 * shadow register (ConfigROMmapNext) and needs a bus reset
1861 * for the changes to take place. When the bus reset is
1862 * detected, the controller loads the new values for the
1863 * ConfigRomHeader and BusOptions registers from the specified
1864 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1865 * shadow register. All automatically and atomically.
1867 * Now, there's a twist to this story. The automatic load of
1868 * ConfigRomHeader and BusOptions doesn't honor the
1869 * noByteSwapData bit, so with a be32 config rom, the
1870 * controller will load be32 values in to these registers
1871 * during the atomic update, even on litte endian
1872 * architectures. The workaround we use is to put a 0 in the
1873 * header quadlet; 0 is endian agnostic and means that the
1874 * config rom isn't ready yet. In the bus reset tasklet we
1875 * then set up the real values for the two registers.
1877 * We use ohci->lock to avoid racing with the code that sets
1878 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1882 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1883 &next_config_rom_bus, GFP_KERNEL);
1884 if (next_config_rom == NULL)
1887 spin_lock_irqsave(&ohci->lock, flags);
1889 if (ohci->next_config_rom == NULL) {
1890 ohci->next_config_rom = next_config_rom;
1891 ohci->next_config_rom_bus = next_config_rom_bus;
1893 copy_config_rom(ohci->next_config_rom, config_rom, length);
1895 ohci->next_header = config_rom[0];
1896 ohci->next_config_rom[0] = 0;
1898 reg_write(ohci, OHCI1394_ConfigROMmap,
1899 ohci->next_config_rom_bus);
1903 spin_unlock_irqrestore(&ohci->lock, flags);
1906 * Now initiate a bus reset to have the changes take
1907 * effect. We clean up the old config rom memory and DMA
1908 * mappings in the bus reset tasklet, since the OHCI
1909 * controller could need to access it before the bus reset
1913 fw_core_initiate_bus_reset(&ohci->card, 1);
1915 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1916 next_config_rom, next_config_rom_bus);
1921 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1923 struct fw_ohci *ohci = fw_ohci(card);
1925 at_context_transmit(&ohci->at_request_ctx, packet);
1928 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1930 struct fw_ohci *ohci = fw_ohci(card);
1932 at_context_transmit(&ohci->at_response_ctx, packet);
1935 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1937 struct fw_ohci *ohci = fw_ohci(card);
1938 struct context *ctx = &ohci->at_request_ctx;
1939 struct driver_data *driver_data = packet->driver_data;
1942 tasklet_disable(&ctx->tasklet);
1944 if (packet->ack != 0)
1947 if (packet->payload_mapped)
1948 dma_unmap_single(ohci->card.device, packet->payload_bus,
1949 packet->payload_length, DMA_TO_DEVICE);
1951 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1952 driver_data->packet = NULL;
1953 packet->ack = RCODE_CANCELLED;
1954 packet->callback(packet, &ohci->card, packet->ack);
1957 tasklet_enable(&ctx->tasklet);
1962 static int ohci_enable_phys_dma(struct fw_card *card,
1963 int node_id, int generation)
1965 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1968 struct fw_ohci *ohci = fw_ohci(card);
1969 unsigned long flags;
1973 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1974 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1977 spin_lock_irqsave(&ohci->lock, flags);
1979 if (ohci->generation != generation) {
1985 * Note, if the node ID contains a non-local bus ID, physical DMA is
1986 * enabled for _all_ nodes on remote buses.
1989 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1991 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1993 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1997 spin_unlock_irqrestore(&ohci->lock, flags);
2000 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2003 static u32 ohci_read_csr_reg(struct fw_card *card, int csr_offset)
2005 struct fw_ohci *ohci = fw_ohci(card);
2006 unsigned long flags;
2009 switch (csr_offset) {
2011 return reg_read(ohci, OHCI1394_NodeID) << 16;
2013 case CSR_CYCLE_TIME:
2014 return get_cycle_time(ohci);
2018 * We might be called just after the cycle timer has wrapped
2019 * around but just before the cycle64Seconds handler, so we
2020 * better check here, too, if the bus time needs to be updated.
2022 spin_lock_irqsave(&ohci->lock, flags);
2023 value = update_bus_time(ohci);
2024 spin_unlock_irqrestore(&ohci->lock, flags);
2027 case CSR_BUSY_TIMEOUT:
2028 value = reg_read(ohci, OHCI1394_ATRetries);
2029 return (value >> 4) & 0x0ffff00f;
2037 static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value)
2039 struct fw_ohci *ohci = fw_ohci(card);
2040 unsigned long flags;
2042 switch (csr_offset) {
2044 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2048 case CSR_CYCLE_TIME:
2049 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2050 reg_write(ohci, OHCI1394_IntEventSet,
2051 OHCI1394_cycleInconsistent);
2056 spin_lock_irqsave(&ohci->lock, flags);
2057 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2058 spin_unlock_irqrestore(&ohci->lock, flags);
2061 case CSR_BUSY_TIMEOUT:
2062 value = (value & 0xf) | ((value & 0xf) << 4) |
2063 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2064 reg_write(ohci, OHCI1394_ATRetries, value);
2074 static void copy_iso_headers(struct iso_context *ctx, void *p)
2076 int i = ctx->header_length;
2078 if (i + ctx->base.header_size > PAGE_SIZE)
2082 * The iso header is byteswapped to little endian by
2083 * the controller, but the remaining header quadlets
2084 * are big endian. We want to present all the headers
2085 * as big endian, so we have to swap the first quadlet.
2087 if (ctx->base.header_size > 0)
2088 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2089 if (ctx->base.header_size > 4)
2090 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2091 if (ctx->base.header_size > 8)
2092 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2093 ctx->header_length += ctx->base.header_size;
2096 static int handle_ir_packet_per_buffer(struct context *context,
2097 struct descriptor *d,
2098 struct descriptor *last)
2100 struct iso_context *ctx =
2101 container_of(context, struct iso_context, context);
2102 struct descriptor *pd;
2106 for (pd = d; pd <= last; pd++) {
2107 if (pd->transfer_status)
2111 /* Descriptor(s) not done yet, stop iteration */
2115 copy_iso_headers(ctx, p);
2117 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2118 ir_header = (__le32 *) p;
2119 ctx->base.callback(&ctx->base,
2120 le32_to_cpu(ir_header[0]) & 0xffff,
2121 ctx->header_length, ctx->header,
2122 ctx->base.callback_data);
2123 ctx->header_length = 0;
2129 static int handle_it_packet(struct context *context,
2130 struct descriptor *d,
2131 struct descriptor *last)
2133 struct iso_context *ctx =
2134 container_of(context, struct iso_context, context);
2136 struct descriptor *pd;
2138 for (pd = d; pd <= last; pd++)
2139 if (pd->transfer_status)
2142 /* Descriptor(s) not done yet, stop iteration */
2145 i = ctx->header_length;
2146 if (i + 4 < PAGE_SIZE) {
2147 /* Present this value as big-endian to match the receive code */
2148 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2149 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2150 le16_to_cpu(pd->res_count));
2151 ctx->header_length += 4;
2153 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2154 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
2155 ctx->header_length, ctx->header,
2156 ctx->base.callback_data);
2157 ctx->header_length = 0;
2162 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2163 int type, int channel, size_t header_size)
2165 struct fw_ohci *ohci = fw_ohci(card);
2166 struct iso_context *ctx, *list;
2167 descriptor_callback_t callback;
2168 u64 *channels, dont_care = ~0ULL;
2170 unsigned long flags;
2171 int index, ret = -ENOMEM;
2173 if (type == FW_ISO_CONTEXT_TRANSMIT) {
2174 channels = &dont_care;
2175 mask = &ohci->it_context_mask;
2176 list = ohci->it_context_list;
2177 callback = handle_it_packet;
2179 channels = &ohci->ir_context_channels;
2180 mask = &ohci->ir_context_mask;
2181 list = ohci->ir_context_list;
2182 callback = handle_ir_packet_per_buffer;
2185 spin_lock_irqsave(&ohci->lock, flags);
2186 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2188 *channels &= ~(1ULL << channel);
2189 *mask &= ~(1 << index);
2191 spin_unlock_irqrestore(&ohci->lock, flags);
2194 return ERR_PTR(-EBUSY);
2196 if (type == FW_ISO_CONTEXT_TRANSMIT)
2197 regs = OHCI1394_IsoXmitContextBase(index);
2199 regs = OHCI1394_IsoRcvContextBase(index);
2202 memset(ctx, 0, sizeof(*ctx));
2203 ctx->header_length = 0;
2204 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2205 if (ctx->header == NULL)
2208 ret = context_init(&ctx->context, ohci, regs, callback);
2210 goto out_with_header;
2215 free_page((unsigned long)ctx->header);
2217 spin_lock_irqsave(&ohci->lock, flags);
2218 *mask |= 1 << index;
2219 spin_unlock_irqrestore(&ohci->lock, flags);
2221 return ERR_PTR(ret);
2224 static int ohci_start_iso(struct fw_iso_context *base,
2225 s32 cycle, u32 sync, u32 tags)
2227 struct iso_context *ctx = container_of(base, struct iso_context, base);
2228 struct fw_ohci *ohci = ctx->context.ohci;
2232 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2233 index = ctx - ohci->it_context_list;
2236 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2237 (cycle & 0x7fff) << 16;
2239 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2240 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2241 context_run(&ctx->context, match);
2243 index = ctx - ohci->ir_context_list;
2244 control = IR_CONTEXT_ISOCH_HEADER;
2245 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2247 match |= (cycle & 0x07fff) << 12;
2248 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2251 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2252 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2253 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2254 context_run(&ctx->context, control);
2260 static int ohci_stop_iso(struct fw_iso_context *base)
2262 struct fw_ohci *ohci = fw_ohci(base->card);
2263 struct iso_context *ctx = container_of(base, struct iso_context, base);
2266 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2267 index = ctx - ohci->it_context_list;
2268 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2270 index = ctx - ohci->ir_context_list;
2271 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2274 context_stop(&ctx->context);
2279 static void ohci_free_iso_context(struct fw_iso_context *base)
2281 struct fw_ohci *ohci = fw_ohci(base->card);
2282 struct iso_context *ctx = container_of(base, struct iso_context, base);
2283 unsigned long flags;
2286 ohci_stop_iso(base);
2287 context_release(&ctx->context);
2288 free_page((unsigned long)ctx->header);
2290 spin_lock_irqsave(&ohci->lock, flags);
2292 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2293 index = ctx - ohci->it_context_list;
2294 ohci->it_context_mask |= 1 << index;
2296 index = ctx - ohci->ir_context_list;
2297 ohci->ir_context_mask |= 1 << index;
2298 ohci->ir_context_channels |= 1ULL << base->channel;
2301 spin_unlock_irqrestore(&ohci->lock, flags);
2304 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2305 struct fw_iso_packet *packet,
2306 struct fw_iso_buffer *buffer,
2307 unsigned long payload)
2309 struct iso_context *ctx = container_of(base, struct iso_context, base);
2310 struct descriptor *d, *last, *pd;
2311 struct fw_iso_packet *p;
2313 dma_addr_t d_bus, page_bus;
2314 u32 z, header_z, payload_z, irq;
2315 u32 payload_index, payload_end_index, next_page_index;
2316 int page, end_page, i, length, offset;
2319 payload_index = payload;
2325 if (p->header_length > 0)
2328 /* Determine the first page the payload isn't contained in. */
2329 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2330 if (p->payload_length > 0)
2331 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2337 /* Get header size in number of descriptors. */
2338 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2340 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2345 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2346 d[0].req_count = cpu_to_le16(8);
2348 * Link the skip address to this descriptor itself. This causes
2349 * a context to skip a cycle whenever lost cycles or FIFO
2350 * overruns occur, without dropping the data. The application
2351 * should then decide whether this is an error condition or not.
2352 * FIXME: Make the context's cycle-lost behaviour configurable?
2354 d[0].branch_address = cpu_to_le32(d_bus | z);
2356 header = (__le32 *) &d[1];
2357 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2358 IT_HEADER_TAG(p->tag) |
2359 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2360 IT_HEADER_CHANNEL(ctx->base.channel) |
2361 IT_HEADER_SPEED(ctx->base.speed));
2363 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2364 p->payload_length));
2367 if (p->header_length > 0) {
2368 d[2].req_count = cpu_to_le16(p->header_length);
2369 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2370 memcpy(&d[z], p->header, p->header_length);
2373 pd = d + z - payload_z;
2374 payload_end_index = payload_index + p->payload_length;
2375 for (i = 0; i < payload_z; i++) {
2376 page = payload_index >> PAGE_SHIFT;
2377 offset = payload_index & ~PAGE_MASK;
2378 next_page_index = (page + 1) << PAGE_SHIFT;
2380 min(next_page_index, payload_end_index) - payload_index;
2381 pd[i].req_count = cpu_to_le16(length);
2383 page_bus = page_private(buffer->pages[page]);
2384 pd[i].data_address = cpu_to_le32(page_bus + offset);
2386 payload_index += length;
2390 irq = DESCRIPTOR_IRQ_ALWAYS;
2392 irq = DESCRIPTOR_NO_IRQ;
2394 last = z == 2 ? d : d + z - 1;
2395 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2397 DESCRIPTOR_BRANCH_ALWAYS |
2400 context_append(&ctx->context, d, z, header_z);
2405 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2406 struct fw_iso_packet *packet,
2407 struct fw_iso_buffer *buffer,
2408 unsigned long payload)
2410 struct iso_context *ctx = container_of(base, struct iso_context, base);
2411 struct descriptor *d, *pd;
2412 struct fw_iso_packet *p = packet;
2413 dma_addr_t d_bus, page_bus;
2414 u32 z, header_z, rest;
2416 int page, offset, packet_count, header_size, payload_per_buffer;
2419 * The OHCI controller puts the isochronous header and trailer in the
2420 * buffer, so we need at least 8 bytes.
2422 packet_count = p->header_length / ctx->base.header_size;
2423 header_size = max(ctx->base.header_size, (size_t)8);
2425 /* Get header size in number of descriptors. */
2426 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2427 page = payload >> PAGE_SHIFT;
2428 offset = payload & ~PAGE_MASK;
2429 payload_per_buffer = p->payload_length / packet_count;
2431 for (i = 0; i < packet_count; i++) {
2432 /* d points to the header descriptor */
2433 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2434 d = context_get_descriptors(&ctx->context,
2435 z + header_z, &d_bus);
2439 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2440 DESCRIPTOR_INPUT_MORE);
2441 if (p->skip && i == 0)
2442 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2443 d->req_count = cpu_to_le16(header_size);
2444 d->res_count = d->req_count;
2445 d->transfer_status = 0;
2446 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2448 rest = payload_per_buffer;
2450 for (j = 1; j < z; j++) {
2452 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2453 DESCRIPTOR_INPUT_MORE);
2455 if (offset + rest < PAGE_SIZE)
2458 length = PAGE_SIZE - offset;
2459 pd->req_count = cpu_to_le16(length);
2460 pd->res_count = pd->req_count;
2461 pd->transfer_status = 0;
2463 page_bus = page_private(buffer->pages[page]);
2464 pd->data_address = cpu_to_le32(page_bus + offset);
2466 offset = (offset + length) & ~PAGE_MASK;
2471 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2472 DESCRIPTOR_INPUT_LAST |
2473 DESCRIPTOR_BRANCH_ALWAYS);
2474 if (p->interrupt && i == packet_count - 1)
2475 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2477 context_append(&ctx->context, d, z, header_z);
2483 static int ohci_queue_iso(struct fw_iso_context *base,
2484 struct fw_iso_packet *packet,
2485 struct fw_iso_buffer *buffer,
2486 unsigned long payload)
2488 struct iso_context *ctx = container_of(base, struct iso_context, base);
2489 unsigned long flags;
2492 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2493 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2494 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2496 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2498 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2503 static const struct fw_card_driver ohci_driver = {
2504 .enable = ohci_enable,
2505 .update_phy_reg = ohci_update_phy_reg,
2506 .set_config_rom = ohci_set_config_rom,
2507 .send_request = ohci_send_request,
2508 .send_response = ohci_send_response,
2509 .cancel_packet = ohci_cancel_packet,
2510 .enable_phys_dma = ohci_enable_phys_dma,
2511 .read_csr_reg = ohci_read_csr_reg,
2512 .write_csr_reg = ohci_write_csr_reg,
2514 .allocate_iso_context = ohci_allocate_iso_context,
2515 .free_iso_context = ohci_free_iso_context,
2516 .queue_iso = ohci_queue_iso,
2517 .start_iso = ohci_start_iso,
2518 .stop_iso = ohci_stop_iso,
2521 #ifdef CONFIG_PPC_PMAC
2522 static void pmac_ohci_on(struct pci_dev *dev)
2524 if (machine_is(powermac)) {
2525 struct device_node *ofn = pci_device_to_OF_node(dev);
2528 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2529 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2534 static void pmac_ohci_off(struct pci_dev *dev)
2536 if (machine_is(powermac)) {
2537 struct device_node *ofn = pci_device_to_OF_node(dev);
2540 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2541 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2546 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2547 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2548 #endif /* CONFIG_PPC_PMAC */
2550 static int __devinit pci_probe(struct pci_dev *dev,
2551 const struct pci_device_id *ent)
2553 struct fw_ohci *ohci;
2554 u32 bus_options, max_receive, link_speed, version, link_enh;
2556 int i, err, n_ir, n_it;
2559 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2565 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2569 err = pci_enable_device(dev);
2571 fw_error("Failed to enable OHCI hardware\n");
2575 pci_set_master(dev);
2576 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2577 pci_set_drvdata(dev, ohci);
2579 spin_lock_init(&ohci->lock);
2581 tasklet_init(&ohci->bus_reset_tasklet,
2582 bus_reset_tasklet, (unsigned long)ohci);
2584 err = pci_request_region(dev, 0, ohci_driver_name);
2586 fw_error("MMIO resource unavailable\n");
2590 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2591 if (ohci->registers == NULL) {
2592 fw_error("Failed to remap registers\n");
2597 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2598 if (ohci_quirks[i].vendor == dev->vendor &&
2599 (ohci_quirks[i].device == dev->device ||
2600 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2601 ohci->quirks = ohci_quirks[i].flags;
2605 ohci->quirks = param_quirks;
2607 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2608 if (dev->vendor == PCI_VENDOR_ID_TI) {
2609 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2611 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2612 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2613 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2615 /* use priority arbitration for asynchronous responses */
2616 link_enh |= TI_LinkEnh_enab_unfair;
2618 /* required for aPhyEnhanceEnable to work */
2619 link_enh |= TI_LinkEnh_enab_accel;
2621 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2624 ar_context_init(&ohci->ar_request_ctx, ohci,
2625 OHCI1394_AsReqRcvContextControlSet);
2627 ar_context_init(&ohci->ar_response_ctx, ohci,
2628 OHCI1394_AsRspRcvContextControlSet);
2630 context_init(&ohci->at_request_ctx, ohci,
2631 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2633 context_init(&ohci->at_response_ctx, ohci,
2634 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2636 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2637 ohci->ir_context_channels = ~0ULL;
2638 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2639 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2640 n_ir = hweight32(ohci->ir_context_mask);
2641 size = sizeof(struct iso_context) * n_ir;
2642 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2644 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2645 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2646 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2647 n_it = hweight32(ohci->it_context_mask);
2648 size = sizeof(struct iso_context) * n_it;
2649 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2651 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2656 /* self-id dma buffer allocation */
2657 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2661 if (ohci->self_id_cpu == NULL) {
2666 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2667 max_receive = (bus_options >> 12) & 0xf;
2668 link_speed = bus_options & 0x7;
2669 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2670 reg_read(ohci, OHCI1394_GUIDLo);
2672 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2676 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2677 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2678 "%d IR + %d IT contexts, quirks 0x%x\n",
2679 dev_name(&dev->dev), version >> 16, version & 0xff,
2680 n_ir, n_it, ohci->quirks);
2685 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2686 ohci->self_id_cpu, ohci->self_id_bus);
2688 kfree(ohci->ir_context_list);
2689 kfree(ohci->it_context_list);
2690 context_release(&ohci->at_response_ctx);
2691 context_release(&ohci->at_request_ctx);
2692 ar_context_release(&ohci->ar_response_ctx);
2693 ar_context_release(&ohci->ar_request_ctx);
2694 pci_iounmap(dev, ohci->registers);
2696 pci_release_region(dev, 0);
2698 pci_disable_device(dev);
2704 fw_error("Out of memory\n");
2709 static void pci_remove(struct pci_dev *dev)
2711 struct fw_ohci *ohci;
2713 ohci = pci_get_drvdata(dev);
2714 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2716 fw_core_remove_card(&ohci->card);
2719 * FIXME: Fail all pending packets here, now that the upper
2720 * layers can't queue any more.
2723 software_reset(ohci);
2724 free_irq(dev->irq, ohci);
2726 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2727 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2728 ohci->next_config_rom, ohci->next_config_rom_bus);
2729 if (ohci->config_rom)
2730 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2731 ohci->config_rom, ohci->config_rom_bus);
2732 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2733 ohci->self_id_cpu, ohci->self_id_bus);
2734 ar_context_release(&ohci->ar_request_ctx);
2735 ar_context_release(&ohci->ar_response_ctx);
2736 context_release(&ohci->at_request_ctx);
2737 context_release(&ohci->at_response_ctx);
2738 kfree(ohci->it_context_list);
2739 kfree(ohci->ir_context_list);
2740 pci_disable_msi(dev);
2741 pci_iounmap(dev, ohci->registers);
2742 pci_release_region(dev, 0);
2743 pci_disable_device(dev);
2747 fw_notify("Removed fw-ohci device.\n");
2751 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2753 struct fw_ohci *ohci = pci_get_drvdata(dev);
2756 software_reset(ohci);
2757 free_irq(dev->irq, ohci);
2758 pci_disable_msi(dev);
2759 err = pci_save_state(dev);
2761 fw_error("pci_save_state failed\n");
2764 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2766 fw_error("pci_set_power_state failed with %d\n", err);
2772 static int pci_resume(struct pci_dev *dev)
2774 struct fw_ohci *ohci = pci_get_drvdata(dev);
2778 pci_set_power_state(dev, PCI_D0);
2779 pci_restore_state(dev);
2780 err = pci_enable_device(dev);
2782 fw_error("pci_enable_device failed\n");
2786 return ohci_enable(&ohci->card, NULL, 0);
2790 static const struct pci_device_id pci_table[] = {
2791 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2795 MODULE_DEVICE_TABLE(pci, pci_table);
2797 static struct pci_driver fw_ohci_pci_driver = {
2798 .name = ohci_driver_name,
2799 .id_table = pci_table,
2801 .remove = pci_remove,
2803 .resume = pci_resume,
2804 .suspend = pci_suspend,
2808 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2809 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2810 MODULE_LICENSE("GPL");
2812 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2813 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2814 MODULE_ALIAS("ohci1394");
2817 static int __init fw_ohci_init(void)
2819 return pci_register_driver(&fw_ohci_pci_driver);
2822 static void __exit fw_ohci_cleanup(void)
2824 pci_unregister_driver(&fw_ohci_pci_driver);
2827 module_init(fw_ohci_init);
2828 module_exit(fw_ohci_cleanup);