1 #include <linux/module.h>
2 #include "edac_mce_amd.h"
4 static bool report_gart_errors;
5 static void (*nb_bus_decoder)(int node_id, struct err_regs *regs);
6 static void (*orig_mce_callback)(struct mce *m);
8 void amd_report_gart_errors(bool v)
10 report_gart_errors = v;
12 EXPORT_SYMBOL_GPL(amd_report_gart_errors);
14 void amd_register_ecc_decoder(void (*f)(int, struct err_regs *))
18 EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
20 void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *))
23 WARN_ON(nb_bus_decoder != f);
25 nb_bus_decoder = NULL;
28 EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
31 * string representation for the different MCA reported error types, see F3x48
34 const char *tt_msgs[] = { /* transaction type */
40 EXPORT_SYMBOL_GPL(tt_msgs);
42 const char *ll_msgs[] = { /* cache level */
48 EXPORT_SYMBOL_GPL(ll_msgs);
50 const char *rrrr_msgs[] = {
68 EXPORT_SYMBOL_GPL(rrrr_msgs);
70 const char *pp_msgs[] = { /* participating processor */
71 "local node originated (SRC)",
72 "local node responded to request (RES)",
73 "local node observed as 3rd party (OBS)",
76 EXPORT_SYMBOL_GPL(pp_msgs);
78 const char *to_msgs[] = {
82 EXPORT_SYMBOL_GPL(to_msgs);
84 const char *ii_msgs[] = { /* memory or i/o */
90 EXPORT_SYMBOL_GPL(ii_msgs);
93 * Map the 4 or 5 (family-specific) bits of Extended Error code to the
96 const char *ext_msgs[] = {
97 "K8 ECC error", /* 0_0000b */
98 "CRC error on link", /* 0_0001b */
99 "Sync error packets on link", /* 0_0010b */
100 "Master Abort during link operation", /* 0_0011b */
101 "Target Abort during link operation", /* 0_0100b */
102 "Invalid GART PTE entry during table walk", /* 0_0101b */
103 "Unsupported atomic RMW command received", /* 0_0110b */
104 "WDT error: NB transaction timeout", /* 0_0111b */
105 "ECC/ChipKill ECC error", /* 0_1000b */
106 "SVM DEV Error", /* 0_1001b */
107 "Link Data error", /* 0_1010b */
108 "Link/L3/Probe Filter Protocol error", /* 0_1011b */
109 "NB Internal Arrays Parity error", /* 0_1100b */
110 "DRAM Address/Control Parity error", /* 0_1101b */
111 "Link Transmission error", /* 0_1110b */
112 "GART/DEV Table Walk Data error" /* 0_1111b */
113 "Res 0x100 error", /* 1_0000b */
114 "Res 0x101 error", /* 1_0001b */
115 "Res 0x102 error", /* 1_0010b */
116 "Res 0x103 error", /* 1_0011b */
117 "Res 0x104 error", /* 1_0100b */
118 "Res 0x105 error", /* 1_0101b */
119 "Res 0x106 error", /* 1_0110b */
120 "Res 0x107 error", /* 1_0111b */
121 "Res 0x108 error", /* 1_1000b */
122 "Res 0x109 error", /* 1_1001b */
123 "Res 0x10A error", /* 1_1010b */
124 "Res 0x10B error", /* 1_1011b */
125 "ECC error in L3 Cache Data", /* 1_1100b */
126 "L3 Cache Tag error", /* 1_1101b */
127 "L3 Cache LRU Parity error", /* 1_1110b */
128 "Probe Filter error" /* 1_1111b */
130 EXPORT_SYMBOL_GPL(ext_msgs);
132 static void amd_decode_dc_mce(u64 mc0_status)
134 u32 ec = mc0_status & 0xffff;
135 u32 xec = (mc0_status >> 16) & 0xf;
137 pr_emerg(" Data Cache Error");
139 if (xec == 1 && TLB_ERROR(ec))
140 pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
142 if (mc0_status & (1ULL << 40))
143 pr_cont(" during Data Scrub.\n");
144 else if (TLB_ERROR(ec))
145 pr_cont(": %s TLB parity error.\n", LL_MSG(ec));
146 else if (MEM_ERROR(ec)) {
148 u8 tt = (ec >> 2) & 0x3;
149 u8 rrrr = (ec >> 4) & 0xf;
151 /* see F10h BKDG (31116), Table 92. */
156 pr_cont(": Data/Tag %s error.\n", RRRR_MSG(ec));
158 } else if (ll == 0x2 && rrrr == 0x3)
159 pr_cont(" during L1 linefill from L2.\n");
162 } else if (BUS_ERROR(ec) && boot_cpu_data.x86 == 0xf)
163 pr_cont(" during system linefill.\n");
172 pr_warning("Corrupted DC MCE info?\n");
175 static void amd_decode_ic_mce(u64 mc1_status)
177 u32 ec = mc1_status & 0xffff;
178 u32 xec = (mc1_status >> 16) & 0xf;
180 pr_emerg(" Instruction Cache Error");
182 if (xec == 1 && TLB_ERROR(ec))
183 pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
186 pr_cont(": %s TLB Parity error.\n", LL_MSG(ec));
187 else if (BUS_ERROR(ec)) {
188 if (boot_cpu_data.x86 == 0xf &&
189 (mc1_status & (1ULL << 58)))
190 pr_cont(" during system linefill.\n");
192 pr_cont(" during attempted NB data read.\n");
193 } else if (MEM_ERROR(ec)) {
195 u8 rrrr = (ec >> 4) & 0xf;
198 pr_cont(" during a linefill from L2.\n");
199 else if (ll == 0x1) {
203 pr_cont(": Parity error during "
208 pr_cont(": Copyback Parity/Victim"
213 pr_cont(": Tag Snoop error.\n");
229 pr_warning("Corrupted IC MCE info?\n");
232 static void amd_decode_bu_mce(u64 mc2_status)
234 u32 ec = mc2_status & 0xffff;
235 u32 xec = (mc2_status >> 16) & 0xf;
237 pr_emerg(" Bus Unit Error");
240 pr_cont(" in the write data buffers.\n");
242 pr_cont(" in the victim data buffers.\n");
243 else if (xec == 0x2 && MEM_ERROR(ec))
244 pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
245 else if (xec == 0x0) {
247 pr_cont(": %s error in a Page Descriptor Cache or "
248 "Guest TLB.\n", TT_MSG(ec));
249 else if (BUS_ERROR(ec))
250 pr_cont(": %s/ECC error in data read from NB: %s.\n",
251 RRRR_MSG(ec), PP_MSG(ec));
252 else if (MEM_ERROR(ec)) {
253 u8 rrrr = (ec >> 4) & 0xf;
256 pr_cont(": %s error during data copyback.\n",
258 else if (rrrr <= 0x1)
259 pr_cont(": %s parity/ECC error during data "
260 "access from L2.\n", RRRR_MSG(ec));
271 pr_warning("Corrupted BU MCE info?\n");
274 static void amd_decode_ls_mce(u64 mc3_status)
276 u32 ec = mc3_status & 0xffff;
277 u32 xec = (mc3_status >> 16) & 0xf;
279 pr_emerg(" Load Store Error");
282 u8 rrrr = (ec >> 4) & 0xf;
284 if (!BUS_ERROR(ec) || (rrrr != 0x3 && rrrr != 0x4))
287 pr_cont(" during %s.\n", RRRR_MSG(ec));
292 pr_warning("Corrupted LS MCE info?\n");
295 void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
297 u32 ec = ERROR_CODE(regs->nbsl);
298 u32 xec = EXT_ERROR_CODE(regs->nbsl);
303 pr_emerg(" Northbridge Error, node %d", node_id);
306 * F10h, revD can disable ErrCpu[3:0] so check that first and also the
307 * value encoding has changed so interpret those differently
309 if ((boot_cpu_data.x86 == 0x10) &&
310 (boot_cpu_data.x86_model > 8)) {
311 if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
312 pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
314 pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));
318 pr_emerg("%s.\n", EXT_ERR_MSG(xec));
320 if (BUS_ERROR(ec) && nb_bus_decoder)
321 nb_bus_decoder(node_id, regs);
323 EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
325 static void amd_decode_fr_mce(u64 mc5_status)
327 /* we have only one error signature so match all fields at once. */
328 if ((mc5_status & 0xffff) == 0x0f0f)
329 pr_emerg(" FR Error: CPU Watchdog timer expire.\n");
331 pr_warning("Corrupted FR MCE info?\n");
334 static inline void amd_decode_err_code(unsigned int ec)
338 * GART errors are intended to help graphics driver developers
339 * to detect bad GART PTEs. It is recommended by AMD to disable
340 * GART table walk error reporting by default[1] (currently
341 * being disabled in mce_cpu_quirks()) and according to the
342 * comment in mce_cpu_quirks(), such GART errors can be
343 * incorrectly triggered. We may see these errors anyway and
344 * unless requested by the user, they won't be reported.
346 * [1] section 13.10.1 on BIOS and Kernel Developers Guide for
347 * AMD NPT family 0Fh processors
349 if (!report_gart_errors)
352 pr_emerg(" Transaction: %s, Cache Level %s\n",
353 TT_MSG(ec), LL_MSG(ec));
354 } else if (MEM_ERROR(ec)) {
355 pr_emerg(" Transaction: %s, Type: %s, Cache Level: %s",
356 RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
357 } else if (BUS_ERROR(ec)) {
358 pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, "
359 "Participating Processor: %s\n",
360 RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
363 pr_warning("Huh? Unknown MCE error 0x%x\n", ec);
366 static void amd_decode_mce(struct mce *m)
368 struct err_regs regs;
371 pr_emerg("MC%d_STATUS: ", m->bank);
373 pr_cont("%sorrected error, report: %s, MiscV: %svalid, "
374 "CPU context corrupt: %s",
375 ((m->status & MCI_STATUS_UC) ? "Unc" : "C"),
376 ((m->status & MCI_STATUS_EN) ? "yes" : "no"),
377 ((m->status & MCI_STATUS_MISCV) ? "" : "in"),
378 ((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
380 /* do the two bits[14:13] together */
381 ecc = m->status & (3ULL << 45);
383 pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
389 amd_decode_dc_mce(m->status);
393 amd_decode_ic_mce(m->status);
397 amd_decode_bu_mce(m->status);
401 amd_decode_ls_mce(m->status);
405 regs.nbsl = (u32) m->status;
406 regs.nbsh = (u32)(m->status >> 32);
407 regs.nbeal = (u32) m->addr;
408 regs.nbeah = (u32)(m->addr >> 32);
409 node = amd_get_nb_id(m->extcpu);
411 amd_decode_nb_mce(node, ®s, 1);
415 amd_decode_fr_mce(m->status);
422 amd_decode_err_code(m->status & 0xffff);
425 static int __init mce_amd_init(void)
428 * We can decode MCEs for Opteron and later CPUs:
430 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
431 (boot_cpu_data.x86 >= 0xf)) {
432 /* safe the default decode mce callback */
433 orig_mce_callback = x86_mce_decode_callback;
435 x86_mce_decode_callback = amd_decode_mce;
440 early_initcall(mce_amd_init);
443 static void __exit mce_amd_exit(void)
445 x86_mce_decode_callback = orig_mce_callback;
448 MODULE_DESCRIPTION("AMD MCE decoder");
449 MODULE_ALIAS("edac-mce-amd");
450 MODULE_LICENSE("GPL");
451 module_exit(mce_amd_exit);