2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
30 #include <linux/tboot.h>
31 #include "kvm_cache_regs.h"
37 #include <asm/virtext.h>
42 #define __ex(x) __kvm_handle_fault_on_reboot(x)
44 MODULE_AUTHOR("Qumranet");
45 MODULE_LICENSE("GPL");
47 static int __read_mostly bypass_guest_pf = 1;
48 module_param(bypass_guest_pf, bool, S_IRUGO);
50 static int __read_mostly enable_vpid = 1;
51 module_param_named(vpid, enable_vpid, bool, 0444);
53 static int __read_mostly flexpriority_enabled = 1;
54 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
56 static int __read_mostly enable_ept = 1;
57 module_param_named(ept, enable_ept, bool, S_IRUGO);
59 static int __read_mostly enable_unrestricted_guest = 1;
60 module_param_named(unrestricted_guest,
61 enable_unrestricted_guest, bool, S_IRUGO);
63 static int __read_mostly emulate_invalid_guest_state = 0;
64 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
66 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
67 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
68 #define KVM_GUEST_CR0_MASK \
69 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
70 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
71 (X86_CR0_WP | X86_CR0_NE)
72 #define KVM_VM_CR0_ALWAYS_ON \
73 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
74 #define KVM_CR4_GUEST_OWNED_BITS \
75 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
78 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
79 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
81 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
84 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
85 * ple_gap: upper bound on the amount of time between two successive
86 * executions of PAUSE in a loop. Also indicate if ple enabled.
87 * According to test, this time is usually small than 41 cycles.
88 * ple_window: upper bound on the amount of time a guest is allowed to execute
89 * in a PAUSE loop. Tests indicate that most spinlocks are held for
90 * less than 2^12 cycles
91 * Time is measured based on a counter that runs at the same rate as the TSC,
92 * refer SDM volume 3b section 21.6.13 & 22.1.3.
94 #define KVM_VMX_DEFAULT_PLE_GAP 41
95 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
96 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
97 module_param(ple_gap, int, S_IRUGO);
99 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
100 module_param(ple_window, int, S_IRUGO);
102 #define NR_AUTOLOAD_MSRS 1
110 struct shared_msr_entry {
117 struct kvm_vcpu vcpu;
118 struct list_head local_vcpus_link;
119 unsigned long host_rsp;
122 u32 idt_vectoring_info;
123 struct shared_msr_entry *guest_msrs;
127 u64 msr_host_kernel_gs_base;
128 u64 msr_guest_kernel_gs_base;
131 struct msr_autoload {
133 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
134 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
138 u16 fs_sel, gs_sel, ldt_sel;
139 int gs_ldt_reload_needed;
140 int fs_reload_needed;
145 struct kvm_save_segment {
150 } tr, es, ds, fs, gs;
158 bool emulation_required;
160 /* Support for vnmi-less CPUs */
161 int soft_vnmi_blocked;
163 s64 vnmi_blocked_time;
169 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
171 return container_of(vcpu, struct vcpu_vmx, vcpu);
174 static int init_rmode(struct kvm *kvm);
175 static u64 construct_eptp(unsigned long root_hpa);
177 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
178 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
179 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
181 static unsigned long *vmx_io_bitmap_a;
182 static unsigned long *vmx_io_bitmap_b;
183 static unsigned long *vmx_msr_bitmap_legacy;
184 static unsigned long *vmx_msr_bitmap_longmode;
186 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
187 static DEFINE_SPINLOCK(vmx_vpid_lock);
189 static struct vmcs_config {
193 u32 pin_based_exec_ctrl;
194 u32 cpu_based_exec_ctrl;
195 u32 cpu_based_2nd_exec_ctrl;
200 static struct vmx_capability {
205 #define VMX_SEGMENT_FIELD(seg) \
206 [VCPU_SREG_##seg] = { \
207 .selector = GUEST_##seg##_SELECTOR, \
208 .base = GUEST_##seg##_BASE, \
209 .limit = GUEST_##seg##_LIMIT, \
210 .ar_bytes = GUEST_##seg##_AR_BYTES, \
213 static struct kvm_vmx_segment_field {
218 } kvm_vmx_segment_fields[] = {
219 VMX_SEGMENT_FIELD(CS),
220 VMX_SEGMENT_FIELD(DS),
221 VMX_SEGMENT_FIELD(ES),
222 VMX_SEGMENT_FIELD(FS),
223 VMX_SEGMENT_FIELD(GS),
224 VMX_SEGMENT_FIELD(SS),
225 VMX_SEGMENT_FIELD(TR),
226 VMX_SEGMENT_FIELD(LDTR),
229 static u64 host_efer;
231 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
234 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
235 * away by decrementing the array size.
237 static const u32 vmx_msr_index[] = {
239 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
241 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
243 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
245 static inline bool is_page_fault(u32 intr_info)
247 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
248 INTR_INFO_VALID_MASK)) ==
249 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
252 static inline bool is_no_device(u32 intr_info)
254 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
255 INTR_INFO_VALID_MASK)) ==
256 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
259 static inline bool is_invalid_opcode(u32 intr_info)
261 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
262 INTR_INFO_VALID_MASK)) ==
263 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
266 static inline bool is_external_interrupt(u32 intr_info)
268 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
269 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
272 static inline bool is_machine_check(u32 intr_info)
274 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
275 INTR_INFO_VALID_MASK)) ==
276 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
279 static inline bool cpu_has_vmx_msr_bitmap(void)
281 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
284 static inline bool cpu_has_vmx_tpr_shadow(void)
286 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
289 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
291 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
294 static inline bool cpu_has_secondary_exec_ctrls(void)
296 return vmcs_config.cpu_based_exec_ctrl &
297 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
300 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
302 return vmcs_config.cpu_based_2nd_exec_ctrl &
303 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
306 static inline bool cpu_has_vmx_flexpriority(void)
308 return cpu_has_vmx_tpr_shadow() &&
309 cpu_has_vmx_virtualize_apic_accesses();
312 static inline bool cpu_has_vmx_ept_execute_only(void)
314 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
317 static inline bool cpu_has_vmx_eptp_uncacheable(void)
319 return vmx_capability.ept & VMX_EPTP_UC_BIT;
322 static inline bool cpu_has_vmx_eptp_writeback(void)
324 return vmx_capability.ept & VMX_EPTP_WB_BIT;
327 static inline bool cpu_has_vmx_ept_2m_page(void)
329 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
332 static inline bool cpu_has_vmx_ept_1g_page(void)
334 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
337 static inline bool cpu_has_vmx_invept_individual_addr(void)
339 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
342 static inline bool cpu_has_vmx_invept_context(void)
344 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
347 static inline bool cpu_has_vmx_invept_global(void)
349 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
352 static inline bool cpu_has_vmx_ept(void)
354 return vmcs_config.cpu_based_2nd_exec_ctrl &
355 SECONDARY_EXEC_ENABLE_EPT;
358 static inline bool cpu_has_vmx_unrestricted_guest(void)
360 return vmcs_config.cpu_based_2nd_exec_ctrl &
361 SECONDARY_EXEC_UNRESTRICTED_GUEST;
364 static inline bool cpu_has_vmx_ple(void)
366 return vmcs_config.cpu_based_2nd_exec_ctrl &
367 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
370 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
372 return flexpriority_enabled && irqchip_in_kernel(kvm);
375 static inline bool cpu_has_vmx_vpid(void)
377 return vmcs_config.cpu_based_2nd_exec_ctrl &
378 SECONDARY_EXEC_ENABLE_VPID;
381 static inline bool cpu_has_vmx_rdtscp(void)
383 return vmcs_config.cpu_based_2nd_exec_ctrl &
384 SECONDARY_EXEC_RDTSCP;
387 static inline bool cpu_has_virtual_nmis(void)
389 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
392 static inline bool report_flexpriority(void)
394 return flexpriority_enabled;
397 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
401 for (i = 0; i < vmx->nmsrs; ++i)
402 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
407 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
413 } operand = { vpid, 0, gva };
415 asm volatile (__ex(ASM_VMX_INVVPID)
416 /* CF==1 or ZF==1 --> rc = -1 */
418 : : "a"(&operand), "c"(ext) : "cc", "memory");
421 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
425 } operand = {eptp, gpa};
427 asm volatile (__ex(ASM_VMX_INVEPT)
428 /* CF==1 or ZF==1 --> rc = -1 */
429 "; ja 1f ; ud2 ; 1:\n"
430 : : "a" (&operand), "c" (ext) : "cc", "memory");
433 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
437 i = __find_msr_index(vmx, msr);
439 return &vmx->guest_msrs[i];
443 static void vmcs_clear(struct vmcs *vmcs)
445 u64 phys_addr = __pa(vmcs);
448 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
449 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
452 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
456 static void __vcpu_clear(void *arg)
458 struct vcpu_vmx *vmx = arg;
459 int cpu = raw_smp_processor_id();
461 if (vmx->vcpu.cpu == cpu)
462 vmcs_clear(vmx->vmcs);
463 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
464 per_cpu(current_vmcs, cpu) = NULL;
465 rdtscll(vmx->vcpu.arch.host_tsc);
466 list_del(&vmx->local_vcpus_link);
471 static void vcpu_clear(struct vcpu_vmx *vmx)
473 if (vmx->vcpu.cpu == -1)
475 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
478 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
483 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
486 static inline void ept_sync_global(void)
488 if (cpu_has_vmx_invept_global())
489 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
492 static inline void ept_sync_context(u64 eptp)
495 if (cpu_has_vmx_invept_context())
496 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
502 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
505 if (cpu_has_vmx_invept_individual_addr())
506 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
509 ept_sync_context(eptp);
513 static unsigned long vmcs_readl(unsigned long field)
517 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
518 : "=a"(value) : "d"(field) : "cc");
522 static u16 vmcs_read16(unsigned long field)
524 return vmcs_readl(field);
527 static u32 vmcs_read32(unsigned long field)
529 return vmcs_readl(field);
532 static u64 vmcs_read64(unsigned long field)
535 return vmcs_readl(field);
537 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
541 static noinline void vmwrite_error(unsigned long field, unsigned long value)
543 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
544 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
548 static void vmcs_writel(unsigned long field, unsigned long value)
552 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
553 : "=q"(error) : "a"(value), "d"(field) : "cc");
555 vmwrite_error(field, value);
558 static void vmcs_write16(unsigned long field, u16 value)
560 vmcs_writel(field, value);
563 static void vmcs_write32(unsigned long field, u32 value)
565 vmcs_writel(field, value);
568 static void vmcs_write64(unsigned long field, u64 value)
570 vmcs_writel(field, value);
571 #ifndef CONFIG_X86_64
573 vmcs_writel(field+1, value >> 32);
577 static void vmcs_clear_bits(unsigned long field, u32 mask)
579 vmcs_writel(field, vmcs_readl(field) & ~mask);
582 static void vmcs_set_bits(unsigned long field, u32 mask)
584 vmcs_writel(field, vmcs_readl(field) | mask);
587 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
591 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
592 (1u << NM_VECTOR) | (1u << DB_VECTOR);
593 if ((vcpu->guest_debug &
594 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
595 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
596 eb |= 1u << BP_VECTOR;
597 if (to_vmx(vcpu)->rmode.vm86_active)
600 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
601 if (vcpu->fpu_active)
602 eb &= ~(1u << NM_VECTOR);
603 vmcs_write32(EXCEPTION_BITMAP, eb);
606 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
609 struct msr_autoload *m = &vmx->msr_autoload;
611 for (i = 0; i < m->nr; ++i)
612 if (m->guest[i].index == msr)
618 m->guest[i] = m->guest[m->nr];
619 m->host[i] = m->host[m->nr];
620 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
621 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
624 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
625 u64 guest_val, u64 host_val)
628 struct msr_autoload *m = &vmx->msr_autoload;
630 for (i = 0; i < m->nr; ++i)
631 if (m->guest[i].index == msr)
636 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
637 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
640 m->guest[i].index = msr;
641 m->guest[i].value = guest_val;
642 m->host[i].index = msr;
643 m->host[i].value = host_val;
646 static void reload_tss(void)
649 * VT restores TR but not its size. Useless.
652 struct desc_struct *descs;
654 native_store_gdt(&gdt);
655 descs = (void *)gdt.address;
656 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
660 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
665 guest_efer = vmx->vcpu.arch.efer;
668 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
671 ignore_bits = EFER_NX | EFER_SCE;
673 ignore_bits |= EFER_LMA | EFER_LME;
674 /* SCE is meaningful only in long mode on Intel */
675 if (guest_efer & EFER_LMA)
676 ignore_bits &= ~(u64)EFER_SCE;
678 guest_efer &= ~ignore_bits;
679 guest_efer |= host_efer & ignore_bits;
680 vmx->guest_msrs[efer_offset].data = guest_efer;
681 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
683 clear_atomic_switch_msr(vmx, MSR_EFER);
684 /* On ept, can't emulate nx, and must switch nx atomically */
685 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
686 guest_efer = vmx->vcpu.arch.efer;
687 if (!(guest_efer & EFER_LMA))
688 guest_efer &= ~EFER_LME;
689 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
696 static unsigned long segment_base(u16 selector)
699 struct desc_struct *d;
700 unsigned long table_base;
703 if (!(selector & ~3))
706 native_store_gdt(&gdt);
707 table_base = gdt.address;
709 if (selector & 4) { /* from ldt */
710 u16 ldt_selector = kvm_read_ldt();
712 if (!(ldt_selector & ~3))
715 table_base = segment_base(ldt_selector);
717 d = (struct desc_struct *)(table_base + (selector & ~7));
718 v = get_desc_base(d);
720 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
721 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
726 static inline unsigned long kvm_read_tr_base(void)
729 asm("str %0" : "=g"(tr));
730 return segment_base(tr);
733 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
735 struct vcpu_vmx *vmx = to_vmx(vcpu);
738 if (vmx->host_state.loaded)
741 vmx->host_state.loaded = 1;
743 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
744 * allow segment selectors with cpl > 0 or ti == 1.
746 vmx->host_state.ldt_sel = kvm_read_ldt();
747 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
748 vmx->host_state.fs_sel = kvm_read_fs();
749 if (!(vmx->host_state.fs_sel & 7)) {
750 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
751 vmx->host_state.fs_reload_needed = 0;
753 vmcs_write16(HOST_FS_SELECTOR, 0);
754 vmx->host_state.fs_reload_needed = 1;
756 vmx->host_state.gs_sel = kvm_read_gs();
757 if (!(vmx->host_state.gs_sel & 7))
758 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
760 vmcs_write16(HOST_GS_SELECTOR, 0);
761 vmx->host_state.gs_ldt_reload_needed = 1;
765 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
766 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
768 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
769 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
773 if (is_long_mode(&vmx->vcpu)) {
774 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
775 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
778 for (i = 0; i < vmx->save_nmsrs; ++i)
779 kvm_set_shared_msr(vmx->guest_msrs[i].index,
780 vmx->guest_msrs[i].data,
781 vmx->guest_msrs[i].mask);
784 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
788 if (!vmx->host_state.loaded)
791 ++vmx->vcpu.stat.host_state_reload;
792 vmx->host_state.loaded = 0;
793 if (vmx->host_state.fs_reload_needed)
794 kvm_load_fs(vmx->host_state.fs_sel);
795 if (vmx->host_state.gs_ldt_reload_needed) {
796 kvm_load_ldt(vmx->host_state.ldt_sel);
798 * If we have to reload gs, we must take care to
799 * preserve our gs base.
801 local_irq_save(flags);
802 kvm_load_gs(vmx->host_state.gs_sel);
804 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
806 local_irq_restore(flags);
810 if (is_long_mode(&vmx->vcpu)) {
811 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
812 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
815 if (current_thread_info()->status & TS_USEDFPU)
819 static void vmx_load_host_state(struct vcpu_vmx *vmx)
822 __vmx_load_host_state(vmx);
827 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
828 * vcpu mutex is already taken.
830 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
832 struct vcpu_vmx *vmx = to_vmx(vcpu);
833 u64 phys_addr = __pa(vmx->vmcs);
834 u64 tsc_this, delta, new_offset;
836 if (vcpu->cpu != cpu) {
838 kvm_migrate_timers(vcpu);
839 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
841 list_add(&vmx->local_vcpus_link,
842 &per_cpu(vcpus_on_cpu, cpu));
846 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
849 per_cpu(current_vmcs, cpu) = vmx->vmcs;
850 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
851 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
854 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
855 vmx->vmcs, phys_addr);
858 if (vcpu->cpu != cpu) {
860 unsigned long sysenter_esp;
864 * Linux uses per-cpu TSS and GDT, so set these when switching
867 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
868 native_store_gdt(&dt);
869 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
871 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
872 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
875 * Make sure the time stamp counter is monotonous.
878 if (tsc_this < vcpu->arch.host_tsc) {
879 delta = vcpu->arch.host_tsc - tsc_this;
880 new_offset = vmcs_read64(TSC_OFFSET) + delta;
881 vmcs_write64(TSC_OFFSET, new_offset);
886 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
888 __vmx_load_host_state(to_vmx(vcpu));
891 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
895 if (vcpu->fpu_active)
897 vcpu->fpu_active = 1;
898 cr0 = vmcs_readl(GUEST_CR0);
899 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
900 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
901 vmcs_writel(GUEST_CR0, cr0);
902 update_exception_bitmap(vcpu);
903 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
904 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
907 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
909 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
911 vmx_decache_cr0_guest_bits(vcpu);
912 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
913 update_exception_bitmap(vcpu);
914 vcpu->arch.cr0_guest_owned_bits = 0;
915 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
916 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
919 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
921 unsigned long rflags, save_rflags;
923 rflags = vmcs_readl(GUEST_RFLAGS);
924 if (to_vmx(vcpu)->rmode.vm86_active) {
925 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
926 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
927 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
932 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
934 if (to_vmx(vcpu)->rmode.vm86_active) {
935 to_vmx(vcpu)->rmode.save_rflags = rflags;
936 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
938 vmcs_writel(GUEST_RFLAGS, rflags);
941 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
943 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
946 if (interruptibility & GUEST_INTR_STATE_STI)
947 ret |= KVM_X86_SHADOW_INT_STI;
948 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
949 ret |= KVM_X86_SHADOW_INT_MOV_SS;
954 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
956 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
957 u32 interruptibility = interruptibility_old;
959 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
961 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
962 interruptibility |= GUEST_INTR_STATE_MOV_SS;
963 else if (mask & KVM_X86_SHADOW_INT_STI)
964 interruptibility |= GUEST_INTR_STATE_STI;
966 if ((interruptibility != interruptibility_old))
967 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
970 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
974 rip = kvm_rip_read(vcpu);
975 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
976 kvm_rip_write(vcpu, rip);
978 /* skipping an emulated instruction also counts */
979 vmx_set_interrupt_shadow(vcpu, 0);
982 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
983 bool has_error_code, u32 error_code,
986 struct vcpu_vmx *vmx = to_vmx(vcpu);
987 u32 intr_info = nr | INTR_INFO_VALID_MASK;
989 if (has_error_code) {
990 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
991 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
994 if (vmx->rmode.vm86_active) {
995 vmx->rmode.irq.pending = true;
996 vmx->rmode.irq.vector = nr;
997 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
998 if (kvm_exception_is_soft(nr))
999 vmx->rmode.irq.rip +=
1000 vmx->vcpu.arch.event_exit_inst_len;
1001 intr_info |= INTR_TYPE_SOFT_INTR;
1002 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1003 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1004 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1008 if (kvm_exception_is_soft(nr)) {
1009 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1010 vmx->vcpu.arch.event_exit_inst_len);
1011 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1013 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1015 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1018 static bool vmx_rdtscp_supported(void)
1020 return cpu_has_vmx_rdtscp();
1024 * Swap MSR entry in host/guest MSR entry array.
1026 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1028 struct shared_msr_entry tmp;
1030 tmp = vmx->guest_msrs[to];
1031 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1032 vmx->guest_msrs[from] = tmp;
1036 * Set up the vmcs to automatically save and restore system
1037 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1038 * mode, as fiddling with msrs is very expensive.
1040 static void setup_msrs(struct vcpu_vmx *vmx)
1042 int save_nmsrs, index;
1043 unsigned long *msr_bitmap;
1045 vmx_load_host_state(vmx);
1047 #ifdef CONFIG_X86_64
1048 if (is_long_mode(&vmx->vcpu)) {
1049 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1051 move_msr_up(vmx, index, save_nmsrs++);
1052 index = __find_msr_index(vmx, MSR_LSTAR);
1054 move_msr_up(vmx, index, save_nmsrs++);
1055 index = __find_msr_index(vmx, MSR_CSTAR);
1057 move_msr_up(vmx, index, save_nmsrs++);
1058 index = __find_msr_index(vmx, MSR_TSC_AUX);
1059 if (index >= 0 && vmx->rdtscp_enabled)
1060 move_msr_up(vmx, index, save_nmsrs++);
1062 * MSR_K6_STAR is only needed on long mode guests, and only
1063 * if efer.sce is enabled.
1065 index = __find_msr_index(vmx, MSR_K6_STAR);
1066 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1067 move_msr_up(vmx, index, save_nmsrs++);
1070 index = __find_msr_index(vmx, MSR_EFER);
1071 if (index >= 0 && update_transition_efer(vmx, index))
1072 move_msr_up(vmx, index, save_nmsrs++);
1074 vmx->save_nmsrs = save_nmsrs;
1076 if (cpu_has_vmx_msr_bitmap()) {
1077 if (is_long_mode(&vmx->vcpu))
1078 msr_bitmap = vmx_msr_bitmap_longmode;
1080 msr_bitmap = vmx_msr_bitmap_legacy;
1082 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1087 * reads and returns guest's timestamp counter "register"
1088 * guest_tsc = host_tsc + tsc_offset -- 21.3
1090 static u64 guest_read_tsc(void)
1092 u64 host_tsc, tsc_offset;
1095 tsc_offset = vmcs_read64(TSC_OFFSET);
1096 return host_tsc + tsc_offset;
1100 * writes 'guest_tsc' into guest's timestamp counter "register"
1101 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1103 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1105 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1109 * Reads an msr value (of 'msr_index') into 'pdata'.
1110 * Returns 0 on success, non-0 otherwise.
1111 * Assumes vcpu_load() was already called.
1113 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1116 struct shared_msr_entry *msr;
1119 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1123 switch (msr_index) {
1124 #ifdef CONFIG_X86_64
1126 data = vmcs_readl(GUEST_FS_BASE);
1129 data = vmcs_readl(GUEST_GS_BASE);
1131 case MSR_KERNEL_GS_BASE:
1132 vmx_load_host_state(to_vmx(vcpu));
1133 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1137 return kvm_get_msr_common(vcpu, msr_index, pdata);
1139 data = guest_read_tsc();
1141 case MSR_IA32_SYSENTER_CS:
1142 data = vmcs_read32(GUEST_SYSENTER_CS);
1144 case MSR_IA32_SYSENTER_EIP:
1145 data = vmcs_readl(GUEST_SYSENTER_EIP);
1147 case MSR_IA32_SYSENTER_ESP:
1148 data = vmcs_readl(GUEST_SYSENTER_ESP);
1151 if (!to_vmx(vcpu)->rdtscp_enabled)
1153 /* Otherwise falls through */
1155 vmx_load_host_state(to_vmx(vcpu));
1156 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1158 vmx_load_host_state(to_vmx(vcpu));
1162 return kvm_get_msr_common(vcpu, msr_index, pdata);
1170 * Writes msr value into into the appropriate "register".
1171 * Returns 0 on success, non-0 otherwise.
1172 * Assumes vcpu_load() was already called.
1174 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1176 struct vcpu_vmx *vmx = to_vmx(vcpu);
1177 struct shared_msr_entry *msr;
1181 switch (msr_index) {
1183 vmx_load_host_state(vmx);
1184 ret = kvm_set_msr_common(vcpu, msr_index, data);
1186 #ifdef CONFIG_X86_64
1188 vmcs_writel(GUEST_FS_BASE, data);
1191 vmcs_writel(GUEST_GS_BASE, data);
1193 case MSR_KERNEL_GS_BASE:
1194 vmx_load_host_state(vmx);
1195 vmx->msr_guest_kernel_gs_base = data;
1198 case MSR_IA32_SYSENTER_CS:
1199 vmcs_write32(GUEST_SYSENTER_CS, data);
1201 case MSR_IA32_SYSENTER_EIP:
1202 vmcs_writel(GUEST_SYSENTER_EIP, data);
1204 case MSR_IA32_SYSENTER_ESP:
1205 vmcs_writel(GUEST_SYSENTER_ESP, data);
1209 guest_write_tsc(data, host_tsc);
1211 case MSR_IA32_CR_PAT:
1212 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1213 vmcs_write64(GUEST_IA32_PAT, data);
1214 vcpu->arch.pat = data;
1217 ret = kvm_set_msr_common(vcpu, msr_index, data);
1220 if (!vmx->rdtscp_enabled)
1222 /* Check reserved bit, higher 32 bits should be zero */
1223 if ((data >> 32) != 0)
1225 /* Otherwise falls through */
1227 msr = find_msr_entry(vmx, msr_index);
1229 vmx_load_host_state(vmx);
1233 ret = kvm_set_msr_common(vcpu, msr_index, data);
1239 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1241 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1244 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1247 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1249 case VCPU_EXREG_PDPTR:
1251 ept_save_pdptrs(vcpu);
1258 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1260 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1261 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1263 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1265 update_exception_bitmap(vcpu);
1268 static __init int cpu_has_kvm_support(void)
1270 return cpu_has_vmx();
1273 static __init int vmx_disabled_by_bios(void)
1277 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1278 if (msr & FEATURE_CONTROL_LOCKED) {
1279 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1282 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1283 && !tboot_enabled())
1288 /* locked but not enabled */
1291 static int hardware_enable(void *garbage)
1293 int cpu = raw_smp_processor_id();
1294 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1297 if (read_cr4() & X86_CR4_VMXE)
1300 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1301 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1303 test_bits = FEATURE_CONTROL_LOCKED;
1304 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1305 if (tboot_enabled())
1306 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1308 if ((old & test_bits) != test_bits) {
1309 /* enable and lock */
1310 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1312 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1313 asm volatile (ASM_VMX_VMXON_RAX
1314 : : "a"(&phys_addr), "m"(phys_addr)
1322 static void vmclear_local_vcpus(void)
1324 int cpu = raw_smp_processor_id();
1325 struct vcpu_vmx *vmx, *n;
1327 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1333 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1336 static void kvm_cpu_vmxoff(void)
1338 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1339 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1342 static void hardware_disable(void *garbage)
1344 vmclear_local_vcpus();
1348 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1349 u32 msr, u32 *result)
1351 u32 vmx_msr_low, vmx_msr_high;
1352 u32 ctl = ctl_min | ctl_opt;
1354 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1356 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1357 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1359 /* Ensure minimum (required) set of control bits are supported. */
1367 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1369 u32 vmx_msr_low, vmx_msr_high;
1370 u32 min, opt, min2, opt2;
1371 u32 _pin_based_exec_control = 0;
1372 u32 _cpu_based_exec_control = 0;
1373 u32 _cpu_based_2nd_exec_control = 0;
1374 u32 _vmexit_control = 0;
1375 u32 _vmentry_control = 0;
1377 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1378 opt = PIN_BASED_VIRTUAL_NMIS;
1379 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1380 &_pin_based_exec_control) < 0)
1383 min = CPU_BASED_HLT_EXITING |
1384 #ifdef CONFIG_X86_64
1385 CPU_BASED_CR8_LOAD_EXITING |
1386 CPU_BASED_CR8_STORE_EXITING |
1388 CPU_BASED_CR3_LOAD_EXITING |
1389 CPU_BASED_CR3_STORE_EXITING |
1390 CPU_BASED_USE_IO_BITMAPS |
1391 CPU_BASED_MOV_DR_EXITING |
1392 CPU_BASED_USE_TSC_OFFSETING |
1393 CPU_BASED_MWAIT_EXITING |
1394 CPU_BASED_MONITOR_EXITING |
1395 CPU_BASED_INVLPG_EXITING;
1396 opt = CPU_BASED_TPR_SHADOW |
1397 CPU_BASED_USE_MSR_BITMAPS |
1398 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1399 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1400 &_cpu_based_exec_control) < 0)
1402 #ifdef CONFIG_X86_64
1403 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1404 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1405 ~CPU_BASED_CR8_STORE_EXITING;
1407 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1409 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1410 SECONDARY_EXEC_WBINVD_EXITING |
1411 SECONDARY_EXEC_ENABLE_VPID |
1412 SECONDARY_EXEC_ENABLE_EPT |
1413 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1414 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1415 SECONDARY_EXEC_RDTSCP;
1416 if (adjust_vmx_controls(min2, opt2,
1417 MSR_IA32_VMX_PROCBASED_CTLS2,
1418 &_cpu_based_2nd_exec_control) < 0)
1421 #ifndef CONFIG_X86_64
1422 if (!(_cpu_based_2nd_exec_control &
1423 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1424 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1426 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1427 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1429 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1430 CPU_BASED_CR3_STORE_EXITING |
1431 CPU_BASED_INVLPG_EXITING);
1432 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1433 vmx_capability.ept, vmx_capability.vpid);
1437 #ifdef CONFIG_X86_64
1438 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1440 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1441 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1442 &_vmexit_control) < 0)
1446 opt = VM_ENTRY_LOAD_IA32_PAT;
1447 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1448 &_vmentry_control) < 0)
1451 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1453 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1454 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1457 #ifdef CONFIG_X86_64
1458 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1459 if (vmx_msr_high & (1u<<16))
1463 /* Require Write-Back (WB) memory type for VMCS accesses. */
1464 if (((vmx_msr_high >> 18) & 15) != 6)
1467 vmcs_conf->size = vmx_msr_high & 0x1fff;
1468 vmcs_conf->order = get_order(vmcs_config.size);
1469 vmcs_conf->revision_id = vmx_msr_low;
1471 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1472 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1473 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1474 vmcs_conf->vmexit_ctrl = _vmexit_control;
1475 vmcs_conf->vmentry_ctrl = _vmentry_control;
1480 static struct vmcs *alloc_vmcs_cpu(int cpu)
1482 int node = cpu_to_node(cpu);
1486 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1489 vmcs = page_address(pages);
1490 memset(vmcs, 0, vmcs_config.size);
1491 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1495 static struct vmcs *alloc_vmcs(void)
1497 return alloc_vmcs_cpu(raw_smp_processor_id());
1500 static void free_vmcs(struct vmcs *vmcs)
1502 free_pages((unsigned long)vmcs, vmcs_config.order);
1505 static void free_kvm_area(void)
1509 for_each_possible_cpu(cpu) {
1510 free_vmcs(per_cpu(vmxarea, cpu));
1511 per_cpu(vmxarea, cpu) = NULL;
1515 static __init int alloc_kvm_area(void)
1519 for_each_possible_cpu(cpu) {
1522 vmcs = alloc_vmcs_cpu(cpu);
1528 per_cpu(vmxarea, cpu) = vmcs;
1533 static __init int hardware_setup(void)
1535 if (setup_vmcs_config(&vmcs_config) < 0)
1538 if (boot_cpu_has(X86_FEATURE_NX))
1539 kvm_enable_efer_bits(EFER_NX);
1541 if (!cpu_has_vmx_vpid())
1544 if (!cpu_has_vmx_ept()) {
1546 enable_unrestricted_guest = 0;
1549 if (!cpu_has_vmx_unrestricted_guest())
1550 enable_unrestricted_guest = 0;
1552 if (!cpu_has_vmx_flexpriority())
1553 flexpriority_enabled = 0;
1555 if (!cpu_has_vmx_tpr_shadow())
1556 kvm_x86_ops->update_cr8_intercept = NULL;
1558 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1559 kvm_disable_largepages();
1561 if (!cpu_has_vmx_ple())
1564 return alloc_kvm_area();
1567 static __exit void hardware_unsetup(void)
1572 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1574 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1576 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1577 vmcs_write16(sf->selector, save->selector);
1578 vmcs_writel(sf->base, save->base);
1579 vmcs_write32(sf->limit, save->limit);
1580 vmcs_write32(sf->ar_bytes, save->ar);
1582 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1584 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1588 static void enter_pmode(struct kvm_vcpu *vcpu)
1590 unsigned long flags;
1591 struct vcpu_vmx *vmx = to_vmx(vcpu);
1593 vmx->emulation_required = 1;
1594 vmx->rmode.vm86_active = 0;
1596 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1597 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1598 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1600 flags = vmcs_readl(GUEST_RFLAGS);
1601 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1602 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1603 vmcs_writel(GUEST_RFLAGS, flags);
1605 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1606 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1608 update_exception_bitmap(vcpu);
1610 if (emulate_invalid_guest_state)
1613 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1614 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1615 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1616 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1618 vmcs_write16(GUEST_SS_SELECTOR, 0);
1619 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1621 vmcs_write16(GUEST_CS_SELECTOR,
1622 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1623 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1626 static gva_t rmode_tss_base(struct kvm *kvm)
1628 if (!kvm->arch.tss_addr) {
1629 struct kvm_memslots *slots;
1632 slots = kvm_memslots(kvm);
1633 base_gfn = kvm->memslots->memslots[0].base_gfn +
1634 kvm->memslots->memslots[0].npages - 3;
1635 return base_gfn << PAGE_SHIFT;
1637 return kvm->arch.tss_addr;
1640 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1642 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1644 save->selector = vmcs_read16(sf->selector);
1645 save->base = vmcs_readl(sf->base);
1646 save->limit = vmcs_read32(sf->limit);
1647 save->ar = vmcs_read32(sf->ar_bytes);
1648 vmcs_write16(sf->selector, save->base >> 4);
1649 vmcs_write32(sf->base, save->base & 0xfffff);
1650 vmcs_write32(sf->limit, 0xffff);
1651 vmcs_write32(sf->ar_bytes, 0xf3);
1654 static void enter_rmode(struct kvm_vcpu *vcpu)
1656 unsigned long flags;
1657 struct vcpu_vmx *vmx = to_vmx(vcpu);
1659 if (enable_unrestricted_guest)
1662 vmx->emulation_required = 1;
1663 vmx->rmode.vm86_active = 1;
1665 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1666 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1668 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1669 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1671 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1672 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1674 flags = vmcs_readl(GUEST_RFLAGS);
1675 vmx->rmode.save_rflags = flags;
1677 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1679 vmcs_writel(GUEST_RFLAGS, flags);
1680 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1681 update_exception_bitmap(vcpu);
1683 if (emulate_invalid_guest_state)
1684 goto continue_rmode;
1686 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1687 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1688 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1690 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1691 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1692 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1693 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1694 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1696 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1697 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1698 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1699 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1702 kvm_mmu_reset_context(vcpu);
1703 init_rmode(vcpu->kvm);
1706 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1708 struct vcpu_vmx *vmx = to_vmx(vcpu);
1709 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1715 * Force kernel_gs_base reloading before EFER changes, as control
1716 * of this msr depends on is_long_mode().
1718 vmx_load_host_state(to_vmx(vcpu));
1719 vcpu->arch.efer = efer;
1720 if (efer & EFER_LMA) {
1721 vmcs_write32(VM_ENTRY_CONTROLS,
1722 vmcs_read32(VM_ENTRY_CONTROLS) |
1723 VM_ENTRY_IA32E_MODE);
1726 vmcs_write32(VM_ENTRY_CONTROLS,
1727 vmcs_read32(VM_ENTRY_CONTROLS) &
1728 ~VM_ENTRY_IA32E_MODE);
1730 msr->data = efer & ~EFER_LME;
1735 #ifdef CONFIG_X86_64
1737 static void enter_lmode(struct kvm_vcpu *vcpu)
1741 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1742 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1743 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1745 vmcs_write32(GUEST_TR_AR_BYTES,
1746 (guest_tr_ar & ~AR_TYPE_MASK)
1747 | AR_TYPE_BUSY_64_TSS);
1749 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1752 static void exit_lmode(struct kvm_vcpu *vcpu)
1754 vmcs_write32(VM_ENTRY_CONTROLS,
1755 vmcs_read32(VM_ENTRY_CONTROLS)
1756 & ~VM_ENTRY_IA32E_MODE);
1757 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1762 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1764 vpid_sync_vcpu_all(to_vmx(vcpu));
1766 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1769 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1771 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1773 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1774 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1777 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1779 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1781 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1782 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1785 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1787 if (!test_bit(VCPU_EXREG_PDPTR,
1788 (unsigned long *)&vcpu->arch.regs_dirty))
1791 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1792 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1793 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1794 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1795 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1799 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1801 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1802 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1803 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1804 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1805 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1808 __set_bit(VCPU_EXREG_PDPTR,
1809 (unsigned long *)&vcpu->arch.regs_avail);
1810 __set_bit(VCPU_EXREG_PDPTR,
1811 (unsigned long *)&vcpu->arch.regs_dirty);
1814 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1816 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1818 struct kvm_vcpu *vcpu)
1820 if (!(cr0 & X86_CR0_PG)) {
1821 /* From paging/starting to nonpaging */
1822 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1823 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1824 (CPU_BASED_CR3_LOAD_EXITING |
1825 CPU_BASED_CR3_STORE_EXITING));
1826 vcpu->arch.cr0 = cr0;
1827 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1828 } else if (!is_paging(vcpu)) {
1829 /* From nonpaging to paging */
1830 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1831 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1832 ~(CPU_BASED_CR3_LOAD_EXITING |
1833 CPU_BASED_CR3_STORE_EXITING));
1834 vcpu->arch.cr0 = cr0;
1835 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1838 if (!(cr0 & X86_CR0_WP))
1839 *hw_cr0 &= ~X86_CR0_WP;
1842 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1844 struct vcpu_vmx *vmx = to_vmx(vcpu);
1845 unsigned long hw_cr0;
1847 if (enable_unrestricted_guest)
1848 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1849 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1851 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1853 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1856 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1859 #ifdef CONFIG_X86_64
1860 if (vcpu->arch.efer & EFER_LME) {
1861 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1863 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1869 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1871 if (!vcpu->fpu_active)
1872 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1874 vmcs_writel(CR0_READ_SHADOW, cr0);
1875 vmcs_writel(GUEST_CR0, hw_cr0);
1876 vcpu->arch.cr0 = cr0;
1879 static u64 construct_eptp(unsigned long root_hpa)
1883 /* TODO write the value reading from MSR */
1884 eptp = VMX_EPT_DEFAULT_MT |
1885 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1886 eptp |= (root_hpa & PAGE_MASK);
1891 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1893 unsigned long guest_cr3;
1898 eptp = construct_eptp(cr3);
1899 vmcs_write64(EPT_POINTER, eptp);
1900 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1901 vcpu->kvm->arch.ept_identity_map_addr;
1902 ept_load_pdptrs(vcpu);
1905 vmx_flush_tlb(vcpu);
1906 vmcs_writel(GUEST_CR3, guest_cr3);
1909 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1911 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1912 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1914 vcpu->arch.cr4 = cr4;
1916 if (!is_paging(vcpu)) {
1917 hw_cr4 &= ~X86_CR4_PAE;
1918 hw_cr4 |= X86_CR4_PSE;
1919 } else if (!(cr4 & X86_CR4_PAE)) {
1920 hw_cr4 &= ~X86_CR4_PAE;
1924 vmcs_writel(CR4_READ_SHADOW, cr4);
1925 vmcs_writel(GUEST_CR4, hw_cr4);
1928 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1930 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1932 return vmcs_readl(sf->base);
1935 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1936 struct kvm_segment *var, int seg)
1938 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1941 var->base = vmcs_readl(sf->base);
1942 var->limit = vmcs_read32(sf->limit);
1943 var->selector = vmcs_read16(sf->selector);
1944 ar = vmcs_read32(sf->ar_bytes);
1945 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1947 var->type = ar & 15;
1948 var->s = (ar >> 4) & 1;
1949 var->dpl = (ar >> 5) & 3;
1950 var->present = (ar >> 7) & 1;
1951 var->avl = (ar >> 12) & 1;
1952 var->l = (ar >> 13) & 1;
1953 var->db = (ar >> 14) & 1;
1954 var->g = (ar >> 15) & 1;
1955 var->unusable = (ar >> 16) & 1;
1958 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1960 if (!is_protmode(vcpu))
1963 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1966 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1969 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1976 ar = var->type & 15;
1977 ar |= (var->s & 1) << 4;
1978 ar |= (var->dpl & 3) << 5;
1979 ar |= (var->present & 1) << 7;
1980 ar |= (var->avl & 1) << 12;
1981 ar |= (var->l & 1) << 13;
1982 ar |= (var->db & 1) << 14;
1983 ar |= (var->g & 1) << 15;
1985 if (ar == 0) /* a 0 value means unusable */
1986 ar = AR_UNUSABLE_MASK;
1991 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1992 struct kvm_segment *var, int seg)
1994 struct vcpu_vmx *vmx = to_vmx(vcpu);
1995 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1998 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1999 vmx->rmode.tr.selector = var->selector;
2000 vmx->rmode.tr.base = var->base;
2001 vmx->rmode.tr.limit = var->limit;
2002 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2005 vmcs_writel(sf->base, var->base);
2006 vmcs_write32(sf->limit, var->limit);
2007 vmcs_write16(sf->selector, var->selector);
2008 if (vmx->rmode.vm86_active && var->s) {
2010 * Hack real-mode segments into vm86 compatibility.
2012 if (var->base == 0xffff0000 && var->selector == 0xf000)
2013 vmcs_writel(sf->base, 0xf0000);
2016 ar = vmx_segment_access_rights(var);
2019 * Fix the "Accessed" bit in AR field of segment registers for older
2021 * IA32 arch specifies that at the time of processor reset the
2022 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2023 * is setting it to 0 in the usedland code. This causes invalid guest
2024 * state vmexit when "unrestricted guest" mode is turned on.
2025 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2026 * tree. Newer qemu binaries with that qemu fix would not need this
2029 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2030 ar |= 0x1; /* Accessed */
2032 vmcs_write32(sf->ar_bytes, ar);
2035 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2037 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2039 *db = (ar >> 14) & 1;
2040 *l = (ar >> 13) & 1;
2043 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2045 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2046 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2049 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2051 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2052 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2055 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2057 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2058 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2061 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2063 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2064 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2067 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2069 struct kvm_segment var;
2072 vmx_get_segment(vcpu, &var, seg);
2073 ar = vmx_segment_access_rights(&var);
2075 if (var.base != (var.selector << 4))
2077 if (var.limit != 0xffff)
2085 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2087 struct kvm_segment cs;
2088 unsigned int cs_rpl;
2090 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2091 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2095 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2099 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2100 if (cs.dpl > cs_rpl)
2103 if (cs.dpl != cs_rpl)
2109 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2113 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2115 struct kvm_segment ss;
2116 unsigned int ss_rpl;
2118 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2119 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2123 if (ss.type != 3 && ss.type != 7)
2127 if (ss.dpl != ss_rpl) /* DPL != RPL */
2135 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2137 struct kvm_segment var;
2140 vmx_get_segment(vcpu, &var, seg);
2141 rpl = var.selector & SELECTOR_RPL_MASK;
2149 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2150 if (var.dpl < rpl) /* DPL < RPL */
2154 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2160 static bool tr_valid(struct kvm_vcpu *vcpu)
2162 struct kvm_segment tr;
2164 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2168 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2170 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2178 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2180 struct kvm_segment ldtr;
2182 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2186 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2196 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2198 struct kvm_segment cs, ss;
2200 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2201 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2203 return ((cs.selector & SELECTOR_RPL_MASK) ==
2204 (ss.selector & SELECTOR_RPL_MASK));
2208 * Check if guest state is valid. Returns true if valid, false if
2210 * We assume that registers are always usable
2212 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2214 /* real mode guest state checks */
2215 if (!is_protmode(vcpu)) {
2216 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2218 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2220 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2222 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2224 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2226 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2229 /* protected mode guest state checks */
2230 if (!cs_ss_rpl_check(vcpu))
2232 if (!code_segment_valid(vcpu))
2234 if (!stack_segment_valid(vcpu))
2236 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2238 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2240 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2242 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2244 if (!tr_valid(vcpu))
2246 if (!ldtr_valid(vcpu))
2250 * - Add checks on RIP
2251 * - Add checks on RFLAGS
2257 static int init_rmode_tss(struct kvm *kvm)
2259 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2264 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2267 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2268 r = kvm_write_guest_page(kvm, fn++, &data,
2269 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2272 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2275 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2279 r = kvm_write_guest_page(kvm, fn, &data,
2280 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2290 static int init_rmode_identity_map(struct kvm *kvm)
2293 pfn_t identity_map_pfn;
2298 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2299 printk(KERN_ERR "EPT: identity-mapping pagetable "
2300 "haven't been allocated!\n");
2303 if (likely(kvm->arch.ept_identity_pagetable_done))
2306 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2307 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2310 /* Set up identity-mapping pagetable for EPT in real mode */
2311 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2312 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2313 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2314 r = kvm_write_guest_page(kvm, identity_map_pfn,
2315 &tmp, i * sizeof(tmp), sizeof(tmp));
2319 kvm->arch.ept_identity_pagetable_done = true;
2325 static void seg_setup(int seg)
2327 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2330 vmcs_write16(sf->selector, 0);
2331 vmcs_writel(sf->base, 0);
2332 vmcs_write32(sf->limit, 0xffff);
2333 if (enable_unrestricted_guest) {
2335 if (seg == VCPU_SREG_CS)
2336 ar |= 0x08; /* code segment */
2340 vmcs_write32(sf->ar_bytes, ar);
2343 static int alloc_apic_access_page(struct kvm *kvm)
2345 struct kvm_userspace_memory_region kvm_userspace_mem;
2348 mutex_lock(&kvm->slots_lock);
2349 if (kvm->arch.apic_access_page)
2351 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2352 kvm_userspace_mem.flags = 0;
2353 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2354 kvm_userspace_mem.memory_size = PAGE_SIZE;
2355 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2359 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2361 mutex_unlock(&kvm->slots_lock);
2365 static int alloc_identity_pagetable(struct kvm *kvm)
2367 struct kvm_userspace_memory_region kvm_userspace_mem;
2370 mutex_lock(&kvm->slots_lock);
2371 if (kvm->arch.ept_identity_pagetable)
2373 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2374 kvm_userspace_mem.flags = 0;
2375 kvm_userspace_mem.guest_phys_addr =
2376 kvm->arch.ept_identity_map_addr;
2377 kvm_userspace_mem.memory_size = PAGE_SIZE;
2378 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2382 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2383 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2385 mutex_unlock(&kvm->slots_lock);
2389 static void allocate_vpid(struct vcpu_vmx *vmx)
2396 spin_lock(&vmx_vpid_lock);
2397 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2398 if (vpid < VMX_NR_VPIDS) {
2400 __set_bit(vpid, vmx_vpid_bitmap);
2402 spin_unlock(&vmx_vpid_lock);
2405 static void free_vpid(struct vcpu_vmx *vmx)
2409 spin_lock(&vmx_vpid_lock);
2411 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2412 spin_unlock(&vmx_vpid_lock);
2415 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2417 int f = sizeof(unsigned long);
2419 if (!cpu_has_vmx_msr_bitmap())
2423 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2424 * have the write-low and read-high bitmap offsets the wrong way round.
2425 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2427 if (msr <= 0x1fff) {
2428 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2429 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2430 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2432 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2433 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2437 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2440 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2441 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2445 * Sets up the vmcs for emulated real mode.
2447 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2449 u32 host_sysenter_cs, msr_low, msr_high;
2451 u64 host_pat, tsc_this, tsc_base;
2455 unsigned long kvm_vmx_return;
2459 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2460 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2462 if (cpu_has_vmx_msr_bitmap())
2463 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2465 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2468 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2469 vmcs_config.pin_based_exec_ctrl);
2471 exec_control = vmcs_config.cpu_based_exec_ctrl;
2472 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2473 exec_control &= ~CPU_BASED_TPR_SHADOW;
2474 #ifdef CONFIG_X86_64
2475 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2476 CPU_BASED_CR8_LOAD_EXITING;
2480 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2481 CPU_BASED_CR3_LOAD_EXITING |
2482 CPU_BASED_INVLPG_EXITING;
2483 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2485 if (cpu_has_secondary_exec_ctrls()) {
2486 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2487 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2489 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2491 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2493 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2494 enable_unrestricted_guest = 0;
2496 if (!enable_unrestricted_guest)
2497 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2499 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2500 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2504 vmcs_write32(PLE_GAP, ple_gap);
2505 vmcs_write32(PLE_WINDOW, ple_window);
2508 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2509 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2510 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2512 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2513 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2514 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2516 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2517 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2518 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2519 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2520 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2521 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2522 #ifdef CONFIG_X86_64
2523 rdmsrl(MSR_FS_BASE, a);
2524 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2525 rdmsrl(MSR_GS_BASE, a);
2526 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2528 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2529 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2532 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2534 native_store_idt(&dt);
2535 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2537 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2538 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2539 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2540 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2541 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2542 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2543 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2545 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2546 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2547 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2548 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2549 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2550 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2552 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2553 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2554 host_pat = msr_low | ((u64) msr_high << 32);
2555 vmcs_write64(HOST_IA32_PAT, host_pat);
2557 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2558 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2559 host_pat = msr_low | ((u64) msr_high << 32);
2560 /* Write the default value follow host pat */
2561 vmcs_write64(GUEST_IA32_PAT, host_pat);
2562 /* Keep arch.pat sync with GUEST_IA32_PAT */
2563 vmx->vcpu.arch.pat = host_pat;
2566 for (i = 0; i < NR_VMX_MSR; ++i) {
2567 u32 index = vmx_msr_index[i];
2568 u32 data_low, data_high;
2571 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2573 if (wrmsr_safe(index, data_low, data_high) < 0)
2575 vmx->guest_msrs[j].index = i;
2576 vmx->guest_msrs[j].data = 0;
2577 vmx->guest_msrs[j].mask = -1ull;
2581 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2583 /* 22.2.1, 20.8.1 */
2584 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2586 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2587 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2589 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2590 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2592 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2594 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2595 tsc_base = tsc_this;
2597 guest_write_tsc(0, tsc_base);
2602 static int init_rmode(struct kvm *kvm)
2604 if (!init_rmode_tss(kvm))
2606 if (!init_rmode_identity_map(kvm))
2611 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2613 struct vcpu_vmx *vmx = to_vmx(vcpu);
2617 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2618 idx = srcu_read_lock(&vcpu->kvm->srcu);
2619 if (!init_rmode(vmx->vcpu.kvm)) {
2624 vmx->rmode.vm86_active = 0;
2626 vmx->soft_vnmi_blocked = 0;
2628 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2629 kvm_set_cr8(&vmx->vcpu, 0);
2630 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2631 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2632 msr |= MSR_IA32_APICBASE_BSP;
2633 kvm_set_apic_base(&vmx->vcpu, msr);
2635 fx_init(&vmx->vcpu);
2637 seg_setup(VCPU_SREG_CS);
2639 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2640 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2642 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2643 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2644 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2646 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2647 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2650 seg_setup(VCPU_SREG_DS);
2651 seg_setup(VCPU_SREG_ES);
2652 seg_setup(VCPU_SREG_FS);
2653 seg_setup(VCPU_SREG_GS);
2654 seg_setup(VCPU_SREG_SS);
2656 vmcs_write16(GUEST_TR_SELECTOR, 0);
2657 vmcs_writel(GUEST_TR_BASE, 0);
2658 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2659 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2661 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2662 vmcs_writel(GUEST_LDTR_BASE, 0);
2663 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2664 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2666 vmcs_write32(GUEST_SYSENTER_CS, 0);
2667 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2668 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2670 vmcs_writel(GUEST_RFLAGS, 0x02);
2671 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2672 kvm_rip_write(vcpu, 0xfff0);
2674 kvm_rip_write(vcpu, 0);
2675 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2677 vmcs_writel(GUEST_DR7, 0x400);
2679 vmcs_writel(GUEST_GDTR_BASE, 0);
2680 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2682 vmcs_writel(GUEST_IDTR_BASE, 0);
2683 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2685 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2686 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2687 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2689 /* Special registers */
2690 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2694 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2696 if (cpu_has_vmx_tpr_shadow()) {
2697 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2698 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2699 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2700 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2701 vmcs_write32(TPR_THRESHOLD, 0);
2704 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2705 vmcs_write64(APIC_ACCESS_ADDR,
2706 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2709 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2711 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2712 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2713 vmx_set_cr4(&vmx->vcpu, 0);
2714 vmx_set_efer(&vmx->vcpu, 0);
2715 vmx_fpu_activate(&vmx->vcpu);
2716 update_exception_bitmap(&vmx->vcpu);
2718 vpid_sync_vcpu_all(vmx);
2722 /* HACK: Don't enable emulation on guest boot/reset */
2723 vmx->emulation_required = 0;
2726 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2730 static void enable_irq_window(struct kvm_vcpu *vcpu)
2732 u32 cpu_based_vm_exec_control;
2734 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2735 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2736 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2739 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2741 u32 cpu_based_vm_exec_control;
2743 if (!cpu_has_virtual_nmis()) {
2744 enable_irq_window(vcpu);
2748 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2749 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2750 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2753 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2755 struct vcpu_vmx *vmx = to_vmx(vcpu);
2757 int irq = vcpu->arch.interrupt.nr;
2759 trace_kvm_inj_virq(irq);
2761 ++vcpu->stat.irq_injections;
2762 if (vmx->rmode.vm86_active) {
2763 vmx->rmode.irq.pending = true;
2764 vmx->rmode.irq.vector = irq;
2765 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2766 if (vcpu->arch.interrupt.soft)
2767 vmx->rmode.irq.rip +=
2768 vmx->vcpu.arch.event_exit_inst_len;
2769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2770 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2771 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2772 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2775 intr = irq | INTR_INFO_VALID_MASK;
2776 if (vcpu->arch.interrupt.soft) {
2777 intr |= INTR_TYPE_SOFT_INTR;
2778 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2779 vmx->vcpu.arch.event_exit_inst_len);
2781 intr |= INTR_TYPE_EXT_INTR;
2782 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2785 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2787 struct vcpu_vmx *vmx = to_vmx(vcpu);
2789 if (!cpu_has_virtual_nmis()) {
2791 * Tracking the NMI-blocked state in software is built upon
2792 * finding the next open IRQ window. This, in turn, depends on
2793 * well-behaving guests: They have to keep IRQs disabled at
2794 * least as long as the NMI handler runs. Otherwise we may
2795 * cause NMI nesting, maybe breaking the guest. But as this is
2796 * highly unlikely, we can live with the residual risk.
2798 vmx->soft_vnmi_blocked = 1;
2799 vmx->vnmi_blocked_time = 0;
2802 ++vcpu->stat.nmi_injections;
2803 if (vmx->rmode.vm86_active) {
2804 vmx->rmode.irq.pending = true;
2805 vmx->rmode.irq.vector = NMI_VECTOR;
2806 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2807 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2808 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2809 INTR_INFO_VALID_MASK);
2810 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2811 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2814 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2815 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2818 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2820 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2823 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2824 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2827 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2829 if (!cpu_has_virtual_nmis())
2830 return to_vmx(vcpu)->soft_vnmi_blocked;
2831 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2834 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2836 struct vcpu_vmx *vmx = to_vmx(vcpu);
2838 if (!cpu_has_virtual_nmis()) {
2839 if (vmx->soft_vnmi_blocked != masked) {
2840 vmx->soft_vnmi_blocked = masked;
2841 vmx->vnmi_blocked_time = 0;
2845 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2846 GUEST_INTR_STATE_NMI);
2848 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2849 GUEST_INTR_STATE_NMI);
2853 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2855 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2856 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2857 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2860 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2863 struct kvm_userspace_memory_region tss_mem = {
2864 .slot = TSS_PRIVATE_MEMSLOT,
2865 .guest_phys_addr = addr,
2866 .memory_size = PAGE_SIZE * 3,
2870 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2873 kvm->arch.tss_addr = addr;
2877 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2878 int vec, u32 err_code)
2881 * Instruction with address size override prefix opcode 0x67
2882 * Cause the #SS fault with 0 error code in VM86 mode.
2884 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2885 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2888 * Forward all other exceptions that are valid in real mode.
2889 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2890 * the required debugging infrastructure rework.
2894 if (vcpu->guest_debug &
2895 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2897 kvm_queue_exception(vcpu, vec);
2901 * Update instruction length as we may reinject the exception
2902 * from user space while in guest debugging mode.
2904 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2905 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2906 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2917 kvm_queue_exception(vcpu, vec);
2924 * Trigger machine check on the host. We assume all the MSRs are already set up
2925 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2926 * We pass a fake environment to the machine check handler because we want
2927 * the guest to be always treated like user space, no matter what context
2928 * it used internally.
2930 static void kvm_machine_check(void)
2932 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2933 struct pt_regs regs = {
2934 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2935 .flags = X86_EFLAGS_IF,
2938 do_machine_check(®s, 0);
2942 static int handle_machine_check(struct kvm_vcpu *vcpu)
2944 /* already handled by vcpu_run */
2948 static int handle_exception(struct kvm_vcpu *vcpu)
2950 struct vcpu_vmx *vmx = to_vmx(vcpu);
2951 struct kvm_run *kvm_run = vcpu->run;
2952 u32 intr_info, ex_no, error_code;
2953 unsigned long cr2, rip, dr6;
2955 enum emulation_result er;
2957 vect_info = vmx->idt_vectoring_info;
2958 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2960 if (is_machine_check(intr_info))
2961 return handle_machine_check(vcpu);
2963 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2964 !is_page_fault(intr_info)) {
2965 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2966 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2967 vcpu->run->internal.ndata = 2;
2968 vcpu->run->internal.data[0] = vect_info;
2969 vcpu->run->internal.data[1] = intr_info;
2973 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2974 return 1; /* already handled by vmx_vcpu_run() */
2976 if (is_no_device(intr_info)) {
2977 vmx_fpu_activate(vcpu);
2981 if (is_invalid_opcode(intr_info)) {
2982 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2983 if (er != EMULATE_DONE)
2984 kvm_queue_exception(vcpu, UD_VECTOR);
2989 rip = kvm_rip_read(vcpu);
2990 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2991 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2992 if (is_page_fault(intr_info)) {
2993 /* EPT won't cause page fault directly */
2996 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2997 trace_kvm_page_fault(cr2, error_code);
2999 if (kvm_event_needs_reinjection(vcpu))
3000 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3001 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3004 if (vmx->rmode.vm86_active &&
3005 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3007 if (vcpu->arch.halt_request) {
3008 vcpu->arch.halt_request = 0;
3009 return kvm_emulate_halt(vcpu);
3014 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3017 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3018 if (!(vcpu->guest_debug &
3019 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3020 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3021 kvm_queue_exception(vcpu, DB_VECTOR);
3024 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3025 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3029 * Update instruction length as we may reinject #BP from
3030 * user space while in guest debugging mode. Reading it for
3031 * #DB as well causes no harm, it is not used in that case.
3033 vmx->vcpu.arch.event_exit_inst_len =
3034 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3035 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3036 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3037 kvm_run->debug.arch.exception = ex_no;
3040 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3041 kvm_run->ex.exception = ex_no;
3042 kvm_run->ex.error_code = error_code;
3048 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3050 ++vcpu->stat.irq_exits;
3054 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3056 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3060 static int handle_io(struct kvm_vcpu *vcpu)
3062 unsigned long exit_qualification;
3063 int size, in, string;
3066 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3067 string = (exit_qualification & 16) != 0;
3068 in = (exit_qualification & 8) != 0;
3070 ++vcpu->stat.io_exits;
3073 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3075 port = exit_qualification >> 16;
3076 size = (exit_qualification & 7) + 1;
3077 skip_emulated_instruction(vcpu);
3079 return kvm_fast_pio_out(vcpu, size, port);
3083 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3086 * Patch in the VMCALL instruction:
3088 hypercall[0] = 0x0f;
3089 hypercall[1] = 0x01;
3090 hypercall[2] = 0xc1;
3093 static int handle_cr(struct kvm_vcpu *vcpu)
3095 unsigned long exit_qualification, val;
3099 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3100 cr = exit_qualification & 15;
3101 reg = (exit_qualification >> 8) & 15;
3102 switch ((exit_qualification >> 4) & 3) {
3103 case 0: /* mov to cr */
3104 val = kvm_register_read(vcpu, reg);
3105 trace_kvm_cr_write(cr, val);
3108 kvm_set_cr0(vcpu, val);
3109 skip_emulated_instruction(vcpu);
3112 kvm_set_cr3(vcpu, val);
3113 skip_emulated_instruction(vcpu);
3116 kvm_set_cr4(vcpu, val);
3117 skip_emulated_instruction(vcpu);
3120 u8 cr8_prev = kvm_get_cr8(vcpu);
3121 u8 cr8 = kvm_register_read(vcpu, reg);
3122 kvm_set_cr8(vcpu, cr8);
3123 skip_emulated_instruction(vcpu);
3124 if (irqchip_in_kernel(vcpu->kvm))
3126 if (cr8_prev <= cr8)
3128 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3134 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3135 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3136 skip_emulated_instruction(vcpu);
3137 vmx_fpu_activate(vcpu);
3139 case 1: /*mov from cr*/
3142 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3143 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3144 skip_emulated_instruction(vcpu);
3147 val = kvm_get_cr8(vcpu);
3148 kvm_register_write(vcpu, reg, val);
3149 trace_kvm_cr_read(cr, val);
3150 skip_emulated_instruction(vcpu);
3155 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3156 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3157 kvm_lmsw(vcpu, val);
3159 skip_emulated_instruction(vcpu);
3164 vcpu->run->exit_reason = 0;
3165 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3166 (int)(exit_qualification >> 4) & 3, cr);
3170 static int handle_dr(struct kvm_vcpu *vcpu)
3172 unsigned long exit_qualification;
3175 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3176 if (!kvm_require_cpl(vcpu, 0))
3178 dr = vmcs_readl(GUEST_DR7);
3181 * As the vm-exit takes precedence over the debug trap, we
3182 * need to emulate the latter, either for the host or the
3183 * guest debugging itself.
3185 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3186 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3187 vcpu->run->debug.arch.dr7 = dr;
3188 vcpu->run->debug.arch.pc =
3189 vmcs_readl(GUEST_CS_BASE) +
3190 vmcs_readl(GUEST_RIP);
3191 vcpu->run->debug.arch.exception = DB_VECTOR;
3192 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3195 vcpu->arch.dr7 &= ~DR7_GD;
3196 vcpu->arch.dr6 |= DR6_BD;
3197 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3198 kvm_queue_exception(vcpu, DB_VECTOR);
3203 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3204 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3205 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3206 if (exit_qualification & TYPE_MOV_FROM_DR) {
3208 if (!kvm_get_dr(vcpu, dr, &val))
3209 kvm_register_write(vcpu, reg, val);
3211 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3212 skip_emulated_instruction(vcpu);
3216 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3218 vmcs_writel(GUEST_DR7, val);
3221 static int handle_cpuid(struct kvm_vcpu *vcpu)
3223 kvm_emulate_cpuid(vcpu);
3227 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3229 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3232 if (vmx_get_msr(vcpu, ecx, &data)) {
3233 trace_kvm_msr_read_ex(ecx);
3234 kvm_inject_gp(vcpu, 0);
3238 trace_kvm_msr_read(ecx, data);
3240 /* FIXME: handling of bits 32:63 of rax, rdx */
3241 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3242 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3243 skip_emulated_instruction(vcpu);
3247 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3249 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3250 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3251 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3253 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3254 trace_kvm_msr_write_ex(ecx, data);
3255 kvm_inject_gp(vcpu, 0);
3259 trace_kvm_msr_write(ecx, data);
3260 skip_emulated_instruction(vcpu);
3264 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3269 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3271 u32 cpu_based_vm_exec_control;
3273 /* clear pending irq */
3274 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3275 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3276 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3278 ++vcpu->stat.irq_window_exits;
3281 * If the user space waits to inject interrupts, exit as soon as
3284 if (!irqchip_in_kernel(vcpu->kvm) &&
3285 vcpu->run->request_interrupt_window &&
3286 !kvm_cpu_has_interrupt(vcpu)) {
3287 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3293 static int handle_halt(struct kvm_vcpu *vcpu)
3295 skip_emulated_instruction(vcpu);
3296 return kvm_emulate_halt(vcpu);
3299 static int handle_vmcall(struct kvm_vcpu *vcpu)
3301 skip_emulated_instruction(vcpu);
3302 kvm_emulate_hypercall(vcpu);
3306 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3308 kvm_queue_exception(vcpu, UD_VECTOR);
3312 static int handle_invlpg(struct kvm_vcpu *vcpu)
3314 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3316 kvm_mmu_invlpg(vcpu, exit_qualification);
3317 skip_emulated_instruction(vcpu);
3321 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3323 skip_emulated_instruction(vcpu);
3324 /* TODO: Add support for VT-d/pass-through device */
3328 static int handle_apic_access(struct kvm_vcpu *vcpu)
3330 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3333 static int handle_task_switch(struct kvm_vcpu *vcpu)
3335 struct vcpu_vmx *vmx = to_vmx(vcpu);
3336 unsigned long exit_qualification;
3337 bool has_error_code = false;
3340 int reason, type, idt_v;
3342 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3343 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3345 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3347 reason = (u32)exit_qualification >> 30;
3348 if (reason == TASK_SWITCH_GATE && idt_v) {
3350 case INTR_TYPE_NMI_INTR:
3351 vcpu->arch.nmi_injected = false;
3352 if (cpu_has_virtual_nmis())
3353 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3354 GUEST_INTR_STATE_NMI);
3356 case INTR_TYPE_EXT_INTR:
3357 case INTR_TYPE_SOFT_INTR:
3358 kvm_clear_interrupt_queue(vcpu);
3360 case INTR_TYPE_HARD_EXCEPTION:
3361 if (vmx->idt_vectoring_info &
3362 VECTORING_INFO_DELIVER_CODE_MASK) {
3363 has_error_code = true;
3365 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3368 case INTR_TYPE_SOFT_EXCEPTION:
3369 kvm_clear_exception_queue(vcpu);
3375 tss_selector = exit_qualification;
3377 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3378 type != INTR_TYPE_EXT_INTR &&
3379 type != INTR_TYPE_NMI_INTR))
3380 skip_emulated_instruction(vcpu);
3382 if (kvm_task_switch(vcpu, tss_selector, reason,
3383 has_error_code, error_code) == EMULATE_FAIL) {
3384 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3385 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3386 vcpu->run->internal.ndata = 0;
3390 /* clear all local breakpoint enable flags */
3391 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3394 * TODO: What about debug traps on tss switch?
3395 * Are we supposed to inject them and update dr6?
3401 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3403 unsigned long exit_qualification;
3407 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3409 if (exit_qualification & (1 << 6)) {
3410 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3414 gla_validity = (exit_qualification >> 7) & 0x3;
3415 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3416 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3417 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3418 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3419 vmcs_readl(GUEST_LINEAR_ADDRESS));
3420 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3421 (long unsigned int)exit_qualification);
3422 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3423 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3427 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3428 trace_kvm_page_fault(gpa, exit_qualification);
3429 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3432 static u64 ept_rsvd_mask(u64 spte, int level)
3437 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3438 mask |= (1ULL << i);
3441 /* bits 7:3 reserved */
3443 else if (level == 2) {
3444 if (spte & (1ULL << 7))
3445 /* 2MB ref, bits 20:12 reserved */
3448 /* bits 6:3 reserved */
3455 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3458 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3460 /* 010b (write-only) */
3461 WARN_ON((spte & 0x7) == 0x2);
3463 /* 110b (write/execute) */
3464 WARN_ON((spte & 0x7) == 0x6);
3466 /* 100b (execute-only) and value not supported by logical processor */
3467 if (!cpu_has_vmx_ept_execute_only())
3468 WARN_ON((spte & 0x7) == 0x4);
3472 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3474 if (rsvd_bits != 0) {
3475 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3476 __func__, rsvd_bits);
3480 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3481 u64 ept_mem_type = (spte & 0x38) >> 3;
3483 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3484 ept_mem_type == 7) {
3485 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3486 __func__, ept_mem_type);
3493 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3499 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3501 printk(KERN_ERR "EPT: Misconfiguration.\n");
3502 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3504 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3506 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3507 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3509 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3510 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3515 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3517 u32 cpu_based_vm_exec_control;
3519 /* clear pending NMI */
3520 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3521 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3522 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3523 ++vcpu->stat.nmi_window_exits;
3528 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3530 struct vcpu_vmx *vmx = to_vmx(vcpu);
3531 enum emulation_result err = EMULATE_DONE;
3534 while (!guest_state_valid(vcpu)) {
3535 err = emulate_instruction(vcpu, 0, 0, 0);
3537 if (err == EMULATE_DO_MMIO) {
3542 if (err != EMULATE_DONE)
3545 if (signal_pending(current))
3551 vmx->emulation_required = 0;
3557 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3558 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3560 static int handle_pause(struct kvm_vcpu *vcpu)
3562 skip_emulated_instruction(vcpu);
3563 kvm_vcpu_on_spin(vcpu);
3568 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3570 kvm_queue_exception(vcpu, UD_VECTOR);
3575 * The exit handlers return 1 if the exit was handled fully and guest execution
3576 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3577 * to be done to userspace and return 0.
3579 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3580 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3581 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3582 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3583 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3584 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3585 [EXIT_REASON_CR_ACCESS] = handle_cr,
3586 [EXIT_REASON_DR_ACCESS] = handle_dr,
3587 [EXIT_REASON_CPUID] = handle_cpuid,
3588 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3589 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3590 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3591 [EXIT_REASON_HLT] = handle_halt,
3592 [EXIT_REASON_INVLPG] = handle_invlpg,
3593 [EXIT_REASON_VMCALL] = handle_vmcall,
3594 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3595 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3596 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3597 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3598 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3599 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3600 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3601 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3602 [EXIT_REASON_VMON] = handle_vmx_insn,
3603 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3604 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3605 [EXIT_REASON_WBINVD] = handle_wbinvd,
3606 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3607 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3608 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3609 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3610 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3611 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3612 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3615 static const int kvm_vmx_max_exit_handlers =
3616 ARRAY_SIZE(kvm_vmx_exit_handlers);
3619 * The guest has exited. See if we can fix it or if we need userspace
3622 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3624 struct vcpu_vmx *vmx = to_vmx(vcpu);
3625 u32 exit_reason = vmx->exit_reason;
3626 u32 vectoring_info = vmx->idt_vectoring_info;
3628 trace_kvm_exit(exit_reason, vcpu);
3630 /* If guest state is invalid, start emulating */
3631 if (vmx->emulation_required && emulate_invalid_guest_state)
3632 return handle_invalid_guest_state(vcpu);
3634 /* Access CR3 don't cause VMExit in paging mode, so we need
3635 * to sync with guest real CR3. */
3636 if (enable_ept && is_paging(vcpu))
3637 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3639 if (unlikely(vmx->fail)) {
3640 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3641 vcpu->run->fail_entry.hardware_entry_failure_reason
3642 = vmcs_read32(VM_INSTRUCTION_ERROR);
3646 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3647 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3648 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3649 exit_reason != EXIT_REASON_TASK_SWITCH))
3650 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3651 "(0x%x) and exit reason is 0x%x\n",
3652 __func__, vectoring_info, exit_reason);
3654 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3655 if (vmx_interrupt_allowed(vcpu)) {
3656 vmx->soft_vnmi_blocked = 0;
3657 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3658 vcpu->arch.nmi_pending) {
3660 * This CPU don't support us in finding the end of an
3661 * NMI-blocked window if the guest runs with IRQs
3662 * disabled. So we pull the trigger after 1 s of
3663 * futile waiting, but inform the user about this.
3665 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3666 "state on VCPU %d after 1 s timeout\n",
3667 __func__, vcpu->vcpu_id);
3668 vmx->soft_vnmi_blocked = 0;
3672 if (exit_reason < kvm_vmx_max_exit_handlers
3673 && kvm_vmx_exit_handlers[exit_reason])
3674 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3676 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3677 vcpu->run->hw.hardware_exit_reason = exit_reason;
3682 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3684 if (irr == -1 || tpr < irr) {
3685 vmcs_write32(TPR_THRESHOLD, 0);
3689 vmcs_write32(TPR_THRESHOLD, irr);
3692 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3695 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3699 bool idtv_info_valid;
3701 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3703 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3705 /* Handle machine checks before interrupts are enabled */
3706 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3707 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3708 && is_machine_check(exit_intr_info)))
3709 kvm_machine_check();
3711 /* We need to handle NMIs before interrupts are enabled */
3712 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3713 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3714 kvm_before_handle_nmi(&vmx->vcpu);
3716 kvm_after_handle_nmi(&vmx->vcpu);
3719 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3721 if (cpu_has_virtual_nmis()) {
3722 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3723 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3725 * SDM 3: 27.7.1.2 (September 2008)
3726 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3727 * a guest IRET fault.
3728 * SDM 3: 23.2.2 (September 2008)
3729 * Bit 12 is undefined in any of the following cases:
3730 * If the VM exit sets the valid bit in the IDT-vectoring
3731 * information field.
3732 * If the VM exit is due to a double fault.
3734 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3735 vector != DF_VECTOR && !idtv_info_valid)
3736 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3737 GUEST_INTR_STATE_NMI);
3738 } else if (unlikely(vmx->soft_vnmi_blocked))
3739 vmx->vnmi_blocked_time +=
3740 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3742 vmx->vcpu.arch.nmi_injected = false;
3743 kvm_clear_exception_queue(&vmx->vcpu);
3744 kvm_clear_interrupt_queue(&vmx->vcpu);
3746 if (!idtv_info_valid)
3749 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3750 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3753 case INTR_TYPE_NMI_INTR:
3754 vmx->vcpu.arch.nmi_injected = true;
3756 * SDM 3: 27.7.1.2 (September 2008)
3757 * Clear bit "block by NMI" before VM entry if a NMI
3760 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3761 GUEST_INTR_STATE_NMI);
3763 case INTR_TYPE_SOFT_EXCEPTION:
3764 vmx->vcpu.arch.event_exit_inst_len =
3765 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3767 case INTR_TYPE_HARD_EXCEPTION:
3768 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3769 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3770 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3772 kvm_queue_exception(&vmx->vcpu, vector);
3774 case INTR_TYPE_SOFT_INTR:
3775 vmx->vcpu.arch.event_exit_inst_len =
3776 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3778 case INTR_TYPE_EXT_INTR:
3779 kvm_queue_interrupt(&vmx->vcpu, vector,
3780 type == INTR_TYPE_SOFT_INTR);
3788 * Failure to inject an interrupt should give us the information
3789 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3790 * when fetching the interrupt redirection bitmap in the real-mode
3791 * tss, this doesn't happen. So we do it ourselves.
3793 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3795 vmx->rmode.irq.pending = 0;
3796 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3798 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3799 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3800 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3801 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3804 vmx->idt_vectoring_info =
3805 VECTORING_INFO_VALID_MASK
3806 | INTR_TYPE_EXT_INTR
3807 | vmx->rmode.irq.vector;
3810 #ifdef CONFIG_X86_64
3818 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3820 struct vcpu_vmx *vmx = to_vmx(vcpu);
3822 /* Record the guest's net vcpu time for enforced NMI injections. */
3823 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3824 vmx->entry_time = ktime_get();
3826 /* Don't enter VMX if guest state is invalid, let the exit handler
3827 start emulation until we arrive back to a valid state */
3828 if (vmx->emulation_required && emulate_invalid_guest_state)
3831 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3832 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3833 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3834 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3836 /* When single-stepping over STI and MOV SS, we must clear the
3837 * corresponding interruptibility bits in the guest state. Otherwise
3838 * vmentry fails as it then expects bit 14 (BS) in pending debug
3839 * exceptions being set, but that's not correct for the guest debugging
3841 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3842 vmx_set_interrupt_shadow(vcpu, 0);
3845 /* Store host registers */
3846 "push %%"R"dx; push %%"R"bp;"
3848 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3850 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3851 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3853 /* Reload cr2 if changed */
3854 "mov %c[cr2](%0), %%"R"ax \n\t"
3855 "mov %%cr2, %%"R"dx \n\t"
3856 "cmp %%"R"ax, %%"R"dx \n\t"
3858 "mov %%"R"ax, %%cr2 \n\t"
3860 /* Check if vmlaunch of vmresume is needed */
3861 "cmpl $0, %c[launched](%0) \n\t"
3862 /* Load guest registers. Don't clobber flags. */
3863 "mov %c[rax](%0), %%"R"ax \n\t"
3864 "mov %c[rbx](%0), %%"R"bx \n\t"
3865 "mov %c[rdx](%0), %%"R"dx \n\t"
3866 "mov %c[rsi](%0), %%"R"si \n\t"
3867 "mov %c[rdi](%0), %%"R"di \n\t"
3868 "mov %c[rbp](%0), %%"R"bp \n\t"
3869 #ifdef CONFIG_X86_64
3870 "mov %c[r8](%0), %%r8 \n\t"
3871 "mov %c[r9](%0), %%r9 \n\t"
3872 "mov %c[r10](%0), %%r10 \n\t"
3873 "mov %c[r11](%0), %%r11 \n\t"
3874 "mov %c[r12](%0), %%r12 \n\t"
3875 "mov %c[r13](%0), %%r13 \n\t"
3876 "mov %c[r14](%0), %%r14 \n\t"
3877 "mov %c[r15](%0), %%r15 \n\t"
3879 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3881 /* Enter guest mode */
3882 "jne .Llaunched \n\t"
3883 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3884 "jmp .Lkvm_vmx_return \n\t"
3885 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3886 ".Lkvm_vmx_return: "
3887 /* Save guest registers, load host registers, keep flags */
3888 "xchg %0, (%%"R"sp) \n\t"
3889 "mov %%"R"ax, %c[rax](%0) \n\t"
3890 "mov %%"R"bx, %c[rbx](%0) \n\t"
3891 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3892 "mov %%"R"dx, %c[rdx](%0) \n\t"
3893 "mov %%"R"si, %c[rsi](%0) \n\t"
3894 "mov %%"R"di, %c[rdi](%0) \n\t"
3895 "mov %%"R"bp, %c[rbp](%0) \n\t"
3896 #ifdef CONFIG_X86_64
3897 "mov %%r8, %c[r8](%0) \n\t"
3898 "mov %%r9, %c[r9](%0) \n\t"
3899 "mov %%r10, %c[r10](%0) \n\t"
3900 "mov %%r11, %c[r11](%0) \n\t"
3901 "mov %%r12, %c[r12](%0) \n\t"
3902 "mov %%r13, %c[r13](%0) \n\t"
3903 "mov %%r14, %c[r14](%0) \n\t"
3904 "mov %%r15, %c[r15](%0) \n\t"
3906 "mov %%cr2, %%"R"ax \n\t"
3907 "mov %%"R"ax, %c[cr2](%0) \n\t"
3909 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3910 "setbe %c[fail](%0) \n\t"
3911 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3912 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3913 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3914 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3915 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3916 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3917 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3918 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3919 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3920 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3921 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3922 #ifdef CONFIG_X86_64
3923 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3924 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3925 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3926 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3927 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3928 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3929 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3930 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3932 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3934 , R"bx", R"di", R"si"
3935 #ifdef CONFIG_X86_64
3936 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3940 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3941 | (1 << VCPU_EXREG_PDPTR));
3942 vcpu->arch.regs_dirty = 0;
3944 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3945 if (vmx->rmode.irq.pending)
3946 fixup_rmode_irq(vmx);
3948 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3951 vmx_complete_interrupts(vmx);
3957 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3959 struct vcpu_vmx *vmx = to_vmx(vcpu);
3963 free_vmcs(vmx->vmcs);
3968 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3970 struct vcpu_vmx *vmx = to_vmx(vcpu);
3973 vmx_free_vmcs(vcpu);
3974 kfree(vmx->guest_msrs);
3975 kvm_vcpu_uninit(vcpu);
3976 kmem_cache_free(kvm_vcpu_cache, vmx);
3979 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3982 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3986 return ERR_PTR(-ENOMEM);
3990 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3994 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3995 if (!vmx->guest_msrs) {
4000 vmx->vmcs = alloc_vmcs();
4004 vmcs_clear(vmx->vmcs);
4007 vmx_vcpu_load(&vmx->vcpu, cpu);
4008 err = vmx_vcpu_setup(vmx);
4009 vmx_vcpu_put(&vmx->vcpu);
4013 if (vm_need_virtualize_apic_accesses(kvm))
4014 if (alloc_apic_access_page(kvm) != 0)
4018 if (!kvm->arch.ept_identity_map_addr)
4019 kvm->arch.ept_identity_map_addr =
4020 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4021 if (alloc_identity_pagetable(kvm) != 0)
4028 free_vmcs(vmx->vmcs);
4030 kfree(vmx->guest_msrs);
4032 kvm_vcpu_uninit(&vmx->vcpu);
4035 kmem_cache_free(kvm_vcpu_cache, vmx);
4036 return ERR_PTR(err);
4039 static void __init vmx_check_processor_compat(void *rtn)
4041 struct vmcs_config vmcs_conf;
4044 if (setup_vmcs_config(&vmcs_conf) < 0)
4046 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4047 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4048 smp_processor_id());
4053 static int get_ept_level(void)
4055 return VMX_EPT_DEFAULT_GAW + 1;
4058 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4062 /* For VT-d and EPT combination
4063 * 1. MMIO: always map as UC
4065 * a. VT-d without snooping control feature: can't guarantee the
4066 * result, try to trust guest.
4067 * b. VT-d with snooping control feature: snooping control feature of
4068 * VT-d engine can guarantee the cache correctness. Just set it
4069 * to WB to keep consistent with host. So the same as item 3.
4070 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4071 * consistent with host MTRR
4074 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4075 else if (vcpu->kvm->arch.iommu_domain &&
4076 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4077 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4078 VMX_EPT_MT_EPTE_SHIFT;
4080 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4086 #define _ER(x) { EXIT_REASON_##x, #x }
4088 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4090 _ER(EXTERNAL_INTERRUPT),
4092 _ER(PENDING_INTERRUPT),
4112 _ER(IO_INSTRUCTION),
4115 _ER(MWAIT_INSTRUCTION),
4116 _ER(MONITOR_INSTRUCTION),
4117 _ER(PAUSE_INSTRUCTION),
4118 _ER(MCE_DURING_VMENTRY),
4119 _ER(TPR_BELOW_THRESHOLD),
4129 static int vmx_get_lpage_level(void)
4131 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4132 return PT_DIRECTORY_LEVEL;
4134 /* For shadow and EPT supported 1GB page */
4135 return PT_PDPE_LEVEL;
4138 static inline u32 bit(int bitno)
4140 return 1 << (bitno & 31);
4143 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4145 struct kvm_cpuid_entry2 *best;
4146 struct vcpu_vmx *vmx = to_vmx(vcpu);
4149 vmx->rdtscp_enabled = false;
4150 if (vmx_rdtscp_supported()) {
4151 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4152 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4153 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4154 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4155 vmx->rdtscp_enabled = true;
4157 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4158 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4165 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4169 static struct kvm_x86_ops vmx_x86_ops = {
4170 .cpu_has_kvm_support = cpu_has_kvm_support,
4171 .disabled_by_bios = vmx_disabled_by_bios,
4172 .hardware_setup = hardware_setup,
4173 .hardware_unsetup = hardware_unsetup,
4174 .check_processor_compatibility = vmx_check_processor_compat,
4175 .hardware_enable = hardware_enable,
4176 .hardware_disable = hardware_disable,
4177 .cpu_has_accelerated_tpr = report_flexpriority,
4179 .vcpu_create = vmx_create_vcpu,
4180 .vcpu_free = vmx_free_vcpu,
4181 .vcpu_reset = vmx_vcpu_reset,
4183 .prepare_guest_switch = vmx_save_host_state,
4184 .vcpu_load = vmx_vcpu_load,
4185 .vcpu_put = vmx_vcpu_put,
4187 .set_guest_debug = set_guest_debug,
4188 .get_msr = vmx_get_msr,
4189 .set_msr = vmx_set_msr,
4190 .get_segment_base = vmx_get_segment_base,
4191 .get_segment = vmx_get_segment,
4192 .set_segment = vmx_set_segment,
4193 .get_cpl = vmx_get_cpl,
4194 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4195 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4196 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4197 .set_cr0 = vmx_set_cr0,
4198 .set_cr3 = vmx_set_cr3,
4199 .set_cr4 = vmx_set_cr4,
4200 .set_efer = vmx_set_efer,
4201 .get_idt = vmx_get_idt,
4202 .set_idt = vmx_set_idt,
4203 .get_gdt = vmx_get_gdt,
4204 .set_gdt = vmx_set_gdt,
4205 .set_dr7 = vmx_set_dr7,
4206 .cache_reg = vmx_cache_reg,
4207 .get_rflags = vmx_get_rflags,
4208 .set_rflags = vmx_set_rflags,
4209 .fpu_activate = vmx_fpu_activate,
4210 .fpu_deactivate = vmx_fpu_deactivate,
4212 .tlb_flush = vmx_flush_tlb,
4214 .run = vmx_vcpu_run,
4215 .handle_exit = vmx_handle_exit,
4216 .skip_emulated_instruction = skip_emulated_instruction,
4217 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4218 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4219 .patch_hypercall = vmx_patch_hypercall,
4220 .set_irq = vmx_inject_irq,
4221 .set_nmi = vmx_inject_nmi,
4222 .queue_exception = vmx_queue_exception,
4223 .interrupt_allowed = vmx_interrupt_allowed,
4224 .nmi_allowed = vmx_nmi_allowed,
4225 .get_nmi_mask = vmx_get_nmi_mask,
4226 .set_nmi_mask = vmx_set_nmi_mask,
4227 .enable_nmi_window = enable_nmi_window,
4228 .enable_irq_window = enable_irq_window,
4229 .update_cr8_intercept = update_cr8_intercept,
4231 .set_tss_addr = vmx_set_tss_addr,
4232 .get_tdp_level = get_ept_level,
4233 .get_mt_mask = vmx_get_mt_mask,
4235 .exit_reasons_str = vmx_exit_reasons_str,
4236 .get_lpage_level = vmx_get_lpage_level,
4238 .cpuid_update = vmx_cpuid_update,
4240 .rdtscp_supported = vmx_rdtscp_supported,
4242 .set_supported_cpuid = vmx_set_supported_cpuid,
4245 static int __init vmx_init(void)
4249 rdmsrl_safe(MSR_EFER, &host_efer);
4251 for (i = 0; i < NR_VMX_MSR; ++i)
4252 kvm_define_shared_msr(i, vmx_msr_index[i]);
4254 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4255 if (!vmx_io_bitmap_a)
4258 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4259 if (!vmx_io_bitmap_b) {
4264 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4265 if (!vmx_msr_bitmap_legacy) {
4270 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4271 if (!vmx_msr_bitmap_longmode) {
4277 * Allow direct access to the PC debug port (it is often used for I/O
4278 * delays, but the vmexits simply slow things down).
4280 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4281 clear_bit(0x80, vmx_io_bitmap_a);
4283 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4285 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4286 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4288 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4290 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4291 __alignof__(struct vcpu_vmx), THIS_MODULE);
4295 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4296 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4297 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4298 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4299 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4300 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4303 bypass_guest_pf = 0;
4304 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4305 VMX_EPT_WRITABLE_MASK);
4306 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4307 VMX_EPT_EXECUTABLE_MASK);
4312 if (bypass_guest_pf)
4313 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4318 free_page((unsigned long)vmx_msr_bitmap_longmode);
4320 free_page((unsigned long)vmx_msr_bitmap_legacy);
4322 free_page((unsigned long)vmx_io_bitmap_b);
4324 free_page((unsigned long)vmx_io_bitmap_a);
4328 static void __exit vmx_exit(void)
4330 free_page((unsigned long)vmx_msr_bitmap_legacy);
4331 free_page((unsigned long)vmx_msr_bitmap_longmode);
4332 free_page((unsigned long)vmx_io_bitmap_b);
4333 free_page((unsigned long)vmx_io_bitmap_a);
4338 module_init(vmx_init)
4339 module_exit(vmx_exit)