arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/highmem.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27
  28 #include <asm/apic.h>
  29 #include <asm/stacktrace.h>
  30 #include <asm/nmi.h>
  31
  32 static u64 perf_event_mask __read_mostly;
  33
  34 /* The maximal number of PEBS events: */
  35 #define MAX_PEBS_EVENTS 4
  36
  37 /* The size of a BTS record in bytes: */
  38 #define BTS_RECORD_SIZE         24
  39
  40 /* The size of a per-cpu BTS buffer in bytes: */
  41 #define BTS_BUFFER_SIZE         (BTS_RECORD_SIZE * 2048)
  42
  43 /* The BTS overflow threshold in bytes from the end of the buffer: */
  44 #define BTS_OVFL_TH             (BTS_RECORD_SIZE * 128)
  45
  46
  47 /*
  48  * Bits in the debugctlmsr controlling branch tracing.
  49  */
  50 #define X86_DEBUGCTL_TR                 (1 << 6)
  51 #define X86_DEBUGCTL_BTS                (1 << 7)
  52 #define X86_DEBUGCTL_BTINT              (1 << 8)
  53 #define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
  54 #define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
  55
  56 /*
  57  * A debug store configuration.
  58  *
  59  * We only support architectures that use 64bit fields.
  60  */
  61 struct debug_store {
  62         u64     bts_buffer_base;
  63         u64     bts_index;
  64         u64     bts_absolute_maximum;
  65         u64     bts_interrupt_threshold;
  66         u64     pebs_buffer_base;
  67         u64     pebs_index;
  68         u64     pebs_absolute_maximum;
  69         u64     pebs_interrupt_threshold;
  70         u64     pebs_event_reset[MAX_PEBS_EVENTS];
  71 };
  72
  73 struct event_constraint {
  74         union {
  75                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  76                 u64             idxmsk64;
  77         };
  78         u64     code;
  79         u64     cmask;
  80         int     weight;
  81 };
  82
  83 struct amd_nb {
  84         int nb_id;  /* NorthBridge id */
  85         int refcnt; /* reference count */
  86         struct perf_event *owners[X86_PMC_IDX_MAX];
  87         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  88 };
  89
  90 struct cpu_hw_events {
  91         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
  92         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  93         unsigned long           interrupts;
  94         int                     enabled;
  95         struct debug_store      *ds;
  96
  97         int                     n_events;
  98         int                     n_added;
  99         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 100         u64                     tags[X86_PMC_IDX_MAX];
 101         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 102         struct amd_nb           *amd_nb;
 103 };
 104
 105 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 106         { .idxmsk64 = (n) },            \
 107         .code = (c),                    \
 108         .cmask = (m),                   \
 109         .weight = (w),                  \
 110 }
 111
 112 #define EVENT_CONSTRAINT(c, n, m)       \
 113         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 114
 115 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 116         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
 117
 118 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 119         EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
 120
 121 #define EVENT_CONSTRAINT_END            \
 122         EVENT_CONSTRAINT(0, 0, 0)
 123
 124 #define for_each_event_constraint(e, c) \
 125         for ((e) = (c); (e)->cmask; (e)++)
 126
 127 /*
 128  * struct x86_pmu - generic x86 pmu
 129  */
 130 struct x86_pmu {
 131         const char      *name;
 132         int             version;
 133         int             (*handle_irq)(struct pt_regs *);
 134         void            (*disable_all)(void);
 135         void            (*enable_all)(void);
 136         void            (*enable)(struct hw_perf_event *, int);
 137         void            (*disable)(struct hw_perf_event *, int);
 138         unsigned        eventsel;
 139         unsigned        perfctr;
 140         u64             (*event_map)(int);
 141         u64             (*raw_event)(u64);
 142         int             max_events;
 143         int             num_events;
 144         int             num_events_fixed;
 145         int             event_bits;
 146         u64             event_mask;
 147         int             apic;
 148         u64             max_period;
 149         u64             intel_ctrl;
 150         void            (*enable_bts)(u64 config);
 151         void            (*disable_bts)(void);
 152
 153         struct event_constraint *
 154                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 155                                                  struct perf_event *event);
 156
 157         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 158                                                  struct perf_event *event);
 159         struct event_constraint *event_constraints;
 160
 161         void            (*cpu_prepare)(int cpu);
 162         void            (*cpu_starting)(int cpu);
 163         void            (*cpu_dying)(int cpu);
 164         void            (*cpu_dead)(int cpu);
 165 };
 166
 167 static struct x86_pmu x86_pmu __read_mostly;
 168
 169 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 170         .enabled = 1,
 171 };
 172
 173 static int x86_perf_event_set_period(struct perf_event *event);
 174
 175 /*
 176  * Generalized hw caching related hw_event table, filled
 177  * in on a per model basis. A value of 0 means
 178  * 'not supported', -1 means 'hw_event makes no sense on
 179  * this CPU', any other value means the raw hw_event
 180  * ID.
 181  */
 182
 183 #define C(x) PERF_COUNT_HW_CACHE_##x
 184
 185 static u64 __read_mostly hw_cache_event_ids
 186                                 [PERF_COUNT_HW_CACHE_MAX]
 187                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 188                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 189
 190 /*
 191  * Propagate event elapsed time into the generic event.
 192  * Can only be executed on the CPU where the event is active.
 193  * Returns the delta events processed.
 194  */
 195 static u64
 196 x86_perf_event_update(struct perf_event *event)
 197 {
 198         struct hw_perf_event *hwc = &event->hw;
 199         int shift = 64 - x86_pmu.event_bits;
 200         u64 prev_raw_count, new_raw_count;
 201         int idx = hwc->idx;
 202         s64 delta;
 203
 204         if (idx == X86_PMC_IDX_FIXED_BTS)
 205                 return 0;
 206
 207         /*
 208          * Careful: an NMI might modify the previous event value.
 209          *
 210          * Our tactic to handle this is to first atomically read and
 211          * exchange a new raw count - then add that new-prev delta
 212          * count to the generic event atomically:
 213          */
 214 again:
 215         prev_raw_count = atomic64_read(&hwc->prev_count);
 216         rdmsrl(hwc->event_base + idx, new_raw_count);
 217
 218         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 219                                         new_raw_count) != prev_raw_count)
 220                 goto again;
 221
 222         /*
 223          * Now we have the new raw value and have updated the prev
 224          * timestamp already. We can now calculate the elapsed delta
 225          * (event-)time and add that to the generic event.
 226          *
 227          * Careful, not all hw sign-extends above the physical width
 228          * of the count.
 229          */
 230         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 231         delta >>= shift;
 232
 233         atomic64_add(delta, &event->count);
 234         atomic64_sub(delta, &hwc->period_left);
 235
 236         return new_raw_count;
 237 }
 238
 239 static atomic_t active_events;
 240 static DEFINE_MUTEX(pmc_reserve_mutex);
 241
 242 static bool reserve_pmc_hardware(void)
 243 {
 244 #ifdef CONFIG_X86_LOCAL_APIC
 245         int i;
 246
 247         if (nmi_watchdog == NMI_LOCAL_APIC)
 248                 disable_lapic_nmi_watchdog();
 249
 250         for (i = 0; i < x86_pmu.num_events; i++) {
 251                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 252                         goto perfctr_fail;
 253         }
 254
 255         for (i = 0; i < x86_pmu.num_events; i++) {
 256                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 257                         goto eventsel_fail;
 258         }
 259 #endif
 260
 261         return true;
 262
 263 #ifdef CONFIG_X86_LOCAL_APIC
 264 eventsel_fail:
 265         for (i--; i >= 0; i--)
 266                 release_evntsel_nmi(x86_pmu.eventsel + i);
 267
 268         i = x86_pmu.num_events;
 269
 270 perfctr_fail:
 271         for (i--; i >= 0; i--)
 272                 release_perfctr_nmi(x86_pmu.perfctr + i);
 273
 274         if (nmi_watchdog == NMI_LOCAL_APIC)
 275                 enable_lapic_nmi_watchdog();
 276
 277         return false;
 278 #endif
 279 }
 280
 281 static void release_pmc_hardware(void)
 282 {
 283 #ifdef CONFIG_X86_LOCAL_APIC
 284         int i;
 285
 286         for (i = 0; i < x86_pmu.num_events; i++) {
 287                 release_perfctr_nmi(x86_pmu.perfctr + i);
 288                 release_evntsel_nmi(x86_pmu.eventsel + i);
 289         }
 290
 291         if (nmi_watchdog == NMI_LOCAL_APIC)
 292                 enable_lapic_nmi_watchdog();
 293 #endif
 294 }
 295
 296 static inline bool bts_available(void)
 297 {
 298         return x86_pmu.enable_bts != NULL;
 299 }
 300
 301 static void init_debug_store_on_cpu(int cpu)
 302 {
 303         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 304
 305         if (!ds)
 306                 return;
 307
 308         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 309                      (u32)((u64)(unsigned long)ds),
 310                      (u32)((u64)(unsigned long)ds >> 32));
 311 }
 312
 313 static void fini_debug_store_on_cpu(int cpu)
 314 {
 315         if (!per_cpu(cpu_hw_events, cpu).ds)
 316                 return;
 317
 318         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 319 }
 320
 321 static void release_bts_hardware(void)
 322 {
 323         int cpu;
 324
 325         if (!bts_available())
 326                 return;
 327
 328         get_online_cpus();
 329
 330         for_each_online_cpu(cpu)
 331                 fini_debug_store_on_cpu(cpu);
 332
 333         for_each_possible_cpu(cpu) {
 334                 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 335
 336                 if (!ds)
 337                         continue;
 338
 339                 per_cpu(cpu_hw_events, cpu).ds = NULL;
 340
 341                 kfree((void *)(unsigned long)ds->bts_buffer_base);
 342                 kfree(ds);
 343         }
 344
 345         put_online_cpus();
 346 }
 347
 348 static int reserve_bts_hardware(void)
 349 {
 350         int cpu, err = 0;
 351
 352         if (!bts_available())
 353                 return 0;
 354
 355         get_online_cpus();
 356
 357         for_each_possible_cpu(cpu) {
 358                 struct debug_store *ds;
 359                 void *buffer;
 360
 361                 err = -ENOMEM;
 362                 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
 363                 if (unlikely(!buffer))
 364                         break;
 365
 366                 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
 367                 if (unlikely(!ds)) {
 368                         kfree(buffer);
 369                         break;
 370                 }
 371
 372                 ds->bts_buffer_base = (u64)(unsigned long)buffer;
 373                 ds->bts_index = ds->bts_buffer_base;
 374                 ds->bts_absolute_maximum =
 375                         ds->bts_buffer_base + BTS_BUFFER_SIZE;
 376                 ds->bts_interrupt_threshold =
 377                         ds->bts_absolute_maximum - BTS_OVFL_TH;
 378
 379                 per_cpu(cpu_hw_events, cpu).ds = ds;
 380                 err = 0;
 381         }
 382
 383         if (err)
 384                 release_bts_hardware();
 385         else {
 386                 for_each_online_cpu(cpu)
 387                         init_debug_store_on_cpu(cpu);
 388         }
 389
 390         put_online_cpus();
 391
 392         return err;
 393 }
 394
 395 static void hw_perf_event_destroy(struct perf_event *event)
 396 {
 397         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 398                 release_pmc_hardware();
 399                 release_bts_hardware();
 400                 mutex_unlock(&pmc_reserve_mutex);
 401         }
 402 }
 403
 404 static inline int x86_pmu_initialized(void)
 405 {
 406         return x86_pmu.handle_irq != NULL;
 407 }
 408
 409 static inline int
 410 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 411 {
 412         unsigned int cache_type, cache_op, cache_result;
 413         u64 config, val;
 414
 415         config = attr->config;
 416
 417         cache_type = (config >>  0) & 0xff;
 418         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 419                 return -EINVAL;
 420
 421         cache_op = (config >>  8) & 0xff;
 422         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 423                 return -EINVAL;
 424
 425         cache_result = (config >> 16) & 0xff;
 426         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 427                 return -EINVAL;
 428
 429         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 430
 431         if (val == 0)
 432                 return -ENOENT;
 433
 434         if (val == -1)
 435                 return -EINVAL;
 436
 437         hwc->config |= val;
 438
 439         return 0;
 440 }
 441
 442 /*
 443  * Setup the hardware configuration for a given attr_type
 444  */
 445 static int __hw_perf_event_init(struct perf_event *event)
 446 {
 447         struct perf_event_attr *attr = &event->attr;
 448         struct hw_perf_event *hwc = &event->hw;
 449         u64 config;
 450         int err;
 451
 452         if (!x86_pmu_initialized())
 453                 return -ENODEV;
 454
 455         err = 0;
 456         if (!atomic_inc_not_zero(&active_events)) {
 457                 mutex_lock(&pmc_reserve_mutex);
 458                 if (atomic_read(&active_events) == 0) {
 459                         if (!reserve_pmc_hardware())
 460                                 err = -EBUSY;
 461                         else
 462                                 err = reserve_bts_hardware();
 463                 }
 464                 if (!err)
 465                         atomic_inc(&active_events);
 466                 mutex_unlock(&pmc_reserve_mutex);
 467         }
 468         if (err)
 469                 return err;
 470
 471         event->destroy = hw_perf_event_destroy;
 472
 473         /*
 474          * Generate PMC IRQs:
 475          * (keep 'enabled' bit clear for now)
 476          */
 477         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
 478
 479         hwc->idx = -1;
 480         hwc->last_cpu = -1;
 481         hwc->last_tag = ~0ULL;
 482
 483         /*
 484          * Count user and OS events unless requested not to.
 485          */
 486         if (!attr->exclude_user)
 487                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
 488         if (!attr->exclude_kernel)
 489                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
 490
 491         if (!hwc->sample_period) {
 492                 hwc->sample_period = x86_pmu.max_period;
 493                 hwc->last_period = hwc->sample_period;
 494                 atomic64_set(&hwc->period_left, hwc->sample_period);
 495         } else {
 496                 /*
 497                  * If we have a PMU initialized but no APIC
 498                  * interrupts, we cannot sample hardware
 499                  * events (user-space has to fall back and
 500                  * sample via a hrtimer based software event):
 501                  */
 502                 if (!x86_pmu.apic)
 503                         return -EOPNOTSUPP;
 504         }
 505
 506         /*
 507          * Raw hw_event type provide the config in the hw_event structure
 508          */
 509         if (attr->type == PERF_TYPE_RAW) {
 510                 hwc->config |= x86_pmu.raw_event(attr->config);
 511                 if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) &&
 512                     perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
 513                         return -EACCES;
 514                 return 0;
 515         }
 516
 517         if (attr->type == PERF_TYPE_HW_CACHE)
 518                 return set_ext_hw_attr(hwc, attr);
 519
 520         if (attr->config >= x86_pmu.max_events)
 521                 return -EINVAL;
 522
 523         /*
 524          * The generic map:
 525          */
 526         config = x86_pmu.event_map(attr->config);
 527
 528         if (config == 0)
 529                 return -ENOENT;
 530
 531         if (config == -1LL)
 532                 return -EINVAL;
 533
 534         /*
 535          * Branch tracing:
 536          */
 537         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 538             (hwc->sample_period == 1)) {
 539                 /* BTS is not supported by this architecture. */
 540                 if (!bts_available())
 541                         return -EOPNOTSUPP;
 542
 543                 /* BTS is currently only allowed for user-mode. */
 544                 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
 545                         return -EOPNOTSUPP;
 546         }
 547
 548         hwc->config |= config;
 549
 550         return 0;
 551 }
 552
 553 static void x86_pmu_disable_all(void)
 554 {
 555         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 556         int idx;
 557
 558         for (idx = 0; idx < x86_pmu.num_events; idx++) {
 559                 u64 val;
 560
 561                 if (!test_bit(idx, cpuc->active_mask))
 562                         continue;
 563                 rdmsrl(x86_pmu.eventsel + idx, val);
 564                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 565                         continue;
 566                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 567                 wrmsrl(x86_pmu.eventsel + idx, val);
 568         }
 569 }
 570
 571 void hw_perf_disable(void)
 572 {
 573         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 574
 575         if (!x86_pmu_initialized())
 576                 return;
 577
 578         if (!cpuc->enabled)
 579                 return;
 580
 581         cpuc->n_added = 0;
 582         cpuc->enabled = 0;
 583         barrier();
 584
 585         x86_pmu.disable_all();
 586 }
 587
 588 static void x86_pmu_enable_all(void)
 589 {
 590         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 591         int idx;
 592
 593         for (idx = 0; idx < x86_pmu.num_events; idx++) {
 594                 struct perf_event *event = cpuc->events[idx];
 595                 u64 val;
 596
 597                 if (!test_bit(idx, cpuc->active_mask))
 598                         continue;
 599
 600                 val = event->hw.config;
 601                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 602                 wrmsrl(x86_pmu.eventsel + idx, val);
 603         }
 604 }
 605
 606 static const struct pmu pmu;
 607
 608 static inline int is_x86_event(struct perf_event *event)
 609 {
 610         return event->pmu == &pmu;
 611 }
 612
 613 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 614 {
 615         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 616         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 617         int i, j, w, wmax, num = 0;
 618         struct hw_perf_event *hwc;
 619
 620         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 621
 622         for (i = 0; i < n; i++) {
 623                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 624                 constraints[i] = c;
 625         }
 626
 627         /*
 628          * fastpath, try to reuse previous register
 629          */
 630         for (i = 0; i < n; i++) {
 631                 hwc = &cpuc->event_list[i]->hw;
 632                 c = constraints[i];
 633
 634                 /* never assigned */
 635                 if (hwc->idx == -1)
 636                         break;
 637
 638                 /* constraint still honored */
 639                 if (!test_bit(hwc->idx, c->idxmsk))
 640                         break;
 641
 642                 /* not already used */
 643                 if (test_bit(hwc->idx, used_mask))
 644                         break;
 645
 646                 set_bit(hwc->idx, used_mask);
 647                 if (assign)
 648                         assign[i] = hwc->idx;
 649         }
 650         if (i == n)
 651                 goto done;
 652
 653         /*
 654          * begin slow path
 655          */
 656
 657         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 658
 659         /*
 660          * weight = number of possible counters
 661          *
 662          * 1    = most constrained, only works on one counter
 663          * wmax = least constrained, works on any counter
 664          *
 665          * assign events to counters starting with most
 666          * constrained events.
 667          */
 668         wmax = x86_pmu.num_events;
 669
 670         /*
 671          * when fixed event counters are present,
 672          * wmax is incremented by 1 to account
 673          * for one more choice
 674          */
 675         if (x86_pmu.num_events_fixed)
 676                 wmax++;
 677
 678         for (w = 1, num = n; num && w <= wmax; w++) {
 679                 /* for each event */
 680                 for (i = 0; num && i < n; i++) {
 681                         c = constraints[i];
 682                         hwc = &cpuc->event_list[i]->hw;
 683
 684                         if (c->weight != w)
 685                                 continue;
 686
 687                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 688                                 if (!test_bit(j, used_mask))
 689                                         break;
 690                         }
 691
 692                         if (j == X86_PMC_IDX_MAX)
 693                                 break;
 694
 695                         set_bit(j, used_mask);
 696
 697                         if (assign)
 698                                 assign[i] = j;
 699                         num--;
 700                 }
 701         }
 702 done:
 703         /*
 704          * scheduling failed or is just a simulation,
 705          * free resources if necessary
 706          */
 707         if (!assign || num) {
 708                 for (i = 0; i < n; i++) {
 709                         if (x86_pmu.put_event_constraints)
 710                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 711                 }
 712         }
 713         return num ? -ENOSPC : 0;
 714 }
 715
 716 /*
 717  * dogrp: true if must collect siblings events (group)
 718  * returns total number of events and error code
 719  */
 720 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 721 {
 722         struct perf_event *event;
 723         int n, max_count;
 724
 725         max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
 726
 727         /* current number of events already accepted */
 728         n = cpuc->n_events;
 729
 730         if (is_x86_event(leader)) {
 731                 if (n >= max_count)
 732                         return -ENOSPC;
 733                 cpuc->event_list[n] = leader;
 734                 n++;
 735         }
 736         if (!dogrp)
 737                 return n;
 738
 739         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 740                 if (!is_x86_event(event) ||
 741                     event->state <= PERF_EVENT_STATE_OFF)
 742                         continue;
 743
 744                 if (n >= max_count)
 745                         return -ENOSPC;
 746
 747                 cpuc->event_list[n] = event;
 748                 n++;
 749         }
 750         return n;
 751 }
 752
 753 static inline void x86_assign_hw_event(struct perf_event *event,
 754                                 struct cpu_hw_events *cpuc, int i)
 755 {
 756         struct hw_perf_event *hwc = &event->hw;
 757
 758         hwc->idx = cpuc->assign[i];
 759         hwc->last_cpu = smp_processor_id();
 760         hwc->last_tag = ++cpuc->tags[i];
 761
 762         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 763                 hwc->config_base = 0;
 764                 hwc->event_base = 0;
 765         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 766                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 767                 /*
 768                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 769                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 770                  */
 771                 hwc->event_base =
 772                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 773         } else {
 774                 hwc->config_base = x86_pmu.eventsel;
 775                 hwc->event_base  = x86_pmu.perfctr;
 776         }
 777 }
 778
 779 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 780                                         struct cpu_hw_events *cpuc,
 781                                         int i)
 782 {
 783         return hwc->idx == cpuc->assign[i] &&
 784                 hwc->last_cpu == smp_processor_id() &&
 785                 hwc->last_tag == cpuc->tags[i];
 786 }
 787
 788 static void x86_pmu_stop(struct perf_event *event);
 789
 790 void hw_perf_enable(void)
 791 {
 792         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 793         struct perf_event *event;
 794         struct hw_perf_event *hwc;
 795         int i;
 796
 797         if (!x86_pmu_initialized())
 798                 return;
 799
 800         if (cpuc->enabled)
 801                 return;
 802
 803         if (cpuc->n_added) {
 804                 /*
 805                  * apply assignment obtained either from
 806                  * hw_perf_group_sched_in() or x86_pmu_enable()
 807                  *
 808                  * step1: save events moving to new counters
 809                  * step2: reprogram moved events into new counters
 810                  */
 811                 for (i = 0; i < cpuc->n_events; i++) {
 812
 813                         event = cpuc->event_list[i];
 814                         hwc = &event->hw;
 815
 816                         /*
 817                          * we can avoid reprogramming counter if:
 818                          * - assigned same counter as last time
 819                          * - running on same CPU as last time
 820                          * - no other event has used the counter since
 821                          */
 822                         if (hwc->idx == -1 ||
 823                             match_prev_assignment(hwc, cpuc, i))
 824                                 continue;
 825
 826                         x86_pmu_stop(event);
 827
 828                         hwc->idx = -1;
 829                 }
 830
 831                 for (i = 0; i < cpuc->n_events; i++) {
 832
 833                         event = cpuc->event_list[i];
 834                         hwc = &event->hw;
 835
 836                         if (hwc->idx == -1) {
 837                                 x86_assign_hw_event(event, cpuc, i);
 838                                 x86_perf_event_set_period(event);
 839                         }
 840                         /*
 841                          * need to mark as active because x86_pmu_disable()
 842                          * clear active_mask and events[] yet it preserves
 843                          * idx
 844                          */
 845                         set_bit(hwc->idx, cpuc->active_mask);
 846                         cpuc->events[hwc->idx] = event;
 847
 848                         x86_pmu.enable(hwc, hwc->idx);
 849                         perf_event_update_userpage(event);
 850                 }
 851                 cpuc->n_added = 0;
 852                 perf_events_lapic_init();
 853         }
 854
 855         cpuc->enabled = 1;
 856         barrier();
 857
 858         x86_pmu.enable_all();
 859 }
 860
 861 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 862 {
 863         (void)checking_wrmsrl(hwc->config_base + idx,
 864                               hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
 865 }
 866
 867 static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
 868 {
 869         (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
 870 }
 871
 872 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 873
 874 /*
 875  * Set the next IRQ period, based on the hwc->period_left value.
 876  * To be called with the event disabled in hw:
 877  */
 878 static int
 879 x86_perf_event_set_period(struct perf_event *event)
 880 {
 881         struct hw_perf_event *hwc = &event->hw;
 882         s64 left = atomic64_read(&hwc->period_left);
 883         s64 period = hwc->sample_period;
 884         int err, ret = 0, idx = hwc->idx;
 885
 886         if (idx == X86_PMC_IDX_FIXED_BTS)
 887                 return 0;
 888
 889         /*
 890          * If we are way outside a reasonable range then just skip forward:
 891          */
 892         if (unlikely(left <= -period)) {
 893                 left = period;
 894                 atomic64_set(&hwc->period_left, left);
 895                 hwc->last_period = period;
 896                 ret = 1;
 897         }
 898
 899         if (unlikely(left <= 0)) {
 900                 left += period;
 901                 atomic64_set(&hwc->period_left, left);
 902                 hwc->last_period = period;
 903                 ret = 1;
 904         }
 905         /*
 906          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 907          */
 908         if (unlikely(left < 2))
 909                 left = 2;
 910
 911         if (left > x86_pmu.max_period)
 912                 left = x86_pmu.max_period;
 913
 914         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 915
 916         /*
 917          * The hw event starts counting from this event offset,
 918          * mark it to be able to extra future deltas:
 919          */
 920         atomic64_set(&hwc->prev_count, (u64)-left);
 921
 922         err = checking_wrmsrl(hwc->event_base + idx,
 923                              (u64)(-left) & x86_pmu.event_mask);
 924
 925         perf_event_update_userpage(event);
 926
 927         return ret;
 928 }
 929
 930 static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 931 {
 932         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 933         if (cpuc->enabled)
 934                 __x86_pmu_enable_event(hwc, idx);
 935 }
 936
 937 /*
 938  * activate a single event
 939  *
 940  * The event is added to the group of enabled events
 941  * but only if it can be scehduled with existing events.
 942  *
 943  * Called with PMU disabled. If successful and return value 1,
 944  * then guaranteed to call perf_enable() and hw_perf_enable()
 945  */
 946 static int x86_pmu_enable(struct perf_event *event)
 947 {
 948         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 949         struct hw_perf_event *hwc;
 950         int assign[X86_PMC_IDX_MAX];
 951         int n, n0, ret;
 952
 953         hwc = &event->hw;
 954
 955         n0 = cpuc->n_events;
 956         n = collect_events(cpuc, event, false);
 957         if (n < 0)
 958                 return n;
 959
 960         ret = x86_schedule_events(cpuc, n, assign);
 961         if (ret)
 962                 return ret;
 963         /*
 964          * copy new assignment, now we know it is possible
 965          * will be used by hw_perf_enable()
 966          */
 967         memcpy(cpuc->assign, assign, n*sizeof(int));
 968
 969         cpuc->n_events = n;
 970         cpuc->n_added  = n - n0;
 971
 972         return 0;
 973 }
 974
 975 static int x86_pmu_start(struct perf_event *event)
 976 {
 977         struct hw_perf_event *hwc = &event->hw;
 978
 979         if (hwc->idx == -1)
 980                 return -EAGAIN;
 981
 982         x86_perf_event_set_period(event);
 983         x86_pmu.enable(hwc, hwc->idx);
 984
 985         return 0;
 986 }
 987
 988 static void x86_pmu_unthrottle(struct perf_event *event)
 989 {
 990         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 991         struct hw_perf_event *hwc = &event->hw;
 992
 993         if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
 994                                 cpuc->events[hwc->idx] != event))
 995                 return;
 996
 997         x86_pmu.enable(hwc, hwc->idx);
 998 }
 999
1000 void perf_event_print_debug(void)
1001 {
1002         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1003         struct cpu_hw_events *cpuc;
1004         unsigned long flags;
1005         int cpu, idx;
1006
1007         if (!x86_pmu.num_events)
1008                 return;
1009
1010         local_irq_save(flags);
1011
1012         cpu = smp_processor_id();
1013         cpuc = &per_cpu(cpu_hw_events, cpu);
1014
1015         if (x86_pmu.version >= 2) {
1016                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1017                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1018                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1019                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1020
1021                 pr_info("\n");
1022                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1023                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1024                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1025                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1026         }
1027         pr_info("CPU#%d: active:       %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1028
1029         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1030                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1031                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1032
1033                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1034
1035                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1036                         cpu, idx, pmc_ctrl);
1037                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1038                         cpu, idx, pmc_count);
1039                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1040                         cpu, idx, prev_left);
1041         }
1042         for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1043                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1044
1045                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1046                         cpu, idx, pmc_count);
1047         }
1048         local_irq_restore(flags);
1049 }
1050
1051 static void x86_pmu_stop(struct perf_event *event)
1052 {
1053         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1054         struct hw_perf_event *hwc = &event->hw;
1055         int idx = hwc->idx;
1056
1057         /*
1058          * Must be done before we disable, otherwise the nmi handler
1059          * could reenable again:
1060          */
1061         clear_bit(idx, cpuc->active_mask);
1062         x86_pmu.disable(hwc, idx);
1063
1064         /*
1065          * Drain the remaining delta count out of a event
1066          * that we are disabling:
1067          */
1068         x86_perf_event_update(event);
1069
1070         cpuc->events[idx] = NULL;
1071 }
1072
1073 static void x86_pmu_disable(struct perf_event *event)
1074 {
1075         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1076         int i;
1077
1078         x86_pmu_stop(event);
1079
1080         for (i = 0; i < cpuc->n_events; i++) {
1081                 if (event == cpuc->event_list[i]) {
1082
1083                         if (x86_pmu.put_event_constraints)
1084                                 x86_pmu.put_event_constraints(cpuc, event);
1085
1086                         while (++i < cpuc->n_events)
1087                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1088
1089                         --cpuc->n_events;
1090                         break;
1091                 }
1092         }
1093         perf_event_update_userpage(event);
1094 }
1095
1096 static int x86_pmu_handle_irq(struct pt_regs *regs)
1097 {
1098         struct perf_sample_data data;
1099         struct cpu_hw_events *cpuc;
1100         struct perf_event *event;
1101         struct hw_perf_event *hwc;
1102         int idx, handled = 0;
1103         u64 val;
1104
1105         perf_sample_data_init(&data, 0);
1106
1107         cpuc = &__get_cpu_var(cpu_hw_events);
1108
1109         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1110                 if (!test_bit(idx, cpuc->active_mask))
1111                         continue;
1112
1113                 event = cpuc->events[idx];
1114                 hwc = &event->hw;
1115
1116                 val = x86_perf_event_update(event);
1117                 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1118                         continue;
1119
1120                 /*
1121                  * event overflow
1122                  */
1123                 handled         = 1;
1124                 data.period     = event->hw.last_period;
1125
1126                 if (!x86_perf_event_set_period(event))
1127                         continue;
1128
1129                 if (perf_event_overflow(event, 1, &data, regs))
1130                         x86_pmu.disable(hwc, idx);
1131         }
1132
1133         if (handled)
1134                 inc_irq_stat(apic_perf_irqs);
1135
1136         return handled;
1137 }
1138
1139 void smp_perf_pending_interrupt(struct pt_regs *regs)
1140 {
1141         irq_enter();
1142         ack_APIC_irq();
1143         inc_irq_stat(apic_pending_irqs);
1144         perf_event_do_pending();
1145         irq_exit();
1146 }
1147
1148 void set_perf_event_pending(void)
1149 {
1150 #ifdef CONFIG_X86_LOCAL_APIC
1151         if (!x86_pmu.apic || !x86_pmu_initialized())
1152                 return;
1153
1154         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1155 #endif
1156 }
1157
1158 void perf_events_lapic_init(void)
1159 {
1160 #ifdef CONFIG_X86_LOCAL_APIC
1161         if (!x86_pmu.apic || !x86_pmu_initialized())
1162                 return;
1163
1164         /*
1165          * Always use NMI for PMU
1166          */
1167         apic_write(APIC_LVTPC, APIC_DM_NMI);
1168 #endif
1169 }
1170
1171 static int __kprobes
1172 perf_event_nmi_handler(struct notifier_block *self,
1173                          unsigned long cmd, void *__args)
1174 {
1175         struct die_args *args = __args;
1176         struct pt_regs *regs;
1177
1178         if (!atomic_read(&active_events))
1179                 return NOTIFY_DONE;
1180
1181         switch (cmd) {
1182         case DIE_NMI:
1183         case DIE_NMI_IPI:
1184                 break;
1185
1186         default:
1187                 return NOTIFY_DONE;
1188         }
1189
1190         regs = args->regs;
1191
1192 #ifdef CONFIG_X86_LOCAL_APIC
1193         apic_write(APIC_LVTPC, APIC_DM_NMI);
1194 #endif
1195         /*
1196          * Can't rely on the handled return value to say it was our NMI, two
1197          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1198          *
1199          * If the first NMI handles both, the latter will be empty and daze
1200          * the CPU.
1201          */
1202         x86_pmu.handle_irq(regs);
1203
1204         return NOTIFY_STOP;
1205 }
1206
1207 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1208         .notifier_call          = perf_event_nmi_handler,
1209         .next                   = NULL,
1210         .priority               = 1
1211 };
1212
1213 static struct event_constraint unconstrained;
1214 static struct event_constraint emptyconstraint;
1215
1216 static struct event_constraint *
1217 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1218 {
1219         struct event_constraint *c;
1220
1221         if (x86_pmu.event_constraints) {
1222                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1223                         if ((event->hw.config & c->cmask) == c->code)
1224                                 return c;
1225                 }
1226         }
1227
1228         return &unconstrained;
1229 }
1230
1231 static int x86_event_sched_in(struct perf_event *event,
1232                           struct perf_cpu_context *cpuctx)
1233 {
1234         int ret = 0;
1235
1236         event->state = PERF_EVENT_STATE_ACTIVE;
1237         event->oncpu = smp_processor_id();
1238         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1239
1240         if (!is_x86_event(event))
1241                 ret = event->pmu->enable(event);
1242
1243         if (!ret && !is_software_event(event))
1244                 cpuctx->active_oncpu++;
1245
1246         if (!ret && event->attr.exclusive)
1247                 cpuctx->exclusive = 1;
1248
1249         return ret;
1250 }
1251
1252 static void x86_event_sched_out(struct perf_event *event,
1253                             struct perf_cpu_context *cpuctx)
1254 {
1255         event->state = PERF_EVENT_STATE_INACTIVE;
1256         event->oncpu = -1;
1257
1258         if (!is_x86_event(event))
1259                 event->pmu->disable(event);
1260
1261         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1262
1263         if (!is_software_event(event))
1264                 cpuctx->active_oncpu--;
1265
1266         if (event->attr.exclusive || !cpuctx->active_oncpu)
1267                 cpuctx->exclusive = 0;
1268 }
1269
1270 /*
1271  * Called to enable a whole group of events.
1272  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1273  * Assumes the caller has disabled interrupts and has
1274  * frozen the PMU with hw_perf_save_disable.
1275  *
1276  * called with PMU disabled. If successful and return value 1,
1277  * then guaranteed to call perf_enable() and hw_perf_enable()
1278  */
1279 int hw_perf_group_sched_in(struct perf_event *leader,
1280                struct perf_cpu_context *cpuctx,
1281                struct perf_event_context *ctx)
1282 {
1283         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1284         struct perf_event *sub;
1285         int assign[X86_PMC_IDX_MAX];
1286         int n0, n1, ret;
1287
1288         /* n0 = total number of events */
1289         n0 = collect_events(cpuc, leader, true);
1290         if (n0 < 0)
1291                 return n0;
1292
1293         ret = x86_schedule_events(cpuc, n0, assign);
1294         if (ret)
1295                 return ret;
1296
1297         ret = x86_event_sched_in(leader, cpuctx);
1298         if (ret)
1299                 return ret;
1300
1301         n1 = 1;
1302         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1303                 if (sub->state > PERF_EVENT_STATE_OFF) {
1304                         ret = x86_event_sched_in(sub, cpuctx);
1305                         if (ret)
1306                                 goto undo;
1307                         ++n1;
1308                 }
1309         }
1310         /*
1311          * copy new assignment, now we know it is possible
1312          * will be used by hw_perf_enable()
1313          */
1314         memcpy(cpuc->assign, assign, n0*sizeof(int));
1315
1316         cpuc->n_events  = n0;
1317         cpuc->n_added   = n1;
1318         ctx->nr_active += n1;
1319
1320         /*
1321          * 1 means successful and events are active
1322          * This is not quite true because we defer
1323          * actual activation until hw_perf_enable() but
1324          * this way we* ensure caller won't try to enable
1325          * individual events
1326          */
1327         return 1;
1328 undo:
1329         x86_event_sched_out(leader, cpuctx);
1330         n0  = 1;
1331         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1332                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1333                         x86_event_sched_out(sub, cpuctx);
1334                         if (++n0 == n1)
1335                                 break;
1336                 }
1337         }
1338         return ret;
1339 }
1340
1341 #include "perf_event_amd.c"
1342 #include "perf_event_p6.c"
1343 #include "perf_event_intel.c"
1344
1345 static int __cpuinit
1346 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1347 {
1348         unsigned int cpu = (long)hcpu;
1349
1350         switch (action & ~CPU_TASKS_FROZEN) {
1351         case CPU_UP_PREPARE:
1352                 if (x86_pmu.cpu_prepare)
1353                         x86_pmu.cpu_prepare(cpu);
1354                 break;
1355
1356         case CPU_STARTING:
1357                 if (x86_pmu.cpu_starting)
1358                         x86_pmu.cpu_starting(cpu);
1359                 break;
1360
1361         case CPU_DYING:
1362                 if (x86_pmu.cpu_dying)
1363                         x86_pmu.cpu_dying(cpu);
1364                 break;
1365
1366         case CPU_DEAD:
1367                 if (x86_pmu.cpu_dead)
1368                         x86_pmu.cpu_dead(cpu);
1369                 break;
1370
1371         default:
1372                 break;
1373         }
1374
1375         return NOTIFY_OK;
1376 }
1377
1378 static void __init pmu_check_apic(void)
1379 {
1380         if (cpu_has_apic)
1381                 return;
1382
1383         x86_pmu.apic = 0;
1384         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1385         pr_info("no hardware sampling interrupt available.\n");
1386 }
1387
1388 void __init init_hw_perf_events(void)
1389 {
1390         struct event_constraint *c;
1391         int err;
1392
1393         pr_info("Performance Events: ");
1394
1395         switch (boot_cpu_data.x86_vendor) {
1396         case X86_VENDOR_INTEL:
1397                 err = intel_pmu_init();
1398                 break;
1399         case X86_VENDOR_AMD:
1400                 err = amd_pmu_init();
1401                 break;
1402         default:
1403                 return;
1404         }
1405         if (err != 0) {
1406                 pr_cont("no PMU driver, software events only.\n");
1407                 return;
1408         }
1409
1410         pmu_check_apic();
1411
1412         pr_cont("%s PMU driver.\n", x86_pmu.name);
1413
1414         if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
1415                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1416                      x86_pmu.num_events, X86_PMC_MAX_GENERIC);
1417                 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
1418         }
1419         perf_event_mask = (1 << x86_pmu.num_events) - 1;
1420         perf_max_events = x86_pmu.num_events;
1421
1422         if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
1423                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1424                      x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
1425                 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
1426         }
1427
1428         perf_event_mask |=
1429                 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
1430         x86_pmu.intel_ctrl = perf_event_mask;
1431
1432         perf_events_lapic_init();
1433         register_die_notifier(&perf_event_nmi_notifier);
1434
1435         unconstrained = (struct event_constraint)
1436                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1437                                    0, x86_pmu.num_events);
1438
1439         if (x86_pmu.event_constraints) {
1440                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1441                         if (c->cmask != INTEL_ARCH_FIXED_MASK)
1442                                 continue;
1443
1444                         c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
1445                         c->weight += x86_pmu.num_events;
1446                 }
1447         }
1448
1449         pr_info("... version:                %d\n",     x86_pmu.version);
1450         pr_info("... bit width:              %d\n",     x86_pmu.event_bits);
1451         pr_info("... generic registers:      %d\n",     x86_pmu.num_events);
1452         pr_info("... value mask:             %016Lx\n", x86_pmu.event_mask);
1453         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1454         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_events_fixed);
1455         pr_info("... event mask:             %016Lx\n", perf_event_mask);
1456
1457         perf_cpu_notifier(x86_pmu_notifier);
1458 }
1459
1460 static inline void x86_pmu_read(struct perf_event *event)
1461 {
1462         x86_perf_event_update(event);
1463 }
1464
1465 static const struct pmu pmu = {
1466         .enable         = x86_pmu_enable,
1467         .disable        = x86_pmu_disable,
1468         .start          = x86_pmu_start,
1469         .stop           = x86_pmu_stop,
1470         .read           = x86_pmu_read,
1471         .unthrottle     = x86_pmu_unthrottle,
1472 };
1473
1474 /*
1475  * validate a single event group
1476  *
1477  * validation include:
1478  *      - check events are compatible which each other
1479  *      - events do not compete for the same counter
1480  *      - number of events <= number of counters
1481  *
1482  * validation ensures the group can be loaded onto the
1483  * PMU if it was the only group available.
1484  */
1485 static int validate_group(struct perf_event *event)
1486 {
1487         struct perf_event *leader = event->group_leader;
1488         struct cpu_hw_events *fake_cpuc;
1489         int ret, n;
1490
1491         ret = -ENOMEM;
1492         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1493         if (!fake_cpuc)
1494                 goto out;
1495
1496         /*
1497          * the event is not yet connected with its
1498          * siblings therefore we must first collect
1499          * existing siblings, then add the new event
1500          * before we can simulate the scheduling
1501          */
1502         ret = -ENOSPC;
1503         n = collect_events(fake_cpuc, leader, true);
1504         if (n < 0)
1505                 goto out_free;
1506
1507         fake_cpuc->n_events = n;
1508         n = collect_events(fake_cpuc, event, false);
1509         if (n < 0)
1510                 goto out_free;
1511
1512         fake_cpuc->n_events = n;
1513
1514         ret = x86_schedule_events(fake_cpuc, n, NULL);
1515
1516 out_free:
1517         kfree(fake_cpuc);
1518 out:
1519         return ret;
1520 }
1521
1522 const struct pmu *hw_perf_event_init(struct perf_event *event)
1523 {
1524         const struct pmu *tmp;
1525         int err;
1526
1527         err = __hw_perf_event_init(event);
1528         if (!err) {
1529                 /*
1530                  * we temporarily connect event to its pmu
1531                  * such that validate_group() can classify
1532                  * it as an x86 event using is_x86_event()
1533                  */
1534                 tmp = event->pmu;
1535                 event->pmu = &pmu;
1536
1537                 if (event->group_leader != event)
1538                         err = validate_group(event);
1539
1540                 event->pmu = tmp;
1541         }
1542         if (err) {
1543                 if (event->destroy)
1544                         event->destroy(event);
1545                 return ERR_PTR(err);
1546         }
1547
1548         return &pmu;
1549 }
1550
1551 /*
1552  * callchain support
1553  */
1554
1555 static inline
1556 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1557 {
1558         if (entry->nr < PERF_MAX_STACK_DEPTH)
1559                 entry->ip[entry->nr++] = ip;
1560 }
1561
1562 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1563 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1564
1565
1566 static void
1567 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1568 {
1569         /* Ignore warnings */
1570 }
1571
1572 static void backtrace_warning(void *data, char *msg)
1573 {
1574         /* Ignore warnings */
1575 }
1576
1577 static int backtrace_stack(void *data, char *name)
1578 {
1579         return 0;
1580 }
1581
1582 static void backtrace_address(void *data, unsigned long addr, int reliable)
1583 {
1584         struct perf_callchain_entry *entry = data;
1585
1586         if (reliable)
1587                 callchain_store(entry, addr);
1588 }
1589
1590 static const struct stacktrace_ops backtrace_ops = {
1591         .warning                = backtrace_warning,
1592         .warning_symbol         = backtrace_warning_symbol,
1593         .stack                  = backtrace_stack,
1594         .address                = backtrace_address,
1595         .walk_stack             = print_context_stack_bp,
1596 };
1597
1598 #include "../dumpstack.h"
1599
1600 static void
1601 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1602 {
1603         callchain_store(entry, PERF_CONTEXT_KERNEL);
1604         callchain_store(entry, regs->ip);
1605
1606         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1607 }
1608
1609 /*
1610  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1611  */
1612 static unsigned long
1613 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
1614 {
1615         unsigned long offset, addr = (unsigned long)from;
1616         int type = in_nmi() ? KM_NMI : KM_IRQ0;
1617         unsigned long size, len = 0;
1618         struct page *page;
1619         void *map;
1620         int ret;
1621
1622         do {
1623                 ret = __get_user_pages_fast(addr, 1, 0, &page);
1624                 if (!ret)
1625                         break;
1626
1627                 offset = addr & (PAGE_SIZE - 1);
1628                 size = min(PAGE_SIZE - offset, n - len);
1629
1630                 map = kmap_atomic(page, type);
1631                 memcpy(to, map+offset, size);
1632                 kunmap_atomic(map, type);
1633                 put_page(page);
1634
1635                 len  += size;
1636                 to   += size;
1637                 addr += size;
1638
1639         } while (len < n);
1640
1641         return len;
1642 }
1643
1644 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1645 {
1646         unsigned long bytes;
1647
1648         bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
1649
1650         return bytes == sizeof(*frame);
1651 }
1652
1653 static void
1654 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1655 {
1656         struct stack_frame frame;
1657         const void __user *fp;
1658
1659         if (!user_mode(regs))
1660                 regs = task_pt_regs(current);
1661
1662         fp = (void __user *)regs->bp;
1663
1664         callchain_store(entry, PERF_CONTEXT_USER);
1665         callchain_store(entry, regs->ip);
1666
1667         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1668                 frame.next_frame             = NULL;
1669                 frame.return_address = 0;
1670
1671                 if (!copy_stack_frame(fp, &frame))
1672                         break;
1673
1674                 if ((unsigned long)fp < regs->sp)
1675                         break;
1676
1677                 callchain_store(entry, frame.return_address);
1678                 fp = frame.next_frame;
1679         }
1680 }
1681
1682 static void
1683 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1684 {
1685         int is_user;
1686
1687         if (!regs)
1688                 return;
1689
1690         is_user = user_mode(regs);
1691
1692         if (is_user && current->state != TASK_RUNNING)
1693                 return;
1694
1695         if (!is_user)
1696                 perf_callchain_kernel(regs, entry);
1697
1698         if (current->mm)
1699                 perf_callchain_user(regs, entry);
1700 }
1701
1702 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1703 {
1704         struct perf_callchain_entry *entry;
1705
1706         if (in_nmi())
1707                 entry = &__get_cpu_var(pmc_nmi_entry);
1708         else
1709                 entry = &__get_cpu_var(pmc_irq_entry);
1710
1711         entry->nr = 0;
1712
1713         perf_do_callchain(regs, entry);
1714
1715         return entry;
1716 }