1 #include <linux/init.h>
5 #include <asm/processor-cyrix.h>
6 #include <asm/processor-flags.h>
12 /* Put the processor into a state where MTRRs can be safely set */
13 void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
17 /* Disable interrupts locally */
18 local_irq_save(ctxt->flags);
20 if (use_intel() || is_cpu(CYRIX)) {
22 /* Save value of CR4 and clear Page Global Enable (bit 7) */
24 ctxt->cr4val = read_cr4();
25 write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
29 * Disable and flush caches. Note that wbinvd flushes the TLBs
32 cr0 = read_cr0() | X86_CR0_CD;
39 rdmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);
43 * everything else were excluded at the top
45 ctxt->ccr3 = getCx86(CX86_CCR3);
50 void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
53 /* Disable MTRRs, and set the default type to uncached */
54 mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo & 0xf300UL,
58 /* Cyrix ARRs - everything else were excluded at the top */
59 setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
64 /* Restore the processor after a set_mtrr_prepare */
65 void set_mtrr_done(struct set_mtrr_context *ctxt)
67 if (use_intel() || is_cpu(CYRIX)) {
69 /* Flush caches and TLBs */
72 /* Restore MTRRdefType */
74 /* Intel (P6) standard MTRRs */
75 mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo,
80 * everything else was excluded at the top
82 setCx86(CX86_CCR3, ctxt->ccr3);
86 write_cr0(read_cr0() & 0xbfffffff);
88 /* Restore value of CR4 */
90 write_cr4(ctxt->cr4val);
92 /* Re-enable interrupts locally (if enabled previously) */
93 local_irq_restore(ctxt->flags);