2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <linux/debugfs.h>
39 #include <asm/processor.h>
40 #include <asm/hw_irq.h>
47 #include "mce-internal.h"
49 int mce_disabled __read_mostly;
51 #define MISC_MCELOG_MINOR 227
53 #define SPINUNIT 100 /* 100ns */
57 DEFINE_PER_CPU(unsigned, mce_exception_count);
61 * 0: always panic on uncorrected errors, log corrected errors
62 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
63 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
64 * 3: never panic or SIGBUS, log all errors (for testing only)
66 static int tolerant __read_mostly = 1;
67 static int banks __read_mostly;
68 static int rip_msr __read_mostly;
69 static int mce_bootlog __read_mostly = -1;
70 static int monarch_timeout __read_mostly = -1;
71 static int mce_panic_timeout __read_mostly;
72 static int mce_dont_log_ce __read_mostly;
73 int mce_cmci_disabled __read_mostly;
74 int mce_ignore_ce __read_mostly;
75 int mce_ser __read_mostly;
77 struct mce_bank *mce_banks __read_mostly;
79 /* User mode helper program triggered by machine check event */
80 static unsigned long mce_need_notify;
81 static char mce_helper[128];
82 static char *mce_helper_argv[2] = { mce_helper, NULL };
84 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
85 static DEFINE_PER_CPU(struct mce, mces_seen);
86 static int cpu_missing;
89 /* MCA banks polled by the period polling timer for corrected events */
90 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
91 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
94 static DEFINE_PER_CPU(struct work_struct, mce_work);
96 /* Do initial initialization of a struct mce */
97 void mce_setup(struct mce *m)
99 memset(m, 0, sizeof(struct mce));
100 m->cpu = m->extcpu = smp_processor_id();
102 /* We hope get_seconds stays lockless */
103 m->time = get_seconds();
104 m->cpuvendor = boot_cpu_data.x86_vendor;
105 m->cpuid = cpuid_eax(1);
107 m->socketid = cpu_data(m->extcpu).phys_proc_id;
109 m->apicid = cpu_data(m->extcpu).initial_apicid;
110 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
113 DEFINE_PER_CPU(struct mce, injectm);
114 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
117 * Lockless MCE logging infrastructure.
118 * This avoids deadlocks on printk locks without having to break locks. Also
119 * separate MCEs from kernel messages to avoid bogus bug reports.
122 static struct mce_log mcelog = {
123 .signature = MCE_LOG_SIGNATURE,
125 .recordlen = sizeof(struct mce),
128 void mce_log(struct mce *mce)
130 unsigned next, entry;
135 entry = rcu_dereference(mcelog.next);
138 * When the buffer fills up discard new entries.
139 * Assume that the earlier errors are the more
142 if (entry >= MCE_LOG_LEN) {
143 set_bit(MCE_OVERFLOW,
144 (unsigned long *)&mcelog.flags);
147 /* Old left over entry. Skip: */
148 if (mcelog.entry[entry].finished) {
156 if (cmpxchg(&mcelog.next, entry, next) == entry)
159 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
161 mcelog.entry[entry].finished = 1;
165 set_bit(0, &mce_need_notify);
168 void __weak decode_mce(struct mce *m)
173 static void print_mce(struct mce *m)
176 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
177 m->extcpu, m->mcgstatus, m->bank, m->status);
179 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
180 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
182 if (m->cs == __KERNEL_CS)
183 print_symbol("{%s}", m->ip);
184 printk(KERN_CONT "\n");
186 printk(KERN_EMERG "TSC %llx ", m->tsc);
188 printk(KERN_CONT "ADDR %llx ", m->addr);
190 printk(KERN_CONT "MISC %llx ", m->misc);
191 printk(KERN_CONT "\n");
192 printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
193 m->cpuvendor, m->cpuid, m->time, m->socketid,
199 static void print_mce_head(void)
201 printk(KERN_EMERG "\nHARDWARE ERROR\n");
204 static void print_mce_tail(void)
206 printk(KERN_EMERG "This is not a software problem!\n"
207 #if (!defined(CONFIG_EDAC) || !defined(CONFIG_CPU_SUP_AMD))
208 "Run through mcelog --ascii to decode and contact your hardware vendor\n"
213 #define PANIC_TIMEOUT 5 /* 5 seconds */
215 static atomic_t mce_paniced;
217 static int fake_panic;
218 static atomic_t mce_fake_paniced;
220 /* Panic in progress. Enable interrupts and wait for final IPI */
221 static void wait_for_panic(void)
223 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
226 while (timeout-- > 0)
228 if (panic_timeout == 0)
229 panic_timeout = mce_panic_timeout;
230 panic("Panicing machine check CPU died");
233 static void mce_panic(char *msg, struct mce *final, char *exp)
239 * Make sure only one CPU runs in machine check panic
241 if (atomic_inc_return(&mce_paniced) > 1)
248 /* Don't log too much for fake panic */
249 if (atomic_inc_return(&mce_fake_paniced) > 1)
253 /* First print corrected ones that are still unlogged */
254 for (i = 0; i < MCE_LOG_LEN; i++) {
255 struct mce *m = &mcelog.entry[i];
256 if (!(m->status & MCI_STATUS_VAL))
258 if (!(m->status & MCI_STATUS_UC))
261 /* Now print uncorrected but with the final one last */
262 for (i = 0; i < MCE_LOG_LEN; i++) {
263 struct mce *m = &mcelog.entry[i];
264 if (!(m->status & MCI_STATUS_VAL))
266 if (!(m->status & MCI_STATUS_UC))
268 if (!final || memcmp(m, final, sizeof(struct mce)))
274 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
277 printk(KERN_EMERG "Machine check: %s\n", exp);
279 if (panic_timeout == 0)
280 panic_timeout = mce_panic_timeout;
283 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
286 /* Support code for software error injection */
288 static int msr_to_offset(u32 msr)
290 unsigned bank = __get_cpu_var(injectm.bank);
292 return offsetof(struct mce, ip);
293 if (msr == MSR_IA32_MCx_STATUS(bank))
294 return offsetof(struct mce, status);
295 if (msr == MSR_IA32_MCx_ADDR(bank))
296 return offsetof(struct mce, addr);
297 if (msr == MSR_IA32_MCx_MISC(bank))
298 return offsetof(struct mce, misc);
299 if (msr == MSR_IA32_MCG_STATUS)
300 return offsetof(struct mce, mcgstatus);
304 /* MSR access wrappers used for error injection */
305 static u64 mce_rdmsrl(u32 msr)
309 if (__get_cpu_var(injectm).finished) {
310 int offset = msr_to_offset(msr);
314 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
317 if (rdmsrl_safe(msr, &v)) {
318 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
320 * Return zero in case the access faulted. This should
321 * not happen normally but can happen if the CPU does
322 * something weird, or if the code is buggy.
330 static void mce_wrmsrl(u32 msr, u64 v)
332 if (__get_cpu_var(injectm).finished) {
333 int offset = msr_to_offset(msr);
336 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
343 * Simple lockless ring to communicate PFNs from the exception handler with the
344 * process context work function. This is vastly simplified because there's
345 * only a single reader and a single writer.
347 #define MCE_RING_SIZE 16 /* we use one entry less */
350 unsigned short start;
352 unsigned long ring[MCE_RING_SIZE];
354 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
356 /* Runs with CPU affinity in workqueue */
357 static int mce_ring_empty(void)
359 struct mce_ring *r = &__get_cpu_var(mce_ring);
361 return r->start == r->end;
364 static int mce_ring_get(unsigned long *pfn)
371 r = &__get_cpu_var(mce_ring);
372 if (r->start == r->end)
374 *pfn = r->ring[r->start];
375 r->start = (r->start + 1) % MCE_RING_SIZE;
382 /* Always runs in MCE context with preempt off */
383 static int mce_ring_add(unsigned long pfn)
385 struct mce_ring *r = &__get_cpu_var(mce_ring);
388 next = (r->end + 1) % MCE_RING_SIZE;
389 if (next == r->start)
391 r->ring[r->end] = pfn;
397 int mce_available(struct cpuinfo_x86 *c)
401 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
404 static void mce_schedule_work(void)
406 if (!mce_ring_empty()) {
407 struct work_struct *work = &__get_cpu_var(mce_work);
408 if (!work_pending(work))
414 * Get the address of the instruction at the time of the machine check
417 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
420 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
428 m->ip = mce_rdmsrl(rip_msr);
431 #ifdef CONFIG_X86_LOCAL_APIC
433 * Called after interrupts have been reenabled again
434 * when a MCE happened during an interrupts off region
437 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
448 static void mce_report_event(struct pt_regs *regs)
450 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
453 * Triggering the work queue here is just an insurance
454 * policy in case the syscall exit notify handler
455 * doesn't run soon enough or ends up running on the
456 * wrong CPU (can happen when audit sleeps)
462 #ifdef CONFIG_X86_LOCAL_APIC
464 * Without APIC do not notify. The event will be picked
471 * When interrupts are disabled we cannot use
472 * kernel services safely. Trigger an self interrupt
473 * through the APIC to instead do the notification
474 * after interrupts are reenabled again.
476 apic->send_IPI_self(MCE_SELF_VECTOR);
479 * Wait for idle afterwards again so that we don't leave the
480 * APIC in a non idle state because the normal APIC writes
483 apic_wait_icr_idle();
487 DEFINE_PER_CPU(unsigned, mce_poll_count);
490 * Poll for corrected events or events that happened before reset.
491 * Those are just logged through /dev/mcelog.
493 * This is executed in standard interrupt context.
495 * Note: spec recommends to panic for fatal unsignalled
496 * errors here. However this would be quite problematic --
497 * we would need to reimplement the Monarch handling and
498 * it would mess up the exclusion between exception handler
499 * and poll hander -- * so we skip this for now.
500 * These cases should not happen anyways, or only when the CPU
501 * is already totally * confused. In this case it's likely it will
502 * not fully execute the machine check handler either.
504 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
509 __get_cpu_var(mce_poll_count)++;
513 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
514 for (i = 0; i < banks; i++) {
515 if (!mce_banks[i].ctl || !test_bit(i, *b))
524 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
525 if (!(m.status & MCI_STATUS_VAL))
529 * Uncorrected or signalled events are handled by the exception
530 * handler when it is enabled, so don't process those here.
532 * TBD do the same check for MCI_STATUS_EN here?
534 if (!(flags & MCP_UC) &&
535 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
538 if (m.status & MCI_STATUS_MISCV)
539 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
540 if (m.status & MCI_STATUS_ADDRV)
541 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
543 if (!(flags & MCP_TIMESTAMP))
546 * Don't get the IP here because it's unlikely to
547 * have anything to do with the actual error location.
549 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
551 add_taint(TAINT_MACHINE_CHECK);
555 * Clear state for this bank.
557 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
561 * Don't clear MCG_STATUS here because it's only defined for
567 EXPORT_SYMBOL_GPL(machine_check_poll);
570 * Do a quick check if any of the events requires a panic.
571 * This decides if we keep the events around or clear them.
573 static int mce_no_way_out(struct mce *m, char **msg)
577 for (i = 0; i < banks; i++) {
578 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
579 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
586 * Variable to establish order between CPUs while scanning.
587 * Each CPU spins initially until executing is equal its number.
589 static atomic_t mce_executing;
592 * Defines order of CPUs on entry. First CPU becomes Monarch.
594 static atomic_t mce_callin;
597 * Check if a timeout waiting for other CPUs happened.
599 static int mce_timed_out(u64 *t)
602 * The others already did panic for some reason.
603 * Bail out like in a timeout.
604 * rmb() to tell the compiler that system_state
605 * might have been modified by someone else.
608 if (atomic_read(&mce_paniced))
610 if (!monarch_timeout)
612 if ((s64)*t < SPINUNIT) {
613 /* CHECKME: Make panic default for 1 too? */
615 mce_panic("Timeout synchronizing machine check over CPUs",
622 touch_nmi_watchdog();
627 * The Monarch's reign. The Monarch is the CPU who entered
628 * the machine check handler first. It waits for the others to
629 * raise the exception too and then grades them. When any
630 * error is fatal panic. Only then let the others continue.
632 * The other CPUs entering the MCE handler will be controlled by the
633 * Monarch. They are called Subjects.
635 * This way we prevent any potential data corruption in a unrecoverable case
636 * and also makes sure always all CPU's errors are examined.
638 * Also this detects the case of a machine check event coming from outer
639 * space (not detected by any CPUs) In this case some external agent wants
640 * us to shut down, so panic too.
642 * The other CPUs might still decide to panic if the handler happens
643 * in a unrecoverable place, but in this case the system is in a semi-stable
644 * state and won't corrupt anything by itself. It's ok to let the others
645 * continue for a bit first.
647 * All the spin loops have timeouts; when a timeout happens a CPU
648 * typically elects itself to be Monarch.
650 static void mce_reign(void)
653 struct mce *m = NULL;
654 int global_worst = 0;
659 * This CPU is the Monarch and the other CPUs have run
660 * through their handlers.
661 * Grade the severity of the errors of all the CPUs.
663 for_each_possible_cpu(cpu) {
664 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
666 if (severity > global_worst) {
668 global_worst = severity;
669 m = &per_cpu(mces_seen, cpu);
674 * Cannot recover? Panic here then.
675 * This dumps all the mces in the log buffer and stops the
678 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
679 mce_panic("Fatal Machine check", m, msg);
682 * For UC somewhere we let the CPU who detects it handle it.
683 * Also must let continue the others, otherwise the handling
684 * CPU could deadlock on a lock.
688 * No machine check event found. Must be some external
689 * source or one CPU is hung. Panic.
691 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
692 mce_panic("Machine check from unknown source", NULL, NULL);
695 * Now clear all the mces_seen so that they don't reappear on
698 for_each_possible_cpu(cpu)
699 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
702 static atomic_t global_nwo;
705 * Start of Monarch synchronization. This waits until all CPUs have
706 * entered the exception handler and then determines if any of them
707 * saw a fatal event that requires panic. Then it executes them
708 * in the entry order.
709 * TBD double check parallel CPU hotunplug
711 static int mce_start(int *no_way_out)
714 int cpus = num_online_cpus();
715 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
720 atomic_add(*no_way_out, &global_nwo);
722 * global_nwo should be updated before mce_callin
725 order = atomic_inc_return(&mce_callin);
730 while (atomic_read(&mce_callin) != cpus) {
731 if (mce_timed_out(&timeout)) {
732 atomic_set(&global_nwo, 0);
739 * mce_callin should be read before global_nwo
745 * Monarch: Starts executing now, the others wait.
747 atomic_set(&mce_executing, 1);
750 * Subject: Now start the scanning loop one by one in
751 * the original callin order.
752 * This way when there are any shared banks it will be
753 * only seen by one CPU before cleared, avoiding duplicates.
755 while (atomic_read(&mce_executing) < order) {
756 if (mce_timed_out(&timeout)) {
757 atomic_set(&global_nwo, 0);
765 * Cache the global no_way_out state.
767 *no_way_out = atomic_read(&global_nwo);
773 * Synchronize between CPUs after main scanning loop.
774 * This invokes the bulk of the Monarch processing.
776 static int mce_end(int order)
779 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
787 * Allow others to run.
789 atomic_inc(&mce_executing);
792 /* CHECKME: Can this race with a parallel hotplug? */
793 int cpus = num_online_cpus();
796 * Monarch: Wait for everyone to go through their scanning
799 while (atomic_read(&mce_executing) <= cpus) {
800 if (mce_timed_out(&timeout))
810 * Subject: Wait for Monarch to finish.
812 while (atomic_read(&mce_executing) != 0) {
813 if (mce_timed_out(&timeout))
819 * Don't reset anything. That's done by the Monarch.
825 * Reset all global state.
828 atomic_set(&global_nwo, 0);
829 atomic_set(&mce_callin, 0);
833 * Let others run again.
835 atomic_set(&mce_executing, 0);
840 * Check if the address reported by the CPU is in a format we can parse.
841 * It would be possible to add code for most other cases, but all would
842 * be somewhat complicated (e.g. segment offset would require an instruction
843 * parser). So only support physical addresses upto page granuality for now.
845 static int mce_usable_address(struct mce *m)
847 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
849 if ((m->misc & 0x3f) > PAGE_SHIFT)
851 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
856 static void mce_clear_state(unsigned long *toclear)
860 for (i = 0; i < banks; i++) {
861 if (test_bit(i, toclear))
862 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
867 * The actual machine check handler. This only handles real
868 * exceptions when something got corrupted coming in through int 18.
870 * This is executed in NMI context not subject to normal locking rules. This
871 * implies that most kernel services cannot be safely used. Don't even
872 * think about putting a printk in there!
874 * On Intel systems this is entered on all CPUs in parallel through
875 * MCE broadcast. However some CPUs might be broken beyond repair,
876 * so be always careful when synchronizing with others.
878 void do_machine_check(struct pt_regs *regs, long error_code)
880 struct mce m, *final;
885 * Establish sequential order between the CPUs entering the machine
890 * If no_way_out gets set, there is no safe way to recover from this
891 * MCE. If tolerant is cranked up, we'll try anyway.
895 * If kill_it gets set, there might be a way to recover from this
899 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
900 char *msg = "Unknown";
902 atomic_inc(&mce_entry);
904 __get_cpu_var(mce_exception_count)++;
906 if (notify_die(DIE_NMI, "machine check", regs, error_code,
907 18, SIGKILL) == NOTIFY_STOP)
914 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
915 final = &__get_cpu_var(mces_seen);
918 no_way_out = mce_no_way_out(&m, &msg);
923 * When no restart IP must always kill or panic.
925 if (!(m.mcgstatus & MCG_STATUS_RIPV))
929 * Go through all the banks in exclusion of the other CPUs.
930 * This way we don't report duplicated events on shared banks
931 * because the first one to see it will clear it.
933 order = mce_start(&no_way_out);
934 for (i = 0; i < banks; i++) {
935 __clear_bit(i, toclear);
936 if (!mce_banks[i].ctl)
943 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
944 if ((m.status & MCI_STATUS_VAL) == 0)
948 * Non uncorrected or non signaled errors are handled by
949 * machine_check_poll. Leave them alone, unless this panics.
951 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
956 * Set taint even when machine check was not enabled.
958 add_taint(TAINT_MACHINE_CHECK);
960 severity = mce_severity(&m, tolerant, NULL);
963 * When machine check was for corrected handler don't touch,
964 * unless we're panicing.
966 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
968 __set_bit(i, toclear);
969 if (severity == MCE_NO_SEVERITY) {
971 * Machine check event was not enabled. Clear, but
978 * Kill on action required.
980 if (severity == MCE_AR_SEVERITY)
983 if (m.status & MCI_STATUS_MISCV)
984 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
985 if (m.status & MCI_STATUS_ADDRV)
986 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
989 * Action optional error. Queue address for later processing.
990 * When the ring overflows we just ignore the AO error.
991 * RED-PEN add some logging mechanism when
992 * usable_address or mce_add_ring fails.
993 * RED-PEN don't ignore overflow for tolerant == 0
995 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
996 mce_ring_add(m.addr >> PAGE_SHIFT);
998 mce_get_rip(&m, regs);
1001 if (severity > worst) {
1008 mce_clear_state(toclear);
1011 * Do most of the synchronization with other CPUs.
1012 * When there's any problem use only local no_way_out state.
1014 if (mce_end(order) < 0)
1015 no_way_out = worst >= MCE_PANIC_SEVERITY;
1018 * If we have decided that we just CAN'T continue, and the user
1019 * has not set tolerant to an insane level, give up and die.
1021 * This is mainly used in the case when the system doesn't
1022 * support MCE broadcasting or it has been disabled.
1024 if (no_way_out && tolerant < 3)
1025 mce_panic("Fatal machine check on current CPU", final, msg);
1028 * If the error seems to be unrecoverable, something should be
1029 * done. Try to kill as little as possible. If we can kill just
1030 * one task, do that. If the user has set the tolerance very
1031 * high, don't try to do anything at all.
1034 if (kill_it && tolerant < 3)
1035 force_sig(SIGBUS, current);
1037 /* notify userspace ASAP */
1038 set_thread_flag(TIF_MCE_NOTIFY);
1041 mce_report_event(regs);
1042 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1044 atomic_dec(&mce_entry);
1047 EXPORT_SYMBOL_GPL(do_machine_check);
1049 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1050 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1052 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1056 * Called after mce notification in process context. This code
1057 * is allowed to sleep. Call the high level VM handler to process
1058 * any corrupted pages.
1059 * Assume that the work queue code only calls this one at a time
1061 * Note we don't disable preemption, so this code might run on the wrong
1062 * CPU. In this case the event is picked up by the scheduled work queue.
1063 * This is merely a fast path to expedite processing in some common
1066 void mce_notify_process(void)
1070 while (mce_ring_get(&pfn))
1071 memory_failure(pfn, MCE_VECTOR);
1074 static void mce_process_work(struct work_struct *dummy)
1076 mce_notify_process();
1079 #ifdef CONFIG_X86_MCE_INTEL
1081 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1082 * @cpu: The CPU on which the event occurred.
1083 * @status: Event status information
1085 * This function should be called by the thermal interrupt after the
1086 * event has been processed and the decision was made to log the event
1089 * The status parameter will be saved to the 'status' field of 'struct mce'
1090 * and historically has been the register value of the
1091 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1093 void mce_log_therm_throt_event(__u64 status)
1098 m.bank = MCE_THERMAL_BANK;
1102 #endif /* CONFIG_X86_MCE_INTEL */
1105 * Periodic polling timer for "silent" machine check errors. If the
1106 * poller finds an MCE, poll 2x faster. When the poller finds no more
1107 * errors, poll 2x slower (up to check_interval seconds).
1109 static int check_interval = 5 * 60; /* 5 minutes */
1111 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1112 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1114 static void mcheck_timer(unsigned long data)
1116 struct timer_list *t = &per_cpu(mce_timer, data);
1119 WARN_ON(smp_processor_id() != data);
1121 if (mce_available(¤t_cpu_data)) {
1122 machine_check_poll(MCP_TIMESTAMP,
1123 &__get_cpu_var(mce_poll_banks));
1127 * Alert userspace if needed. If we logged an MCE, reduce the
1128 * polling interval, otherwise increase the polling interval.
1130 n = &__get_cpu_var(mce_next_interval);
1131 if (mce_notify_irq())
1132 *n = max(*n/2, HZ/100);
1134 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1136 t->expires = jiffies + *n;
1137 add_timer_on(t, smp_processor_id());
1140 static void mce_do_trigger(struct work_struct *work)
1142 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1145 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1148 * Notify the user(s) about new machine check events.
1149 * Can be called from interrupt context, but not from machine check/NMI
1152 int mce_notify_irq(void)
1154 /* Not more than two messages every minute */
1155 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1157 clear_thread_flag(TIF_MCE_NOTIFY);
1159 if (test_and_clear_bit(0, &mce_need_notify)) {
1160 wake_up_interruptible(&mce_wait);
1163 * There is no risk of missing notifications because
1164 * work_pending is always cleared before the function is
1167 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1168 schedule_work(&mce_trigger_work);
1170 if (__ratelimit(&ratelimit))
1171 printk(KERN_INFO "Machine check events logged\n");
1177 EXPORT_SYMBOL_GPL(mce_notify_irq);
1179 static int mce_banks_init(void)
1183 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1186 for (i = 0; i < banks; i++) {
1187 struct mce_bank *b = &mce_banks[i];
1196 * Initialize Machine Checks for a CPU.
1198 static int __cpuinit mce_cap_init(void)
1203 rdmsrl(MSR_IA32_MCG_CAP, cap);
1205 b = cap & MCG_BANKCNT_MASK;
1206 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1208 if (b > MAX_NR_BANKS) {
1210 "MCE: Using only %u machine check banks out of %u\n",
1215 /* Don't support asymmetric configurations today */
1216 WARN_ON(banks != 0 && b != banks);
1219 int err = mce_banks_init();
1225 /* Use accurate RIP reporting if available. */
1226 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1227 rip_msr = MSR_IA32_MCG_EIP;
1229 if (cap & MCG_SER_P)
1235 static void mce_init(void)
1237 mce_banks_t all_banks;
1242 * Log the machine checks left over from the previous reset.
1244 bitmap_fill(all_banks, MAX_NR_BANKS);
1245 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1247 set_in_cr4(X86_CR4_MCE);
1249 rdmsrl(MSR_IA32_MCG_CAP, cap);
1250 if (cap & MCG_CTL_P)
1251 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1253 for (i = 0; i < banks; i++) {
1254 struct mce_bank *b = &mce_banks[i];
1258 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1259 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1263 /* Add per CPU specific workarounds here */
1264 static int __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c)
1266 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1267 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1271 /* This should be disabled by the BIOS, but isn't always */
1272 if (c->x86_vendor == X86_VENDOR_AMD) {
1273 if (c->x86 == 15 && banks > 4) {
1275 * disable GART TBL walk error reporting, which
1276 * trips off incorrectly with the IOMMU & 3ware
1279 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1281 if (c->x86 <= 17 && mce_bootlog < 0) {
1283 * Lots of broken BIOS around that don't clear them
1284 * by default and leave crap in there. Don't log:
1289 * Various K7s with broken bank 0 around. Always disable
1292 if (c->x86 == 6 && banks > 0)
1293 mce_banks[0].ctl = 0;
1296 if (c->x86_vendor == X86_VENDOR_INTEL) {
1298 * SDM documents that on family 6 bank 0 should not be written
1299 * because it aliases to another special BIOS controlled
1301 * But it's not aliased anymore on model 0x1a+
1302 * Don't ignore bank 0 completely because there could be a
1303 * valid event later, merely don't write CTL0.
1306 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1307 mce_banks[0].init = 0;
1310 * All newer Intel systems support MCE broadcasting. Enable
1311 * synchronization with a one second timeout.
1313 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1314 monarch_timeout < 0)
1315 monarch_timeout = USEC_PER_SEC;
1318 * There are also broken BIOSes on some Pentium M and
1321 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1324 if (monarch_timeout < 0)
1325 monarch_timeout = 0;
1326 if (mce_bootlog != 0)
1327 mce_panic_timeout = 30;
1332 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
1336 switch (c->x86_vendor) {
1337 case X86_VENDOR_INTEL:
1338 intel_p5_mcheck_init(c);
1340 case X86_VENDOR_CENTAUR:
1341 winchip_mcheck_init(c);
1346 static void mce_cpu_features(struct cpuinfo_x86 *c)
1348 switch (c->x86_vendor) {
1349 case X86_VENDOR_INTEL:
1350 mce_intel_feature_init(c);
1352 case X86_VENDOR_AMD:
1353 mce_amd_feature_init(c);
1360 static void mce_init_timer(void)
1362 struct timer_list *t = &__get_cpu_var(mce_timer);
1363 int *n = &__get_cpu_var(mce_next_interval);
1368 *n = check_interval * HZ;
1371 setup_timer(t, mcheck_timer, smp_processor_id());
1372 t->expires = round_jiffies(jiffies + *n);
1373 add_timer_on(t, smp_processor_id());
1376 /* Handle unconfigured int18 (should never happen) */
1377 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1379 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1380 smp_processor_id());
1383 /* Call the installed machine check handler for this CPU setup. */
1384 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1385 unexpected_machine_check;
1388 * Called for each booted CPU to set up machine checks.
1389 * Must be called with preempt off:
1391 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
1396 mce_ancient_init(c);
1398 if (!mce_available(c))
1401 if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) {
1406 machine_check_vector = do_machine_check;
1409 mce_cpu_features(c);
1411 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1415 * Character device to read and clear the MCE log.
1418 static DEFINE_SPINLOCK(mce_state_lock);
1419 static int open_count; /* #times opened */
1420 static int open_exclu; /* already open exclusive? */
1422 static int mce_open(struct inode *inode, struct file *file)
1424 spin_lock(&mce_state_lock);
1426 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1427 spin_unlock(&mce_state_lock);
1432 if (file->f_flags & O_EXCL)
1436 spin_unlock(&mce_state_lock);
1438 return nonseekable_open(inode, file);
1441 static int mce_release(struct inode *inode, struct file *file)
1443 spin_lock(&mce_state_lock);
1448 spin_unlock(&mce_state_lock);
1453 static void collect_tscs(void *data)
1455 unsigned long *cpu_tsc = (unsigned long *)data;
1457 rdtscll(cpu_tsc[smp_processor_id()]);
1460 static DEFINE_MUTEX(mce_read_mutex);
1462 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1465 char __user *buf = ubuf;
1466 unsigned long *cpu_tsc;
1467 unsigned prev, next;
1470 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1474 mutex_lock(&mce_read_mutex);
1475 next = rcu_dereference(mcelog.next);
1477 /* Only supports full reads right now */
1478 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1479 mutex_unlock(&mce_read_mutex);
1488 for (i = prev; i < next; i++) {
1489 unsigned long start = jiffies;
1491 while (!mcelog.entry[i].finished) {
1492 if (time_after_eq(jiffies, start + 2)) {
1493 memset(mcelog.entry + i, 0,
1494 sizeof(struct mce));
1500 err |= copy_to_user(buf, mcelog.entry + i,
1501 sizeof(struct mce));
1502 buf += sizeof(struct mce);
1507 memset(mcelog.entry + prev, 0,
1508 (next - prev) * sizeof(struct mce));
1510 next = cmpxchg(&mcelog.next, prev, 0);
1511 } while (next != prev);
1513 synchronize_sched();
1516 * Collect entries that were still getting written before the
1519 on_each_cpu(collect_tscs, cpu_tsc, 1);
1521 for (i = next; i < MCE_LOG_LEN; i++) {
1522 if (mcelog.entry[i].finished &&
1523 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1524 err |= copy_to_user(buf, mcelog.entry+i,
1525 sizeof(struct mce));
1527 buf += sizeof(struct mce);
1528 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1531 mutex_unlock(&mce_read_mutex);
1534 return err ? -EFAULT : buf - ubuf;
1537 static unsigned int mce_poll(struct file *file, poll_table *wait)
1539 poll_wait(file, &mce_wait, wait);
1540 if (rcu_dereference(mcelog.next))
1541 return POLLIN | POLLRDNORM;
1545 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1547 int __user *p = (int __user *)arg;
1549 if (!capable(CAP_SYS_ADMIN))
1553 case MCE_GET_RECORD_LEN:
1554 return put_user(sizeof(struct mce), p);
1555 case MCE_GET_LOG_LEN:
1556 return put_user(MCE_LOG_LEN, p);
1557 case MCE_GETCLEAR_FLAGS: {
1561 flags = mcelog.flags;
1562 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1564 return put_user(flags, p);
1571 /* Modified in mce-inject.c, so not static or const */
1572 struct file_operations mce_chrdev_ops = {
1574 .release = mce_release,
1577 .unlocked_ioctl = mce_ioctl,
1579 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1581 static struct miscdevice mce_log_device = {
1588 * mce=off Disables machine check
1589 * mce=no_cmci Disables CMCI
1590 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1591 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1592 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1593 * monarchtimeout is how long to wait for other CPUs on machine
1594 * check, or 0 to not wait
1595 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1596 * mce=nobootlog Don't log MCEs from before booting.
1598 static int __init mcheck_enable(char *str)
1606 if (!strcmp(str, "off"))
1608 else if (!strcmp(str, "no_cmci"))
1609 mce_cmci_disabled = 1;
1610 else if (!strcmp(str, "dont_log_ce"))
1611 mce_dont_log_ce = 1;
1612 else if (!strcmp(str, "ignore_ce"))
1614 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1615 mce_bootlog = (str[0] == 'b');
1616 else if (isdigit(str[0])) {
1617 get_option(&str, &tolerant);
1620 get_option(&str, &monarch_timeout);
1623 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1629 __setup("mce", mcheck_enable);
1636 * Disable machine checks on suspend and shutdown. We can't really handle
1639 static int mce_disable(void)
1643 for (i = 0; i < banks; i++) {
1644 struct mce_bank *b = &mce_banks[i];
1647 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1652 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1654 return mce_disable();
1657 static int mce_shutdown(struct sys_device *dev)
1659 return mce_disable();
1663 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1664 * Only one CPU is active at this time, the others get re-added later using
1667 static int mce_resume(struct sys_device *dev)
1670 mce_cpu_features(¤t_cpu_data);
1675 static void mce_cpu_restart(void *data)
1677 del_timer_sync(&__get_cpu_var(mce_timer));
1678 if (!mce_available(¤t_cpu_data))
1684 /* Reinit MCEs after user configuration changes */
1685 static void mce_restart(void)
1687 on_each_cpu(mce_cpu_restart, NULL, 1);
1690 /* Toggle features for corrected errors */
1691 static void mce_disable_ce(void *all)
1693 if (!mce_available(¤t_cpu_data))
1696 del_timer_sync(&__get_cpu_var(mce_timer));
1700 static void mce_enable_ce(void *all)
1702 if (!mce_available(¤t_cpu_data))
1710 static struct sysdev_class mce_sysclass = {
1711 .suspend = mce_suspend,
1712 .shutdown = mce_shutdown,
1713 .resume = mce_resume,
1714 .name = "machinecheck",
1717 DEFINE_PER_CPU(struct sys_device, mce_dev);
1720 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1722 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1724 return container_of(attr, struct mce_bank, attr);
1727 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1730 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1733 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1734 const char *buf, size_t size)
1738 if (strict_strtoull(buf, 0, &new) < 0)
1741 attr_to_bank(attr)->ctl = new;
1748 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1750 strcpy(buf, mce_helper);
1752 return strlen(mce_helper) + 1;
1755 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1756 const char *buf, size_t siz)
1760 strncpy(mce_helper, buf, sizeof(mce_helper));
1761 mce_helper[sizeof(mce_helper)-1] = 0;
1762 p = strchr(mce_helper, '\n');
1767 return strlen(mce_helper) + !!p;
1770 static ssize_t set_ignore_ce(struct sys_device *s,
1771 struct sysdev_attribute *attr,
1772 const char *buf, size_t size)
1776 if (strict_strtoull(buf, 0, &new) < 0)
1779 if (mce_ignore_ce ^ !!new) {
1781 /* disable ce features */
1782 on_each_cpu(mce_disable_ce, (void *)1, 1);
1785 /* enable ce features */
1787 on_each_cpu(mce_enable_ce, (void *)1, 1);
1793 static ssize_t set_cmci_disabled(struct sys_device *s,
1794 struct sysdev_attribute *attr,
1795 const char *buf, size_t size)
1799 if (strict_strtoull(buf, 0, &new) < 0)
1802 if (mce_cmci_disabled ^ !!new) {
1805 on_each_cpu(mce_disable_ce, NULL, 1);
1806 mce_cmci_disabled = 1;
1809 mce_cmci_disabled = 0;
1810 on_each_cpu(mce_enable_ce, NULL, 1);
1816 static ssize_t store_int_with_restart(struct sys_device *s,
1817 struct sysdev_attribute *attr,
1818 const char *buf, size_t size)
1820 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1825 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1826 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1827 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1828 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1830 static struct sysdev_ext_attribute attr_check_interval = {
1831 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1832 store_int_with_restart),
1836 static struct sysdev_ext_attribute attr_ignore_ce = {
1837 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1841 static struct sysdev_ext_attribute attr_cmci_disabled = {
1842 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1846 static struct sysdev_attribute *mce_attrs[] = {
1847 &attr_tolerant.attr,
1848 &attr_check_interval.attr,
1850 &attr_monarch_timeout.attr,
1851 &attr_dont_log_ce.attr,
1852 &attr_ignore_ce.attr,
1853 &attr_cmci_disabled.attr,
1857 static cpumask_var_t mce_dev_initialized;
1859 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1860 static __cpuinit int mce_create_device(unsigned int cpu)
1865 if (!mce_available(&boot_cpu_data))
1868 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1869 per_cpu(mce_dev, cpu).id = cpu;
1870 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1872 err = sysdev_register(&per_cpu(mce_dev, cpu));
1876 for (i = 0; mce_attrs[i]; i++) {
1877 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1881 for (j = 0; j < banks; j++) {
1882 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1883 &mce_banks[j].attr);
1887 cpumask_set_cpu(cpu, mce_dev_initialized);
1892 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1895 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1897 sysdev_unregister(&per_cpu(mce_dev, cpu));
1902 static __cpuinit void mce_remove_device(unsigned int cpu)
1906 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1909 for (i = 0; mce_attrs[i]; i++)
1910 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1912 for (i = 0; i < banks; i++)
1913 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1915 sysdev_unregister(&per_cpu(mce_dev, cpu));
1916 cpumask_clear_cpu(cpu, mce_dev_initialized);
1919 /* Make sure there are no machine checks on offlined CPUs. */
1920 static void mce_disable_cpu(void *h)
1922 unsigned long action = *(unsigned long *)h;
1925 if (!mce_available(¤t_cpu_data))
1927 if (!(action & CPU_TASKS_FROZEN))
1929 for (i = 0; i < banks; i++) {
1930 struct mce_bank *b = &mce_banks[i];
1933 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1937 static void mce_reenable_cpu(void *h)
1939 unsigned long action = *(unsigned long *)h;
1942 if (!mce_available(¤t_cpu_data))
1945 if (!(action & CPU_TASKS_FROZEN))
1947 for (i = 0; i < banks; i++) {
1948 struct mce_bank *b = &mce_banks[i];
1951 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1955 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1956 static int __cpuinit
1957 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1959 unsigned int cpu = (unsigned long)hcpu;
1960 struct timer_list *t = &per_cpu(mce_timer, cpu);
1964 case CPU_ONLINE_FROZEN:
1965 mce_create_device(cpu);
1966 if (threshold_cpu_callback)
1967 threshold_cpu_callback(action, cpu);
1970 case CPU_DEAD_FROZEN:
1971 if (threshold_cpu_callback)
1972 threshold_cpu_callback(action, cpu);
1973 mce_remove_device(cpu);
1975 case CPU_DOWN_PREPARE:
1976 case CPU_DOWN_PREPARE_FROZEN:
1978 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1980 case CPU_DOWN_FAILED:
1981 case CPU_DOWN_FAILED_FROZEN:
1982 t->expires = round_jiffies(jiffies +
1983 __get_cpu_var(mce_next_interval));
1984 add_timer_on(t, cpu);
1985 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1988 /* intentionally ignoring frozen here */
1989 cmci_rediscover(cpu);
1995 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1996 .notifier_call = mce_cpu_callback,
1999 static __init void mce_init_banks(void)
2003 for (i = 0; i < banks; i++) {
2004 struct mce_bank *b = &mce_banks[i];
2005 struct sysdev_attribute *a = &b->attr;
2007 a->attr.name = b->attrname;
2008 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2010 a->attr.mode = 0644;
2011 a->show = show_bank;
2012 a->store = set_bank;
2016 static __init int mce_init_device(void)
2021 if (!mce_available(&boot_cpu_data))
2024 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2028 err = sysdev_class_register(&mce_sysclass);
2032 for_each_online_cpu(i) {
2033 err = mce_create_device(i);
2038 register_hotcpu_notifier(&mce_cpu_notifier);
2039 misc_register(&mce_log_device);
2044 device_initcall(mce_init_device);
2047 * Old style boot options parsing. Only for compatibility.
2049 static int __init mcheck_disable(char *str)
2054 __setup("nomce", mcheck_disable);
2056 #ifdef CONFIG_DEBUG_FS
2057 struct dentry *mce_get_debugfs_dir(void)
2059 static struct dentry *dmce;
2062 dmce = debugfs_create_dir("mce", NULL);
2067 static void mce_reset(void)
2070 atomic_set(&mce_fake_paniced, 0);
2071 atomic_set(&mce_executing, 0);
2072 atomic_set(&mce_callin, 0);
2073 atomic_set(&global_nwo, 0);
2076 static int fake_panic_get(void *data, u64 *val)
2082 static int fake_panic_set(void *data, u64 val)
2089 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2090 fake_panic_set, "%llu\n");
2092 static int __init mce_debugfs_init(void)
2094 struct dentry *dmce, *ffake_panic;
2096 dmce = mce_get_debugfs_dir();
2099 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2106 late_initcall(mce_debugfs_init);