2 * Routines to indentify caches on Intel CPU.
5 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
6 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
7 * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/compiler.h>
14 #include <linux/cpu.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
18 #include <asm/processor.h>
19 #include <linux/smp.h>
30 unsigned char descriptor;
35 #define MB(x) ((x) * 1024)
37 /* All the cache descriptor types we care about (no TLB or
38 trace cache entries) */
40 static const struct _cache_table __cpuinitconst cache_table[] =
42 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
43 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
44 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
45 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
46 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
48 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
49 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
50 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
51 { 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
52 { 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
53 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
54 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
55 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
56 { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
57 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
58 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
59 { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
60 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
61 { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
62 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
63 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
64 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
65 { 0x44, LVL_2, MB(1) }, /* 4-way set assoc, 32 byte line size */
66 { 0x45, LVL_2, MB(2) }, /* 4-way set assoc, 32 byte line size */
67 { 0x46, LVL_3, MB(4) }, /* 4-way set assoc, 64 byte line size */
68 { 0x47, LVL_3, MB(8) }, /* 8-way set assoc, 64 byte line size */
69 { 0x49, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
70 { 0x4a, LVL_3, MB(6) }, /* 12-way set assoc, 64 byte line size */
71 { 0x4b, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
72 { 0x4c, LVL_3, MB(12) }, /* 12-way set assoc, 64 byte line size */
73 { 0x4d, LVL_3, MB(16) }, /* 16-way set assoc, 64 byte line size */
74 { 0x4e, LVL_2, MB(6) }, /* 24-way set assoc, 64 byte line size */
75 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
76 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
77 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
78 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
79 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
80 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
81 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
82 { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
83 { 0x78, LVL_2, MB(1) }, /* 4-way set assoc, 64 byte line size */
84 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
85 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
86 { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
87 { 0x7c, LVL_2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
88 { 0x7d, LVL_2, MB(2) }, /* 8-way set assoc, 64 byte line size */
89 { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
90 { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
91 { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
92 { 0x84, LVL_2, MB(1) }, /* 8-way set assoc, 32 byte line size */
93 { 0x85, LVL_2, MB(2) }, /* 8-way set assoc, 32 byte line size */
94 { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
95 { 0x87, LVL_2, MB(1) }, /* 8-way set assoc, 64 byte line size */
96 { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
97 { 0xd1, LVL_3, MB(1) }, /* 4-way set assoc, 64 byte line size */
98 { 0xd2, LVL_3, MB(2) }, /* 4-way set assoc, 64 byte line size */
99 { 0xd6, LVL_3, MB(1) }, /* 8-way set assoc, 64 byte line size */
100 { 0xd7, LVL_3, MB(2) }, /* 8-way set assoc, 64 byte line size */
101 { 0xd8, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
102 { 0xdc, LVL_3, MB(2) }, /* 12-way set assoc, 64 byte line size */
103 { 0xdd, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
104 { 0xde, LVL_3, MB(8) }, /* 12-way set assoc, 64 byte line size */
105 { 0xe2, LVL_3, MB(2) }, /* 16-way set assoc, 64 byte line size */
106 { 0xe3, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
107 { 0xe4, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
108 { 0xea, LVL_3, MB(12) }, /* 24-way set assoc, 64 byte line size */
109 { 0xeb, LVL_3, MB(18) }, /* 24-way set assoc, 64 byte line size */
110 { 0xec, LVL_3, MB(24) }, /* 24-way set assoc, 64 byte line size */
119 CACHE_TYPE_UNIFIED = 3
122 union _cpuid4_leaf_eax {
124 enum _cache_type type:5;
125 unsigned int level:3;
126 unsigned int is_self_initializing:1;
127 unsigned int is_fully_associative:1;
128 unsigned int reserved:4;
129 unsigned int num_threads_sharing:12;
130 unsigned int num_cores_on_die:6;
135 union _cpuid4_leaf_ebx {
137 unsigned int coherency_line_size:12;
138 unsigned int physical_line_partition:10;
139 unsigned int ways_of_associativity:10;
144 union _cpuid4_leaf_ecx {
146 unsigned int number_of_sets:32;
151 struct amd_l3_cache {
158 struct _cpuid4_info {
159 union _cpuid4_leaf_eax eax;
160 union _cpuid4_leaf_ebx ebx;
161 union _cpuid4_leaf_ecx ecx;
163 struct amd_l3_cache *l3;
164 DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
167 /* subset of above _cpuid4_info w/o shared_cpu_map */
168 struct _cpuid4_info_regs {
169 union _cpuid4_leaf_eax eax;
170 union _cpuid4_leaf_ebx ebx;
171 union _cpuid4_leaf_ecx ecx;
173 struct amd_l3_cache *l3;
176 unsigned short num_cache_leaves;
178 /* AMD doesn't have CPUID4. Emulate it here to report the same
179 information to the user. This makes some assumptions about the machine:
180 L2 not shared, no SMT etc. that is currently true on AMD CPUs.
182 In theory the TLBs could be reported as fake type (they are in "dummy").
186 unsigned line_size:8;
187 unsigned lines_per_tag:8;
189 unsigned size_in_kb:8;
196 unsigned line_size:8;
197 unsigned lines_per_tag:4;
199 unsigned size_in_kb:16;
206 unsigned line_size:8;
207 unsigned lines_per_tag:4;
210 unsigned size_encoded:14;
215 static const unsigned short __cpuinitconst assocs[] = {
226 [0xf] = 0xffff /* fully associative - no way to show this currently */
229 static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
230 static const unsigned char __cpuinitconst types[] = { 1, 2, 3, 3 };
232 static void __cpuinit
233 amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
234 union _cpuid4_leaf_ebx *ebx,
235 union _cpuid4_leaf_ecx *ecx)
238 unsigned line_size, lines_per_tag, assoc, size_in_kb;
239 union l1_cache l1i, l1d;
242 union l1_cache *l1 = &l1d;
248 cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
249 cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
257 assoc = assocs[l1->assoc];
258 line_size = l1->line_size;
259 lines_per_tag = l1->lines_per_tag;
260 size_in_kb = l1->size_in_kb;
265 assoc = assocs[l2.assoc];
266 line_size = l2.line_size;
267 lines_per_tag = l2.lines_per_tag;
268 /* cpu_data has errata corrections for K7 applied */
269 size_in_kb = current_cpu_data.x86_cache_size;
274 assoc = assocs[l3.assoc];
275 line_size = l3.line_size;
276 lines_per_tag = l3.lines_per_tag;
277 size_in_kb = l3.size_encoded * 512;
278 if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
279 size_in_kb = size_in_kb >> 1;
287 eax->split.is_self_initializing = 1;
288 eax->split.type = types[leaf];
289 eax->split.level = levels[leaf];
290 eax->split.num_threads_sharing = 0;
291 eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
295 eax->split.is_fully_associative = 1;
296 ebx->split.coherency_line_size = line_size - 1;
297 ebx->split.ways_of_associativity = assoc - 1;
298 ebx->split.physical_line_partition = lines_per_tag - 1;
299 ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
300 (ebx->split.ways_of_associativity + 1) - 1;
304 struct attribute attr;
305 ssize_t (*show)(struct _cpuid4_info *, char *);
306 ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
309 #ifdef CONFIG_CPU_SUP_AMD
312 * L3 cache descriptors
314 static struct amd_l3_cache **__cpuinitdata l3_caches;
316 static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3)
318 unsigned int sc0, sc1, sc2, sc3;
321 pci_read_config_dword(l3->dev, 0x1C4, &val);
323 /* calculate subcache sizes */
324 l3->subcaches[0] = sc0 = !(val & BIT(0));
325 l3->subcaches[1] = sc1 = !(val & BIT(4));
326 l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9));
327 l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));
329 l3->indices = (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
332 static struct amd_l3_cache * __cpuinit amd_init_l3_cache(int node)
334 struct amd_l3_cache *l3;
335 struct pci_dev *dev = node_to_k8_nb_misc(node);
337 l3 = kzalloc(sizeof(struct amd_l3_cache), GFP_ATOMIC);
339 printk(KERN_WARNING "Error allocating L3 struct\n");
345 amd_calc_l3_indices(l3);
350 static void __cpuinit
351 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
355 if (boot_cpu_data.x86 != 0x10)
361 /* see errata #382 and #388 */
362 if (boot_cpu_data.x86_model < 0x8)
365 if ((boot_cpu_data.x86_model == 0x8 ||
366 boot_cpu_data.x86_model == 0x9)
368 boot_cpu_data.x86_mask < 0x1)
371 /* not in virtualized environments */
372 if (num_k8_northbridges == 0)
376 * Strictly speaking, the amount in @size below is leaked since it is
377 * never freed but this is done only on shutdown so it doesn't matter.
380 int size = num_k8_northbridges * sizeof(struct amd_l3_cache *);
382 l3_caches = kzalloc(size, GFP_ATOMIC);
387 node = amd_get_nb_id(smp_processor_id());
389 if (!l3_caches[node]) {
390 l3_caches[node] = amd_init_l3_cache(node);
391 l3_caches[node]->can_disable = true;
394 WARN_ON(!l3_caches[node]);
396 this_leaf->l3 = l3_caches[node];
399 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
402 struct pci_dev *dev = this_leaf->l3->dev;
403 unsigned int reg = 0;
405 if (!this_leaf->l3 || !this_leaf->l3->can_disable)
411 pci_read_config_dword(dev, 0x1BC + index * 4, ®);
412 return sprintf(buf, "0x%08x\n", reg);
415 #define SHOW_CACHE_DISABLE(index) \
417 show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
419 return show_cache_disable(this_leaf, buf, index); \
421 SHOW_CACHE_DISABLE(0)
422 SHOW_CACHE_DISABLE(1)
424 static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
425 const char *buf, size_t count, unsigned int index)
427 struct pci_dev *dev = this_leaf->l3->dev;
428 int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
429 unsigned long val = 0;
431 #define SUBCACHE_MASK (3UL << 20)
432 #define SUBCACHE_INDEX 0xfff
434 if (!this_leaf->l3 || !this_leaf->l3->can_disable)
437 if (!capable(CAP_SYS_ADMIN))
443 if (strict_strtoul(buf, 10, &val) < 0)
446 /* do not allow writes outside of allowed bits */
447 if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
448 ((val & SUBCACHE_INDEX) > this_leaf->l3->indices))
452 pci_write_config_dword(dev, 0x1BC + index * 4, val);
454 * We need to WBINVD on a core on the node containing the L3 cache which
455 * indices we disable therefore a simple wbinvd() is not sufficient.
458 pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
462 #define STORE_CACHE_DISABLE(index) \
464 store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
465 const char *buf, size_t count) \
467 return store_cache_disable(this_leaf, buf, count, index); \
469 STORE_CACHE_DISABLE(0)
470 STORE_CACHE_DISABLE(1)
472 static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
473 show_cache_disable_0, store_cache_disable_0);
474 static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
475 show_cache_disable_1, store_cache_disable_1);
477 #else /* CONFIG_CPU_SUP_AMD */
478 static void __cpuinit
479 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
482 #endif /* CONFIG_CPU_SUP_AMD */
485 __cpuinit cpuid4_cache_lookup_regs(int index,
486 struct _cpuid4_info_regs *this_leaf)
488 union _cpuid4_leaf_eax eax;
489 union _cpuid4_leaf_ebx ebx;
490 union _cpuid4_leaf_ecx ecx;
493 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
494 amd_cpuid4(index, &eax, &ebx, &ecx);
495 amd_check_l3_disable(index, this_leaf);
497 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
500 if (eax.split.type == CACHE_TYPE_NULL)
501 return -EIO; /* better error ? */
503 this_leaf->eax = eax;
504 this_leaf->ebx = ebx;
505 this_leaf->ecx = ecx;
506 this_leaf->size = (ecx.split.number_of_sets + 1) *
507 (ebx.split.coherency_line_size + 1) *
508 (ebx.split.physical_line_partition + 1) *
509 (ebx.split.ways_of_associativity + 1);
513 static int __cpuinit find_num_cache_leaves(void)
515 unsigned int eax, ebx, ecx, edx;
516 union _cpuid4_leaf_eax cache_eax;
521 /* Do cpuid(4) loop to find out num_cache_leaves */
522 cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
523 cache_eax.full = eax;
524 } while (cache_eax.split.type != CACHE_TYPE_NULL);
528 unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
531 unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
532 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
533 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
534 unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
536 unsigned int cpu = c->cpu_index;
539 if (c->cpuid_level > 3) {
540 static int is_initialized;
542 if (is_initialized == 0) {
543 /* Init num_cache_leaves from boot CPU */
544 num_cache_leaves = find_num_cache_leaves();
549 * Whenever possible use cpuid(4), deterministic cache
550 * parameters cpuid leaf to find the cache details
552 for (i = 0; i < num_cache_leaves; i++) {
553 struct _cpuid4_info_regs this_leaf;
556 retval = cpuid4_cache_lookup_regs(i, &this_leaf);
558 switch (this_leaf.eax.split.level) {
560 if (this_leaf.eax.split.type ==
562 new_l1d = this_leaf.size/1024;
563 else if (this_leaf.eax.split.type ==
565 new_l1i = this_leaf.size/1024;
568 new_l2 = this_leaf.size/1024;
569 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
570 index_msb = get_count_order(num_threads_sharing);
571 l2_id = c->apicid >> index_msb;
574 new_l3 = this_leaf.size/1024;
575 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
576 index_msb = get_count_order(
577 num_threads_sharing);
578 l3_id = c->apicid >> index_msb;
587 * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
590 if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
591 /* supports eax=2 call */
593 unsigned int regs[4];
594 unsigned char *dp = (unsigned char *)regs;
597 if (num_cache_leaves != 0 && c->x86 == 15)
600 /* Number of times to iterate */
601 n = cpuid_eax(2) & 0xFF;
603 for (i = 0 ; i < n ; i++) {
604 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
606 /* If bit 31 is set, this is an unknown format */
607 for (j = 0 ; j < 3 ; j++)
608 if (regs[j] & (1 << 31))
611 /* Byte 0 is level count, not a descriptor */
612 for (j = 1 ; j < 16 ; j++) {
613 unsigned char des = dp[j];
616 /* look up this descriptor in the table */
617 while (cache_table[k].descriptor != 0) {
618 if (cache_table[k].descriptor == des) {
619 if (only_trace && cache_table[k].cache_type != LVL_TRACE)
621 switch (cache_table[k].cache_type) {
623 l1i += cache_table[k].size;
626 l1d += cache_table[k].size;
629 l2 += cache_table[k].size;
632 l3 += cache_table[k].size;
635 trace += cache_table[k].size;
657 per_cpu(cpu_llc_id, cpu) = l2_id;
664 per_cpu(cpu_llc_id, cpu) = l3_id;
668 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
675 /* pointer to _cpuid4_info array (for each cache leaf) */
676 static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
677 #define CPUID4_INFO_IDX(x, y) (&((per_cpu(ici_cpuid4_info, x))[y]))
680 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
682 struct _cpuid4_info *this_leaf, *sibling_leaf;
683 unsigned long num_threads_sharing;
684 int index_msb, i, sibling;
685 struct cpuinfo_x86 *c = &cpu_data(cpu);
687 if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
688 for_each_cpu(i, c->llc_shared_map) {
689 if (!per_cpu(ici_cpuid4_info, i))
691 this_leaf = CPUID4_INFO_IDX(i, index);
692 for_each_cpu(sibling, c->llc_shared_map) {
693 if (!cpu_online(sibling))
695 set_bit(sibling, this_leaf->shared_cpu_map);
700 this_leaf = CPUID4_INFO_IDX(cpu, index);
701 num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
703 if (num_threads_sharing == 1)
704 cpumask_set_cpu(cpu, to_cpumask(this_leaf->shared_cpu_map));
706 index_msb = get_count_order(num_threads_sharing);
708 for_each_online_cpu(i) {
709 if (cpu_data(i).apicid >> index_msb ==
710 c->apicid >> index_msb) {
712 to_cpumask(this_leaf->shared_cpu_map));
713 if (i != cpu && per_cpu(ici_cpuid4_info, i)) {
715 CPUID4_INFO_IDX(i, index);
716 cpumask_set_cpu(cpu, to_cpumask(
717 sibling_leaf->shared_cpu_map));
723 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
725 struct _cpuid4_info *this_leaf, *sibling_leaf;
728 this_leaf = CPUID4_INFO_IDX(cpu, index);
729 for_each_cpu(sibling, to_cpumask(this_leaf->shared_cpu_map)) {
730 sibling_leaf = CPUID4_INFO_IDX(sibling, index);
731 cpumask_clear_cpu(cpu,
732 to_cpumask(sibling_leaf->shared_cpu_map));
736 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
740 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
745 static void __cpuinit free_cache_attributes(unsigned int cpu)
749 for (i = 0; i < num_cache_leaves; i++)
750 cache_remove_shared_cpu_map(cpu, i);
752 kfree(per_cpu(ici_cpuid4_info, cpu)->l3);
753 kfree(per_cpu(ici_cpuid4_info, cpu));
754 per_cpu(ici_cpuid4_info, cpu) = NULL;
758 __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
760 struct _cpuid4_info_regs *leaf_regs =
761 (struct _cpuid4_info_regs *)this_leaf;
763 return cpuid4_cache_lookup_regs(index, leaf_regs);
766 static void __cpuinit get_cpu_leaves(void *_retval)
768 int j, *retval = _retval, cpu = smp_processor_id();
770 /* Do cpuid and store the results */
771 for (j = 0; j < num_cache_leaves; j++) {
772 struct _cpuid4_info *this_leaf;
773 this_leaf = CPUID4_INFO_IDX(cpu, j);
774 *retval = cpuid4_cache_lookup(j, this_leaf);
775 if (unlikely(*retval < 0)) {
778 for (i = 0; i < j; i++)
779 cache_remove_shared_cpu_map(cpu, i);
782 cache_shared_cpu_map_setup(cpu, j);
786 static int __cpuinit detect_cache_attributes(unsigned int cpu)
790 if (num_cache_leaves == 0)
793 per_cpu(ici_cpuid4_info, cpu) = kzalloc(
794 sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
795 if (per_cpu(ici_cpuid4_info, cpu) == NULL)
798 smp_call_function_single(cpu, get_cpu_leaves, &retval, true);
800 kfree(per_cpu(ici_cpuid4_info, cpu));
801 per_cpu(ici_cpuid4_info, cpu) = NULL;
807 #include <linux/kobject.h>
808 #include <linux/sysfs.h>
810 extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
812 /* pointer to kobject for cpuX/cache */
813 static DEFINE_PER_CPU(struct kobject *, ici_cache_kobject);
815 struct _index_kobject {
818 unsigned short index;
821 /* pointer to array of kobjects for cpuX/cache/indexY */
822 static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject);
823 #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y]))
825 #define show_one_plus(file_name, object, val) \
826 static ssize_t show_##file_name \
827 (struct _cpuid4_info *this_leaf, char *buf) \
829 return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
832 show_one_plus(level, eax.split.level, 0);
833 show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
834 show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
835 show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
836 show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
838 static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
840 return sprintf(buf, "%luK\n", this_leaf->size / 1024);
843 static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
846 ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
850 const struct cpumask *mask;
852 mask = to_cpumask(this_leaf->shared_cpu_map);
854 cpulist_scnprintf(buf, len-2, mask) :
855 cpumask_scnprintf(buf, len-2, mask);
862 static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
864 return show_shared_cpu_map_func(leaf, 0, buf);
867 static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
869 return show_shared_cpu_map_func(leaf, 1, buf);
872 static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
874 switch (this_leaf->eax.split.type) {
875 case CACHE_TYPE_DATA:
876 return sprintf(buf, "Data\n");
877 case CACHE_TYPE_INST:
878 return sprintf(buf, "Instruction\n");
879 case CACHE_TYPE_UNIFIED:
880 return sprintf(buf, "Unified\n");
882 return sprintf(buf, "Unknown\n");
886 #define to_object(k) container_of(k, struct _index_kobject, kobj)
887 #define to_attr(a) container_of(a, struct _cache_attr, attr)
889 #define define_one_ro(_name) \
890 static struct _cache_attr _name = \
891 __ATTR(_name, 0444, show_##_name, NULL)
893 define_one_ro(level);
895 define_one_ro(coherency_line_size);
896 define_one_ro(physical_line_partition);
897 define_one_ro(ways_of_associativity);
898 define_one_ro(number_of_sets);
900 define_one_ro(shared_cpu_map);
901 define_one_ro(shared_cpu_list);
903 #define DEFAULT_SYSFS_CACHE_ATTRS \
906 &coherency_line_size.attr, \
907 &physical_line_partition.attr, \
908 &ways_of_associativity.attr, \
909 &number_of_sets.attr, \
911 &shared_cpu_map.attr, \
912 &shared_cpu_list.attr
914 static struct attribute *default_attrs[] = {
915 DEFAULT_SYSFS_CACHE_ATTRS,
919 static struct attribute *default_l3_attrs[] = {
920 DEFAULT_SYSFS_CACHE_ATTRS,
921 #ifdef CONFIG_CPU_SUP_AMD
922 &cache_disable_0.attr,
923 &cache_disable_1.attr,
928 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
930 struct _cache_attr *fattr = to_attr(attr);
931 struct _index_kobject *this_leaf = to_object(kobj);
935 fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
941 static ssize_t store(struct kobject *kobj, struct attribute *attr,
942 const char *buf, size_t count)
944 struct _cache_attr *fattr = to_attr(attr);
945 struct _index_kobject *this_leaf = to_object(kobj);
949 fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
955 static const struct sysfs_ops sysfs_ops = {
960 static struct kobj_type ktype_cache = {
961 .sysfs_ops = &sysfs_ops,
962 .default_attrs = default_attrs,
965 static struct kobj_type ktype_percpu_entry = {
966 .sysfs_ops = &sysfs_ops,
969 static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
971 kfree(per_cpu(ici_cache_kobject, cpu));
972 kfree(per_cpu(ici_index_kobject, cpu));
973 per_cpu(ici_cache_kobject, cpu) = NULL;
974 per_cpu(ici_index_kobject, cpu) = NULL;
975 free_cache_attributes(cpu);
978 static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
982 if (num_cache_leaves == 0)
985 err = detect_cache_attributes(cpu);
989 /* Allocate all required memory */
990 per_cpu(ici_cache_kobject, cpu) =
991 kzalloc(sizeof(struct kobject), GFP_KERNEL);
992 if (unlikely(per_cpu(ici_cache_kobject, cpu) == NULL))
995 per_cpu(ici_index_kobject, cpu) = kzalloc(
996 sizeof(struct _index_kobject) * num_cache_leaves, GFP_KERNEL);
997 if (unlikely(per_cpu(ici_index_kobject, cpu) == NULL))
1003 cpuid4_cache_sysfs_exit(cpu);
1007 static DECLARE_BITMAP(cache_dev_map, NR_CPUS);
1009 /* Add/Remove cache interface for CPU device */
1010 static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
1012 unsigned int cpu = sys_dev->id;
1014 struct _index_kobject *this_object;
1015 struct _cpuid4_info *this_leaf;
1018 retval = cpuid4_cache_sysfs_init(cpu);
1019 if (unlikely(retval < 0))
1022 retval = kobject_init_and_add(per_cpu(ici_cache_kobject, cpu),
1023 &ktype_percpu_entry,
1024 &sys_dev->kobj, "%s", "cache");
1026 cpuid4_cache_sysfs_exit(cpu);
1030 for (i = 0; i < num_cache_leaves; i++) {
1031 this_object = INDEX_KOBJECT_PTR(cpu, i);
1032 this_object->cpu = cpu;
1033 this_object->index = i;
1035 this_leaf = CPUID4_INFO_IDX(cpu, i);
1037 if (this_leaf->l3 && this_leaf->l3->can_disable)
1038 ktype_cache.default_attrs = default_l3_attrs;
1040 ktype_cache.default_attrs = default_attrs;
1042 retval = kobject_init_and_add(&(this_object->kobj),
1044 per_cpu(ici_cache_kobject, cpu),
1046 if (unlikely(retval)) {
1047 for (j = 0; j < i; j++)
1048 kobject_put(&(INDEX_KOBJECT_PTR(cpu, j)->kobj));
1049 kobject_put(per_cpu(ici_cache_kobject, cpu));
1050 cpuid4_cache_sysfs_exit(cpu);
1053 kobject_uevent(&(this_object->kobj), KOBJ_ADD);
1055 cpumask_set_cpu(cpu, to_cpumask(cache_dev_map));
1057 kobject_uevent(per_cpu(ici_cache_kobject, cpu), KOBJ_ADD);
1061 static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
1063 unsigned int cpu = sys_dev->id;
1066 if (per_cpu(ici_cpuid4_info, cpu) == NULL)
1068 if (!cpumask_test_cpu(cpu, to_cpumask(cache_dev_map)))
1070 cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
1072 for (i = 0; i < num_cache_leaves; i++)
1073 kobject_put(&(INDEX_KOBJECT_PTR(cpu, i)->kobj));
1074 kobject_put(per_cpu(ici_cache_kobject, cpu));
1075 cpuid4_cache_sysfs_exit(cpu);
1078 static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
1079 unsigned long action, void *hcpu)
1081 unsigned int cpu = (unsigned long)hcpu;
1082 struct sys_device *sys_dev;
1084 sys_dev = get_cpu_sysdev(cpu);
1087 case CPU_ONLINE_FROZEN:
1088 cache_add_dev(sys_dev);
1091 case CPU_DEAD_FROZEN:
1092 cache_remove_dev(sys_dev);
1098 static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier = {
1099 .notifier_call = cacheinfo_cpu_callback,
1102 static int __cpuinit cache_sysfs_init(void)
1106 if (num_cache_leaves == 0)
1109 for_each_online_cpu(i) {
1111 struct sys_device *sys_dev = get_cpu_sysdev(i);
1113 err = cache_add_dev(sys_dev);
1117 register_hotcpu_notifier(&cacheinfo_cpu_notifier);
1121 device_initcall(cache_sysfs_init);