2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
58 #include <asm/msidef.h>
59 #include <asm/hypertransport.h>
60 #include <asm/setup.h>
61 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
72 * Is the SiS APIC rmw bug present ?
73 * -1 = don't know, 0 = no, 1 = yes
75 int sis_apic_bug = -1;
77 static DEFINE_RAW_SPINLOCK(ioapic_lock);
78 static DEFINE_RAW_SPINLOCK(vector_lock);
81 * # of IRQ routing registers
83 int nr_ioapic_registers[MAX_IO_APICS];
85 /* I/O APIC entries */
86 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
89 /* IO APIC gsi routing info */
90 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
92 /* The one past the highest gsi number used */
95 /* MP IRQ source entries */
96 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
98 /* # of MP IRQ source entries */
102 static int nr_irqs_gsi = NR_IRQS_LEGACY;
104 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
105 int mp_bus_id_to_type[MAX_MP_BUSSES];
108 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
110 int skip_ioapic_setup;
112 void arch_disable_smp_support(void)
116 noioapicreroute = -1;
118 skip_ioapic_setup = 1;
121 static int __init parse_noapic(char *str)
123 /* disable IO-APIC */
124 arch_disable_smp_support();
127 early_param("noapic", parse_noapic);
129 struct irq_pin_list {
131 struct irq_pin_list *next;
134 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
136 struct irq_pin_list *pin;
138 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
143 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
144 #ifdef CONFIG_SPARSE_IRQ
145 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
147 static struct irq_cfg irq_cfgx[NR_IRQS];
150 int __init arch_early_irq_init(void)
153 struct irq_desc *desc;
158 if (!legacy_pic->nr_legacy_irqs) {
164 count = ARRAY_SIZE(irq_cfgx);
165 node= cpu_to_node(boot_cpu_id);
167 for (i = 0; i < count; i++) {
168 desc = irq_to_desc(i);
169 desc->chip_data = &cfg[i];
170 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
171 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
173 * For legacy IRQ's, start with assigning irq0 to irq15 to
174 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
176 if (i < legacy_pic->nr_legacy_irqs) {
177 cfg[i].vector = IRQ0_VECTOR + i;
178 cpumask_set_cpu(0, cfg[i].domain);
185 #ifdef CONFIG_SPARSE_IRQ
186 struct irq_cfg *irq_cfg(unsigned int irq)
188 struct irq_cfg *cfg = NULL;
189 struct irq_desc *desc;
191 desc = irq_to_desc(irq);
193 cfg = desc->chip_data;
198 static struct irq_cfg *get_one_free_irq_cfg(int node)
202 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
204 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
207 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
209 free_cpumask_var(cfg->domain);
218 int arch_init_chip_data(struct irq_desc *desc, int node)
222 cfg = desc->chip_data;
224 desc->chip_data = get_one_free_irq_cfg(node);
225 if (!desc->chip_data) {
226 printk(KERN_ERR "can not alloc irq_cfg\n");
234 /* for move_irq_desc */
236 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
238 struct irq_pin_list *old_entry, *head, *tail, *entry;
240 cfg->irq_2_pin = NULL;
241 old_entry = old_cfg->irq_2_pin;
245 entry = get_one_free_irq_2_pin(node);
249 entry->apic = old_entry->apic;
250 entry->pin = old_entry->pin;
253 old_entry = old_entry->next;
255 entry = get_one_free_irq_2_pin(node);
263 /* still use the old one */
266 entry->apic = old_entry->apic;
267 entry->pin = old_entry->pin;
270 old_entry = old_entry->next;
274 cfg->irq_2_pin = head;
277 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
279 struct irq_pin_list *entry, *next;
281 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
284 entry = old_cfg->irq_2_pin;
291 old_cfg->irq_2_pin = NULL;
294 void arch_init_copy_chip_data(struct irq_desc *old_desc,
295 struct irq_desc *desc, int node)
298 struct irq_cfg *old_cfg;
300 cfg = get_one_free_irq_cfg(node);
305 desc->chip_data = cfg;
307 old_cfg = old_desc->chip_data;
309 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
311 init_copy_irq_2_pin(old_cfg, cfg, node);
314 static void free_irq_cfg(struct irq_cfg *old_cfg)
319 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
321 struct irq_cfg *old_cfg, *cfg;
323 old_cfg = old_desc->chip_data;
324 cfg = desc->chip_data;
330 free_irq_2_pin(old_cfg, cfg);
331 free_irq_cfg(old_cfg);
332 old_desc->chip_data = NULL;
335 /* end for move_irq_desc */
338 struct irq_cfg *irq_cfg(unsigned int irq)
340 return irq < nr_irqs ? irq_cfgx + irq : NULL;
347 unsigned int unused[3];
349 unsigned int unused2[11];
353 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
355 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
356 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
359 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
361 struct io_apic __iomem *io_apic = io_apic_base(apic);
362 writel(vector, &io_apic->eoi);
365 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
367 struct io_apic __iomem *io_apic = io_apic_base(apic);
368 writel(reg, &io_apic->index);
369 return readl(&io_apic->data);
372 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
374 struct io_apic __iomem *io_apic = io_apic_base(apic);
375 writel(reg, &io_apic->index);
376 writel(value, &io_apic->data);
380 * Re-write a value: to be used for read-modify-write
381 * cycles where the read already set up the index register.
383 * Older SiS APIC requires we rewrite the index register
385 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
387 struct io_apic __iomem *io_apic = io_apic_base(apic);
390 writel(reg, &io_apic->index);
391 writel(value, &io_apic->data);
394 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
396 struct irq_pin_list *entry;
399 raw_spin_lock_irqsave(&ioapic_lock, flags);
400 for_each_irq_pin(entry, cfg->irq_2_pin) {
405 reg = io_apic_read(entry->apic, 0x10 + pin*2);
406 /* Is the remote IRR bit set? */
407 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
408 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
412 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
418 struct { u32 w1, w2; };
419 struct IO_APIC_route_entry entry;
422 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
424 union entry_union eu;
426 raw_spin_lock_irqsave(&ioapic_lock, flags);
427 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
428 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
429 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
434 * When we write a new IO APIC routing entry, we need to write the high
435 * word first! If the mask bit in the low word is clear, we will enable
436 * the interrupt, and we need to make sure the entry is fully populated
437 * before that happens.
440 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
442 union entry_union eu = {{0, 0}};
445 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
446 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
449 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
452 raw_spin_lock_irqsave(&ioapic_lock, flags);
453 __ioapic_write_entry(apic, pin, e);
454 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
458 * When we mask an IO APIC routing entry, we need to write the low
459 * word first, in order to set the mask bit before we change the
462 static void ioapic_mask_entry(int apic, int pin)
465 union entry_union eu = { .entry.mask = 1 };
467 raw_spin_lock_irqsave(&ioapic_lock, flags);
468 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
469 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
470 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
474 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
475 * shared ISA-space IRQs, so we have to support them. We are super
476 * fast in the common case, and fast for shared ISA-space IRQs.
479 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
481 struct irq_pin_list **last, *entry;
483 /* don't allow duplicates */
484 last = &cfg->irq_2_pin;
485 for_each_irq_pin(entry, cfg->irq_2_pin) {
486 if (entry->apic == apic && entry->pin == pin)
491 entry = get_one_free_irq_2_pin(node);
493 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
504 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
506 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
507 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
511 * Reroute an IRQ to a different pin.
513 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
514 int oldapic, int oldpin,
515 int newapic, int newpin)
517 struct irq_pin_list *entry;
519 for_each_irq_pin(entry, cfg->irq_2_pin) {
520 if (entry->apic == oldapic && entry->pin == oldpin) {
521 entry->apic = newapic;
523 /* every one is different, right? */
528 /* old apic/pin didn't exist, so just add new ones */
529 add_pin_to_irq_node(cfg, node, newapic, newpin);
532 static void __io_apic_modify_irq(struct irq_pin_list *entry,
533 int mask_and, int mask_or,
534 void (*final)(struct irq_pin_list *entry))
536 unsigned int reg, pin;
539 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
542 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
547 static void io_apic_modify_irq(struct irq_cfg *cfg,
548 int mask_and, int mask_or,
549 void (*final)(struct irq_pin_list *entry))
551 struct irq_pin_list *entry;
553 for_each_irq_pin(entry, cfg->irq_2_pin)
554 __io_apic_modify_irq(entry, mask_and, mask_or, final);
557 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
559 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
560 IO_APIC_REDIR_MASKED, NULL);
563 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
565 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
566 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
569 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
571 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
574 static void io_apic_sync(struct irq_pin_list *entry)
577 * Synchronize the IO-APIC and the CPU by doing
578 * a dummy read from the IO-APIC
580 struct io_apic __iomem *io_apic;
581 io_apic = io_apic_base(entry->apic);
582 readl(&io_apic->data);
585 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
587 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
590 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
592 struct irq_cfg *cfg = desc->chip_data;
597 raw_spin_lock_irqsave(&ioapic_lock, flags);
598 __mask_IO_APIC_irq(cfg);
599 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
602 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
604 struct irq_cfg *cfg = desc->chip_data;
607 raw_spin_lock_irqsave(&ioapic_lock, flags);
608 __unmask_IO_APIC_irq(cfg);
609 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
612 static void mask_IO_APIC_irq(unsigned int irq)
614 struct irq_desc *desc = irq_to_desc(irq);
616 mask_IO_APIC_irq_desc(desc);
618 static void unmask_IO_APIC_irq(unsigned int irq)
620 struct irq_desc *desc = irq_to_desc(irq);
622 unmask_IO_APIC_irq_desc(desc);
625 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
627 struct IO_APIC_route_entry entry;
629 /* Check delivery_mode to be sure we're not clearing an SMI pin */
630 entry = ioapic_read_entry(apic, pin);
631 if (entry.delivery_mode == dest_SMI)
634 * Disable it in the IO-APIC irq-routing table:
636 ioapic_mask_entry(apic, pin);
639 static void clear_IO_APIC (void)
643 for (apic = 0; apic < nr_ioapics; apic++)
644 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
645 clear_IO_APIC_pin(apic, pin);
650 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
651 * specific CPU-side IRQs.
655 static int pirq_entries[MAX_PIRQS] = {
656 [0 ... MAX_PIRQS - 1] = -1
659 static int __init ioapic_pirq_setup(char *str)
662 int ints[MAX_PIRQS+1];
664 get_options(str, ARRAY_SIZE(ints), ints);
666 apic_printk(APIC_VERBOSE, KERN_INFO
667 "PIRQ redirection, working around broken MP-BIOS.\n");
669 if (ints[0] < MAX_PIRQS)
672 for (i = 0; i < max; i++) {
673 apic_printk(APIC_VERBOSE, KERN_DEBUG
674 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
676 * PIRQs are mapped upside down, usually.
678 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
683 __setup("pirq=", ioapic_pirq_setup);
684 #endif /* CONFIG_X86_32 */
686 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
689 struct IO_APIC_route_entry **ioapic_entries;
691 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
696 for (apic = 0; apic < nr_ioapics; apic++) {
697 ioapic_entries[apic] =
698 kzalloc(sizeof(struct IO_APIC_route_entry) *
699 nr_ioapic_registers[apic], GFP_ATOMIC);
700 if (!ioapic_entries[apic])
704 return ioapic_entries;
708 kfree(ioapic_entries[apic]);
709 kfree(ioapic_entries);
715 * Saves all the IO-APIC RTE's
717 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
724 for (apic = 0; apic < nr_ioapics; apic++) {
725 if (!ioapic_entries[apic])
728 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
729 ioapic_entries[apic][pin] =
730 ioapic_read_entry(apic, pin);
737 * Mask all IO APIC entries.
739 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
746 for (apic = 0; apic < nr_ioapics; apic++) {
747 if (!ioapic_entries[apic])
750 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
751 struct IO_APIC_route_entry entry;
753 entry = ioapic_entries[apic][pin];
756 ioapic_write_entry(apic, pin, entry);
763 * Restore IO APIC entries which was saved in ioapic_entries.
765 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
772 for (apic = 0; apic < nr_ioapics; apic++) {
773 if (!ioapic_entries[apic])
776 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
777 ioapic_write_entry(apic, pin,
778 ioapic_entries[apic][pin]);
783 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
787 for (apic = 0; apic < nr_ioapics; apic++)
788 kfree(ioapic_entries[apic]);
790 kfree(ioapic_entries);
794 * Find the IRQ entry number of a certain pin.
796 static int find_irq_entry(int apic, int pin, int type)
800 for (i = 0; i < mp_irq_entries; i++)
801 if (mp_irqs[i].irqtype == type &&
802 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
803 mp_irqs[i].dstapic == MP_APIC_ALL) &&
804 mp_irqs[i].dstirq == pin)
811 * Find the pin to which IRQ[irq] (ISA) is connected
813 static int __init find_isa_irq_pin(int irq, int type)
817 for (i = 0; i < mp_irq_entries; i++) {
818 int lbus = mp_irqs[i].srcbus;
820 if (test_bit(lbus, mp_bus_not_pci) &&
821 (mp_irqs[i].irqtype == type) &&
822 (mp_irqs[i].srcbusirq == irq))
824 return mp_irqs[i].dstirq;
829 static int __init find_isa_irq_apic(int irq, int type)
833 for (i = 0; i < mp_irq_entries; i++) {
834 int lbus = mp_irqs[i].srcbus;
836 if (test_bit(lbus, mp_bus_not_pci) &&
837 (mp_irqs[i].irqtype == type) &&
838 (mp_irqs[i].srcbusirq == irq))
841 if (i < mp_irq_entries) {
843 for(apic = 0; apic < nr_ioapics; apic++) {
844 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
852 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
854 * EISA Edge/Level control register, ELCR
856 static int EISA_ELCR(unsigned int irq)
858 if (irq < legacy_pic->nr_legacy_irqs) {
859 unsigned int port = 0x4d0 + (irq >> 3);
860 return (inb(port) >> (irq & 7)) & 1;
862 apic_printk(APIC_VERBOSE, KERN_INFO
863 "Broken MPtable reports ISA irq %d\n", irq);
869 /* ISA interrupts are always polarity zero edge triggered,
870 * when listed as conforming in the MP table. */
872 #define default_ISA_trigger(idx) (0)
873 #define default_ISA_polarity(idx) (0)
875 /* EISA interrupts are always polarity zero and can be edge or level
876 * trigger depending on the ELCR value. If an interrupt is listed as
877 * EISA conforming in the MP table, that means its trigger type must
878 * be read in from the ELCR */
880 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
881 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
883 /* PCI interrupts are always polarity one level triggered,
884 * when listed as conforming in the MP table. */
886 #define default_PCI_trigger(idx) (1)
887 #define default_PCI_polarity(idx) (1)
889 /* MCA interrupts are always polarity zero level triggered,
890 * when listed as conforming in the MP table. */
892 #define default_MCA_trigger(idx) (1)
893 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
895 static int MPBIOS_polarity(int idx)
897 int bus = mp_irqs[idx].srcbus;
901 * Determine IRQ line polarity (high active or low active):
903 switch (mp_irqs[idx].irqflag & 3)
905 case 0: /* conforms, ie. bus-type dependent polarity */
906 if (test_bit(bus, mp_bus_not_pci))
907 polarity = default_ISA_polarity(idx);
909 polarity = default_PCI_polarity(idx);
911 case 1: /* high active */
916 case 2: /* reserved */
918 printk(KERN_WARNING "broken BIOS!!\n");
922 case 3: /* low active */
927 default: /* invalid */
929 printk(KERN_WARNING "broken BIOS!!\n");
937 static int MPBIOS_trigger(int idx)
939 int bus = mp_irqs[idx].srcbus;
943 * Determine IRQ trigger mode (edge or level sensitive):
945 switch ((mp_irqs[idx].irqflag>>2) & 3)
947 case 0: /* conforms, ie. bus-type dependent */
948 if (test_bit(bus, mp_bus_not_pci))
949 trigger = default_ISA_trigger(idx);
951 trigger = default_PCI_trigger(idx);
952 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
953 switch (mp_bus_id_to_type[bus]) {
954 case MP_BUS_ISA: /* ISA pin */
956 /* set before the switch */
959 case MP_BUS_EISA: /* EISA pin */
961 trigger = default_EISA_trigger(idx);
964 case MP_BUS_PCI: /* PCI pin */
966 /* set before the switch */
969 case MP_BUS_MCA: /* MCA pin */
971 trigger = default_MCA_trigger(idx);
976 printk(KERN_WARNING "broken BIOS!!\n");
988 case 2: /* reserved */
990 printk(KERN_WARNING "broken BIOS!!\n");
999 default: /* invalid */
1001 printk(KERN_WARNING "broken BIOS!!\n");
1009 static inline int irq_polarity(int idx)
1011 return MPBIOS_polarity(idx);
1014 static inline int irq_trigger(int idx)
1016 return MPBIOS_trigger(idx);
1019 static int pin_2_irq(int idx, int apic, int pin)
1022 int bus = mp_irqs[idx].srcbus;
1025 * Debugging check, we are in big trouble if this message pops up!
1027 if (mp_irqs[idx].dstirq != pin)
1028 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1030 if (test_bit(bus, mp_bus_not_pci)) {
1031 irq = mp_irqs[idx].srcbusirq;
1033 u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
1035 if (gsi >= NR_IRQS_LEGACY)
1038 irq = gsi_top + gsi;
1041 #ifdef CONFIG_X86_32
1043 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1045 if ((pin >= 16) && (pin <= 23)) {
1046 if (pirq_entries[pin-16] != -1) {
1047 if (!pirq_entries[pin-16]) {
1048 apic_printk(APIC_VERBOSE, KERN_DEBUG
1049 "disabling PIRQ%d\n", pin-16);
1051 irq = pirq_entries[pin-16];
1052 apic_printk(APIC_VERBOSE, KERN_DEBUG
1053 "using PIRQ%d -> IRQ %d\n",
1064 * Find a specific PCI IRQ entry.
1065 * Not an __init, possibly needed by modules
1067 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1068 struct io_apic_irq_attr *irq_attr)
1070 int apic, i, best_guess = -1;
1072 apic_printk(APIC_DEBUG,
1073 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1075 if (test_bit(bus, mp_bus_not_pci)) {
1076 apic_printk(APIC_VERBOSE,
1077 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1080 for (i = 0; i < mp_irq_entries; i++) {
1081 int lbus = mp_irqs[i].srcbus;
1083 for (apic = 0; apic < nr_ioapics; apic++)
1084 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1085 mp_irqs[i].dstapic == MP_APIC_ALL)
1088 if (!test_bit(lbus, mp_bus_not_pci) &&
1089 !mp_irqs[i].irqtype &&
1091 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1092 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1094 if (!(apic || IO_APIC_IRQ(irq)))
1097 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1098 set_io_apic_irq_attr(irq_attr, apic,
1105 * Use the first all-but-pin matching entry as a
1106 * best-guess fuzzy result for broken mptables.
1108 if (best_guess < 0) {
1109 set_io_apic_irq_attr(irq_attr, apic,
1119 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1121 void lock_vector_lock(void)
1123 /* Used to the online set of cpus does not change
1124 * during assign_irq_vector.
1126 raw_spin_lock(&vector_lock);
1129 void unlock_vector_lock(void)
1131 raw_spin_unlock(&vector_lock);
1135 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1138 * NOTE! The local APIC isn't very good at handling
1139 * multiple interrupts at the same interrupt level.
1140 * As the interrupt level is determined by taking the
1141 * vector number and shifting that right by 4, we
1142 * want to spread these out a bit so that they don't
1143 * all fall in the same interrupt level.
1145 * Also, we've got to be careful not to trash gate
1146 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1148 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1149 static int current_offset = VECTOR_OFFSET_START % 8;
1150 unsigned int old_vector;
1152 cpumask_var_t tmp_mask;
1154 if (cfg->move_in_progress)
1157 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1160 old_vector = cfg->vector;
1162 cpumask_and(tmp_mask, mask, cpu_online_mask);
1163 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1164 if (!cpumask_empty(tmp_mask)) {
1165 free_cpumask_var(tmp_mask);
1170 /* Only try and allocate irqs on cpus that are present */
1172 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1176 apic->vector_allocation_domain(cpu, tmp_mask);
1178 vector = current_vector;
1179 offset = current_offset;
1182 if (vector >= first_system_vector) {
1183 /* If out of vectors on large boxen, must share them. */
1184 offset = (offset + 1) % 8;
1185 vector = FIRST_EXTERNAL_VECTOR + offset;
1187 if (unlikely(current_vector == vector))
1190 if (test_bit(vector, used_vectors))
1193 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1194 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1197 current_vector = vector;
1198 current_offset = offset;
1200 cfg->move_in_progress = 1;
1201 cpumask_copy(cfg->old_domain, cfg->domain);
1203 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1204 per_cpu(vector_irq, new_cpu)[vector] = irq;
1205 cfg->vector = vector;
1206 cpumask_copy(cfg->domain, tmp_mask);
1210 free_cpumask_var(tmp_mask);
1214 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1217 unsigned long flags;
1219 raw_spin_lock_irqsave(&vector_lock, flags);
1220 err = __assign_irq_vector(irq, cfg, mask);
1221 raw_spin_unlock_irqrestore(&vector_lock, flags);
1225 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1229 BUG_ON(!cfg->vector);
1231 vector = cfg->vector;
1232 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1233 per_cpu(vector_irq, cpu)[vector] = -1;
1236 cpumask_clear(cfg->domain);
1238 if (likely(!cfg->move_in_progress))
1240 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1241 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1243 if (per_cpu(vector_irq, cpu)[vector] != irq)
1245 per_cpu(vector_irq, cpu)[vector] = -1;
1249 cfg->move_in_progress = 0;
1252 void __setup_vector_irq(int cpu)
1254 /* Initialize vector_irq on a new cpu */
1256 struct irq_cfg *cfg;
1257 struct irq_desc *desc;
1260 * vector_lock will make sure that we don't run into irq vector
1261 * assignments that might be happening on another cpu in parallel,
1262 * while we setup our initial vector to irq mappings.
1264 raw_spin_lock(&vector_lock);
1265 /* Mark the inuse vectors */
1266 for_each_irq_desc(irq, desc) {
1267 cfg = desc->chip_data;
1270 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1271 * will be part of the irq_cfg's domain.
1273 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1274 cpumask_set_cpu(cpu, cfg->domain);
1276 if (!cpumask_test_cpu(cpu, cfg->domain))
1278 vector = cfg->vector;
1279 per_cpu(vector_irq, cpu)[vector] = irq;
1281 /* Mark the free vectors */
1282 for (vector = 0; vector < NR_VECTORS; ++vector) {
1283 irq = per_cpu(vector_irq, cpu)[vector];
1288 if (!cpumask_test_cpu(cpu, cfg->domain))
1289 per_cpu(vector_irq, cpu)[vector] = -1;
1291 raw_spin_unlock(&vector_lock);
1294 static struct irq_chip ioapic_chip;
1295 static struct irq_chip ir_ioapic_chip;
1297 #define IOAPIC_AUTO -1
1298 #define IOAPIC_EDGE 0
1299 #define IOAPIC_LEVEL 1
1301 #ifdef CONFIG_X86_32
1302 static inline int IO_APIC_irq_trigger(int irq)
1306 for (apic = 0; apic < nr_ioapics; apic++) {
1307 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1308 idx = find_irq_entry(apic, pin, mp_INT);
1309 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1310 return irq_trigger(idx);
1314 * nonexistent IRQs are edge default
1319 static inline int IO_APIC_irq_trigger(int irq)
1325 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1328 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1329 trigger == IOAPIC_LEVEL)
1330 desc->status |= IRQ_LEVEL;
1332 desc->status &= ~IRQ_LEVEL;
1334 if (irq_remapped(irq)) {
1335 desc->status |= IRQ_MOVE_PCNTXT;
1337 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1341 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1342 handle_edge_irq, "edge");
1346 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1347 trigger == IOAPIC_LEVEL)
1348 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1352 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1353 handle_edge_irq, "edge");
1356 int setup_ioapic_entry(int apic_id, int irq,
1357 struct IO_APIC_route_entry *entry,
1358 unsigned int destination, int trigger,
1359 int polarity, int vector, int pin)
1362 * add it to the IO-APIC irq-routing table:
1364 memset(entry,0,sizeof(*entry));
1366 if (intr_remapping_enabled) {
1367 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1369 struct IR_IO_APIC_route_entry *ir_entry =
1370 (struct IR_IO_APIC_route_entry *) entry;
1374 panic("No mapping iommu for ioapic %d\n", apic_id);
1376 index = alloc_irte(iommu, irq, 1);
1378 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1380 memset(&irte, 0, sizeof(irte));
1383 irte.dst_mode = apic->irq_dest_mode;
1385 * Trigger mode in the IRTE will always be edge, and the
1386 * actual level or edge trigger will be setup in the IO-APIC
1387 * RTE. This will help simplify level triggered irq migration.
1388 * For more details, see the comments above explainig IO-APIC
1389 * irq migration in the presence of interrupt-remapping.
1391 irte.trigger_mode = 0;
1392 irte.dlvry_mode = apic->irq_delivery_mode;
1393 irte.vector = vector;
1394 irte.dest_id = IRTE_DEST(destination);
1395 irte.redir_hint = 1;
1397 /* Set source-id of interrupt request */
1398 set_ioapic_sid(&irte, apic_id);
1400 modify_irte(irq, &irte);
1402 ir_entry->index2 = (index >> 15) & 0x1;
1404 ir_entry->format = 1;
1405 ir_entry->index = (index & 0x7fff);
1407 * IO-APIC RTE will be configured with virtual vector.
1408 * irq handler will do the explicit EOI to the io-apic.
1410 ir_entry->vector = pin;
1412 entry->delivery_mode = apic->irq_delivery_mode;
1413 entry->dest_mode = apic->irq_dest_mode;
1414 entry->dest = destination;
1415 entry->vector = vector;
1418 entry->mask = 0; /* enable IRQ */
1419 entry->trigger = trigger;
1420 entry->polarity = polarity;
1422 /* Mask level triggered irqs.
1423 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1430 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1431 int trigger, int polarity)
1433 struct irq_cfg *cfg;
1434 struct IO_APIC_route_entry entry;
1437 if (!IO_APIC_IRQ(irq))
1440 cfg = desc->chip_data;
1443 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1444 * controllers like 8259. Now that IO-APIC can handle this irq, update
1447 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1448 apic->vector_allocation_domain(0, cfg->domain);
1450 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1453 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1455 apic_printk(APIC_VERBOSE,KERN_DEBUG
1456 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1457 "IRQ %d Mode:%i Active:%i)\n",
1458 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1459 irq, trigger, polarity);
1462 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1463 dest, trigger, polarity, cfg->vector, pin)) {
1464 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1465 mp_ioapics[apic_id].apicid, pin);
1466 __clear_irq_vector(irq, cfg);
1470 ioapic_register_intr(irq, desc, trigger);
1471 if (irq < legacy_pic->nr_legacy_irqs)
1472 legacy_pic->chip->mask(irq);
1474 ioapic_write_entry(apic_id, pin, entry);
1478 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1479 } mp_ioapic_routing[MAX_IO_APICS];
1481 static void __init setup_IO_APIC_irqs(void)
1483 int apic_id, pin, idx, irq;
1485 struct irq_desc *desc;
1486 struct irq_cfg *cfg;
1487 int node = cpu_to_node(boot_cpu_id);
1489 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1491 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1492 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1493 idx = find_irq_entry(apic_id, pin, mp_INT);
1497 apic_printk(APIC_VERBOSE,
1498 KERN_DEBUG " %d-%d",
1499 mp_ioapics[apic_id].apicid, pin);
1501 apic_printk(APIC_VERBOSE, " %d-%d",
1502 mp_ioapics[apic_id].apicid, pin);
1506 apic_printk(APIC_VERBOSE,
1507 " (apicid-pin) not connected\n");
1511 irq = pin_2_irq(idx, apic_id, pin);
1513 if ((apic_id > 0) && (irq > 16))
1517 * Skip the timer IRQ if there's a quirk handler
1518 * installed and if it returns 1:
1520 if (apic->multi_timer_check &&
1521 apic->multi_timer_check(apic_id, irq))
1524 desc = irq_to_desc_alloc_node(irq, node);
1526 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1529 cfg = desc->chip_data;
1530 add_pin_to_irq_node(cfg, node, apic_id, pin);
1532 * don't mark it in pin_programmed, so later acpi could
1533 * set it correctly when irq < 16
1535 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1536 irq_trigger(idx), irq_polarity(idx));
1540 apic_printk(APIC_VERBOSE,
1541 " (apicid-pin) not connected\n");
1545 * for the gsit that is not in first ioapic
1546 * but could not use acpi_register_gsi()
1547 * like some special sci in IBM x3330
1549 void setup_IO_APIC_irq_extra(u32 gsi)
1551 int apic_id = 0, pin, idx, irq;
1552 int node = cpu_to_node(boot_cpu_id);
1553 struct irq_desc *desc;
1554 struct irq_cfg *cfg;
1557 * Convert 'gsi' to 'ioapic.pin'.
1559 apic_id = mp_find_ioapic(gsi);
1563 pin = mp_find_ioapic_pin(apic_id, gsi);
1564 idx = find_irq_entry(apic_id, pin, mp_INT);
1568 irq = pin_2_irq(idx, apic_id, pin);
1569 #ifdef CONFIG_SPARSE_IRQ
1570 desc = irq_to_desc(irq);
1574 desc = irq_to_desc_alloc_node(irq, node);
1576 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1580 cfg = desc->chip_data;
1581 add_pin_to_irq_node(cfg, node, apic_id, pin);
1583 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1584 pr_debug("Pin %d-%d already programmed\n",
1585 mp_ioapics[apic_id].apicid, pin);
1588 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1590 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1591 irq_trigger(idx), irq_polarity(idx));
1595 * Set up the timer pin, possibly with the 8259A-master behind.
1597 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1600 struct IO_APIC_route_entry entry;
1602 if (intr_remapping_enabled)
1605 memset(&entry, 0, sizeof(entry));
1608 * We use logical delivery to get the timer IRQ
1611 entry.dest_mode = apic->irq_dest_mode;
1612 entry.mask = 0; /* don't mask IRQ for edge */
1613 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1614 entry.delivery_mode = apic->irq_delivery_mode;
1617 entry.vector = vector;
1620 * The timer IRQ doesn't have to know that behind the
1621 * scene we may have a 8259A-master in AEOI mode ...
1623 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1626 * Add it to the IO-APIC irq-routing table:
1628 ioapic_write_entry(apic_id, pin, entry);
1632 __apicdebuginit(void) print_IO_APIC(void)
1635 union IO_APIC_reg_00 reg_00;
1636 union IO_APIC_reg_01 reg_01;
1637 union IO_APIC_reg_02 reg_02;
1638 union IO_APIC_reg_03 reg_03;
1639 unsigned long flags;
1640 struct irq_cfg *cfg;
1641 struct irq_desc *desc;
1644 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1645 for (i = 0; i < nr_ioapics; i++)
1646 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1647 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1650 * We are a bit conservative about what we expect. We have to
1651 * know about every hardware change ASAP.
1653 printk(KERN_INFO "testing the IO APIC.......................\n");
1655 for (apic = 0; apic < nr_ioapics; apic++) {
1657 raw_spin_lock_irqsave(&ioapic_lock, flags);
1658 reg_00.raw = io_apic_read(apic, 0);
1659 reg_01.raw = io_apic_read(apic, 1);
1660 if (reg_01.bits.version >= 0x10)
1661 reg_02.raw = io_apic_read(apic, 2);
1662 if (reg_01.bits.version >= 0x20)
1663 reg_03.raw = io_apic_read(apic, 3);
1664 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1667 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1668 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1669 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1670 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1671 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1673 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1674 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1676 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1677 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1680 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1681 * but the value of reg_02 is read as the previous read register
1682 * value, so ignore it if reg_02 == reg_01.
1684 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1685 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1686 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1690 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1691 * or reg_03, but the value of reg_0[23] is read as the previous read
1692 * register value, so ignore it if reg_03 == reg_0[12].
1694 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1695 reg_03.raw != reg_01.raw) {
1696 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1697 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1700 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1702 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1703 " Stat Dmod Deli Vect:\n");
1705 for (i = 0; i <= reg_01.bits.entries; i++) {
1706 struct IO_APIC_route_entry entry;
1708 entry = ioapic_read_entry(apic, i);
1710 printk(KERN_DEBUG " %02x %03X ",
1715 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1720 entry.delivery_status,
1722 entry.delivery_mode,
1727 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1728 for_each_irq_desc(irq, desc) {
1729 struct irq_pin_list *entry;
1731 cfg = desc->chip_data;
1734 entry = cfg->irq_2_pin;
1737 printk(KERN_DEBUG "IRQ%d ", irq);
1738 for_each_irq_pin(entry, cfg->irq_2_pin)
1739 printk("-> %d:%d", entry->apic, entry->pin);
1743 printk(KERN_INFO ".................................... done.\n");
1748 __apicdebuginit(void) print_APIC_field(int base)
1754 for (i = 0; i < 8; i++)
1755 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1757 printk(KERN_CONT "\n");
1760 __apicdebuginit(void) print_local_APIC(void *dummy)
1762 unsigned int i, v, ver, maxlvt;
1765 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1766 smp_processor_id(), hard_smp_processor_id());
1767 v = apic_read(APIC_ID);
1768 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1769 v = apic_read(APIC_LVR);
1770 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1771 ver = GET_APIC_VERSION(v);
1772 maxlvt = lapic_get_maxlvt();
1774 v = apic_read(APIC_TASKPRI);
1775 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1777 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1778 if (!APIC_XAPIC(ver)) {
1779 v = apic_read(APIC_ARBPRI);
1780 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1781 v & APIC_ARBPRI_MASK);
1783 v = apic_read(APIC_PROCPRI);
1784 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1788 * Remote read supported only in the 82489DX and local APIC for
1789 * Pentium processors.
1791 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1792 v = apic_read(APIC_RRR);
1793 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1796 v = apic_read(APIC_LDR);
1797 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1798 if (!x2apic_enabled()) {
1799 v = apic_read(APIC_DFR);
1800 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1802 v = apic_read(APIC_SPIV);
1803 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1805 printk(KERN_DEBUG "... APIC ISR field:\n");
1806 print_APIC_field(APIC_ISR);
1807 printk(KERN_DEBUG "... APIC TMR field:\n");
1808 print_APIC_field(APIC_TMR);
1809 printk(KERN_DEBUG "... APIC IRR field:\n");
1810 print_APIC_field(APIC_IRR);
1812 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1813 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1814 apic_write(APIC_ESR, 0);
1816 v = apic_read(APIC_ESR);
1817 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1820 icr = apic_icr_read();
1821 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1822 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1824 v = apic_read(APIC_LVTT);
1825 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1827 if (maxlvt > 3) { /* PC is LVT#4. */
1828 v = apic_read(APIC_LVTPC);
1829 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1831 v = apic_read(APIC_LVT0);
1832 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1833 v = apic_read(APIC_LVT1);
1834 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1836 if (maxlvt > 2) { /* ERR is LVT#3. */
1837 v = apic_read(APIC_LVTERR);
1838 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1841 v = apic_read(APIC_TMICT);
1842 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1843 v = apic_read(APIC_TMCCT);
1844 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1845 v = apic_read(APIC_TDCR);
1846 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1848 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1849 v = apic_read(APIC_EFEAT);
1850 maxlvt = (v >> 16) & 0xff;
1851 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1852 v = apic_read(APIC_ECTRL);
1853 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1854 for (i = 0; i < maxlvt; i++) {
1855 v = apic_read(APIC_EILVTn(i));
1856 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1862 __apicdebuginit(void) print_local_APICs(int maxcpu)
1870 for_each_online_cpu(cpu) {
1873 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1878 __apicdebuginit(void) print_PIC(void)
1881 unsigned long flags;
1883 if (!legacy_pic->nr_legacy_irqs)
1886 printk(KERN_DEBUG "\nprinting PIC contents\n");
1888 raw_spin_lock_irqsave(&i8259A_lock, flags);
1890 v = inb(0xa1) << 8 | inb(0x21);
1891 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1893 v = inb(0xa0) << 8 | inb(0x20);
1894 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1898 v = inb(0xa0) << 8 | inb(0x20);
1902 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1904 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1906 v = inb(0x4d1) << 8 | inb(0x4d0);
1907 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1910 static int __initdata show_lapic = 1;
1911 static __init int setup_show_lapic(char *arg)
1915 if (strcmp(arg, "all") == 0) {
1916 show_lapic = CONFIG_NR_CPUS;
1918 get_option(&arg, &num);
1925 __setup("show_lapic=", setup_show_lapic);
1927 __apicdebuginit(int) print_ICs(void)
1929 if (apic_verbosity == APIC_QUIET)
1934 /* don't print out if apic is not there */
1935 if (!cpu_has_apic && !apic_from_smp_config())
1938 print_local_APICs(show_lapic);
1944 fs_initcall(print_ICs);
1947 /* Where if anywhere is the i8259 connect in external int mode */
1948 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1950 void __init enable_IO_APIC(void)
1952 int i8259_apic, i8259_pin;
1955 if (!legacy_pic->nr_legacy_irqs)
1958 for(apic = 0; apic < nr_ioapics; apic++) {
1960 /* See if any of the pins is in ExtINT mode */
1961 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1962 struct IO_APIC_route_entry entry;
1963 entry = ioapic_read_entry(apic, pin);
1965 /* If the interrupt line is enabled and in ExtInt mode
1966 * I have found the pin where the i8259 is connected.
1968 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1969 ioapic_i8259.apic = apic;
1970 ioapic_i8259.pin = pin;
1976 /* Look to see what if the MP table has reported the ExtINT */
1977 /* If we could not find the appropriate pin by looking at the ioapic
1978 * the i8259 probably is not connected the ioapic but give the
1979 * mptable a chance anyway.
1981 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1982 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1983 /* Trust the MP table if nothing is setup in the hardware */
1984 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1985 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1986 ioapic_i8259.pin = i8259_pin;
1987 ioapic_i8259.apic = i8259_apic;
1989 /* Complain if the MP table and the hardware disagree */
1990 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1991 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1993 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1997 * Do not trust the IO-APIC being empty at bootup
2003 * Not an __init, needed by the reboot code
2005 void disable_IO_APIC(void)
2008 * Clear the IO-APIC before rebooting:
2012 if (!legacy_pic->nr_legacy_irqs)
2016 * If the i8259 is routed through an IOAPIC
2017 * Put that IOAPIC in virtual wire mode
2018 * so legacy interrupts can be delivered.
2020 * With interrupt-remapping, for now we will use virtual wire A mode,
2021 * as virtual wire B is little complex (need to configure both
2022 * IOAPIC RTE aswell as interrupt-remapping table entry).
2023 * As this gets called during crash dump, keep this simple for now.
2025 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2026 struct IO_APIC_route_entry entry;
2028 memset(&entry, 0, sizeof(entry));
2029 entry.mask = 0; /* Enabled */
2030 entry.trigger = 0; /* Edge */
2032 entry.polarity = 0; /* High */
2033 entry.delivery_status = 0;
2034 entry.dest_mode = 0; /* Physical */
2035 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2037 entry.dest = read_apic_id();
2040 * Add it to the IO-APIC irq-routing table:
2042 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2046 * Use virtual wire A mode when interrupt remapping is enabled.
2048 if (cpu_has_apic || apic_from_smp_config())
2049 disconnect_bsp_APIC(!intr_remapping_enabled &&
2050 ioapic_i8259.pin != -1);
2053 #ifdef CONFIG_X86_32
2055 * function to set the IO-APIC physical IDs based on the
2056 * values stored in the MPC table.
2058 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2061 void __init setup_ioapic_ids_from_mpc(void)
2063 union IO_APIC_reg_00 reg_00;
2064 physid_mask_t phys_id_present_map;
2067 unsigned char old_id;
2068 unsigned long flags;
2073 * Don't check I/O APIC IDs for xAPIC systems. They have
2074 * no meaning without the serial APIC bus.
2076 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2077 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2080 * This is broken; anything with a real cpu count has to
2081 * circumvent this idiocy regardless.
2083 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2086 * Set the IOAPIC ID to the value stored in the MPC table.
2088 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2090 /* Read the register 0 value */
2091 raw_spin_lock_irqsave(&ioapic_lock, flags);
2092 reg_00.raw = io_apic_read(apic_id, 0);
2093 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2095 old_id = mp_ioapics[apic_id].apicid;
2097 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2098 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2099 apic_id, mp_ioapics[apic_id].apicid);
2100 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2102 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2106 * Sanity check, is the ID really free? Every APIC in a
2107 * system must have a unique ID or we get lots of nice
2108 * 'stuck on smp_invalidate_needed IPI wait' messages.
2110 if (apic->check_apicid_used(&phys_id_present_map,
2111 mp_ioapics[apic_id].apicid)) {
2112 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2113 apic_id, mp_ioapics[apic_id].apicid);
2114 for (i = 0; i < get_physical_broadcast(); i++)
2115 if (!physid_isset(i, phys_id_present_map))
2117 if (i >= get_physical_broadcast())
2118 panic("Max APIC ID exceeded!\n");
2119 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2121 physid_set(i, phys_id_present_map);
2122 mp_ioapics[apic_id].apicid = i;
2125 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2126 apic_printk(APIC_VERBOSE, "Setting %d in the "
2127 "phys_id_present_map\n",
2128 mp_ioapics[apic_id].apicid);
2129 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2134 * We need to adjust the IRQ routing table
2135 * if the ID changed.
2137 if (old_id != mp_ioapics[apic_id].apicid)
2138 for (i = 0; i < mp_irq_entries; i++)
2139 if (mp_irqs[i].dstapic == old_id)
2141 = mp_ioapics[apic_id].apicid;
2144 * Read the right value from the MPC table and
2145 * write it into the ID register.
2147 apic_printk(APIC_VERBOSE, KERN_INFO
2148 "...changing IO-APIC physical APIC ID to %d ...",
2149 mp_ioapics[apic_id].apicid);
2151 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2152 raw_spin_lock_irqsave(&ioapic_lock, flags);
2153 io_apic_write(apic_id, 0, reg_00.raw);
2154 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2159 raw_spin_lock_irqsave(&ioapic_lock, flags);
2160 reg_00.raw = io_apic_read(apic_id, 0);
2161 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2162 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2163 printk("could not set ID!\n");
2165 apic_printk(APIC_VERBOSE, " ok.\n");
2170 int no_timer_check __initdata;
2172 static int __init notimercheck(char *s)
2177 __setup("no_timer_check", notimercheck);
2180 * There is a nasty bug in some older SMP boards, their mptable lies
2181 * about the timer IRQ. We do the following to work around the situation:
2183 * - timer IRQ defaults to IO-APIC IRQ
2184 * - if this function detects that timer IRQs are defunct, then we fall
2185 * back to ISA timer IRQs
2187 static int __init timer_irq_works(void)
2189 unsigned long t1 = jiffies;
2190 unsigned long flags;
2195 local_save_flags(flags);
2197 /* Let ten ticks pass... */
2198 mdelay((10 * 1000) / HZ);
2199 local_irq_restore(flags);
2202 * Expect a few ticks at least, to be sure some possible
2203 * glue logic does not lock up after one or two first
2204 * ticks in a non-ExtINT mode. Also the local APIC
2205 * might have cached one ExtINT interrupt. Finally, at
2206 * least one tick may be lost due to delays.
2210 if (time_after(jiffies, t1 + 4))
2216 * In the SMP+IOAPIC case it might happen that there are an unspecified
2217 * number of pending IRQ events unhandled. These cases are very rare,
2218 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2219 * better to do it this way as thus we do not have to be aware of
2220 * 'pending' interrupts in the IRQ path, except at this point.
2223 * Edge triggered needs to resend any interrupt
2224 * that was delayed but this is now handled in the device
2229 * Starting up a edge-triggered IO-APIC interrupt is
2230 * nasty - we need to make sure that we get the edge.
2231 * If it is already asserted for some reason, we need
2232 * return 1 to indicate that is was pending.
2234 * This is not complete - we should be able to fake
2235 * an edge even if it isn't on the 8259A...
2238 static unsigned int startup_ioapic_irq(unsigned int irq)
2240 int was_pending = 0;
2241 unsigned long flags;
2242 struct irq_cfg *cfg;
2244 raw_spin_lock_irqsave(&ioapic_lock, flags);
2245 if (irq < legacy_pic->nr_legacy_irqs) {
2246 legacy_pic->chip->mask(irq);
2247 if (legacy_pic->irq_pending(irq))
2251 __unmask_IO_APIC_irq(cfg);
2252 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2257 static int ioapic_retrigger_irq(unsigned int irq)
2260 struct irq_cfg *cfg = irq_cfg(irq);
2261 unsigned long flags;
2263 raw_spin_lock_irqsave(&vector_lock, flags);
2264 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2265 raw_spin_unlock_irqrestore(&vector_lock, flags);
2271 * Level and edge triggered IO-APIC interrupts need different handling,
2272 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2273 * handled with the level-triggered descriptor, but that one has slightly
2274 * more overhead. Level-triggered interrupts cannot be handled with the
2275 * edge-triggered handler, without risking IRQ storms and other ugly
2280 void send_cleanup_vector(struct irq_cfg *cfg)
2282 cpumask_var_t cleanup_mask;
2284 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2286 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2287 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2289 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2290 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2291 free_cpumask_var(cleanup_mask);
2293 cfg->move_in_progress = 0;
2296 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2299 struct irq_pin_list *entry;
2300 u8 vector = cfg->vector;
2302 for_each_irq_pin(entry, cfg->irq_2_pin) {
2308 * With interrupt-remapping, destination information comes
2309 * from interrupt-remapping table entry.
2311 if (!irq_remapped(irq))
2312 io_apic_write(apic, 0x11 + pin*2, dest);
2313 reg = io_apic_read(apic, 0x10 + pin*2);
2314 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2316 io_apic_modify(apic, 0x10 + pin*2, reg);
2321 * Either sets desc->affinity to a valid value, and returns
2322 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2323 * leaves desc->affinity untouched.
2326 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2327 unsigned int *dest_id)
2329 struct irq_cfg *cfg;
2332 if (!cpumask_intersects(mask, cpu_online_mask))
2336 cfg = desc->chip_data;
2337 if (assign_irq_vector(irq, cfg, mask))
2340 cpumask_copy(desc->affinity, mask);
2342 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2347 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2349 struct irq_cfg *cfg;
2350 unsigned long flags;
2356 cfg = desc->chip_data;
2358 raw_spin_lock_irqsave(&ioapic_lock, flags);
2359 ret = set_desc_affinity(desc, mask, &dest);
2361 /* Only the high 8 bits are valid. */
2362 dest = SET_APIC_LOGICAL_ID(dest);
2363 __target_IO_APIC_irq(irq, dest, cfg);
2365 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2371 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2373 struct irq_desc *desc;
2375 desc = irq_to_desc(irq);
2377 return set_ioapic_affinity_irq_desc(desc, mask);
2380 #ifdef CONFIG_INTR_REMAP
2383 * Migrate the IO-APIC irq in the presence of intr-remapping.
2385 * For both level and edge triggered, irq migration is a simple atomic
2386 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2388 * For level triggered, we eliminate the io-apic RTE modification (with the
2389 * updated vector information), by using a virtual vector (io-apic pin number).
2390 * Real vector that is used for interrupting cpu will be coming from
2391 * the interrupt-remapping table entry.
2394 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2396 struct irq_cfg *cfg;
2402 if (!cpumask_intersects(mask, cpu_online_mask))
2406 if (get_irte(irq, &irte))
2409 cfg = desc->chip_data;
2410 if (assign_irq_vector(irq, cfg, mask))
2413 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2415 irte.vector = cfg->vector;
2416 irte.dest_id = IRTE_DEST(dest);
2419 * Modified the IRTE and flushes the Interrupt entry cache.
2421 modify_irte(irq, &irte);
2423 if (cfg->move_in_progress)
2424 send_cleanup_vector(cfg);
2426 cpumask_copy(desc->affinity, mask);
2432 * Migrates the IRQ destination in the process context.
2434 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2435 const struct cpumask *mask)
2437 return migrate_ioapic_irq_desc(desc, mask);
2439 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2440 const struct cpumask *mask)
2442 struct irq_desc *desc = irq_to_desc(irq);
2444 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2447 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2448 const struct cpumask *mask)
2454 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2456 unsigned vector, me;
2462 me = smp_processor_id();
2463 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2466 struct irq_desc *desc;
2467 struct irq_cfg *cfg;
2468 irq = __get_cpu_var(vector_irq)[vector];
2473 desc = irq_to_desc(irq);
2478 raw_spin_lock(&desc->lock);
2481 * Check if the irq migration is in progress. If so, we
2482 * haven't received the cleanup request yet for this irq.
2484 if (cfg->move_in_progress)
2487 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2490 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2492 * Check if the vector that needs to be cleanedup is
2493 * registered at the cpu's IRR. If so, then this is not
2494 * the best time to clean it up. Lets clean it up in the
2495 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2498 if (irr & (1 << (vector % 32))) {
2499 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2502 __get_cpu_var(vector_irq)[vector] = -1;
2504 raw_spin_unlock(&desc->lock);
2510 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2512 struct irq_desc *desc = *descp;
2513 struct irq_cfg *cfg = desc->chip_data;
2516 if (likely(!cfg->move_in_progress))
2519 me = smp_processor_id();
2521 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2522 send_cleanup_vector(cfg);
2525 static void irq_complete_move(struct irq_desc **descp)
2527 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2530 void irq_force_complete_move(int irq)
2532 struct irq_desc *desc = irq_to_desc(irq);
2533 struct irq_cfg *cfg = desc->chip_data;
2538 __irq_complete_move(&desc, cfg->vector);
2541 static inline void irq_complete_move(struct irq_desc **descp) {}
2544 static void ack_apic_edge(unsigned int irq)
2546 struct irq_desc *desc = irq_to_desc(irq);
2548 irq_complete_move(&desc);
2549 move_native_irq(irq);
2553 atomic_t irq_mis_count;
2556 * IO-APIC versions below 0x20 don't support EOI register.
2557 * For the record, here is the information about various versions:
2559 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2560 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2563 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2564 * version as 0x2. This is an error with documentation and these ICH chips
2565 * use io-apic's of version 0x20.
2567 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2568 * Otherwise, we simulate the EOI message manually by changing the trigger
2569 * mode to edge and then back to level, with RTE being masked during this.
2571 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2573 struct irq_pin_list *entry;
2575 for_each_irq_pin(entry, cfg->irq_2_pin) {
2576 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2578 * Intr-remapping uses pin number as the virtual vector
2579 * in the RTE. Actual vector is programmed in
2580 * intr-remapping table entry. Hence for the io-apic
2581 * EOI we use the pin number.
2583 if (irq_remapped(irq))
2584 io_apic_eoi(entry->apic, entry->pin);
2586 io_apic_eoi(entry->apic, cfg->vector);
2588 __mask_and_edge_IO_APIC_irq(entry);
2589 __unmask_and_level_IO_APIC_irq(entry);
2594 static void eoi_ioapic_irq(struct irq_desc *desc)
2596 struct irq_cfg *cfg;
2597 unsigned long flags;
2601 cfg = desc->chip_data;
2603 raw_spin_lock_irqsave(&ioapic_lock, flags);
2604 __eoi_ioapic_irq(irq, cfg);
2605 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2608 static void ack_apic_level(unsigned int irq)
2610 struct irq_desc *desc = irq_to_desc(irq);
2613 struct irq_cfg *cfg;
2614 int do_unmask_irq = 0;
2616 irq_complete_move(&desc);
2617 #ifdef CONFIG_GENERIC_PENDING_IRQ
2618 /* If we are moving the irq we need to mask it */
2619 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2621 mask_IO_APIC_irq_desc(desc);
2626 * It appears there is an erratum which affects at least version 0x11
2627 * of I/O APIC (that's the 82093AA and cores integrated into various
2628 * chipsets). Under certain conditions a level-triggered interrupt is
2629 * erroneously delivered as edge-triggered one but the respective IRR
2630 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2631 * message but it will never arrive and further interrupts are blocked
2632 * from the source. The exact reason is so far unknown, but the
2633 * phenomenon was observed when two consecutive interrupt requests
2634 * from a given source get delivered to the same CPU and the source is
2635 * temporarily disabled in between.
2637 * A workaround is to simulate an EOI message manually. We achieve it
2638 * by setting the trigger mode to edge and then to level when the edge
2639 * trigger mode gets detected in the TMR of a local APIC for a
2640 * level-triggered interrupt. We mask the source for the time of the
2641 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2642 * The idea is from Manfred Spraul. --macro
2644 * Also in the case when cpu goes offline, fixup_irqs() will forward
2645 * any unhandled interrupt on the offlined cpu to the new cpu
2646 * destination that is handling the corresponding interrupt. This
2647 * interrupt forwarding is done via IPI's. Hence, in this case also
2648 * level-triggered io-apic interrupt will be seen as an edge
2649 * interrupt in the IRR. And we can't rely on the cpu's EOI
2650 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2651 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2652 * supporting EOI register, we do an explicit EOI to clear the
2653 * remote IRR and on IO-APIC's which don't have an EOI register,
2654 * we use the above logic (mask+edge followed by unmask+level) from
2655 * Manfred Spraul to clear the remote IRR.
2657 cfg = desc->chip_data;
2659 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2662 * We must acknowledge the irq before we move it or the acknowledge will
2663 * not propagate properly.
2668 * Tail end of clearing remote IRR bit (either by delivering the EOI
2669 * message via io-apic EOI register write or simulating it using
2670 * mask+edge followed by unnask+level logic) manually when the
2671 * level triggered interrupt is seen as the edge triggered interrupt
2674 if (!(v & (1 << (i & 0x1f)))) {
2675 atomic_inc(&irq_mis_count);
2677 eoi_ioapic_irq(desc);
2680 /* Now we can move and renable the irq */
2681 if (unlikely(do_unmask_irq)) {
2682 /* Only migrate the irq if the ack has been received.
2684 * On rare occasions the broadcast level triggered ack gets
2685 * delayed going to ioapics, and if we reprogram the
2686 * vector while Remote IRR is still set the irq will never
2689 * To prevent this scenario we read the Remote IRR bit
2690 * of the ioapic. This has two effects.
2691 * - On any sane system the read of the ioapic will
2692 * flush writes (and acks) going to the ioapic from
2694 * - We get to see if the ACK has actually been delivered.
2696 * Based on failed experiments of reprogramming the
2697 * ioapic entry from outside of irq context starting
2698 * with masking the ioapic entry and then polling until
2699 * Remote IRR was clear before reprogramming the
2700 * ioapic I don't trust the Remote IRR bit to be
2701 * completey accurate.
2703 * However there appears to be no other way to plug
2704 * this race, so if the Remote IRR bit is not
2705 * accurate and is causing problems then it is a hardware bug
2706 * and you can go talk to the chipset vendor about it.
2708 cfg = desc->chip_data;
2709 if (!io_apic_level_ack_pending(cfg))
2710 move_masked_irq(irq);
2711 unmask_IO_APIC_irq_desc(desc);
2715 #ifdef CONFIG_INTR_REMAP
2716 static void ir_ack_apic_edge(unsigned int irq)
2721 static void ir_ack_apic_level(unsigned int irq)
2723 struct irq_desc *desc = irq_to_desc(irq);
2726 eoi_ioapic_irq(desc);
2728 #endif /* CONFIG_INTR_REMAP */
2730 static struct irq_chip ioapic_chip __read_mostly = {
2732 .startup = startup_ioapic_irq,
2733 .mask = mask_IO_APIC_irq,
2734 .unmask = unmask_IO_APIC_irq,
2735 .ack = ack_apic_edge,
2736 .eoi = ack_apic_level,
2738 .set_affinity = set_ioapic_affinity_irq,
2740 .retrigger = ioapic_retrigger_irq,
2743 static struct irq_chip ir_ioapic_chip __read_mostly = {
2744 .name = "IR-IO-APIC",
2745 .startup = startup_ioapic_irq,
2746 .mask = mask_IO_APIC_irq,
2747 .unmask = unmask_IO_APIC_irq,
2748 #ifdef CONFIG_INTR_REMAP
2749 .ack = ir_ack_apic_edge,
2750 .eoi = ir_ack_apic_level,
2752 .set_affinity = set_ir_ioapic_affinity_irq,
2755 .retrigger = ioapic_retrigger_irq,
2758 static inline void init_IO_APIC_traps(void)
2761 struct irq_desc *desc;
2762 struct irq_cfg *cfg;
2765 * NOTE! The local APIC isn't very good at handling
2766 * multiple interrupts at the same interrupt level.
2767 * As the interrupt level is determined by taking the
2768 * vector number and shifting that right by 4, we
2769 * want to spread these out a bit so that they don't
2770 * all fall in the same interrupt level.
2772 * Also, we've got to be careful not to trash gate
2773 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2775 for_each_irq_desc(irq, desc) {
2776 cfg = desc->chip_data;
2777 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2779 * Hmm.. We don't have an entry for this,
2780 * so default to an old-fashioned 8259
2781 * interrupt if we can..
2783 if (irq < legacy_pic->nr_legacy_irqs)
2784 legacy_pic->make_irq(irq);
2786 /* Strange. Oh, well.. */
2787 desc->chip = &no_irq_chip;
2793 * The local APIC irq-chip implementation:
2796 static void mask_lapic_irq(unsigned int irq)
2800 v = apic_read(APIC_LVT0);
2801 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2804 static void unmask_lapic_irq(unsigned int irq)
2808 v = apic_read(APIC_LVT0);
2809 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2812 static void ack_lapic_irq(unsigned int irq)
2817 static struct irq_chip lapic_chip __read_mostly = {
2818 .name = "local-APIC",
2819 .mask = mask_lapic_irq,
2820 .unmask = unmask_lapic_irq,
2821 .ack = ack_lapic_irq,
2824 static void lapic_register_intr(int irq, struct irq_desc *desc)
2826 desc->status &= ~IRQ_LEVEL;
2827 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2831 static void __init setup_nmi(void)
2834 * Dirty trick to enable the NMI watchdog ...
2835 * We put the 8259A master into AEOI mode and
2836 * unmask on all local APICs LVT0 as NMI.
2838 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2839 * is from Maciej W. Rozycki - so we do not have to EOI from
2840 * the NMI handler or the timer interrupt.
2842 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2844 enable_NMI_through_LVT0();
2846 apic_printk(APIC_VERBOSE, " done.\n");
2850 * This looks a bit hackish but it's about the only one way of sending
2851 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2852 * not support the ExtINT mode, unfortunately. We need to send these
2853 * cycles as some i82489DX-based boards have glue logic that keeps the
2854 * 8259A interrupt line asserted until INTA. --macro
2856 static inline void __init unlock_ExtINT_logic(void)
2859 struct IO_APIC_route_entry entry0, entry1;
2860 unsigned char save_control, save_freq_select;
2862 pin = find_isa_irq_pin(8, mp_INT);
2867 apic = find_isa_irq_apic(8, mp_INT);
2873 entry0 = ioapic_read_entry(apic, pin);
2874 clear_IO_APIC_pin(apic, pin);
2876 memset(&entry1, 0, sizeof(entry1));
2878 entry1.dest_mode = 0; /* physical delivery */
2879 entry1.mask = 0; /* unmask IRQ now */
2880 entry1.dest = hard_smp_processor_id();
2881 entry1.delivery_mode = dest_ExtINT;
2882 entry1.polarity = entry0.polarity;
2886 ioapic_write_entry(apic, pin, entry1);
2888 save_control = CMOS_READ(RTC_CONTROL);
2889 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2890 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2892 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2897 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2901 CMOS_WRITE(save_control, RTC_CONTROL);
2902 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2903 clear_IO_APIC_pin(apic, pin);
2905 ioapic_write_entry(apic, pin, entry0);
2908 static int disable_timer_pin_1 __initdata;
2909 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2910 static int __init disable_timer_pin_setup(char *arg)
2912 disable_timer_pin_1 = 1;
2915 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2917 int timer_through_8259 __initdata;
2920 * This code may look a bit paranoid, but it's supposed to cooperate with
2921 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2922 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2923 * fanatically on his truly buggy board.
2925 * FIXME: really need to revamp this for all platforms.
2927 static inline void __init check_timer(void)
2929 struct irq_desc *desc = irq_to_desc(0);
2930 struct irq_cfg *cfg = desc->chip_data;
2931 int node = cpu_to_node(boot_cpu_id);
2932 int apic1, pin1, apic2, pin2;
2933 unsigned long flags;
2936 local_irq_save(flags);
2939 * get/set the timer IRQ vector:
2941 legacy_pic->chip->mask(0);
2942 assign_irq_vector(0, cfg, apic->target_cpus());
2945 * As IRQ0 is to be enabled in the 8259A, the virtual
2946 * wire has to be disabled in the local APIC. Also
2947 * timer interrupts need to be acknowledged manually in
2948 * the 8259A for the i82489DX when using the NMI
2949 * watchdog as that APIC treats NMIs as level-triggered.
2950 * The AEOI mode will finish them in the 8259A
2953 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2954 legacy_pic->init(1);
2955 #ifdef CONFIG_X86_32
2959 ver = apic_read(APIC_LVR);
2960 ver = GET_APIC_VERSION(ver);
2961 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2965 pin1 = find_isa_irq_pin(0, mp_INT);
2966 apic1 = find_isa_irq_apic(0, mp_INT);
2967 pin2 = ioapic_i8259.pin;
2968 apic2 = ioapic_i8259.apic;
2970 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2971 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2972 cfg->vector, apic1, pin1, apic2, pin2);
2975 * Some BIOS writers are clueless and report the ExtINTA
2976 * I/O APIC input from the cascaded 8259A as the timer
2977 * interrupt input. So just in case, if only one pin
2978 * was found above, try it both directly and through the
2982 if (intr_remapping_enabled)
2983 panic("BIOS bug: timer not connected to IO-APIC");
2987 } else if (pin2 == -1) {
2994 * Ok, does IRQ0 through the IOAPIC work?
2997 add_pin_to_irq_node(cfg, node, apic1, pin1);
2998 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
3000 /* for edge trigger, setup_IO_APIC_irq already
3001 * leave it unmasked.
3002 * so only need to unmask if it is level-trigger
3003 * do we really have level trigger timer?
3006 idx = find_irq_entry(apic1, pin1, mp_INT);
3007 if (idx != -1 && irq_trigger(idx))
3008 unmask_IO_APIC_irq_desc(desc);
3010 if (timer_irq_works()) {
3011 if (nmi_watchdog == NMI_IO_APIC) {
3013 legacy_pic->chip->unmask(0);
3015 if (disable_timer_pin_1 > 0)
3016 clear_IO_APIC_pin(0, pin1);
3019 if (intr_remapping_enabled)
3020 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3021 local_irq_disable();
3022 clear_IO_APIC_pin(apic1, pin1);
3024 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
3025 "8254 timer not connected to IO-APIC\n");
3027 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3028 "(IRQ0) through the 8259A ...\n");
3029 apic_printk(APIC_QUIET, KERN_INFO
3030 "..... (found apic %d pin %d) ...\n", apic2, pin2);
3032 * legacy devices should be connected to IO APIC #0
3034 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
3035 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3036 legacy_pic->chip->unmask(0);
3037 if (timer_irq_works()) {
3038 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3039 timer_through_8259 = 1;
3040 if (nmi_watchdog == NMI_IO_APIC) {
3041 legacy_pic->chip->mask(0);
3043 legacy_pic->chip->unmask(0);
3048 * Cleanup, just in case ...
3050 local_irq_disable();
3051 legacy_pic->chip->mask(0);
3052 clear_IO_APIC_pin(apic2, pin2);
3053 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3056 if (nmi_watchdog == NMI_IO_APIC) {
3057 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3058 "through the IO-APIC - disabling NMI Watchdog!\n");
3059 nmi_watchdog = NMI_NONE;
3061 #ifdef CONFIG_X86_32
3065 apic_printk(APIC_QUIET, KERN_INFO
3066 "...trying to set up timer as Virtual Wire IRQ...\n");
3068 lapic_register_intr(0, desc);
3069 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3070 legacy_pic->chip->unmask(0);
3072 if (timer_irq_works()) {
3073 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3076 local_irq_disable();
3077 legacy_pic->chip->mask(0);
3078 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3079 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3081 apic_printk(APIC_QUIET, KERN_INFO
3082 "...trying to set up timer as ExtINT IRQ...\n");
3084 legacy_pic->init(0);
3085 legacy_pic->make_irq(0);
3086 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3088 unlock_ExtINT_logic();
3090 if (timer_irq_works()) {
3091 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3094 local_irq_disable();
3095 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3096 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3097 "report. Then try booting with the 'noapic' option.\n");
3099 local_irq_restore(flags);
3103 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3104 * to devices. However there may be an I/O APIC pin available for
3105 * this interrupt regardless. The pin may be left unconnected, but
3106 * typically it will be reused as an ExtINT cascade interrupt for
3107 * the master 8259A. In the MPS case such a pin will normally be
3108 * reported as an ExtINT interrupt in the MP table. With ACPI
3109 * there is no provision for ExtINT interrupts, and in the absence
3110 * of an override it would be treated as an ordinary ISA I/O APIC
3111 * interrupt, that is edge-triggered and unmasked by default. We
3112 * used to do this, but it caused problems on some systems because
3113 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3114 * the same ExtINT cascade interrupt to drive the local APIC of the
3115 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3116 * the I/O APIC in all cases now. No actual device should request
3117 * it anyway. --macro
3119 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3121 void __init setup_IO_APIC(void)
3125 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3127 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3129 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3131 * Set up IO-APIC IRQ routing.
3133 x86_init.mpparse.setup_ioapic_ids();
3136 setup_IO_APIC_irqs();
3137 init_IO_APIC_traps();
3138 if (legacy_pic->nr_legacy_irqs)
3143 * Called after all the initialization is done. If we didnt find any
3144 * APIC bugs then we can allow the modify fast path
3147 static int __init io_apic_bug_finalize(void)
3149 if (sis_apic_bug == -1)
3154 late_initcall(io_apic_bug_finalize);
3156 struct sysfs_ioapic_data {
3157 struct sys_device dev;
3158 struct IO_APIC_route_entry entry[0];
3160 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3162 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3164 struct IO_APIC_route_entry *entry;
3165 struct sysfs_ioapic_data *data;
3168 data = container_of(dev, struct sysfs_ioapic_data, dev);
3169 entry = data->entry;
3170 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3171 *entry = ioapic_read_entry(dev->id, i);
3176 static int ioapic_resume(struct sys_device *dev)
3178 struct IO_APIC_route_entry *entry;
3179 struct sysfs_ioapic_data *data;
3180 unsigned long flags;
3181 union IO_APIC_reg_00 reg_00;
3184 data = container_of(dev, struct sysfs_ioapic_data, dev);
3185 entry = data->entry;
3187 raw_spin_lock_irqsave(&ioapic_lock, flags);
3188 reg_00.raw = io_apic_read(dev->id, 0);
3189 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3190 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3191 io_apic_write(dev->id, 0, reg_00.raw);
3193 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3194 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3195 ioapic_write_entry(dev->id, i, entry[i]);
3200 static struct sysdev_class ioapic_sysdev_class = {
3202 .suspend = ioapic_suspend,
3203 .resume = ioapic_resume,
3206 static int __init ioapic_init_sysfs(void)
3208 struct sys_device * dev;
3211 error = sysdev_class_register(&ioapic_sysdev_class);
3215 for (i = 0; i < nr_ioapics; i++ ) {
3216 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3217 * sizeof(struct IO_APIC_route_entry);
3218 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3219 if (!mp_ioapic_data[i]) {
3220 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3223 dev = &mp_ioapic_data[i]->dev;
3225 dev->cls = &ioapic_sysdev_class;
3226 error = sysdev_register(dev);
3228 kfree(mp_ioapic_data[i]);
3229 mp_ioapic_data[i] = NULL;
3230 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3238 device_initcall(ioapic_init_sysfs);
3241 * Dynamic irq allocate and deallocation
3243 unsigned int create_irq_nr(unsigned int irq_want, int node)
3245 /* Allocate an unused irq */
3248 unsigned long flags;
3249 struct irq_cfg *cfg_new = NULL;
3250 struct irq_desc *desc_new = NULL;
3253 if (irq_want < nr_irqs_gsi)
3254 irq_want = nr_irqs_gsi;
3256 raw_spin_lock_irqsave(&vector_lock, flags);
3257 for (new = irq_want; new < nr_irqs; new++) {
3258 desc_new = irq_to_desc_alloc_node(new, node);
3260 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3263 cfg_new = desc_new->chip_data;
3265 if (cfg_new->vector != 0)
3268 desc_new = move_irq_desc(desc_new, node);
3269 cfg_new = desc_new->chip_data;
3271 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3275 raw_spin_unlock_irqrestore(&vector_lock, flags);
3278 dynamic_irq_init_keep_chip_data(irq);
3283 int create_irq(void)
3285 int node = cpu_to_node(boot_cpu_id);
3286 unsigned int irq_want;
3289 irq_want = nr_irqs_gsi;
3290 irq = create_irq_nr(irq_want, node);
3298 void destroy_irq(unsigned int irq)
3300 unsigned long flags;
3302 dynamic_irq_cleanup_keep_chip_data(irq);
3305 raw_spin_lock_irqsave(&vector_lock, flags);
3306 __clear_irq_vector(irq, get_irq_chip_data(irq));
3307 raw_spin_unlock_irqrestore(&vector_lock, flags);
3311 * MSI message composition
3313 #ifdef CONFIG_PCI_MSI
3314 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3315 struct msi_msg *msg, u8 hpet_id)
3317 struct irq_cfg *cfg;
3325 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3329 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3331 if (irq_remapped(irq)) {
3336 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3337 BUG_ON(ir_index == -1);
3339 memset (&irte, 0, sizeof(irte));
3342 irte.dst_mode = apic->irq_dest_mode;
3343 irte.trigger_mode = 0; /* edge */
3344 irte.dlvry_mode = apic->irq_delivery_mode;
3345 irte.vector = cfg->vector;
3346 irte.dest_id = IRTE_DEST(dest);
3347 irte.redir_hint = 1;
3349 /* Set source-id of interrupt request */
3351 set_msi_sid(&irte, pdev);
3353 set_hpet_sid(&irte, hpet_id);
3355 modify_irte(irq, &irte);
3357 msg->address_hi = MSI_ADDR_BASE_HI;
3358 msg->data = sub_handle;
3359 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3361 MSI_ADDR_IR_INDEX1(ir_index) |
3362 MSI_ADDR_IR_INDEX2(ir_index);
3364 if (x2apic_enabled())
3365 msg->address_hi = MSI_ADDR_BASE_HI |
3366 MSI_ADDR_EXT_DEST_ID(dest);
3368 msg->address_hi = MSI_ADDR_BASE_HI;
3372 ((apic->irq_dest_mode == 0) ?
3373 MSI_ADDR_DEST_MODE_PHYSICAL:
3374 MSI_ADDR_DEST_MODE_LOGICAL) |
3375 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3376 MSI_ADDR_REDIRECTION_CPU:
3377 MSI_ADDR_REDIRECTION_LOWPRI) |
3378 MSI_ADDR_DEST_ID(dest);
3381 MSI_DATA_TRIGGER_EDGE |
3382 MSI_DATA_LEVEL_ASSERT |
3383 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3384 MSI_DATA_DELIVERY_FIXED:
3385 MSI_DATA_DELIVERY_LOWPRI) |
3386 MSI_DATA_VECTOR(cfg->vector);
3392 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3394 struct irq_desc *desc = irq_to_desc(irq);
3395 struct irq_cfg *cfg;
3399 if (set_desc_affinity(desc, mask, &dest))
3402 cfg = desc->chip_data;
3404 get_cached_msi_msg_desc(desc, &msg);
3406 msg.data &= ~MSI_DATA_VECTOR_MASK;
3407 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3408 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3409 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3411 write_msi_msg_desc(desc, &msg);
3415 #ifdef CONFIG_INTR_REMAP
3417 * Migrate the MSI irq to another cpumask. This migration is
3418 * done in the process context using interrupt-remapping hardware.
3421 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3423 struct irq_desc *desc = irq_to_desc(irq);
3424 struct irq_cfg *cfg = desc->chip_data;
3428 if (get_irte(irq, &irte))
3431 if (set_desc_affinity(desc, mask, &dest))
3434 irte.vector = cfg->vector;
3435 irte.dest_id = IRTE_DEST(dest);
3438 * atomically update the IRTE with the new destination and vector.
3440 modify_irte(irq, &irte);
3443 * After this point, all the interrupts will start arriving
3444 * at the new destination. So, time to cleanup the previous
3445 * vector allocation.
3447 if (cfg->move_in_progress)
3448 send_cleanup_vector(cfg);
3454 #endif /* CONFIG_SMP */
3457 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3458 * which implement the MSI or MSI-X Capability Structure.
3460 static struct irq_chip msi_chip = {
3462 .unmask = unmask_msi_irq,
3463 .mask = mask_msi_irq,
3464 .ack = ack_apic_edge,
3466 .set_affinity = set_msi_irq_affinity,
3468 .retrigger = ioapic_retrigger_irq,
3471 static struct irq_chip msi_ir_chip = {
3472 .name = "IR-PCI-MSI",
3473 .unmask = unmask_msi_irq,
3474 .mask = mask_msi_irq,
3475 #ifdef CONFIG_INTR_REMAP
3476 .ack = ir_ack_apic_edge,
3478 .set_affinity = ir_set_msi_irq_affinity,
3481 .retrigger = ioapic_retrigger_irq,
3485 * Map the PCI dev to the corresponding remapping hardware unit
3486 * and allocate 'nvec' consecutive interrupt-remapping table entries
3489 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3491 struct intel_iommu *iommu;
3494 iommu = map_dev_to_ir(dev);
3497 "Unable to map PCI %s to iommu\n", pci_name(dev));
3501 index = alloc_irte(iommu, irq, nvec);
3504 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3511 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3516 ret = msi_compose_msg(dev, irq, &msg, -1);
3520 set_irq_msi(irq, msidesc);
3521 write_msi_msg(irq, &msg);
3523 if (irq_remapped(irq)) {
3524 struct irq_desc *desc = irq_to_desc(irq);
3526 * irq migration in process context
3528 desc->status |= IRQ_MOVE_PCNTXT;
3529 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3531 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3533 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3538 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3541 int ret, sub_handle;
3542 struct msi_desc *msidesc;
3543 unsigned int irq_want;
3544 struct intel_iommu *iommu = NULL;
3548 /* x86 doesn't support multiple MSI yet */
3549 if (type == PCI_CAP_ID_MSI && nvec > 1)
3552 node = dev_to_node(&dev->dev);
3553 irq_want = nr_irqs_gsi;
3555 list_for_each_entry(msidesc, &dev->msi_list, list) {
3556 irq = create_irq_nr(irq_want, node);
3560 if (!intr_remapping_enabled)
3565 * allocate the consecutive block of IRTE's
3568 index = msi_alloc_irte(dev, irq, nvec);
3574 iommu = map_dev_to_ir(dev);
3580 * setup the mapping between the irq and the IRTE
3581 * base index, the sub_handle pointing to the
3582 * appropriate interrupt remap table entry.
3584 set_irte_irq(irq, iommu, index, sub_handle);
3587 ret = setup_msi_irq(dev, msidesc, irq);
3599 void arch_teardown_msi_irq(unsigned int irq)
3604 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3606 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3608 struct irq_desc *desc = irq_to_desc(irq);
3609 struct irq_cfg *cfg;
3613 if (set_desc_affinity(desc, mask, &dest))
3616 cfg = desc->chip_data;
3618 dmar_msi_read(irq, &msg);
3620 msg.data &= ~MSI_DATA_VECTOR_MASK;
3621 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3622 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3623 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3625 dmar_msi_write(irq, &msg);
3630 #endif /* CONFIG_SMP */
3632 static struct irq_chip dmar_msi_type = {
3634 .unmask = dmar_msi_unmask,
3635 .mask = dmar_msi_mask,
3636 .ack = ack_apic_edge,
3638 .set_affinity = dmar_msi_set_affinity,
3640 .retrigger = ioapic_retrigger_irq,
3643 int arch_setup_dmar_msi(unsigned int irq)
3648 ret = msi_compose_msg(NULL, irq, &msg, -1);
3651 dmar_msi_write(irq, &msg);
3652 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3658 #ifdef CONFIG_HPET_TIMER
3661 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3663 struct irq_desc *desc = irq_to_desc(irq);
3664 struct irq_cfg *cfg;
3668 if (set_desc_affinity(desc, mask, &dest))
3671 cfg = desc->chip_data;
3673 hpet_msi_read(irq, &msg);
3675 msg.data &= ~MSI_DATA_VECTOR_MASK;
3676 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3677 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3678 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3680 hpet_msi_write(irq, &msg);
3685 #endif /* CONFIG_SMP */
3687 static struct irq_chip ir_hpet_msi_type = {
3688 .name = "IR-HPET_MSI",
3689 .unmask = hpet_msi_unmask,
3690 .mask = hpet_msi_mask,
3691 #ifdef CONFIG_INTR_REMAP
3692 .ack = ir_ack_apic_edge,
3694 .set_affinity = ir_set_msi_irq_affinity,
3697 .retrigger = ioapic_retrigger_irq,
3700 static struct irq_chip hpet_msi_type = {
3702 .unmask = hpet_msi_unmask,
3703 .mask = hpet_msi_mask,
3704 .ack = ack_apic_edge,
3706 .set_affinity = hpet_msi_set_affinity,
3708 .retrigger = ioapic_retrigger_irq,
3711 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3715 struct irq_desc *desc = irq_to_desc(irq);
3717 if (intr_remapping_enabled) {
3718 struct intel_iommu *iommu = map_hpet_to_ir(id);
3724 index = alloc_irte(iommu, irq, 1);
3729 ret = msi_compose_msg(NULL, irq, &msg, id);
3733 hpet_msi_write(irq, &msg);
3734 desc->status |= IRQ_MOVE_PCNTXT;
3735 if (irq_remapped(irq))
3736 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3737 handle_edge_irq, "edge");
3739 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3740 handle_edge_irq, "edge");
3746 #endif /* CONFIG_PCI_MSI */
3748 * Hypertransport interrupt support
3750 #ifdef CONFIG_HT_IRQ
3754 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3756 struct ht_irq_msg msg;
3757 fetch_ht_irq_msg(irq, &msg);
3759 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3760 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3762 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3763 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3765 write_ht_irq_msg(irq, &msg);
3768 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3770 struct irq_desc *desc = irq_to_desc(irq);
3771 struct irq_cfg *cfg;
3774 if (set_desc_affinity(desc, mask, &dest))
3777 cfg = desc->chip_data;
3779 target_ht_irq(irq, dest, cfg->vector);
3786 static struct irq_chip ht_irq_chip = {
3788 .mask = mask_ht_irq,
3789 .unmask = unmask_ht_irq,
3790 .ack = ack_apic_edge,
3792 .set_affinity = set_ht_irq_affinity,
3794 .retrigger = ioapic_retrigger_irq,
3797 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3799 struct irq_cfg *cfg;
3806 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3808 struct ht_irq_msg msg;
3811 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3812 apic->target_cpus());
3814 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3818 HT_IRQ_LOW_DEST_ID(dest) |
3819 HT_IRQ_LOW_VECTOR(cfg->vector) |
3820 ((apic->irq_dest_mode == 0) ?
3821 HT_IRQ_LOW_DM_PHYSICAL :
3822 HT_IRQ_LOW_DM_LOGICAL) |
3823 HT_IRQ_LOW_RQEOI_EDGE |
3824 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3825 HT_IRQ_LOW_MT_FIXED :
3826 HT_IRQ_LOW_MT_ARBITRATED) |
3827 HT_IRQ_LOW_IRQ_MASKED;
3829 write_ht_irq_msg(irq, &msg);
3831 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3832 handle_edge_irq, "edge");
3834 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3838 #endif /* CONFIG_HT_IRQ */
3840 int __init io_apic_get_redir_entries (int ioapic)
3842 union IO_APIC_reg_01 reg_01;
3843 unsigned long flags;
3845 raw_spin_lock_irqsave(&ioapic_lock, flags);
3846 reg_01.raw = io_apic_read(ioapic, 1);
3847 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3849 /* The register returns the maximum index redir index
3850 * supported, which is one less than the total number of redir
3853 return reg_01.bits.entries + 1;
3856 void __init probe_nr_irqs_gsi(void)
3860 nr = gsi_top + NR_IRQS_LEGACY;
3861 if (nr > nr_irqs_gsi)
3864 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3867 #ifdef CONFIG_SPARSE_IRQ
3868 int __init arch_probe_nr_irqs(void)
3872 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3873 nr_irqs = NR_VECTORS * nr_cpu_ids;
3875 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3876 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3878 * for MSI and HT dyn irq
3880 nr += nr_irqs_gsi * 16;
3889 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3890 struct io_apic_irq_attr *irq_attr)
3892 struct irq_desc *desc;
3893 struct irq_cfg *cfg;
3896 int trigger, polarity;
3898 ioapic = irq_attr->ioapic;
3899 if (!IO_APIC_IRQ(irq)) {
3900 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3906 node = dev_to_node(dev);
3908 node = cpu_to_node(boot_cpu_id);
3910 desc = irq_to_desc_alloc_node(irq, node);
3912 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3916 pin = irq_attr->ioapic_pin;
3917 trigger = irq_attr->trigger;
3918 polarity = irq_attr->polarity;
3921 * IRQs < 16 are already in the irq_2_pin[] map
3923 if (irq >= legacy_pic->nr_legacy_irqs) {
3924 cfg = desc->chip_data;
3925 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3926 printk(KERN_INFO "can not add pin %d for irq %d\n",
3932 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3937 int io_apic_set_pci_routing(struct device *dev, int irq,
3938 struct io_apic_irq_attr *irq_attr)
3942 * Avoid pin reprogramming. PRTs typically include entries
3943 * with redundant pin->gsi mappings (but unique PCI devices);
3944 * we only program the IOAPIC on the first.
3946 ioapic = irq_attr->ioapic;
3947 pin = irq_attr->ioapic_pin;
3948 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3949 pr_debug("Pin %d-%d already programmed\n",
3950 mp_ioapics[ioapic].apicid, pin);
3953 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3955 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3958 u8 __init io_apic_unique_id(u8 id)
3960 #ifdef CONFIG_X86_32
3961 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3962 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3963 return io_apic_get_unique_id(nr_ioapics, id);
3968 DECLARE_BITMAP(used, 256);
3970 bitmap_zero(used, 256);
3971 for (i = 0; i < nr_ioapics; i++) {
3972 struct mpc_ioapic *ia = &mp_ioapics[i];
3973 __set_bit(ia->apicid, used);
3975 if (!test_bit(id, used))
3977 return find_first_zero_bit(used, 256);
3981 #ifdef CONFIG_X86_32
3982 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3984 union IO_APIC_reg_00 reg_00;
3985 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3987 unsigned long flags;
3991 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3992 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3993 * supports up to 16 on one shared APIC bus.
3995 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3996 * advantage of new APIC bus architecture.
3999 if (physids_empty(apic_id_map))
4000 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
4002 raw_spin_lock_irqsave(&ioapic_lock, flags);
4003 reg_00.raw = io_apic_read(ioapic, 0);
4004 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4006 if (apic_id >= get_physical_broadcast()) {
4007 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
4008 "%d\n", ioapic, apic_id, reg_00.bits.ID);
4009 apic_id = reg_00.bits.ID;
4013 * Every APIC in a system must have a unique ID or we get lots of nice
4014 * 'stuck on smp_invalidate_needed IPI wait' messages.
4016 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
4018 for (i = 0; i < get_physical_broadcast(); i++) {
4019 if (!apic->check_apicid_used(&apic_id_map, i))
4023 if (i == get_physical_broadcast())
4024 panic("Max apic_id exceeded!\n");
4026 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
4027 "trying %d\n", ioapic, apic_id, i);
4032 apic->apicid_to_cpu_present(apic_id, &tmp);
4033 physids_or(apic_id_map, apic_id_map, tmp);
4035 if (reg_00.bits.ID != apic_id) {
4036 reg_00.bits.ID = apic_id;
4038 raw_spin_lock_irqsave(&ioapic_lock, flags);
4039 io_apic_write(ioapic, 0, reg_00.raw);
4040 reg_00.raw = io_apic_read(ioapic, 0);
4041 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4044 if (reg_00.bits.ID != apic_id) {
4045 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4050 apic_printk(APIC_VERBOSE, KERN_INFO
4051 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4057 int __init io_apic_get_version(int ioapic)
4059 union IO_APIC_reg_01 reg_01;
4060 unsigned long flags;
4062 raw_spin_lock_irqsave(&ioapic_lock, flags);
4063 reg_01.raw = io_apic_read(ioapic, 1);
4064 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4066 return reg_01.bits.version;
4069 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
4071 int ioapic, pin, idx;
4073 if (skip_ioapic_setup)
4076 ioapic = mp_find_ioapic(gsi);
4080 pin = mp_find_ioapic_pin(ioapic, gsi);
4084 idx = find_irq_entry(ioapic, pin, mp_INT);
4088 *trigger = irq_trigger(idx);
4089 *polarity = irq_polarity(idx);
4094 * This function currently is only a helper for the i386 smp boot process where
4095 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4096 * so mask in all cases should simply be apic->target_cpus()
4099 void __init setup_ioapic_dest(void)
4101 int pin, ioapic, irq, irq_entry;
4102 struct irq_desc *desc;
4103 const struct cpumask *mask;
4105 if (skip_ioapic_setup == 1)
4108 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
4109 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4110 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4111 if (irq_entry == -1)
4113 irq = pin_2_irq(irq_entry, ioapic, pin);
4115 if ((ioapic > 0) && (irq > 16))
4118 desc = irq_to_desc(irq);
4121 * Honour affinities which have been set in early boot
4124 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4125 mask = desc->affinity;
4127 mask = apic->target_cpus();
4129 if (intr_remapping_enabled)
4130 set_ir_ioapic_affinity_irq_desc(desc, mask);
4132 set_ioapic_affinity_irq_desc(desc, mask);
4138 #define IOAPIC_RESOURCE_NAME_SIZE 11
4140 static struct resource *ioapic_resources;
4142 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4145 struct resource *res;
4149 if (nr_ioapics <= 0)
4152 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4155 mem = alloc_bootmem(n);
4158 mem += sizeof(struct resource) * nr_ioapics;
4160 for (i = 0; i < nr_ioapics; i++) {
4162 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4163 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4164 mem += IOAPIC_RESOURCE_NAME_SIZE;
4167 ioapic_resources = res;
4172 void __init ioapic_init_mappings(void)
4174 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4175 struct resource *ioapic_res;
4178 ioapic_res = ioapic_setup_resources(nr_ioapics);
4179 for (i = 0; i < nr_ioapics; i++) {
4180 if (smp_found_config) {
4181 ioapic_phys = mp_ioapics[i].apicaddr;
4182 #ifdef CONFIG_X86_32
4185 "WARNING: bogus zero IO-APIC "
4186 "address found in MPTABLE, "
4187 "disabling IO/APIC support!\n");
4188 smp_found_config = 0;
4189 skip_ioapic_setup = 1;
4190 goto fake_ioapic_page;
4194 #ifdef CONFIG_X86_32
4197 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4198 ioapic_phys = __pa(ioapic_phys);
4200 set_fixmap_nocache(idx, ioapic_phys);
4201 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4202 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4206 ioapic_res->start = ioapic_phys;
4207 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4212 void __init ioapic_insert_resources(void)
4215 struct resource *r = ioapic_resources;
4220 "IO APIC resources couldn't be allocated.\n");
4224 for (i = 0; i < nr_ioapics; i++) {
4225 insert_resource(&iomem_resource, r);
4230 int mp_find_ioapic(u32 gsi)
4234 /* Find the IOAPIC that manages this GSI. */
4235 for (i = 0; i < nr_ioapics; i++) {
4236 if ((gsi >= mp_gsi_routing[i].gsi_base)
4237 && (gsi <= mp_gsi_routing[i].gsi_end))
4241 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4245 int mp_find_ioapic_pin(int ioapic, u32 gsi)
4247 if (WARN_ON(ioapic == -1))
4249 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4252 return gsi - mp_gsi_routing[ioapic].gsi_base;
4255 static int bad_ioapic(unsigned long address)
4257 if (nr_ioapics >= MAX_IO_APICS) {
4258 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4259 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4263 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4264 " found in table, skipping!\n");
4270 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4275 if (bad_ioapic(address))
4280 mp_ioapics[idx].type = MP_IOAPIC;
4281 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4282 mp_ioapics[idx].apicaddr = address;
4284 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4285 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4286 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4289 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4290 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4292 entries = io_apic_get_redir_entries(idx);
4293 mp_gsi_routing[idx].gsi_base = gsi_base;
4294 mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
4297 * The number of IO-APIC IRQ registers (== #pins):
4299 nr_ioapic_registers[idx] = entries;
4301 if (mp_gsi_routing[idx].gsi_end >= gsi_top)
4302 gsi_top = mp_gsi_routing[idx].gsi_end + 1;
4304 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4305 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4306 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4307 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4312 /* Enable IOAPIC early just for system timer */
4313 void __init pre_init_apic_IRQ0(void)
4315 struct irq_cfg *cfg;
4316 struct irq_desc *desc;
4318 printk(KERN_INFO "Early APIC setup for system timer0\n");
4320 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
4322 desc = irq_to_desc_alloc_node(0, 0);
4327 add_pin_to_irq_node(cfg, 0, 0, 0);
4328 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
4330 setup_IO_APIC_irq(0, 0, 0, desc, 0, 0);