arch/x86/kernel/apic/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/pci.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39 #ifdef CONFIG_ACPI
  40 #include <acpi/acpi_bus.h>
  41 #endif
  42 #include <linux/bootmem.h>
  43 #include <linux/dmar.h>
  44 #include <linux/hpet.h>
  45
  46 #include <asm/idle.h>
  47 #include <asm/io.h>
  48 #include <asm/smp.h>
  49 #include <asm/cpu.h>
  50 #include <asm/desc.h>
  51 #include <asm/proto.h>
  52 #include <asm/acpi.h>
  53 #include <asm/dma.h>
  54 #include <asm/timer.h>
  55 #include <asm/i8259.h>
  56 #include <asm/nmi.h>
  57 #include <asm/msidef.h>
  58 #include <asm/hypertransport.h>
  59 #include <asm/setup.h>
  60 #include <asm/irq_remapping.h>
  61 #include <asm/hpet.h>
  62 #include <asm/uv/uv_hub.h>
  63 #include <asm/uv/uv_irq.h>
  64
  65 #include <asm/apic.h>
  66
  67 #define __apicdebuginit(type) static type __init
  68
  69 /*
  70  *      Is the SiS APIC rmw bug present ?
  71  *      -1 = don't know, 0 = no, 1 = yes
  72  */
  73 int sis_apic_bug = -1;
  74
  75 static DEFINE_SPINLOCK(ioapic_lock);
  76 static DEFINE_SPINLOCK(vector_lock);
  77
  78 /*
  79  * # of IRQ routing registers
  80  */
  81 int nr_ioapic_registers[MAX_IO_APICS];
  82
  83 /* I/O APIC entries */
  84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
  85 int nr_ioapics;
  86
  87 /* MP IRQ source entries */
  88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
  89
  90 /* # of MP IRQ source entries */
  91 int mp_irq_entries;
  92
  93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  94 int mp_bus_id_to_type[MAX_MP_BUSSES];
  95 #endif
  96
  97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  98
  99 int skip_ioapic_setup;
 100
 101 void arch_disable_smp_support(void)
 102 {
 103 #ifdef CONFIG_PCI
 104         noioapicquirk = 1;
 105         noioapicreroute = -1;
 106 #endif
 107         skip_ioapic_setup = 1;
 108 }
 109
 110 static int __init parse_noapic(char *str)
 111 {
 112         /* disable IO-APIC */
 113         arch_disable_smp_support();
 114         return 0;
 115 }
 116 early_param("noapic", parse_noapic);
 117
 118 struct irq_pin_list;
 119
 120 /*
 121  * This is performance-critical, we want to do it O(1)
 122  *
 123  * the indexing order of this array favors 1:1 mappings
 124  * between pins and IRQs.
 125  */
 126
 127 struct irq_pin_list {
 128         int apic, pin;
 129         struct irq_pin_list *next;
 130 };
 131
 132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
 133 {
 134         struct irq_pin_list *pin;
 135         int node;
 136
 137         node = cpu_to_node(cpu);
 138
 139         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
 140
 141         return pin;
 142 }
 143
 144 struct irq_cfg {
 145         struct irq_pin_list *irq_2_pin;
 146         cpumask_var_t domain;
 147         cpumask_var_t old_domain;
 148         unsigned move_cleanup_count;
 149         u8 vector;
 150         u8 move_in_progress : 1;
 151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 152         u8 move_desc_pending : 1;
 153 #endif
 154 };
 155
 156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 157 #ifdef CONFIG_SPARSE_IRQ
 158 static struct irq_cfg irq_cfgx[] = {
 159 #else
 160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
 161 #endif
 162         [0]  = { .vector = IRQ0_VECTOR,  },
 163         [1]  = { .vector = IRQ1_VECTOR,  },
 164         [2]  = { .vector = IRQ2_VECTOR,  },
 165         [3]  = { .vector = IRQ3_VECTOR,  },
 166         [4]  = { .vector = IRQ4_VECTOR,  },
 167         [5]  = { .vector = IRQ5_VECTOR,  },
 168         [6]  = { .vector = IRQ6_VECTOR,  },
 169         [7]  = { .vector = IRQ7_VECTOR,  },
 170         [8]  = { .vector = IRQ8_VECTOR,  },
 171         [9]  = { .vector = IRQ9_VECTOR,  },
 172         [10] = { .vector = IRQ10_VECTOR, },
 173         [11] = { .vector = IRQ11_VECTOR, },
 174         [12] = { .vector = IRQ12_VECTOR, },
 175         [13] = { .vector = IRQ13_VECTOR, },
 176         [14] = { .vector = IRQ14_VECTOR, },
 177         [15] = { .vector = IRQ15_VECTOR, },
 178 };
 179
 180 int __init arch_early_irq_init(void)
 181 {
 182         struct irq_cfg *cfg;
 183         struct irq_desc *desc;
 184         int count;
 185         int i;
 186
 187         cfg = irq_cfgx;
 188         count = ARRAY_SIZE(irq_cfgx);
 189
 190         for (i = 0; i < count; i++) {
 191                 desc = irq_to_desc(i);
 192                 desc->chip_data = &cfg[i];
 193                 alloc_bootmem_cpumask_var(&cfg[i].domain);
 194                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
 195                 if (i < NR_IRQS_LEGACY)
 196                         cpumask_setall(cfg[i].domain);
 197         }
 198
 199         return 0;
 200 }
 201
 202 #ifdef CONFIG_SPARSE_IRQ
 203 static struct irq_cfg *irq_cfg(unsigned int irq)
 204 {
 205         struct irq_cfg *cfg = NULL;
 206         struct irq_desc *desc;
 207
 208         desc = irq_to_desc(irq);
 209         if (desc)
 210                 cfg = desc->chip_data;
 211
 212         return cfg;
 213 }
 214
 215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
 216 {
 217         struct irq_cfg *cfg;
 218         int node;
 219
 220         node = cpu_to_node(cpu);
 221
 222         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
 223         if (cfg) {
 224                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
 225                         kfree(cfg);
 226                         cfg = NULL;
 227                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
 228                                                           GFP_ATOMIC, node)) {
 229                         free_cpumask_var(cfg->domain);
 230                         kfree(cfg);
 231                         cfg = NULL;
 232                 } else {
 233                         cpumask_clear(cfg->domain);
 234                         cpumask_clear(cfg->old_domain);
 235                 }
 236         }
 237
 238         return cfg;
 239 }
 240
 241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
 242 {
 243         struct irq_cfg *cfg;
 244
 245         cfg = desc->chip_data;
 246         if (!cfg) {
 247                 desc->chip_data = get_one_free_irq_cfg(cpu);
 248                 if (!desc->chip_data) {
 249                         printk(KERN_ERR "can not alloc irq_cfg\n");
 250                         BUG_ON(1);
 251                 }
 252         }
 253
 254         return 0;
 255 }
 256
 257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 258
 259 static void
 260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
 261 {
 262         struct irq_pin_list *old_entry, *head, *tail, *entry;
 263
 264         cfg->irq_2_pin = NULL;
 265         old_entry = old_cfg->irq_2_pin;
 266         if (!old_entry)
 267                 return;
 268
 269         entry = get_one_free_irq_2_pin(cpu);
 270         if (!entry)
 271                 return;
 272
 273         entry->apic     = old_entry->apic;
 274         entry->pin      = old_entry->pin;
 275         head            = entry;
 276         tail            = entry;
 277         old_entry       = old_entry->next;
 278         while (old_entry) {
 279                 entry = get_one_free_irq_2_pin(cpu);
 280                 if (!entry) {
 281                         entry = head;
 282                         while (entry) {
 283                                 head = entry->next;
 284                                 kfree(entry);
 285                                 entry = head;
 286                         }
 287                         /* still use the old one */
 288                         return;
 289                 }
 290                 entry->apic     = old_entry->apic;
 291                 entry->pin      = old_entry->pin;
 292                 tail->next      = entry;
 293                 tail            = entry;
 294                 old_entry       = old_entry->next;
 295         }
 296
 297         tail->next = NULL;
 298         cfg->irq_2_pin = head;
 299 }
 300
 301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
 302 {
 303         struct irq_pin_list *entry, *next;
 304
 305         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
 306                 return;
 307
 308         entry = old_cfg->irq_2_pin;
 309
 310         while (entry) {
 311                 next = entry->next;
 312                 kfree(entry);
 313                 entry = next;
 314         }
 315         old_cfg->irq_2_pin = NULL;
 316 }
 317
 318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
 319                                  struct irq_desc *desc, int cpu)
 320 {
 321         struct irq_cfg *cfg;
 322         struct irq_cfg *old_cfg;
 323
 324         cfg = get_one_free_irq_cfg(cpu);
 325
 326         if (!cfg)
 327                 return;
 328
 329         desc->chip_data = cfg;
 330
 331         old_cfg = old_desc->chip_data;
 332
 333         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
 334
 335         init_copy_irq_2_pin(old_cfg, cfg, cpu);
 336 }
 337
 338 static void free_irq_cfg(struct irq_cfg *old_cfg)
 339 {
 340         kfree(old_cfg);
 341 }
 342
 343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
 344 {
 345         struct irq_cfg *old_cfg, *cfg;
 346
 347         old_cfg = old_desc->chip_data;
 348         cfg = desc->chip_data;
 349
 350         if (old_cfg == cfg)
 351                 return;
 352
 353         if (old_cfg) {
 354                 free_irq_2_pin(old_cfg, cfg);
 355                 free_irq_cfg(old_cfg);
 356                 old_desc->chip_data = NULL;
 357         }
 358 }
 359
 360 static void
 361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 362 {
 363         struct irq_cfg *cfg = desc->chip_data;
 364
 365         if (!cfg->move_in_progress) {
 366                 /* it means that domain is not changed */
 367                 if (!cpumask_intersects(desc->affinity, mask))
 368                         cfg->move_desc_pending = 1;
 369         }
 370 }
 371 #endif
 372
 373 #else
 374 static struct irq_cfg *irq_cfg(unsigned int irq)
 375 {
 376         return irq < nr_irqs ? irq_cfgx + irq : NULL;
 377 }
 378
 379 #endif
 380
 381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
 382 static inline void
 383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 384 {
 385 }
 386 #endif
 387
 388 struct io_apic {
 389         unsigned int index;
 390         unsigned int unused[3];
 391         unsigned int data;
 392         unsigned int unused2[11];
 393         unsigned int eoi;
 394 };
 395
 396 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 397 {
 398         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 399                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
 400 }
 401
 402 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
 403 {
 404         struct io_apic __iomem *io_apic = io_apic_base(apic);
 405         writel(vector, &io_apic->eoi);
 406 }
 407
 408 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 409 {
 410         struct io_apic __iomem *io_apic = io_apic_base(apic);
 411         writel(reg, &io_apic->index);
 412         return readl(&io_apic->data);
 413 }
 414
 415 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 416 {
 417         struct io_apic __iomem *io_apic = io_apic_base(apic);
 418         writel(reg, &io_apic->index);
 419         writel(value, &io_apic->data);
 420 }
 421
 422 /*
 423  * Re-write a value: to be used for read-modify-write
 424  * cycles where the read already set up the index register.
 425  *
 426  * Older SiS APIC requires we rewrite the index register
 427  */
 428 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 429 {
 430         struct io_apic __iomem *io_apic = io_apic_base(apic);
 431
 432         if (sis_apic_bug)
 433                 writel(reg, &io_apic->index);
 434         writel(value, &io_apic->data);
 435 }
 436
 437 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
 438 {
 439         struct irq_pin_list *entry;
 440         unsigned long flags;
 441
 442         spin_lock_irqsave(&ioapic_lock, flags);
 443         entry = cfg->irq_2_pin;
 444         for (;;) {
 445                 unsigned int reg;
 446                 int pin;
 447
 448                 if (!entry)
 449                         break;
 450                 pin = entry->pin;
 451                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 452                 /* Is the remote IRR bit set? */
 453                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
 454                         spin_unlock_irqrestore(&ioapic_lock, flags);
 455                         return true;
 456                 }
 457                 if (!entry->next)
 458                         break;
 459                 entry = entry->next;
 460         }
 461         spin_unlock_irqrestore(&ioapic_lock, flags);
 462
 463         return false;
 464 }
 465
 466 union entry_union {
 467         struct { u32 w1, w2; };
 468         struct IO_APIC_route_entry entry;
 469 };
 470
 471 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 472 {
 473         union entry_union eu;
 474         unsigned long flags;
 475         spin_lock_irqsave(&ioapic_lock, flags);
 476         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 477         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 478         spin_unlock_irqrestore(&ioapic_lock, flags);
 479         return eu.entry;
 480 }
 481
 482 /*
 483  * When we write a new IO APIC routing entry, we need to write the high
 484  * word first! If the mask bit in the low word is clear, we will enable
 485  * the interrupt, and we need to make sure the entry is fully populated
 486  * before that happens.
 487  */
 488 static void
 489 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 490 {
 491         union entry_union eu;
 492         eu.entry = e;
 493         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 494         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 495 }
 496
 497 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 498 {
 499         unsigned long flags;
 500         spin_lock_irqsave(&ioapic_lock, flags);
 501         __ioapic_write_entry(apic, pin, e);
 502         spin_unlock_irqrestore(&ioapic_lock, flags);
 503 }
 504
 505 /*
 506  * When we mask an IO APIC routing entry, we need to write the low
 507  * word first, in order to set the mask bit before we change the
 508  * high bits!
 509  */
 510 static void ioapic_mask_entry(int apic, int pin)
 511 {
 512         unsigned long flags;
 513         union entry_union eu = { .entry.mask = 1 };
 514
 515         spin_lock_irqsave(&ioapic_lock, flags);
 516         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 517         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 518         spin_unlock_irqrestore(&ioapic_lock, flags);
 519 }
 520
 521 /*
 522  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 523  * shared ISA-space IRQs, so we have to support them. We are super
 524  * fast in the common case, and fast for shared ISA-space IRQs.
 525  */
 526 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
 527 {
 528         struct irq_pin_list *entry;
 529
 530         entry = cfg->irq_2_pin;
 531         if (!entry) {
 532                 entry = get_one_free_irq_2_pin(cpu);
 533                 if (!entry) {
 534                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
 535                                         apic, pin);
 536                         return;
 537                 }
 538                 cfg->irq_2_pin = entry;
 539                 entry->apic = apic;
 540                 entry->pin = pin;
 541                 return;
 542         }
 543
 544         while (entry->next) {
 545                 /* not again, please */
 546                 if (entry->apic == apic && entry->pin == pin)
 547                         return;
 548
 549                 entry = entry->next;
 550         }
 551
 552         entry->next = get_one_free_irq_2_pin(cpu);
 553         entry = entry->next;
 554         entry->apic = apic;
 555         entry->pin = pin;
 556 }
 557
 558 /*
 559  * Reroute an IRQ to a different pin.
 560  */
 561 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
 562                                       int oldapic, int oldpin,
 563                                       int newapic, int newpin)
 564 {
 565         struct irq_pin_list *entry = cfg->irq_2_pin;
 566         int replaced = 0;
 567
 568         while (entry) {
 569                 if (entry->apic == oldapic && entry->pin == oldpin) {
 570                         entry->apic = newapic;
 571                         entry->pin = newpin;
 572                         replaced = 1;
 573                         /* every one is different, right? */
 574                         break;
 575                 }
 576                 entry = entry->next;
 577         }
 578
 579         /* why? call replace before add? */
 580         if (!replaced)
 581                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
 582 }
 583
 584 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
 585                                 int mask_and, int mask_or,
 586                                 void (*final)(struct irq_pin_list *entry))
 587 {
 588         int pin;
 589         struct irq_pin_list *entry;
 590
 591         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
 592                 unsigned int reg;
 593                 pin = entry->pin;
 594                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
 595                 reg &= mask_and;
 596                 reg |= mask_or;
 597                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
 598                 if (final)
 599                         final(entry);
 600         }
 601 }
 602
 603 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
 604 {
 605         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
 606 }
 607
 608 #ifdef CONFIG_X86_64
 609 static void io_apic_sync(struct irq_pin_list *entry)
 610 {
 611         /*
 612          * Synchronize the IO-APIC and the CPU by doing
 613          * a dummy read from the IO-APIC
 614          */
 615         struct io_apic __iomem *io_apic;
 616         io_apic = io_apic_base(entry->apic);
 617         readl(&io_apic->data);
 618 }
 619
 620 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 621 {
 622         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 623 }
 624 #else /* CONFIG_X86_32 */
 625 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 626 {
 627         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
 628 }
 629
 630 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
 631 {
 632         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
 633                         IO_APIC_REDIR_MASKED, NULL);
 634 }
 635
 636 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
 637 {
 638         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
 639                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
 640 }
 641 #endif /* CONFIG_X86_32 */
 642
 643 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
 644 {
 645         struct irq_cfg *cfg = desc->chip_data;
 646         unsigned long flags;
 647
 648         BUG_ON(!cfg);
 649
 650         spin_lock_irqsave(&ioapic_lock, flags);
 651         __mask_IO_APIC_irq(cfg);
 652         spin_unlock_irqrestore(&ioapic_lock, flags);
 653 }
 654
 655 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
 656 {
 657         struct irq_cfg *cfg = desc->chip_data;
 658         unsigned long flags;
 659
 660         spin_lock_irqsave(&ioapic_lock, flags);
 661         __unmask_IO_APIC_irq(cfg);
 662         spin_unlock_irqrestore(&ioapic_lock, flags);
 663 }
 664
 665 static void mask_IO_APIC_irq(unsigned int irq)
 666 {
 667         struct irq_desc *desc = irq_to_desc(irq);
 668
 669         mask_IO_APIC_irq_desc(desc);
 670 }
 671 static void unmask_IO_APIC_irq(unsigned int irq)
 672 {
 673         struct irq_desc *desc = irq_to_desc(irq);
 674
 675         unmask_IO_APIC_irq_desc(desc);
 676 }
 677
 678 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 679 {
 680         struct IO_APIC_route_entry entry;
 681
 682         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 683         entry = ioapic_read_entry(apic, pin);
 684         if (entry.delivery_mode == dest_SMI)
 685                 return;
 686         /*
 687          * Disable it in the IO-APIC irq-routing table:
 688          */
 689         ioapic_mask_entry(apic, pin);
 690 }
 691
 692 static void clear_IO_APIC (void)
 693 {
 694         int apic, pin;
 695
 696         for (apic = 0; apic < nr_ioapics; apic++)
 697                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 698                         clear_IO_APIC_pin(apic, pin);
 699 }
 700
 701 #ifdef CONFIG_X86_32
 702 /*
 703  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 704  * specific CPU-side IRQs.
 705  */
 706
 707 #define MAX_PIRQS 8
 708 static int pirq_entries[MAX_PIRQS] = {
 709         [0 ... MAX_PIRQS - 1] = -1
 710 };
 711
 712 static int __init ioapic_pirq_setup(char *str)
 713 {
 714         int i, max;
 715         int ints[MAX_PIRQS+1];
 716
 717         get_options(str, ARRAY_SIZE(ints), ints);
 718
 719         apic_printk(APIC_VERBOSE, KERN_INFO
 720                         "PIRQ redirection, working around broken MP-BIOS.\n");
 721         max = MAX_PIRQS;
 722         if (ints[0] < MAX_PIRQS)
 723                 max = ints[0];
 724
 725         for (i = 0; i < max; i++) {
 726                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 727                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 728                 /*
 729                  * PIRQs are mapped upside down, usually.
 730                  */
 731                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 732         }
 733         return 1;
 734 }
 735
 736 __setup("pirq=", ioapic_pirq_setup);
 737 #endif /* CONFIG_X86_32 */
 738
 739 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
 740 {
 741         int apic;
 742         struct IO_APIC_route_entry **ioapic_entries;
 743
 744         ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
 745                                 GFP_ATOMIC);
 746         if (!ioapic_entries)
 747                 return 0;
 748
 749         for (apic = 0; apic < nr_ioapics; apic++) {
 750                 ioapic_entries[apic] =
 751                         kzalloc(sizeof(struct IO_APIC_route_entry) *
 752                                 nr_ioapic_registers[apic], GFP_ATOMIC);
 753                 if (!ioapic_entries[apic])
 754                         goto nomem;
 755         }
 756
 757         return ioapic_entries;
 758
 759 nomem:
 760         while (--apic >= 0)
 761                 kfree(ioapic_entries[apic]);
 762         kfree(ioapic_entries);
 763
 764         return 0;
 765 }
 766
 767 /*
 768  * Saves all the IO-APIC RTE's
 769  */
 770 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
 771 {
 772         int apic, pin;
 773
 774         if (!ioapic_entries)
 775                 return -ENOMEM;
 776
 777         for (apic = 0; apic < nr_ioapics; apic++) {
 778                 if (!ioapic_entries[apic])
 779                         return -ENOMEM;
 780
 781                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 782                         ioapic_entries[apic][pin] =
 783                                 ioapic_read_entry(apic, pin);
 784         }
 785
 786         return 0;
 787 }
 788
 789 /*
 790  * Mask all IO APIC entries.
 791  */
 792 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
 793 {
 794         int apic, pin;
 795
 796         if (!ioapic_entries)
 797                 return;
 798
 799         for (apic = 0; apic < nr_ioapics; apic++) {
 800                 if (!ioapic_entries[apic])
 801                         break;
 802
 803                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 804                         struct IO_APIC_route_entry entry;
 805
 806                         entry = ioapic_entries[apic][pin];
 807                         if (!entry.mask) {
 808                                 entry.mask = 1;
 809                                 ioapic_write_entry(apic, pin, entry);
 810                         }
 811                 }
 812         }
 813 }
 814
 815 /*
 816  * Restore IO APIC entries which was saved in ioapic_entries.
 817  */
 818 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
 819 {
 820         int apic, pin;
 821
 822         if (!ioapic_entries)
 823                 return -ENOMEM;
 824
 825         for (apic = 0; apic < nr_ioapics; apic++) {
 826                 if (!ioapic_entries[apic])
 827                         return -ENOMEM;
 828
 829                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 830                         ioapic_write_entry(apic, pin,
 831                                         ioapic_entries[apic][pin]);
 832         }
 833         return 0;
 834 }
 835
 836 void reinit_intr_remapped_IO_APIC(int intr_remapping,
 837         struct IO_APIC_route_entry **ioapic_entries)
 838
 839 {
 840         /*
 841          * for now plain restore of previous settings.
 842          * TBD: In the case of OS enabling interrupt-remapping,
 843          * IO-APIC RTE's need to be setup to point to interrupt-remapping
 844          * table entries. for now, do a plain restore, and wait for
 845          * the setup_IO_APIC_irqs() to do proper initialization.
 846          */
 847         restore_IO_APIC_setup(ioapic_entries);
 848 }
 849
 850 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
 851 {
 852         int apic;
 853
 854         for (apic = 0; apic < nr_ioapics; apic++)
 855                 kfree(ioapic_entries[apic]);
 856
 857         kfree(ioapic_entries);
 858 }
 859
 860 /*
 861  * Find the IRQ entry number of a certain pin.
 862  */
 863 static int find_irq_entry(int apic, int pin, int type)
 864 {
 865         int i;
 866
 867         for (i = 0; i < mp_irq_entries; i++)
 868                 if (mp_irqs[i].irqtype == type &&
 869                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
 870                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
 871                     mp_irqs[i].dstirq == pin)
 872                         return i;
 873
 874         return -1;
 875 }
 876
 877 /*
 878  * Find the pin to which IRQ[irq] (ISA) is connected
 879  */
 880 static int __init find_isa_irq_pin(int irq, int type)
 881 {
 882         int i;
 883
 884         for (i = 0; i < mp_irq_entries; i++) {
 885                 int lbus = mp_irqs[i].srcbus;
 886
 887                 if (test_bit(lbus, mp_bus_not_pci) &&
 888                     (mp_irqs[i].irqtype == type) &&
 889                     (mp_irqs[i].srcbusirq == irq))
 890
 891                         return mp_irqs[i].dstirq;
 892         }
 893         return -1;
 894 }
 895
 896 static int __init find_isa_irq_apic(int irq, int type)
 897 {
 898         int i;
 899
 900         for (i = 0; i < mp_irq_entries; i++) {
 901                 int lbus = mp_irqs[i].srcbus;
 902
 903                 if (test_bit(lbus, mp_bus_not_pci) &&
 904                     (mp_irqs[i].irqtype == type) &&
 905                     (mp_irqs[i].srcbusirq == irq))
 906                         break;
 907         }
 908         if (i < mp_irq_entries) {
 909                 int apic;
 910                 for(apic = 0; apic < nr_ioapics; apic++) {
 911                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
 912                                 return apic;
 913                 }
 914         }
 915
 916         return -1;
 917 }
 918
 919 /*
 920  * Find a specific PCI IRQ entry.
 921  * Not an __init, possibly needed by modules
 922  */
 923 static int pin_2_irq(int idx, int apic, int pin);
 924
 925 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 926 {
 927         int apic, i, best_guess = -1;
 928
 929         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 930                 bus, slot, pin);
 931         if (test_bit(bus, mp_bus_not_pci)) {
 932                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 933                 return -1;
 934         }
 935         for (i = 0; i < mp_irq_entries; i++) {
 936                 int lbus = mp_irqs[i].srcbus;
 937
 938                 for (apic = 0; apic < nr_ioapics; apic++)
 939                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
 940                             mp_irqs[i].dstapic == MP_APIC_ALL)
 941                                 break;
 942
 943                 if (!test_bit(lbus, mp_bus_not_pci) &&
 944                     !mp_irqs[i].irqtype &&
 945                     (bus == lbus) &&
 946                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
 947                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
 948
 949                         if (!(apic || IO_APIC_IRQ(irq)))
 950                                 continue;
 951
 952                         if (pin == (mp_irqs[i].srcbusirq & 3))
 953                                 return irq;
 954                         /*
 955                          * Use the first all-but-pin matching entry as a
 956                          * best-guess fuzzy result for broken mptables.
 957                          */
 958                         if (best_guess < 0)
 959                                 best_guess = irq;
 960                 }
 961         }
 962         return best_guess;
 963 }
 964
 965 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 966
 967 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
 968 /*
 969  * EISA Edge/Level control register, ELCR
 970  */
 971 static int EISA_ELCR(unsigned int irq)
 972 {
 973         if (irq < NR_IRQS_LEGACY) {
 974                 unsigned int port = 0x4d0 + (irq >> 3);
 975                 return (inb(port) >> (irq & 7)) & 1;
 976         }
 977         apic_printk(APIC_VERBOSE, KERN_INFO
 978                         "Broken MPtable reports ISA irq %d\n", irq);
 979         return 0;
 980 }
 981
 982 #endif
 983
 984 /* ISA interrupts are always polarity zero edge triggered,
 985  * when listed as conforming in the MP table. */
 986
 987 #define default_ISA_trigger(idx)        (0)
 988 #define default_ISA_polarity(idx)       (0)
 989
 990 /* EISA interrupts are always polarity zero and can be edge or level
 991  * trigger depending on the ELCR value.  If an interrupt is listed as
 992  * EISA conforming in the MP table, that means its trigger type must
 993  * be read in from the ELCR */
 994
 995 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
 996 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
 997
 998 /* PCI interrupts are always polarity one level triggered,
 999  * when listed as conforming in the MP table. */
1000
1001 #define default_PCI_trigger(idx)        (1)
1002 #define default_PCI_polarity(idx)       (1)
1003
1004 /* MCA interrupts are always polarity zero level triggered,
1005  * when listed as conforming in the MP table. */
1006
1007 #define default_MCA_trigger(idx)        (1)
1008 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1009
1010 static int MPBIOS_polarity(int idx)
1011 {
1012         int bus = mp_irqs[idx].srcbus;
1013         int polarity;
1014
1015         /*
1016          * Determine IRQ line polarity (high active or low active):
1017          */
1018         switch (mp_irqs[idx].irqflag & 3)
1019         {
1020                 case 0: /* conforms, ie. bus-type dependent polarity */
1021                         if (test_bit(bus, mp_bus_not_pci))
1022                                 polarity = default_ISA_polarity(idx);
1023                         else
1024                                 polarity = default_PCI_polarity(idx);
1025                         break;
1026                 case 1: /* high active */
1027                 {
1028                         polarity = 0;
1029                         break;
1030                 }
1031                 case 2: /* reserved */
1032                 {
1033                         printk(KERN_WARNING "broken BIOS!!\n");
1034                         polarity = 1;
1035                         break;
1036                 }
1037                 case 3: /* low active */
1038                 {
1039                         polarity = 1;
1040                         break;
1041                 }
1042                 default: /* invalid */
1043                 {
1044                         printk(KERN_WARNING "broken BIOS!!\n");
1045                         polarity = 1;
1046                         break;
1047                 }
1048         }
1049         return polarity;
1050 }
1051
1052 static int MPBIOS_trigger(int idx)
1053 {
1054         int bus = mp_irqs[idx].srcbus;
1055         int trigger;
1056
1057         /*
1058          * Determine IRQ trigger mode (edge or level sensitive):
1059          */
1060         switch ((mp_irqs[idx].irqflag>>2) & 3)
1061         {
1062                 case 0: /* conforms, ie. bus-type dependent */
1063                         if (test_bit(bus, mp_bus_not_pci))
1064                                 trigger = default_ISA_trigger(idx);
1065                         else
1066                                 trigger = default_PCI_trigger(idx);
1067 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1068                         switch (mp_bus_id_to_type[bus]) {
1069                                 case MP_BUS_ISA: /* ISA pin */
1070                                 {
1071                                         /* set before the switch */
1072                                         break;
1073                                 }
1074                                 case MP_BUS_EISA: /* EISA pin */
1075                                 {
1076                                         trigger = default_EISA_trigger(idx);
1077                                         break;
1078                                 }
1079                                 case MP_BUS_PCI: /* PCI pin */
1080                                 {
1081                                         /* set before the switch */
1082                                         break;
1083                                 }
1084                                 case MP_BUS_MCA: /* MCA pin */
1085                                 {
1086                                         trigger = default_MCA_trigger(idx);
1087                                         break;
1088                                 }
1089                                 default:
1090                                 {
1091                                         printk(KERN_WARNING "broken BIOS!!\n");
1092                                         trigger = 1;
1093                                         break;
1094                                 }
1095                         }
1096 #endif
1097                         break;
1098                 case 1: /* edge */
1099                 {
1100                         trigger = 0;
1101                         break;
1102                 }
1103                 case 2: /* reserved */
1104                 {
1105                         printk(KERN_WARNING "broken BIOS!!\n");
1106                         trigger = 1;
1107                         break;
1108                 }
1109                 case 3: /* level */
1110                 {
1111                         trigger = 1;
1112                         break;
1113                 }
1114                 default: /* invalid */
1115                 {
1116                         printk(KERN_WARNING "broken BIOS!!\n");
1117                         trigger = 0;
1118                         break;
1119                 }
1120         }
1121         return trigger;
1122 }
1123
1124 static inline int irq_polarity(int idx)
1125 {
1126         return MPBIOS_polarity(idx);
1127 }
1128
1129 static inline int irq_trigger(int idx)
1130 {
1131         return MPBIOS_trigger(idx);
1132 }
1133
1134 int (*ioapic_renumber_irq)(int ioapic, int irq);
1135 static int pin_2_irq(int idx, int apic, int pin)
1136 {
1137         int irq, i;
1138         int bus = mp_irqs[idx].srcbus;
1139
1140         /*
1141          * Debugging check, we are in big trouble if this message pops up!
1142          */
1143         if (mp_irqs[idx].dstirq != pin)
1144                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1145
1146         if (test_bit(bus, mp_bus_not_pci)) {
1147                 irq = mp_irqs[idx].srcbusirq;
1148         } else {
1149                 /*
1150                  * PCI IRQs are mapped in order
1151                  */
1152                 i = irq = 0;
1153                 while (i < apic)
1154                         irq += nr_ioapic_registers[i++];
1155                 irq += pin;
1156                 /*
1157                  * For MPS mode, so far only needed by ES7000 platform
1158                  */
1159                 if (ioapic_renumber_irq)
1160                         irq = ioapic_renumber_irq(apic, irq);
1161         }
1162
1163 #ifdef CONFIG_X86_32
1164         /*
1165          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1166          */
1167         if ((pin >= 16) && (pin <= 23)) {
1168                 if (pirq_entries[pin-16] != -1) {
1169                         if (!pirq_entries[pin-16]) {
1170                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1171                                                 "disabling PIRQ%d\n", pin-16);
1172                         } else {
1173                                 irq = pirq_entries[pin-16];
1174                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1175                                                 "using PIRQ%d -> IRQ %d\n",
1176                                                 pin-16, irq);
1177                         }
1178                 }
1179         }
1180 #endif
1181
1182         return irq;
1183 }
1184
1185 void lock_vector_lock(void)
1186 {
1187         /* Used to the online set of cpus does not change
1188          * during assign_irq_vector.
1189          */
1190         spin_lock(&vector_lock);
1191 }
1192
1193 void unlock_vector_lock(void)
1194 {
1195         spin_unlock(&vector_lock);
1196 }
1197
1198 static int
1199 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1200 {
1201         /*
1202          * NOTE! The local APIC isn't very good at handling
1203          * multiple interrupts at the same interrupt level.
1204          * As the interrupt level is determined by taking the
1205          * vector number and shifting that right by 4, we
1206          * want to spread these out a bit so that they don't
1207          * all fall in the same interrupt level.
1208          *
1209          * Also, we've got to be careful not to trash gate
1210          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1211          */
1212         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1213         unsigned int old_vector;
1214         int cpu, err;
1215         cpumask_var_t tmp_mask;
1216
1217         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1218                 return -EBUSY;
1219
1220         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1221                 return -ENOMEM;
1222
1223         old_vector = cfg->vector;
1224         if (old_vector) {
1225                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1226                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1227                 if (!cpumask_empty(tmp_mask)) {
1228                         free_cpumask_var(tmp_mask);
1229                         return 0;
1230                 }
1231         }
1232
1233         /* Only try and allocate irqs on cpus that are present */
1234         err = -ENOSPC;
1235         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1236                 int new_cpu;
1237                 int vector, offset;
1238
1239                 apic->vector_allocation_domain(cpu, tmp_mask);
1240
1241                 vector = current_vector;
1242                 offset = current_offset;
1243 next:
1244                 vector += 8;
1245                 if (vector >= first_system_vector) {
1246                         /* If out of vectors on large boxen, must share them. */
1247                         offset = (offset + 1) % 8;
1248                         vector = FIRST_DEVICE_VECTOR + offset;
1249                 }
1250                 if (unlikely(current_vector == vector))
1251                         continue;
1252
1253                 if (test_bit(vector, used_vectors))
1254                         goto next;
1255
1256                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1257                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1258                                 goto next;
1259                 /* Found one! */
1260                 current_vector = vector;
1261                 current_offset = offset;
1262                 if (old_vector) {
1263                         cfg->move_in_progress = 1;
1264                         cpumask_copy(cfg->old_domain, cfg->domain);
1265                 }
1266                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1267                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1268                 cfg->vector = vector;
1269                 cpumask_copy(cfg->domain, tmp_mask);
1270                 err = 0;
1271                 break;
1272         }
1273         free_cpumask_var(tmp_mask);
1274         return err;
1275 }
1276
1277 static int
1278 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1279 {
1280         int err;
1281         unsigned long flags;
1282
1283         spin_lock_irqsave(&vector_lock, flags);
1284         err = __assign_irq_vector(irq, cfg, mask);
1285         spin_unlock_irqrestore(&vector_lock, flags);
1286         return err;
1287 }
1288
1289 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1290 {
1291         int cpu, vector;
1292
1293         BUG_ON(!cfg->vector);
1294
1295         vector = cfg->vector;
1296         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1297                 per_cpu(vector_irq, cpu)[vector] = -1;
1298
1299         cfg->vector = 0;
1300         cpumask_clear(cfg->domain);
1301
1302         if (likely(!cfg->move_in_progress))
1303                 return;
1304         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1305                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1306                                                                 vector++) {
1307                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1308                                 continue;
1309                         per_cpu(vector_irq, cpu)[vector] = -1;
1310                         break;
1311                 }
1312         }
1313         cfg->move_in_progress = 0;
1314 }
1315
1316 void __setup_vector_irq(int cpu)
1317 {
1318         /* Initialize vector_irq on a new cpu */
1319         /* This function must be called with vector_lock held */
1320         int irq, vector;
1321         struct irq_cfg *cfg;
1322         struct irq_desc *desc;
1323
1324         /* Mark the inuse vectors */
1325         for_each_irq_desc(irq, desc) {
1326                 cfg = desc->chip_data;
1327                 if (!cpumask_test_cpu(cpu, cfg->domain))
1328                         continue;
1329                 vector = cfg->vector;
1330                 per_cpu(vector_irq, cpu)[vector] = irq;
1331         }
1332         /* Mark the free vectors */
1333         for (vector = 0; vector < NR_VECTORS; ++vector) {
1334                 irq = per_cpu(vector_irq, cpu)[vector];
1335                 if (irq < 0)
1336                         continue;
1337
1338                 cfg = irq_cfg(irq);
1339                 if (!cpumask_test_cpu(cpu, cfg->domain))
1340                         per_cpu(vector_irq, cpu)[vector] = -1;
1341         }
1342 }
1343
1344 static struct irq_chip ioapic_chip;
1345 static struct irq_chip ir_ioapic_chip;
1346
1347 #define IOAPIC_AUTO     -1
1348 #define IOAPIC_EDGE     0
1349 #define IOAPIC_LEVEL    1
1350
1351 #ifdef CONFIG_X86_32
1352 static inline int IO_APIC_irq_trigger(int irq)
1353 {
1354         int apic, idx, pin;
1355
1356         for (apic = 0; apic < nr_ioapics; apic++) {
1357                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1358                         idx = find_irq_entry(apic, pin, mp_INT);
1359                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1360                                 return irq_trigger(idx);
1361                 }
1362         }
1363         /*
1364          * nonexistent IRQs are edge default
1365          */
1366         return 0;
1367 }
1368 #else
1369 static inline int IO_APIC_irq_trigger(int irq)
1370 {
1371         return 1;
1372 }
1373 #endif
1374
1375 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1376 {
1377
1378         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1379             trigger == IOAPIC_LEVEL)
1380                 desc->status |= IRQ_LEVEL;
1381         else
1382                 desc->status &= ~IRQ_LEVEL;
1383
1384         if (irq_remapped(irq)) {
1385                 desc->status |= IRQ_MOVE_PCNTXT;
1386                 if (trigger)
1387                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1388                                                       handle_fasteoi_irq,
1389                                                      "fasteoi");
1390                 else
1391                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1392                                                       handle_edge_irq, "edge");
1393                 return;
1394         }
1395
1396         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1397             trigger == IOAPIC_LEVEL)
1398                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1399                                               handle_fasteoi_irq,
1400                                               "fasteoi");
1401         else
1402                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1403                                               handle_edge_irq, "edge");
1404 }
1405
1406 int setup_ioapic_entry(int apic_id, int irq,
1407                        struct IO_APIC_route_entry *entry,
1408                        unsigned int destination, int trigger,
1409                        int polarity, int vector, int pin)
1410 {
1411         /*
1412          * add it to the IO-APIC irq-routing table:
1413          */
1414         memset(entry,0,sizeof(*entry));
1415
1416         if (intr_remapping_enabled) {
1417                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1418                 struct irte irte;
1419                 struct IR_IO_APIC_route_entry *ir_entry =
1420                         (struct IR_IO_APIC_route_entry *) entry;
1421                 int index;
1422
1423                 if (!iommu)
1424                         panic("No mapping iommu for ioapic %d\n", apic_id);
1425
1426                 index = alloc_irte(iommu, irq, 1);
1427                 if (index < 0)
1428                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1429
1430                 memset(&irte, 0, sizeof(irte));
1431
1432                 irte.present = 1;
1433                 irte.dst_mode = apic->irq_dest_mode;
1434                 /*
1435                  * Trigger mode in the IRTE will always be edge, and the
1436                  * actual level or edge trigger will be setup in the IO-APIC
1437                  * RTE. This will help simplify level triggered irq migration.
1438                  * For more details, see the comments above explainig IO-APIC
1439                  * irq migration in the presence of interrupt-remapping.
1440                  */
1441                 irte.trigger_mode = 0;
1442                 irte.dlvry_mode = apic->irq_delivery_mode;
1443                 irte.vector = vector;
1444                 irte.dest_id = IRTE_DEST(destination);
1445
1446                 modify_irte(irq, &irte);
1447
1448                 ir_entry->index2 = (index >> 15) & 0x1;
1449                 ir_entry->zero = 0;
1450                 ir_entry->format = 1;
1451                 ir_entry->index = (index & 0x7fff);
1452                 /*
1453                  * IO-APIC RTE will be configured with virtual vector.
1454                  * irq handler will do the explicit EOI to the io-apic.
1455                  */
1456                 ir_entry->vector = pin;
1457         } else {
1458                 entry->delivery_mode = apic->irq_delivery_mode;
1459                 entry->dest_mode = apic->irq_dest_mode;
1460                 entry->dest = destination;
1461                 entry->vector = vector;
1462         }
1463
1464         entry->mask = 0;                                /* enable IRQ */
1465         entry->trigger = trigger;
1466         entry->polarity = polarity;
1467
1468         /* Mask level triggered irqs.
1469          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1470          */
1471         if (trigger)
1472                 entry->mask = 1;
1473         return 0;
1474 }
1475
1476 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1477                               int trigger, int polarity)
1478 {
1479         struct irq_cfg *cfg;
1480         struct IO_APIC_route_entry entry;
1481         unsigned int dest;
1482
1483         if (!IO_APIC_IRQ(irq))
1484                 return;
1485
1486         cfg = desc->chip_data;
1487
1488         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1489                 return;
1490
1491         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1492
1493         apic_printk(APIC_VERBOSE,KERN_DEBUG
1494                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1495                     "IRQ %d Mode:%i Active:%i)\n",
1496                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1497                     irq, trigger, polarity);
1498
1499
1500         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1501                                dest, trigger, polarity, cfg->vector, pin)) {
1502                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1503                        mp_ioapics[apic_id].apicid, pin);
1504                 __clear_irq_vector(irq, cfg);
1505                 return;
1506         }
1507
1508         ioapic_register_intr(irq, desc, trigger);
1509         if (irq < NR_IRQS_LEGACY)
1510                 disable_8259A_irq(irq);
1511
1512         ioapic_write_entry(apic_id, pin, entry);
1513 }
1514
1515 static void __init setup_IO_APIC_irqs(void)
1516 {
1517         int apic_id, pin, idx, irq;
1518         int notcon = 0;
1519         struct irq_desc *desc;
1520         struct irq_cfg *cfg;
1521         int cpu = boot_cpu_id;
1522
1523         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1524
1525         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1526                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1527
1528                         idx = find_irq_entry(apic_id, pin, mp_INT);
1529                         if (idx == -1) {
1530                                 if (!notcon) {
1531                                         notcon = 1;
1532                                         apic_printk(APIC_VERBOSE,
1533                                                 KERN_DEBUG " %d-%d",
1534                                                 mp_ioapics[apic_id].apicid, pin);
1535                                 } else
1536                                         apic_printk(APIC_VERBOSE, " %d-%d",
1537                                                 mp_ioapics[apic_id].apicid, pin);
1538                                 continue;
1539                         }
1540                         if (notcon) {
1541                                 apic_printk(APIC_VERBOSE,
1542                                         " (apicid-pin) not connected\n");
1543                                 notcon = 0;
1544                         }
1545
1546                         irq = pin_2_irq(idx, apic_id, pin);
1547
1548                         /*
1549                          * Skip the timer IRQ if there's a quirk handler
1550                          * installed and if it returns 1:
1551                          */
1552                         if (apic->multi_timer_check &&
1553                                         apic->multi_timer_check(apic_id, irq))
1554                                 continue;
1555
1556                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1557                         if (!desc) {
1558                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1559                                 continue;
1560                         }
1561                         cfg = desc->chip_data;
1562                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1563
1564                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1565                                         irq_trigger(idx), irq_polarity(idx));
1566                 }
1567         }
1568
1569         if (notcon)
1570                 apic_printk(APIC_VERBOSE,
1571                         " (apicid-pin) not connected\n");
1572 }
1573
1574 /*
1575  * Set up the timer pin, possibly with the 8259A-master behind.
1576  */
1577 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1578                                         int vector)
1579 {
1580         struct IO_APIC_route_entry entry;
1581
1582         if (intr_remapping_enabled)
1583                 return;
1584
1585         memset(&entry, 0, sizeof(entry));
1586
1587         /*
1588          * We use logical delivery to get the timer IRQ
1589          * to the first CPU.
1590          */
1591         entry.dest_mode = apic->irq_dest_mode;
1592         entry.mask = 0;                 /* don't mask IRQ for edge */
1593         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1594         entry.delivery_mode = apic->irq_delivery_mode;
1595         entry.polarity = 0;
1596         entry.trigger = 0;
1597         entry.vector = vector;
1598
1599         /*
1600          * The timer IRQ doesn't have to know that behind the
1601          * scene we may have a 8259A-master in AEOI mode ...
1602          */
1603         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1604
1605         /*
1606          * Add it to the IO-APIC irq-routing table:
1607          */
1608         ioapic_write_entry(apic_id, pin, entry);
1609 }
1610
1611
1612 __apicdebuginit(void) print_IO_APIC(void)
1613 {
1614         int apic, i;
1615         union IO_APIC_reg_00 reg_00;
1616         union IO_APIC_reg_01 reg_01;
1617         union IO_APIC_reg_02 reg_02;
1618         union IO_APIC_reg_03 reg_03;
1619         unsigned long flags;
1620         struct irq_cfg *cfg;
1621         struct irq_desc *desc;
1622         unsigned int irq;
1623
1624         if (apic_verbosity == APIC_QUIET)
1625                 return;
1626
1627         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1628         for (i = 0; i < nr_ioapics; i++)
1629                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1630                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1631
1632         /*
1633          * We are a bit conservative about what we expect.  We have to
1634          * know about every hardware change ASAP.
1635          */
1636         printk(KERN_INFO "testing the IO APIC.......................\n");
1637
1638         for (apic = 0; apic < nr_ioapics; apic++) {
1639
1640         spin_lock_irqsave(&ioapic_lock, flags);
1641         reg_00.raw = io_apic_read(apic, 0);
1642         reg_01.raw = io_apic_read(apic, 1);
1643         if (reg_01.bits.version >= 0x10)
1644                 reg_02.raw = io_apic_read(apic, 2);
1645         if (reg_01.bits.version >= 0x20)
1646                 reg_03.raw = io_apic_read(apic, 3);
1647         spin_unlock_irqrestore(&ioapic_lock, flags);
1648
1649         printk("\n");
1650         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1651         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1652         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1653         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1654         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1655
1656         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1657         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1658
1659         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1660         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1661
1662         /*
1663          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1664          * but the value of reg_02 is read as the previous read register
1665          * value, so ignore it if reg_02 == reg_01.
1666          */
1667         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1668                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1669                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1670         }
1671
1672         /*
1673          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1674          * or reg_03, but the value of reg_0[23] is read as the previous read
1675          * register value, so ignore it if reg_03 == reg_0[12].
1676          */
1677         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1678             reg_03.raw != reg_01.raw) {
1679                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1680                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1681         }
1682
1683         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1684
1685         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1686                           " Stat Dmod Deli Vect:   \n");
1687
1688         for (i = 0; i <= reg_01.bits.entries; i++) {
1689                 struct IO_APIC_route_entry entry;
1690
1691                 entry = ioapic_read_entry(apic, i);
1692
1693                 printk(KERN_DEBUG " %02x %03X ",
1694                         i,
1695                         entry.dest
1696                 );
1697
1698                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1699                         entry.mask,
1700                         entry.trigger,
1701                         entry.irr,
1702                         entry.polarity,
1703                         entry.delivery_status,
1704                         entry.dest_mode,
1705                         entry.delivery_mode,
1706                         entry.vector
1707                 );
1708         }
1709         }
1710         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1711         for_each_irq_desc(irq, desc) {
1712                 struct irq_pin_list *entry;
1713
1714                 cfg = desc->chip_data;
1715                 entry = cfg->irq_2_pin;
1716                 if (!entry)
1717                         continue;
1718                 printk(KERN_DEBUG "IRQ%d ", irq);
1719                 for (;;) {
1720                         printk("-> %d:%d", entry->apic, entry->pin);
1721                         if (!entry->next)
1722                                 break;
1723                         entry = entry->next;
1724                 }
1725                 printk("\n");
1726         }
1727
1728         printk(KERN_INFO ".................................... done.\n");
1729
1730         return;
1731 }
1732
1733 __apicdebuginit(void) print_APIC_bitfield(int base)
1734 {
1735         unsigned int v;
1736         int i, j;
1737
1738         if (apic_verbosity == APIC_QUIET)
1739                 return;
1740
1741         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1742         for (i = 0; i < 8; i++) {
1743                 v = apic_read(base + i*0x10);
1744                 for (j = 0; j < 32; j++) {
1745                         if (v & (1<<j))
1746                                 printk("1");
1747                         else
1748                                 printk("0");
1749                 }
1750                 printk("\n");
1751         }
1752 }
1753
1754 __apicdebuginit(void) print_local_APIC(void *dummy)
1755 {
1756         unsigned int v, ver, maxlvt;
1757         u64 icr;
1758
1759         if (apic_verbosity == APIC_QUIET)
1760                 return;
1761
1762         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1763                 smp_processor_id(), hard_smp_processor_id());
1764         v = apic_read(APIC_ID);
1765         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1766         v = apic_read(APIC_LVR);
1767         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1768         ver = GET_APIC_VERSION(v);
1769         maxlvt = lapic_get_maxlvt();
1770
1771         v = apic_read(APIC_TASKPRI);
1772         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1773
1774         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1775                 if (!APIC_XAPIC(ver)) {
1776                         v = apic_read(APIC_ARBPRI);
1777                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1778                                v & APIC_ARBPRI_MASK);
1779                 }
1780                 v = apic_read(APIC_PROCPRI);
1781                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1782         }
1783
1784         /*
1785          * Remote read supported only in the 82489DX and local APIC for
1786          * Pentium processors.
1787          */
1788         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1789                 v = apic_read(APIC_RRR);
1790                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1791         }
1792
1793         v = apic_read(APIC_LDR);
1794         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1795         if (!x2apic_enabled()) {
1796                 v = apic_read(APIC_DFR);
1797                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1798         }
1799         v = apic_read(APIC_SPIV);
1800         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1801
1802         printk(KERN_DEBUG "... APIC ISR field:\n");
1803         print_APIC_bitfield(APIC_ISR);
1804         printk(KERN_DEBUG "... APIC TMR field:\n");
1805         print_APIC_bitfield(APIC_TMR);
1806         printk(KERN_DEBUG "... APIC IRR field:\n");
1807         print_APIC_bitfield(APIC_IRR);
1808
1809         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1810                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1811                         apic_write(APIC_ESR, 0);
1812
1813                 v = apic_read(APIC_ESR);
1814                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1815         }
1816
1817         icr = apic_icr_read();
1818         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1819         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1820
1821         v = apic_read(APIC_LVTT);
1822         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1823
1824         if (maxlvt > 3) {                       /* PC is LVT#4. */
1825                 v = apic_read(APIC_LVTPC);
1826                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1827         }
1828         v = apic_read(APIC_LVT0);
1829         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1830         v = apic_read(APIC_LVT1);
1831         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1832
1833         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1834                 v = apic_read(APIC_LVTERR);
1835                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1836         }
1837
1838         v = apic_read(APIC_TMICT);
1839         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1840         v = apic_read(APIC_TMCCT);
1841         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1842         v = apic_read(APIC_TDCR);
1843         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1844         printk("\n");
1845 }
1846
1847 __apicdebuginit(void) print_all_local_APICs(void)
1848 {
1849         int cpu;
1850
1851         preempt_disable();
1852         for_each_online_cpu(cpu)
1853                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1854         preempt_enable();
1855 }
1856
1857 __apicdebuginit(void) print_PIC(void)
1858 {
1859         unsigned int v;
1860         unsigned long flags;
1861
1862         if (apic_verbosity == APIC_QUIET)
1863                 return;
1864
1865         printk(KERN_DEBUG "\nprinting PIC contents\n");
1866
1867         spin_lock_irqsave(&i8259A_lock, flags);
1868
1869         v = inb(0xa1) << 8 | inb(0x21);
1870         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1871
1872         v = inb(0xa0) << 8 | inb(0x20);
1873         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1874
1875         outb(0x0b,0xa0);
1876         outb(0x0b,0x20);
1877         v = inb(0xa0) << 8 | inb(0x20);
1878         outb(0x0a,0xa0);
1879         outb(0x0a,0x20);
1880
1881         spin_unlock_irqrestore(&i8259A_lock, flags);
1882
1883         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1884
1885         v = inb(0x4d1) << 8 | inb(0x4d0);
1886         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1887 }
1888
1889 __apicdebuginit(int) print_all_ICs(void)
1890 {
1891         print_PIC();
1892         print_all_local_APICs();
1893         print_IO_APIC();
1894
1895         return 0;
1896 }
1897
1898 fs_initcall(print_all_ICs);
1899
1900
1901 /* Where if anywhere is the i8259 connect in external int mode */
1902 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1903
1904 void __init enable_IO_APIC(void)
1905 {
1906         union IO_APIC_reg_01 reg_01;
1907         int i8259_apic, i8259_pin;
1908         int apic;
1909         unsigned long flags;
1910
1911         /*
1912          * The number of IO-APIC IRQ registers (== #pins):
1913          */
1914         for (apic = 0; apic < nr_ioapics; apic++) {
1915                 spin_lock_irqsave(&ioapic_lock, flags);
1916                 reg_01.raw = io_apic_read(apic, 1);
1917                 spin_unlock_irqrestore(&ioapic_lock, flags);
1918                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1919         }
1920         for(apic = 0; apic < nr_ioapics; apic++) {
1921                 int pin;
1922                 /* See if any of the pins is in ExtINT mode */
1923                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1924                         struct IO_APIC_route_entry entry;
1925                         entry = ioapic_read_entry(apic, pin);
1926
1927                         /* If the interrupt line is enabled and in ExtInt mode
1928                          * I have found the pin where the i8259 is connected.
1929                          */
1930                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1931                                 ioapic_i8259.apic = apic;
1932                                 ioapic_i8259.pin  = pin;
1933                                 goto found_i8259;
1934                         }
1935                 }
1936         }
1937  found_i8259:
1938         /* Look to see what if the MP table has reported the ExtINT */
1939         /* If we could not find the appropriate pin by looking at the ioapic
1940          * the i8259 probably is not connected the ioapic but give the
1941          * mptable a chance anyway.
1942          */
1943         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1944         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1945         /* Trust the MP table if nothing is setup in the hardware */
1946         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1947                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1948                 ioapic_i8259.pin  = i8259_pin;
1949                 ioapic_i8259.apic = i8259_apic;
1950         }
1951         /* Complain if the MP table and the hardware disagree */
1952         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1953                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1954         {
1955                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1956         }
1957
1958         /*
1959          * Do not trust the IO-APIC being empty at bootup
1960          */
1961         clear_IO_APIC();
1962 }
1963
1964 /*
1965  * Not an __init, needed by the reboot code
1966  */
1967 void disable_IO_APIC(void)
1968 {
1969         /*
1970          * Clear the IO-APIC before rebooting:
1971          */
1972         clear_IO_APIC();
1973
1974         /*
1975          * If the i8259 is routed through an IOAPIC
1976          * Put that IOAPIC in virtual wire mode
1977          * so legacy interrupts can be delivered.
1978          *
1979          * With interrupt-remapping, for now we will use virtual wire A mode,
1980          * as virtual wire B is little complex (need to configure both
1981          * IOAPIC RTE aswell as interrupt-remapping table entry).
1982          * As this gets called during crash dump, keep this simple for now.
1983          */
1984         if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1985                 struct IO_APIC_route_entry entry;
1986
1987                 memset(&entry, 0, sizeof(entry));
1988                 entry.mask            = 0; /* Enabled */
1989                 entry.trigger         = 0; /* Edge */
1990                 entry.irr             = 0;
1991                 entry.polarity        = 0; /* High */
1992                 entry.delivery_status = 0;
1993                 entry.dest_mode       = 0; /* Physical */
1994                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1995                 entry.vector          = 0;
1996                 entry.dest            = read_apic_id();
1997
1998                 /*
1999                  * Add it to the IO-APIC irq-routing table:
2000                  */
2001                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2002         }
2003
2004         /*
2005          * Use virtual wire A mode when interrupt remapping is enabled.
2006          */
2007         disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2008 }
2009
2010 #ifdef CONFIG_X86_32
2011 /*
2012  * function to set the IO-APIC physical IDs based on the
2013  * values stored in the MPC table.
2014  *
2015  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2016  */
2017
2018 static void __init setup_ioapic_ids_from_mpc(void)
2019 {
2020         union IO_APIC_reg_00 reg_00;
2021         physid_mask_t phys_id_present_map;
2022         int apic_id;
2023         int i;
2024         unsigned char old_id;
2025         unsigned long flags;
2026
2027         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2028                 return;
2029
2030         /*
2031          * Don't check I/O APIC IDs for xAPIC systems.  They have
2032          * no meaning without the serial APIC bus.
2033          */
2034         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2035                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2036                 return;
2037         /*
2038          * This is broken; anything with a real cpu count has to
2039          * circumvent this idiocy regardless.
2040          */
2041         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2042
2043         /*
2044          * Set the IOAPIC ID to the value stored in the MPC table.
2045          */
2046         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2047
2048                 /* Read the register 0 value */
2049                 spin_lock_irqsave(&ioapic_lock, flags);
2050                 reg_00.raw = io_apic_read(apic_id, 0);
2051                 spin_unlock_irqrestore(&ioapic_lock, flags);
2052
2053                 old_id = mp_ioapics[apic_id].apicid;
2054
2055                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2056                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2057                                 apic_id, mp_ioapics[apic_id].apicid);
2058                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2059                                 reg_00.bits.ID);
2060                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2061                 }
2062
2063                 /*
2064                  * Sanity check, is the ID really free? Every APIC in a
2065                  * system must have a unique ID or we get lots of nice
2066                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2067                  */
2068                 if (apic->check_apicid_used(phys_id_present_map,
2069                                         mp_ioapics[apic_id].apicid)) {
2070                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2071                                 apic_id, mp_ioapics[apic_id].apicid);
2072                         for (i = 0; i < get_physical_broadcast(); i++)
2073                                 if (!physid_isset(i, phys_id_present_map))
2074                                         break;
2075                         if (i >= get_physical_broadcast())
2076                                 panic("Max APIC ID exceeded!\n");
2077                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2078                                 i);
2079                         physid_set(i, phys_id_present_map);
2080                         mp_ioapics[apic_id].apicid = i;
2081                 } else {
2082                         physid_mask_t tmp;
2083                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2084                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2085                                         "phys_id_present_map\n",
2086                                         mp_ioapics[apic_id].apicid);
2087                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2088                 }
2089
2090
2091                 /*
2092                  * We need to adjust the IRQ routing table
2093                  * if the ID changed.
2094                  */
2095                 if (old_id != mp_ioapics[apic_id].apicid)
2096                         for (i = 0; i < mp_irq_entries; i++)
2097                                 if (mp_irqs[i].dstapic == old_id)
2098                                         mp_irqs[i].dstapic
2099                                                 = mp_ioapics[apic_id].apicid;
2100
2101                 /*
2102                  * Read the right value from the MPC table and
2103                  * write it into the ID register.
2104                  */
2105                 apic_printk(APIC_VERBOSE, KERN_INFO
2106                         "...changing IO-APIC physical APIC ID to %d ...",
2107                         mp_ioapics[apic_id].apicid);
2108
2109                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2110                 spin_lock_irqsave(&ioapic_lock, flags);
2111                 io_apic_write(apic_id, 0, reg_00.raw);
2112                 spin_unlock_irqrestore(&ioapic_lock, flags);
2113
2114                 /*
2115                  * Sanity check
2116                  */
2117                 spin_lock_irqsave(&ioapic_lock, flags);
2118                 reg_00.raw = io_apic_read(apic_id, 0);
2119                 spin_unlock_irqrestore(&ioapic_lock, flags);
2120                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2121                         printk("could not set ID!\n");
2122                 else
2123                         apic_printk(APIC_VERBOSE, " ok.\n");
2124         }
2125 }
2126 #endif
2127
2128 int no_timer_check __initdata;
2129
2130 static int __init notimercheck(char *s)
2131 {
2132         no_timer_check = 1;
2133         return 1;
2134 }
2135 __setup("no_timer_check", notimercheck);
2136
2137 /*
2138  * There is a nasty bug in some older SMP boards, their mptable lies
2139  * about the timer IRQ. We do the following to work around the situation:
2140  *
2141  *      - timer IRQ defaults to IO-APIC IRQ
2142  *      - if this function detects that timer IRQs are defunct, then we fall
2143  *        back to ISA timer IRQs
2144  */
2145 static int __init timer_irq_works(void)
2146 {
2147         unsigned long t1 = jiffies;
2148         unsigned long flags;
2149
2150         if (no_timer_check)
2151                 return 1;
2152
2153         local_save_flags(flags);
2154         local_irq_enable();
2155         /* Let ten ticks pass... */
2156         mdelay((10 * 1000) / HZ);
2157         local_irq_restore(flags);
2158
2159         /*
2160          * Expect a few ticks at least, to be sure some possible
2161          * glue logic does not lock up after one or two first
2162          * ticks in a non-ExtINT mode.  Also the local APIC
2163          * might have cached one ExtINT interrupt.  Finally, at
2164          * least one tick may be lost due to delays.
2165          */
2166
2167         /* jiffies wrap? */
2168         if (time_after(jiffies, t1 + 4))
2169                 return 1;
2170         return 0;
2171 }
2172
2173 /*
2174  * In the SMP+IOAPIC case it might happen that there are an unspecified
2175  * number of pending IRQ events unhandled. These cases are very rare,
2176  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2177  * better to do it this way as thus we do not have to be aware of
2178  * 'pending' interrupts in the IRQ path, except at this point.
2179  */
2180 /*
2181  * Edge triggered needs to resend any interrupt
2182  * that was delayed but this is now handled in the device
2183  * independent code.
2184  */
2185
2186 /*
2187  * Starting up a edge-triggered IO-APIC interrupt is
2188  * nasty - we need to make sure that we get the edge.
2189  * If it is already asserted for some reason, we need
2190  * return 1 to indicate that is was pending.
2191  *
2192  * This is not complete - we should be able to fake
2193  * an edge even if it isn't on the 8259A...
2194  */
2195
2196 static unsigned int startup_ioapic_irq(unsigned int irq)
2197 {
2198         int was_pending = 0;
2199         unsigned long flags;
2200         struct irq_cfg *cfg;
2201
2202         spin_lock_irqsave(&ioapic_lock, flags);
2203         if (irq < NR_IRQS_LEGACY) {
2204                 disable_8259A_irq(irq);
2205                 if (i8259A_irq_pending(irq))
2206                         was_pending = 1;
2207         }
2208         cfg = irq_cfg(irq);
2209         __unmask_IO_APIC_irq(cfg);
2210         spin_unlock_irqrestore(&ioapic_lock, flags);
2211
2212         return was_pending;
2213 }
2214
2215 #ifdef CONFIG_X86_64
2216 static int ioapic_retrigger_irq(unsigned int irq)
2217 {
2218
2219         struct irq_cfg *cfg = irq_cfg(irq);
2220         unsigned long flags;
2221
2222         spin_lock_irqsave(&vector_lock, flags);
2223         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2224         spin_unlock_irqrestore(&vector_lock, flags);
2225
2226         return 1;
2227 }
2228 #else
2229 static int ioapic_retrigger_irq(unsigned int irq)
2230 {
2231         apic->send_IPI_self(irq_cfg(irq)->vector);
2232
2233         return 1;
2234 }
2235 #endif
2236
2237 /*
2238  * Level and edge triggered IO-APIC interrupts need different handling,
2239  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2240  * handled with the level-triggered descriptor, but that one has slightly
2241  * more overhead. Level-triggered interrupts cannot be handled with the
2242  * edge-triggered handler, without risking IRQ storms and other ugly
2243  * races.
2244  */
2245
2246 #ifdef CONFIG_SMP
2247 static void send_cleanup_vector(struct irq_cfg *cfg)
2248 {
2249         cpumask_var_t cleanup_mask;
2250
2251         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2252                 unsigned int i;
2253                 cfg->move_cleanup_count = 0;
2254                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2255                         cfg->move_cleanup_count++;
2256                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2257                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2258         } else {
2259                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2260                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2261                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2262                 free_cpumask_var(cleanup_mask);
2263         }
2264         cfg->move_in_progress = 0;
2265 }
2266
2267 static void
2268 __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2269 {
2270         int apic, pin;
2271         struct irq_pin_list *entry;
2272         u8 vector = cfg->vector;
2273
2274         entry = cfg->irq_2_pin;
2275         for (;;) {
2276                 unsigned int reg;
2277
2278                 if (!entry)
2279                         break;
2280
2281                 apic = entry->apic;
2282                 pin = entry->pin;
2283                 /*
2284                  * With interrupt-remapping, destination information comes
2285                  * from interrupt-remapping table entry.
2286                  */
2287                 if (!irq_remapped(irq))
2288                         io_apic_write(apic, 0x11 + pin*2, dest);
2289                 reg = io_apic_read(apic, 0x10 + pin*2);
2290                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2291                 reg |= vector;
2292                 io_apic_modify(apic, 0x10 + pin*2, reg);
2293                 if (!entry->next)
2294                         break;
2295                 entry = entry->next;
2296         }
2297 }
2298
2299 /*
2300  * Either sets desc->affinity to a valid value, and returns
2301  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2302  * leaves desc->affinity untouched.
2303  */
2304 static unsigned int
2305 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2306 {
2307         struct irq_cfg *cfg;
2308         unsigned int irq;
2309
2310         if (!cpumask_intersects(mask, cpu_online_mask))
2311                 return BAD_APICID;
2312
2313         irq = desc->irq;
2314         cfg = desc->chip_data;
2315         if (assign_irq_vector(irq, cfg, mask))
2316                 return BAD_APICID;
2317
2318         /* check that before desc->addinity get updated */
2319         set_extra_move_desc(desc, mask);
2320
2321         cpumask_copy(desc->affinity, mask);
2322
2323         return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2324 }
2325
2326 static void
2327 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2328 {
2329         struct irq_cfg *cfg;
2330         unsigned long flags;
2331         unsigned int dest;
2332         unsigned int irq;
2333
2334         irq = desc->irq;
2335         cfg = desc->chip_data;
2336
2337         spin_lock_irqsave(&ioapic_lock, flags);
2338         dest = set_desc_affinity(desc, mask);
2339         if (dest != BAD_APICID) {
2340                 /* Only the high 8 bits are valid. */
2341                 dest = SET_APIC_LOGICAL_ID(dest);
2342                 __target_IO_APIC_irq(irq, dest, cfg);
2343         }
2344         spin_unlock_irqrestore(&ioapic_lock, flags);
2345 }
2346
2347 static void
2348 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2349 {
2350         struct irq_desc *desc;
2351
2352         desc = irq_to_desc(irq);
2353
2354         set_ioapic_affinity_irq_desc(desc, mask);
2355 }
2356
2357 #ifdef CONFIG_INTR_REMAP
2358
2359 /*
2360  * Migrate the IO-APIC irq in the presence of intr-remapping.
2361  *
2362  * For both level and edge triggered, irq migration is a simple atomic
2363  * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2364  *
2365  * For level triggered, we eliminate the io-apic RTE modification (with the
2366  * updated vector information), by using a virtual vector (io-apic pin number).
2367  * Real vector that is used for interrupting cpu will be coming from
2368  * the interrupt-remapping table entry.
2369  */
2370 static void
2371 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2372 {
2373         struct irq_cfg *cfg;
2374         struct irte irte;
2375         unsigned int dest;
2376         unsigned int irq;
2377
2378         if (!cpumask_intersects(mask, cpu_online_mask))
2379                 return;
2380
2381         irq = desc->irq;
2382         if (get_irte(irq, &irte))
2383                 return;
2384
2385         cfg = desc->chip_data;
2386         if (assign_irq_vector(irq, cfg, mask))
2387                 return;
2388
2389         set_extra_move_desc(desc, mask);
2390
2391         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2392
2393         irte.vector = cfg->vector;
2394         irte.dest_id = IRTE_DEST(dest);
2395
2396         /*
2397          * Modified the IRTE and flushes the Interrupt entry cache.
2398          */
2399         modify_irte(irq, &irte);
2400
2401         if (cfg->move_in_progress)
2402                 send_cleanup_vector(cfg);
2403
2404         cpumask_copy(desc->affinity, mask);
2405 }
2406
2407 /*
2408  * Migrates the IRQ destination in the process context.
2409  */
2410 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2411                                             const struct cpumask *mask)
2412 {
2413         migrate_ioapic_irq_desc(desc, mask);
2414 }
2415 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2416                                        const struct cpumask *mask)
2417 {
2418         struct irq_desc *desc = irq_to_desc(irq);
2419
2420         set_ir_ioapic_affinity_irq_desc(desc, mask);
2421 }
2422 #else
2423 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2424                                                    const struct cpumask *mask)
2425 {
2426 }
2427 #endif
2428
2429 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2430 {
2431         unsigned vector, me;
2432
2433         ack_APIC_irq();
2434         exit_idle();
2435         irq_enter();
2436
2437         me = smp_processor_id();
2438         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2439                 unsigned int irq;
2440                 unsigned int irr;
2441                 struct irq_desc *desc;
2442                 struct irq_cfg *cfg;
2443                 irq = __get_cpu_var(vector_irq)[vector];
2444
2445                 if (irq == -1)
2446                         continue;
2447
2448                 desc = irq_to_desc(irq);
2449                 if (!desc)
2450                         continue;
2451
2452                 cfg = irq_cfg(irq);
2453                 spin_lock(&desc->lock);
2454                 if (!cfg->move_cleanup_count)
2455                         goto unlock;
2456
2457                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2458                         goto unlock;
2459
2460                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2461                 /*
2462                  * Check if the vector that needs to be cleanedup is
2463                  * registered at the cpu's IRR. If so, then this is not
2464                  * the best time to clean it up. Lets clean it up in the
2465                  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2466                  * to myself.
2467                  */
2468                 if (irr  & (1 << (vector % 32))) {
2469                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2470                         goto unlock;
2471                 }
2472                 __get_cpu_var(vector_irq)[vector] = -1;
2473                 cfg->move_cleanup_count--;
2474 unlock:
2475                 spin_unlock(&desc->lock);
2476         }
2477
2478         irq_exit();
2479 }
2480
2481 static void irq_complete_move(struct irq_desc **descp)
2482 {
2483         struct irq_desc *desc = *descp;
2484         struct irq_cfg *cfg = desc->chip_data;
2485         unsigned vector, me;
2486
2487         if (likely(!cfg->move_in_progress)) {
2488 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2489                 if (likely(!cfg->move_desc_pending))
2490                         return;
2491
2492                 /* domain has not changed, but affinity did */
2493                 me = smp_processor_id();
2494                 if (cpumask_test_cpu(me, desc->affinity)) {
2495                         *descp = desc = move_irq_desc(desc, me);
2496                         /* get the new one */
2497                         cfg = desc->chip_data;
2498                         cfg->move_desc_pending = 0;
2499                 }
2500 #endif
2501                 return;
2502         }
2503
2504         vector = ~get_irq_regs()->orig_ax;
2505         me = smp_processor_id();
2506
2507         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2508 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2509                 *descp = desc = move_irq_desc(desc, me);
2510                 /* get the new one */
2511                 cfg = desc->chip_data;
2512 #endif
2513                 send_cleanup_vector(cfg);
2514         }
2515 }
2516 #else
2517 static inline void irq_complete_move(struct irq_desc **descp) {}
2518 #endif
2519
2520 static void ack_apic_edge(unsigned int irq)
2521 {
2522         struct irq_desc *desc = irq_to_desc(irq);
2523
2524         irq_complete_move(&desc);
2525         move_native_irq(irq);
2526         ack_APIC_irq();
2527 }
2528
2529 atomic_t irq_mis_count;
2530
2531 static void ack_apic_level(unsigned int irq)
2532 {
2533         struct irq_desc *desc = irq_to_desc(irq);
2534
2535 #ifdef CONFIG_X86_32
2536         unsigned long v;
2537         int i;
2538 #endif
2539         struct irq_cfg *cfg;
2540         int do_unmask_irq = 0;
2541
2542         irq_complete_move(&desc);
2543 #ifdef CONFIG_GENERIC_PENDING_IRQ
2544         /* If we are moving the irq we need to mask it */
2545         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2546                 do_unmask_irq = 1;
2547                 mask_IO_APIC_irq_desc(desc);
2548         }
2549 #endif
2550
2551 #ifdef CONFIG_X86_32
2552         /*
2553         * It appears there is an erratum which affects at least version 0x11
2554         * of I/O APIC (that's the 82093AA and cores integrated into various
2555         * chipsets).  Under certain conditions a level-triggered interrupt is
2556         * erroneously delivered as edge-triggered one but the respective IRR
2557         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2558         * message but it will never arrive and further interrupts are blocked
2559         * from the source.  The exact reason is so far unknown, but the
2560         * phenomenon was observed when two consecutive interrupt requests
2561         * from a given source get delivered to the same CPU and the source is
2562         * temporarily disabled in between.
2563         *
2564         * A workaround is to simulate an EOI message manually.  We achieve it
2565         * by setting the trigger mode to edge and then to level when the edge
2566         * trigger mode gets detected in the TMR of a local APIC for a
2567         * level-triggered interrupt.  We mask the source for the time of the
2568         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2569         * The idea is from Manfred Spraul.  --macro
2570         */
2571         cfg = desc->chip_data;
2572         i = cfg->vector;
2573
2574         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2575 #endif
2576
2577         /*
2578          * We must acknowledge the irq before we move it or the acknowledge will
2579          * not propagate properly.
2580          */
2581         ack_APIC_irq();
2582
2583         /* Now we can move and renable the irq */
2584         if (unlikely(do_unmask_irq)) {
2585                 /* Only migrate the irq if the ack has been received.
2586                  *
2587                  * On rare occasions the broadcast level triggered ack gets
2588                  * delayed going to ioapics, and if we reprogram the
2589                  * vector while Remote IRR is still set the irq will never
2590                  * fire again.
2591                  *
2592                  * To prevent this scenario we read the Remote IRR bit
2593                  * of the ioapic.  This has two effects.
2594                  * - On any sane system the read of the ioapic will
2595                  *   flush writes (and acks) going to the ioapic from
2596                  *   this cpu.
2597                  * - We get to see if the ACK has actually been delivered.
2598                  *
2599                  * Based on failed experiments of reprogramming the
2600                  * ioapic entry from outside of irq context starting
2601                  * with masking the ioapic entry and then polling until
2602                  * Remote IRR was clear before reprogramming the
2603                  * ioapic I don't trust the Remote IRR bit to be
2604                  * completey accurate.
2605                  *
2606                  * However there appears to be no other way to plug
2607                  * this race, so if the Remote IRR bit is not
2608                  * accurate and is causing problems then it is a hardware bug
2609                  * and you can go talk to the chipset vendor about it.
2610                  */
2611                 cfg = desc->chip_data;
2612                 if (!io_apic_level_ack_pending(cfg))
2613                         move_masked_irq(irq);
2614                 unmask_IO_APIC_irq_desc(desc);
2615         }
2616
2617 #ifdef CONFIG_X86_32
2618         if (!(v & (1 << (i & 0x1f)))) {
2619                 atomic_inc(&irq_mis_count);
2620                 spin_lock(&ioapic_lock);
2621                 __mask_and_edge_IO_APIC_irq(cfg);
2622                 __unmask_and_level_IO_APIC_irq(cfg);
2623                 spin_unlock(&ioapic_lock);
2624         }
2625 #endif
2626 }
2627
2628 #ifdef CONFIG_INTR_REMAP
2629 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2630 {
2631         int apic, pin;
2632         struct irq_pin_list *entry;
2633
2634         entry = cfg->irq_2_pin;
2635         for (;;) {
2636
2637                 if (!entry)
2638                         break;
2639
2640                 apic = entry->apic;
2641                 pin = entry->pin;
2642                 io_apic_eoi(apic, pin);
2643                 entry = entry->next;
2644         }
2645 }
2646
2647 static void
2648 eoi_ioapic_irq(struct irq_desc *desc)
2649 {
2650         struct irq_cfg *cfg;
2651         unsigned long flags;
2652         unsigned int irq;
2653
2654         irq = desc->irq;
2655         cfg = desc->chip_data;
2656
2657         spin_lock_irqsave(&ioapic_lock, flags);
2658         __eoi_ioapic_irq(irq, cfg);
2659         spin_unlock_irqrestore(&ioapic_lock, flags);
2660 }
2661
2662 static void ir_ack_apic_edge(unsigned int irq)
2663 {
2664         ack_APIC_irq();
2665 }
2666
2667 static void ir_ack_apic_level(unsigned int irq)
2668 {
2669         struct irq_desc *desc = irq_to_desc(irq);
2670
2671         ack_APIC_irq();
2672         eoi_ioapic_irq(desc);
2673 }
2674 #endif /* CONFIG_INTR_REMAP */
2675
2676 static struct irq_chip ioapic_chip __read_mostly = {
2677         .name           = "IO-APIC",
2678         .startup        = startup_ioapic_irq,
2679         .mask           = mask_IO_APIC_irq,
2680         .unmask         = unmask_IO_APIC_irq,
2681         .ack            = ack_apic_edge,
2682         .eoi            = ack_apic_level,
2683 #ifdef CONFIG_SMP
2684         .set_affinity   = set_ioapic_affinity_irq,
2685 #endif
2686         .retrigger      = ioapic_retrigger_irq,
2687 };
2688
2689 static struct irq_chip ir_ioapic_chip __read_mostly = {
2690         .name           = "IR-IO-APIC",
2691         .startup        = startup_ioapic_irq,
2692         .mask           = mask_IO_APIC_irq,
2693         .unmask         = unmask_IO_APIC_irq,
2694 #ifdef CONFIG_INTR_REMAP
2695         .ack            = ir_ack_apic_edge,
2696         .eoi            = ir_ack_apic_level,
2697 #ifdef CONFIG_SMP
2698         .set_affinity   = set_ir_ioapic_affinity_irq,
2699 #endif
2700 #endif
2701         .retrigger      = ioapic_retrigger_irq,
2702 };
2703
2704 static inline void init_IO_APIC_traps(void)
2705 {
2706         int irq;
2707         struct irq_desc *desc;
2708         struct irq_cfg *cfg;
2709
2710         /*
2711          * NOTE! The local APIC isn't very good at handling
2712          * multiple interrupts at the same interrupt level.
2713          * As the interrupt level is determined by taking the
2714          * vector number and shifting that right by 4, we
2715          * want to spread these out a bit so that they don't
2716          * all fall in the same interrupt level.
2717          *
2718          * Also, we've got to be careful not to trash gate
2719          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2720          */
2721         for_each_irq_desc(irq, desc) {
2722                 cfg = desc->chip_data;
2723                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2724                         /*
2725                          * Hmm.. We don't have an entry for this,
2726                          * so default to an old-fashioned 8259
2727                          * interrupt if we can..
2728                          */
2729                         if (irq < NR_IRQS_LEGACY)
2730                                 make_8259A_irq(irq);
2731                         else
2732                                 /* Strange. Oh, well.. */
2733                                 desc->chip = &no_irq_chip;
2734                 }
2735         }
2736 }
2737
2738 /*
2739  * The local APIC irq-chip implementation:
2740  */
2741
2742 static void mask_lapic_irq(unsigned int irq)
2743 {
2744         unsigned long v;
2745
2746         v = apic_read(APIC_LVT0);
2747         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2748 }
2749
2750 static void unmask_lapic_irq(unsigned int irq)
2751 {
2752         unsigned long v;
2753
2754         v = apic_read(APIC_LVT0);
2755         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2756 }
2757
2758 static void ack_lapic_irq(unsigned int irq)
2759 {
2760         ack_APIC_irq();
2761 }
2762
2763 static struct irq_chip lapic_chip __read_mostly = {
2764         .name           = "local-APIC",
2765         .mask           = mask_lapic_irq,
2766         .unmask         = unmask_lapic_irq,
2767         .ack            = ack_lapic_irq,
2768 };
2769
2770 static void lapic_register_intr(int irq, struct irq_desc *desc)
2771 {
2772         desc->status &= ~IRQ_LEVEL;
2773         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2774                                       "edge");
2775 }
2776
2777 static void __init setup_nmi(void)
2778 {
2779         /*
2780          * Dirty trick to enable the NMI watchdog ...
2781          * We put the 8259A master into AEOI mode and
2782          * unmask on all local APICs LVT0 as NMI.
2783          *
2784          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2785          * is from Maciej W. Rozycki - so we do not have to EOI from
2786          * the NMI handler or the timer interrupt.
2787          */
2788         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2789
2790         enable_NMI_through_LVT0();
2791
2792         apic_printk(APIC_VERBOSE, " done.\n");
2793 }
2794
2795 /*
2796  * This looks a bit hackish but it's about the only one way of sending
2797  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2798  * not support the ExtINT mode, unfortunately.  We need to send these
2799  * cycles as some i82489DX-based boards have glue logic that keeps the
2800  * 8259A interrupt line asserted until INTA.  --macro
2801  */
2802 static inline void __init unlock_ExtINT_logic(void)
2803 {
2804         int apic, pin, i;
2805         struct IO_APIC_route_entry entry0, entry1;
2806         unsigned char save_control, save_freq_select;
2807
2808         pin  = find_isa_irq_pin(8, mp_INT);
2809         if (pin == -1) {
2810                 WARN_ON_ONCE(1);
2811                 return;
2812         }
2813         apic = find_isa_irq_apic(8, mp_INT);
2814         if (apic == -1) {
2815                 WARN_ON_ONCE(1);
2816                 return;
2817         }
2818
2819         entry0 = ioapic_read_entry(apic, pin);
2820         clear_IO_APIC_pin(apic, pin);
2821
2822         memset(&entry1, 0, sizeof(entry1));
2823
2824         entry1.dest_mode = 0;                   /* physical delivery */
2825         entry1.mask = 0;                        /* unmask IRQ now */
2826         entry1.dest = hard_smp_processor_id();
2827         entry1.delivery_mode = dest_ExtINT;
2828         entry1.polarity = entry0.polarity;
2829         entry1.trigger = 0;
2830         entry1.vector = 0;
2831
2832         ioapic_write_entry(apic, pin, entry1);
2833
2834         save_control = CMOS_READ(RTC_CONTROL);
2835         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2836         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2837                    RTC_FREQ_SELECT);
2838         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2839
2840         i = 100;
2841         while (i-- > 0) {
2842                 mdelay(10);
2843                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2844                         i -= 10;
2845         }
2846
2847         CMOS_WRITE(save_control, RTC_CONTROL);
2848         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2849         clear_IO_APIC_pin(apic, pin);
2850
2851         ioapic_write_entry(apic, pin, entry0);
2852 }
2853
2854 static int disable_timer_pin_1 __initdata;
2855 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2856 static int __init disable_timer_pin_setup(char *arg)
2857 {
2858         disable_timer_pin_1 = 1;
2859         return 0;
2860 }
2861 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2862
2863 int timer_through_8259 __initdata;
2864
2865 /*
2866  * This code may look a bit paranoid, but it's supposed to cooperate with
2867  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2868  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2869  * fanatically on his truly buggy board.
2870  *
2871  * FIXME: really need to revamp this for all platforms.
2872  */
2873 static inline void __init check_timer(void)
2874 {
2875         struct irq_desc *desc = irq_to_desc(0);
2876         struct irq_cfg *cfg = desc->chip_data;
2877         int cpu = boot_cpu_id;
2878         int apic1, pin1, apic2, pin2;
2879         unsigned long flags;
2880         int no_pin1 = 0;
2881
2882         local_irq_save(flags);
2883
2884         /*
2885          * get/set the timer IRQ vector:
2886          */
2887         disable_8259A_irq(0);
2888         assign_irq_vector(0, cfg, apic->target_cpus());
2889
2890         /*
2891          * As IRQ0 is to be enabled in the 8259A, the virtual
2892          * wire has to be disabled in the local APIC.  Also
2893          * timer interrupts need to be acknowledged manually in
2894          * the 8259A for the i82489DX when using the NMI
2895          * watchdog as that APIC treats NMIs as level-triggered.
2896          * The AEOI mode will finish them in the 8259A
2897          * automatically.
2898          */
2899         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2900         init_8259A(1);
2901 #ifdef CONFIG_X86_32
2902         {
2903                 unsigned int ver;
2904
2905                 ver = apic_read(APIC_LVR);
2906                 ver = GET_APIC_VERSION(ver);
2907                 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2908         }
2909 #endif
2910
2911         pin1  = find_isa_irq_pin(0, mp_INT);
2912         apic1 = find_isa_irq_apic(0, mp_INT);
2913         pin2  = ioapic_i8259.pin;
2914         apic2 = ioapic_i8259.apic;
2915
2916         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2917                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2918                     cfg->vector, apic1, pin1, apic2, pin2);
2919
2920         /*
2921          * Some BIOS writers are clueless and report the ExtINTA
2922          * I/O APIC input from the cascaded 8259A as the timer
2923          * interrupt input.  So just in case, if only one pin
2924          * was found above, try it both directly and through the
2925          * 8259A.
2926          */
2927         if (pin1 == -1) {
2928                 if (intr_remapping_enabled)
2929                         panic("BIOS bug: timer not connected to IO-APIC");
2930                 pin1 = pin2;
2931                 apic1 = apic2;
2932                 no_pin1 = 1;
2933         } else if (pin2 == -1) {
2934                 pin2 = pin1;
2935                 apic2 = apic1;
2936         }
2937
2938         if (pin1 != -1) {
2939                 /*
2940                  * Ok, does IRQ0 through the IOAPIC work?
2941                  */
2942                 if (no_pin1) {
2943                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2944                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2945                 } else {
2946                         /* for edge trigger, setup_IO_APIC_irq already
2947                          * leave it unmasked.
2948                          * so only need to unmask if it is level-trigger
2949                          * do we really have level trigger timer?
2950                          */
2951                         int idx;
2952                         idx = find_irq_entry(apic1, pin1, mp_INT);
2953                         if (idx != -1 && irq_trigger(idx))
2954                                 unmask_IO_APIC_irq_desc(desc);
2955                 }
2956                 if (timer_irq_works()) {
2957                         if (nmi_watchdog == NMI_IO_APIC) {
2958                                 setup_nmi();
2959                                 enable_8259A_irq(0);
2960                         }
2961                         if (disable_timer_pin_1 > 0)
2962                                 clear_IO_APIC_pin(0, pin1);
2963                         goto out;
2964                 }
2965                 if (intr_remapping_enabled)
2966                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2967                 local_irq_disable();
2968                 clear_IO_APIC_pin(apic1, pin1);
2969                 if (!no_pin1)
2970                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2971                                     "8254 timer not connected to IO-APIC\n");
2972
2973                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2974                             "(IRQ0) through the 8259A ...\n");
2975                 apic_printk(APIC_QUIET, KERN_INFO
2976                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2977                 /*
2978                  * legacy devices should be connected to IO APIC #0
2979                  */
2980                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2981                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2982                 enable_8259A_irq(0);
2983                 if (timer_irq_works()) {
2984                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2985                         timer_through_8259 = 1;
2986                         if (nmi_watchdog == NMI_IO_APIC) {
2987                                 disable_8259A_irq(0);
2988                                 setup_nmi();
2989                                 enable_8259A_irq(0);
2990                         }
2991                         goto out;
2992                 }
2993                 /*
2994                  * Cleanup, just in case ...
2995                  */
2996                 local_irq_disable();
2997                 disable_8259A_irq(0);
2998                 clear_IO_APIC_pin(apic2, pin2);
2999                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3000         }
3001
3002         if (nmi_watchdog == NMI_IO_APIC) {
3003                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3004                             "through the IO-APIC - disabling NMI Watchdog!\n");
3005                 nmi_watchdog = NMI_NONE;
3006         }
3007 #ifdef CONFIG_X86_32
3008         timer_ack = 0;
3009 #endif
3010
3011         apic_printk(APIC_QUIET, KERN_INFO
3012                     "...trying to set up timer as Virtual Wire IRQ...\n");
3013
3014         lapic_register_intr(0, desc);
3015         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
3016         enable_8259A_irq(0);
3017
3018         if (timer_irq_works()) {
3019                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3020                 goto out;
3021         }
3022         local_irq_disable();
3023         disable_8259A_irq(0);
3024         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3025         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3026
3027         apic_printk(APIC_QUIET, KERN_INFO
3028                     "...trying to set up timer as ExtINT IRQ...\n");
3029
3030         init_8259A(0);
3031         make_8259A_irq(0);
3032         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3033
3034         unlock_ExtINT_logic();
3035
3036         if (timer_irq_works()) {
3037                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3038                 goto out;
3039         }
3040         local_irq_disable();
3041         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3042         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3043                 "report.  Then try booting with the 'noapic' option.\n");
3044 out:
3045         local_irq_restore(flags);
3046 }
3047
3048 /*
3049  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3050  * to devices.  However there may be an I/O APIC pin available for
3051  * this interrupt regardless.  The pin may be left unconnected, but
3052  * typically it will be reused as an ExtINT cascade interrupt for
3053  * the master 8259A.  In the MPS case such a pin will normally be
3054  * reported as an ExtINT interrupt in the MP table.  With ACPI
3055  * there is no provision for ExtINT interrupts, and in the absence
3056  * of an override it would be treated as an ordinary ISA I/O APIC
3057  * interrupt, that is edge-triggered and unmasked by default.  We
3058  * used to do this, but it caused problems on some systems because
3059  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3060  * the same ExtINT cascade interrupt to drive the local APIC of the
3061  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3062  * the I/O APIC in all cases now.  No actual device should request
3063  * it anyway.  --macro
3064  */
3065 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3066
3067 void __init setup_IO_APIC(void)
3068 {
3069
3070         /*
3071          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3072          */
3073
3074         io_apic_irqs = ~PIC_IRQS;
3075
3076         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3077         /*
3078          * Set up IO-APIC IRQ routing.
3079          */
3080 #ifdef CONFIG_X86_32
3081         if (!acpi_ioapic)
3082                 setup_ioapic_ids_from_mpc();
3083 #endif
3084         sync_Arb_IDs();
3085         setup_IO_APIC_irqs();
3086         init_IO_APIC_traps();
3087         check_timer();
3088 }
3089
3090 /*
3091  *      Called after all the initialization is done. If we didnt find any
3092  *      APIC bugs then we can allow the modify fast path
3093  */
3094
3095 static int __init io_apic_bug_finalize(void)
3096 {
3097         if (sis_apic_bug == -1)
3098                 sis_apic_bug = 0;
3099         return 0;
3100 }
3101
3102 late_initcall(io_apic_bug_finalize);
3103
3104 struct sysfs_ioapic_data {
3105         struct sys_device dev;
3106         struct IO_APIC_route_entry entry[0];
3107 };
3108 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3109
3110 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3111 {
3112         struct IO_APIC_route_entry *entry;
3113         struct sysfs_ioapic_data *data;
3114         int i;
3115
3116         data = container_of(dev, struct sysfs_ioapic_data, dev);
3117         entry = data->entry;
3118         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3119                 *entry = ioapic_read_entry(dev->id, i);
3120
3121         return 0;
3122 }
3123
3124 static int ioapic_resume(struct sys_device *dev)
3125 {
3126         struct IO_APIC_route_entry *entry;
3127         struct sysfs_ioapic_data *data;
3128         unsigned long flags;
3129         union IO_APIC_reg_00 reg_00;
3130         int i;
3131
3132         data = container_of(dev, struct sysfs_ioapic_data, dev);
3133         entry = data->entry;
3134
3135         spin_lock_irqsave(&ioapic_lock, flags);
3136         reg_00.raw = io_apic_read(dev->id, 0);
3137         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3138                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3139                 io_apic_write(dev->id, 0, reg_00.raw);
3140         }
3141         spin_unlock_irqrestore(&ioapic_lock, flags);
3142         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3143                 ioapic_write_entry(dev->id, i, entry[i]);
3144
3145         return 0;
3146 }
3147
3148 static struct sysdev_class ioapic_sysdev_class = {
3149         .name = "ioapic",
3150         .suspend = ioapic_suspend,
3151         .resume = ioapic_resume,
3152 };
3153
3154 static int __init ioapic_init_sysfs(void)
3155 {
3156         struct sys_device * dev;
3157         int i, size, error;
3158
3159         error = sysdev_class_register(&ioapic_sysdev_class);
3160         if (error)
3161                 return error;
3162
3163         for (i = 0; i < nr_ioapics; i++ ) {
3164                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3165                         * sizeof(struct IO_APIC_route_entry);
3166                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3167                 if (!mp_ioapic_data[i]) {
3168                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3169                         continue;
3170                 }
3171                 dev = &mp_ioapic_data[i]->dev;
3172                 dev->id = i;
3173                 dev->cls = &ioapic_sysdev_class;
3174                 error = sysdev_register(dev);
3175                 if (error) {
3176                         kfree(mp_ioapic_data[i]);
3177                         mp_ioapic_data[i] = NULL;
3178                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3179                         continue;
3180                 }
3181         }
3182
3183         return 0;
3184 }
3185
3186 device_initcall(ioapic_init_sysfs);
3187
3188 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3189 /*
3190  * Dynamic irq allocate and deallocation
3191  */
3192 unsigned int create_irq_nr(unsigned int irq_want)
3193 {
3194         /* Allocate an unused irq */
3195         unsigned int irq;
3196         unsigned int new;
3197         unsigned long flags;
3198         struct irq_cfg *cfg_new = NULL;
3199         int cpu = boot_cpu_id;
3200         struct irq_desc *desc_new = NULL;
3201
3202         irq = 0;
3203         if (irq_want < nr_irqs_gsi)
3204                 irq_want = nr_irqs_gsi;
3205
3206         spin_lock_irqsave(&vector_lock, flags);
3207         for (new = irq_want; new < nr_irqs; new++) {
3208                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3209                 if (!desc_new) {
3210                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3211                         continue;
3212                 }
3213                 cfg_new = desc_new->chip_data;
3214
3215                 if (cfg_new->vector != 0)
3216                         continue;
3217                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3218                         irq = new;
3219                 break;
3220         }
3221         spin_unlock_irqrestore(&vector_lock, flags);
3222
3223         if (irq > 0) {
3224                 dynamic_irq_init(irq);
3225                 /* restore it, in case dynamic_irq_init clear it */
3226                 if (desc_new)
3227                         desc_new->chip_data = cfg_new;
3228         }
3229         return irq;
3230 }
3231
3232 int create_irq(void)
3233 {
3234         unsigned int irq_want;
3235         int irq;
3236
3237         irq_want = nr_irqs_gsi;
3238         irq = create_irq_nr(irq_want);
3239
3240         if (irq == 0)
3241                 irq = -1;
3242
3243         return irq;
3244 }
3245
3246 void destroy_irq(unsigned int irq)
3247 {
3248         unsigned long flags;
3249         struct irq_cfg *cfg;
3250         struct irq_desc *desc;
3251
3252         /* store it, in case dynamic_irq_cleanup clear it */
3253         desc = irq_to_desc(irq);
3254         cfg = desc->chip_data;
3255         dynamic_irq_cleanup(irq);
3256         /* connect back irq_cfg */
3257         if (desc)
3258                 desc->chip_data = cfg;
3259
3260         free_irte(irq);
3261         spin_lock_irqsave(&vector_lock, flags);
3262         __clear_irq_vector(irq, cfg);
3263         spin_unlock_irqrestore(&vector_lock, flags);
3264 }
3265
3266 /*
3267  * MSI message composition
3268  */
3269 #ifdef CONFIG_PCI_MSI
3270 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3271 {
3272         struct irq_cfg *cfg;
3273         int err;
3274         unsigned dest;
3275
3276         if (disable_apic)
3277                 return -ENXIO;
3278
3279         cfg = irq_cfg(irq);
3280         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3281         if (err)
3282                 return err;
3283
3284         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3285
3286         if (irq_remapped(irq)) {
3287                 struct irte irte;
3288                 int ir_index;
3289                 u16 sub_handle;
3290
3291                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3292                 BUG_ON(ir_index == -1);
3293
3294                 memset (&irte, 0, sizeof(irte));
3295
3296                 irte.present = 1;
3297                 irte.dst_mode = apic->irq_dest_mode;
3298                 irte.trigger_mode = 0; /* edge */
3299                 irte.dlvry_mode = apic->irq_delivery_mode;
3300                 irte.vector = cfg->vector;
3301                 irte.dest_id = IRTE_DEST(dest);
3302
3303                 modify_irte(irq, &irte);
3304
3305                 msg->address_hi = MSI_ADDR_BASE_HI;
3306                 msg->data = sub_handle;
3307                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3308                                   MSI_ADDR_IR_SHV |
3309                                   MSI_ADDR_IR_INDEX1(ir_index) |
3310                                   MSI_ADDR_IR_INDEX2(ir_index);
3311         } else {
3312                 if (x2apic_enabled())
3313                         msg->address_hi = MSI_ADDR_BASE_HI |
3314                                           MSI_ADDR_EXT_DEST_ID(dest);
3315                 else
3316                         msg->address_hi = MSI_ADDR_BASE_HI;
3317
3318                 msg->address_lo =
3319                         MSI_ADDR_BASE_LO |
3320                         ((apic->irq_dest_mode == 0) ?
3321                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3322                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3323                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3324                                 MSI_ADDR_REDIRECTION_CPU:
3325                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3326                         MSI_ADDR_DEST_ID(dest);
3327
3328                 msg->data =
3329                         MSI_DATA_TRIGGER_EDGE |
3330                         MSI_DATA_LEVEL_ASSERT |
3331                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3332                                 MSI_DATA_DELIVERY_FIXED:
3333                                 MSI_DATA_DELIVERY_LOWPRI) |
3334                         MSI_DATA_VECTOR(cfg->vector);
3335         }
3336         return err;
3337 }
3338
3339 #ifdef CONFIG_SMP
3340 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3341 {
3342         struct irq_desc *desc = irq_to_desc(irq);
3343         struct irq_cfg *cfg;
3344         struct msi_msg msg;
3345         unsigned int dest;
3346
3347         dest = set_desc_affinity(desc, mask);
3348         if (dest == BAD_APICID)
3349                 return;
3350
3351         cfg = desc->chip_data;
3352
3353         read_msi_msg_desc(desc, &msg);
3354
3355         msg.data &= ~MSI_DATA_VECTOR_MASK;
3356         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3357         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3358         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3359
3360         write_msi_msg_desc(desc, &msg);
3361 }
3362 #ifdef CONFIG_INTR_REMAP
3363 /*
3364  * Migrate the MSI irq to another cpumask. This migration is
3365  * done in the process context using interrupt-remapping hardware.
3366  */
3367 static void
3368 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3369 {
3370         struct irq_desc *desc = irq_to_desc(irq);
3371         struct irq_cfg *cfg = desc->chip_data;
3372         unsigned int dest;
3373         struct irte irte;
3374
3375         if (get_irte(irq, &irte))
3376                 return;
3377
3378         dest = set_desc_affinity(desc, mask);
3379         if (dest == BAD_APICID)
3380                 return;
3381
3382         irte.vector = cfg->vector;
3383         irte.dest_id = IRTE_DEST(dest);
3384
3385         /*
3386          * atomically update the IRTE with the new destination and vector.
3387          */
3388         modify_irte(irq, &irte);
3389
3390         /*
3391          * After this point, all the interrupts will start arriving
3392          * at the new destination. So, time to cleanup the previous
3393          * vector allocation.
3394          */
3395         if (cfg->move_in_progress)
3396                 send_cleanup_vector(cfg);
3397 }
3398
3399 #endif
3400 #endif /* CONFIG_SMP */
3401
3402 /*
3403  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3404  * which implement the MSI or MSI-X Capability Structure.
3405  */
3406 static struct irq_chip msi_chip = {
3407         .name           = "PCI-MSI",
3408         .unmask         = unmask_msi_irq,
3409         .mask           = mask_msi_irq,
3410         .ack            = ack_apic_edge,
3411 #ifdef CONFIG_SMP
3412         .set_affinity   = set_msi_irq_affinity,
3413 #endif
3414         .retrigger      = ioapic_retrigger_irq,
3415 };
3416
3417 static struct irq_chip msi_ir_chip = {
3418         .name           = "IR-PCI-MSI",
3419         .unmask         = unmask_msi_irq,
3420         .mask           = mask_msi_irq,
3421 #ifdef CONFIG_INTR_REMAP
3422         .ack            = ir_ack_apic_edge,
3423 #ifdef CONFIG_SMP
3424         .set_affinity   = ir_set_msi_irq_affinity,
3425 #endif
3426 #endif
3427         .retrigger      = ioapic_retrigger_irq,
3428 };
3429
3430 /*
3431  * Map the PCI dev to the corresponding remapping hardware unit
3432  * and allocate 'nvec' consecutive interrupt-remapping table entries
3433  * in it.
3434  */
3435 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3436 {
3437         struct intel_iommu *iommu;
3438         int index;
3439
3440         iommu = map_dev_to_ir(dev);
3441         if (!iommu) {
3442                 printk(KERN_ERR
3443                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3444                 return -ENOENT;
3445         }
3446
3447         index = alloc_irte(iommu, irq, nvec);
3448         if (index < 0) {
3449                 printk(KERN_ERR
3450                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3451                        pci_name(dev));
3452                 return -ENOSPC;
3453         }
3454         return index;
3455 }
3456
3457 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3458 {
3459         int ret;
3460         struct msi_msg msg;
3461
3462         ret = msi_compose_msg(dev, irq, &msg);
3463         if (ret < 0)
3464                 return ret;
3465
3466         set_irq_msi(irq, msidesc);
3467         write_msi_msg(irq, &msg);
3468
3469         if (irq_remapped(irq)) {
3470                 struct irq_desc *desc = irq_to_desc(irq);
3471                 /*
3472                  * irq migration in process context
3473                  */
3474                 desc->status |= IRQ_MOVE_PCNTXT;
3475                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3476         } else
3477                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3478
3479         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3480
3481         return 0;
3482 }
3483
3484 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3485 {
3486         unsigned int irq;
3487         int ret, sub_handle;
3488         struct msi_desc *msidesc;
3489         unsigned int irq_want;
3490         struct intel_iommu *iommu = NULL;
3491         int index = 0;
3492
3493         /* x86 doesn't support multiple MSI yet */
3494         if (type == PCI_CAP_ID_MSI && nvec > 1)
3495                 return 1;
3496
3497         irq_want = nr_irqs_gsi;
3498         sub_handle = 0;
3499         list_for_each_entry(msidesc, &dev->msi_list, list) {
3500                 irq = create_irq_nr(irq_want);
3501                 if (irq == 0)
3502                         return -1;
3503                 irq_want = irq + 1;
3504                 if (!intr_remapping_enabled)
3505                         goto no_ir;
3506
3507                 if (!sub_handle) {
3508                         /*
3509                          * allocate the consecutive block of IRTE's
3510                          * for 'nvec'
3511                          */
3512                         index = msi_alloc_irte(dev, irq, nvec);
3513                         if (index < 0) {
3514                                 ret = index;
3515                                 goto error;
3516                         }
3517                 } else {
3518                         iommu = map_dev_to_ir(dev);
3519                         if (!iommu) {
3520                                 ret = -ENOENT;
3521                                 goto error;
3522                         }
3523                         /*
3524                          * setup the mapping between the irq and the IRTE
3525                          * base index, the sub_handle pointing to the
3526                          * appropriate interrupt remap table entry.
3527                          */
3528                         set_irte_irq(irq, iommu, index, sub_handle);
3529                 }
3530 no_ir:
3531                 ret = setup_msi_irq(dev, msidesc, irq);
3532                 if (ret < 0)
3533                         goto error;
3534                 sub_handle++;
3535         }
3536         return 0;
3537
3538 error:
3539         destroy_irq(irq);
3540         return ret;
3541 }
3542
3543 void arch_teardown_msi_irq(unsigned int irq)
3544 {
3545         destroy_irq(irq);
3546 }
3547
3548 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3549 #ifdef CONFIG_SMP
3550 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3551 {
3552         struct irq_desc *desc = irq_to_desc(irq);
3553         struct irq_cfg *cfg;
3554         struct msi_msg msg;
3555         unsigned int dest;
3556
3557         dest = set_desc_affinity(desc, mask);
3558         if (dest == BAD_APICID)
3559                 return;
3560
3561         cfg = desc->chip_data;
3562
3563         dmar_msi_read(irq, &msg);
3564
3565         msg.data &= ~MSI_DATA_VECTOR_MASK;
3566         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3567         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3568         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3569
3570         dmar_msi_write(irq, &msg);
3571 }
3572
3573 #endif /* CONFIG_SMP */
3574
3575 struct irq_chip dmar_msi_type = {
3576         .name = "DMAR_MSI",
3577         .unmask = dmar_msi_unmask,
3578         .mask = dmar_msi_mask,
3579         .ack = ack_apic_edge,
3580 #ifdef CONFIG_SMP
3581         .set_affinity = dmar_msi_set_affinity,
3582 #endif
3583         .retrigger = ioapic_retrigger_irq,
3584 };
3585
3586 int arch_setup_dmar_msi(unsigned int irq)
3587 {
3588         int ret;
3589         struct msi_msg msg;
3590
3591         ret = msi_compose_msg(NULL, irq, &msg);
3592         if (ret < 0)
3593                 return ret;
3594         dmar_msi_write(irq, &msg);
3595         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3596                 "edge");
3597         return 0;
3598 }
3599 #endif
3600
3601 #ifdef CONFIG_HPET_TIMER
3602
3603 #ifdef CONFIG_SMP
3604 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3605 {
3606         struct irq_desc *desc = irq_to_desc(irq);
3607         struct irq_cfg *cfg;
3608         struct msi_msg msg;
3609         unsigned int dest;
3610
3611         dest = set_desc_affinity(desc, mask);
3612         if (dest == BAD_APICID)
3613                 return;
3614
3615         cfg = desc->chip_data;
3616
3617         hpet_msi_read(irq, &msg);
3618
3619         msg.data &= ~MSI_DATA_VECTOR_MASK;
3620         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3621         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3622         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3623
3624         hpet_msi_write(irq, &msg);
3625 }
3626
3627 #endif /* CONFIG_SMP */
3628
3629 static struct irq_chip hpet_msi_type = {
3630         .name = "HPET_MSI",
3631         .unmask = hpet_msi_unmask,
3632         .mask = hpet_msi_mask,
3633         .ack = ack_apic_edge,
3634 #ifdef CONFIG_SMP
3635         .set_affinity = hpet_msi_set_affinity,
3636 #endif
3637         .retrigger = ioapic_retrigger_irq,
3638 };
3639
3640 int arch_setup_hpet_msi(unsigned int irq)
3641 {
3642         int ret;
3643         struct msi_msg msg;
3644
3645         ret = msi_compose_msg(NULL, irq, &msg);
3646         if (ret < 0)
3647                 return ret;
3648
3649         hpet_msi_write(irq, &msg);
3650         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3651                 "edge");
3652
3653         return 0;
3654 }
3655 #endif
3656
3657 #endif /* CONFIG_PCI_MSI */
3658 /*
3659  * Hypertransport interrupt support
3660  */
3661 #ifdef CONFIG_HT_IRQ
3662
3663 #ifdef CONFIG_SMP
3664
3665 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3666 {
3667         struct ht_irq_msg msg;
3668         fetch_ht_irq_msg(irq, &msg);
3669
3670         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3671         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3672
3673         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3674         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3675
3676         write_ht_irq_msg(irq, &msg);
3677 }
3678
3679 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3680 {
3681         struct irq_desc *desc = irq_to_desc(irq);
3682         struct irq_cfg *cfg;
3683         unsigned int dest;
3684
3685         dest = set_desc_affinity(desc, mask);
3686         if (dest == BAD_APICID)
3687                 return;
3688
3689         cfg = desc->chip_data;
3690
3691         target_ht_irq(irq, dest, cfg->vector);
3692 }
3693
3694 #endif
3695
3696 static struct irq_chip ht_irq_chip = {
3697         .name           = "PCI-HT",
3698         .mask           = mask_ht_irq,
3699         .unmask         = unmask_ht_irq,
3700         .ack            = ack_apic_edge,
3701 #ifdef CONFIG_SMP
3702         .set_affinity   = set_ht_irq_affinity,
3703 #endif
3704         .retrigger      = ioapic_retrigger_irq,
3705 };
3706
3707 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3708 {
3709         struct irq_cfg *cfg;
3710         int err;
3711
3712         if (disable_apic)
3713                 return -ENXIO;
3714
3715         cfg = irq_cfg(irq);
3716         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3717         if (!err) {
3718                 struct ht_irq_msg msg;
3719                 unsigned dest;
3720
3721                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3722                                                     apic->target_cpus());
3723
3724                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3725
3726                 msg.address_lo =
3727                         HT_IRQ_LOW_BASE |
3728                         HT_IRQ_LOW_DEST_ID(dest) |
3729                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3730                         ((apic->irq_dest_mode == 0) ?
3731                                 HT_IRQ_LOW_DM_PHYSICAL :
3732                                 HT_IRQ_LOW_DM_LOGICAL) |
3733                         HT_IRQ_LOW_RQEOI_EDGE |
3734                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3735                                 HT_IRQ_LOW_MT_FIXED :
3736                                 HT_IRQ_LOW_MT_ARBITRATED) |
3737                         HT_IRQ_LOW_IRQ_MASKED;
3738
3739                 write_ht_irq_msg(irq, &msg);
3740
3741                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3742                                               handle_edge_irq, "edge");
3743
3744                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3745         }
3746         return err;
3747 }
3748 #endif /* CONFIG_HT_IRQ */
3749
3750 #ifdef CONFIG_X86_UV
3751 /*
3752  * Re-target the irq to the specified CPU and enable the specified MMR located
3753  * on the specified blade to allow the sending of MSIs to the specified CPU.
3754  */
3755 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3756                        unsigned long mmr_offset)
3757 {
3758         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3759         struct irq_cfg *cfg;
3760         int mmr_pnode;
3761         unsigned long mmr_value;
3762         struct uv_IO_APIC_route_entry *entry;
3763         unsigned long flags;
3764         int err;
3765
3766         cfg = irq_cfg(irq);
3767
3768         err = assign_irq_vector(irq, cfg, eligible_cpu);
3769         if (err != 0)
3770                 return err;
3771
3772         spin_lock_irqsave(&vector_lock, flags);
3773         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3774                                       irq_name);
3775         spin_unlock_irqrestore(&vector_lock, flags);
3776
3777         mmr_value = 0;
3778         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3779         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3780
3781         entry->vector = cfg->vector;
3782         entry->delivery_mode = apic->irq_delivery_mode;
3783         entry->dest_mode = apic->irq_dest_mode;
3784         entry->polarity = 0;
3785         entry->trigger = 0;
3786         entry->mask = 0;
3787         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3788
3789         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3790         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3791
3792         return irq;
3793 }
3794
3795 /*
3796  * Disable the specified MMR located on the specified blade so that MSIs are
3797  * longer allowed to be sent.
3798  */
3799 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3800 {
3801         unsigned long mmr_value;
3802         struct uv_IO_APIC_route_entry *entry;
3803         int mmr_pnode;
3804
3805         mmr_value = 0;
3806         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3807         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3808
3809         entry->mask = 1;
3810
3811         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3812         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3813 }
3814 #endif /* CONFIG_X86_64 */
3815
3816 int __init io_apic_get_redir_entries (int ioapic)
3817 {
3818         union IO_APIC_reg_01    reg_01;
3819         unsigned long flags;
3820
3821         spin_lock_irqsave(&ioapic_lock, flags);
3822         reg_01.raw = io_apic_read(ioapic, 1);
3823         spin_unlock_irqrestore(&ioapic_lock, flags);
3824
3825         return reg_01.bits.entries;
3826 }
3827
3828 void __init probe_nr_irqs_gsi(void)
3829 {
3830         int nr = 0;
3831
3832         nr = acpi_probe_gsi();
3833         if (nr > nr_irqs_gsi) {
3834                 nr_irqs_gsi = nr;
3835         } else {
3836                 /* for acpi=off or acpi is not compiled in */
3837                 int idx;
3838
3839                 nr = 0;
3840                 for (idx = 0; idx < nr_ioapics; idx++)
3841                         nr += io_apic_get_redir_entries(idx) + 1;
3842
3843                 if (nr > nr_irqs_gsi)
3844                         nr_irqs_gsi = nr;
3845         }
3846
3847         printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3848 }
3849
3850 #ifdef CONFIG_SPARSE_IRQ
3851 int __init arch_probe_nr_irqs(void)
3852 {
3853         int nr;
3854
3855         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3856                 nr_irqs = NR_VECTORS * nr_cpu_ids;
3857
3858         nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3859 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3860         /*
3861          * for MSI and HT dyn irq
3862          */
3863         nr += nr_irqs_gsi * 16;
3864 #endif
3865         if (nr < nr_irqs)
3866                 nr_irqs = nr;
3867
3868         return 0;
3869 }
3870 #endif
3871
3872 /* --------------------------------------------------------------------------
3873                           ACPI-based IOAPIC Configuration
3874    -------------------------------------------------------------------------- */
3875
3876 #ifdef CONFIG_ACPI
3877
3878 #ifdef CONFIG_X86_32
3879 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3880 {
3881         union IO_APIC_reg_00 reg_00;
3882         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3883         physid_mask_t tmp;
3884         unsigned long flags;
3885         int i = 0;
3886
3887         /*
3888          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3889          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3890          * supports up to 16 on one shared APIC bus.
3891          *
3892          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3893          *      advantage of new APIC bus architecture.
3894          */
3895
3896         if (physids_empty(apic_id_map))
3897                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3898
3899         spin_lock_irqsave(&ioapic_lock, flags);
3900         reg_00.raw = io_apic_read(ioapic, 0);
3901         spin_unlock_irqrestore(&ioapic_lock, flags);
3902
3903         if (apic_id >= get_physical_broadcast()) {
3904                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3905                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3906                 apic_id = reg_00.bits.ID;
3907         }
3908
3909         /*
3910          * Every APIC in a system must have a unique ID or we get lots of nice
3911          * 'stuck on smp_invalidate_needed IPI wait' messages.
3912          */
3913         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3914
3915                 for (i = 0; i < get_physical_broadcast(); i++) {
3916                         if (!apic->check_apicid_used(apic_id_map, i))
3917                                 break;
3918                 }
3919
3920                 if (i == get_physical_broadcast())
3921                         panic("Max apic_id exceeded!\n");
3922
3923                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3924                         "trying %d\n", ioapic, apic_id, i);
3925
3926                 apic_id = i;
3927         }
3928
3929         tmp = apic->apicid_to_cpu_present(apic_id);
3930         physids_or(apic_id_map, apic_id_map, tmp);
3931
3932         if (reg_00.bits.ID != apic_id) {
3933                 reg_00.bits.ID = apic_id;
3934
3935                 spin_lock_irqsave(&ioapic_lock, flags);
3936                 io_apic_write(ioapic, 0, reg_00.raw);
3937                 reg_00.raw = io_apic_read(ioapic, 0);
3938                 spin_unlock_irqrestore(&ioapic_lock, flags);
3939
3940                 /* Sanity check */
3941                 if (reg_00.bits.ID != apic_id) {
3942                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3943                         return -1;
3944                 }
3945         }
3946
3947         apic_printk(APIC_VERBOSE, KERN_INFO
3948                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3949
3950         return apic_id;
3951 }
3952
3953 int __init io_apic_get_version(int ioapic)
3954 {
3955         union IO_APIC_reg_01    reg_01;
3956         unsigned long flags;
3957
3958         spin_lock_irqsave(&ioapic_lock, flags);
3959         reg_01.raw = io_apic_read(ioapic, 1);
3960         spin_unlock_irqrestore(&ioapic_lock, flags);
3961
3962         return reg_01.bits.version;
3963 }
3964 #endif
3965
3966 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3967 {
3968         struct irq_desc *desc;
3969         struct irq_cfg *cfg;
3970         int cpu = boot_cpu_id;
3971
3972         if (!IO_APIC_IRQ(irq)) {
3973                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3974                         ioapic);
3975                 return -EINVAL;
3976         }
3977
3978         desc = irq_to_desc_alloc_cpu(irq, cpu);
3979         if (!desc) {
3980                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3981                 return 0;
3982         }
3983
3984         /*
3985          * IRQs < 16 are already in the irq_2_pin[] map
3986          */
3987         if (irq >= NR_IRQS_LEGACY) {
3988                 cfg = desc->chip_data;
3989                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3990         }
3991
3992         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3993
3994         return 0;
3995 }
3996
3997
3998 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3999 {
4000         int i;
4001
4002         if (skip_ioapic_setup)
4003                 return -1;
4004
4005         for (i = 0; i < mp_irq_entries; i++)
4006                 if (mp_irqs[i].irqtype == mp_INT &&
4007                     mp_irqs[i].srcbusirq == bus_irq)
4008                         break;
4009         if (i >= mp_irq_entries)
4010                 return -1;
4011
4012         *trigger = irq_trigger(i);
4013         *polarity = irq_polarity(i);
4014         return 0;
4015 }
4016
4017 #endif /* CONFIG_ACPI */
4018
4019 /*
4020  * This function currently is only a helper for the i386 smp boot process where
4021  * we need to reprogram the ioredtbls to cater for the cpus which have come online
4022  * so mask in all cases should simply be apic->target_cpus()
4023  */
4024 #ifdef CONFIG_SMP
4025 void __init setup_ioapic_dest(void)
4026 {
4027         int pin, ioapic, irq, irq_entry;
4028         struct irq_desc *desc;
4029         struct irq_cfg *cfg;
4030         const struct cpumask *mask;
4031
4032         if (skip_ioapic_setup == 1)
4033                 return;
4034
4035         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4036                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4037                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4038                         if (irq_entry == -1)
4039                                 continue;
4040                         irq = pin_2_irq(irq_entry, ioapic, pin);
4041
4042                         /* setup_IO_APIC_irqs could fail to get vector for some device
4043                          * when you have too many devices, because at that time only boot
4044                          * cpu is online.
4045                          */
4046                         desc = irq_to_desc(irq);
4047                         cfg = desc->chip_data;
4048                         if (!cfg->vector) {
4049                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4050                                                   irq_trigger(irq_entry),
4051                                                   irq_polarity(irq_entry));
4052                                 continue;
4053
4054                         }
4055
4056                         /*
4057                          * Honour affinities which have been set in early boot
4058                          */
4059                         if (desc->status &
4060                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4061                                 mask = desc->affinity;
4062                         else
4063                                 mask = apic->target_cpus();
4064
4065                         if (intr_remapping_enabled)
4066                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4067                         else
4068                                 set_ioapic_affinity_irq_desc(desc, mask);
4069                 }
4070
4071         }
4072 }
4073 #endif
4074
4075 #define IOAPIC_RESOURCE_NAME_SIZE 11
4076
4077 static struct resource *ioapic_resources;
4078
4079 static struct resource * __init ioapic_setup_resources(void)
4080 {
4081         unsigned long n;
4082         struct resource *res;
4083         char *mem;
4084         int i;
4085
4086         if (nr_ioapics <= 0)
4087                 return NULL;
4088
4089         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4090         n *= nr_ioapics;
4091
4092         mem = alloc_bootmem(n);
4093         res = (void *)mem;
4094
4095         if (mem != NULL) {
4096                 mem += sizeof(struct resource) * nr_ioapics;
4097
4098                 for (i = 0; i < nr_ioapics; i++) {
4099                         res[i].name = mem;
4100                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4101                         sprintf(mem,  "IOAPIC %u", i);
4102                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4103                 }
4104         }
4105
4106         ioapic_resources = res;
4107
4108         return res;
4109 }
4110
4111 void __init ioapic_init_mappings(void)
4112 {
4113         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4114         struct resource *ioapic_res;
4115         int i;
4116
4117         ioapic_res = ioapic_setup_resources();
4118         for (i = 0; i < nr_ioapics; i++) {
4119                 if (smp_found_config) {
4120                         ioapic_phys = mp_ioapics[i].apicaddr;
4121 #ifdef CONFIG_X86_32
4122                         if (!ioapic_phys) {
4123                                 printk(KERN_ERR
4124                                        "WARNING: bogus zero IO-APIC "
4125                                        "address found in MPTABLE, "
4126                                        "disabling IO/APIC support!\n");
4127                                 smp_found_config = 0;
4128                                 skip_ioapic_setup = 1;
4129                                 goto fake_ioapic_page;
4130                         }
4131 #endif
4132                 } else {
4133 #ifdef CONFIG_X86_32
4134 fake_ioapic_page:
4135 #endif
4136                         ioapic_phys = (unsigned long)
4137                                 alloc_bootmem_pages(PAGE_SIZE);
4138                         ioapic_phys = __pa(ioapic_phys);
4139                 }
4140                 set_fixmap_nocache(idx, ioapic_phys);
4141                 apic_printk(APIC_VERBOSE,
4142                             "mapped IOAPIC to %08lx (%08lx)\n",
4143                             __fix_to_virt(idx), ioapic_phys);
4144                 idx++;
4145
4146                 if (ioapic_res != NULL) {
4147                         ioapic_res->start = ioapic_phys;
4148                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4149                         ioapic_res++;
4150                 }
4151         }
4152 }
4153
4154 static int __init ioapic_insert_resources(void)
4155 {
4156         int i;
4157         struct resource *r = ioapic_resources;
4158
4159         if (!r) {
4160                 if (nr_ioapics > 0) {
4161                         printk(KERN_ERR
4162                                 "IO APIC resources couldn't be allocated.\n");
4163                         return -1;
4164                 }
4165                 return 0;
4166         }
4167
4168         for (i = 0; i < nr_ioapics; i++) {
4169                 insert_resource(&iomem_resource, r);
4170                 r++;
4171         }
4172
4173         return 0;
4174 }
4175
4176 /* Insert the IO APIC resources after PCI initialization has occured to handle
4177  * IO APICS that are mapped in on a BAR in PCI space. */
4178 late_initcall(ioapic_insert_resources);