2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_proto.h>
29 #include <asm/amd_iommu_types.h>
30 #include <asm/amd_iommu.h>
31 #include <asm/iommu.h>
33 #include <asm/x86_init.h>
36 * definitions for the ACPI scanning code
38 #define IVRS_HEADER_LENGTH 48
40 #define ACPI_IVHD_TYPE 0x10
41 #define ACPI_IVMD_TYPE_ALL 0x20
42 #define ACPI_IVMD_TYPE 0x21
43 #define ACPI_IVMD_TYPE_RANGE 0x22
45 #define IVHD_DEV_ALL 0x01
46 #define IVHD_DEV_SELECT 0x02
47 #define IVHD_DEV_SELECT_RANGE_START 0x03
48 #define IVHD_DEV_RANGE_END 0x04
49 #define IVHD_DEV_ALIAS 0x42
50 #define IVHD_DEV_ALIAS_RANGE 0x43
51 #define IVHD_DEV_EXT_SELECT 0x46
52 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
54 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
55 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
56 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
57 #define IVHD_FLAG_ISOC_EN_MASK 0x08
59 #define IVMD_FLAG_EXCL_RANGE 0x08
60 #define IVMD_FLAG_UNITY_MAP 0x01
62 #define ACPI_DEVFLAG_INITPASS 0x01
63 #define ACPI_DEVFLAG_EXTINT 0x02
64 #define ACPI_DEVFLAG_NMI 0x04
65 #define ACPI_DEVFLAG_SYSMGT1 0x10
66 #define ACPI_DEVFLAG_SYSMGT2 0x20
67 #define ACPI_DEVFLAG_LINT0 0x40
68 #define ACPI_DEVFLAG_LINT1 0x80
69 #define ACPI_DEVFLAG_ATSDIS 0x10000000
72 * ACPI table definitions
74 * These data structures are laid over the table to parse the important values
79 * structure describing one IOMMU in the ACPI table. Typically followed by one
80 * or more ivhd_entrys.
92 } __attribute__((packed));
95 * A device entry describing which devices a specific IOMMU translates and
96 * which requestor ids they use.
103 } __attribute__((packed));
106 * An AMD IOMMU memory definition structure. It defines things like exclusion
107 * ranges for devices and regions that should be unity mapped.
118 } __attribute__((packed));
122 static int __initdata amd_iommu_detected;
124 u16 amd_iommu_last_bdf; /* largest PCI device id we have
126 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
128 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
130 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
133 /* Array to assign indices to IOMMUs*/
134 struct amd_iommu *amd_iommus[MAX_IOMMUS];
135 int amd_iommus_present;
137 /* IOMMUs have a non-present cache? */
138 bool amd_iommu_np_cache __read_mostly;
141 * List of protection domains - used during resume
143 LIST_HEAD(amd_iommu_pd_list);
144 spinlock_t amd_iommu_pd_lock;
147 * Pointer to the device table which is shared by all AMD IOMMUs
148 * it is indexed by the PCI device id or the HT unit id and contains
149 * information about the domain the device belongs to as well as the
150 * page table root pointer.
152 struct dev_table_entry *amd_iommu_dev_table;
155 * The alias table is a driver specific data structure which contains the
156 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
157 * More than one device can share the same requestor id.
159 u16 *amd_iommu_alias_table;
162 * The rlookup table is used to find the IOMMU which is responsible
163 * for a specific device. It is also indexed by the PCI device id.
165 struct amd_iommu **amd_iommu_rlookup_table;
168 * The pd table (protection domain table) is used to find the protection domain
169 * data structure a device belongs to. Indexed with the PCI device id too.
171 struct protection_domain **amd_iommu_pd_table;
174 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
175 * to know which ones are already in use.
177 unsigned long *amd_iommu_pd_alloc_bitmap;
179 static u32 dev_table_size; /* size of the device table */
180 static u32 alias_table_size; /* size of the alias table */
181 static u32 rlookup_table_size; /* size if the rlookup table */
183 static inline void update_last_devid(u16 devid)
185 if (devid > amd_iommu_last_bdf)
186 amd_iommu_last_bdf = devid;
189 static inline unsigned long tbl_size(int entry_size)
191 unsigned shift = PAGE_SHIFT +
192 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
197 /****************************************************************************
199 * AMD IOMMU MMIO register space handling functions
201 * These functions are used to program the IOMMU device registers in
202 * MMIO space required for that driver.
204 ****************************************************************************/
207 * This function set the exclusion range in the IOMMU. DMA accesses to the
208 * exclusion range are passed through untranslated
210 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
212 u64 start = iommu->exclusion_start & PAGE_MASK;
213 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
216 if (!iommu->exclusion_start)
219 entry = start | MMIO_EXCL_ENABLE_MASK;
220 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
221 &entry, sizeof(entry));
224 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
225 &entry, sizeof(entry));
228 /* Programs the physical address of the device table into the IOMMU hardware */
229 static void __init iommu_set_device_table(struct amd_iommu *iommu)
233 BUG_ON(iommu->mmio_base == NULL);
235 entry = virt_to_phys(amd_iommu_dev_table);
236 entry |= (dev_table_size >> 12) - 1;
237 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
238 &entry, sizeof(entry));
241 /* Generic functions to enable/disable certain features of the IOMMU. */
242 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
246 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
248 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
251 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
255 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
257 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
260 /* Function to enable the hardware */
261 static void iommu_enable(struct amd_iommu *iommu)
263 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
264 dev_name(&iommu->dev->dev), iommu->cap_ptr);
266 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
269 static void iommu_disable(struct amd_iommu *iommu)
271 /* Disable command buffer */
272 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
274 /* Disable event logging and event interrupts */
275 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
276 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
278 /* Disable IOMMU hardware itself */
279 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
283 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
284 * the system has one.
286 static u8 * __init iommu_map_mmio_space(u64 address)
290 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
293 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
297 release_mem_region(address, MMIO_REGION_LENGTH);
302 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
304 if (iommu->mmio_base)
305 iounmap(iommu->mmio_base);
306 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
309 /****************************************************************************
311 * The functions below belong to the first pass of AMD IOMMU ACPI table
312 * parsing. In this pass we try to find out the highest device id this
313 * code has to handle. Upon this information the size of the shared data
314 * structures is determined later.
316 ****************************************************************************/
319 * This function calculates the length of a given IVHD entry
321 static inline int ivhd_entry_length(u8 *ivhd)
323 return 0x04 << (*ivhd >> 6);
327 * This function reads the last device id the IOMMU has to handle from the PCI
328 * capability header for this IOMMU
330 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
334 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
335 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
341 * After reading the highest device id from the IOMMU PCI capability header
342 * this function looks if there is a higher device id defined in the ACPI table
344 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
346 u8 *p = (void *)h, *end = (void *)h;
347 struct ivhd_entry *dev;
352 find_last_devid_on_pci(PCI_BUS(h->devid),
358 dev = (struct ivhd_entry *)p;
360 case IVHD_DEV_SELECT:
361 case IVHD_DEV_RANGE_END:
363 case IVHD_DEV_EXT_SELECT:
364 /* all the above subfield types refer to device ids */
365 update_last_devid(dev->devid);
370 p += ivhd_entry_length(p);
379 * Iterate over all IVHD entries in the ACPI table and find the highest device
380 * id which we need to handle. This is the first of three functions which parse
381 * the ACPI table. So we check the checksum here.
383 static int __init find_last_devid_acpi(struct acpi_table_header *table)
386 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
387 struct ivhd_header *h;
390 * Validate checksum here so we don't need to do it when
391 * we actually parse the table
393 for (i = 0; i < table->length; ++i)
396 /* ACPI table corrupt */
399 p += IVRS_HEADER_LENGTH;
401 end += table->length;
403 h = (struct ivhd_header *)p;
406 find_last_devid_from_ivhd(h);
418 /****************************************************************************
420 * The following functions belong the the code path which parses the ACPI table
421 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
422 * data structures, initialize the device/alias/rlookup table and also
423 * basically initialize the hardware.
425 ****************************************************************************/
428 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
429 * write commands to that buffer later and the IOMMU will execute them
432 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
434 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
435 get_order(CMD_BUFFER_SIZE));
440 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
446 * This function resets the command buffer if the IOMMU stopped fetching
449 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
451 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
453 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
454 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
456 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
460 * This function writes the command buffer address to the hardware and
463 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
467 BUG_ON(iommu->cmd_buf == NULL);
469 entry = (u64)virt_to_phys(iommu->cmd_buf);
470 entry |= MMIO_CMD_SIZE_512;
472 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
473 &entry, sizeof(entry));
475 amd_iommu_reset_cmd_buffer(iommu);
478 static void __init free_command_buffer(struct amd_iommu *iommu)
480 free_pages((unsigned long)iommu->cmd_buf,
481 get_order(iommu->cmd_buf_size));
484 /* allocates the memory where the IOMMU will log its events to */
485 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
487 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
488 get_order(EVT_BUFFER_SIZE));
490 if (iommu->evt_buf == NULL)
493 iommu->evt_buf_size = EVT_BUFFER_SIZE;
495 return iommu->evt_buf;
498 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
502 BUG_ON(iommu->evt_buf == NULL);
504 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
506 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
507 &entry, sizeof(entry));
509 /* set head and tail to zero manually */
510 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
511 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
513 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
516 static void __init free_event_buffer(struct amd_iommu *iommu)
518 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
521 /* sets a specific bit in the device table entry. */
522 static void set_dev_entry_bit(u16 devid, u8 bit)
524 int i = (bit >> 5) & 0x07;
525 int _bit = bit & 0x1f;
527 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
530 static int get_dev_entry_bit(u16 devid, u8 bit)
532 int i = (bit >> 5) & 0x07;
533 int _bit = bit & 0x1f;
535 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
539 void amd_iommu_apply_erratum_63(u16 devid)
543 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
544 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
547 set_dev_entry_bit(devid, DEV_ENTRY_IW);
550 /* Writes the specific IOMMU for a device into the rlookup table */
551 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
553 amd_iommu_rlookup_table[devid] = iommu;
557 * This function takes the device specific flags read from the ACPI
558 * table and sets up the device table entry with that information
560 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
561 u16 devid, u32 flags, u32 ext_flags)
563 if (flags & ACPI_DEVFLAG_INITPASS)
564 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
565 if (flags & ACPI_DEVFLAG_EXTINT)
566 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
567 if (flags & ACPI_DEVFLAG_NMI)
568 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
569 if (flags & ACPI_DEVFLAG_SYSMGT1)
570 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
571 if (flags & ACPI_DEVFLAG_SYSMGT2)
572 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
573 if (flags & ACPI_DEVFLAG_LINT0)
574 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
575 if (flags & ACPI_DEVFLAG_LINT1)
576 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
578 amd_iommu_apply_erratum_63(devid);
580 set_iommu_for_device(iommu, devid);
584 * Reads the device exclusion range from ACPI and initialize IOMMU with
587 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
589 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
591 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
596 * We only can configure exclusion ranges per IOMMU, not
597 * per device. But we can enable the exclusion range per
598 * device. This is done here
600 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
601 iommu->exclusion_start = m->range_start;
602 iommu->exclusion_length = m->range_length;
607 * This function reads some important data from the IOMMU PCI space and
608 * initializes the driver data structure with it. It reads the hardware
609 * capabilities and the first/last device entries
611 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
613 int cap_ptr = iommu->cap_ptr;
616 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
618 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
620 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
623 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
625 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
627 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
631 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
632 * initializes the hardware and our data structures with it.
634 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
635 struct ivhd_header *h)
638 u8 *end = p, flags = 0;
639 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
642 struct ivhd_entry *e;
645 * First set the recommended feature enable bits from ACPI
646 * into the IOMMU control registers
648 h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
649 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
650 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
652 h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
653 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
654 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
656 h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
657 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
658 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
660 h->flags & IVHD_FLAG_ISOC_EN_MASK ?
661 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
662 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
665 * make IOMMU memory accesses cache coherent
667 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
670 * Done. Now parse the device entries
672 p += sizeof(struct ivhd_header);
677 e = (struct ivhd_entry *)p;
681 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
682 " last device %02x:%02x.%x flags: %02x\n",
683 PCI_BUS(iommu->first_device),
684 PCI_SLOT(iommu->first_device),
685 PCI_FUNC(iommu->first_device),
686 PCI_BUS(iommu->last_device),
687 PCI_SLOT(iommu->last_device),
688 PCI_FUNC(iommu->last_device),
691 for (dev_i = iommu->first_device;
692 dev_i <= iommu->last_device; ++dev_i)
693 set_dev_entry_from_acpi(iommu, dev_i,
696 case IVHD_DEV_SELECT:
698 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
706 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
708 case IVHD_DEV_SELECT_RANGE_START:
710 DUMP_printk(" DEV_SELECT_RANGE_START\t "
711 "devid: %02x:%02x.%x flags: %02x\n",
717 devid_start = e->devid;
724 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
725 "flags: %02x devid_to: %02x:%02x.%x\n",
730 PCI_BUS(e->ext >> 8),
731 PCI_SLOT(e->ext >> 8),
732 PCI_FUNC(e->ext >> 8));
735 devid_to = e->ext >> 8;
736 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
737 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
738 amd_iommu_alias_table[devid] = devid_to;
740 case IVHD_DEV_ALIAS_RANGE:
742 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
743 "devid: %02x:%02x.%x flags: %02x "
744 "devid_to: %02x:%02x.%x\n",
749 PCI_BUS(e->ext >> 8),
750 PCI_SLOT(e->ext >> 8),
751 PCI_FUNC(e->ext >> 8));
753 devid_start = e->devid;
755 devid_to = e->ext >> 8;
759 case IVHD_DEV_EXT_SELECT:
761 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
762 "flags: %02x ext: %08x\n",
769 set_dev_entry_from_acpi(iommu, devid, e->flags,
772 case IVHD_DEV_EXT_SELECT_RANGE:
774 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
775 "%02x:%02x.%x flags: %02x ext: %08x\n",
781 devid_start = e->devid;
786 case IVHD_DEV_RANGE_END:
788 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
794 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
796 amd_iommu_alias_table[dev_i] = devid_to;
797 set_dev_entry_from_acpi(iommu,
798 devid_to, flags, ext_flags);
800 set_dev_entry_from_acpi(iommu, dev_i,
808 p += ivhd_entry_length(p);
812 /* Initializes the device->iommu mapping for the driver */
813 static int __init init_iommu_devices(struct amd_iommu *iommu)
817 for (i = iommu->first_device; i <= iommu->last_device; ++i)
818 set_iommu_for_device(iommu, i);
823 static void __init free_iommu_one(struct amd_iommu *iommu)
825 free_command_buffer(iommu);
826 free_event_buffer(iommu);
827 iommu_unmap_mmio_space(iommu);
830 static void __init free_iommu_all(void)
832 struct amd_iommu *iommu, *next;
834 for_each_iommu_safe(iommu, next) {
835 list_del(&iommu->list);
836 free_iommu_one(iommu);
842 * This function clues the initialization function for one IOMMU
843 * together and also allocates the command buffer and programs the
844 * hardware. It does NOT enable the IOMMU. This is done afterwards.
846 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
848 spin_lock_init(&iommu->lock);
850 /* Add IOMMU to internal data structures */
851 list_add_tail(&iommu->list, &amd_iommu_list);
852 iommu->index = amd_iommus_present++;
854 if (unlikely(iommu->index >= MAX_IOMMUS)) {
855 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
859 /* Index is fine - add IOMMU to the array */
860 amd_iommus[iommu->index] = iommu;
863 * Copy data from ACPI table entry to the iommu struct
865 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
869 iommu->cap_ptr = h->cap_ptr;
870 iommu->pci_seg = h->pci_seg;
871 iommu->mmio_phys = h->mmio_phys;
872 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
873 if (!iommu->mmio_base)
876 iommu->cmd_buf = alloc_command_buffer(iommu);
880 iommu->evt_buf = alloc_event_buffer(iommu);
884 iommu->int_enabled = false;
886 init_iommu_from_pci(iommu);
887 init_iommu_from_acpi(iommu, h);
888 init_iommu_devices(iommu);
890 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
891 amd_iommu_np_cache = true;
893 return pci_enable_device(iommu->dev);
897 * Iterates over all IOMMU entries in the ACPI table, allocates the
898 * IOMMU structure and initializes it with init_iommu_one()
900 static int __init init_iommu_all(struct acpi_table_header *table)
902 u8 *p = (u8 *)table, *end = (u8 *)table;
903 struct ivhd_header *h;
904 struct amd_iommu *iommu;
907 end += table->length;
908 p += IVRS_HEADER_LENGTH;
911 h = (struct ivhd_header *)p;
915 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
916 "seg: %d flags: %01x info %04x\n",
917 PCI_BUS(h->devid), PCI_SLOT(h->devid),
918 PCI_FUNC(h->devid), h->cap_ptr,
919 h->pci_seg, h->flags, h->info);
920 DUMP_printk(" mmio-addr: %016llx\n",
923 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
926 ret = init_iommu_one(iommu, h);
941 /****************************************************************************
943 * The following functions initialize the MSI interrupts for all IOMMUs
944 * in the system. Its a bit challenging because there could be multiple
945 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
948 ****************************************************************************/
950 static int iommu_setup_msi(struct amd_iommu *iommu)
954 if (pci_enable_msi(iommu->dev))
957 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
963 pci_disable_msi(iommu->dev);
967 iommu->int_enabled = true;
968 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
973 static int iommu_init_msi(struct amd_iommu *iommu)
975 if (iommu->int_enabled)
978 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
979 return iommu_setup_msi(iommu);
984 /****************************************************************************
986 * The next functions belong to the third pass of parsing the ACPI
987 * table. In this last pass the memory mapping requirements are
988 * gathered (like exclusion and unity mapping reanges).
990 ****************************************************************************/
992 static void __init free_unity_maps(void)
994 struct unity_map_entry *entry, *next;
996 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
997 list_del(&entry->list);
1002 /* called when we find an exclusion range definition in ACPI */
1003 static int __init init_exclusion_range(struct ivmd_header *m)
1008 case ACPI_IVMD_TYPE:
1009 set_device_exclusion_range(m->devid, m);
1011 case ACPI_IVMD_TYPE_ALL:
1012 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1013 set_device_exclusion_range(i, m);
1015 case ACPI_IVMD_TYPE_RANGE:
1016 for (i = m->devid; i <= m->aux; ++i)
1017 set_device_exclusion_range(i, m);
1026 /* called for unity map ACPI definition */
1027 static int __init init_unity_map_range(struct ivmd_header *m)
1029 struct unity_map_entry *e = 0;
1032 e = kzalloc(sizeof(*e), GFP_KERNEL);
1040 case ACPI_IVMD_TYPE:
1041 s = "IVMD_TYPEi\t\t\t";
1042 e->devid_start = e->devid_end = m->devid;
1044 case ACPI_IVMD_TYPE_ALL:
1045 s = "IVMD_TYPE_ALL\t\t";
1047 e->devid_end = amd_iommu_last_bdf;
1049 case ACPI_IVMD_TYPE_RANGE:
1050 s = "IVMD_TYPE_RANGE\t\t";
1051 e->devid_start = m->devid;
1052 e->devid_end = m->aux;
1055 e->address_start = PAGE_ALIGN(m->range_start);
1056 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1057 e->prot = m->flags >> 1;
1059 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1060 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1061 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1062 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1063 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1064 e->address_start, e->address_end, m->flags);
1066 list_add_tail(&e->list, &amd_iommu_unity_map);
1071 /* iterates over all memory definitions we find in the ACPI table */
1072 static int __init init_memory_definitions(struct acpi_table_header *table)
1074 u8 *p = (u8 *)table, *end = (u8 *)table;
1075 struct ivmd_header *m;
1077 end += table->length;
1078 p += IVRS_HEADER_LENGTH;
1081 m = (struct ivmd_header *)p;
1082 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1083 init_exclusion_range(m);
1084 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1085 init_unity_map_range(m);
1094 * Init the device table to not allow DMA access for devices and
1095 * suppress all page faults
1097 static void init_device_table(void)
1101 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1102 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1103 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1108 * This function finally enables all IOMMUs found in the system after
1109 * they have been initialized
1111 static void enable_iommus(void)
1113 struct amd_iommu *iommu;
1115 for_each_iommu(iommu) {
1116 iommu_disable(iommu);
1117 iommu_set_device_table(iommu);
1118 iommu_enable_command_buffer(iommu);
1119 iommu_enable_event_buffer(iommu);
1120 iommu_set_exclusion_range(iommu);
1121 iommu_init_msi(iommu);
1122 iommu_enable(iommu);
1126 static void disable_iommus(void)
1128 struct amd_iommu *iommu;
1130 for_each_iommu(iommu)
1131 iommu_disable(iommu);
1135 * Suspend/Resume support
1136 * disable suspend until real resume implemented
1139 static int amd_iommu_resume(struct sys_device *dev)
1141 /* re-load the hardware */
1145 * we have to flush after the IOMMUs are enabled because a
1146 * disabled IOMMU will never execute the commands we send
1148 amd_iommu_flush_all_devices();
1149 amd_iommu_flush_all_domains();
1154 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
1156 /* disable IOMMUs to go out of the way for BIOS */
1162 static struct sysdev_class amd_iommu_sysdev_class = {
1163 .name = "amd_iommu",
1164 .suspend = amd_iommu_suspend,
1165 .resume = amd_iommu_resume,
1168 static struct sys_device device_amd_iommu = {
1170 .cls = &amd_iommu_sysdev_class,
1174 * This is the core init function for AMD IOMMU hardware in the system.
1175 * This function is called from the generic x86 DMA layer initialization
1178 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1181 * 1 pass) Find the highest PCI device id the driver has to handle.
1182 * Upon this information the size of the data structures is
1183 * determined that needs to be allocated.
1185 * 2 pass) Initialize the data structures just allocated with the
1186 * information in the ACPI table about available AMD IOMMUs
1187 * in the system. It also maps the PCI devices in the
1188 * system to specific IOMMUs
1190 * 3 pass) After the basic data structures are allocated and
1191 * initialized we update them with information about memory
1192 * remapping requirements parsed out of the ACPI table in
1195 * After that the hardware is initialized and ready to go. In the last
1196 * step we do some Linux specific things like registering the driver in
1197 * the dma_ops interface and initializing the suspend/resume support
1198 * functions. Finally it prints some information about AMD IOMMUs and
1199 * the driver state and enables the hardware.
1201 static int __init amd_iommu_init(void)
1206 * First parse ACPI tables to find the largest Bus/Dev/Func
1207 * we need to handle. Upon this information the shared data
1208 * structures for the IOMMUs in the system will be allocated
1210 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1213 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1214 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1215 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1219 /* Device table - directly used by all IOMMUs */
1220 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1221 get_order(dev_table_size));
1222 if (amd_iommu_dev_table == NULL)
1226 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1227 * IOMMU see for that device
1229 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1230 get_order(alias_table_size));
1231 if (amd_iommu_alias_table == NULL)
1234 /* IOMMU rlookup table - find the IOMMU for a specific device */
1235 amd_iommu_rlookup_table = (void *)__get_free_pages(
1236 GFP_KERNEL | __GFP_ZERO,
1237 get_order(rlookup_table_size));
1238 if (amd_iommu_rlookup_table == NULL)
1242 * Protection Domain table - maps devices to protection domains
1243 * This table has the same size as the rlookup_table
1245 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1246 get_order(rlookup_table_size));
1247 if (amd_iommu_pd_table == NULL)
1250 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1251 GFP_KERNEL | __GFP_ZERO,
1252 get_order(MAX_DOMAIN_ID/8));
1253 if (amd_iommu_pd_alloc_bitmap == NULL)
1256 /* init the device table */
1257 init_device_table();
1260 * let all alias entries point to itself
1262 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1263 amd_iommu_alias_table[i] = i;
1266 * never allocate domain 0 because its used as the non-allocated and
1267 * error value placeholder
1269 amd_iommu_pd_alloc_bitmap[0] = 1;
1271 spin_lock_init(&amd_iommu_pd_lock);
1274 * now the data structures are allocated and basically initialized
1275 * start the real acpi table scan
1278 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1281 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1284 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1288 ret = sysdev_register(&device_amd_iommu);
1292 if (iommu_pass_through)
1293 ret = amd_iommu_init_passthrough();
1295 ret = amd_iommu_init_dma_ops();
1301 if (iommu_pass_through)
1304 if (amd_iommu_unmap_flush)
1305 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1307 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1309 x86_platform.iommu_shutdown = disable_iommus;
1314 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1315 get_order(MAX_DOMAIN_ID/8));
1317 free_pages((unsigned long)amd_iommu_pd_table,
1318 get_order(rlookup_table_size));
1320 free_pages((unsigned long)amd_iommu_rlookup_table,
1321 get_order(rlookup_table_size));
1323 free_pages((unsigned long)amd_iommu_alias_table,
1324 get_order(alias_table_size));
1326 free_pages((unsigned long)amd_iommu_dev_table,
1327 get_order(dev_table_size));
1336 /****************************************************************************
1338 * Early detect code. This code runs at IOMMU detection time in the DMA
1339 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1342 ****************************************************************************/
1343 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1348 void __init amd_iommu_detect(void)
1350 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1353 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1355 amd_iommu_detected = 1;
1356 x86_init.iommu.iommu_init = amd_iommu_init;
1360 /****************************************************************************
1362 * Parsing functions for the AMD IOMMU specific kernel command line
1365 ****************************************************************************/
1367 static int __init parse_amd_iommu_dump(char *str)
1369 amd_iommu_dump = true;
1374 static int __init parse_amd_iommu_options(char *str)
1376 for (; *str; ++str) {
1377 if (strncmp(str, "fullflush", 9) == 0)
1378 amd_iommu_unmap_flush = true;
1384 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1385 __setup("amd_iommu=", parse_amd_iommu_options);