2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
49 static struct protection_domain *pt_domain;
51 static struct iommu_ops amd_iommu_ops;
54 * general struct to manage commands send to an IOMMU
60 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
61 struct unity_map_entry *e);
62 static u64 *alloc_pte(struct protection_domain *domain,
63 unsigned long address, int end_lvl,
64 u64 **pte_page, gfp_t gfp);
65 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
66 unsigned long start_page,
68 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
69 static u64 *fetch_pte(struct protection_domain *domain,
70 unsigned long address, int map_size);
71 static void update_domain(struct protection_domain *domain);
73 /****************************************************************************
77 ****************************************************************************/
79 static inline u16 get_device_id(struct device *dev)
81 struct pci_dev *pdev = to_pci_dev(dev);
83 return calc_devid(pdev->bus->number, pdev->devfn);
87 * In this function the list of preallocated protection domains is traversed to
88 * find the domain for a specific device
90 static struct dma_ops_domain *find_protection_domain(u16 devid)
92 struct dma_ops_domain *entry, *ret = NULL;
94 u16 alias = amd_iommu_alias_table[devid];
96 if (list_empty(&iommu_pd_list))
99 spin_lock_irqsave(&iommu_pd_list_lock, flags);
101 list_for_each_entry(entry, &iommu_pd_list, list) {
102 if (entry->target_dev == devid ||
103 entry->target_dev == alias) {
109 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
115 * This function checks if the driver got a valid device from the caller to
116 * avoid dereferencing invalid pointers.
118 static bool check_device(struct device *dev)
122 if (!dev || !dev->dma_mask)
125 /* No device or no PCI device */
126 if (!dev || dev->bus != &pci_bus_type)
129 devid = get_device_id(dev);
131 /* Out of our scope? */
132 if (devid > amd_iommu_last_bdf)
135 if (amd_iommu_rlookup_table[devid] == NULL)
141 #ifdef CONFIG_AMD_IOMMU_STATS
144 * Initialization code for statistics collection
147 DECLARE_STATS_COUNTER(compl_wait);
148 DECLARE_STATS_COUNTER(cnt_map_single);
149 DECLARE_STATS_COUNTER(cnt_unmap_single);
150 DECLARE_STATS_COUNTER(cnt_map_sg);
151 DECLARE_STATS_COUNTER(cnt_unmap_sg);
152 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
153 DECLARE_STATS_COUNTER(cnt_free_coherent);
154 DECLARE_STATS_COUNTER(cross_page);
155 DECLARE_STATS_COUNTER(domain_flush_single);
156 DECLARE_STATS_COUNTER(domain_flush_all);
157 DECLARE_STATS_COUNTER(alloced_io_mem);
158 DECLARE_STATS_COUNTER(total_map_requests);
160 static struct dentry *stats_dir;
161 static struct dentry *de_isolate;
162 static struct dentry *de_fflush;
164 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
166 if (stats_dir == NULL)
169 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
173 static void amd_iommu_stats_init(void)
175 stats_dir = debugfs_create_dir("amd-iommu", NULL);
176 if (stats_dir == NULL)
179 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
180 (u32 *)&amd_iommu_isolate);
182 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
183 (u32 *)&amd_iommu_unmap_flush);
185 amd_iommu_stats_add(&compl_wait);
186 amd_iommu_stats_add(&cnt_map_single);
187 amd_iommu_stats_add(&cnt_unmap_single);
188 amd_iommu_stats_add(&cnt_map_sg);
189 amd_iommu_stats_add(&cnt_unmap_sg);
190 amd_iommu_stats_add(&cnt_alloc_coherent);
191 amd_iommu_stats_add(&cnt_free_coherent);
192 amd_iommu_stats_add(&cross_page);
193 amd_iommu_stats_add(&domain_flush_single);
194 amd_iommu_stats_add(&domain_flush_all);
195 amd_iommu_stats_add(&alloced_io_mem);
196 amd_iommu_stats_add(&total_map_requests);
201 /****************************************************************************
203 * Interrupt handling functions
205 ****************************************************************************/
207 static void dump_dte_entry(u16 devid)
211 for (i = 0; i < 8; ++i)
212 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
213 amd_iommu_dev_table[devid].data[i]);
216 static void dump_command(unsigned long phys_addr)
218 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
221 for (i = 0; i < 4; ++i)
222 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
225 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
228 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
229 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
230 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
231 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
232 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
234 printk(KERN_ERR "AMD-Vi: Event logged [");
237 case EVENT_TYPE_ILL_DEV:
238 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
239 "address=0x%016llx flags=0x%04x]\n",
240 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
242 dump_dte_entry(devid);
244 case EVENT_TYPE_IO_FAULT:
245 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
246 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
247 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
248 domid, address, flags);
250 case EVENT_TYPE_DEV_TAB_ERR:
251 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
252 "address=0x%016llx flags=0x%04x]\n",
253 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
256 case EVENT_TYPE_PAGE_TAB_ERR:
257 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
258 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
259 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
260 domid, address, flags);
262 case EVENT_TYPE_ILL_CMD:
263 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
264 reset_iommu_command_buffer(iommu);
265 dump_command(address);
267 case EVENT_TYPE_CMD_HARD_ERR:
268 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
269 "flags=0x%04x]\n", address, flags);
271 case EVENT_TYPE_IOTLB_INV_TO:
272 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
273 "address=0x%016llx]\n",
274 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
277 case EVENT_TYPE_INV_DEV_REQ:
278 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
279 "address=0x%016llx flags=0x%04x]\n",
280 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
284 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
288 static void iommu_poll_events(struct amd_iommu *iommu)
293 spin_lock_irqsave(&iommu->lock, flags);
295 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
296 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
298 while (head != tail) {
299 iommu_print_event(iommu, iommu->evt_buf + head);
300 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
303 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
305 spin_unlock_irqrestore(&iommu->lock, flags);
308 irqreturn_t amd_iommu_int_handler(int irq, void *data)
310 struct amd_iommu *iommu;
312 for_each_iommu(iommu)
313 iommu_poll_events(iommu);
318 /****************************************************************************
320 * IOMMU command queuing functions
322 ****************************************************************************/
325 * Writes the command to the IOMMUs command buffer and informs the
326 * hardware about the new command. Must be called with iommu->lock held.
328 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
333 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
334 target = iommu->cmd_buf + tail;
335 memcpy_toio(target, cmd, sizeof(*cmd));
336 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
337 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
340 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
346 * General queuing function for commands. Takes iommu->lock and calls
347 * __iommu_queue_command().
349 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
354 spin_lock_irqsave(&iommu->lock, flags);
355 ret = __iommu_queue_command(iommu, cmd);
357 iommu->need_sync = true;
358 spin_unlock_irqrestore(&iommu->lock, flags);
364 * This function waits until an IOMMU has completed a completion
367 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
373 INC_STATS_COUNTER(compl_wait);
375 while (!ready && (i < EXIT_LOOP_COUNT)) {
377 /* wait for the bit to become one */
378 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
379 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
382 /* set bit back to zero */
383 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
384 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
386 if (unlikely(i == EXIT_LOOP_COUNT)) {
387 spin_unlock(&iommu->lock);
388 reset_iommu_command_buffer(iommu);
389 spin_lock(&iommu->lock);
394 * This function queues a completion wait command into the command
397 static int __iommu_completion_wait(struct amd_iommu *iommu)
399 struct iommu_cmd cmd;
401 memset(&cmd, 0, sizeof(cmd));
402 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
403 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
405 return __iommu_queue_command(iommu, &cmd);
409 * This function is called whenever we need to ensure that the IOMMU has
410 * completed execution of all commands we sent. It sends a
411 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
412 * us about that by writing a value to a physical address we pass with
415 static int iommu_completion_wait(struct amd_iommu *iommu)
420 spin_lock_irqsave(&iommu->lock, flags);
422 if (!iommu->need_sync)
425 ret = __iommu_completion_wait(iommu);
427 iommu->need_sync = false;
432 __iommu_wait_for_completion(iommu);
435 spin_unlock_irqrestore(&iommu->lock, flags);
440 static void iommu_flush_complete(struct protection_domain *domain)
444 for (i = 0; i < amd_iommus_present; ++i) {
445 if (!domain->dev_iommu[i])
449 * Devices of this domain are behind this IOMMU
450 * We need to wait for completion of all commands.
452 iommu_completion_wait(amd_iommus[i]);
457 * Command send function for invalidating a device table entry
459 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
461 struct iommu_cmd cmd;
464 BUG_ON(iommu == NULL);
466 memset(&cmd, 0, sizeof(cmd));
467 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
470 ret = iommu_queue_command(iommu, &cmd);
475 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
476 u16 domid, int pde, int s)
478 memset(cmd, 0, sizeof(*cmd));
479 address &= PAGE_MASK;
480 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
481 cmd->data[1] |= domid;
482 cmd->data[2] = lower_32_bits(address);
483 cmd->data[3] = upper_32_bits(address);
484 if (s) /* size bit - we flush more than one 4kb page */
485 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
486 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
487 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
491 * Generic command send function for invalidaing TLB entries
493 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
494 u64 address, u16 domid, int pde, int s)
496 struct iommu_cmd cmd;
499 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
501 ret = iommu_queue_command(iommu, &cmd);
507 * TLB invalidation function which is called from the mapping functions.
508 * It invalidates a single PTE if the range to flush is within a single
509 * page. Otherwise it flushes the whole TLB of the IOMMU.
511 static void __iommu_flush_pages(struct protection_domain *domain,
512 u64 address, size_t size, int pde)
515 unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE);
517 address &= PAGE_MASK;
521 * If we have to flush more than one page, flush all
522 * TLB entries for this domain
524 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
529 for (i = 0; i < amd_iommus_present; ++i) {
530 if (!domain->dev_iommu[i])
534 * Devices of this domain are behind this IOMMU
535 * We need a TLB flush
537 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
544 static void iommu_flush_pages(struct protection_domain *domain,
545 u64 address, size_t size)
547 __iommu_flush_pages(domain, address, size, 0);
550 /* Flush the whole IO/TLB for a given protection domain */
551 static void iommu_flush_tlb(struct protection_domain *domain)
553 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
556 /* Flush the whole IO/TLB for a given protection domain - including PDE */
557 static void iommu_flush_tlb_pde(struct protection_domain *domain)
559 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
563 * This function flushes all domains that have devices on the given IOMMU
565 static void flush_all_domains_on_iommu(struct amd_iommu *iommu)
567 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
568 struct protection_domain *domain;
571 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
573 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
574 if (domain->dev_iommu[iommu->index] == 0)
577 spin_lock(&domain->lock);
578 iommu_queue_inv_iommu_pages(iommu, address, domain->id, 1, 1);
579 iommu_flush_complete(domain);
580 spin_unlock(&domain->lock);
583 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
587 * This function uses heavy locking and may disable irqs for some time. But
588 * this is no issue because it is only called during resume.
590 void amd_iommu_flush_all_domains(void)
592 struct protection_domain *domain;
595 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
597 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
598 spin_lock(&domain->lock);
599 iommu_flush_tlb_pde(domain);
600 iommu_flush_complete(domain);
601 spin_unlock(&domain->lock);
604 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
607 static void flush_all_devices_for_iommu(struct amd_iommu *iommu)
611 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
612 if (iommu != amd_iommu_rlookup_table[i])
615 iommu_queue_inv_dev_entry(iommu, i);
616 iommu_completion_wait(iommu);
620 static void flush_devices_by_domain(struct protection_domain *domain)
622 struct amd_iommu *iommu;
625 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
626 if ((domain == NULL && amd_iommu_pd_table[i] == NULL) ||
627 (amd_iommu_pd_table[i] != domain))
630 iommu = amd_iommu_rlookup_table[i];
634 iommu_queue_inv_dev_entry(iommu, i);
635 iommu_completion_wait(iommu);
639 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
641 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
643 if (iommu->reset_in_progress)
644 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
646 iommu->reset_in_progress = true;
648 amd_iommu_reset_cmd_buffer(iommu);
649 flush_all_devices_for_iommu(iommu);
650 flush_all_domains_on_iommu(iommu);
652 iommu->reset_in_progress = false;
655 void amd_iommu_flush_all_devices(void)
657 flush_devices_by_domain(NULL);
660 /****************************************************************************
662 * The functions below are used the create the page table mappings for
663 * unity mapped regions.
665 ****************************************************************************/
668 * Generic mapping functions. It maps a physical address into a DMA
669 * address space. It allocates the page table pages if necessary.
670 * In the future it can be extended to a generic mapping function
671 * supporting all features of AMD IOMMU page tables like level skipping
672 * and full 64 bit address spaces.
674 static int iommu_map_page(struct protection_domain *dom,
675 unsigned long bus_addr,
676 unsigned long phys_addr,
682 bus_addr = PAGE_ALIGN(bus_addr);
683 phys_addr = PAGE_ALIGN(phys_addr);
685 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
686 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
688 if (!(prot & IOMMU_PROT_MASK))
691 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
693 if (IOMMU_PTE_PRESENT(*pte))
696 __pte = phys_addr | IOMMU_PTE_P;
697 if (prot & IOMMU_PROT_IR)
698 __pte |= IOMMU_PTE_IR;
699 if (prot & IOMMU_PROT_IW)
700 __pte |= IOMMU_PTE_IW;
709 static void iommu_unmap_page(struct protection_domain *dom,
710 unsigned long bus_addr, int map_size)
712 u64 *pte = fetch_pte(dom, bus_addr, map_size);
719 * This function checks if a specific unity mapping entry is needed for
720 * this specific IOMMU.
722 static int iommu_for_unity_map(struct amd_iommu *iommu,
723 struct unity_map_entry *entry)
727 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
728 bdf = amd_iommu_alias_table[i];
729 if (amd_iommu_rlookup_table[bdf] == iommu)
737 * Init the unity mappings for a specific IOMMU in the system
739 * Basically iterates over all unity mapping entries and applies them to
740 * the default domain DMA of that IOMMU if necessary.
742 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
744 struct unity_map_entry *entry;
747 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
748 if (!iommu_for_unity_map(iommu, entry))
750 ret = dma_ops_unity_map(iommu->default_dom, entry);
759 * This function actually applies the mapping to the page table of the
762 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
763 struct unity_map_entry *e)
768 for (addr = e->address_start; addr < e->address_end;
770 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
775 * if unity mapping is in aperture range mark the page
776 * as allocated in the aperture
778 if (addr < dma_dom->aperture_size)
779 __set_bit(addr >> PAGE_SHIFT,
780 dma_dom->aperture[0]->bitmap);
787 * Inits the unity mappings required for a specific device
789 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
792 struct unity_map_entry *e;
795 list_for_each_entry(e, &amd_iommu_unity_map, list) {
796 if (!(devid >= e->devid_start && devid <= e->devid_end))
798 ret = dma_ops_unity_map(dma_dom, e);
806 /****************************************************************************
808 * The next functions belong to the address allocator for the dma_ops
809 * interface functions. They work like the allocators in the other IOMMU
810 * drivers. Its basically a bitmap which marks the allocated pages in
811 * the aperture. Maybe it could be enhanced in the future to a more
812 * efficient allocator.
814 ****************************************************************************/
817 * The address allocator core functions.
819 * called with domain->lock held
823 * This function checks if there is a PTE for a given dma address. If
824 * there is one, it returns the pointer to it.
826 static u64 *fetch_pte(struct protection_domain *domain,
827 unsigned long address, int map_size)
832 level = domain->mode - 1;
833 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
835 while (level > map_size) {
836 if (!IOMMU_PTE_PRESENT(*pte))
841 pte = IOMMU_PTE_PAGE(*pte);
842 pte = &pte[PM_LEVEL_INDEX(level, address)];
844 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
854 * This function is used to add a new aperture range to an existing
855 * aperture in case of dma_ops domain allocation or address allocation
858 static int alloc_new_range(struct dma_ops_domain *dma_dom,
859 bool populate, gfp_t gfp)
861 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
862 struct amd_iommu *iommu;
865 #ifdef CONFIG_IOMMU_STRESS
869 if (index >= APERTURE_MAX_RANGES)
872 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
873 if (!dma_dom->aperture[index])
876 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
877 if (!dma_dom->aperture[index]->bitmap)
880 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
883 unsigned long address = dma_dom->aperture_size;
884 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
887 for (i = 0; i < num_ptes; ++i) {
888 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
893 dma_dom->aperture[index]->pte_pages[i] = pte_page;
895 address += APERTURE_RANGE_SIZE / 64;
899 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
901 /* Intialize the exclusion range if necessary */
902 for_each_iommu(iommu) {
903 if (iommu->exclusion_start &&
904 iommu->exclusion_start >= dma_dom->aperture[index]->offset
905 && iommu->exclusion_start < dma_dom->aperture_size) {
906 unsigned long startpage;
907 int pages = iommu_num_pages(iommu->exclusion_start,
908 iommu->exclusion_length,
910 startpage = iommu->exclusion_start >> PAGE_SHIFT;
911 dma_ops_reserve_addresses(dma_dom, startpage, pages);
916 * Check for areas already mapped as present in the new aperture
917 * range and mark those pages as reserved in the allocator. Such
918 * mappings may already exist as a result of requested unity
919 * mappings for devices.
921 for (i = dma_dom->aperture[index]->offset;
922 i < dma_dom->aperture_size;
924 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
925 if (!pte || !IOMMU_PTE_PRESENT(*pte))
928 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
931 update_domain(&dma_dom->domain);
936 update_domain(&dma_dom->domain);
938 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
940 kfree(dma_dom->aperture[index]);
941 dma_dom->aperture[index] = NULL;
946 static unsigned long dma_ops_area_alloc(struct device *dev,
947 struct dma_ops_domain *dom,
949 unsigned long align_mask,
953 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
954 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
955 int i = start >> APERTURE_RANGE_SHIFT;
956 unsigned long boundary_size;
957 unsigned long address = -1;
960 next_bit >>= PAGE_SHIFT;
962 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
963 PAGE_SIZE) >> PAGE_SHIFT;
965 for (;i < max_index; ++i) {
966 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
968 if (dom->aperture[i]->offset >= dma_mask)
971 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
972 dma_mask >> PAGE_SHIFT);
974 address = iommu_area_alloc(dom->aperture[i]->bitmap,
975 limit, next_bit, pages, 0,
976 boundary_size, align_mask);
978 address = dom->aperture[i]->offset +
979 (address << PAGE_SHIFT);
980 dom->next_address = address + (pages << PAGE_SHIFT);
990 static unsigned long dma_ops_alloc_addresses(struct device *dev,
991 struct dma_ops_domain *dom,
993 unsigned long align_mask,
996 unsigned long address;
998 #ifdef CONFIG_IOMMU_STRESS
999 dom->next_address = 0;
1000 dom->need_flush = true;
1003 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1004 dma_mask, dom->next_address);
1006 if (address == -1) {
1007 dom->next_address = 0;
1008 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1010 dom->need_flush = true;
1013 if (unlikely(address == -1))
1014 address = DMA_ERROR_CODE;
1016 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1022 * The address free function.
1024 * called with domain->lock held
1026 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1027 unsigned long address,
1030 unsigned i = address >> APERTURE_RANGE_SHIFT;
1031 struct aperture_range *range = dom->aperture[i];
1033 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1035 #ifdef CONFIG_IOMMU_STRESS
1040 if (address >= dom->next_address)
1041 dom->need_flush = true;
1043 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1045 iommu_area_free(range->bitmap, address, pages);
1049 /****************************************************************************
1051 * The next functions belong to the domain allocation. A domain is
1052 * allocated for every IOMMU as the default domain. If device isolation
1053 * is enabled, every device get its own domain. The most important thing
1054 * about domains is the page table mapping the DMA address space they
1057 ****************************************************************************/
1060 * This function adds a protection domain to the global protection domain list
1062 static void add_domain_to_list(struct protection_domain *domain)
1064 unsigned long flags;
1066 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1067 list_add(&domain->list, &amd_iommu_pd_list);
1068 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1072 * This function removes a protection domain to the global
1073 * protection domain list
1075 static void del_domain_from_list(struct protection_domain *domain)
1077 unsigned long flags;
1079 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1080 list_del(&domain->list);
1081 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1084 static u16 domain_id_alloc(void)
1086 unsigned long flags;
1089 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1090 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1092 if (id > 0 && id < MAX_DOMAIN_ID)
1093 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1096 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1101 static void domain_id_free(int id)
1103 unsigned long flags;
1105 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1106 if (id > 0 && id < MAX_DOMAIN_ID)
1107 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1108 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1112 * Used to reserve address ranges in the aperture (e.g. for exclusion
1115 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1116 unsigned long start_page,
1119 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1121 if (start_page + pages > last_page)
1122 pages = last_page - start_page;
1124 for (i = start_page; i < start_page + pages; ++i) {
1125 int index = i / APERTURE_RANGE_PAGES;
1126 int page = i % APERTURE_RANGE_PAGES;
1127 __set_bit(page, dom->aperture[index]->bitmap);
1131 static void free_pagetable(struct protection_domain *domain)
1136 p1 = domain->pt_root;
1141 for (i = 0; i < 512; ++i) {
1142 if (!IOMMU_PTE_PRESENT(p1[i]))
1145 p2 = IOMMU_PTE_PAGE(p1[i]);
1146 for (j = 0; j < 512; ++j) {
1147 if (!IOMMU_PTE_PRESENT(p2[j]))
1149 p3 = IOMMU_PTE_PAGE(p2[j]);
1150 free_page((unsigned long)p3);
1153 free_page((unsigned long)p2);
1156 free_page((unsigned long)p1);
1158 domain->pt_root = NULL;
1162 * Free a domain, only used if something went wrong in the
1163 * allocation path and we need to free an already allocated page table
1165 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1172 del_domain_from_list(&dom->domain);
1174 free_pagetable(&dom->domain);
1176 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1177 if (!dom->aperture[i])
1179 free_page((unsigned long)dom->aperture[i]->bitmap);
1180 kfree(dom->aperture[i]);
1187 * Allocates a new protection domain usable for the dma_ops functions.
1188 * It also intializes the page table and the address allocator data
1189 * structures required for the dma_ops interface
1191 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1193 struct dma_ops_domain *dma_dom;
1195 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1199 spin_lock_init(&dma_dom->domain.lock);
1201 dma_dom->domain.id = domain_id_alloc();
1202 if (dma_dom->domain.id == 0)
1204 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1205 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1206 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1207 dma_dom->domain.priv = dma_dom;
1208 if (!dma_dom->domain.pt_root)
1211 dma_dom->need_flush = false;
1212 dma_dom->target_dev = 0xffff;
1214 add_domain_to_list(&dma_dom->domain);
1216 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1220 * mark the first page as allocated so we never return 0 as
1221 * a valid dma-address. So we can use 0 as error value
1223 dma_dom->aperture[0]->bitmap[0] = 1;
1224 dma_dom->next_address = 0;
1230 dma_ops_domain_free(dma_dom);
1236 * little helper function to check whether a given protection domain is a
1239 static bool dma_ops_domain(struct protection_domain *domain)
1241 return domain->flags & PD_DMA_OPS_MASK;
1244 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1246 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1247 u64 pte_root = virt_to_phys(domain->pt_root);
1249 BUG_ON(amd_iommu_pd_table[devid] != NULL);
1251 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1252 << DEV_ENTRY_MODE_SHIFT;
1253 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1255 amd_iommu_dev_table[devid].data[2] = domain->id;
1256 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1257 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1259 amd_iommu_pd_table[devid] = domain;
1261 /* Do reference counting */
1262 domain->dev_iommu[iommu->index] += 1;
1263 domain->dev_cnt += 1;
1265 /* Flush the changes DTE entry */
1266 iommu_queue_inv_dev_entry(iommu, devid);
1269 static void clear_dte_entry(u16 devid)
1271 struct protection_domain *domain = amd_iommu_pd_table[devid];
1272 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1274 BUG_ON(domain == NULL);
1276 /* remove domain from the lookup table */
1277 amd_iommu_pd_table[devid] = NULL;
1279 /* remove entry from the device table seen by the hardware */
1280 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1281 amd_iommu_dev_table[devid].data[1] = 0;
1282 amd_iommu_dev_table[devid].data[2] = 0;
1284 amd_iommu_apply_erratum_63(devid);
1286 /* decrease reference counters */
1287 domain->dev_iommu[iommu->index] -= 1;
1288 domain->dev_cnt -= 1;
1290 iommu_queue_inv_dev_entry(iommu, devid);
1294 * If a device is not yet associated with a domain, this function does
1295 * assigns it visible for the hardware
1297 static int __attach_device(struct device *dev,
1298 struct protection_domain *domain)
1300 u16 devid = get_device_id(dev);
1301 u16 alias = amd_iommu_alias_table[devid];
1304 spin_lock(&domain->lock);
1306 /* Some sanity checks */
1307 if (amd_iommu_pd_table[alias] != NULL &&
1308 amd_iommu_pd_table[alias] != domain)
1311 if (amd_iommu_pd_table[devid] != NULL &&
1312 amd_iommu_pd_table[devid] != domain)
1315 /* Do real assignment */
1316 if (alias != devid &&
1317 amd_iommu_pd_table[alias] == NULL)
1318 set_dte_entry(alias, domain);
1320 if (amd_iommu_pd_table[devid] == NULL)
1321 set_dte_entry(devid, domain);
1324 spin_unlock(&domain->lock);
1330 * If a device is not yet associated with a domain, this function does
1331 * assigns it visible for the hardware
1333 static int attach_device(struct device *dev,
1334 struct protection_domain *domain)
1336 unsigned long flags;
1339 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1340 ret = __attach_device(dev, domain);
1341 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1344 * We might boot into a crash-kernel here. The crashed kernel
1345 * left the caches in the IOMMU dirty. So we have to flush
1346 * here to evict all dirty stuff.
1348 iommu_flush_tlb_pde(domain);
1354 * Removes a device from a protection domain (unlocked)
1356 static void __detach_device(struct device *dev)
1358 u16 devid = get_device_id(dev);
1359 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1363 clear_dte_entry(devid);
1366 * If we run in passthrough mode the device must be assigned to the
1367 * passthrough domain if it is detached from any other domain
1369 if (iommu_pass_through)
1370 __attach_device(dev, pt_domain);
1374 * Removes a device from a protection domain (with devtable_lock held)
1376 static void detach_device(struct device *dev)
1378 unsigned long flags;
1380 /* lock device table */
1381 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1382 __detach_device(dev);
1383 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1387 * Find out the protection domain structure for a given PCI device. This
1388 * will give us the pointer to the page table root for example.
1390 static struct protection_domain *domain_for_device(struct device *dev)
1392 struct protection_domain *dom;
1393 unsigned long flags;
1396 devid = get_device_id(dev);
1397 alias = amd_iommu_alias_table[devid];
1399 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1400 dom = amd_iommu_pd_table[devid];
1402 amd_iommu_pd_table[alias] != NULL) {
1403 __attach_device(dev, amd_iommu_pd_table[alias]);
1404 dom = amd_iommu_pd_table[devid];
1407 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1412 static int device_change_notifier(struct notifier_block *nb,
1413 unsigned long action, void *data)
1415 struct device *dev = data;
1417 struct protection_domain *domain;
1418 struct dma_ops_domain *dma_domain;
1419 struct amd_iommu *iommu;
1420 unsigned long flags;
1422 if (!check_device(dev))
1425 devid = get_device_id(dev);
1426 iommu = amd_iommu_rlookup_table[devid];
1427 domain = domain_for_device(dev);
1429 if (domain && !dma_ops_domain(domain))
1430 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1431 "to a non-dma-ops domain\n", dev_name(dev));
1434 case BUS_NOTIFY_UNBOUND_DRIVER:
1437 if (iommu_pass_through)
1441 case BUS_NOTIFY_ADD_DEVICE:
1442 /* allocate a protection domain if a device is added */
1443 dma_domain = find_protection_domain(devid);
1446 dma_domain = dma_ops_domain_alloc();
1449 dma_domain->target_dev = devid;
1451 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1452 list_add_tail(&dma_domain->list, &iommu_pd_list);
1453 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1460 iommu_queue_inv_dev_entry(iommu, devid);
1461 iommu_completion_wait(iommu);
1467 static struct notifier_block device_nb = {
1468 .notifier_call = device_change_notifier,
1471 /*****************************************************************************
1473 * The next functions belong to the dma_ops mapping/unmapping code.
1475 *****************************************************************************/
1478 * In the dma_ops path we only have the struct device. This function
1479 * finds the corresponding IOMMU, the protection domain and the
1480 * requestor id for a given device.
1481 * If the device is not yet associated with a domain this is also done
1484 static struct protection_domain *get_domain(struct device *dev)
1486 struct protection_domain *domain;
1487 struct dma_ops_domain *dma_dom;
1488 u16 devid = get_device_id(dev);
1490 if (!check_device(dev))
1491 return ERR_PTR(-EINVAL);
1493 domain = domain_for_device(dev);
1494 if (domain != NULL && !dma_ops_domain(domain))
1495 return ERR_PTR(-EBUSY);
1500 /* Device not bount yet - bind it */
1501 dma_dom = find_protection_domain(devid);
1503 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1504 attach_device(dev, &dma_dom->domain);
1505 DUMP_printk("Using protection domain %d for device %s\n",
1506 dma_dom->domain.id, dev_name(dev));
1508 return &dma_dom->domain;
1511 static void update_device_table(struct protection_domain *domain)
1513 unsigned long flags;
1516 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
1517 if (amd_iommu_pd_table[i] != domain)
1519 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1520 set_dte_entry(i, domain);
1521 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1525 static void update_domain(struct protection_domain *domain)
1527 if (!domain->updated)
1530 update_device_table(domain);
1531 flush_devices_by_domain(domain);
1532 iommu_flush_tlb_pde(domain);
1534 domain->updated = false;
1538 * This function is used to add another level to an IO page table. Adding
1539 * another level increases the size of the address space by 9 bits to a size up
1542 static bool increase_address_space(struct protection_domain *domain,
1547 if (domain->mode == PAGE_MODE_6_LEVEL)
1548 /* address space already 64 bit large */
1551 pte = (void *)get_zeroed_page(gfp);
1555 *pte = PM_LEVEL_PDE(domain->mode,
1556 virt_to_phys(domain->pt_root));
1557 domain->pt_root = pte;
1559 domain->updated = true;
1564 static u64 *alloc_pte(struct protection_domain *domain,
1565 unsigned long address,
1573 while (address > PM_LEVEL_SIZE(domain->mode))
1574 increase_address_space(domain, gfp);
1576 level = domain->mode - 1;
1577 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1579 while (level > end_lvl) {
1580 if (!IOMMU_PTE_PRESENT(*pte)) {
1581 page = (u64 *)get_zeroed_page(gfp);
1584 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1589 pte = IOMMU_PTE_PAGE(*pte);
1591 if (pte_page && level == end_lvl)
1594 pte = &pte[PM_LEVEL_INDEX(level, address)];
1601 * This function fetches the PTE for a given address in the aperture
1603 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1604 unsigned long address)
1606 struct aperture_range *aperture;
1607 u64 *pte, *pte_page;
1609 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1613 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1615 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1617 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1619 pte += PM_LEVEL_INDEX(0, address);
1621 update_domain(&dom->domain);
1627 * This is the generic map function. It maps one 4kb page at paddr to
1628 * the given address in the DMA address space for the domain.
1630 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1631 unsigned long address,
1637 WARN_ON(address > dom->aperture_size);
1641 pte = dma_ops_get_pte(dom, address);
1643 return DMA_ERROR_CODE;
1645 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1647 if (direction == DMA_TO_DEVICE)
1648 __pte |= IOMMU_PTE_IR;
1649 else if (direction == DMA_FROM_DEVICE)
1650 __pte |= IOMMU_PTE_IW;
1651 else if (direction == DMA_BIDIRECTIONAL)
1652 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1658 return (dma_addr_t)address;
1662 * The generic unmapping function for on page in the DMA address space.
1664 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1665 unsigned long address)
1667 struct aperture_range *aperture;
1670 if (address >= dom->aperture_size)
1673 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1677 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1681 pte += PM_LEVEL_INDEX(0, address);
1689 * This function contains common code for mapping of a physically
1690 * contiguous memory region into DMA address space. It is used by all
1691 * mapping functions provided with this IOMMU driver.
1692 * Must be called with the domain lock held.
1694 static dma_addr_t __map_single(struct device *dev,
1695 struct dma_ops_domain *dma_dom,
1702 dma_addr_t offset = paddr & ~PAGE_MASK;
1703 dma_addr_t address, start, ret;
1705 unsigned long align_mask = 0;
1708 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1711 INC_STATS_COUNTER(total_map_requests);
1714 INC_STATS_COUNTER(cross_page);
1717 align_mask = (1UL << get_order(size)) - 1;
1720 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1722 if (unlikely(address == DMA_ERROR_CODE)) {
1724 * setting next_address here will let the address
1725 * allocator only scan the new allocated range in the
1726 * first run. This is a small optimization.
1728 dma_dom->next_address = dma_dom->aperture_size;
1730 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1734 * aperture was sucessfully enlarged by 128 MB, try
1741 for (i = 0; i < pages; ++i) {
1742 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1743 if (ret == DMA_ERROR_CODE)
1751 ADD_STATS_COUNTER(alloced_io_mem, size);
1753 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1754 iommu_flush_tlb(&dma_dom->domain);
1755 dma_dom->need_flush = false;
1756 } else if (unlikely(amd_iommu_np_cache))
1757 iommu_flush_pages(&dma_dom->domain, address, size);
1764 for (--i; i >= 0; --i) {
1766 dma_ops_domain_unmap(dma_dom, start);
1769 dma_ops_free_addresses(dma_dom, address, pages);
1771 return DMA_ERROR_CODE;
1775 * Does the reverse of the __map_single function. Must be called with
1776 * the domain lock held too
1778 static void __unmap_single(struct dma_ops_domain *dma_dom,
1779 dma_addr_t dma_addr,
1783 dma_addr_t i, start;
1786 if ((dma_addr == DMA_ERROR_CODE) ||
1787 (dma_addr + size > dma_dom->aperture_size))
1790 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1791 dma_addr &= PAGE_MASK;
1794 for (i = 0; i < pages; ++i) {
1795 dma_ops_domain_unmap(dma_dom, start);
1799 SUB_STATS_COUNTER(alloced_io_mem, size);
1801 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1803 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1804 iommu_flush_pages(&dma_dom->domain, dma_addr, size);
1805 dma_dom->need_flush = false;
1810 * The exported map_single function for dma_ops.
1812 static dma_addr_t map_page(struct device *dev, struct page *page,
1813 unsigned long offset, size_t size,
1814 enum dma_data_direction dir,
1815 struct dma_attrs *attrs)
1817 unsigned long flags;
1818 struct protection_domain *domain;
1821 phys_addr_t paddr = page_to_phys(page) + offset;
1823 INC_STATS_COUNTER(cnt_map_single);
1825 domain = get_domain(dev);
1826 if (PTR_ERR(domain) == -EINVAL)
1827 return (dma_addr_t)paddr;
1828 else if (IS_ERR(domain))
1829 return DMA_ERROR_CODE;
1831 dma_mask = *dev->dma_mask;
1833 spin_lock_irqsave(&domain->lock, flags);
1835 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1837 if (addr == DMA_ERROR_CODE)
1840 iommu_flush_complete(domain);
1843 spin_unlock_irqrestore(&domain->lock, flags);
1849 * The exported unmap_single function for dma_ops.
1851 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1852 enum dma_data_direction dir, struct dma_attrs *attrs)
1854 unsigned long flags;
1855 struct protection_domain *domain;
1857 INC_STATS_COUNTER(cnt_unmap_single);
1859 domain = get_domain(dev);
1863 spin_lock_irqsave(&domain->lock, flags);
1865 __unmap_single(domain->priv, dma_addr, size, dir);
1867 iommu_flush_complete(domain);
1869 spin_unlock_irqrestore(&domain->lock, flags);
1873 * This is a special map_sg function which is used if we should map a
1874 * device which is not handled by an AMD IOMMU in the system.
1876 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1877 int nelems, int dir)
1879 struct scatterlist *s;
1882 for_each_sg(sglist, s, nelems, i) {
1883 s->dma_address = (dma_addr_t)sg_phys(s);
1884 s->dma_length = s->length;
1891 * The exported map_sg function for dma_ops (handles scatter-gather
1894 static int map_sg(struct device *dev, struct scatterlist *sglist,
1895 int nelems, enum dma_data_direction dir,
1896 struct dma_attrs *attrs)
1898 unsigned long flags;
1899 struct protection_domain *domain;
1901 struct scatterlist *s;
1903 int mapped_elems = 0;
1906 INC_STATS_COUNTER(cnt_map_sg);
1908 domain = get_domain(dev);
1909 if (PTR_ERR(domain) == -EINVAL)
1910 return map_sg_no_iommu(dev, sglist, nelems, dir);
1911 else if (IS_ERR(domain))
1914 dma_mask = *dev->dma_mask;
1916 spin_lock_irqsave(&domain->lock, flags);
1918 for_each_sg(sglist, s, nelems, i) {
1921 s->dma_address = __map_single(dev, domain->priv,
1922 paddr, s->length, dir, false,
1925 if (s->dma_address) {
1926 s->dma_length = s->length;
1932 iommu_flush_complete(domain);
1935 spin_unlock_irqrestore(&domain->lock, flags);
1937 return mapped_elems;
1939 for_each_sg(sglist, s, mapped_elems, i) {
1941 __unmap_single(domain->priv, s->dma_address,
1942 s->dma_length, dir);
1943 s->dma_address = s->dma_length = 0;
1952 * The exported map_sg function for dma_ops (handles scatter-gather
1955 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1956 int nelems, enum dma_data_direction dir,
1957 struct dma_attrs *attrs)
1959 unsigned long flags;
1960 struct protection_domain *domain;
1961 struct scatterlist *s;
1964 INC_STATS_COUNTER(cnt_unmap_sg);
1966 domain = get_domain(dev);
1970 spin_lock_irqsave(&domain->lock, flags);
1972 for_each_sg(sglist, s, nelems, i) {
1973 __unmap_single(domain->priv, s->dma_address,
1974 s->dma_length, dir);
1975 s->dma_address = s->dma_length = 0;
1978 iommu_flush_complete(domain);
1980 spin_unlock_irqrestore(&domain->lock, flags);
1984 * The exported alloc_coherent function for dma_ops.
1986 static void *alloc_coherent(struct device *dev, size_t size,
1987 dma_addr_t *dma_addr, gfp_t flag)
1989 unsigned long flags;
1991 struct protection_domain *domain;
1993 u64 dma_mask = dev->coherent_dma_mask;
1995 INC_STATS_COUNTER(cnt_alloc_coherent);
1997 domain = get_domain(dev);
1998 if (PTR_ERR(domain) == -EINVAL) {
1999 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2000 *dma_addr = __pa(virt_addr);
2002 } else if (IS_ERR(domain))
2005 dma_mask = dev->coherent_dma_mask;
2006 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2009 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2013 paddr = virt_to_phys(virt_addr);
2016 dma_mask = *dev->dma_mask;
2018 spin_lock_irqsave(&domain->lock, flags);
2020 *dma_addr = __map_single(dev, domain->priv, paddr,
2021 size, DMA_BIDIRECTIONAL, true, dma_mask);
2023 if (*dma_addr == DMA_ERROR_CODE) {
2024 spin_unlock_irqrestore(&domain->lock, flags);
2028 iommu_flush_complete(domain);
2030 spin_unlock_irqrestore(&domain->lock, flags);
2036 free_pages((unsigned long)virt_addr, get_order(size));
2042 * The exported free_coherent function for dma_ops.
2044 static void free_coherent(struct device *dev, size_t size,
2045 void *virt_addr, dma_addr_t dma_addr)
2047 unsigned long flags;
2048 struct protection_domain *domain;
2050 INC_STATS_COUNTER(cnt_free_coherent);
2052 domain = get_domain(dev);
2056 spin_lock_irqsave(&domain->lock, flags);
2058 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2060 iommu_flush_complete(domain);
2062 spin_unlock_irqrestore(&domain->lock, flags);
2065 free_pages((unsigned long)virt_addr, get_order(size));
2069 * This function is called by the DMA layer to find out if we can handle a
2070 * particular device. It is part of the dma_ops.
2072 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2074 return check_device(dev);
2078 * The function for pre-allocating protection domains.
2080 * If the driver core informs the DMA layer if a driver grabs a device
2081 * we don't need to preallocate the protection domains anymore.
2082 * For now we have to.
2084 static void prealloc_protection_domains(void)
2086 struct pci_dev *dev = NULL;
2087 struct dma_ops_domain *dma_dom;
2090 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2092 /* Do we handle this device? */
2093 if (!check_device(&dev->dev))
2096 /* Is there already any domain for it? */
2097 if (domain_for_device(&dev->dev))
2100 devid = get_device_id(&dev->dev);
2102 dma_dom = dma_ops_domain_alloc();
2105 init_unity_mappings_for_device(dma_dom, devid);
2106 dma_dom->target_dev = devid;
2108 attach_device(&dev->dev, &dma_dom->domain);
2110 list_add_tail(&dma_dom->list, &iommu_pd_list);
2114 static struct dma_map_ops amd_iommu_dma_ops = {
2115 .alloc_coherent = alloc_coherent,
2116 .free_coherent = free_coherent,
2117 .map_page = map_page,
2118 .unmap_page = unmap_page,
2120 .unmap_sg = unmap_sg,
2121 .dma_supported = amd_iommu_dma_supported,
2125 * The function which clues the AMD IOMMU driver into dma_ops.
2127 int __init amd_iommu_init_dma_ops(void)
2129 struct amd_iommu *iommu;
2133 * first allocate a default protection domain for every IOMMU we
2134 * found in the system. Devices not assigned to any other
2135 * protection domain will be assigned to the default one.
2137 for_each_iommu(iommu) {
2138 iommu->default_dom = dma_ops_domain_alloc();
2139 if (iommu->default_dom == NULL)
2141 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2142 ret = iommu_init_unity_mappings(iommu);
2148 * If device isolation is enabled, pre-allocate the protection
2149 * domains for each device.
2151 if (amd_iommu_isolate)
2152 prealloc_protection_domains();
2156 #ifdef CONFIG_GART_IOMMU
2157 gart_iommu_aperture_disabled = 1;
2158 gart_iommu_aperture = 0;
2161 /* Make the driver finally visible to the drivers */
2162 dma_ops = &amd_iommu_dma_ops;
2164 register_iommu(&amd_iommu_ops);
2166 bus_register_notifier(&pci_bus_type, &device_nb);
2168 amd_iommu_stats_init();
2174 for_each_iommu(iommu) {
2175 if (iommu->default_dom)
2176 dma_ops_domain_free(iommu->default_dom);
2182 /*****************************************************************************
2184 * The following functions belong to the exported interface of AMD IOMMU
2186 * This interface allows access to lower level functions of the IOMMU
2187 * like protection domain handling and assignement of devices to domains
2188 * which is not possible with the dma_ops interface.
2190 *****************************************************************************/
2192 static void cleanup_domain(struct protection_domain *domain)
2194 unsigned long flags;
2197 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2199 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2200 if (amd_iommu_pd_table[devid] == domain)
2201 clear_dte_entry(devid);
2203 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2206 static void protection_domain_free(struct protection_domain *domain)
2211 del_domain_from_list(domain);
2214 domain_id_free(domain->id);
2219 static struct protection_domain *protection_domain_alloc(void)
2221 struct protection_domain *domain;
2223 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2227 spin_lock_init(&domain->lock);
2228 domain->id = domain_id_alloc();
2232 add_domain_to_list(domain);
2242 static int amd_iommu_domain_init(struct iommu_domain *dom)
2244 struct protection_domain *domain;
2246 domain = protection_domain_alloc();
2250 domain->mode = PAGE_MODE_3_LEVEL;
2251 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2252 if (!domain->pt_root)
2260 protection_domain_free(domain);
2265 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2267 struct protection_domain *domain = dom->priv;
2272 if (domain->dev_cnt > 0)
2273 cleanup_domain(domain);
2275 BUG_ON(domain->dev_cnt != 0);
2277 free_pagetable(domain);
2279 domain_id_free(domain->id);
2286 static void amd_iommu_detach_device(struct iommu_domain *dom,
2289 struct amd_iommu *iommu;
2292 if (!check_device(dev))
2295 devid = get_device_id(dev);
2297 if (amd_iommu_pd_table[devid] != NULL)
2300 iommu = amd_iommu_rlookup_table[devid];
2304 iommu_queue_inv_dev_entry(iommu, devid);
2305 iommu_completion_wait(iommu);
2308 static int amd_iommu_attach_device(struct iommu_domain *dom,
2311 struct protection_domain *domain = dom->priv;
2312 struct protection_domain *old_domain;
2313 struct amd_iommu *iommu;
2317 if (!check_device(dev))
2320 devid = get_device_id(dev);
2322 iommu = amd_iommu_rlookup_table[devid];
2326 old_domain = amd_iommu_pd_table[devid];
2330 ret = attach_device(dev, domain);
2332 iommu_completion_wait(iommu);
2337 static int amd_iommu_map_range(struct iommu_domain *dom,
2338 unsigned long iova, phys_addr_t paddr,
2339 size_t size, int iommu_prot)
2341 struct protection_domain *domain = dom->priv;
2342 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2346 if (iommu_prot & IOMMU_READ)
2347 prot |= IOMMU_PROT_IR;
2348 if (iommu_prot & IOMMU_WRITE)
2349 prot |= IOMMU_PROT_IW;
2354 for (i = 0; i < npages; ++i) {
2355 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2366 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2367 unsigned long iova, size_t size)
2370 struct protection_domain *domain = dom->priv;
2371 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2375 for (i = 0; i < npages; ++i) {
2376 iommu_unmap_page(domain, iova, PM_MAP_4k);
2380 iommu_flush_tlb_pde(domain);
2383 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2386 struct protection_domain *domain = dom->priv;
2387 unsigned long offset = iova & ~PAGE_MASK;
2391 pte = fetch_pte(domain, iova, PM_MAP_4k);
2393 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2396 paddr = *pte & IOMMU_PAGE_MASK;
2402 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2408 static struct iommu_ops amd_iommu_ops = {
2409 .domain_init = amd_iommu_domain_init,
2410 .domain_destroy = amd_iommu_domain_destroy,
2411 .attach_dev = amd_iommu_attach_device,
2412 .detach_dev = amd_iommu_detach_device,
2413 .map = amd_iommu_map_range,
2414 .unmap = amd_iommu_unmap_range,
2415 .iova_to_phys = amd_iommu_iova_to_phys,
2416 .domain_has_cap = amd_iommu_domain_has_cap,
2419 /*****************************************************************************
2421 * The next functions do a basic initialization of IOMMU for pass through
2424 * In passthrough mode the IOMMU is initialized and enabled but not used for
2425 * DMA-API translation.
2427 *****************************************************************************/
2429 int __init amd_iommu_init_passthrough(void)
2431 struct amd_iommu *iommu;
2432 struct pci_dev *dev = NULL;
2435 /* allocate passthroug domain */
2436 pt_domain = protection_domain_alloc();
2440 pt_domain->mode |= PAGE_MODE_NONE;
2442 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2444 if (!check_device(&dev->dev))
2447 devid = get_device_id(&dev->dev);
2449 iommu = amd_iommu_rlookup_table[devid];
2453 attach_device(&dev->dev, pt_domain);
2456 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");