arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19
  20 #include <asm/bugs.h>
  21 #include <asm/cpu.h>
  22 #include <asm/fpu.h>
  23 #include <asm/mipsregs.h>
  24 #include <asm/system.h>
  25 #include <asm/watch.h>
  26
  27 /*
  28  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  29  * the implementation of the "wait" feature differs between CPU families. This
  30  * points to the function that implements CPU specific wait.
  31  * The wait instruction stops the pipeline and reduces the power consumption of
  32  * the CPU very much.
  33  */
  34 void (*cpu_wait)(void);
  35
  36 static void r3081_wait(void)
  37 {
  38         unsigned long cfg = read_c0_conf();
  39         write_c0_conf(cfg | R30XX_CONF_HALT);
  40 }
  41
  42 static void r39xx_wait(void)
  43 {
  44         local_irq_disable();
  45         if (!need_resched())
  46                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  47         local_irq_enable();
  48 }
  49
  50 extern void r4k_wait(void);
  51
  52 /*
  53  * This variant is preferable as it allows testing need_resched and going to
  54  * sleep depending on the outcome atomically.  Unfortunately the "It is
  55  * implementation-dependent whether the pipeline restarts when a non-enabled
  56  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  57  * using this version a gamble.
  58  */
  59 void r4k_wait_irqoff(void)
  60 {
  61         local_irq_disable();
  62         if (!need_resched())
  63                 __asm__("       .set    push            \n"
  64                         "       .set    mips3           \n"
  65                         "       wait                    \n"
  66                         "       .set    pop             \n");
  67         local_irq_enable();
  68         __asm__("       .globl __pastwait       \n"
  69                 "__pastwait:                    \n");
  70         return;
  71 }
  72
  73 /*
  74  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  75  * have any pending stores when the WAIT instruction is executed.
  76  */
  77 static void rm7k_wait_irqoff(void)
  78 {
  79         local_irq_disable();
  80         if (!need_resched())
  81                 __asm__(
  82                 "       .set    push                                    \n"
  83                 "       .set    mips3                                   \n"
  84                 "       .set    noat                                    \n"
  85                 "       mfc0    $1, $12                                 \n"
  86                 "       sync                                            \n"
  87                 "       mtc0    $1, $12         # stalls until W stage  \n"
  88                 "       wait                                            \n"
  89                 "       mtc0    $1, $12         # stalls until W stage  \n"
  90                 "       .set    pop                                     \n");
  91         local_irq_enable();
  92 }
  93
  94 /*
  95  * The Au1xxx wait is available only if using 32khz counter or
  96  * external timer source, but specifically not CP0 Counter.
  97  * alchemy/common/time.c may override cpu_wait!
  98  */
  99 static void au1k_wait(void)
 100 {
 101         __asm__("       .set    mips3                   \n"
 102                 "       cache   0x14, 0(%0)             \n"
 103                 "       cache   0x14, 32(%0)            \n"
 104                 "       sync                            \n"
 105                 "       nop                             \n"
 106                 "       wait                            \n"
 107                 "       nop                             \n"
 108                 "       nop                             \n"
 109                 "       nop                             \n"
 110                 "       nop                             \n"
 111                 "       .set    mips0                   \n"
 112                 : : "r" (au1k_wait));
 113 }
 114
 115 static int __initdata nowait;
 116
 117 static int __init wait_disable(char *s)
 118 {
 119         nowait = 1;
 120
 121         return 1;
 122 }
 123
 124 __setup("nowait", wait_disable);
 125
 126 void __init check_wait(void)
 127 {
 128         struct cpuinfo_mips *c = &current_cpu_data;
 129
 130         if (nowait) {
 131                 printk("Wait instruction disabled.\n");
 132                 return;
 133         }
 134
 135         switch (c->cputype) {
 136         case CPU_R3081:
 137         case CPU_R3081E:
 138                 cpu_wait = r3081_wait;
 139                 break;
 140         case CPU_TX3927:
 141                 cpu_wait = r39xx_wait;
 142                 break;
 143         case CPU_R4200:
 144 /*      case CPU_R4300: */
 145         case CPU_R4600:
 146         case CPU_R4640:
 147         case CPU_R4650:
 148         case CPU_R4700:
 149         case CPU_R5000:
 150         case CPU_R5500:
 151         case CPU_NEVADA:
 152         case CPU_4KC:
 153         case CPU_4KEC:
 154         case CPU_4KSC:
 155         case CPU_5KC:
 156         case CPU_25KF:
 157         case CPU_PR4450:
 158         case CPU_BCM3302:
 159         case CPU_CAVIUM_OCTEON:
 160                 cpu_wait = r4k_wait;
 161                 break;
 162
 163         case CPU_RM7000:
 164                 cpu_wait = rm7k_wait_irqoff;
 165                 break;
 166
 167         case CPU_24K:
 168         case CPU_34K:
 169         case CPU_1004K:
 170                 cpu_wait = r4k_wait;
 171                 if (read_c0_config7() & MIPS_CONF7_WII)
 172                         cpu_wait = r4k_wait_irqoff;
 173                 break;
 174
 175         case CPU_74K:
 176                 cpu_wait = r4k_wait;
 177                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 178                         cpu_wait = r4k_wait_irqoff;
 179                 break;
 180
 181         case CPU_TX49XX:
 182                 cpu_wait = r4k_wait_irqoff;
 183                 break;
 184         case CPU_ALCHEMY:
 185                 cpu_wait = au1k_wait;
 186                 break;
 187         case CPU_20KC:
 188                 /*
 189                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 190                  * WAIT on Rev2.0 and Rev3.0 has E16.
 191                  * Rev3.1 WAIT is nop, why bother
 192                  */
 193                 if ((c->processor_id & 0xff) <= 0x64)
 194                         break;
 195
 196                 /*
 197                  * Another rev is incremeting c0_count at a reduced clock
 198                  * rate while in WAIT mode.  So we basically have the choice
 199                  * between using the cp0 timer as clocksource or avoiding
 200                  * the WAIT instruction.  Until more details are known,
 201                  * disable the use of WAIT for 20Kc entirely.
 202                    cpu_wait = r4k_wait;
 203                  */
 204                 break;
 205         case CPU_RM9000:
 206                 if ((c->processor_id & 0x00ff) >= 0x40)
 207                         cpu_wait = r4k_wait;
 208                 break;
 209         default:
 210                 break;
 211         }
 212 }
 213
 214 static inline void check_errata(void)
 215 {
 216         struct cpuinfo_mips *c = &current_cpu_data;
 217
 218         switch (c->cputype) {
 219         case CPU_34K:
 220                 /*
 221                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 222                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 223                  * making use of VPE1 will be responsable for that VPE.
 224                  */
 225                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 226                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 227                 break;
 228         default:
 229                 break;
 230         }
 231 }
 232
 233 void __init check_bugs32(void)
 234 {
 235         check_errata();
 236 }
 237
 238 /*
 239  * Probe whether cpu has config register by trying to play with
 240  * alternate cache bit and see whether it matters.
 241  * It's used by cpu_probe to distinguish between R3000A and R3081.
 242  */
 243 static inline int cpu_has_confreg(void)
 244 {
 245 #ifdef CONFIG_CPU_R3000
 246         extern unsigned long r3k_cache_size(unsigned long);
 247         unsigned long size1, size2;
 248         unsigned long cfg = read_c0_conf();
 249
 250         size1 = r3k_cache_size(ST0_ISC);
 251         write_c0_conf(cfg ^ R30XX_CONF_AC);
 252         size2 = r3k_cache_size(ST0_ISC);
 253         write_c0_conf(cfg);
 254         return size1 != size2;
 255 #else
 256         return 0;
 257 #endif
 258 }
 259
 260 /*
 261  * Get the FPU Implementation/Revision.
 262  */
 263 static inline unsigned long cpu_get_fpu_id(void)
 264 {
 265         unsigned long tmp, fpu_id;
 266
 267         tmp = read_c0_status();
 268         __enable_fpu();
 269         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 270         write_c0_status(tmp);
 271         return fpu_id;
 272 }
 273
 274 /*
 275  * Check the CPU has an FPU the official way.
 276  */
 277 static inline int __cpu_has_fpu(void)
 278 {
 279         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 280 }
 281
 282 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 283                 | MIPS_CPU_COUNTER)
 284
 285 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 286 {
 287         switch (c->processor_id & 0xff00) {
 288         case PRID_IMP_R2000:
 289                 c->cputype = CPU_R2000;
 290                 __cpu_name[cpu] = "R2000";
 291                 c->isa_level = MIPS_CPU_ISA_I;
 292                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 293                              MIPS_CPU_NOFPUEX;
 294                 if (__cpu_has_fpu())
 295                         c->options |= MIPS_CPU_FPU;
 296                 c->tlbsize = 64;
 297                 break;
 298         case PRID_IMP_R3000:
 299                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 300                         if (cpu_has_confreg()) {
 301                                 c->cputype = CPU_R3081E;
 302                                 __cpu_name[cpu] = "R3081";
 303                         } else {
 304                                 c->cputype = CPU_R3000A;
 305                                 __cpu_name[cpu] = "R3000A";
 306                         }
 307                         break;
 308                 } else {
 309                         c->cputype = CPU_R3000;
 310                         __cpu_name[cpu] = "R3000";
 311                 }
 312                 c->isa_level = MIPS_CPU_ISA_I;
 313                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 314                              MIPS_CPU_NOFPUEX;
 315                 if (__cpu_has_fpu())
 316                         c->options |= MIPS_CPU_FPU;
 317                 c->tlbsize = 64;
 318                 break;
 319         case PRID_IMP_R4000:
 320                 if (read_c0_config() & CONF_SC) {
 321                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 322                                 c->cputype = CPU_R4400PC;
 323                                 __cpu_name[cpu] = "R4400PC";
 324                         } else {
 325                                 c->cputype = CPU_R4000PC;
 326                                 __cpu_name[cpu] = "R4000PC";
 327                         }
 328                 } else {
 329                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 330                                 c->cputype = CPU_R4400SC;
 331                                 __cpu_name[cpu] = "R4400SC";
 332                         } else {
 333                                 c->cputype = CPU_R4000SC;
 334                                 __cpu_name[cpu] = "R4000SC";
 335                         }
 336                 }
 337
 338                 c->isa_level = MIPS_CPU_ISA_III;
 339                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 340                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 341                              MIPS_CPU_LLSC;
 342                 c->tlbsize = 48;
 343                 break;
 344         case PRID_IMP_VR41XX:
 345                 switch (c->processor_id & 0xf0) {
 346                 case PRID_REV_VR4111:
 347                         c->cputype = CPU_VR4111;
 348                         __cpu_name[cpu] = "NEC VR4111";
 349                         break;
 350                 case PRID_REV_VR4121:
 351                         c->cputype = CPU_VR4121;
 352                         __cpu_name[cpu] = "NEC VR4121";
 353                         break;
 354                 case PRID_REV_VR4122:
 355                         if ((c->processor_id & 0xf) < 0x3) {
 356                                 c->cputype = CPU_VR4122;
 357                                 __cpu_name[cpu] = "NEC VR4122";
 358                         } else {
 359                                 c->cputype = CPU_VR4181A;
 360                                 __cpu_name[cpu] = "NEC VR4181A";
 361                         }
 362                         break;
 363                 case PRID_REV_VR4130:
 364                         if ((c->processor_id & 0xf) < 0x4) {
 365                                 c->cputype = CPU_VR4131;
 366                                 __cpu_name[cpu] = "NEC VR4131";
 367                         } else {
 368                                 c->cputype = CPU_VR4133;
 369                                 __cpu_name[cpu] = "NEC VR4133";
 370                         }
 371                         break;
 372                 default:
 373                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 374                         c->cputype = CPU_VR41XX;
 375                         __cpu_name[cpu] = "NEC Vr41xx";
 376                         break;
 377                 }
 378                 c->isa_level = MIPS_CPU_ISA_III;
 379                 c->options = R4K_OPTS;
 380                 c->tlbsize = 32;
 381                 break;
 382         case PRID_IMP_R4300:
 383                 c->cputype = CPU_R4300;
 384                 __cpu_name[cpu] = "R4300";
 385                 c->isa_level = MIPS_CPU_ISA_III;
 386                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 387                              MIPS_CPU_LLSC;
 388                 c->tlbsize = 32;
 389                 break;
 390         case PRID_IMP_R4600:
 391                 c->cputype = CPU_R4600;
 392                 __cpu_name[cpu] = "R4600";
 393                 c->isa_level = MIPS_CPU_ISA_III;
 394                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 395                              MIPS_CPU_LLSC;
 396                 c->tlbsize = 48;
 397                 break;
 398         #if 0
 399         case PRID_IMP_R4650:
 400                 /*
 401                  * This processor doesn't have an MMU, so it's not
 402                  * "real easy" to run Linux on it. It is left purely
 403                  * for documentation.  Commented out because it shares
 404                  * it's c0_prid id number with the TX3900.
 405                  */
 406                 c->cputype = CPU_R4650;
 407                 __cpu_name[cpu] = "R4650";
 408                 c->isa_level = MIPS_CPU_ISA_III;
 409                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 410                 c->tlbsize = 48;
 411                 break;
 412         #endif
 413         case PRID_IMP_TX39:
 414                 c->isa_level = MIPS_CPU_ISA_I;
 415                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 416
 417                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 418                         c->cputype = CPU_TX3927;
 419                         __cpu_name[cpu] = "TX3927";
 420                         c->tlbsize = 64;
 421                 } else {
 422                         switch (c->processor_id & 0xff) {
 423                         case PRID_REV_TX3912:
 424                                 c->cputype = CPU_TX3912;
 425                                 __cpu_name[cpu] = "TX3912";
 426                                 c->tlbsize = 32;
 427                                 break;
 428                         case PRID_REV_TX3922:
 429                                 c->cputype = CPU_TX3922;
 430                                 __cpu_name[cpu] = "TX3922";
 431                                 c->tlbsize = 64;
 432                                 break;
 433                         }
 434                 }
 435                 break;
 436         case PRID_IMP_R4700:
 437                 c->cputype = CPU_R4700;
 438                 __cpu_name[cpu] = "R4700";
 439                 c->isa_level = MIPS_CPU_ISA_III;
 440                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 441                              MIPS_CPU_LLSC;
 442                 c->tlbsize = 48;
 443                 break;
 444         case PRID_IMP_TX49:
 445                 c->cputype = CPU_TX49XX;
 446                 __cpu_name[cpu] = "R49XX";
 447                 c->isa_level = MIPS_CPU_ISA_III;
 448                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 449                 if (!(c->processor_id & 0x08))
 450                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 451                 c->tlbsize = 48;
 452                 break;
 453         case PRID_IMP_R5000:
 454                 c->cputype = CPU_R5000;
 455                 __cpu_name[cpu] = "R5000";
 456                 c->isa_level = MIPS_CPU_ISA_IV;
 457                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 458                              MIPS_CPU_LLSC;
 459                 c->tlbsize = 48;
 460                 break;
 461         case PRID_IMP_R5432:
 462                 c->cputype = CPU_R5432;
 463                 __cpu_name[cpu] = "R5432";
 464                 c->isa_level = MIPS_CPU_ISA_IV;
 465                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 466                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 467                 c->tlbsize = 48;
 468                 break;
 469         case PRID_IMP_R5500:
 470                 c->cputype = CPU_R5500;
 471                 __cpu_name[cpu] = "R5500";
 472                 c->isa_level = MIPS_CPU_ISA_IV;
 473                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 474                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 475                 c->tlbsize = 48;
 476                 break;
 477         case PRID_IMP_NEVADA:
 478                 c->cputype = CPU_NEVADA;
 479                 __cpu_name[cpu] = "Nevada";
 480                 c->isa_level = MIPS_CPU_ISA_IV;
 481                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 482                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 483                 c->tlbsize = 48;
 484                 break;
 485         case PRID_IMP_R6000:
 486                 c->cputype = CPU_R6000;
 487                 __cpu_name[cpu] = "R6000";
 488                 c->isa_level = MIPS_CPU_ISA_II;
 489                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 490                              MIPS_CPU_LLSC;
 491                 c->tlbsize = 32;
 492                 break;
 493         case PRID_IMP_R6000A:
 494                 c->cputype = CPU_R6000A;
 495                 __cpu_name[cpu] = "R6000A";
 496                 c->isa_level = MIPS_CPU_ISA_II;
 497                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 498                              MIPS_CPU_LLSC;
 499                 c->tlbsize = 32;
 500                 break;
 501         case PRID_IMP_RM7000:
 502                 c->cputype = CPU_RM7000;
 503                 __cpu_name[cpu] = "RM7000";
 504                 c->isa_level = MIPS_CPU_ISA_IV;
 505                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 506                              MIPS_CPU_LLSC;
 507                 /*
 508                  * Undocumented RM7000:  Bit 29 in the info register of
 509                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 510                  * entries.
 511                  *
 512                  * 29      1 =>    64 entry JTLB
 513                  *         0 =>    48 entry JTLB
 514                  */
 515                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 516                 break;
 517         case PRID_IMP_RM9000:
 518                 c->cputype = CPU_RM9000;
 519                 __cpu_name[cpu] = "RM9000";
 520                 c->isa_level = MIPS_CPU_ISA_IV;
 521                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 522                              MIPS_CPU_LLSC;
 523                 /*
 524                  * Bit 29 in the info register of the RM9000
 525                  * indicates if the TLB has 48 or 64 entries.
 526                  *
 527                  * 29      1 =>    64 entry JTLB
 528                  *         0 =>    48 entry JTLB
 529                  */
 530                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 531                 break;
 532         case PRID_IMP_R8000:
 533                 c->cputype = CPU_R8000;
 534                 __cpu_name[cpu] = "RM8000";
 535                 c->isa_level = MIPS_CPU_ISA_IV;
 536                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 537                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 538                              MIPS_CPU_LLSC;
 539                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 540                 break;
 541         case PRID_IMP_R10000:
 542                 c->cputype = CPU_R10000;
 543                 __cpu_name[cpu] = "R10000";
 544                 c->isa_level = MIPS_CPU_ISA_IV;
 545                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 546                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 547                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 548                              MIPS_CPU_LLSC;
 549                 c->tlbsize = 64;
 550                 break;
 551         case PRID_IMP_R12000:
 552                 c->cputype = CPU_R12000;
 553                 __cpu_name[cpu] = "R12000";
 554                 c->isa_level = MIPS_CPU_ISA_IV;
 555                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 556                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 557                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 558                              MIPS_CPU_LLSC;
 559                 c->tlbsize = 64;
 560                 break;
 561         case PRID_IMP_R14000:
 562                 c->cputype = CPU_R14000;
 563                 __cpu_name[cpu] = "R14000";
 564                 c->isa_level = MIPS_CPU_ISA_IV;
 565                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 566                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 567                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 568                              MIPS_CPU_LLSC;
 569                 c->tlbsize = 64;
 570                 break;
 571         case PRID_IMP_LOONGSON2:
 572                 c->cputype = CPU_LOONGSON2;
 573                 __cpu_name[cpu] = "ICT Loongson-2";
 574                 c->isa_level = MIPS_CPU_ISA_III;
 575                 c->options = R4K_OPTS |
 576                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 577                              MIPS_CPU_32FPR;
 578                 c->tlbsize = 64;
 579                 break;
 580         }
 581 }
 582
 583 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 584         "Unsupported ISA type, c0.config0: %d.";
 585
 586 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 587 {
 588         unsigned int config0;
 589         int isa;
 590
 591         config0 = read_c0_config();
 592
 593         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 594                 c->options |= MIPS_CPU_TLB;
 595         isa = (config0 & MIPS_CONF_AT) >> 13;
 596         switch (isa) {
 597         case 0:
 598                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 599                 case 0:
 600                         c->isa_level = MIPS_CPU_ISA_M32R1;
 601                         break;
 602                 case 1:
 603                         c->isa_level = MIPS_CPU_ISA_M32R2;
 604                         break;
 605                 default:
 606                         goto unknown;
 607                 }
 608                 break;
 609         case 2:
 610                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 611                 case 0:
 612                         c->isa_level = MIPS_CPU_ISA_M64R1;
 613                         break;
 614                 case 1:
 615                         c->isa_level = MIPS_CPU_ISA_M64R2;
 616                         break;
 617                 default:
 618                         goto unknown;
 619                 }
 620                 break;
 621         default:
 622                 goto unknown;
 623         }
 624
 625         return config0 & MIPS_CONF_M;
 626
 627 unknown:
 628         panic(unknown_isa, config0);
 629 }
 630
 631 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 632 {
 633         unsigned int config1;
 634
 635         config1 = read_c0_config1();
 636
 637         if (config1 & MIPS_CONF1_MD)
 638                 c->ases |= MIPS_ASE_MDMX;
 639         if (config1 & MIPS_CONF1_WR)
 640                 c->options |= MIPS_CPU_WATCH;
 641         if (config1 & MIPS_CONF1_CA)
 642                 c->ases |= MIPS_ASE_MIPS16;
 643         if (config1 & MIPS_CONF1_EP)
 644                 c->options |= MIPS_CPU_EJTAG;
 645         if (config1 & MIPS_CONF1_FP) {
 646                 c->options |= MIPS_CPU_FPU;
 647                 c->options |= MIPS_CPU_32FPR;
 648         }
 649         if (cpu_has_tlb)
 650                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 651
 652         return config1 & MIPS_CONF_M;
 653 }
 654
 655 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 656 {
 657         unsigned int config2;
 658
 659         config2 = read_c0_config2();
 660
 661         if (config2 & MIPS_CONF2_SL)
 662                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 663
 664         return config2 & MIPS_CONF_M;
 665 }
 666
 667 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 668 {
 669         unsigned int config3;
 670
 671         config3 = read_c0_config3();
 672
 673         if (config3 & MIPS_CONF3_SM)
 674                 c->ases |= MIPS_ASE_SMARTMIPS;
 675         if (config3 & MIPS_CONF3_DSP)
 676                 c->ases |= MIPS_ASE_DSP;
 677         if (config3 & MIPS_CONF3_VINT)
 678                 c->options |= MIPS_CPU_VINT;
 679         if (config3 & MIPS_CONF3_VEIC)
 680                 c->options |= MIPS_CPU_VEIC;
 681         if (config3 & MIPS_CONF3_MT)
 682                 c->ases |= MIPS_ASE_MIPSMT;
 683         if (config3 & MIPS_CONF3_ULRI)
 684                 c->options |= MIPS_CPU_ULRI;
 685
 686         return config3 & MIPS_CONF_M;
 687 }
 688
 689 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 690 {
 691         int ok;
 692
 693         /* MIPS32 or MIPS64 compliant CPU.  */
 694         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 695                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 696
 697         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 698
 699         ok = decode_config0(c);                 /* Read Config registers.  */
 700         BUG_ON(!ok);                            /* Arch spec violation!  */
 701         if (ok)
 702                 ok = decode_config1(c);
 703         if (ok)
 704                 ok = decode_config2(c);
 705         if (ok)
 706                 ok = decode_config3(c);
 707
 708         mips_probe_watch_registers(c);
 709 }
 710
 711 #ifdef CONFIG_CPU_MIPSR2
 712 extern void spram_config(void);
 713 #else
 714 static inline void spram_config(void) {}
 715 #endif
 716
 717 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 718 {
 719         decode_configs(c);
 720         switch (c->processor_id & 0xff00) {
 721         case PRID_IMP_4KC:
 722                 c->cputype = CPU_4KC;
 723                 __cpu_name[cpu] = "MIPS 4Kc";
 724                 break;
 725         case PRID_IMP_4KEC:
 726                 c->cputype = CPU_4KEC;
 727                 __cpu_name[cpu] = "MIPS 4KEc";
 728                 break;
 729         case PRID_IMP_4KECR2:
 730                 c->cputype = CPU_4KEC;
 731                 __cpu_name[cpu] = "MIPS 4KEc";
 732                 break;
 733         case PRID_IMP_4KSC:
 734         case PRID_IMP_4KSD:
 735                 c->cputype = CPU_4KSC;
 736                 __cpu_name[cpu] = "MIPS 4KSc";
 737                 break;
 738         case PRID_IMP_5KC:
 739                 c->cputype = CPU_5KC;
 740                 __cpu_name[cpu] = "MIPS 5Kc";
 741                 break;
 742         case PRID_IMP_20KC:
 743                 c->cputype = CPU_20KC;
 744                 __cpu_name[cpu] = "MIPS 20Kc";
 745                 break;
 746         case PRID_IMP_24K:
 747         case PRID_IMP_24KE:
 748                 c->cputype = CPU_24K;
 749                 __cpu_name[cpu] = "MIPS 24Kc";
 750                 break;
 751         case PRID_IMP_25KF:
 752                 c->cputype = CPU_25KF;
 753                 __cpu_name[cpu] = "MIPS 25Kc";
 754                 break;
 755         case PRID_IMP_34K:
 756                 c->cputype = CPU_34K;
 757                 __cpu_name[cpu] = "MIPS 34Kc";
 758                 break;
 759         case PRID_IMP_74K:
 760                 c->cputype = CPU_74K;
 761                 __cpu_name[cpu] = "MIPS 74Kc";
 762                 break;
 763         case PRID_IMP_1004K:
 764                 c->cputype = CPU_1004K;
 765                 __cpu_name[cpu] = "MIPS 1004Kc";
 766                 break;
 767         }
 768
 769         spram_config();
 770 }
 771
 772 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 773 {
 774         decode_configs(c);
 775         switch (c->processor_id & 0xff00) {
 776         case PRID_IMP_AU1_REV1:
 777         case PRID_IMP_AU1_REV2:
 778                 c->cputype = CPU_ALCHEMY;
 779                 switch ((c->processor_id >> 24) & 0xff) {
 780                 case 0:
 781                         __cpu_name[cpu] = "Au1000";
 782                         break;
 783                 case 1:
 784                         __cpu_name[cpu] = "Au1500";
 785                         break;
 786                 case 2:
 787                         __cpu_name[cpu] = "Au1100";
 788                         break;
 789                 case 3:
 790                         __cpu_name[cpu] = "Au1550";
 791                         break;
 792                 case 4:
 793                         __cpu_name[cpu] = "Au1200";
 794                         if ((c->processor_id & 0xff) == 2)
 795                                 __cpu_name[cpu] = "Au1250";
 796                         break;
 797                 case 5:
 798                         __cpu_name[cpu] = "Au1210";
 799                         break;
 800                 default:
 801                         __cpu_name[cpu] = "Au1xxx";
 802                         break;
 803                 }
 804                 break;
 805         }
 806 }
 807
 808 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 809 {
 810         decode_configs(c);
 811
 812         switch (c->processor_id & 0xff00) {
 813         case PRID_IMP_SB1:
 814                 c->cputype = CPU_SB1;
 815                 __cpu_name[cpu] = "SiByte SB1";
 816                 /* FPU in pass1 is known to have issues. */
 817                 if ((c->processor_id & 0xff) < 0x02)
 818                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 819                 break;
 820         case PRID_IMP_SB1A:
 821                 c->cputype = CPU_SB1A;
 822                 __cpu_name[cpu] = "SiByte SB1A";
 823                 break;
 824         }
 825 }
 826
 827 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 828 {
 829         decode_configs(c);
 830         switch (c->processor_id & 0xff00) {
 831         case PRID_IMP_SR71000:
 832                 c->cputype = CPU_SR71000;
 833                 __cpu_name[cpu] = "Sandcraft SR71000";
 834                 c->scache.ways = 8;
 835                 c->tlbsize = 64;
 836                 break;
 837         }
 838 }
 839
 840 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 841 {
 842         decode_configs(c);
 843         switch (c->processor_id & 0xff00) {
 844         case PRID_IMP_PR4450:
 845                 c->cputype = CPU_PR4450;
 846                 __cpu_name[cpu] = "Philips PR4450";
 847                 c->isa_level = MIPS_CPU_ISA_M32R1;
 848                 break;
 849         }
 850 }
 851
 852 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 853 {
 854         decode_configs(c);
 855         switch (c->processor_id & 0xff00) {
 856         case PRID_IMP_BCM3302:
 857                 c->cputype = CPU_BCM3302;
 858                 __cpu_name[cpu] = "Broadcom BCM3302";
 859                 break;
 860         case PRID_IMP_BCM4710:
 861                 c->cputype = CPU_BCM4710;
 862                 __cpu_name[cpu] = "Broadcom BCM4710";
 863                 break;
 864         }
 865 }
 866
 867 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 868 {
 869         decode_configs(c);
 870         switch (c->processor_id & 0xff00) {
 871         case PRID_IMP_CAVIUM_CN38XX:
 872         case PRID_IMP_CAVIUM_CN31XX:
 873         case PRID_IMP_CAVIUM_CN30XX:
 874         case PRID_IMP_CAVIUM_CN58XX:
 875         case PRID_IMP_CAVIUM_CN56XX:
 876         case PRID_IMP_CAVIUM_CN50XX:
 877         case PRID_IMP_CAVIUM_CN52XX:
 878                 c->cputype = CPU_CAVIUM_OCTEON;
 879                 __cpu_name[cpu] = "Cavium Octeon";
 880                 break;
 881         default:
 882                 printk(KERN_INFO "Unknown Octeon chip!\n");
 883                 c->cputype = CPU_UNKNOWN;
 884                 break;
 885         }
 886 }
 887
 888 const char *__cpu_name[NR_CPUS];
 889
 890 __cpuinit void cpu_probe(void)
 891 {
 892         struct cpuinfo_mips *c = &current_cpu_data;
 893         unsigned int cpu = smp_processor_id();
 894
 895         c->processor_id = PRID_IMP_UNKNOWN;
 896         c->fpu_id       = FPIR_IMP_NONE;
 897         c->cputype      = CPU_UNKNOWN;
 898
 899         c->processor_id = read_c0_prid();
 900         switch (c->processor_id & 0xff0000) {
 901         case PRID_COMP_LEGACY:
 902                 cpu_probe_legacy(c, cpu);
 903                 break;
 904         case PRID_COMP_MIPS:
 905                 cpu_probe_mips(c, cpu);
 906                 break;
 907         case PRID_COMP_ALCHEMY:
 908                 cpu_probe_alchemy(c, cpu);
 909                 break;
 910         case PRID_COMP_SIBYTE:
 911                 cpu_probe_sibyte(c, cpu);
 912                 break;
 913         case PRID_COMP_BROADCOM:
 914                 cpu_probe_broadcom(c, cpu);
 915                 break;
 916         case PRID_COMP_SANDCRAFT:
 917                 cpu_probe_sandcraft(c, cpu);
 918                 break;
 919         case PRID_COMP_NXP:
 920                 cpu_probe_nxp(c, cpu);
 921                 break;
 922         case PRID_COMP_CAVIUM:
 923                 cpu_probe_cavium(c, cpu);
 924                 break;
 925         }
 926
 927         BUG_ON(!__cpu_name[cpu]);
 928         BUG_ON(c->cputype == CPU_UNKNOWN);
 929
 930         /*
 931          * Platform code can force the cpu type to optimize code
 932          * generation. In that case be sure the cpu type is correctly
 933          * manually setup otherwise it could trigger some nasty bugs.
 934          */
 935         BUG_ON(current_cpu_type() != c->cputype);
 936
 937         if (c->options & MIPS_CPU_FPU) {
 938                 c->fpu_id = cpu_get_fpu_id();
 939
 940                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
 941                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
 942                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
 943                     c->isa_level == MIPS_CPU_ISA_M64R2) {
 944                         if (c->fpu_id & MIPS_FPIR_3D)
 945                                 c->ases |= MIPS_ASE_MIPS3D;
 946                 }
 947         }
 948
 949         if (cpu_has_mips_r2)
 950                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
 951         else
 952                 c->srsets = 1;
 953 }
 954
 955 __cpuinit void cpu_report(void)
 956 {
 957         struct cpuinfo_mips *c = &current_cpu_data;
 958
 959         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
 960                c->processor_id, cpu_name_string());
 961         if (c->options & MIPS_CPU_FPU)
 962                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
 963 }