2 * AMD Alchemy DBAu1200 Reference Board
3 * Board register defines.
5 * ########################################################################
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 * ########################################################################
24 #ifndef __ASM_DB1200_H
25 #define __ASM_DB1200_H
27 #include <linux/types.h>
28 #include <asm/mach-au1x00/au1000.h>
29 #include <asm/mach-au1x00/au1xxx_psc.h>
31 #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
32 #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
33 #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
34 #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
37 * SPI and SMB are muxed on the DBAu1200 board.
38 * Refer to board documentation.
40 #define SPI_PSC_BASE PSC0_BASE_ADDR
41 #define SMBUS_PSC_BASE PSC0_BASE_ADDR
43 * AC'97 and I2S are muxed on the DBAu1200 board.
44 * Refer to board documentation.
46 #define AC97_PSC_BASE PSC1_BASE_ADDR
47 #define I2S_PSC_BASE PSC1_BASE_ADDR
49 /* Bit positions for the different interrupt sources */
50 #define BCSR_INT_IDE 0x0001
51 #define BCSR_INT_ETH 0x0002
52 #define BCSR_INT_PC0 0x0004
53 #define BCSR_INT_PC0STSCHG 0x0008
54 #define BCSR_INT_PC1 0x0010
55 #define BCSR_INT_PC1STSCHG 0x0020
56 #define BCSR_INT_DC 0x0040
57 #define BCSR_INT_FLASHBUSY 0x0080
58 #define BCSR_INT_PC0INSERT 0x0100
59 #define BCSR_INT_PC0EJECT 0x0200
60 #define BCSR_INT_PC1INSERT 0x0400
61 #define BCSR_INT_PC1EJECT 0x0800
62 #define BCSR_INT_SD0INSERT 0x1000
63 #define BCSR_INT_SD0EJECT 0x2000
65 #define SMC91C111_PHYS_ADDR 0x19000300
66 #define SMC91C111_INT DB1200_ETH_INT
68 #define IDE_PHYS_ADDR 0x18800000
69 #define IDE_REG_SHIFT 5
70 #define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
71 #define IDE_INT DB1200_IDE_INT
72 #define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
73 #define IDE_RQSIZE 128
75 #define NAND_PHYS_ADDR 0x20000000
78 * External Interrupts for DBAu1200 as of 8/6/2004.
79 * Bit positions in the CPLD registers can be calculated by taking
80 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
82 * Example: IDE bis pos is = 64 - 64
83 * ETH bit pos is = 65 - 64
85 enum external_pb1200_ints {
86 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
88 DB1200_IDE_INT = DB1200_INT_BEGIN,
91 DB1200_PC0_STSCHG_INT,
93 DB1200_PC1_STSCHG_INT,
96 DB1200_PC0_INSERT_INT,
98 DB1200_PC1_INSERT_INT,
100 DB1200_SD0_INSERT_INT,
101 DB1200_SD0_EJECT_INT,
103 DB1200_INT_END = DB1200_INT_BEGIN + 15,
108 * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
110 #define PCMCIA_MAX_SOCK 1
111 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
114 #define SET_VCC_VPP(VCC, VPP, SLOT) \
115 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
117 #define BOARD_PC0_INT DB1200_PC0_INT
118 #define BOARD_PC1_INT DB1200_PC1_INT
119 #define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT) & (1 << (8 + (2 * SOCKET))))
121 /* NAND chip select */
124 #endif /* __ASM_DB1200_H */