2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/delay.h>
27 #include <linux/gpio.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <asm/mach-au1x00/au1000.h>
32 #include <asm/mach-pb1x00/pb1500.h>
33 #include <asm/mach-db1x00/bcsr.h>
38 char irq_tab_alchemy[][5] __initdata = {
39 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */
40 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
43 struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
44 { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
45 { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
46 { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
47 { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
48 { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
52 const char *get_system_type(void)
54 return "Alchemy Pb1500";
57 void board_reset(void)
59 bcsr_write(BCSR_SYSTEM, 0);
62 void __init board_init_irq(void)
64 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
67 void __init board_setup(void)
70 u32 sys_freqctrl, sys_clksrc;
73 bcsr_init(DB1000_BCSR_PHYS_ADDR,
74 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
76 argptr = prom_getcmdline();
77 #ifdef CONFIG_SERIAL_8250_CONSOLE
78 argptr = strstr(argptr, "console=");
80 argptr = prom_getcmdline();
81 strcat(argptr, " console=ttyS0,115200");
85 #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
86 /* au1000 does not support vra, au1500 and au1100 do */
87 strcat(argptr, " au1000_audio=vra");
88 argptr = prom_getcmdline();
91 sys_clksrc = sys_freqctrl = pin_func = 0;
92 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
93 au_writel(8, SYS_AUXPLL);
94 au_writel(0, SYS_PINSTATERD);
97 /* GPIO201 is input for PCMCIA card detect */
98 /* GPIO203 is input for PCMCIA interrupt request */
99 alchemy_gpio_direction_input(201);
100 alchemy_gpio_direction_input(203);
102 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
104 /* Zero and disable FREQ2 */
105 sys_freqctrl = au_readl(SYS_FREQCTRL0);
106 sys_freqctrl &= ~0xFFF00000;
107 au_writel(sys_freqctrl, SYS_FREQCTRL0);
109 /* zero and disable USBH/USBD clocks */
110 sys_clksrc = au_readl(SYS_CLKSRC);
111 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
112 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
113 au_writel(sys_clksrc, SYS_CLKSRC);
115 sys_freqctrl = au_readl(SYS_FREQCTRL0);
116 sys_freqctrl &= ~0xFFF00000;
118 sys_clksrc = au_readl(SYS_CLKSRC);
119 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
120 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
122 /* FREQ2 = aux/2 = 48 MHz */
123 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
124 au_writel(sys_freqctrl, SYS_FREQCTRL0);
127 * Route 48MHz FREQ2 into USB Host and/or Device
129 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
130 au_writel(sys_clksrc, SYS_CLKSRC);
132 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
133 /* 2nd USB port is USB host */
134 pin_func |= SYS_PF_USB;
135 au_writel(pin_func, SYS_PINFUNC);
136 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
139 /* Setup PCI bus controller */
140 au_writel(0, Au1500_PCI_CMEM);
141 au_writel(0x00003fff, Au1500_CFG_BASE);
142 #if defined(__MIPSEB__)
143 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
145 au_writel(0xf, Au1500_PCI_CFG);
147 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
148 au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
149 au_writel(0x02a00356, Au1500_PCI_STATCMD);
150 au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
151 au_writel(0x00000008, Au1500_PCI_MBAR);
155 /* Enable sys bus clock divider when IDLE state or no bus activity. */
156 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
158 /* Enable the RTC if not already enabled */
159 if (!(au_readl(0xac000028) & 0x20)) {
160 printk(KERN_INFO "enabling clock ...\n");
161 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
163 /* Put the clock in BCD mode */
164 if (au_readl(0xac00002c) & 0x4) { /* reg B */
165 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);