2 * Exception handling for Microblaze
4 * Rewriten interrupt handling
6 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
7 * Copyright (C) 2008-2009 PetaLogix
9 * uClinux customisation (C) 2005 John Williams
11 * MMU code derived from arch/ppc/kernel/head_4xx.S:
12 * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
13 * Initial PowerPC version.
14 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
16 * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
17 * Low-level exception handers, MMU support, and rewrite.
18 * Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
19 * PowerPC 8xx modifications.
20 * Copyright (C) 1998-1999 TiVo, Inc.
21 * PowerPC 403GCX modifications.
22 * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
23 * PowerPC 403GCX/405GP modifications.
24 * Copyright 2000 MontaVista Software Inc.
25 * PPC405 modifications
26 * PowerPC 403GCX/405GP modifications.
27 * Author: MontaVista Software, Inc.
28 * frank_rowand@mvista.com or source@mvista.com
29 * debbie_chu@mvista.com
32 * Copyright (C) 2004 Xilinx, Inc.
34 * This program is free software; you can redistribute it and/or modify it
35 * under the terms of the GNU General Public License version 2 as published
36 * by the Free Software Foundation.
40 * Here are the handlers which don't require enabling translation
41 * and calling other kernel code thus we can keep their design very simple
42 * and do all processing in real mode. All what they need is a valid current
43 * (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
44 * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
45 * these registers are saved/restored
46 * The handlers which require translation are in entry.S --KAA
48 * Microblaze HW Exception Handler
49 * - Non self-modifying exception handler for the following exception conditions
51 * - Instruction bus error
53 * - Illegal instruction opcode
56 * - Privileged instruction exception (MMU)
57 * - Data storage exception (MMU)
58 * - Instruction storage exception (MMU)
59 * - Data TLB miss exception (MMU)
60 * - Instruction TLB miss exception (MMU)
62 * Note we disable interrupts during exception handling, otherwise we will
63 * possibly get multiple re-entrancy if interrupt handles themselves cause
67 #include <asm/exceptions.h>
68 #include <asm/unistd.h>
71 #include <asm/entry.h>
72 #include <asm/current.h>
73 #include <linux/linkage.h>
76 #include <asm/pgtable.h>
77 #include <asm/signal.h>
78 #include <asm/asm-offsets.h>
82 #define EX_HANDLER_STACK_SIZ (4*19)
84 #define NUM_TO_REG(num) r ## num
87 #define RESTORE_STATE \
95 lwi r11, r1, PT_R11; \
96 lwi r31, r1, PT_R31; \
97 lwi r1, r0, TOPHYS(r0_ram + 0);
98 #endif /* CONFIG_MMU */
101 bri ex_handler_unhandled; \
105 bri ex_handler_unhandled; \
108 /* FIXME this is weird - for noMMU kernel is not possible to use brid
109 * instruction which can shorten executed time
112 /* r3 is the source */
113 #define R3_TO_LWREG_V(regnum) \
114 swi r3, r1, 4 * regnum; \
117 /* r3 is the source */
118 #define R3_TO_LWREG(regnum) \
119 or NUM_TO_REG (regnum), r0, r3; \
122 /* r3 is the target */
123 #define SWREG_TO_R3_V(regnum) \
124 lwi r3, r1, 4 * regnum; \
127 /* r3 is the target */
128 #define SWREG_TO_R3(regnum) \
129 or r3, r0, NUM_TO_REG (regnum); \
133 #define R3_TO_LWREG_VM_V(regnum) \
135 swi r3, r7, 4 * regnum;
137 #define R3_TO_LWREG_VM(regnum) \
139 or NUM_TO_REG (regnum), r0, r3;
141 #define SWREG_TO_R3_VM_V(regnum) \
142 brid ex_sw_tail_vm; \
143 lwi r3, r7, 4 * regnum;
145 #define SWREG_TO_R3_VM(regnum) \
146 brid ex_sw_tail_vm; \
147 or r3, r0, NUM_TO_REG (regnum);
149 /* Shift right instruction depending on available configuration */
150 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
151 #define BSRLI(rD, rA, imm) \
153 #elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0
154 #define BSRLI(rD, rA, imm) \
155 ori rD, r0, (1 << imm); \
158 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
159 /* Only the used shift constants defined here - add more if needed */
160 #define BSRLI2(rD, rA) \
161 srl rD, rA; /* << 1 */ \
162 srl rD, rD; /* << 2 */
163 #define BSRLI10(rD, rA) \
164 srl rD, rA; /* << 1 */ \
165 srl rD, rD; /* << 2 */ \
166 srl rD, rD; /* << 3 */ \
167 srl rD, rD; /* << 4 */ \
168 srl rD, rD; /* << 5 */ \
169 srl rD, rD; /* << 6 */ \
170 srl rD, rD; /* << 7 */ \
171 srl rD, rD; /* << 8 */ \
172 srl rD, rD; /* << 9 */ \
173 srl rD, rD /* << 10 */
174 #define BSRLI20(rD, rA) \
178 #endif /* CONFIG_MMU */
180 .extern other_exception_handler /* Defined in exception.c */
183 * hw_exception_handler - Handler for exceptions
185 * Exception handler notes:
186 * - Handles all exceptions
187 * - Does not handle unaligned exceptions during load into r17, r1, r0.
188 * - Does not handle unaligned exceptions during store from r17 (cannot be
189 * done) and r1 (slows down common case)
191 * Relevant register structures
193 * EAR - |----|----|----|----|----|----|----|----|
194 * - < ## 32 bit faulting address ## >
196 * ESR - |----|----|----|----|----| - | - |-----|-----|
200 * STACK FRAME STRUCTURE (for NO_MMU)
201 * ---------------------------------
203 * +-------------+ + 0
205 * +-------------+ + 4
212 * +-------------+ + 76
216 * NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S
217 * which is used for storing register values - old style was, that value were
218 * stored in stack but in case of failure you lost information about register.
219 * Currently you can see register value in memory in specific place.
220 * In compare to with previous solution the speed should be the same.
222 * MMU exception handler has different handling compare to no MMU kernel.
223 * Exception handler use jump table for directing of what happen. For MMU kernel
224 * is this approach better because MMU relate exception are handled by asm code
225 * in this file. In compare to with MMU expect of unaligned exception
226 * is everything handled by C code.
230 * every of these handlers is entered having R3/4/5/6/11/current saved on stack
231 * and clobbered so care should be taken to restore them if someone is going to
232 * return from exception
235 /* wrappers to restore state before coming to entry.S */
240 _MB_HW_ExceptionVectorTable:
242 .long TOPHYS(ex_handler_unhandled)
243 /* 1 - Unaligned data access exception */
244 .long TOPHYS(handle_unaligned_ex)
245 /* 2 - Illegal op-code exception */
246 .long TOPHYS(full_exception_trapw)
247 /* 3 - Instruction bus error exception */
248 .long TOPHYS(full_exception_trapw)
249 /* 4 - Data bus error exception */
250 .long TOPHYS(full_exception_trapw)
251 /* 5 - Divide by zero exception */
252 .long TOPHYS(full_exception_trapw)
253 /* 6 - Floating point unit exception */
254 .long TOPHYS(full_exception_trapw)
255 /* 7 - Privileged instruction exception */
256 .long TOPHYS(full_exception_trapw)
257 /* 8 - 15 - Undefined */
258 .long TOPHYS(ex_handler_unhandled)
259 .long TOPHYS(ex_handler_unhandled)
260 .long TOPHYS(ex_handler_unhandled)
261 .long TOPHYS(ex_handler_unhandled)
262 .long TOPHYS(ex_handler_unhandled)
263 .long TOPHYS(ex_handler_unhandled)
264 .long TOPHYS(ex_handler_unhandled)
265 .long TOPHYS(ex_handler_unhandled)
266 /* 16 - Data storage exception */
267 .long TOPHYS(handle_data_storage_exception)
268 /* 17 - Instruction storage exception */
269 .long TOPHYS(handle_instruction_storage_exception)
270 /* 18 - Data TLB miss exception */
271 .long TOPHYS(handle_data_tlb_miss_exception)
272 /* 19 - Instruction TLB miss exception */
273 .long TOPHYS(handle_instruction_tlb_miss_exception)
274 /* 20 - 31 - Undefined */
275 .long TOPHYS(ex_handler_unhandled)
276 .long TOPHYS(ex_handler_unhandled)
277 .long TOPHYS(ex_handler_unhandled)
278 .long TOPHYS(ex_handler_unhandled)
279 .long TOPHYS(ex_handler_unhandled)
280 .long TOPHYS(ex_handler_unhandled)
281 .long TOPHYS(ex_handler_unhandled)
282 .long TOPHYS(ex_handler_unhandled)
283 .long TOPHYS(ex_handler_unhandled)
284 .long TOPHYS(ex_handler_unhandled)
285 .long TOPHYS(ex_handler_unhandled)
286 .long TOPHYS(ex_handler_unhandled)
289 .global _hw_exception_handler
292 .ent _hw_exception_handler
293 _hw_exception_handler:
295 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
297 swi r1, r0, TOPHYS(r0_ram + 0); /* GET_SP */
298 /* Save date to kernel memory. Here is the problem
299 * when you came from user space */
300 ori r1, r0, TOPHYS(r0_ram + 28);
310 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
322 andi r5, r3, 0x1000; /* Check ESR[DS] */
323 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
324 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
330 andi r5, r3, 0x1F; /* Extract ESR[EXC] */
333 /* Calculate exception vector offset = r5 << 2 */
334 addk r6, r5, r5; /* << 1 */
335 addk r6, r6, r6; /* << 2 */
338 /* counting which exception happen */
339 lwi r5, r0, 0x200 + TOPHYS(r0_ram)
341 swi r5, r0, 0x200 + TOPHYS(r0_ram)
342 lwi r5, r6, 0x200 + TOPHYS(r0_ram)
344 swi r5, r6, 0x200 + TOPHYS(r0_ram)
347 /* Load the HW Exception vector */
348 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
351 full_exception_trapw:
353 bri full_exception_trap
355 /* Exceptions enabled here. This will allow nested exceptions */
358 swi r6, r1, 0; /* RMSR_OFFSET */
359 ori r6, r6, 0x100; /* Turn ON the EE bit */
360 andi r6, r6, ~2; /* Disable interrupts */
364 xori r6, r5, 1; /* 00001 = Unaligned Exception */
365 /* Jump to unalignment exception handler */
366 beqi r6, handle_unaligned_ex;
368 handle_other_ex: /* Handle Other exceptions here */
369 /* Save other volatiles before we make procedure calls below */
381 andi r6, r3, 0x1F; /* Load ESR[EC] */
382 lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
386 addk r8, r17, r0; /* Load exception address */
387 bralid r15, full_exception; /* Branch to the handler */
389 mts rfsr, r0; /* Clear sticky fsr */
393 * Trigger execution of the signal handler by enabling
394 * interrupts and calling an invalid syscall.
399 mts rmsr, r5; /* enable interrupt */
401 addi r12, r0, __NR_syscalls;
403 mfs r5, rmsr; /* disable interrupt */
419 bri ex_handler_done; /* Complete exception handling */
422 /* 0x01 - Unaligned data access exception
423 * This occurs when a word access is not aligned on a word boundary,
424 * or when a 16-bit access is not aligned on a 16-bit boundary.
425 * This handler perform the access, and returns, except for MMU when
426 * the unaligned address is last on a 4k page or the physical address is
427 * not found in the page table, in which case unaligned_data_trap is called.
430 /* Working registers already saved: R3, R4, R5, R6
435 andi r6, r3, 0x1000 /* Check ESR[DS] */
436 beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
437 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
440 /* jump to high level unaligned handler */
442 bri unaligned_data_trap
444 andi r6, r3, 0x3E0; /* Mask and extract the register operand */
445 srl r6, r6; /* r6 >> 5 */
450 /* Store the register operand in a temporary location */
451 sbi r6, r0, TOPHYS(ex_reg_op);
453 andi r6, r3, 0x400; /* Extract ESR[S] */
456 andi r6, r3, 0x800; /* Extract ESR[W] */
458 lbui r5, r4, 0; /* Exception address in r4 */
459 /* Load a word, byte-by-byte from destination address
460 and save it in tmp space */
461 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
463 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
465 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
467 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
468 /* Get the destination register value into r3 */
469 lwi r3, r0, TOPHYS(ex_tmp_data_loc_0);
472 lbui r5, r4, 0; /* Exception address in r4 */
473 /* Load a half-word, byte-by-byte from destination
474 address and save it in tmp space */
475 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
477 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
478 /* Get the destination register value into r3 */
479 lhui r3, r0, TOPHYS(ex_tmp_data_loc_0);
481 /* Get the destination register number into r5 */
482 lbui r5, r0, TOPHYS(ex_reg_op);
483 /* Form load_word jump table offset (lw_table + (8 * regnum)) */
484 la r6, r0, TOPHYS(lw_table);
490 ex_lw_end: /* Exception handling of load word, ends */
492 /* Get the destination register number into r5 */
493 lbui r5, r0, TOPHYS(ex_reg_op);
494 /* Form store_word jump table offset (sw_table + (8 * regnum)) */
495 la r6, r0, TOPHYS(sw_table);
504 andi r6, r6, 0x800; /* Extract ESR[W] */
506 /* Get the word - delay slot */
507 swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
508 /* Store the word, byte-by-byte into destination address */
509 lbui r3, r0, TOPHYS(ex_tmp_data_loc_0);
511 lbui r3, r0, TOPHYS(ex_tmp_data_loc_1);
513 lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
515 lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
520 /* Store the lower half-word, byte-by-byte into destination address */
521 swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
522 lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
524 lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
526 ex_sw_end: /* Exception handling of store word, ends. */
530 lwi r5, r1, 0 /* RMSR */
540 addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
548 /* Exception vector entry code. This code runs with address translation
549 * turned off (i.e. using physical addresses). */
551 /* Exception vectors. */
553 /* 0x10 - Data Storage Exception
554 * This happens for just a few reasons. U0 set (but we don't do that),
555 * or zone protection fault (user violation, write to protected page).
556 * If this is just an update of modified status, we do that quickly
557 * and exit. Otherwise, we call heavyweight functions to do the work.
559 handle_data_storage_exception:
560 /* Working registers already saved: R3, R4, R5, R6
566 mfs r3, rear /* Get faulting address */
568 /* If we are faulting a kernel address, we have to use the
569 * kernel page tables.
571 ori r4, r0, CONFIG_KERNEL_START
574 /* First, check if it was a zone fault (which means a user
575 * tried to access a kernel or read-protected page - always
576 * a SEGV). All other faults here must be stores, so no
577 * need to check ESR_S as well. */
580 andi r4, r4, 0x800 /* ESR_Z - zone protection */
583 ori r4, r0, swapper_pg_dir
584 mts rpid, r0 /* TLB will have 0 TID */
588 /* Get the PGD for the current thread. */
590 /* First, check if it was a zone fault (which means a user
591 * tried to access a kernel or read-protected page - always
592 * a SEGV). All other faults here must be stores, so no
593 * need to check ESR_S as well. */
596 andi r4, r4, 0x800 /* ESR_Z */
598 /* get current task address */
599 addi r4 ,CURRENT_TASK, TOPHYS(0);
600 lwi r4, r4, TASK_THREAD+PGDIR
603 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
605 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
607 lwi r4, r4, 0 /* Get L1 entry */
608 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
609 beqi r5, ex2 /* Bail if no table */
612 BSRLI(r6,r3,10) /* Compute PTE address */
614 andi r5, r5, 0xfffff003
616 lwi r4, r5, 0 /* Get Linux PTE */
618 andi r6, r4, _PAGE_RW /* Is it writeable? */
619 beqi r6, ex2 /* Bail if not */
621 /* Update 'changed' */
622 ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
623 swi r4, r5, 0 /* Update Linux page table */
625 /* Most of the Linux PTE is ready to load into the TLB LO.
626 * We set ZSEL, where only the LS-bit determines user access.
627 * We set execute, because we don't have the granularity to
628 * properly set this at the page level (Linux problem).
629 * If shared is set, we cause a zero PID->TID load.
630 * Many of these bits are software only. Bits we don't set
631 * here we (properly should) assume have the appropriate value.
633 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
634 ori r4, r4, _PAGE_HWEXEC /* make it executable */
636 /* find the TLB index that caused the fault. It has to be here*/
639 mfs r5, rtlbx /* DEBUG: TBD */
641 mts rtlblo, r4 /* Load TLB LO */
643 /* Will sync shadow TLBs */
645 /* Done...restore registers and get out of here. */
654 /* The bailout. Restore registers to pre-exception conditions
655 * and call the heavyweights to help us out. */
660 bri page_fault_data_trap
663 /* 0x11 - Instruction Storage Exception
664 * This is caused by a fetch from non-execute or guarded pages. */
665 handle_instruction_storage_exception:
666 /* Working registers already saved: R3, R4, R5, R6
670 mfs r3, rear /* Get faulting address */
673 bri page_fault_instr_trap
675 /* 0x12 - Data TLB Miss Exception
676 * As the name implies, translation is not in the MMU, so search the
677 * page tables and fix it. The only purpose of this function is to
678 * load TLB entries from the page table if they exist.
680 handle_data_tlb_miss_exception:
681 /* Working registers already saved: R3, R4, R5, R6
687 mfs r3, rear /* Get faulting address */
690 /* If we are faulting a kernel address, we have to use the
691 * kernel page tables. */
692 ori r4, r0, CONFIG_KERNEL_START
695 ori r4, r0, swapper_pg_dir
696 mts rpid, r0 /* TLB will have 0 TID */
700 /* Get the PGD for the current thread. */
702 /* get current task address */
703 addi r4 ,CURRENT_TASK, TOPHYS(0);
704 lwi r4, r4, TASK_THREAD+PGDIR
707 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
709 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
711 lwi r4, r4, 0 /* Get L1 entry */
712 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
713 beqi r5, ex7 /* Bail if no table */
716 BSRLI(r6,r3,10) /* Compute PTE address */
718 andi r5, r5, 0xfffff003
720 lwi r4, r5, 0 /* Get Linux PTE */
722 andi r6, r4, _PAGE_PRESENT
725 ori r4, r4, _PAGE_ACCESSED
728 /* Most of the Linux PTE is ready to load into the TLB LO.
729 * We set ZSEL, where only the LS-bit determines user access.
730 * We set execute, because we don't have the granularity to
731 * properly set this at the page level (Linux problem).
732 * If shared is set, we cause a zero PID->TID load.
733 * Many of these bits are software only. Bits we don't set
734 * here we (properly should) assume have the appropriate value.
736 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
740 /* The bailout. Restore registers to pre-exception conditions
741 * and call the heavyweights to help us out.
747 bri page_fault_data_trap
749 /* 0x13 - Instruction TLB Miss Exception
750 * Nearly the same as above, except we get our information from
751 * different registers and bailout to a different point.
753 handle_instruction_tlb_miss_exception:
754 /* Working registers already saved: R3, R4, R5, R6
760 mfs r3, rear /* Get faulting address */
763 /* If we are faulting a kernel address, we have to use the
764 * kernel page tables.
766 ori r4, r0, CONFIG_KERNEL_START
769 ori r4, r0, swapper_pg_dir
770 mts rpid, r0 /* TLB will have 0 TID */
774 /* Get the PGD for the current thread. */
776 /* get current task address */
777 addi r4 ,CURRENT_TASK, TOPHYS(0);
778 lwi r4, r4, TASK_THREAD+PGDIR
781 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
783 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
785 lwi r4, r4, 0 /* Get L1 entry */
786 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
787 beqi r5, ex10 /* Bail if no table */
790 BSRLI(r6,r3,10) /* Compute PTE address */
792 andi r5, r5, 0xfffff003
794 lwi r4, r5, 0 /* Get Linux PTE */
796 andi r6, r4, _PAGE_PRESENT
799 ori r4, r4, _PAGE_ACCESSED
802 /* Most of the Linux PTE is ready to load into the TLB LO.
803 * We set ZSEL, where only the LS-bit determines user access.
804 * We set execute, because we don't have the granularity to
805 * properly set this at the page level (Linux problem).
806 * If shared is set, we cause a zero PID->TID load.
807 * Many of these bits are software only. Bits we don't set
808 * here we (properly should) assume have the appropriate value.
810 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
814 /* The bailout. Restore registers to pre-exception conditions
815 * and call the heavyweights to help us out.
821 bri page_fault_instr_trap
823 /* Both the instruction and data TLB miss get to this point to load the TLB.
825 * r4 - TLB LO (info from Linux PTE)
826 * r5, r6 - available to use
827 * PID - loaded with proper value when we get here
828 * Upon exit, we reload everything and RFI.
829 * A common place to load the TLB.
832 .long 1 /* MS: storing last used tlb index */
834 /* MS: load the last used TLB index. */
835 lwi r5, r0, TOPHYS(tlb_index)
836 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
838 /* MS: FIXME this is potential fault, because this is mask not count */
839 andi r5, r5, (MICROBLAZE_TLB_SIZE-1)
845 /* MS: save back current TLB index */
846 swi r5, r0, TOPHYS(tlb_index)
848 ori r4, r4, _PAGE_HWEXEC /* make it executable */
849 mts rtlbx, r5 /* MS: save current TLB */
851 mts rtlblo, r4 /* MS: save to TLB LO */
854 /* Create EPN. This is the faulting address plus a static
855 * set of bits. These are size, valid, E, U0, and ensure
856 * bits 20 and 21 are zero.
858 andi r3, r3, 0xfffff000
860 mts rtlbhi, r3 /* Load TLB HI */
863 /* Done...restore registers and get out of here. */
872 /* extern void giveup_fpu(struct task_struct *prev)
874 * The MicroBlaze processor may have an FPU, so this should not just
880 bralid r15,0 /* TBD */
883 /* At present, this routine just hangs. - extern void abort(void) */
892 mts rpid, r5 /* Shadow TLBs are automatically */
894 bri 4 /* flushed by changing PID */
899 .end _hw_exception_handler
902 /* Unaligned data access exception last on a 4k page for MMU.
903 * When this is called, we are in virtual mode with exceptions enabled
904 * and registers 1-13,15,17,18 saved.
908 * R7 = pointer to saved registers (struct pt_regs *regs)
910 * This handler perform the access, and returns via ret_from_exc.
912 .global _unaligned_data_exception
913 .ent _unaligned_data_exception
914 _unaligned_data_exception:
915 andi r8, r3, 0x3E0; /* Mask and extract the register operand */
916 BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */
917 andi r6, r3, 0x400; /* Extract ESR[S] */
919 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
922 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
923 /* Load a word, byte-by-byte from destination address and save it in tmp space*/
924 la r6, r0, ex_tmp_data_loc_0;
926 load2: lbui r5, r4, 1;
928 load3: lbui r5, r4, 2;
930 load4: lbui r5, r4, 3;
933 /* Get the destination register value into r3 - delay slot */
936 /* Load a half-word, byte-by-byte from destination address and
937 * save it in tmp space */
938 la r6, r0, ex_tmp_data_loc_0;
940 load5: lbui r5, r4, 1;
942 lhui r3, r6, 0; /* Get the destination register value into r3 */
944 /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
945 addik r5, r8, lw_table_vm;
947 ex_lw_end_vm: /* Exception handling of load word, ends */
950 /* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
951 addik r5, r8, sw_table_vm;
954 la r5, r0, ex_tmp_data_loc_0;
956 swi r3, r5, 0; /* Get the word - delay slot */
957 /* Store the word, byte-by-byte into destination address */
959 store1: sbi r3, r4, 0;
961 store2: sbi r3, r4, 1;
963 store3: sbi r3, r4, 2;
966 store4: sbi r3, r4, 3; /* Delay slot */
968 /* Store the lower half-word, byte-by-byte into destination address */
970 store5: sbi r3, r4, 0;
973 store6: sbi r3, r4, 1; /* Delay slot */
974 ex_sw_end_vm: /* Exception handling of store word, ends. */
976 /* We have to prevent cases that get/put_user macros get unaligned pointer
977 * to bad page area. We have to find out which origin instruction caused it
978 * and called fixup for that origin instruction not instruction in unaligned
981 ori r5, r7, 0 /* setup pointer to pt_regs */
982 lwi r6, r7, PT_PC; /* faulting address is one instruction above */
983 addik r6, r6, -4 /* for finding proper fixup */
984 swi r6, r7, PT_PC; /* a save back it to PT_PC */
985 addik r7, r0, SIGSEGV
986 /* call bad_page_fault for finding aligned fixup, fixup address is saved
987 * in PT_PC which is used as return address from exception */
988 la r15, r0, ret_from_exc-8 /* setup return address */
992 /* We prevent all load/store because it could failed any attempt to access */
993 .section __ex_table,"a";
994 .word load1,ex_unaligned_fixup;
995 .word load2,ex_unaligned_fixup;
996 .word load3,ex_unaligned_fixup;
997 .word load4,ex_unaligned_fixup;
998 .word load5,ex_unaligned_fixup;
999 .word store1,ex_unaligned_fixup;
1000 .word store2,ex_unaligned_fixup;
1001 .word store3,ex_unaligned_fixup;
1002 .word store4,ex_unaligned_fixup;
1003 .word store5,ex_unaligned_fixup;
1004 .word store6,ex_unaligned_fixup;
1006 .end _unaligned_data_exception
1007 #endif /* CONFIG_MMU */
1009 ex_handler_unhandled:
1010 /* FIXME add handle function for unhandled exception - dump register */
1014 * hw_exception_handler Jump Table
1015 * - Contains code snippets for each register that caused the unalign exception
1016 * - Hence exception handler is NOT self-modifying
1017 * - Separate table for load exceptions and store exceptions.
1018 * - Each table is of size: (8 * 32) = 256 bytes
1024 lw_r0: R3_TO_LWREG (0);
1026 lw_r2: R3_TO_LWREG (2);
1027 lw_r3: R3_TO_LWREG_V (3);
1028 lw_r4: R3_TO_LWREG_V (4);
1029 lw_r5: R3_TO_LWREG_V (5);
1030 lw_r6: R3_TO_LWREG_V (6);
1031 lw_r7: R3_TO_LWREG (7);
1032 lw_r8: R3_TO_LWREG (8);
1033 lw_r9: R3_TO_LWREG (9);
1034 lw_r10: R3_TO_LWREG (10);
1035 lw_r11: R3_TO_LWREG (11);
1036 lw_r12: R3_TO_LWREG (12);
1037 lw_r13: R3_TO_LWREG (13);
1038 lw_r14: R3_TO_LWREG (14);
1039 lw_r15: R3_TO_LWREG (15);
1040 lw_r16: R3_TO_LWREG (16);
1042 lw_r18: R3_TO_LWREG (18);
1043 lw_r19: R3_TO_LWREG (19);
1044 lw_r20: R3_TO_LWREG (20);
1045 lw_r21: R3_TO_LWREG (21);
1046 lw_r22: R3_TO_LWREG (22);
1047 lw_r23: R3_TO_LWREG (23);
1048 lw_r24: R3_TO_LWREG (24);
1049 lw_r25: R3_TO_LWREG (25);
1050 lw_r26: R3_TO_LWREG (26);
1051 lw_r27: R3_TO_LWREG (27);
1052 lw_r28: R3_TO_LWREG (28);
1053 lw_r29: R3_TO_LWREG (29);
1054 lw_r30: R3_TO_LWREG (30);
1056 lw_r31: R3_TO_LWREG_V (31);
1058 lw_r31: R3_TO_LWREG (31);
1062 sw_r0: SWREG_TO_R3 (0);
1064 sw_r2: SWREG_TO_R3 (2);
1065 sw_r3: SWREG_TO_R3_V (3);
1066 sw_r4: SWREG_TO_R3_V (4);
1067 sw_r5: SWREG_TO_R3_V (5);
1068 sw_r6: SWREG_TO_R3_V (6);
1069 sw_r7: SWREG_TO_R3 (7);
1070 sw_r8: SWREG_TO_R3 (8);
1071 sw_r9: SWREG_TO_R3 (9);
1072 sw_r10: SWREG_TO_R3 (10);
1073 sw_r11: SWREG_TO_R3 (11);
1074 sw_r12: SWREG_TO_R3 (12);
1075 sw_r13: SWREG_TO_R3 (13);
1076 sw_r14: SWREG_TO_R3 (14);
1077 sw_r15: SWREG_TO_R3 (15);
1078 sw_r16: SWREG_TO_R3 (16);
1080 sw_r18: SWREG_TO_R3 (18);
1081 sw_r19: SWREG_TO_R3 (19);
1082 sw_r20: SWREG_TO_R3 (20);
1083 sw_r21: SWREG_TO_R3 (21);
1084 sw_r22: SWREG_TO_R3 (22);
1085 sw_r23: SWREG_TO_R3 (23);
1086 sw_r24: SWREG_TO_R3 (24);
1087 sw_r25: SWREG_TO_R3 (25);
1088 sw_r26: SWREG_TO_R3 (26);
1089 sw_r27: SWREG_TO_R3 (27);
1090 sw_r28: SWREG_TO_R3 (28);
1091 sw_r29: SWREG_TO_R3 (29);
1092 sw_r30: SWREG_TO_R3 (30);
1094 sw_r31: SWREG_TO_R3_V (31);
1096 sw_r31: SWREG_TO_R3 (31);
1101 lw_r0_vm: R3_TO_LWREG_VM (0);
1102 lw_r1_vm: R3_TO_LWREG_VM_V (1);
1103 lw_r2_vm: R3_TO_LWREG_VM_V (2);
1104 lw_r3_vm: R3_TO_LWREG_VM_V (3);
1105 lw_r4_vm: R3_TO_LWREG_VM_V (4);
1106 lw_r5_vm: R3_TO_LWREG_VM_V (5);
1107 lw_r6_vm: R3_TO_LWREG_VM_V (6);
1108 lw_r7_vm: R3_TO_LWREG_VM_V (7);
1109 lw_r8_vm: R3_TO_LWREG_VM_V (8);
1110 lw_r9_vm: R3_TO_LWREG_VM_V (9);
1111 lw_r10_vm: R3_TO_LWREG_VM_V (10);
1112 lw_r11_vm: R3_TO_LWREG_VM_V (11);
1113 lw_r12_vm: R3_TO_LWREG_VM_V (12);
1114 lw_r13_vm: R3_TO_LWREG_VM_V (13);
1115 lw_r14_vm: R3_TO_LWREG_VM (14);
1116 lw_r15_vm: R3_TO_LWREG_VM_V (15);
1117 lw_r16_vm: R3_TO_LWREG_VM (16);
1118 lw_r17_vm: R3_TO_LWREG_VM_V (17);
1119 lw_r18_vm: R3_TO_LWREG_VM_V (18);
1120 lw_r19_vm: R3_TO_LWREG_VM (19);
1121 lw_r20_vm: R3_TO_LWREG_VM (20);
1122 lw_r21_vm: R3_TO_LWREG_VM (21);
1123 lw_r22_vm: R3_TO_LWREG_VM (22);
1124 lw_r23_vm: R3_TO_LWREG_VM (23);
1125 lw_r24_vm: R3_TO_LWREG_VM (24);
1126 lw_r25_vm: R3_TO_LWREG_VM (25);
1127 lw_r26_vm: R3_TO_LWREG_VM (26);
1128 lw_r27_vm: R3_TO_LWREG_VM (27);
1129 lw_r28_vm: R3_TO_LWREG_VM (28);
1130 lw_r29_vm: R3_TO_LWREG_VM (29);
1131 lw_r30_vm: R3_TO_LWREG_VM (30);
1132 lw_r31_vm: R3_TO_LWREG_VM_V (31);
1135 sw_r0_vm: SWREG_TO_R3_VM (0);
1136 sw_r1_vm: SWREG_TO_R3_VM_V (1);
1137 sw_r2_vm: SWREG_TO_R3_VM_V (2);
1138 sw_r3_vm: SWREG_TO_R3_VM_V (3);
1139 sw_r4_vm: SWREG_TO_R3_VM_V (4);
1140 sw_r5_vm: SWREG_TO_R3_VM_V (5);
1141 sw_r6_vm: SWREG_TO_R3_VM_V (6);
1142 sw_r7_vm: SWREG_TO_R3_VM_V (7);
1143 sw_r8_vm: SWREG_TO_R3_VM_V (8);
1144 sw_r9_vm: SWREG_TO_R3_VM_V (9);
1145 sw_r10_vm: SWREG_TO_R3_VM_V (10);
1146 sw_r11_vm: SWREG_TO_R3_VM_V (11);
1147 sw_r12_vm: SWREG_TO_R3_VM_V (12);
1148 sw_r13_vm: SWREG_TO_R3_VM_V (13);
1149 sw_r14_vm: SWREG_TO_R3_VM (14);
1150 sw_r15_vm: SWREG_TO_R3_VM_V (15);
1151 sw_r16_vm: SWREG_TO_R3_VM (16);
1152 sw_r17_vm: SWREG_TO_R3_VM_V (17);
1153 sw_r18_vm: SWREG_TO_R3_VM_V (18);
1154 sw_r19_vm: SWREG_TO_R3_VM (19);
1155 sw_r20_vm: SWREG_TO_R3_VM (20);
1156 sw_r21_vm: SWREG_TO_R3_VM (21);
1157 sw_r22_vm: SWREG_TO_R3_VM (22);
1158 sw_r23_vm: SWREG_TO_R3_VM (23);
1159 sw_r24_vm: SWREG_TO_R3_VM (24);
1160 sw_r25_vm: SWREG_TO_R3_VM (25);
1161 sw_r26_vm: SWREG_TO_R3_VM (26);
1162 sw_r27_vm: SWREG_TO_R3_VM (27);
1163 sw_r28_vm: SWREG_TO_R3_VM (28);
1164 sw_r29_vm: SWREG_TO_R3_VM (29);
1165 sw_r30_vm: SWREG_TO_R3_VM (30);
1166 sw_r31_vm: SWREG_TO_R3_VM_V (31);
1167 #endif /* CONFIG_MMU */
1169 /* Temporary data structures used in the handler */