arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/pci.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/timer.h>
  40 #include <asm/i8259.h>
  41 #include <asm/nmi.h>
  42 #include <asm/msidef.h>
  43
  44 #include <mach_apic.h>
  45 #include <mach_apicdef.h>
  46
  47 #include "io_ports.h"
  48
  49 int (*ioapic_renumber_irq)(int ioapic, int irq);
  50 atomic_t irq_mis_count;
  51
  52 /* Where if anywhere is the i8259 connect in external int mode */
  53 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  54
  55 static DEFINE_SPINLOCK(ioapic_lock);
  56 static DEFINE_SPINLOCK(vector_lock);
  57
  58 int timer_over_8254 __initdata = 1;
  59
  60 /*
  61  *      Is the SiS APIC rmw bug present ?
  62  *      -1 = don't know, 0 = no, 1 = yes
  63  */
  64 int sis_apic_bug = -1;
  65
  66 /*
  67  * # of IRQ routing registers
  68  */
  69 int nr_ioapic_registers[MAX_IO_APICS];
  70
  71 static int disable_timer_pin_1 __initdata;
  72
  73 /*
  74  * Rough estimation of how many shared IRQs there are, can
  75  * be changed anytime.
  76  */
  77 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  79
  80 /*
  81  * This is performance-critical, we want to do it O(1)
  82  *
  83  * the indexing order of this array favors 1:1 mappings
  84  * between pins and IRQs.
  85  */
  86
  87 static struct irq_pin_list {
  88         int apic, pin, next;
  89 } irq_2_pin[PIN_MAP_SIZE];
  90
  91 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  92 #ifdef CONFIG_PCI_MSI
  93 #define vector_to_irq(vector)   \
  94         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  95 #else
  96 #define vector_to_irq(vector)   (vector)
  97 #endif
  98
  99
 100 union entry_union {
 101         struct { u32 w1, w2; };
 102         struct IO_APIC_route_entry entry;
 103 };
 104
 105 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 106 {
 107         union entry_union eu;
 108         unsigned long flags;
 109         spin_lock_irqsave(&ioapic_lock, flags);
 110         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 111         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 112         spin_unlock_irqrestore(&ioapic_lock, flags);
 113         return eu.entry;
 114 }
 115
 116 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 117 {
 118         unsigned long flags;
 119         union entry_union eu;
 120         eu.entry = e;
 121         spin_lock_irqsave(&ioapic_lock, flags);
 122         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 123         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 124         spin_unlock_irqrestore(&ioapic_lock, flags);
 125 }
 126
 127 /*
 128  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 129  * shared ISA-space IRQs, so we have to support them. We are super
 130  * fast in the common case, and fast for shared ISA-space IRQs.
 131  */
 132 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 133 {
 134         static int first_free_entry = NR_IRQS;
 135         struct irq_pin_list *entry = irq_2_pin + irq;
 136
 137         while (entry->next)
 138                 entry = irq_2_pin + entry->next;
 139
 140         if (entry->pin != -1) {
 141                 entry->next = first_free_entry;
 142                 entry = irq_2_pin + entry->next;
 143                 if (++first_free_entry >= PIN_MAP_SIZE)
 144                         panic("io_apic.c: whoops");
 145         }
 146         entry->apic = apic;
 147         entry->pin = pin;
 148 }
 149
 150 /*
 151  * Reroute an IRQ to a different pin.
 152  */
 153 static void __init replace_pin_at_irq(unsigned int irq,
 154                                       int oldapic, int oldpin,
 155                                       int newapic, int newpin)
 156 {
 157         struct irq_pin_list *entry = irq_2_pin + irq;
 158
 159         while (1) {
 160                 if (entry->apic == oldapic && entry->pin == oldpin) {
 161                         entry->apic = newapic;
 162                         entry->pin = newpin;
 163                 }
 164                 if (!entry->next)
 165                         break;
 166                 entry = irq_2_pin + entry->next;
 167         }
 168 }
 169
 170 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 171 {
 172         struct irq_pin_list *entry = irq_2_pin + irq;
 173         unsigned int pin, reg;
 174
 175         for (;;) {
 176                 pin = entry->pin;
 177                 if (pin == -1)
 178                         break;
 179                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 180                 reg &= ~disable;
 181                 reg |= enable;
 182                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 183                 if (!entry->next)
 184                         break;
 185                 entry = irq_2_pin + entry->next;
 186         }
 187 }
 188
 189 /* mask = 1 */
 190 static void __mask_IO_APIC_irq (unsigned int irq)
 191 {
 192         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 193 }
 194
 195 /* mask = 0 */
 196 static void __unmask_IO_APIC_irq (unsigned int irq)
 197 {
 198         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 199 }
 200
 201 /* mask = 1, trigger = 0 */
 202 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 203 {
 204         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 205 }
 206
 207 /* mask = 0, trigger = 1 */
 208 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 209 {
 210         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 211 }
 212
 213 static void mask_IO_APIC_irq (unsigned int irq)
 214 {
 215         unsigned long flags;
 216
 217         spin_lock_irqsave(&ioapic_lock, flags);
 218         __mask_IO_APIC_irq(irq);
 219         spin_unlock_irqrestore(&ioapic_lock, flags);
 220 }
 221
 222 static void unmask_IO_APIC_irq (unsigned int irq)
 223 {
 224         unsigned long flags;
 225
 226         spin_lock_irqsave(&ioapic_lock, flags);
 227         __unmask_IO_APIC_irq(irq);
 228         spin_unlock_irqrestore(&ioapic_lock, flags);
 229 }
 230
 231 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 232 {
 233         struct IO_APIC_route_entry entry;
 234
 235         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 236         entry = ioapic_read_entry(apic, pin);
 237         if (entry.delivery_mode == dest_SMI)
 238                 return;
 239
 240         /*
 241          * Disable it in the IO-APIC irq-routing table:
 242          */
 243         memset(&entry, 0, sizeof(entry));
 244         entry.mask = 1;
 245         ioapic_write_entry(apic, pin, entry);
 246 }
 247
 248 static void clear_IO_APIC (void)
 249 {
 250         int apic, pin;
 251
 252         for (apic = 0; apic < nr_ioapics; apic++)
 253                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 254                         clear_IO_APIC_pin(apic, pin);
 255 }
 256
 257 #ifdef CONFIG_SMP
 258 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 259 {
 260         unsigned long flags;
 261         int pin;
 262         struct irq_pin_list *entry = irq_2_pin + irq;
 263         unsigned int apicid_value;
 264         cpumask_t tmp;
 265
 266         cpus_and(tmp, cpumask, cpu_online_map);
 267         if (cpus_empty(tmp))
 268                 tmp = TARGET_CPUS;
 269
 270         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 271
 272         apicid_value = cpu_mask_to_apicid(cpumask);
 273         /* Prepare to do the io_apic_write */
 274         apicid_value = apicid_value << 24;
 275         spin_lock_irqsave(&ioapic_lock, flags);
 276         for (;;) {
 277                 pin = entry->pin;
 278                 if (pin == -1)
 279                         break;
 280                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 281                 if (!entry->next)
 282                         break;
 283                 entry = irq_2_pin + entry->next;
 284         }
 285         set_irq_info(irq, cpumask);
 286         spin_unlock_irqrestore(&ioapic_lock, flags);
 287 }
 288
 289 #if defined(CONFIG_IRQBALANCE)
 290 # include <asm/processor.h>     /* kernel_thread() */
 291 # include <linux/kernel_stat.h> /* kstat */
 292 # include <linux/slab.h>                /* kmalloc() */
 293 # include <linux/timer.h>       /* time_after() */
 294
 295 #ifdef CONFIG_BALANCED_IRQ_DEBUG
 296 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 297 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 298 # else
 299 #  define TDprintk(x...)
 300 #  define Dprintk(x...)
 301 # endif
 302
 303 #define IRQBALANCE_CHECK_ARCH -999
 304 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 305 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 306 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 307 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 308
 309 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 310 static int physical_balance __read_mostly;
 311 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 312
 313 static struct irq_cpu_info {
 314         unsigned long * last_irq;
 315         unsigned long * irq_delta;
 316         unsigned long irq;
 317 } irq_cpu_data[NR_CPUS];
 318
 319 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 320 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 321 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 322
 323 #define IDLE_ENOUGH(cpu,now) \
 324         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 325
 326 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 327
 328 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 329
 330 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 331         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 332 };
 333
 334 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 335 {
 336         balance_irq_affinity[irq] = mask;
 337 }
 338
 339 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 340                         unsigned long now, int direction)
 341 {
 342         int search_idle = 1;
 343         int cpu = curr_cpu;
 344
 345         goto inside;
 346
 347         do {
 348                 if (unlikely(cpu == curr_cpu))
 349                         search_idle = 0;
 350 inside:
 351                 if (direction == 1) {
 352                         cpu++;
 353                         if (cpu >= NR_CPUS)
 354                                 cpu = 0;
 355                 } else {
 356                         cpu--;
 357                         if (cpu == -1)
 358                                 cpu = NR_CPUS-1;
 359                 }
 360         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 361                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 362
 363         return cpu;
 364 }
 365
 366 static inline void balance_irq(int cpu, int irq)
 367 {
 368         unsigned long now = jiffies;
 369         cpumask_t allowed_mask;
 370         unsigned int new_cpu;
 371
 372         if (irqbalance_disabled)
 373                 return;
 374
 375         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 376         new_cpu = move(cpu, allowed_mask, now, 1);
 377         if (cpu != new_cpu) {
 378                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 379         }
 380 }
 381
 382 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 383 {
 384         int i, j;
 385         Dprintk("Rotating IRQs among CPUs.\n");
 386         for_each_online_cpu(i) {
 387                 for (j = 0; j < NR_IRQS; j++) {
 388                         if (!irq_desc[j].action)
 389                                 continue;
 390                         /* Is it a significant load ?  */
 391                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 392                                                 useful_load_threshold)
 393                                 continue;
 394                         balance_irq(i, j);
 395                 }
 396         }
 397         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 398                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 399         return;
 400 }
 401
 402 static void do_irq_balance(void)
 403 {
 404         int i, j;
 405         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 406         unsigned long move_this_load = 0;
 407         int max_loaded = 0, min_loaded = 0;
 408         int load;
 409         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 410         int selected_irq;
 411         int tmp_loaded, first_attempt = 1;
 412         unsigned long tmp_cpu_irq;
 413         unsigned long imbalance = 0;
 414         cpumask_t allowed_mask, target_cpu_mask, tmp;
 415
 416         for_each_possible_cpu(i) {
 417                 int package_index;
 418                 CPU_IRQ(i) = 0;
 419                 if (!cpu_online(i))
 420                         continue;
 421                 package_index = CPU_TO_PACKAGEINDEX(i);
 422                 for (j = 0; j < NR_IRQS; j++) {
 423                         unsigned long value_now, delta;
 424                         /* Is this an active IRQ? */
 425                         if (!irq_desc[j].action)
 426                                 continue;
 427                         if ( package_index == i )
 428                                 IRQ_DELTA(package_index,j) = 0;
 429                         /* Determine the total count per processor per IRQ */
 430                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 431
 432                         /* Determine the activity per processor per IRQ */
 433                         delta = value_now - LAST_CPU_IRQ(i,j);
 434
 435                         /* Update last_cpu_irq[][] for the next time */
 436                         LAST_CPU_IRQ(i,j) = value_now;
 437
 438                         /* Ignore IRQs whose rate is less than the clock */
 439                         if (delta < useful_load_threshold)
 440                                 continue;
 441                         /* update the load for the processor or package total */
 442                         IRQ_DELTA(package_index,j) += delta;
 443
 444                         /* Keep track of the higher numbered sibling as well */
 445                         if (i != package_index)
 446                                 CPU_IRQ(i) += delta;
 447                         /*
 448                          * We have sibling A and sibling B in the package
 449                          *
 450                          * cpu_irq[A] = load for cpu A + load for cpu B
 451                          * cpu_irq[B] = load for cpu B
 452                          */
 453                         CPU_IRQ(package_index) += delta;
 454                 }
 455         }
 456         /* Find the least loaded processor package */
 457         for_each_online_cpu(i) {
 458                 if (i != CPU_TO_PACKAGEINDEX(i))
 459                         continue;
 460                 if (min_cpu_irq > CPU_IRQ(i)) {
 461                         min_cpu_irq = CPU_IRQ(i);
 462                         min_loaded = i;
 463                 }
 464         }
 465         max_cpu_irq = ULONG_MAX;
 466
 467 tryanothercpu:
 468         /* Look for heaviest loaded processor.
 469          * We may come back to get the next heaviest loaded processor.
 470          * Skip processors with trivial loads.
 471          */
 472         tmp_cpu_irq = 0;
 473         tmp_loaded = -1;
 474         for_each_online_cpu(i) {
 475                 if (i != CPU_TO_PACKAGEINDEX(i))
 476                         continue;
 477                 if (max_cpu_irq <= CPU_IRQ(i))
 478                         continue;
 479                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 480                         tmp_cpu_irq = CPU_IRQ(i);
 481                         tmp_loaded = i;
 482                 }
 483         }
 484
 485         if (tmp_loaded == -1) {
 486          /* In the case of small number of heavy interrupt sources,
 487           * loading some of the cpus too much. We use Ingo's original
 488           * approach to rotate them around.
 489           */
 490                 if (!first_attempt && imbalance >= useful_load_threshold) {
 491                         rotate_irqs_among_cpus(useful_load_threshold);
 492                         return;
 493                 }
 494                 goto not_worth_the_effort;
 495         }
 496
 497         first_attempt = 0;              /* heaviest search */
 498         max_cpu_irq = tmp_cpu_irq;      /* load */
 499         max_loaded = tmp_loaded;        /* processor */
 500         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 501
 502         Dprintk("max_loaded cpu = %d\n", max_loaded);
 503         Dprintk("min_loaded cpu = %d\n", min_loaded);
 504         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 505         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 506         Dprintk("load imbalance = %lu\n", imbalance);
 507
 508         /* if imbalance is less than approx 10% of max load, then
 509          * observe diminishing returns action. - quit
 510          */
 511         if (imbalance < (max_cpu_irq >> 3)) {
 512                 Dprintk("Imbalance too trivial\n");
 513                 goto not_worth_the_effort;
 514         }
 515
 516 tryanotherirq:
 517         /* if we select an IRQ to move that can't go where we want, then
 518          * see if there is another one to try.
 519          */
 520         move_this_load = 0;
 521         selected_irq = -1;
 522         for (j = 0; j < NR_IRQS; j++) {
 523                 /* Is this an active IRQ? */
 524                 if (!irq_desc[j].action)
 525                         continue;
 526                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 527                         continue;
 528                 /* Try to find the IRQ that is closest to the imbalance
 529                  * without going over.
 530                  */
 531                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 532                         move_this_load = IRQ_DELTA(max_loaded,j);
 533                         selected_irq = j;
 534                 }
 535         }
 536         if (selected_irq == -1) {
 537                 goto tryanothercpu;
 538         }
 539
 540         imbalance = move_this_load;
 541
 542         /* For physical_balance case, we accumlated both load
 543          * values in the one of the siblings cpu_irq[],
 544          * to use the same code for physical and logical processors
 545          * as much as possible.
 546          *
 547          * NOTE: the cpu_irq[] array holds the sum of the load for
 548          * sibling A and sibling B in the slot for the lowest numbered
 549          * sibling (A), _AND_ the load for sibling B in the slot for
 550          * the higher numbered sibling.
 551          *
 552          * We seek the least loaded sibling by making the comparison
 553          * (A+B)/2 vs B
 554          */
 555         load = CPU_IRQ(min_loaded) >> 1;
 556         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 557                 if (load > CPU_IRQ(j)) {
 558                         /* This won't change cpu_sibling_map[min_loaded] */
 559                         load = CPU_IRQ(j);
 560                         min_loaded = j;
 561                 }
 562         }
 563
 564         cpus_and(allowed_mask,
 565                 cpu_online_map,
 566                 balance_irq_affinity[selected_irq]);
 567         target_cpu_mask = cpumask_of_cpu(min_loaded);
 568         cpus_and(tmp, target_cpu_mask, allowed_mask);
 569
 570         if (!cpus_empty(tmp)) {
 571
 572                 Dprintk("irq = %d moved to cpu = %d\n",
 573                                 selected_irq, min_loaded);
 574                 /* mark for change destination */
 575                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 576
 577                 /* Since we made a change, come back sooner to
 578                  * check for more variation.
 579                  */
 580                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 581                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 582                 return;
 583         }
 584         goto tryanotherirq;
 585
 586 not_worth_the_effort:
 587         /*
 588          * if we did not find an IRQ to move, then adjust the time interval
 589          * upward
 590          */
 591         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 592                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 593         Dprintk("IRQ worth rotating not found\n");
 594         return;
 595 }
 596
 597 static int balanced_irq(void *unused)
 598 {
 599         int i;
 600         unsigned long prev_balance_time = jiffies;
 601         long time_remaining = balanced_irq_interval;
 602
 603         daemonize("kirqd");
 604
 605         /* push everything to CPU 0 to give us a starting point.  */
 606         for (i = 0 ; i < NR_IRQS ; i++) {
 607                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 608                 set_pending_irq(i, cpumask_of_cpu(0));
 609         }
 610
 611         for ( ; ; ) {
 612                 time_remaining = schedule_timeout_interruptible(time_remaining);
 613                 try_to_freeze();
 614                 if (time_after(jiffies,
 615                                 prev_balance_time+balanced_irq_interval)) {
 616                         preempt_disable();
 617                         do_irq_balance();
 618                         prev_balance_time = jiffies;
 619                         time_remaining = balanced_irq_interval;
 620                         preempt_enable();
 621                 }
 622         }
 623         return 0;
 624 }
 625
 626 static int __init balanced_irq_init(void)
 627 {
 628         int i;
 629         struct cpuinfo_x86 *c;
 630         cpumask_t tmp;
 631
 632         cpus_shift_right(tmp, cpu_online_map, 2);
 633         c = &boot_cpu_data;
 634         /* When not overwritten by the command line ask subarchitecture. */
 635         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 636                 irqbalance_disabled = NO_BALANCE_IRQ;
 637         if (irqbalance_disabled)
 638                 return 0;
 639
 640          /* disable irqbalance completely if there is only one processor online */
 641         if (num_online_cpus() < 2) {
 642                 irqbalance_disabled = 1;
 643                 return 0;
 644         }
 645         /*
 646          * Enable physical balance only if more than 1 physical processor
 647          * is present
 648          */
 649         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 650                 physical_balance = 1;
 651
 652         for_each_online_cpu(i) {
 653                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 654                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 655                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 656                         printk(KERN_ERR "balanced_irq_init: out of memory");
 657                         goto failed;
 658                 }
 659                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 660                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 661         }
 662
 663         printk(KERN_INFO "Starting balanced_irq\n");
 664         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 665                 return 0;
 666         else
 667                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 668 failed:
 669         for_each_possible_cpu(i) {
 670                 kfree(irq_cpu_data[i].irq_delta);
 671                 irq_cpu_data[i].irq_delta = NULL;
 672                 kfree(irq_cpu_data[i].last_irq);
 673                 irq_cpu_data[i].last_irq = NULL;
 674         }
 675         return 0;
 676 }
 677
 678 int __init irqbalance_disable(char *str)
 679 {
 680         irqbalance_disabled = 1;
 681         return 1;
 682 }
 683
 684 __setup("noirqbalance", irqbalance_disable);
 685
 686 late_initcall(balanced_irq_init);
 687 #endif /* CONFIG_IRQBALANCE */
 688 #endif /* CONFIG_SMP */
 689
 690 #ifndef CONFIG_SMP
 691 void fastcall send_IPI_self(int vector)
 692 {
 693         unsigned int cfg;
 694
 695         /*
 696          * Wait for idle.
 697          */
 698         apic_wait_icr_idle();
 699         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 700         /*
 701          * Send the IPI. The write to APIC_ICR fires this off.
 702          */
 703         apic_write_around(APIC_ICR, cfg);
 704 }
 705 #endif /* !CONFIG_SMP */
 706
 707
 708 /*
 709  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 710  * specific CPU-side IRQs.
 711  */
 712
 713 #define MAX_PIRQS 8
 714 static int pirq_entries [MAX_PIRQS];
 715 static int pirqs_enabled;
 716 int skip_ioapic_setup;
 717
 718 static int __init ioapic_setup(char *str)
 719 {
 720         skip_ioapic_setup = 1;
 721         return 1;
 722 }
 723
 724 __setup("noapic", ioapic_setup);
 725
 726 static int __init ioapic_pirq_setup(char *str)
 727 {
 728         int i, max;
 729         int ints[MAX_PIRQS+1];
 730
 731         get_options(str, ARRAY_SIZE(ints), ints);
 732
 733         for (i = 0; i < MAX_PIRQS; i++)
 734                 pirq_entries[i] = -1;
 735
 736         pirqs_enabled = 1;
 737         apic_printk(APIC_VERBOSE, KERN_INFO
 738                         "PIRQ redirection, working around broken MP-BIOS.\n");
 739         max = MAX_PIRQS;
 740         if (ints[0] < MAX_PIRQS)
 741                 max = ints[0];
 742
 743         for (i = 0; i < max; i++) {
 744                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 745                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 746                 /*
 747                  * PIRQs are mapped upside down, usually.
 748                  */
 749                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 750         }
 751         return 1;
 752 }
 753
 754 __setup("pirq=", ioapic_pirq_setup);
 755
 756 /*
 757  * Find the IRQ entry number of a certain pin.
 758  */
 759 static int find_irq_entry(int apic, int pin, int type)
 760 {
 761         int i;
 762
 763         for (i = 0; i < mp_irq_entries; i++)
 764                 if (mp_irqs[i].mpc_irqtype == type &&
 765                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 766                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 767                     mp_irqs[i].mpc_dstirq == pin)
 768                         return i;
 769
 770         return -1;
 771 }
 772
 773 /*
 774  * Find the pin to which IRQ[irq] (ISA) is connected
 775  */
 776 static int __init find_isa_irq_pin(int irq, int type)
 777 {
 778         int i;
 779
 780         for (i = 0; i < mp_irq_entries; i++) {
 781                 int lbus = mp_irqs[i].mpc_srcbus;
 782
 783                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 784                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 785                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 786                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 787                     ) &&
 788                     (mp_irqs[i].mpc_irqtype == type) &&
 789                     (mp_irqs[i].mpc_srcbusirq == irq))
 790
 791                         return mp_irqs[i].mpc_dstirq;
 792         }
 793         return -1;
 794 }
 795
 796 static int __init find_isa_irq_apic(int irq, int type)
 797 {
 798         int i;
 799
 800         for (i = 0; i < mp_irq_entries; i++) {
 801                 int lbus = mp_irqs[i].mpc_srcbus;
 802
 803                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 804                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 805                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 806                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 807                     ) &&
 808                     (mp_irqs[i].mpc_irqtype == type) &&
 809                     (mp_irqs[i].mpc_srcbusirq == irq))
 810                         break;
 811         }
 812         if (i < mp_irq_entries) {
 813                 int apic;
 814                 for(apic = 0; apic < nr_ioapics; apic++) {
 815                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 816                                 return apic;
 817                 }
 818         }
 819
 820         return -1;
 821 }
 822
 823 /*
 824  * Find a specific PCI IRQ entry.
 825  * Not an __init, possibly needed by modules
 826  */
 827 static int pin_2_irq(int idx, int apic, int pin);
 828
 829 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 830 {
 831         int apic, i, best_guess = -1;
 832
 833         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 834                 "slot:%d, pin:%d.\n", bus, slot, pin);
 835         if (mp_bus_id_to_pci_bus[bus] == -1) {
 836                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 837                 return -1;
 838         }
 839         for (i = 0; i < mp_irq_entries; i++) {
 840                 int lbus = mp_irqs[i].mpc_srcbus;
 841
 842                 for (apic = 0; apic < nr_ioapics; apic++)
 843                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 844                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 845                                 break;
 846
 847                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 848                     !mp_irqs[i].mpc_irqtype &&
 849                     (bus == lbus) &&
 850                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 851                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 852
 853                         if (!(apic || IO_APIC_IRQ(irq)))
 854                                 continue;
 855
 856                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 857                                 return irq;
 858                         /*
 859                          * Use the first all-but-pin matching entry as a
 860                          * best-guess fuzzy result for broken mptables.
 861                          */
 862                         if (best_guess < 0)
 863                                 best_guess = irq;
 864                 }
 865         }
 866         return best_guess;
 867 }
 868 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 869
 870 /*
 871  * This function currently is only a helper for the i386 smp boot process where
 872  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 873  * so mask in all cases should simply be TARGET_CPUS
 874  */
 875 #ifdef CONFIG_SMP
 876 void __init setup_ioapic_dest(void)
 877 {
 878         int pin, ioapic, irq, irq_entry;
 879
 880         if (skip_ioapic_setup == 1)
 881                 return;
 882
 883         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 884                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 885                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 886                         if (irq_entry == -1)
 887                                 continue;
 888                         irq = pin_2_irq(irq_entry, ioapic, pin);
 889                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 890                 }
 891
 892         }
 893 }
 894 #endif
 895
 896 /*
 897  * EISA Edge/Level control register, ELCR
 898  */
 899 static int EISA_ELCR(unsigned int irq)
 900 {
 901         if (irq < 16) {
 902                 unsigned int port = 0x4d0 + (irq >> 3);
 903                 return (inb(port) >> (irq & 7)) & 1;
 904         }
 905         apic_printk(APIC_VERBOSE, KERN_INFO
 906                         "Broken MPtable reports ISA irq %d\n", irq);
 907         return 0;
 908 }
 909
 910 /* EISA interrupts are always polarity zero and can be edge or level
 911  * trigger depending on the ELCR value.  If an interrupt is listed as
 912  * EISA conforming in the MP table, that means its trigger type must
 913  * be read in from the ELCR */
 914
 915 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 916 #define default_EISA_polarity(idx)      (0)
 917
 918 /* ISA interrupts are always polarity zero edge triggered,
 919  * when listed as conforming in the MP table. */
 920
 921 #define default_ISA_trigger(idx)        (0)
 922 #define default_ISA_polarity(idx)       (0)
 923
 924 /* PCI interrupts are always polarity one level triggered,
 925  * when listed as conforming in the MP table. */
 926
 927 #define default_PCI_trigger(idx)        (1)
 928 #define default_PCI_polarity(idx)       (1)
 929
 930 /* MCA interrupts are always polarity zero level triggered,
 931  * when listed as conforming in the MP table. */
 932
 933 #define default_MCA_trigger(idx)        (1)
 934 #define default_MCA_polarity(idx)       (0)
 935
 936 /* NEC98 interrupts are always polarity zero edge triggered,
 937  * when listed as conforming in the MP table. */
 938
 939 #define default_NEC98_trigger(idx)     (0)
 940 #define default_NEC98_polarity(idx)    (0)
 941
 942 static int __init MPBIOS_polarity(int idx)
 943 {
 944         int bus = mp_irqs[idx].mpc_srcbus;
 945         int polarity;
 946
 947         /*
 948          * Determine IRQ line polarity (high active or low active):
 949          */
 950         switch (mp_irqs[idx].mpc_irqflag & 3)
 951         {
 952                 case 0: /* conforms, ie. bus-type dependent polarity */
 953                 {
 954                         switch (mp_bus_id_to_type[bus])
 955                         {
 956                                 case MP_BUS_ISA: /* ISA pin */
 957                                 {
 958                                         polarity = default_ISA_polarity(idx);
 959                                         break;
 960                                 }
 961                                 case MP_BUS_EISA: /* EISA pin */
 962                                 {
 963                                         polarity = default_EISA_polarity(idx);
 964                                         break;
 965                                 }
 966                                 case MP_BUS_PCI: /* PCI pin */
 967                                 {
 968                                         polarity = default_PCI_polarity(idx);
 969                                         break;
 970                                 }
 971                                 case MP_BUS_MCA: /* MCA pin */
 972                                 {
 973                                         polarity = default_MCA_polarity(idx);
 974                                         break;
 975                                 }
 976                                 case MP_BUS_NEC98: /* NEC 98 pin */
 977                                 {
 978                                         polarity = default_NEC98_polarity(idx);
 979                                         break;
 980                                 }
 981                                 default:
 982                                 {
 983                                         printk(KERN_WARNING "broken BIOS!!\n");
 984                                         polarity = 1;
 985                                         break;
 986                                 }
 987                         }
 988                         break;
 989                 }
 990                 case 1: /* high active */
 991                 {
 992                         polarity = 0;
 993                         break;
 994                 }
 995                 case 2: /* reserved */
 996                 {
 997                         printk(KERN_WARNING "broken BIOS!!\n");
 998                         polarity = 1;
 999                         break;
1000                 }
1001                 case 3: /* low active */
1002                 {
1003                         polarity = 1;
1004                         break;
1005                 }
1006                 default: /* invalid */
1007                 {
1008                         printk(KERN_WARNING "broken BIOS!!\n");
1009                         polarity = 1;
1010                         break;
1011                 }
1012         }
1013         return polarity;
1014 }
1015
1016 static int MPBIOS_trigger(int idx)
1017 {
1018         int bus = mp_irqs[idx].mpc_srcbus;
1019         int trigger;
1020
1021         /*
1022          * Determine IRQ trigger mode (edge or level sensitive):
1023          */
1024         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1025         {
1026                 case 0: /* conforms, ie. bus-type dependent */
1027                 {
1028                         switch (mp_bus_id_to_type[bus])
1029                         {
1030                                 case MP_BUS_ISA: /* ISA pin */
1031                                 {
1032                                         trigger = default_ISA_trigger(idx);
1033                                         break;
1034                                 }
1035                                 case MP_BUS_EISA: /* EISA pin */
1036                                 {
1037                                         trigger = default_EISA_trigger(idx);
1038                                         break;
1039                                 }
1040                                 case MP_BUS_PCI: /* PCI pin */
1041                                 {
1042                                         trigger = default_PCI_trigger(idx);
1043                                         break;
1044                                 }
1045                                 case MP_BUS_MCA: /* MCA pin */
1046                                 {
1047                                         trigger = default_MCA_trigger(idx);
1048                                         break;
1049                                 }
1050                                 case MP_BUS_NEC98: /* NEC 98 pin */
1051                                 {
1052                                         trigger = default_NEC98_trigger(idx);
1053                                         break;
1054                                 }
1055                                 default:
1056                                 {
1057                                         printk(KERN_WARNING "broken BIOS!!\n");
1058                                         trigger = 1;
1059                                         break;
1060                                 }
1061                         }
1062                         break;
1063                 }
1064                 case 1: /* edge */
1065                 {
1066                         trigger = 0;
1067                         break;
1068                 }
1069                 case 2: /* reserved */
1070                 {
1071                         printk(KERN_WARNING "broken BIOS!!\n");
1072                         trigger = 1;
1073                         break;
1074                 }
1075                 case 3: /* level */
1076                 {
1077                         trigger = 1;
1078                         break;
1079                 }
1080                 default: /* invalid */
1081                 {
1082                         printk(KERN_WARNING "broken BIOS!!\n");
1083                         trigger = 0;
1084                         break;
1085                 }
1086         }
1087         return trigger;
1088 }
1089
1090 static inline int irq_polarity(int idx)
1091 {
1092         return MPBIOS_polarity(idx);
1093 }
1094
1095 static inline int irq_trigger(int idx)
1096 {
1097         return MPBIOS_trigger(idx);
1098 }
1099
1100 static int pin_2_irq(int idx, int apic, int pin)
1101 {
1102         int irq, i;
1103         int bus = mp_irqs[idx].mpc_srcbus;
1104
1105         /*
1106          * Debugging check, we are in big trouble if this message pops up!
1107          */
1108         if (mp_irqs[idx].mpc_dstirq != pin)
1109                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1110
1111         switch (mp_bus_id_to_type[bus])
1112         {
1113                 case MP_BUS_ISA: /* ISA pin */
1114                 case MP_BUS_EISA:
1115                 case MP_BUS_MCA:
1116                 case MP_BUS_NEC98:
1117                 {
1118                         irq = mp_irqs[idx].mpc_srcbusirq;
1119                         break;
1120                 }
1121                 case MP_BUS_PCI: /* PCI pin */
1122                 {
1123                         /*
1124                          * PCI IRQs are mapped in order
1125                          */
1126                         i = irq = 0;
1127                         while (i < apic)
1128                                 irq += nr_ioapic_registers[i++];
1129                         irq += pin;
1130
1131                         /*
1132                          * For MPS mode, so far only needed by ES7000 platform
1133                          */
1134                         if (ioapic_renumber_irq)
1135                                 irq = ioapic_renumber_irq(apic, irq);
1136
1137                         break;
1138                 }
1139                 default:
1140                 {
1141                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1142                         irq = 0;
1143                         break;
1144                 }
1145         }
1146
1147         /*
1148          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1149          */
1150         if ((pin >= 16) && (pin <= 23)) {
1151                 if (pirq_entries[pin-16] != -1) {
1152                         if (!pirq_entries[pin-16]) {
1153                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1154                                                 "disabling PIRQ%d\n", pin-16);
1155                         } else {
1156                                 irq = pirq_entries[pin-16];
1157                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1158                                                 "using PIRQ%d -> IRQ %d\n",
1159                                                 pin-16, irq);
1160                         }
1161                 }
1162         }
1163         return irq;
1164 }
1165
1166 static inline int IO_APIC_irq_trigger(int irq)
1167 {
1168         int apic, idx, pin;
1169
1170         for (apic = 0; apic < nr_ioapics; apic++) {
1171                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1172                         idx = find_irq_entry(apic,pin,mp_INT);
1173                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1174                                 return irq_trigger(idx);
1175                 }
1176         }
1177         /*
1178          * nonexistent IRQs are edge default
1179          */
1180         return 0;
1181 }
1182
1183 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1184 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1185
1186 int assign_irq_vector(int irq)
1187 {
1188         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1189         unsigned long flags;
1190         int vector;
1191
1192         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
1193
1194         spin_lock_irqsave(&vector_lock, flags);
1195
1196         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
1197                 spin_unlock_irqrestore(&vector_lock, flags);
1198                 return IO_APIC_VECTOR(irq);
1199         }
1200 next:
1201         current_vector += 8;
1202         if (current_vector == SYSCALL_VECTOR)
1203                 goto next;
1204
1205         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1206                 offset++;
1207                 if (!(offset%8)) {
1208                         spin_unlock_irqrestore(&vector_lock, flags);
1209                         return -ENOSPC;
1210                 }
1211                 current_vector = FIRST_DEVICE_VECTOR + offset;
1212         }
1213
1214         vector = current_vector;
1215         vector_irq[vector] = irq;
1216         if (irq != AUTO_ASSIGN)
1217                 IO_APIC_VECTOR(irq) = vector;
1218
1219         spin_unlock_irqrestore(&vector_lock, flags);
1220
1221         return vector;
1222 }
1223
1224 static struct irq_chip ioapic_chip;
1225
1226 #define IOAPIC_AUTO     -1
1227 #define IOAPIC_EDGE     0
1228 #define IOAPIC_LEVEL    1
1229
1230 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1231 {
1232         unsigned idx;
1233
1234         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
1235
1236         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1237                         trigger == IOAPIC_LEVEL)
1238                 set_irq_chip_and_handler(idx, &ioapic_chip,
1239                                          handle_fasteoi_irq);
1240         else
1241                 set_irq_chip_and_handler(idx, &ioapic_chip,
1242                                          handle_edge_irq);
1243         set_intr_gate(vector, interrupt[idx]);
1244 }
1245
1246 static void __init setup_IO_APIC_irqs(void)
1247 {
1248         struct IO_APIC_route_entry entry;
1249         int apic, pin, idx, irq, first_notcon = 1, vector;
1250         unsigned long flags;
1251
1252         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1253
1254         for (apic = 0; apic < nr_ioapics; apic++) {
1255         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1256
1257                 /*
1258                  * add it to the IO-APIC irq-routing table:
1259                  */
1260                 memset(&entry,0,sizeof(entry));
1261
1262                 entry.delivery_mode = INT_DELIVERY_MODE;
1263                 entry.dest_mode = INT_DEST_MODE;
1264                 entry.mask = 0;                         /* enable IRQ */
1265                 entry.dest.logical.logical_dest =
1266                                         cpu_mask_to_apicid(TARGET_CPUS);
1267
1268                 idx = find_irq_entry(apic,pin,mp_INT);
1269                 if (idx == -1) {
1270                         if (first_notcon) {
1271                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1272                                                 " IO-APIC (apicid-pin) %d-%d",
1273                                                 mp_ioapics[apic].mpc_apicid,
1274                                                 pin);
1275                                 first_notcon = 0;
1276                         } else
1277                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1278                                         mp_ioapics[apic].mpc_apicid, pin);
1279                         continue;
1280                 }
1281
1282                 entry.trigger = irq_trigger(idx);
1283                 entry.polarity = irq_polarity(idx);
1284
1285                 if (irq_trigger(idx)) {
1286                         entry.trigger = 1;
1287                         entry.mask = 1;
1288                 }
1289
1290                 irq = pin_2_irq(idx, apic, pin);
1291                 /*
1292                  * skip adding the timer int on secondary nodes, which causes
1293                  * a small but painful rift in the time-space continuum
1294                  */
1295                 if (multi_timer_check(apic, irq))
1296                         continue;
1297                 else
1298                         add_pin_to_irq(irq, apic, pin);
1299
1300                 if (!apic && !IO_APIC_IRQ(irq))
1301                         continue;
1302
1303                 if (IO_APIC_IRQ(irq)) {
1304                         vector = assign_irq_vector(irq);
1305                         entry.vector = vector;
1306                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1307
1308                         if (!apic && (irq < 16))
1309                                 disable_8259A_irq(irq);
1310                 }
1311                 ioapic_write_entry(apic, pin, entry);
1312                 spin_lock_irqsave(&ioapic_lock, flags);
1313                 set_native_irq_info(irq, TARGET_CPUS);
1314                 spin_unlock_irqrestore(&ioapic_lock, flags);
1315         }
1316         }
1317
1318         if (!first_notcon)
1319                 apic_printk(APIC_VERBOSE, " not connected.\n");
1320 }
1321
1322 /*
1323  * Set up the 8259A-master output pin:
1324  */
1325 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1326 {
1327         struct IO_APIC_route_entry entry;
1328
1329         memset(&entry,0,sizeof(entry));
1330
1331         disable_8259A_irq(0);
1332
1333         /* mask LVT0 */
1334         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1335
1336         /*
1337          * We use logical delivery to get the timer IRQ
1338          * to the first CPU.
1339          */
1340         entry.dest_mode = INT_DEST_MODE;
1341         entry.mask = 0;                                 /* unmask IRQ now */
1342         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1343         entry.delivery_mode = INT_DELIVERY_MODE;
1344         entry.polarity = 0;
1345         entry.trigger = 0;
1346         entry.vector = vector;
1347
1348         /*
1349          * The timer IRQ doesn't have to know that behind the
1350          * scene we have a 8259A-master in AEOI mode ...
1351          */
1352         irq_desc[0].chip = &ioapic_chip;
1353         set_irq_handler(0, handle_edge_irq);
1354
1355         /*
1356          * Add it to the IO-APIC irq-routing table:
1357          */
1358         ioapic_write_entry(apic, pin, entry);
1359
1360         enable_8259A_irq(0);
1361 }
1362
1363 static inline void UNEXPECTED_IO_APIC(void)
1364 {
1365 }
1366
1367 void __init print_IO_APIC(void)
1368 {
1369         int apic, i;
1370         union IO_APIC_reg_00 reg_00;
1371         union IO_APIC_reg_01 reg_01;
1372         union IO_APIC_reg_02 reg_02;
1373         union IO_APIC_reg_03 reg_03;
1374         unsigned long flags;
1375
1376         if (apic_verbosity == APIC_QUIET)
1377                 return;
1378
1379         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1380         for (i = 0; i < nr_ioapics; i++)
1381                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1382                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1383
1384         /*
1385          * We are a bit conservative about what we expect.  We have to
1386          * know about every hardware change ASAP.
1387          */
1388         printk(KERN_INFO "testing the IO APIC.......................\n");
1389
1390         for (apic = 0; apic < nr_ioapics; apic++) {
1391
1392         spin_lock_irqsave(&ioapic_lock, flags);
1393         reg_00.raw = io_apic_read(apic, 0);
1394         reg_01.raw = io_apic_read(apic, 1);
1395         if (reg_01.bits.version >= 0x10)
1396                 reg_02.raw = io_apic_read(apic, 2);
1397         if (reg_01.bits.version >= 0x20)
1398                 reg_03.raw = io_apic_read(apic, 3);
1399         spin_unlock_irqrestore(&ioapic_lock, flags);
1400
1401         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1402         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1403         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1404         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1405         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1406         if (reg_00.bits.ID >= get_physical_broadcast())
1407                 UNEXPECTED_IO_APIC();
1408         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1409                 UNEXPECTED_IO_APIC();
1410
1411         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1412         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1413         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1414                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1415                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1416                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1417                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1418                 (reg_01.bits.entries != 0x2E) &&
1419                 (reg_01.bits.entries != 0x3F)
1420         )
1421                 UNEXPECTED_IO_APIC();
1422
1423         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1424         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1425         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1426                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1427                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1428                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1429                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1430         )
1431                 UNEXPECTED_IO_APIC();
1432         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1433                 UNEXPECTED_IO_APIC();
1434
1435         /*
1436          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1437          * but the value of reg_02 is read as the previous read register
1438          * value, so ignore it if reg_02 == reg_01.
1439          */
1440         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1441                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1442                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1443                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1444                         UNEXPECTED_IO_APIC();
1445         }
1446
1447         /*
1448          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1449          * or reg_03, but the value of reg_0[23] is read as the previous read
1450          * register value, so ignore it if reg_03 == reg_0[12].
1451          */
1452         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1453             reg_03.raw != reg_01.raw) {
1454                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1455                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1456                 if (reg_03.bits.__reserved_1)
1457                         UNEXPECTED_IO_APIC();
1458         }
1459
1460         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1461
1462         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1463                           " Stat Dest Deli Vect:   \n");
1464
1465         for (i = 0; i <= reg_01.bits.entries; i++) {
1466                 struct IO_APIC_route_entry entry;
1467
1468                 entry = ioapic_read_entry(apic, i);
1469
1470                 printk(KERN_DEBUG " %02x %03X %02X  ",
1471                         i,
1472                         entry.dest.logical.logical_dest,
1473                         entry.dest.physical.physical_dest
1474                 );
1475
1476                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1477                         entry.mask,
1478                         entry.trigger,
1479                         entry.irr,
1480                         entry.polarity,
1481                         entry.delivery_status,
1482                         entry.dest_mode,
1483                         entry.delivery_mode,
1484                         entry.vector
1485                 );
1486         }
1487         }
1488         if (use_pci_vector())
1489                 printk(KERN_INFO "Using vector-based indexing\n");
1490         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1491         for (i = 0; i < NR_IRQS; i++) {
1492                 struct irq_pin_list *entry = irq_2_pin + i;
1493                 if (entry->pin < 0)
1494                         continue;
1495                 if (use_pci_vector() && !platform_legacy_irq(i))
1496                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1497                 else
1498                         printk(KERN_DEBUG "IRQ%d ", i);
1499                 for (;;) {
1500                         printk("-> %d:%d", entry->apic, entry->pin);
1501                         if (!entry->next)
1502                                 break;
1503                         entry = irq_2_pin + entry->next;
1504                 }
1505                 printk("\n");
1506         }
1507
1508         printk(KERN_INFO ".................................... done.\n");
1509
1510         return;
1511 }
1512
1513 #if 0
1514
1515 static void print_APIC_bitfield (int base)
1516 {
1517         unsigned int v;
1518         int i, j;
1519
1520         if (apic_verbosity == APIC_QUIET)
1521                 return;
1522
1523         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1524         for (i = 0; i < 8; i++) {
1525                 v = apic_read(base + i*0x10);
1526                 for (j = 0; j < 32; j++) {
1527                         if (v & (1<<j))
1528                                 printk("1");
1529                         else
1530                                 printk("0");
1531                 }
1532                 printk("\n");
1533         }
1534 }
1535
1536 void /*__init*/ print_local_APIC(void * dummy)
1537 {
1538         unsigned int v, ver, maxlvt;
1539
1540         if (apic_verbosity == APIC_QUIET)
1541                 return;
1542
1543         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1544                 smp_processor_id(), hard_smp_processor_id());
1545         v = apic_read(APIC_ID);
1546         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1547         v = apic_read(APIC_LVR);
1548         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1549         ver = GET_APIC_VERSION(v);
1550         maxlvt = get_maxlvt();
1551
1552         v = apic_read(APIC_TASKPRI);
1553         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1554
1555         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1556                 v = apic_read(APIC_ARBPRI);
1557                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1558                         v & APIC_ARBPRI_MASK);
1559                 v = apic_read(APIC_PROCPRI);
1560                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1561         }
1562
1563         v = apic_read(APIC_EOI);
1564         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1565         v = apic_read(APIC_RRR);
1566         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1567         v = apic_read(APIC_LDR);
1568         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1569         v = apic_read(APIC_DFR);
1570         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1571         v = apic_read(APIC_SPIV);
1572         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1573
1574         printk(KERN_DEBUG "... APIC ISR field:\n");
1575         print_APIC_bitfield(APIC_ISR);
1576         printk(KERN_DEBUG "... APIC TMR field:\n");
1577         print_APIC_bitfield(APIC_TMR);
1578         printk(KERN_DEBUG "... APIC IRR field:\n");
1579         print_APIC_bitfield(APIC_IRR);
1580
1581         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1582                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1583                         apic_write(APIC_ESR, 0);
1584                 v = apic_read(APIC_ESR);
1585                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1586         }
1587
1588         v = apic_read(APIC_ICR);
1589         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1590         v = apic_read(APIC_ICR2);
1591         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1592
1593         v = apic_read(APIC_LVTT);
1594         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1595
1596         if (maxlvt > 3) {                       /* PC is LVT#4. */
1597                 v = apic_read(APIC_LVTPC);
1598                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1599         }
1600         v = apic_read(APIC_LVT0);
1601         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1602         v = apic_read(APIC_LVT1);
1603         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1604
1605         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1606                 v = apic_read(APIC_LVTERR);
1607                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1608         }
1609
1610         v = apic_read(APIC_TMICT);
1611         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1612         v = apic_read(APIC_TMCCT);
1613         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1614         v = apic_read(APIC_TDCR);
1615         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1616         printk("\n");
1617 }
1618
1619 void print_all_local_APICs (void)
1620 {
1621         on_each_cpu(print_local_APIC, NULL, 1, 1);
1622 }
1623
1624 void /*__init*/ print_PIC(void)
1625 {
1626         unsigned int v;
1627         unsigned long flags;
1628
1629         if (apic_verbosity == APIC_QUIET)
1630                 return;
1631
1632         printk(KERN_DEBUG "\nprinting PIC contents\n");
1633
1634         spin_lock_irqsave(&i8259A_lock, flags);
1635
1636         v = inb(0xa1) << 8 | inb(0x21);
1637         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1638
1639         v = inb(0xa0) << 8 | inb(0x20);
1640         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1641
1642         outb(0x0b,0xa0);
1643         outb(0x0b,0x20);
1644         v = inb(0xa0) << 8 | inb(0x20);
1645         outb(0x0a,0xa0);
1646         outb(0x0a,0x20);
1647
1648         spin_unlock_irqrestore(&i8259A_lock, flags);
1649
1650         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1651
1652         v = inb(0x4d1) << 8 | inb(0x4d0);
1653         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1654 }
1655
1656 #endif  /*  0  */
1657
1658 static void __init enable_IO_APIC(void)
1659 {
1660         union IO_APIC_reg_01 reg_01;
1661         int i8259_apic, i8259_pin;
1662         int i, apic;
1663         unsigned long flags;
1664
1665         for (i = 0; i < PIN_MAP_SIZE; i++) {
1666                 irq_2_pin[i].pin = -1;
1667                 irq_2_pin[i].next = 0;
1668         }
1669         if (!pirqs_enabled)
1670                 for (i = 0; i < MAX_PIRQS; i++)
1671                         pirq_entries[i] = -1;
1672
1673         /*
1674          * The number of IO-APIC IRQ registers (== #pins):
1675          */
1676         for (apic = 0; apic < nr_ioapics; apic++) {
1677                 spin_lock_irqsave(&ioapic_lock, flags);
1678                 reg_01.raw = io_apic_read(apic, 1);
1679                 spin_unlock_irqrestore(&ioapic_lock, flags);
1680                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1681         }
1682         for(apic = 0; apic < nr_ioapics; apic++) {
1683                 int pin;
1684                 /* See if any of the pins is in ExtINT mode */
1685                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1686                         struct IO_APIC_route_entry entry;
1687                         entry = ioapic_read_entry(apic, pin);
1688
1689
1690                         /* If the interrupt line is enabled and in ExtInt mode
1691                          * I have found the pin where the i8259 is connected.
1692                          */
1693                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1694                                 ioapic_i8259.apic = apic;
1695                                 ioapic_i8259.pin  = pin;
1696                                 goto found_i8259;
1697                         }
1698                 }
1699         }
1700  found_i8259:
1701         /* Look to see what if the MP table has reported the ExtINT */
1702         /* If we could not find the appropriate pin by looking at the ioapic
1703          * the i8259 probably is not connected the ioapic but give the
1704          * mptable a chance anyway.
1705          */
1706         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1707         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1708         /* Trust the MP table if nothing is setup in the hardware */
1709         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1710                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1711                 ioapic_i8259.pin  = i8259_pin;
1712                 ioapic_i8259.apic = i8259_apic;
1713         }
1714         /* Complain if the MP table and the hardware disagree */
1715         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1716                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1717         {
1718                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1719         }
1720
1721         /*
1722          * Do not trust the IO-APIC being empty at bootup
1723          */
1724         clear_IO_APIC();
1725 }
1726
1727 /*
1728  * Not an __init, needed by the reboot code
1729  */
1730 void disable_IO_APIC(void)
1731 {
1732         /*
1733          * Clear the IO-APIC before rebooting:
1734          */
1735         clear_IO_APIC();
1736
1737         /*
1738          * If the i8259 is routed through an IOAPIC
1739          * Put that IOAPIC in virtual wire mode
1740          * so legacy interrupts can be delivered.
1741          */
1742         if (ioapic_i8259.pin != -1) {
1743                 struct IO_APIC_route_entry entry;
1744
1745                 memset(&entry, 0, sizeof(entry));
1746                 entry.mask            = 0; /* Enabled */
1747                 entry.trigger         = 0; /* Edge */
1748                 entry.irr             = 0;
1749                 entry.polarity        = 0; /* High */
1750                 entry.delivery_status = 0;
1751                 entry.dest_mode       = 0; /* Physical */
1752                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1753                 entry.vector          = 0;
1754                 entry.dest.physical.physical_dest =
1755                                         GET_APIC_ID(apic_read(APIC_ID));
1756
1757                 /*
1758                  * Add it to the IO-APIC irq-routing table:
1759                  */
1760                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1761         }
1762         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1763 }
1764
1765 /*
1766  * function to set the IO-APIC physical IDs based on the
1767  * values stored in the MPC table.
1768  *
1769  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1770  */
1771
1772 #ifndef CONFIG_X86_NUMAQ
1773 static void __init setup_ioapic_ids_from_mpc(void)
1774 {
1775         union IO_APIC_reg_00 reg_00;
1776         physid_mask_t phys_id_present_map;
1777         int apic;
1778         int i;
1779         unsigned char old_id;
1780         unsigned long flags;
1781
1782         /*
1783          * Don't check I/O APIC IDs for xAPIC systems.  They have
1784          * no meaning without the serial APIC bus.
1785          */
1786         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1787                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1788                 return;
1789         /*
1790          * This is broken; anything with a real cpu count has to
1791          * circumvent this idiocy regardless.
1792          */
1793         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1794
1795         /*
1796          * Set the IOAPIC ID to the value stored in the MPC table.
1797          */
1798         for (apic = 0; apic < nr_ioapics; apic++) {
1799
1800                 /* Read the register 0 value */
1801                 spin_lock_irqsave(&ioapic_lock, flags);
1802                 reg_00.raw = io_apic_read(apic, 0);
1803                 spin_unlock_irqrestore(&ioapic_lock, flags);
1804
1805                 old_id = mp_ioapics[apic].mpc_apicid;
1806
1807                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1808                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1809                                 apic, mp_ioapics[apic].mpc_apicid);
1810                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1811                                 reg_00.bits.ID);
1812                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1813                 }
1814
1815                 /*
1816                  * Sanity check, is the ID really free? Every APIC in a
1817                  * system must have a unique ID or we get lots of nice
1818                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1819                  */
1820                 if (check_apicid_used(phys_id_present_map,
1821                                         mp_ioapics[apic].mpc_apicid)) {
1822                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1823                                 apic, mp_ioapics[apic].mpc_apicid);
1824                         for (i = 0; i < get_physical_broadcast(); i++)
1825                                 if (!physid_isset(i, phys_id_present_map))
1826                                         break;
1827                         if (i >= get_physical_broadcast())
1828                                 panic("Max APIC ID exceeded!\n");
1829                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1830                                 i);
1831                         physid_set(i, phys_id_present_map);
1832                         mp_ioapics[apic].mpc_apicid = i;
1833                 } else {
1834                         physid_mask_t tmp;
1835                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1836                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1837                                         "phys_id_present_map\n",
1838                                         mp_ioapics[apic].mpc_apicid);
1839                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1840                 }
1841
1842
1843                 /*
1844                  * We need to adjust the IRQ routing table
1845                  * if the ID changed.
1846                  */
1847                 if (old_id != mp_ioapics[apic].mpc_apicid)
1848                         for (i = 0; i < mp_irq_entries; i++)
1849                                 if (mp_irqs[i].mpc_dstapic == old_id)
1850                                         mp_irqs[i].mpc_dstapic
1851                                                 = mp_ioapics[apic].mpc_apicid;
1852
1853                 /*
1854                  * Read the right value from the MPC table and
1855                  * write it into the ID register.
1856                  */
1857                 apic_printk(APIC_VERBOSE, KERN_INFO
1858                         "...changing IO-APIC physical APIC ID to %d ...",
1859                         mp_ioapics[apic].mpc_apicid);
1860
1861                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1862                 spin_lock_irqsave(&ioapic_lock, flags);
1863                 io_apic_write(apic, 0, reg_00.raw);
1864                 spin_unlock_irqrestore(&ioapic_lock, flags);
1865
1866                 /*
1867                  * Sanity check
1868                  */
1869                 spin_lock_irqsave(&ioapic_lock, flags);
1870                 reg_00.raw = io_apic_read(apic, 0);
1871                 spin_unlock_irqrestore(&ioapic_lock, flags);
1872                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1873                         printk("could not set ID!\n");
1874                 else
1875                         apic_printk(APIC_VERBOSE, " ok.\n");
1876         }
1877 }
1878 #else
1879 static void __init setup_ioapic_ids_from_mpc(void) { }
1880 #endif
1881
1882 /*
1883  * There is a nasty bug in some older SMP boards, their mptable lies
1884  * about the timer IRQ. We do the following to work around the situation:
1885  *
1886  *      - timer IRQ defaults to IO-APIC IRQ
1887  *      - if this function detects that timer IRQs are defunct, then we fall
1888  *        back to ISA timer IRQs
1889  */
1890 static int __init timer_irq_works(void)
1891 {
1892         unsigned long t1 = jiffies;
1893
1894         local_irq_enable();
1895         /* Let ten ticks pass... */
1896         mdelay((10 * 1000) / HZ);
1897
1898         /*
1899          * Expect a few ticks at least, to be sure some possible
1900          * glue logic does not lock up after one or two first
1901          * ticks in a non-ExtINT mode.  Also the local APIC
1902          * might have cached one ExtINT interrupt.  Finally, at
1903          * least one tick may be lost due to delays.
1904          */
1905         if (jiffies - t1 > 4)
1906                 return 1;
1907
1908         return 0;
1909 }
1910
1911 /*
1912  * In the SMP+IOAPIC case it might happen that there are an unspecified
1913  * number of pending IRQ events unhandled. These cases are very rare,
1914  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1915  * better to do it this way as thus we do not have to be aware of
1916  * 'pending' interrupts in the IRQ path, except at this point.
1917  */
1918 /*
1919  * Edge triggered needs to resend any interrupt
1920  * that was delayed but this is now handled in the device
1921  * independent code.
1922  */
1923
1924 /*
1925  * Startup quirk:
1926  *
1927  * Starting up a edge-triggered IO-APIC interrupt is
1928  * nasty - we need to make sure that we get the edge.
1929  * If it is already asserted for some reason, we need
1930  * return 1 to indicate that is was pending.
1931  *
1932  * This is not complete - we should be able to fake
1933  * an edge even if it isn't on the 8259A...
1934  *
1935  * (We do this for level-triggered IRQs too - it cannot hurt.)
1936  */
1937 static unsigned int startup_ioapic_irq(unsigned int irq)
1938 {
1939         int was_pending = 0;
1940         unsigned long flags;
1941
1942         spin_lock_irqsave(&ioapic_lock, flags);
1943         if (irq < 16) {
1944                 disable_8259A_irq(irq);
1945                 if (i8259A_irq_pending(irq))
1946                         was_pending = 1;
1947         }
1948         __unmask_IO_APIC_irq(irq);
1949         spin_unlock_irqrestore(&ioapic_lock, flags);
1950
1951         return was_pending;
1952 }
1953
1954 static void ack_ioapic_irq(unsigned int irq)
1955 {
1956         move_irq(irq);
1957         ack_APIC_irq();
1958 }
1959
1960 static void ack_ioapic_quirk_irq(unsigned int irq)
1961 {
1962         unsigned long v;
1963         int i;
1964
1965         move_irq(irq);
1966 /*
1967  * It appears there is an erratum which affects at least version 0x11
1968  * of I/O APIC (that's the 82093AA and cores integrated into various
1969  * chipsets).  Under certain conditions a level-triggered interrupt is
1970  * erroneously delivered as edge-triggered one but the respective IRR
1971  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1972  * message but it will never arrive and further interrupts are blocked
1973  * from the source.  The exact reason is so far unknown, but the
1974  * phenomenon was observed when two consecutive interrupt requests
1975  * from a given source get delivered to the same CPU and the source is
1976  * temporarily disabled in between.
1977  *
1978  * A workaround is to simulate an EOI message manually.  We achieve it
1979  * by setting the trigger mode to edge and then to level when the edge
1980  * trigger mode gets detected in the TMR of a local APIC for a
1981  * level-triggered interrupt.  We mask the source for the time of the
1982  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1983  * The idea is from Manfred Spraul.  --macro
1984  */
1985         i = IO_APIC_VECTOR(irq);
1986
1987         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1988
1989         ack_APIC_irq();
1990
1991         if (!(v & (1 << (i & 0x1f)))) {
1992                 atomic_inc(&irq_mis_count);
1993                 spin_lock(&ioapic_lock);
1994                 __mask_and_edge_IO_APIC_irq(irq);
1995                 __unmask_and_level_IO_APIC_irq(irq);
1996                 spin_unlock(&ioapic_lock);
1997         }
1998 }
1999
2000 static unsigned int startup_ioapic_vector(unsigned int vector)
2001 {
2002         int irq = vector_to_irq(vector);
2003
2004         return startup_ioapic_irq(irq);
2005 }
2006
2007 static void ack_ioapic_vector(unsigned int vector)
2008 {
2009         int irq = vector_to_irq(vector);
2010
2011         move_native_irq(vector);
2012         ack_ioapic_irq(irq);
2013 }
2014
2015 static void ack_ioapic_quirk_vector(unsigned int vector)
2016 {
2017         int irq = vector_to_irq(vector);
2018
2019         move_native_irq(vector);
2020         ack_ioapic_quirk_irq(irq);
2021 }
2022
2023 static void mask_IO_APIC_vector (unsigned int vector)
2024 {
2025         int irq = vector_to_irq(vector);
2026
2027         mask_IO_APIC_irq(irq);
2028 }
2029
2030 static void unmask_IO_APIC_vector (unsigned int vector)
2031 {
2032         int irq = vector_to_irq(vector);
2033
2034         unmask_IO_APIC_irq(irq);
2035 }
2036
2037 /*
2038  * Oh just glorious.  If CONFIG_PCI_MSI we've done
2039  * #define set_ioapic_affinity set_ioapic_affinity_vector
2040  */
2041 #if defined (CONFIG_SMP) && defined(CONFIG_X86_IO_APIC) && \
2042                 defined(CONFIG_PCI_MSI)
2043 static void set_ioapic_affinity_vector (unsigned int vector,
2044                                         cpumask_t cpu_mask)
2045 {
2046         int irq = vector_to_irq(vector);
2047
2048         set_native_irq_info(vector, cpu_mask);
2049         set_ioapic_affinity_irq(irq, cpu_mask);
2050 }
2051 #endif
2052
2053 static int ioapic_retrigger_vector(unsigned int vector)
2054 {
2055         int irq = vector_to_irq(vector);
2056
2057         send_IPI_self(IO_APIC_VECTOR(irq));
2058
2059         return 1;
2060 }
2061
2062 static struct irq_chip ioapic_chip __read_mostly = {
2063         .name           = "IO-APIC",
2064         .startup        = startup_ioapic_vector,
2065         .mask           = mask_IO_APIC_vector,
2066         .unmask         = unmask_IO_APIC_vector,
2067         .ack            = ack_ioapic_vector,
2068         .eoi            = ack_ioapic_quirk_vector,
2069 #ifdef CONFIG_SMP
2070         .set_affinity   = set_ioapic_affinity,
2071 #endif
2072         .retrigger      = ioapic_retrigger_vector,
2073 };
2074
2075
2076 static inline void init_IO_APIC_traps(void)
2077 {
2078         int irq;
2079
2080         /*
2081          * NOTE! The local APIC isn't very good at handling
2082          * multiple interrupts at the same interrupt level.
2083          * As the interrupt level is determined by taking the
2084          * vector number and shifting that right by 4, we
2085          * want to spread these out a bit so that they don't
2086          * all fall in the same interrupt level.
2087          *
2088          * Also, we've got to be careful not to trash gate
2089          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2090          */
2091         for (irq = 0; irq < NR_IRQS ; irq++) {
2092                 int tmp = irq;
2093                 if (use_pci_vector()) {
2094                         if (!platform_legacy_irq(tmp))
2095                                 if ((tmp = vector_to_irq(tmp)) == -1)
2096                                         continue;
2097                 }
2098                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2099                         /*
2100                          * Hmm.. We don't have an entry for this,
2101                          * so default to an old-fashioned 8259
2102                          * interrupt if we can..
2103                          */
2104                         if (irq < 16)
2105                                 make_8259A_irq(irq);
2106                         else
2107                                 /* Strange. Oh, well.. */
2108                                 irq_desc[irq].chip = &no_irq_chip;
2109                 }
2110         }
2111 }
2112
2113 /*
2114  * The local APIC irq-chip implementation:
2115  */
2116
2117 static void ack_apic(unsigned int irq)
2118 {
2119         ack_APIC_irq();
2120 }
2121
2122 static void mask_lapic_irq (unsigned int irq)
2123 {
2124         unsigned long v;
2125
2126         v = apic_read(APIC_LVT0);
2127         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2128 }
2129
2130 static void unmask_lapic_irq (unsigned int irq)
2131 {
2132         unsigned long v;
2133
2134         v = apic_read(APIC_LVT0);
2135         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2136 }
2137
2138 static struct irq_chip lapic_chip __read_mostly = {
2139         .name           = "local-APIC-edge",
2140         .mask           = mask_lapic_irq,
2141         .unmask         = unmask_lapic_irq,
2142         .eoi            = ack_apic,
2143 };
2144
2145 static void setup_nmi (void)
2146 {
2147         /*
2148          * Dirty trick to enable the NMI watchdog ...
2149          * We put the 8259A master into AEOI mode and
2150          * unmask on all local APICs LVT0 as NMI.
2151          *
2152          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2153          * is from Maciej W. Rozycki - so we do not have to EOI from
2154          * the NMI handler or the timer interrupt.
2155          */
2156         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2157
2158         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2159
2160         apic_printk(APIC_VERBOSE, " done.\n");
2161 }
2162
2163 /*
2164  * This looks a bit hackish but it's about the only one way of sending
2165  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2166  * not support the ExtINT mode, unfortunately.  We need to send these
2167  * cycles as some i82489DX-based boards have glue logic that keeps the
2168  * 8259A interrupt line asserted until INTA.  --macro
2169  */
2170 static inline void unlock_ExtINT_logic(void)
2171 {
2172         int apic, pin, i;
2173         struct IO_APIC_route_entry entry0, entry1;
2174         unsigned char save_control, save_freq_select;
2175
2176         pin  = find_isa_irq_pin(8, mp_INT);
2177         apic = find_isa_irq_apic(8, mp_INT);
2178         if (pin == -1)
2179                 return;
2180
2181         entry0 = ioapic_read_entry(apic, pin);
2182         clear_IO_APIC_pin(apic, pin);
2183
2184         memset(&entry1, 0, sizeof(entry1));
2185
2186         entry1.dest_mode = 0;                   /* physical delivery */
2187         entry1.mask = 0;                        /* unmask IRQ now */
2188         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2189         entry1.delivery_mode = dest_ExtINT;
2190         entry1.polarity = entry0.polarity;
2191         entry1.trigger = 0;
2192         entry1.vector = 0;
2193
2194         ioapic_write_entry(apic, pin, entry1);
2195
2196         save_control = CMOS_READ(RTC_CONTROL);
2197         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2198         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2199                    RTC_FREQ_SELECT);
2200         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2201
2202         i = 100;
2203         while (i-- > 0) {
2204                 mdelay(10);
2205                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2206                         i -= 10;
2207         }
2208
2209         CMOS_WRITE(save_control, RTC_CONTROL);
2210         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2211         clear_IO_APIC_pin(apic, pin);
2212
2213         ioapic_write_entry(apic, pin, entry0);
2214 }
2215
2216 int timer_uses_ioapic_pin_0;
2217
2218 /*
2219  * This code may look a bit paranoid, but it's supposed to cooperate with
2220  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2221  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2222  * fanatically on his truly buggy board.
2223  */
2224 static inline void check_timer(void)
2225 {
2226         int apic1, pin1, apic2, pin2;
2227         int vector;
2228
2229         /*
2230          * get/set the timer IRQ vector:
2231          */
2232         disable_8259A_irq(0);
2233         vector = assign_irq_vector(0);
2234         set_intr_gate(vector, interrupt[0]);
2235
2236         /*
2237          * Subtle, code in do_timer_interrupt() expects an AEOI
2238          * mode for the 8259A whenever interrupts are routed
2239          * through I/O APICs.  Also IRQ0 has to be enabled in
2240          * the 8259A which implies the virtual wire has to be
2241          * disabled in the local APIC.
2242          */
2243         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2244         init_8259A(1);
2245         timer_ack = 1;
2246         if (timer_over_8254 > 0)
2247                 enable_8259A_irq(0);
2248
2249         pin1  = find_isa_irq_pin(0, mp_INT);
2250         apic1 = find_isa_irq_apic(0, mp_INT);
2251         pin2  = ioapic_i8259.pin;
2252         apic2 = ioapic_i8259.apic;
2253
2254         if (pin1 == 0)
2255                 timer_uses_ioapic_pin_0 = 1;
2256
2257         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2258                 vector, apic1, pin1, apic2, pin2);
2259
2260         if (pin1 != -1) {
2261                 /*
2262                  * Ok, does IRQ0 through the IOAPIC work?
2263                  */
2264                 unmask_IO_APIC_irq(0);
2265                 if (timer_irq_works()) {
2266                         if (nmi_watchdog == NMI_IO_APIC) {
2267                                 disable_8259A_irq(0);
2268                                 setup_nmi();
2269                                 enable_8259A_irq(0);
2270                         }
2271                         if (disable_timer_pin_1 > 0)
2272                                 clear_IO_APIC_pin(0, pin1);
2273                         return;
2274                 }
2275                 clear_IO_APIC_pin(apic1, pin1);
2276                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2277                                 "IO-APIC\n");
2278         }
2279
2280         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2281         if (pin2 != -1) {
2282                 printk("\n..... (found pin %d) ...", pin2);
2283                 /*
2284                  * legacy devices should be connected to IO APIC #0
2285                  */
2286                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2287                 if (timer_irq_works()) {
2288                         printk("works.\n");
2289                         if (pin1 != -1)
2290                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2291                         else
2292                                 add_pin_to_irq(0, apic2, pin2);
2293                         if (nmi_watchdog == NMI_IO_APIC) {
2294                                 setup_nmi();
2295                         }
2296                         return;
2297                 }
2298                 /*
2299                  * Cleanup, just in case ...
2300                  */
2301                 clear_IO_APIC_pin(apic2, pin2);
2302         }
2303         printk(" failed.\n");
2304
2305         if (nmi_watchdog == NMI_IO_APIC) {
2306                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2307                 nmi_watchdog = 0;
2308         }
2309
2310         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2311
2312         disable_8259A_irq(0);
2313         set_irq_chip_and_handler(0, &lapic_chip, handle_fasteoi_irq);
2314         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2315         enable_8259A_irq(0);
2316
2317         if (timer_irq_works()) {
2318                 printk(" works.\n");
2319                 return;
2320         }
2321         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2322         printk(" failed.\n");
2323
2324         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2325
2326         timer_ack = 0;
2327         init_8259A(0);
2328         make_8259A_irq(0);
2329         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2330
2331         unlock_ExtINT_logic();
2332
2333         if (timer_irq_works()) {
2334                 printk(" works.\n");
2335                 return;
2336         }
2337         printk(" failed :(.\n");
2338         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2339                 "report.  Then try booting with the 'noapic' option");
2340 }
2341
2342 /*
2343  *
2344  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2345  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2346  *   Linux doesn't really care, as it's not actually used
2347  *   for any interrupt handling anyway.
2348  */
2349 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2350
2351 void __init setup_IO_APIC(void)
2352 {
2353         enable_IO_APIC();
2354
2355         if (acpi_ioapic)
2356                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2357         else
2358                 io_apic_irqs = ~PIC_IRQS;
2359
2360         printk("ENABLING IO-APIC IRQs\n");
2361
2362         /*
2363          * Set up IO-APIC IRQ routing.
2364          */
2365         if (!acpi_ioapic)
2366                 setup_ioapic_ids_from_mpc();
2367         sync_Arb_IDs();
2368         setup_IO_APIC_irqs();
2369         init_IO_APIC_traps();
2370         check_timer();
2371         if (!acpi_ioapic)
2372                 print_IO_APIC();
2373 }
2374
2375 static int __init setup_disable_8254_timer(char *s)
2376 {
2377         timer_over_8254 = -1;
2378         return 1;
2379 }
2380 static int __init setup_enable_8254_timer(char *s)
2381 {
2382         timer_over_8254 = 2;
2383         return 1;
2384 }
2385
2386 __setup("disable_8254_timer", setup_disable_8254_timer);
2387 __setup("enable_8254_timer", setup_enable_8254_timer);
2388
2389 /*
2390  *      Called after all the initialization is done. If we didnt find any
2391  *      APIC bugs then we can allow the modify fast path
2392  */
2393
2394 static int __init io_apic_bug_finalize(void)
2395 {
2396         if(sis_apic_bug == -1)
2397                 sis_apic_bug = 0;
2398         return 0;
2399 }
2400
2401 late_initcall(io_apic_bug_finalize);
2402
2403 struct sysfs_ioapic_data {
2404         struct sys_device dev;
2405         struct IO_APIC_route_entry entry[0];
2406 };
2407 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2408
2409 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2410 {
2411         struct IO_APIC_route_entry *entry;
2412         struct sysfs_ioapic_data *data;
2413         int i;
2414
2415         data = container_of(dev, struct sysfs_ioapic_data, dev);
2416         entry = data->entry;
2417         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2418                 entry[i] = ioapic_read_entry(dev->id, i);
2419
2420         return 0;
2421 }
2422
2423 static int ioapic_resume(struct sys_device *dev)
2424 {
2425         struct IO_APIC_route_entry *entry;
2426         struct sysfs_ioapic_data *data;
2427         unsigned long flags;
2428         union IO_APIC_reg_00 reg_00;
2429         int i;
2430
2431         data = container_of(dev, struct sysfs_ioapic_data, dev);
2432         entry = data->entry;
2433
2434         spin_lock_irqsave(&ioapic_lock, flags);
2435         reg_00.raw = io_apic_read(dev->id, 0);
2436         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2437                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2438                 io_apic_write(dev->id, 0, reg_00.raw);
2439         }
2440         spin_unlock_irqrestore(&ioapic_lock, flags);
2441         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2442                 ioapic_write_entry(dev->id, i, entry[i]);
2443
2444         return 0;
2445 }
2446
2447 static struct sysdev_class ioapic_sysdev_class = {
2448         set_kset_name("ioapic"),
2449         .suspend = ioapic_suspend,
2450         .resume = ioapic_resume,
2451 };
2452
2453 static int __init ioapic_init_sysfs(void)
2454 {
2455         struct sys_device * dev;
2456         int i, size, error = 0;
2457
2458         error = sysdev_class_register(&ioapic_sysdev_class);
2459         if (error)
2460                 return error;
2461
2462         for (i = 0; i < nr_ioapics; i++ ) {
2463                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2464                         * sizeof(struct IO_APIC_route_entry);
2465                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2466                 if (!mp_ioapic_data[i]) {
2467                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2468                         continue;
2469                 }
2470                 memset(mp_ioapic_data[i], 0, size);
2471                 dev = &mp_ioapic_data[i]->dev;
2472                 dev->id = i;
2473                 dev->cls = &ioapic_sysdev_class;
2474                 error = sysdev_register(dev);
2475                 if (error) {
2476                         kfree(mp_ioapic_data[i]);
2477                         mp_ioapic_data[i] = NULL;
2478                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2479                         continue;
2480                 }
2481         }
2482
2483         return 0;
2484 }
2485
2486 device_initcall(ioapic_init_sysfs);
2487
2488 #ifdef CONFIG_PCI_MSI
2489 /*
2490  * Dynamic irq allocate and deallocation for MSI
2491  */
2492 int create_irq(void)
2493 {
2494         /* Hack of the day: irq == vector.
2495          *
2496          * Ultimately this will be be more general,
2497          * and not depend on the irq to vector identity mapping.
2498          * But this version is needed until msi.c can cope with
2499          * the more general form.
2500          */
2501         int irq, vector;
2502         unsigned long flags;
2503         vector = assign_irq_vector(AUTO_ASSIGN);
2504         irq = vector;
2505
2506         if (vector >= 0) {
2507                 struct irq_desc *desc;
2508
2509                 spin_lock_irqsave(&vector_lock, flags);
2510                 vector_irq[vector] = irq;
2511                 irq_vector[irq] = vector;
2512                 spin_unlock_irqrestore(&vector_lock, flags);
2513
2514                 set_intr_gate(vector, interrupt[irq]);
2515
2516                 dynamic_irq_init(irq);
2517         }
2518         return irq;
2519 }
2520
2521 void destroy_irq(unsigned int irq)
2522 {
2523         unsigned long flags;
2524         unsigned int vector;
2525
2526         dynamic_irq_cleanup(irq);
2527
2528         spin_lock_irqsave(&vector_lock, flags);
2529         vector = irq_vector[irq];
2530         vector_irq[vector] = -1;
2531         irq_vector[irq] = 0;
2532         spin_unlock_irqrestore(&vector_lock, flags);
2533 }
2534 #endif /* CONFIG_PCI_MSI */
2535
2536 /*
2537  * MSI mesage composition
2538  */
2539 #ifdef CONFIG_PCI_MSI
2540 static int msi_msg_setup(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2541 {
2542         /* For now always this code always uses physical delivery
2543          * mode.
2544          */
2545         int vector;
2546         unsigned dest;
2547
2548         vector = assign_irq_vector(irq);
2549         if (vector >= 0) {
2550                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2551
2552                 msg->address_hi = MSI_ADDR_BASE_HI;
2553                 msg->address_lo =
2554                         MSI_ADDR_BASE_LO |
2555                         ((INT_DEST_MODE == 0) ?
2556                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2557                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2558                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2559                                 MSI_ADDR_REDIRECTION_CPU:
2560                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2561                         MSI_ADDR_DEST_ID(dest);
2562
2563                 msg->data =
2564                         MSI_DATA_TRIGGER_EDGE |
2565                         MSI_DATA_LEVEL_ASSERT |
2566                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2567                                 MSI_DATA_DELIVERY_FIXED:
2568                                 MSI_DATA_DELIVERY_LOWPRI) |
2569                         MSI_DATA_VECTOR(vector);
2570         }
2571         return vector;
2572 }
2573
2574 static void msi_msg_teardown(unsigned int irq)
2575 {
2576         return;
2577 }
2578
2579 static void msi_msg_set_affinity(unsigned int irq, cpumask_t mask, struct msi_msg *msg)
2580 {
2581         int vector;
2582         unsigned dest;
2583
2584         vector = assign_irq_vector(irq);
2585         if (vector > 0) {
2586                 dest = cpu_mask_to_apicid(mask);
2587
2588                 msg->data &= ~MSI_DATA_VECTOR_MASK;
2589                 msg->data |= MSI_DATA_VECTOR(vector);
2590                 msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2591                 msg->address_lo |= MSI_ADDR_DEST_ID(dest);
2592         }
2593 }
2594
2595 struct msi_ops arch_msi_ops = {
2596         .needs_64bit_address = 0,
2597         .setup = msi_msg_setup,
2598         .teardown = msi_msg_teardown,
2599         .target = msi_msg_set_affinity,
2600 };
2601
2602 #endif /* CONFIG_PCI_MSI */
2603
2604 /* --------------------------------------------------------------------------
2605                           ACPI-based IOAPIC Configuration
2606    -------------------------------------------------------------------------- */
2607
2608 #ifdef CONFIG_ACPI
2609
2610 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2611 {
2612         union IO_APIC_reg_00 reg_00;
2613         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2614         physid_mask_t tmp;
2615         unsigned long flags;
2616         int i = 0;
2617
2618         /*
2619          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2620          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2621          * supports up to 16 on one shared APIC bus.
2622          *
2623          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2624          *      advantage of new APIC bus architecture.
2625          */
2626
2627         if (physids_empty(apic_id_map))
2628                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2629
2630         spin_lock_irqsave(&ioapic_lock, flags);
2631         reg_00.raw = io_apic_read(ioapic, 0);
2632         spin_unlock_irqrestore(&ioapic_lock, flags);
2633
2634         if (apic_id >= get_physical_broadcast()) {
2635                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2636                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2637                 apic_id = reg_00.bits.ID;
2638         }
2639
2640         /*
2641          * Every APIC in a system must have a unique ID or we get lots of nice
2642          * 'stuck on smp_invalidate_needed IPI wait' messages.
2643          */
2644         if (check_apicid_used(apic_id_map, apic_id)) {
2645
2646                 for (i = 0; i < get_physical_broadcast(); i++) {
2647                         if (!check_apicid_used(apic_id_map, i))
2648                                 break;
2649                 }
2650
2651                 if (i == get_physical_broadcast())
2652                         panic("Max apic_id exceeded!\n");
2653
2654                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2655                         "trying %d\n", ioapic, apic_id, i);
2656
2657                 apic_id = i;
2658         }
2659
2660         tmp = apicid_to_cpu_present(apic_id);
2661         physids_or(apic_id_map, apic_id_map, tmp);
2662
2663         if (reg_00.bits.ID != apic_id) {
2664                 reg_00.bits.ID = apic_id;
2665
2666                 spin_lock_irqsave(&ioapic_lock, flags);
2667                 io_apic_write(ioapic, 0, reg_00.raw);
2668                 reg_00.raw = io_apic_read(ioapic, 0);
2669                 spin_unlock_irqrestore(&ioapic_lock, flags);
2670
2671                 /* Sanity check */
2672                 if (reg_00.bits.ID != apic_id) {
2673                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2674                         return -1;
2675                 }
2676         }
2677
2678         apic_printk(APIC_VERBOSE, KERN_INFO
2679                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2680
2681         return apic_id;
2682 }
2683
2684
2685 int __init io_apic_get_version (int ioapic)
2686 {
2687         union IO_APIC_reg_01    reg_01;
2688         unsigned long flags;
2689
2690         spin_lock_irqsave(&ioapic_lock, flags);
2691         reg_01.raw = io_apic_read(ioapic, 1);
2692         spin_unlock_irqrestore(&ioapic_lock, flags);
2693
2694         return reg_01.bits.version;
2695 }
2696
2697
2698 int __init io_apic_get_redir_entries (int ioapic)
2699 {
2700         union IO_APIC_reg_01    reg_01;
2701         unsigned long flags;
2702
2703         spin_lock_irqsave(&ioapic_lock, flags);
2704         reg_01.raw = io_apic_read(ioapic, 1);
2705         spin_unlock_irqrestore(&ioapic_lock, flags);
2706
2707         return reg_01.bits.entries;
2708 }
2709
2710
2711 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2712 {
2713         struct IO_APIC_route_entry entry;
2714         unsigned long flags;
2715
2716         if (!IO_APIC_IRQ(irq)) {
2717                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2718                         ioapic);
2719                 return -EINVAL;
2720         }
2721
2722         /*
2723          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2724          * Note that we mask (disable) IRQs now -- these get enabled when the
2725          * corresponding device driver registers for this IRQ.
2726          */
2727
2728         memset(&entry,0,sizeof(entry));
2729
2730         entry.delivery_mode = INT_DELIVERY_MODE;
2731         entry.dest_mode = INT_DEST_MODE;
2732         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2733         entry.trigger = edge_level;
2734         entry.polarity = active_high_low;
2735         entry.mask  = 1;
2736
2737         /*
2738          * IRQs < 16 are already in the irq_2_pin[] map
2739          */
2740         if (irq >= 16)
2741                 add_pin_to_irq(irq, ioapic, pin);
2742
2743         entry.vector = assign_irq_vector(irq);
2744
2745         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2746                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2747                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2748                 edge_level, active_high_low);
2749
2750         ioapic_register_intr(irq, entry.vector, edge_level);
2751
2752         if (!ioapic && (irq < 16))
2753                 disable_8259A_irq(irq);
2754
2755         ioapic_write_entry(ioapic, pin, entry);
2756         spin_lock_irqsave(&ioapic_lock, flags);
2757         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2758         spin_unlock_irqrestore(&ioapic_lock, flags);
2759
2760         return 0;
2761 }
2762
2763 #endif /* CONFIG_ACPI */
2764
2765 static int __init parse_disable_timer_pin_1(char *arg)
2766 {
2767         disable_timer_pin_1 = 1;
2768         return 0;
2769 }
2770 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2771
2772 static int __init parse_enable_timer_pin_1(char *arg)
2773 {
2774         disable_timer_pin_1 = -1;
2775         return 0;
2776 }
2777 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2778
2779 static int __init parse_noapic(char *arg)
2780 {
2781         /* disable IO-APIC */
2782         disable_ioapic_setup();
2783         return 0;
2784 }
2785 early_param("noapic", parse_noapic);