arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #ifdef CONFIG_IPIPE
  19 #include <linux/ipipe.h>
  20 #endif
  21 #ifdef CONFIG_KGDB
  22 #include <linux/kgdb.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29
  30 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
  31
  32 #ifdef BF537_FAMILY
  33 # define BF537_GENERIC_ERROR_INT_DEMUX
  34 #else
  35 # undef BF537_GENERIC_ERROR_INT_DEMUX
  36 #endif
  37
  38 /*
  39  * NOTES:
  40  * - we have separated the physical Hardware interrupt from the
  41  * levels that the LINUX kernel sees (see the description in irq.h)
  42  * -
  43  */
  44
  45 #ifndef CONFIG_SMP
  46 /* Initialize this to an actual value to force it into the .data
  47  * section so that we know it is properly initialized at entry into
  48  * the kernel but before bss is initialized to zero (which is where
  49  * it would live otherwise).  The 0x1f magic represents the IRQs we
  50  * cannot actually mask out in hardware.
  51  */
  52 unsigned long bfin_irq_flags = 0x1f;
  53 EXPORT_SYMBOL(bfin_irq_flags);
  54 #endif
  55
  56 /* The number of spurious interrupts */
  57 atomic_t num_spurious;
  58
  59 #ifdef CONFIG_PM
  60 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  61 unsigned vr_wakeup;
  62 #endif
  63
  64 struct ivgx {
  65         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  66         unsigned int irqno;
  67         /* corresponding bit in the SIC_ISR register */
  68         unsigned int isrflag;
  69 } ivg_table[NR_PERI_INTS];
  70
  71 struct ivg_slice {
  72         /* position of first irq in ivg_table for given ivg */
  73         struct ivgx *ifirst;
  74         struct ivgx *istop;
  75 } ivg7_13[IVG13 - IVG7 + 1];
  76
  77
  78 /*
  79  * Search SIC_IAR and fill tables with the irqvalues
  80  * and their positions in the SIC_ISR register.
  81  */
  82 static void __init search_IAR(void)
  83 {
  84         unsigned ivg, irq_pos = 0;
  85         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  86                 int irqn;
  87
  88                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  89
  90                 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
  91                         int iar_shift = (irqn & 7) * 4;
  92                                 if (ivg == (0xf &
  93 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
  94         || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
  95                              bfin_read32((unsigned long *)SIC_IAR0 +
  96                                          ((irqn % 32) >> 3) + ((irqn / 32) *
  97                                          ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
  98 #else
  99                              bfin_read32((unsigned long *)SIC_IAR0 +
 100                                          (irqn >> 3)) >> iar_shift)) {
 101 #endif
 102                                 ivg_table[irq_pos].irqno = IVG7 + irqn;
 103                                 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 104                                 ivg7_13[ivg].istop++;
 105                                 irq_pos++;
 106                         }
 107                 }
 108         }
 109 }
 110
 111 /*
 112  * This is for core internal IRQs
 113  */
 114
 115 static void bfin_ack_noop(unsigned int irq)
 116 {
 117         /* Dummy function.  */
 118 }
 119
 120 static void bfin_core_mask_irq(unsigned int irq)
 121 {
 122         bfin_irq_flags &= ~(1 << irq);
 123         if (!irqs_disabled_hw())
 124                 local_irq_enable_hw();
 125 }
 126
 127 static void bfin_core_unmask_irq(unsigned int irq)
 128 {
 129         bfin_irq_flags |= 1 << irq;
 130         /*
 131          * If interrupts are enabled, IMASK must contain the same value
 132          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 133          * are currently disabled we need not do anything; one of the
 134          * callers will take care of setting IMASK to the proper value
 135          * when reenabling interrupts.
 136          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 137          * what we need.
 138          */
 139         if (!irqs_disabled_hw())
 140                 local_irq_enable_hw();
 141         return;
 142 }
 143
 144 static void bfin_internal_mask_irq(unsigned int irq)
 145 {
 146         unsigned long flags;
 147
 148 #ifdef CONFIG_BF53x
 149         local_irq_save_hw(flags);
 150         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 151                              ~(1 << SIC_SYSIRQ(irq)));
 152 #else
 153         unsigned mask_bank, mask_bit;
 154         local_irq_save_hw(flags);
 155         mask_bank = SIC_SYSIRQ(irq) / 32;
 156         mask_bit = SIC_SYSIRQ(irq) % 32;
 157         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 158                              ~(1 << mask_bit));
 159 #ifdef CONFIG_SMP
 160         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 161                              ~(1 << mask_bit));
 162 #endif
 163 #endif
 164         local_irq_restore_hw(flags);
 165 }
 166
 167 static void bfin_internal_unmask_irq(unsigned int irq)
 168 {
 169         unsigned long flags;
 170
 171 #ifdef CONFIG_BF53x
 172         local_irq_save_hw(flags);
 173         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 174                              (1 << SIC_SYSIRQ(irq)));
 175 #else
 176         unsigned mask_bank, mask_bit;
 177         local_irq_save_hw(flags);
 178         mask_bank = SIC_SYSIRQ(irq) / 32;
 179         mask_bit = SIC_SYSIRQ(irq) % 32;
 180         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
 181                              (1 << mask_bit));
 182 #ifdef CONFIG_SMP
 183         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
 184                              (1 << mask_bit));
 185 #endif
 186 #endif
 187         local_irq_restore_hw(flags);
 188 }
 189
 190 #ifdef CONFIG_PM
 191 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 192 {
 193         u32 bank, bit, wakeup = 0;
 194         unsigned long flags;
 195         bank = SIC_SYSIRQ(irq) / 32;
 196         bit = SIC_SYSIRQ(irq) % 32;
 197
 198         switch (irq) {
 199 #ifdef IRQ_RTC
 200         case IRQ_RTC:
 201         wakeup |= WAKE;
 202         break;
 203 #endif
 204 #ifdef IRQ_CAN0_RX
 205         case IRQ_CAN0_RX:
 206         wakeup |= CANWE;
 207         break;
 208 #endif
 209 #ifdef IRQ_CAN1_RX
 210         case IRQ_CAN1_RX:
 211         wakeup |= CANWE;
 212         break;
 213 #endif
 214 #ifdef IRQ_USB_INT0
 215         case IRQ_USB_INT0:
 216         wakeup |= USBWE;
 217         break;
 218 #endif
 219 #ifdef IRQ_KEY
 220         case IRQ_KEY:
 221         wakeup |= KPADWE;
 222         break;
 223 #endif
 224 #ifdef CONFIG_BF54x
 225         case IRQ_CNT:
 226         wakeup |= ROTWE;
 227         break;
 228 #endif
 229         default:
 230         break;
 231         }
 232
 233         local_irq_save_hw(flags);
 234
 235         if (state) {
 236                 bfin_sic_iwr[bank] |= (1 << bit);
 237                 vr_wakeup  |= wakeup;
 238
 239         } else {
 240                 bfin_sic_iwr[bank] &= ~(1 << bit);
 241                 vr_wakeup  &= ~wakeup;
 242         }
 243
 244         local_irq_restore_hw(flags);
 245
 246         return 0;
 247 }
 248 #endif
 249
 250 static struct irq_chip bfin_core_irqchip = {
 251         .name = "CORE",
 252         .ack = bfin_ack_noop,
 253         .mask = bfin_core_mask_irq,
 254         .unmask = bfin_core_unmask_irq,
 255 };
 256
 257 static struct irq_chip bfin_internal_irqchip = {
 258         .name = "INTN",
 259         .ack = bfin_ack_noop,
 260         .mask = bfin_internal_mask_irq,
 261         .unmask = bfin_internal_unmask_irq,
 262         .mask_ack = bfin_internal_mask_irq,
 263         .disable = bfin_internal_mask_irq,
 264         .enable = bfin_internal_unmask_irq,
 265 #ifdef CONFIG_PM
 266         .set_wake = bfin_internal_set_wake,
 267 #endif
 268 };
 269
 270 static void bfin_handle_irq(unsigned irq)
 271 {
 272 #ifdef CONFIG_IPIPE
 273         struct pt_regs regs;    /* Contents not used. */
 274         ipipe_trace_irq_entry(irq);
 275         __ipipe_handle_irq(irq, &regs);
 276         ipipe_trace_irq_exit(irq);
 277 #else /* !CONFIG_IPIPE */
 278         struct irq_desc *desc = irq_desc + irq;
 279         desc->handle_irq(irq, desc);
 280 #endif  /* !CONFIG_IPIPE */
 281 }
 282
 283 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 284 static int error_int_mask;
 285
 286 static void bfin_generic_error_mask_irq(unsigned int irq)
 287 {
 288         error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
 289
 290         if (!error_int_mask)
 291                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
 292 }
 293
 294 static void bfin_generic_error_unmask_irq(unsigned int irq)
 295 {
 296         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
 297         error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
 298 }
 299
 300 static struct irq_chip bfin_generic_error_irqchip = {
 301         .name = "ERROR",
 302         .ack = bfin_ack_noop,
 303         .mask_ack = bfin_generic_error_mask_irq,
 304         .mask = bfin_generic_error_mask_irq,
 305         .unmask = bfin_generic_error_unmask_irq,
 306 };
 307
 308 static void bfin_demux_error_irq(unsigned int int_err_irq,
 309                                  struct irq_desc *inta_desc)
 310 {
 311         int irq = 0;
 312
 313 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 314         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 315                 irq = IRQ_MAC_ERROR;
 316         else
 317 #endif
 318         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 319                 irq = IRQ_SPORT0_ERROR;
 320         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 321                 irq = IRQ_SPORT1_ERROR;
 322         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 323                 irq = IRQ_PPI_ERROR;
 324         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 325                 irq = IRQ_CAN_ERROR;
 326         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 327                 irq = IRQ_SPI_ERROR;
 328         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
 329                  (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
 330                 irq = IRQ_UART0_ERROR;
 331         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
 332                  (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
 333                 irq = IRQ_UART1_ERROR;
 334
 335         if (irq) {
 336                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
 337                         bfin_handle_irq(irq);
 338                 else {
 339
 340                         switch (irq) {
 341                         case IRQ_PPI_ERROR:
 342                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
 343                                 break;
 344 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 345                         case IRQ_MAC_ERROR:
 346                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 347                                 break;
 348 #endif
 349                         case IRQ_SPORT0_ERROR:
 350                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 351                                 break;
 352
 353                         case IRQ_SPORT1_ERROR:
 354                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 355                                 break;
 356
 357                         case IRQ_CAN_ERROR:
 358                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
 359                                 break;
 360
 361                         case IRQ_SPI_ERROR:
 362                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
 363                                 break;
 364
 365                         default:
 366                                 break;
 367                         }
 368
 369                         pr_debug("IRQ %d:"
 370                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 371                                  irq);
 372                 }
 373         } else
 374                 printk(KERN_ERR
 375                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
 376                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 377                        __func__, __FILE__, __LINE__);
 378
 379 }
 380 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 381
 382 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 383 {
 384 #ifdef CONFIG_IPIPE
 385         _set_irq_handler(irq, handle_level_irq);
 386 #else
 387         struct irq_desc *desc = irq_desc + irq;
 388         /* May not call generic set_irq_handler() due to spinlock
 389            recursion. */
 390         desc->handle_irq = handle;
 391 #endif
 392 }
 393
 394 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 395 extern void bfin_gpio_irq_prepare(unsigned gpio);
 396
 397 #if !defined(CONFIG_BF54x)
 398
 399 static void bfin_gpio_ack_irq(unsigned int irq)
 400 {
 401         /* AFAIK ack_irq in case mask_ack is provided
 402          * get's only called for edge sense irqs
 403          */
 404         set_gpio_data(irq_to_gpio(irq), 0);
 405 }
 406
 407 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 408 {
 409         struct irq_desc *desc = irq_desc + irq;
 410         u32 gpionr = irq_to_gpio(irq);
 411
 412         if (desc->handle_irq == handle_edge_irq)
 413                 set_gpio_data(gpionr, 0);
 414
 415         set_gpio_maska(gpionr, 0);
 416 }
 417
 418 static void bfin_gpio_mask_irq(unsigned int irq)
 419 {
 420         set_gpio_maska(irq_to_gpio(irq), 0);
 421 }
 422
 423 static void bfin_gpio_unmask_irq(unsigned int irq)
 424 {
 425         set_gpio_maska(irq_to_gpio(irq), 1);
 426 }
 427
 428 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 429 {
 430         u32 gpionr = irq_to_gpio(irq);
 431
 432         if (__test_and_set_bit(gpionr, gpio_enabled))
 433                 bfin_gpio_irq_prepare(gpionr);
 434
 435         bfin_gpio_unmask_irq(irq);
 436
 437         return 0;
 438 }
 439
 440 static void bfin_gpio_irq_shutdown(unsigned int irq)
 441 {
 442         u32 gpionr = irq_to_gpio(irq);
 443
 444         bfin_gpio_mask_irq(irq);
 445         __clear_bit(gpionr, gpio_enabled);
 446         bfin_gpio_irq_free(gpionr);
 447 }
 448
 449 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 450 {
 451         int ret;
 452         char buf[16];
 453         u32 gpionr = irq_to_gpio(irq);
 454
 455         if (type == IRQ_TYPE_PROBE) {
 456                 /* only probe unenabled GPIO interrupt lines */
 457                 if (test_bit(gpionr, gpio_enabled))
 458                         return 0;
 459                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 460         }
 461
 462         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 463                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 464
 465                 snprintf(buf, 16, "gpio-irq%d", irq);
 466                 ret = bfin_gpio_irq_request(gpionr, buf);
 467                 if (ret)
 468                         return ret;
 469
 470                 if (__test_and_set_bit(gpionr, gpio_enabled))
 471                         bfin_gpio_irq_prepare(gpionr);
 472
 473         } else {
 474                 __clear_bit(gpionr, gpio_enabled);
 475                 return 0;
 476         }
 477
 478         set_gpio_inen(gpionr, 0);
 479         set_gpio_dir(gpionr, 0);
 480
 481         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 482             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 483                 set_gpio_both(gpionr, 1);
 484         else
 485                 set_gpio_both(gpionr, 0);
 486
 487         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 488                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 489         else
 490                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 491
 492         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 493                 set_gpio_edge(gpionr, 1);
 494                 set_gpio_inen(gpionr, 1);
 495                 set_gpio_data(gpionr, 0);
 496
 497         } else {
 498                 set_gpio_edge(gpionr, 0);
 499                 set_gpio_inen(gpionr, 1);
 500         }
 501
 502         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 503                 bfin_set_irq_handler(irq, handle_edge_irq);
 504         else
 505                 bfin_set_irq_handler(irq, handle_level_irq);
 506
 507         return 0;
 508 }
 509
 510 #ifdef CONFIG_PM
 511 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 512 {
 513         unsigned gpio = irq_to_gpio(irq);
 514
 515         if (state)
 516                 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
 517         else
 518                 gpio_pm_wakeup_free(gpio);
 519
 520         return 0;
 521 }
 522 #endif
 523
 524 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 525                                 struct irq_desc *desc)
 526 {
 527         unsigned int i, gpio, mask, irq, search = 0;
 528
 529         switch (inta_irq) {
 530 #if defined(CONFIG_BF53x)
 531         case IRQ_PROG_INTA:
 532                 irq = IRQ_PF0;
 533                 search = 1;
 534                 break;
 535 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 536         case IRQ_MAC_RX:
 537                 irq = IRQ_PH0;
 538                 break;
 539 # endif
 540 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
 541         case IRQ_PORTF_INTA:
 542                 irq = IRQ_PF0;
 543                 break;
 544 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 545         case IRQ_PORTF_INTA:
 546                 irq = IRQ_PF0;
 547                 break;
 548         case IRQ_PORTG_INTA:
 549                 irq = IRQ_PG0;
 550                 break;
 551         case IRQ_PORTH_INTA:
 552                 irq = IRQ_PH0;
 553                 break;
 554 #elif defined(CONFIG_BF561)
 555         case IRQ_PROG0_INTA:
 556                 irq = IRQ_PF0;
 557                 break;
 558         case IRQ_PROG1_INTA:
 559                 irq = IRQ_PF16;
 560                 break;
 561         case IRQ_PROG2_INTA:
 562                 irq = IRQ_PF32;
 563                 break;
 564 #endif
 565         default:
 566                 BUG();
 567                 return;
 568         }
 569
 570         if (search) {
 571                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
 572                         irq += i;
 573
 574                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
 575
 576                         while (mask) {
 577                                 if (mask & 1)
 578                                         bfin_handle_irq(irq);
 579                                 irq++;
 580                                 mask >>= 1;
 581                         }
 582                 }
 583         } else {
 584                         gpio = irq_to_gpio(irq);
 585                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 586
 587                         do {
 588                                 if (mask & 1)
 589                                         bfin_handle_irq(irq);
 590                                 irq++;
 591                                 mask >>= 1;
 592                         } while (mask);
 593         }
 594
 595 }
 596
 597 #else                           /* CONFIG_BF54x */
 598
 599 #define NR_PINT_SYS_IRQS        4
 600 #define NR_PINT_BITS            32
 601 #define NR_PINTS                160
 602 #define IRQ_NOT_AVAIL           0xFF
 603
 604 #define PINT_2_BANK(x)          ((x) >> 5)
 605 #define PINT_2_BIT(x)           ((x) & 0x1F)
 606 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 607
 608 static unsigned char irq2pint_lut[NR_PINTS];
 609 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 610
 611 struct pin_int_t {
 612         unsigned int mask_set;
 613         unsigned int mask_clear;
 614         unsigned int request;
 615         unsigned int assign;
 616         unsigned int edge_set;
 617         unsigned int edge_clear;
 618         unsigned int invert_set;
 619         unsigned int invert_clear;
 620         unsigned int pinstate;
 621         unsigned int latch;
 622 };
 623
 624 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
 625         (struct pin_int_t *)PINT0_MASK_SET,
 626         (struct pin_int_t *)PINT1_MASK_SET,
 627         (struct pin_int_t *)PINT2_MASK_SET,
 628         (struct pin_int_t *)PINT3_MASK_SET,
 629 };
 630
 631 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 632 {
 633         unsigned int irq_base;
 634
 635         if (bank < 2) {         /*PA-PB */
 636                 irq_base = IRQ_PA0 + bmap * 16;
 637         } else {                /*PC-PJ */
 638                 irq_base = IRQ_PC0 + bmap * 16;
 639         }
 640
 641         return irq_base;
 642 }
 643
 644         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 645 void init_pint_lut(void)
 646 {
 647         u16 bank, bit, irq_base, bit_pos;
 648         u32 pint_assign;
 649         u8 bmap;
 650
 651         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 652
 653         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 654
 655                 pint_assign = pint[bank]->assign;
 656
 657                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 658
 659                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 660
 661                         irq_base = get_irq_base(bank, bmap);
 662
 663                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 664                         bit_pos = bit + bank * NR_PINT_BITS;
 665
 666                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 667                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 668                 }
 669         }
 670 }
 671
 672 static void bfin_gpio_ack_irq(unsigned int irq)
 673 {
 674         struct irq_desc *desc = irq_desc + irq;
 675         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 676         u32 pintbit = PINT_BIT(pint_val);
 677         u32 bank = PINT_2_BANK(pint_val);
 678
 679         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 680                 if (pint[bank]->invert_set & pintbit)
 681                         pint[bank]->invert_clear = pintbit;
 682                 else
 683                         pint[bank]->invert_set = pintbit;
 684         }
 685         pint[bank]->request = pintbit;
 686
 687 }
 688
 689 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 690 {
 691         struct irq_desc *desc = irq_desc + irq;
 692         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 693         u32 pintbit = PINT_BIT(pint_val);
 694         u32 bank = PINT_2_BANK(pint_val);
 695
 696         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 697                 if (pint[bank]->invert_set & pintbit)
 698                         pint[bank]->invert_clear = pintbit;
 699                 else
 700                         pint[bank]->invert_set = pintbit;
 701         }
 702
 703         pint[bank]->request = pintbit;
 704         pint[bank]->mask_clear = pintbit;
 705 }
 706
 707 static void bfin_gpio_mask_irq(unsigned int irq)
 708 {
 709         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 710
 711         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 712 }
 713
 714 static void bfin_gpio_unmask_irq(unsigned int irq)
 715 {
 716         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 717         u32 pintbit = PINT_BIT(pint_val);
 718         u32 bank = PINT_2_BANK(pint_val);
 719
 720         pint[bank]->request = pintbit;
 721         pint[bank]->mask_set = pintbit;
 722 }
 723
 724 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 725 {
 726         u32 gpionr = irq_to_gpio(irq);
 727         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 728
 729         if (pint_val == IRQ_NOT_AVAIL) {
 730                 printk(KERN_ERR
 731                 "GPIO IRQ %d :Not in PINT Assign table "
 732                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 733                 return -ENODEV;
 734         }
 735
 736         if (__test_and_set_bit(gpionr, gpio_enabled))
 737                 bfin_gpio_irq_prepare(gpionr);
 738
 739         bfin_gpio_unmask_irq(irq);
 740
 741         return 0;
 742 }
 743
 744 static void bfin_gpio_irq_shutdown(unsigned int irq)
 745 {
 746         u32 gpionr = irq_to_gpio(irq);
 747
 748         bfin_gpio_mask_irq(irq);
 749         __clear_bit(gpionr, gpio_enabled);
 750         bfin_gpio_irq_free(gpionr);
 751 }
 752
 753 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 754 {
 755         int ret;
 756         char buf[16];
 757         u32 gpionr = irq_to_gpio(irq);
 758         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 759         u32 pintbit = PINT_BIT(pint_val);
 760         u32 bank = PINT_2_BANK(pint_val);
 761
 762         if (pint_val == IRQ_NOT_AVAIL)
 763                 return -ENODEV;
 764
 765         if (type == IRQ_TYPE_PROBE) {
 766                 /* only probe unenabled GPIO interrupt lines */
 767                 if (test_bit(gpionr, gpio_enabled))
 768                         return 0;
 769                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 770         }
 771
 772         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 773                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 774
 775                 snprintf(buf, 16, "gpio-irq%d", irq);
 776                 ret = bfin_gpio_irq_request(gpionr, buf);
 777                 if (ret)
 778                         return ret;
 779
 780                 if (__test_and_set_bit(gpionr, gpio_enabled))
 781                         bfin_gpio_irq_prepare(gpionr);
 782
 783         } else {
 784                 __clear_bit(gpionr, gpio_enabled);
 785                 return 0;
 786         }
 787
 788         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 789                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
 790         else
 791                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
 792
 793         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 794             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 795                 if (gpio_get_value(gpionr))
 796                         pint[bank]->invert_set = pintbit;
 797                 else
 798                         pint[bank]->invert_clear = pintbit;
 799         }
 800
 801         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 802                 pint[bank]->edge_set = pintbit;
 803                 bfin_set_irq_handler(irq, handle_edge_irq);
 804         } else {
 805                 pint[bank]->edge_clear = pintbit;
 806                 bfin_set_irq_handler(irq, handle_level_irq);
 807         }
 808
 809         return 0;
 810 }
 811
 812 #ifdef CONFIG_PM
 813 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
 814 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
 815
 816 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 817 {
 818         u32 pint_irq;
 819         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 820         u32 bank = PINT_2_BANK(pint_val);
 821         u32 pintbit = PINT_BIT(pint_val);
 822
 823         switch (bank) {
 824         case 0:
 825                 pint_irq = IRQ_PINT0;
 826                 break;
 827         case 2:
 828                 pint_irq = IRQ_PINT2;
 829                 break;
 830         case 3:
 831                 pint_irq = IRQ_PINT3;
 832                 break;
 833         case 1:
 834                 pint_irq = IRQ_PINT1;
 835                 break;
 836         default:
 837                 return -EINVAL;
 838         }
 839
 840         bfin_internal_set_wake(pint_irq, state);
 841
 842         if (state)
 843                 pint_wakeup_masks[bank] |= pintbit;
 844         else
 845                 pint_wakeup_masks[bank] &= ~pintbit;
 846
 847         return 0;
 848 }
 849
 850 u32 bfin_pm_setup(void)
 851 {
 852         u32 val, i;
 853
 854         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
 855                 val = pint[i]->mask_clear;
 856                 pint_saved_masks[i] = val;
 857                 if (val ^ pint_wakeup_masks[i]) {
 858                         pint[i]->mask_clear = val;
 859                         pint[i]->mask_set = pint_wakeup_masks[i];
 860                 }
 861         }
 862
 863         return 0;
 864 }
 865
 866 void bfin_pm_restore(void)
 867 {
 868         u32 i, val;
 869
 870         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
 871                 val = pint_saved_masks[i];
 872                 if (val ^ pint_wakeup_masks[i]) {
 873                         pint[i]->mask_clear = pint[i]->mask_clear;
 874                         pint[i]->mask_set = val;
 875                 }
 876         }
 877 }
 878 #endif
 879
 880 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 881                                 struct irq_desc *desc)
 882 {
 883         u32 bank, pint_val;
 884         u32 request, irq;
 885
 886         switch (inta_irq) {
 887         case IRQ_PINT0:
 888                 bank = 0;
 889                 break;
 890         case IRQ_PINT2:
 891                 bank = 2;
 892                 break;
 893         case IRQ_PINT3:
 894                 bank = 3;
 895                 break;
 896         case IRQ_PINT1:
 897                 bank = 1;
 898                 break;
 899         default:
 900                 return;
 901         }
 902
 903         pint_val = bank * NR_PINT_BITS;
 904
 905         request = pint[bank]->request;
 906
 907         while (request) {
 908                 if (request & 1) {
 909                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
 910                         bfin_handle_irq(irq);
 911                 }
 912                 pint_val++;
 913                 request >>= 1;
 914         }
 915
 916 }
 917 #endif
 918
 919 static struct irq_chip bfin_gpio_irqchip = {
 920         .name = "GPIO",
 921         .ack = bfin_gpio_ack_irq,
 922         .mask = bfin_gpio_mask_irq,
 923         .mask_ack = bfin_gpio_mask_ack_irq,
 924         .unmask = bfin_gpio_unmask_irq,
 925         .disable = bfin_gpio_mask_irq,
 926         .enable = bfin_gpio_unmask_irq,
 927         .set_type = bfin_gpio_irq_type,
 928         .startup = bfin_gpio_irq_startup,
 929         .shutdown = bfin_gpio_irq_shutdown,
 930 #ifdef CONFIG_PM
 931         .set_wake = bfin_gpio_set_wake,
 932 #endif
 933 };
 934
 935 void __cpuinit init_exception_vectors(void)
 936 {
 937         /* cannot program in software:
 938          * evt0 - emulation (jtag)
 939          * evt1 - reset
 940          */
 941         bfin_write_EVT2(evt_nmi);
 942         bfin_write_EVT3(trap);
 943         bfin_write_EVT5(evt_ivhw);
 944         bfin_write_EVT6(evt_timer);
 945         bfin_write_EVT7(evt_evt7);
 946         bfin_write_EVT8(evt_evt8);
 947         bfin_write_EVT9(evt_evt9);
 948         bfin_write_EVT10(evt_evt10);
 949         bfin_write_EVT11(evt_evt11);
 950         bfin_write_EVT12(evt_evt12);
 951         bfin_write_EVT13(evt_evt13);
 952         bfin_write_EVT14(evt_evt14);
 953         bfin_write_EVT15(evt_system_call);
 954         CSYNC();
 955 }
 956
 957 /*
 958  * This function should be called during kernel startup to initialize
 959  * the BFin IRQ handling routines.
 960  */
 961
 962 int __init init_arch_irq(void)
 963 {
 964         int irq;
 965         unsigned long ilat = 0;
 966         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
 967 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
 968         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
 969         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
 970         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
 971 # ifdef CONFIG_BF54x
 972         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
 973 # endif
 974 # ifdef CONFIG_SMP
 975         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
 976         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
 977 # endif
 978 #else
 979         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 980 #endif
 981
 982         local_irq_disable();
 983
 984 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 985         /* Clear EMAC Interrupt Status bits so we can demux it later */
 986         bfin_write_EMAC_SYSTAT(-1);
 987 #endif
 988
 989 #ifdef CONFIG_BF54x
 990 # ifdef CONFIG_PINTx_REASSIGN
 991         pint[0]->assign = CONFIG_PINT0_ASSIGN;
 992         pint[1]->assign = CONFIG_PINT1_ASSIGN;
 993         pint[2]->assign = CONFIG_PINT2_ASSIGN;
 994         pint[3]->assign = CONFIG_PINT3_ASSIGN;
 995 # endif
 996         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 997         init_pint_lut();
 998 #endif
 999
1000         for (irq = 0; irq <= SYS_IRQS; irq++) {
1001                 if (irq <= IRQ_CORETMR)
1002                         set_irq_chip(irq, &bfin_core_irqchip);
1003                 else
1004                         set_irq_chip(irq, &bfin_internal_irqchip);
1005
1006                 switch (irq) {
1007 #if defined(CONFIG_BF53x)
1008                 case IRQ_PROG_INTA:
1009 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1010                 case IRQ_MAC_RX:
1011 # endif
1012 #elif defined(CONFIG_BF54x)
1013                 case IRQ_PINT0:
1014                 case IRQ_PINT1:
1015                 case IRQ_PINT2:
1016                 case IRQ_PINT3:
1017 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1018                 case IRQ_PORTF_INTA:
1019                 case IRQ_PORTG_INTA:
1020                 case IRQ_PORTH_INTA:
1021 #elif defined(CONFIG_BF561)
1022                 case IRQ_PROG0_INTA:
1023                 case IRQ_PROG1_INTA:
1024                 case IRQ_PROG2_INTA:
1025 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1026                 case IRQ_PORTF_INTA:
1027 #endif
1028
1029                         set_irq_chained_handler(irq,
1030                                                 bfin_demux_gpio_irq);
1031                         break;
1032 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1033                 case IRQ_GENERIC_ERROR:
1034                         set_irq_chained_handler(irq, bfin_demux_error_irq);
1035                         break;
1036 #endif
1037
1038 #ifdef CONFIG_SMP
1039 #ifdef CONFIG_TICKSOURCE_GPTMR0
1040                 case IRQ_TIMER0:
1041 #endif
1042 #ifdef CONFIG_TICKSOURCE_CORETMR
1043                 case IRQ_CORETMR:
1044 #endif
1045                 case IRQ_SUPPLE_0:
1046                 case IRQ_SUPPLE_1:
1047                         set_irq_handler(irq, handle_percpu_irq);
1048                         break;
1049 #endif
1050
1051 #ifdef CONFIG_IPIPE
1052 #ifndef CONFIG_TICKSOURCE_CORETMR
1053                 case IRQ_TIMER0:
1054                         set_irq_handler(irq, handle_simple_irq);
1055                         break;
1056 #endif
1057                 case IRQ_CORETMR:
1058                         set_irq_handler(irq, handle_simple_irq);
1059                         break;
1060                 default:
1061                         set_irq_handler(irq, handle_level_irq);
1062                         break;
1063 #else /* !CONFIG_IPIPE */
1064                 default:
1065                         set_irq_handler(irq, handle_simple_irq);
1066                         break;
1067 #endif /* !CONFIG_IPIPE */
1068                 }
1069         }
1070
1071 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1072         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1073                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1074                                          handle_level_irq);
1075 #endif
1076
1077         /* if configured as edge, then will be changed to do_edge_IRQ */
1078         for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1079                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1080                                          handle_level_irq);
1081
1082
1083         bfin_write_IMASK(0);
1084         CSYNC();
1085         ilat = bfin_read_ILAT();
1086         CSYNC();
1087         bfin_write_ILAT(ilat);
1088         CSYNC();
1089
1090         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1091         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1092          * local_irq_enable()
1093          */
1094         program_IAR();
1095         /* Therefore it's better to setup IARs before interrupts enabled */
1096         search_IAR();
1097
1098         /* Enable interrupts IVG7-15 */
1099         bfin_irq_flags |= IMASK_IVG15 |
1100             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1101             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1102
1103         /* This implicitly covers ANOMALY_05000171
1104          * Boot-ROM code modifies SICA_IWRx wakeup registers
1105          */
1106 #ifdef SIC_IWR0
1107         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1108 # ifdef SIC_IWR1
1109         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1110          * will screw up the bootrom as it relies on MDMA0/1 waking it
1111          * up from IDLE instructions.  See this report for more info:
1112          * http://blackfin.uclinux.org/gf/tracker/4323
1113          */
1114         if (ANOMALY_05000435)
1115                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1116         else
1117                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1118 # endif
1119 # ifdef SIC_IWR2
1120         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1121 # endif
1122 #else
1123         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1124 #endif
1125
1126         return 0;
1127 }
1128
1129 #ifdef CONFIG_DO_IRQ_L1
1130 __attribute__((l1_text))
1131 #endif
1132 void do_irq(int vec, struct pt_regs *fp)
1133 {
1134         if (vec == EVT_IVTMR_P) {
1135                 vec = IRQ_CORETMR;
1136         } else {
1137                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1138                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1139 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1140                 unsigned long sic_status[3];
1141
1142                 if (smp_processor_id()) {
1143 # ifdef SICB_ISR0
1144                         /* This will be optimized out in UP mode. */
1145                         sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1146                         sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1147 # endif
1148                 } else {
1149                         sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1150                         sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1151                 }
1152 # ifdef SIC_ISR2
1153                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1154 # endif
1155                 for (;; ivg++) {
1156                         if (ivg >= ivg_stop) {
1157                                 atomic_inc(&num_spurious);
1158                                 return;
1159                         }
1160                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1161                                 break;
1162                 }
1163 #else
1164                 unsigned long sic_status;
1165
1166                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1167
1168                 for (;; ivg++) {
1169                         if (ivg >= ivg_stop) {
1170                                 atomic_inc(&num_spurious);
1171                                 return;
1172                         } else if (sic_status & ivg->isrflag)
1173                                 break;
1174                 }
1175 #endif
1176                 vec = ivg->irqno;
1177         }
1178         asm_do_IRQ(vec, fp);
1179 }
1180
1181 #ifdef CONFIG_IPIPE
1182
1183 int __ipipe_get_irq_priority(unsigned irq)
1184 {
1185         int ient, prio;
1186
1187         if (irq <= IRQ_CORETMR)
1188                 return irq;
1189
1190         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1191                 struct ivgx *ivg = ivg_table + ient;
1192                 if (ivg->irqno == irq) {
1193                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1194                                 if (ivg7_13[prio].ifirst <= ivg &&
1195                                     ivg7_13[prio].istop > ivg)
1196                                         return IVG7 + prio;
1197                         }
1198                 }
1199         }
1200
1201         return IVG15;
1202 }
1203
1204 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1205 #ifdef CONFIG_DO_IRQ_L1
1206 __attribute__((l1_text))
1207 #endif
1208 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1209 {
1210         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1211         struct ipipe_domain *this_domain = __ipipe_current_domain;
1212         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1213         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1214         int irq, s;
1215
1216         if (likely(vec == EVT_IVTMR_P))
1217                 irq = IRQ_CORETMR;
1218         else {
1219 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1220                 unsigned long sic_status[3];
1221
1222                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1223                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1224 # ifdef SIC_ISR2
1225                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1226 # endif
1227                 for (;; ivg++) {
1228                         if (ivg >= ivg_stop) {
1229                                 atomic_inc(&num_spurious);
1230                                 return 0;
1231                         }
1232                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1233                                 break;
1234                 }
1235 #else
1236                 unsigned long sic_status;
1237
1238                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1239
1240                 for (;; ivg++) {
1241                         if (ivg >= ivg_stop) {
1242                                 atomic_inc(&num_spurious);
1243                                 return 0;
1244                         } else if (sic_status & ivg->isrflag)
1245                                 break;
1246                 }
1247 #endif
1248                 irq = ivg->irqno;
1249         }
1250
1251         if (irq == IRQ_SYSTMR) {
1252 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1253                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1254 #endif
1255                 /* This is basically what we need from the register frame. */
1256                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1257                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1258                 if (this_domain != ipipe_root_domain)
1259                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1260                 else
1261                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1262         }
1263
1264         if (this_domain == ipipe_root_domain) {
1265                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1266                 barrier();
1267         }
1268
1269         ipipe_trace_irq_entry(irq);
1270         __ipipe_handle_irq(irq, regs);
1271         ipipe_trace_irq_exit(irq);
1272
1273         if (this_domain == ipipe_root_domain) {
1274                 set_thread_flag(TIF_IRQ_SYNC);
1275                 if (!s) {
1276                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1277                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1278                 }
1279         }
1280
1281         return 0;
1282 }
1283
1284 #endif /* CONFIG_IPIPE */