2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
34 config GENERIC_FIND_NEXT_BIT
38 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
46 config GENERIC_IRQ_PROBE
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
67 source "kernel/Kconfig.preempt"
69 menu "Blackfin Processor Options"
71 comment "Processor and Board Settings"
80 BF522 Processor Support.
85 BF523 Processor Support.
90 BF524 Processor Support.
95 BF525 Processor Support.
100 BF526 Processor Support.
105 BF527 Processor Support.
110 BF531 Processor Support.
115 BF532 Processor Support.
120 BF533 Processor Support.
125 BF534 Processor Support.
130 BF536 Processor Support.
135 BF537 Processor Support.
140 BF542 Processor Support.
145 BF544 Processor Support.
150 BF547 Processor Support.
155 BF548 Processor Support.
160 BF549 Processor Support.
165 Not Supported Yet - Work in progress - BF561 Processor Support.
171 default BF_REV_0_1 if BF527
172 default BF_REV_0_2 if BF537
173 default BF_REV_0_3 if BF533
174 default BF_REV_0_0 if BF549
178 depends on (BF52x || BF54x)
182 depends on (BF52x || BF54x)
186 depends on (BF537 || BF536 || BF534)
190 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
194 depends on (BF561 || BF533 || BF532 || BF531)
198 depends on (BF561 || BF533 || BF532 || BF531)
210 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
215 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
220 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
223 config MEM_GENERIC_BOARD
225 depends on GENERIC_BOARD
228 config MEM_MT48LC64M4A2FB_7E
230 depends on (BFIN533_STAMP)
233 config MEM_MT48LC16M16A2TG_75
235 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
236 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
237 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
240 config MEM_MT48LC32M8A2_75
242 depends on (BFIN537_STAMP || PNAV10)
245 config MEM_MT48LC8M32B2B5_7
247 depends on (BFIN561_BLUETECHNIX_CM)
250 config MEM_MT48LC32M16A2TG_75
252 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
255 source "arch/blackfin/mach-bf527/Kconfig"
256 source "arch/blackfin/mach-bf533/Kconfig"
257 source "arch/blackfin/mach-bf561/Kconfig"
258 source "arch/blackfin/mach-bf537/Kconfig"
259 source "arch/blackfin/mach-bf548/Kconfig"
261 menu "Board customizations"
264 bool "Default bootloader kernel arguments"
267 string "Initial kernel command string"
268 depends on CMDLINE_BOOL
269 default "console=ttyBF0,57600"
271 If you don't have a boot loader capable of passing a command line string
272 to the kernel, you may specify one here. As a minimum, you should specify
273 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
276 hex "Kernel load address for booting"
278 range 0x1000 0x20000000
280 This option allows you to set the load address of the kernel.
281 This can be useful if you are on a board which has a small amount
282 of memory or you wish to reserve some memory at the beginning of
285 Note that you need to keep this value above 4k (0x1000) as this
286 memory region is used to capture NULL pointer references as well
287 as some core kernel functions.
290 hex "Kernel ROM Base"
292 range 0x20000000 0x20400000 if !(BF54x || BF561)
293 range 0x20000000 0x30000000 if (BF54x || BF561)
296 comment "Clock/PLL Setup"
299 int "Frequency of the crystal on the board in Hz"
300 default "11059200" if BFIN533_STAMP
301 default "27000000" if BFIN533_EZKIT
302 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
303 default "30000000" if BFIN561_EZKIT
304 default "24576000" if PNAV10
305 default "10000000" if BFIN532_IP0X
307 The frequency of CLKIN crystal oscillator on the board in Hz.
308 Warning: This value should match the crystal on the board. Otherwise,
309 peripherals won't work properly.
311 config BFIN_KERNEL_CLOCK
312 bool "Re-program Clocks while Kernel boots?"
315 This option decides if kernel clocks are re-programed from the
316 bootloader settings. If the clocks are not set, the SDRAM settings
317 are also not changed, and the Bootloader does 100% of the hardware
322 depends on BFIN_KERNEL_CLOCK
327 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
330 If this is set the clock will be divided by 2, before it goes to the PLL.
334 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
336 default "22" if BFIN533_EZKIT
337 default "45" if BFIN533_STAMP
338 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
339 default "22" if BFIN533_BLUETECHNIX_CM
340 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
341 default "20" if BFIN561_EZKIT
342 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
344 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
345 PLL Frequency = (Crystal Frequency) * (this setting)
348 prompt "Core Clock Divider"
349 depends on BFIN_KERNEL_CLOCK
352 This sets the frequency of the core. It can be 1, 2, 4 or 8
353 Core Frequency = (PLL frequency) / (this setting)
369 int "System Clock Divider"
370 depends on BFIN_KERNEL_CLOCK
374 This sets the frequency of the system clock (including SDRAM or DDR).
375 This can be between 1 and 15
376 System Clock = (PLL frequency) / (this setting)
379 int "Max SDRAM Memory Size in MBytes"
383 This is the max memory size that the kernel will create CPLB
384 tables for. Your system will not be able to handle any more.
387 prompt "DDR SDRAM Chip Type"
388 depends on BFIN_KERNEL_CLOCK
390 default MEM_MT46V32M16_5B
392 config MEM_MT46V32M16_6T
395 config MEM_MT46V32M16_5B
400 # Max & Min Speeds for various Chips
404 default 600000000 if BF522
405 default 400000000 if BF523
406 default 400000000 if BF524
407 default 600000000 if BF525
408 default 400000000 if BF526
409 default 600000000 if BF527
410 default 400000000 if BF531
411 default 400000000 if BF532
412 default 750000000 if BF533
413 default 500000000 if BF534
414 default 400000000 if BF536
415 default 600000000 if BF537
416 default 533333333 if BF538
417 default 533333333 if BF539
418 default 600000000 if BF542
419 default 533333333 if BF544
420 default 600000000 if BF547
421 default 600000000 if BF548
422 default 533333333 if BF549
423 default 600000000 if BF561
437 comment "Kernel Timer/Scheduler"
439 source kernel/Kconfig.hz
445 config GENERIC_CLOCKEVENTS
446 bool "Generic clock events"
447 depends on GENERIC_TIME
450 config CYCLES_CLOCKSOURCE
451 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
452 depends on EXPERIMENTAL
453 depends on GENERIC_CLOCKEVENTS
454 depends on !BFIN_SCRATCH_REG_CYCLES
457 If you say Y here, you will enable support for using the 'cycles'
458 registers as a clock source. Doing so means you will be unable to
459 safely write to the 'cycles' register during runtime. You will
460 still be able to read it (such as for performance monitoring), but
461 writing the registers will most likely crash the kernel.
463 source kernel/time/Kconfig
465 comment "Memory Setup"
470 prompt "Blackfin Exception Scratch Register"
471 default BFIN_SCRATCH_REG_RETN
473 Select the resource to reserve for the Exception handler:
474 - RETN: Non-Maskable Interrupt (NMI)
475 - RETE: Exception Return (JTAG/ICE)
476 - CYCLES: Performance counter
478 If you are unsure, please select "RETN".
480 config BFIN_SCRATCH_REG_RETN
483 Use the RETN register in the Blackfin exception handler
484 as a stack scratch register. This means you cannot
485 safely use NMI on the Blackfin while running Linux, but
486 you can debug the system with a JTAG ICE and use the
487 CYCLES performance registers.
489 If you are unsure, please select "RETN".
491 config BFIN_SCRATCH_REG_RETE
494 Use the RETE register in the Blackfin exception handler
495 as a stack scratch register. This means you cannot
496 safely use a JTAG ICE while debugging a Blackfin board,
497 but you can safely use the CYCLES performance registers
500 If you are unsure, please select "RETN".
502 config BFIN_SCRATCH_REG_CYCLES
505 Use the CYCLES register in the Blackfin exception handler
506 as a stack scratch register. This means you cannot
507 safely use the CYCLES performance registers on a Blackfin
508 board at anytime, but you can debug the system with a JTAG
511 If you are unsure, please select "RETN".
518 menu "Blackfin Kernel Optimizations"
520 comment "Memory Optimizations"
523 bool "Locate interrupt entry code in L1 Memory"
526 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
527 into L1 instruction memory. (less latency)
529 config EXCPT_IRQ_SYSC_L1
530 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
533 If enabled, the entire ASM lowlevel exception and interrupt entry code
534 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
538 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
541 If enabled, the frequently called do_irq dispatcher function is linked
542 into L1 instruction memory. (less latency)
544 config CORE_TIMER_IRQ_L1
545 bool "Locate frequently called timer_interrupt() function in L1 Memory"
548 If enabled, the frequently called timer_interrupt() function is linked
549 into L1 instruction memory. (less latency)
552 bool "Locate frequently idle function in L1 Memory"
555 If enabled, the frequently called idle function is linked
556 into L1 instruction memory. (less latency)
559 bool "Locate kernel schedule function in L1 Memory"
562 If enabled, the frequently called kernel schedule is linked
563 into L1 instruction memory. (less latency)
565 config ARITHMETIC_OPS_L1
566 bool "Locate kernel owned arithmetic functions in L1 Memory"
569 If enabled, arithmetic functions are linked
570 into L1 instruction memory. (less latency)
573 bool "Locate access_ok function in L1 Memory"
576 If enabled, the access_ok function is linked
577 into L1 instruction memory. (less latency)
580 bool "Locate memset function in L1 Memory"
583 If enabled, the memset function is linked
584 into L1 instruction memory. (less latency)
587 bool "Locate memcpy function in L1 Memory"
590 If enabled, the memcpy function is linked
591 into L1 instruction memory. (less latency)
593 config SYS_BFIN_SPINLOCK_L1
594 bool "Locate sys_bfin_spinlock function in L1 Memory"
597 If enabled, sys_bfin_spinlock function is linked
598 into L1 instruction memory. (less latency)
600 config IP_CHECKSUM_L1
601 bool "Locate IP Checksum function in L1 Memory"
604 If enabled, the IP Checksum function is linked
605 into L1 instruction memory. (less latency)
607 config CACHELINE_ALIGNED_L1
608 bool "Locate cacheline_aligned data to L1 Data Memory"
613 If enabled, cacheline_anligned data is linked
614 into L1 data memory. (less latency)
616 config SYSCALL_TAB_L1
617 bool "Locate Syscall Table L1 Data Memory"
621 If enabled, the Syscall LUT is linked
622 into L1 data memory. (less latency)
624 config CPLB_SWITCH_TAB_L1
625 bool "Locate CPLB Switch Tables L1 Data Memory"
629 If enabled, the CPLB Switch Tables are linked
630 into L1 data memory. (less latency)
633 bool "Support locating application stack in L1 Scratch Memory"
636 If enabled the application stack can be located in L1
637 scratch memory (less latency).
639 Currently only works with FLAT binaries.
641 comment "Speed Optimizations"
642 config BFIN_INS_LOWOVERHEAD
643 bool "ins[bwl] low overhead, higher interrupt latency"
646 Reads on the Blackfin are speculative. In Blackfin terms, this means
647 they can be interrupted at any time (even after they have been issued
648 on to the external bus), and re-issued after the interrupt occurs.
649 For memory - this is not a big deal, since memory does not change if
652 If a FIFO is sitting on the end of the read, it will see two reads,
653 when the core only sees one since the FIFO receives both the read
654 which is cancelled (and not delivered to the core) and the one which
655 is re-issued (which is delivered to the core).
657 To solve this, interrupts are turned off before reads occur to
658 I/O space. This option controls which the overhead/latency of
659 controlling interrupts during this time
660 "n" turns interrupts off every read
661 (higher overhead, but lower interrupt latency)
662 "y" turns interrupts off every loop
663 (low overhead, but longer interrupt latency)
665 default behavior is to leave this set to on (type "Y"). If you are experiencing
666 interrupt latency issues, it is safe and OK to turn this off.
672 prompt "Kernel executes from"
674 Choose the memory type that the kernel will be running in.
679 The kernel will be resident in RAM when running.
684 The kernel will be resident in FLASH/ROM when running.
691 tristate "Enable Blackfin General Purpose Timers API"
694 Enable support for the General Purpose Timers API. If you
697 To compile this driver as a module, choose M here: the module
698 will be called gptimers.ko.
701 bool "Enable DMA Support"
702 depends on (BF52x || BF53x || BF561 || BF54x)
705 DMA driver for BF5xx.
708 prompt "Uncached SDRAM region"
709 default DMA_UNCACHED_1M
710 depends on BFIN_DMA_5XX
711 config DMA_UNCACHED_4M
712 bool "Enable 4M DMA region"
713 config DMA_UNCACHED_2M
714 bool "Enable 2M DMA region"
715 config DMA_UNCACHED_1M
716 bool "Enable 1M DMA region"
717 config DMA_UNCACHED_NONE
718 bool "Disable DMA region"
722 comment "Cache Support"
727 config BFIN_DCACHE_BANKA
728 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
729 depends on BFIN_DCACHE && !BF531
731 config BFIN_ICACHE_LOCK
732 bool "Enable Instruction Cache Locking"
736 depends on BFIN_DCACHE
742 Cached data will be written back to SDRAM only when needed.
743 This can give a nice increase in performance, but beware of
744 broken drivers that do not properly invalidate/flush their
747 Write Through Policy:
748 Cached data will always be written back to SDRAM when the
749 cache is updated. This is a completely safe setting, but
750 performance is worse than Write Back.
752 If you are unsure of the options and you want to be safe,
753 then go with Write Through.
759 Cached data will be written back to SDRAM only when needed.
760 This can give a nice increase in performance, but beware of
761 broken drivers that do not properly invalidate/flush their
764 Write Through Policy:
765 Cached data will always be written back to SDRAM when the
766 cache is updated. This is a completely safe setting, but
767 performance is worse than Write Back.
769 If you are unsure of the options and you want to be safe,
770 then go with Write Through.
775 bool "Enable the memory protection unit (EXPERIMENTAL)"
778 Use the processor's MPU to protect applications from accessing
779 memory they do not own. This comes at a performance penalty
780 and is recommended only for debugging.
782 comment "Asynchonous Memory Configuration"
784 menu "EBIU_AMGCTL Global Control"
790 bool "DMA has priority over core for ext. accesses"
795 bool "Bank 0 16 bit packing enable"
800 bool "Bank 1 16 bit packing enable"
805 bool "Bank 2 16 bit packing enable"
810 bool "Bank 3 16 bit packing enable"
814 prompt"Enable Asynchonous Memory Banks"
818 bool "Disable All Banks"
824 bool "Enable Bank 0 & 1"
826 config C_AMBEN_B0_B1_B2
827 bool "Enable Bank 0 & 1 & 2"
830 bool "Enable All Banks"
834 menu "EBIU_AMBCTL Control"
842 default 0x5558 if BF54x
853 config EBIU_MBSCTLVAL
854 hex "EBIU Bank Select Control Register"
859 hex "Flash Memory Mode Control Register"
864 hex "Flash Memory Bank Control Register"
869 #############################################################################
870 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
878 source "drivers/pci/Kconfig"
881 bool "Support for hot-pluggable device"
883 Say Y here if you want to plug devices into your computer while
884 the system is running, and be able to use them quickly. In many
885 cases, the devices can likewise be unplugged at any time too.
887 One well known example of this is PCMCIA- or PC-cards, credit-card
888 size devices such as network cards, modems or hard drives which are
889 plugged into slots found on all modern laptop computers. Another
890 example, used on modern desktops as well as laptops, is USB.
892 Enable HOTPLUG and build a modular kernel. Get agent software
893 (from <http://linux-hotplug.sourceforge.net/>) and install it.
894 Then your kernel will automatically call out to a user mode "policy
895 agent" (/sbin/hotplug) to load modules and set up software needed
896 to use devices as you hotplug them.
898 source "drivers/pcmcia/Kconfig"
900 source "drivers/pci/hotplug/Kconfig"
904 menu "Executable file formats"
906 source "fs/Kconfig.binfmt"
910 menu "Power management options"
911 source "kernel/power/Kconfig"
913 config ARCH_SUSPEND_POSSIBLE
918 prompt "Standby Power Saving Mode"
920 default PM_BFIN_SLEEP_DEEPER
921 config PM_BFIN_SLEEP_DEEPER
924 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
925 power dissipation by disabling the clock to the processor core (CCLK).
926 Furthermore, Standby sets the internal power supply voltage (VDDINT)
927 to 0.85 V to provide the greatest power savings, while preserving the
929 The PLL and system clock (SCLK) continue to operate at a very low
930 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
931 the SDRAM is put into Self Refresh Mode. Typically an external event
932 such as GPIO interrupt or RTC activity wakes up the processor.
933 Various Peripherals such as UART, SPORT, PPI may not function as
934 normal during Sleep Deeper, due to the reduced SCLK frequency.
935 When in the sleep mode, system DMA access to L1 memory is not supported.
937 If unsure, select "Sleep Deeper".
942 Sleep Mode (High Power Savings) - The sleep mode reduces power
943 dissipation by disabling the clock to the processor core (CCLK).
944 The PLL and system clock (SCLK), however, continue to operate in
945 this mode. Typically an external event or RTC activity will wake
946 up the processor. When in the sleep mode, system DMA access to L1
947 memory is not supported.
949 If unsure, select "Sleep Deeper".
952 config PM_WAKEUP_BY_GPIO
953 bool "Allow Wakeup from Standby by GPIO"
955 config PM_WAKEUP_GPIO_NUMBER
958 depends on PM_WAKEUP_BY_GPIO
959 default 2 if BFIN537_STAMP
962 prompt "GPIO Polarity"
963 depends on PM_WAKEUP_BY_GPIO
964 default PM_WAKEUP_GPIO_POLAR_H
965 config PM_WAKEUP_GPIO_POLAR_H
967 config PM_WAKEUP_GPIO_POLAR_L
969 config PM_WAKEUP_GPIO_POLAR_EDGE_F
971 config PM_WAKEUP_GPIO_POLAR_EDGE_R
973 config PM_WAKEUP_GPIO_POLAR_EDGE_B
977 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
980 config PM_BFIN_WAKE_PH6
981 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
982 depends on PM && (BF52x || BF534 || BF536 || BF537)
985 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
987 config PM_BFIN_WAKE_GP
988 bool "Allow Wake-Up from GPIOs"
989 depends on PM && BF54x
992 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
995 menu "CPU Frequency scaling"
997 source "drivers/cpufreq/Kconfig"
1000 bool "CPU Voltage scaling"
1001 depends on EXPERIMENTAL
1005 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1006 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1007 manuals. There is a theoretical risk that during VDDINT transitions
1012 source "net/Kconfig"
1014 source "drivers/Kconfig"
1018 source "arch/blackfin/Kconfig.debug"
1020 source "security/Kconfig"
1022 source "crypto/Kconfig"
1024 source "lib/Kconfig"