2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
14 config RWSEM_GENERIC_SPINLOCK
17 config RWSEM_XCHGADD_ALGORITHM
22 select HAVE_FUNCTION_GRAPH_TRACER
23 select HAVE_FUNCTION_TRACER
25 select HAVE_KERNEL_GZIP
26 select HAVE_KERNEL_BZIP2
27 select HAVE_KERNEL_LZMA
29 select ARCH_WANT_OPTIONAL_GPIOLIB
41 config GENERIC_FIND_NEXT_BIT
44 config GENERIC_HWEIGHT
47 config GENERIC_HARDIRQS
50 config GENERIC_IRQ_PROBE
53 config GENERIC_HARDIRQS_NO__DO_IRQ
59 config FORCE_MAX_ZONEORDER
63 config GENERIC_CALIBRATE_DELAY
66 config LOCKDEP_SUPPORT
69 config STACKTRACE_SUPPORT
72 config TRACE_IRQFLAGS_SUPPORT
77 source "kernel/Kconfig.preempt"
79 source "kernel/Kconfig.freezer"
81 menu "Blackfin Processor Options"
83 comment "Processor and Board Settings"
92 BF512 Processor Support.
97 BF514 Processor Support.
102 BF516 Processor Support.
107 BF518 Processor Support.
112 BF522 Processor Support.
117 BF523 Processor Support.
122 BF524 Processor Support.
127 BF525 Processor Support.
132 BF526 Processor Support.
137 BF527 Processor Support.
142 BF531 Processor Support.
147 BF532 Processor Support.
152 BF533 Processor Support.
157 BF534 Processor Support.
162 BF536 Processor Support.
167 BF537 Processor Support.
172 BF538 Processor Support.
177 BF539 Processor Support.
182 BF542 Processor Support.
187 BF542 Processor Support.
192 BF544 Processor Support.
197 BF544 Processor Support.
202 BF547 Processor Support.
207 BF547 Processor Support.
212 BF548 Processor Support.
217 BF548 Processor Support.
222 BF549 Processor Support.
227 BF549 Processor Support.
232 BF561 Processor Support.
238 select GENERIC_CLOCKEVENTS
239 bool "Symmetric multi-processing support"
241 This enables support for systems with more than one CPU,
242 like the dual core BF561. If you have a system with only one
243 CPU, say N. If you have a system with more than one CPU, say Y.
245 If you don't know what to do here, say N.
259 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
260 default 2 if (BF537 || BF536 || BF534)
261 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
262 default 4 if (BF538 || BF539)
266 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
267 default 3 if (BF537 || BF536 || BF534 || BF54xM)
268 default 5 if (BF561 || BF538 || BF539)
269 default 6 if (BF533 || BF532 || BF531)
273 default BF_REV_0_0 if (BF51x || BF52x)
274 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
275 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
279 depends on (BF51x || BF52x || (BF54x && !BF54xM))
283 depends on (BF51x || BF52x || (BF54x && !BF54xM))
287 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
291 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
295 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
299 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
303 depends on (BF533 || BF532 || BF531)
315 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
318 config MEM_GENERIC_BOARD
320 depends on GENERIC_BOARD
323 config MEM_MT48LC64M4A2FB_7E
325 depends on (BFIN533_STAMP)
328 config MEM_MT48LC16M16A2TG_75
330 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
331 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
332 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
333 || BFIN527_BLUETECHNIX_CM)
336 config MEM_MT48LC32M8A2_75
338 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
341 config MEM_MT48LC8M32B2B5_7
343 depends on (BFIN561_BLUETECHNIX_CM)
346 config MEM_MT48LC32M16A2TG_75
348 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
351 config MEM_MT48LC32M8A2_75
353 depends on (BFIN518F_EZBRD)
356 config MEM_MT48H32M16LFCJ_75
358 depends on (BFIN526_EZBRD)
361 source "arch/blackfin/mach-bf518/Kconfig"
362 source "arch/blackfin/mach-bf527/Kconfig"
363 source "arch/blackfin/mach-bf533/Kconfig"
364 source "arch/blackfin/mach-bf561/Kconfig"
365 source "arch/blackfin/mach-bf537/Kconfig"
366 source "arch/blackfin/mach-bf538/Kconfig"
367 source "arch/blackfin/mach-bf548/Kconfig"
369 menu "Board customizations"
372 bool "Default bootloader kernel arguments"
375 string "Initial kernel command string"
376 depends on CMDLINE_BOOL
377 default "console=ttyBF0,57600"
379 If you don't have a boot loader capable of passing a command line string
380 to the kernel, you may specify one here. As a minimum, you should specify
381 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
384 hex "Kernel load address for booting"
386 range 0x1000 0x20000000
388 This option allows you to set the load address of the kernel.
389 This can be useful if you are on a board which has a small amount
390 of memory or you wish to reserve some memory at the beginning of
393 Note that you need to keep this value above 4k (0x1000) as this
394 memory region is used to capture NULL pointer references as well
395 as some core kernel functions.
398 hex "Kernel ROM Base"
401 range 0x20000000 0x20400000 if !(BF54x || BF561)
402 range 0x20000000 0x30000000 if (BF54x || BF561)
405 comment "Clock/PLL Setup"
408 int "Frequency of the crystal on the board in Hz"
409 default "10000000" if BFIN532_IP0X
410 default "11059200" if BFIN533_STAMP
411 default "24576000" if PNAV10
412 default "25000000" # most people use this
413 default "27000000" if BFIN533_EZKIT
414 default "30000000" if BFIN561_EZKIT
416 The frequency of CLKIN crystal oscillator on the board in Hz.
417 Warning: This value should match the crystal on the board. Otherwise,
418 peripherals won't work properly.
420 config BFIN_KERNEL_CLOCK
421 bool "Re-program Clocks while Kernel boots?"
424 This option decides if kernel clocks are re-programed from the
425 bootloader settings. If the clocks are not set, the SDRAM settings
426 are also not changed, and the Bootloader does 100% of the hardware
431 depends on BFIN_KERNEL_CLOCK
436 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
439 If this is set the clock will be divided by 2, before it goes to the PLL.
443 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
445 default "22" if BFIN533_EZKIT
446 default "45" if BFIN533_STAMP
447 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
448 default "22" if BFIN533_BLUETECHNIX_CM
449 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
450 default "20" if BFIN561_EZKIT
451 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
453 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
454 PLL Frequency = (Crystal Frequency) * (this setting)
457 prompt "Core Clock Divider"
458 depends on BFIN_KERNEL_CLOCK
461 This sets the frequency of the core. It can be 1, 2, 4 or 8
462 Core Frequency = (PLL frequency) / (this setting)
478 int "System Clock Divider"
479 depends on BFIN_KERNEL_CLOCK
483 This sets the frequency of the system clock (including SDRAM or DDR).
484 This can be between 1 and 15
485 System Clock = (PLL frequency) / (this setting)
488 prompt "DDR SDRAM Chip Type"
489 depends on BFIN_KERNEL_CLOCK
491 default MEM_MT46V32M16_5B
493 config MEM_MT46V32M16_6T
496 config MEM_MT46V32M16_5B
501 prompt "DDR/SDRAM Timing"
502 depends on BFIN_KERNEL_CLOCK
503 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
505 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
506 The calculated SDRAM timing parameters may not be 100%
507 accurate - This option is therefore marked experimental.
509 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
510 bool "Calculate Timings (EXPERIMENTAL)"
511 depends on EXPERIMENTAL
513 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
514 bool "Provide accurate Timings based on target SCLK"
516 Please consult the Blackfin Hardware Reference Manuals as well
517 as the memory device datasheet.
518 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
521 menu "Memory Init Control"
522 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
539 config MEM_EBIU_DDRQUE
556 # Max & Min Speeds for various Chips
560 default 400000000 if BF512
561 default 400000000 if BF514
562 default 400000000 if BF516
563 default 400000000 if BF518
564 default 400000000 if BF522
565 default 600000000 if BF523
566 default 400000000 if BF524
567 default 600000000 if BF525
568 default 400000000 if BF526
569 default 600000000 if BF527
570 default 400000000 if BF531
571 default 400000000 if BF532
572 default 750000000 if BF533
573 default 500000000 if BF534
574 default 400000000 if BF536
575 default 600000000 if BF537
576 default 533333333 if BF538
577 default 533333333 if BF539
578 default 600000000 if BF542
579 default 533333333 if BF544
580 default 600000000 if BF547
581 default 600000000 if BF548
582 default 533333333 if BF549
583 default 600000000 if BF561
597 comment "Kernel Timer/Scheduler"
599 source kernel/Kconfig.hz
604 config GENERIC_CLOCKEVENTS
605 bool "Generic clock events"
609 prompt "Kernel Tick Source"
610 depends on GENERIC_CLOCKEVENTS
611 default TICKSOURCE_CORETMR
613 config TICKSOURCE_GPTMR0
614 bool "Gptimer0 (SCLK domain)"
617 config TICKSOURCE_CORETMR
618 bool "Core timer (CCLK domain)"
622 config CYCLES_CLOCKSOURCE
623 bool "Use 'CYCLES' as a clocksource"
624 depends on GENERIC_CLOCKEVENTS
625 depends on !BFIN_SCRATCH_REG_CYCLES
628 If you say Y here, you will enable support for using the 'cycles'
629 registers as a clock source. Doing so means you will be unable to
630 safely write to the 'cycles' register during runtime. You will
631 still be able to read it (such as for performance monitoring), but
632 writing the registers will most likely crash the kernel.
634 config GPTMR0_CLOCKSOURCE
635 bool "Use GPTimer0 as a clocksource"
637 depends on GENERIC_CLOCKEVENTS
638 depends on !TICKSOURCE_GPTMR0
640 config ARCH_USES_GETTIMEOFFSET
641 depends on !GENERIC_CLOCKEVENTS
644 source kernel/time/Kconfig
649 prompt "Blackfin Exception Scratch Register"
650 default BFIN_SCRATCH_REG_RETN
652 Select the resource to reserve for the Exception handler:
653 - RETN: Non-Maskable Interrupt (NMI)
654 - RETE: Exception Return (JTAG/ICE)
655 - CYCLES: Performance counter
657 If you are unsure, please select "RETN".
659 config BFIN_SCRATCH_REG_RETN
662 Use the RETN register in the Blackfin exception handler
663 as a stack scratch register. This means you cannot
664 safely use NMI on the Blackfin while running Linux, but
665 you can debug the system with a JTAG ICE and use the
666 CYCLES performance registers.
668 If you are unsure, please select "RETN".
670 config BFIN_SCRATCH_REG_RETE
673 Use the RETE register in the Blackfin exception handler
674 as a stack scratch register. This means you cannot
675 safely use a JTAG ICE while debugging a Blackfin board,
676 but you can safely use the CYCLES performance registers
679 If you are unsure, please select "RETN".
681 config BFIN_SCRATCH_REG_CYCLES
684 Use the CYCLES register in the Blackfin exception handler
685 as a stack scratch register. This means you cannot
686 safely use the CYCLES performance registers on a Blackfin
687 board at anytime, but you can debug the system with a JTAG
690 If you are unsure, please select "RETN".
697 menu "Blackfin Kernel Optimizations"
700 comment "Memory Optimizations"
703 bool "Locate interrupt entry code in L1 Memory"
706 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
707 into L1 instruction memory. (less latency)
709 config EXCPT_IRQ_SYSC_L1
710 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
713 If enabled, the entire ASM lowlevel exception and interrupt entry code
714 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
718 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
721 If enabled, the frequently called do_irq dispatcher function is linked
722 into L1 instruction memory. (less latency)
724 config CORE_TIMER_IRQ_L1
725 bool "Locate frequently called timer_interrupt() function in L1 Memory"
728 If enabled, the frequently called timer_interrupt() function is linked
729 into L1 instruction memory. (less latency)
732 bool "Locate frequently idle function in L1 Memory"
735 If enabled, the frequently called idle function is linked
736 into L1 instruction memory. (less latency)
739 bool "Locate kernel schedule function in L1 Memory"
742 If enabled, the frequently called kernel schedule is linked
743 into L1 instruction memory. (less latency)
745 config ARITHMETIC_OPS_L1
746 bool "Locate kernel owned arithmetic functions in L1 Memory"
749 If enabled, arithmetic functions are linked
750 into L1 instruction memory. (less latency)
753 bool "Locate access_ok function in L1 Memory"
756 If enabled, the access_ok function is linked
757 into L1 instruction memory. (less latency)
760 bool "Locate memset function in L1 Memory"
763 If enabled, the memset function is linked
764 into L1 instruction memory. (less latency)
767 bool "Locate memcpy function in L1 Memory"
770 If enabled, the memcpy function is linked
771 into L1 instruction memory. (less latency)
773 config SYS_BFIN_SPINLOCK_L1
774 bool "Locate sys_bfin_spinlock function in L1 Memory"
777 If enabled, sys_bfin_spinlock function is linked
778 into L1 instruction memory. (less latency)
780 config IP_CHECKSUM_L1
781 bool "Locate IP Checksum function in L1 Memory"
784 If enabled, the IP Checksum function is linked
785 into L1 instruction memory. (less latency)
787 config CACHELINE_ALIGNED_L1
788 bool "Locate cacheline_aligned data to L1 Data Memory"
793 If enabled, cacheline_aligned data is linked
794 into L1 data memory. (less latency)
796 config SYSCALL_TAB_L1
797 bool "Locate Syscall Table L1 Data Memory"
801 If enabled, the Syscall LUT is linked
802 into L1 data memory. (less latency)
804 config CPLB_SWITCH_TAB_L1
805 bool "Locate CPLB Switch Tables L1 Data Memory"
809 If enabled, the CPLB Switch Tables are linked
810 into L1 data memory. (less latency)
813 bool "Support locating application stack in L1 Scratch Memory"
816 If enabled the application stack can be located in L1
817 scratch memory (less latency).
819 Currently only works with FLAT binaries.
821 config EXCEPTION_L1_SCRATCH
822 bool "Locate exception stack in L1 Scratch Memory"
824 depends on !APP_STACK_L1
826 Whenever an exception occurs, use the L1 Scratch memory for
827 stack storage. You cannot place the stacks of FLAT binaries
828 in L1 when using this option.
830 If you don't use L1 Scratch, then you should say Y here.
832 comment "Speed Optimizations"
833 config BFIN_INS_LOWOVERHEAD
834 bool "ins[bwl] low overhead, higher interrupt latency"
837 Reads on the Blackfin are speculative. In Blackfin terms, this means
838 they can be interrupted at any time (even after they have been issued
839 on to the external bus), and re-issued after the interrupt occurs.
840 For memory - this is not a big deal, since memory does not change if
843 If a FIFO is sitting on the end of the read, it will see two reads,
844 when the core only sees one since the FIFO receives both the read
845 which is cancelled (and not delivered to the core) and the one which
846 is re-issued (which is delivered to the core).
848 To solve this, interrupts are turned off before reads occur to
849 I/O space. This option controls which the overhead/latency of
850 controlling interrupts during this time
851 "n" turns interrupts off every read
852 (higher overhead, but lower interrupt latency)
853 "y" turns interrupts off every loop
854 (low overhead, but longer interrupt latency)
856 default behavior is to leave this set to on (type "Y"). If you are experiencing
857 interrupt latency issues, it is safe and OK to turn this off.
862 prompt "Kernel executes from"
864 Choose the memory type that the kernel will be running in.
869 The kernel will be resident in RAM when running.
874 The kernel will be resident in FLASH/ROM when running.
881 tristate "Enable Blackfin General Purpose Timers API"
884 Enable support for the General Purpose Timers API. If you
887 To compile this driver as a module, choose M here: the module
888 will be called gptimers.
891 prompt "Uncached DMA region"
892 default DMA_UNCACHED_1M
893 config DMA_UNCACHED_4M
894 bool "Enable 4M DMA region"
895 config DMA_UNCACHED_2M
896 bool "Enable 2M DMA region"
897 config DMA_UNCACHED_1M
898 bool "Enable 1M DMA region"
899 config DMA_UNCACHED_512K
900 bool "Enable 512K DMA region"
901 config DMA_UNCACHED_256K
902 bool "Enable 256K DMA region"
903 config DMA_UNCACHED_128K
904 bool "Enable 128K DMA region"
905 config DMA_UNCACHED_NONE
906 bool "Disable DMA region"
910 comment "Cache Support"
915 config BFIN_EXTMEM_ICACHEABLE
916 bool "Enable ICACHE for external memory"
917 depends on BFIN_ICACHE
919 config BFIN_L2_ICACHEABLE
920 bool "Enable ICACHE for L2 SRAM"
921 depends on BFIN_ICACHE
922 depends on BF54x || BF561
928 config BFIN_DCACHE_BANKA
929 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
930 depends on BFIN_DCACHE && !BF531
932 config BFIN_EXTMEM_DCACHEABLE
933 bool "Enable DCACHE for external memory"
934 depends on BFIN_DCACHE
937 prompt "External memory DCACHE policy"
938 depends on BFIN_EXTMEM_DCACHEABLE
939 default BFIN_EXTMEM_WRITEBACK if !SMP
940 default BFIN_EXTMEM_WRITETHROUGH if SMP
941 config BFIN_EXTMEM_WRITEBACK
946 Cached data will be written back to SDRAM only when needed.
947 This can give a nice increase in performance, but beware of
948 broken drivers that do not properly invalidate/flush their
951 Write Through Policy:
952 Cached data will always be written back to SDRAM when the
953 cache is updated. This is a completely safe setting, but
954 performance is worse than Write Back.
956 If you are unsure of the options and you want to be safe,
957 then go with Write Through.
959 config BFIN_EXTMEM_WRITETHROUGH
963 Cached data will be written back to SDRAM only when needed.
964 This can give a nice increase in performance, but beware of
965 broken drivers that do not properly invalidate/flush their
968 Write Through Policy:
969 Cached data will always be written back to SDRAM when the
970 cache is updated. This is a completely safe setting, but
971 performance is worse than Write Back.
973 If you are unsure of the options and you want to be safe,
974 then go with Write Through.
978 config BFIN_L2_DCACHEABLE
979 bool "Enable DCACHE for L2 SRAM"
980 depends on BFIN_DCACHE
981 depends on (BF54x || BF561) && !SMP
984 prompt "L2 SRAM DCACHE policy"
985 depends on BFIN_L2_DCACHEABLE
986 default BFIN_L2_WRITEBACK
987 config BFIN_L2_WRITEBACK
990 config BFIN_L2_WRITETHROUGH
995 comment "Memory Protection Unit"
997 bool "Enable the memory protection unit (EXPERIMENTAL)"
1000 Use the processor's MPU to protect applications from accessing
1001 memory they do not own. This comes at a performance penalty
1002 and is recommended only for debugging.
1004 comment "Asynchronous Memory Configuration"
1006 menu "EBIU_AMGCTL Global Control"
1008 bool "Enable CLKOUT"
1012 bool "DMA has priority over core for ext. accesses"
1017 bool "Bank 0 16 bit packing enable"
1022 bool "Bank 1 16 bit packing enable"
1027 bool "Bank 2 16 bit packing enable"
1032 bool "Bank 3 16 bit packing enable"
1036 prompt "Enable Asynchronous Memory Banks"
1040 bool "Disable All Banks"
1043 bool "Enable Bank 0"
1045 config C_AMBEN_B0_B1
1046 bool "Enable Bank 0 & 1"
1048 config C_AMBEN_B0_B1_B2
1049 bool "Enable Bank 0 & 1 & 2"
1052 bool "Enable All Banks"
1056 menu "EBIU_AMBCTL Control"
1058 hex "Bank 0 (AMBCTL0.L)"
1061 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1062 used to control the Asynchronous Memory Bank 0 settings.
1065 hex "Bank 1 (AMBCTL0.H)"
1067 default 0x5558 if BF54x
1069 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1070 used to control the Asynchronous Memory Bank 1 settings.
1073 hex "Bank 2 (AMBCTL1.L)"
1076 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1077 used to control the Asynchronous Memory Bank 2 settings.
1080 hex "Bank 3 (AMBCTL1.H)"
1083 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1084 used to control the Asynchronous Memory Bank 3 settings.
1088 config EBIU_MBSCTLVAL
1089 hex "EBIU Bank Select Control Register"
1094 hex "Flash Memory Mode Control Register"
1099 hex "Flash Memory Bank Control Register"
1104 #############################################################################
1105 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1111 Support for PCI bus.
1113 source "drivers/pci/Kconfig"
1116 bool "Support for hot-pluggable device"
1118 Say Y here if you want to plug devices into your computer while
1119 the system is running, and be able to use them quickly. In many
1120 cases, the devices can likewise be unplugged at any time too.
1122 One well known example of this is PCMCIA- or PC-cards, credit-card
1123 size devices such as network cards, modems or hard drives which are
1124 plugged into slots found on all modern laptop computers. Another
1125 example, used on modern desktops as well as laptops, is USB.
1127 Enable HOTPLUG and build a modular kernel. Get agent software
1128 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1129 Then your kernel will automatically call out to a user mode "policy
1130 agent" (/sbin/hotplug) to load modules and set up software needed
1131 to use devices as you hotplug them.
1133 source "drivers/pcmcia/Kconfig"
1135 source "drivers/pci/hotplug/Kconfig"
1139 menu "Executable file formats"
1141 source "fs/Kconfig.binfmt"
1145 menu "Power management options"
1148 source "kernel/power/Kconfig"
1150 config ARCH_SUSPEND_POSSIBLE
1154 prompt "Standby Power Saving Mode"
1156 default PM_BFIN_SLEEP_DEEPER
1157 config PM_BFIN_SLEEP_DEEPER
1160 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1161 power dissipation by disabling the clock to the processor core (CCLK).
1162 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1163 to 0.85 V to provide the greatest power savings, while preserving the
1165 The PLL and system clock (SCLK) continue to operate at a very low
1166 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1167 the SDRAM is put into Self Refresh Mode. Typically an external event
1168 such as GPIO interrupt or RTC activity wakes up the processor.
1169 Various Peripherals such as UART, SPORT, PPI may not function as
1170 normal during Sleep Deeper, due to the reduced SCLK frequency.
1171 When in the sleep mode, system DMA access to L1 memory is not supported.
1173 If unsure, select "Sleep Deeper".
1175 config PM_BFIN_SLEEP
1178 Sleep Mode (High Power Savings) - The sleep mode reduces power
1179 dissipation by disabling the clock to the processor core (CCLK).
1180 The PLL and system clock (SCLK), however, continue to operate in
1181 this mode. Typically an external event or RTC activity will wake
1182 up the processor. When in the sleep mode, system DMA access to L1
1183 memory is not supported.
1185 If unsure, select "Sleep Deeper".
1188 config PM_WAKEUP_BY_GPIO
1189 bool "Allow Wakeup from Standby by GPIO"
1190 depends on PM && !BF54x
1192 config PM_WAKEUP_GPIO_NUMBER
1195 depends on PM_WAKEUP_BY_GPIO
1199 prompt "GPIO Polarity"
1200 depends on PM_WAKEUP_BY_GPIO
1201 default PM_WAKEUP_GPIO_POLAR_H
1202 config PM_WAKEUP_GPIO_POLAR_H
1204 config PM_WAKEUP_GPIO_POLAR_L
1206 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1208 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1210 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1214 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1217 config PM_BFIN_WAKE_PH6
1218 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1219 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1222 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1224 config PM_BFIN_WAKE_GP
1225 bool "Allow Wake-Up from GPIOs"
1226 depends on PM && BF54x
1229 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1230 (all processors, except ADSP-BF549). This option sets
1231 the general-purpose wake-up enable (GPWE) control bit to enable
1232 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1233 On ADSP-BF549 this option enables the the same functionality on the
1234 /MRXON pin also PH7.
1238 menu "CPU Frequency scaling"
1241 source "drivers/cpufreq/Kconfig"
1243 config BFIN_CPU_FREQ
1246 select CPU_FREQ_TABLE
1250 bool "CPU Voltage scaling"
1251 depends on EXPERIMENTAL
1255 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1256 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1257 manuals. There is a theoretical risk that during VDDINT transitions
1262 source "net/Kconfig"
1264 source "drivers/Kconfig"
1266 source "drivers/firmware/Kconfig"
1270 source "arch/blackfin/Kconfig.debug"
1272 source "security/Kconfig"
1274 source "crypto/Kconfig"
1276 source "lib/Kconfig"