2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
14 #include <asm/arch/board.h>
15 #include <asm/arch/portmux.h>
16 #include <asm/arch/sm.h>
25 .end = base + 0x3ff, \
26 .flags = IORESOURCE_MEM, \
32 .flags = IORESOURCE_IRQ, \
34 #define NAMED_IRQ(num, _name) \
39 .flags = IORESOURCE_IRQ, \
42 #define DEFINE_DEV(_name, _id) \
43 static struct platform_device _name##_id##_device = { \
46 .resource = _name##_id##_resource, \
47 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
49 #define DEFINE_DEV_DATA(_name, _id) \
50 static struct platform_device _name##_id##_device = { \
54 .platform_data = &_name##_id##_data, \
56 .resource = _name##_id##_resource, \
57 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
60 #define DEV_CLK(_name, devname, bus, _index) \
61 static struct clk devname##_##_name = { \
63 .dev = &devname##_device.dev, \
64 .parent = &bus##_clk, \
65 .mode = bus##_clk_mode, \
66 .get_rate = bus##_clk_get_rate, \
82 unsigned long at32ap7000_osc_rates[3] = {
84 /* FIXME: these are ATSTK1002-specific */
89 static unsigned long osc_get_rate(struct clk *clk)
91 return at32ap7000_osc_rates[clk->index];
94 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
96 unsigned long div, mul, rate;
98 if (!(control & SM_BIT(PLLEN)))
101 div = SM_BFEXT(PLLDIV, control) + 1;
102 mul = SM_BFEXT(PLLMUL, control) + 1;
104 rate = clk->parent->get_rate(clk->parent);
105 rate = (rate + div / 2) / div;
111 static unsigned long pll0_get_rate(struct clk *clk)
115 control = sm_readl(&system_manager, PM_PLL0);
117 return pll_get_rate(clk, control);
120 static unsigned long pll1_get_rate(struct clk *clk)
124 control = sm_readl(&system_manager, PM_PLL1);
126 return pll_get_rate(clk, control);
130 * The AT32AP7000 has five primary clock sources: One 32kHz
131 * oscillator, two crystal oscillators and two PLLs.
133 static struct clk osc32k = {
135 .get_rate = osc_get_rate,
139 static struct clk osc0 = {
141 .get_rate = osc_get_rate,
145 static struct clk osc1 = {
147 .get_rate = osc_get_rate,
150 static struct clk pll0 = {
152 .get_rate = pll0_get_rate,
155 static struct clk pll1 = {
157 .get_rate = pll1_get_rate,
162 * The main clock can be either osc0 or pll0. The boot loader may
163 * have chosen one for us, so we don't really know which one until we
164 * have a look at the SM.
166 static struct clk *main_clock;
169 * Synchronous clocks are generated from the main clock. The clocks
170 * must satisfy the constraint
171 * fCPU >= fHSB >= fPB
172 * i.e. each clock must not be faster than its parent.
174 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
176 return main_clock->get_rate(main_clock) >> shift;
179 static void cpu_clk_mode(struct clk *clk, int enabled)
181 struct at32_sm *sm = &system_manager;
185 spin_lock_irqsave(&sm->lock, flags);
186 mask = sm_readl(sm, PM_CPU_MASK);
188 mask |= 1 << clk->index;
190 mask &= ~(1 << clk->index);
191 sm_writel(sm, PM_CPU_MASK, mask);
192 spin_unlock_irqrestore(&sm->lock, flags);
195 static unsigned long cpu_clk_get_rate(struct clk *clk)
197 unsigned long cksel, shift = 0;
199 cksel = sm_readl(&system_manager, PM_CKSEL);
200 if (cksel & SM_BIT(CPUDIV))
201 shift = SM_BFEXT(CPUSEL, cksel) + 1;
203 return bus_clk_get_rate(clk, shift);
206 static void hsb_clk_mode(struct clk *clk, int enabled)
208 struct at32_sm *sm = &system_manager;
212 spin_lock_irqsave(&sm->lock, flags);
213 mask = sm_readl(sm, PM_HSB_MASK);
215 mask |= 1 << clk->index;
217 mask &= ~(1 << clk->index);
218 sm_writel(sm, PM_HSB_MASK, mask);
219 spin_unlock_irqrestore(&sm->lock, flags);
222 static unsigned long hsb_clk_get_rate(struct clk *clk)
224 unsigned long cksel, shift = 0;
226 cksel = sm_readl(&system_manager, PM_CKSEL);
227 if (cksel & SM_BIT(HSBDIV))
228 shift = SM_BFEXT(HSBSEL, cksel) + 1;
230 return bus_clk_get_rate(clk, shift);
233 static void pba_clk_mode(struct clk *clk, int enabled)
235 struct at32_sm *sm = &system_manager;
239 spin_lock_irqsave(&sm->lock, flags);
240 mask = sm_readl(sm, PM_PBA_MASK);
242 mask |= 1 << clk->index;
244 mask &= ~(1 << clk->index);
245 sm_writel(sm, PM_PBA_MASK, mask);
246 spin_unlock_irqrestore(&sm->lock, flags);
249 static unsigned long pba_clk_get_rate(struct clk *clk)
251 unsigned long cksel, shift = 0;
253 cksel = sm_readl(&system_manager, PM_CKSEL);
254 if (cksel & SM_BIT(PBADIV))
255 shift = SM_BFEXT(PBASEL, cksel) + 1;
257 return bus_clk_get_rate(clk, shift);
260 static void pbb_clk_mode(struct clk *clk, int enabled)
262 struct at32_sm *sm = &system_manager;
266 spin_lock_irqsave(&sm->lock, flags);
267 mask = sm_readl(sm, PM_PBB_MASK);
269 mask |= 1 << clk->index;
271 mask &= ~(1 << clk->index);
272 sm_writel(sm, PM_PBB_MASK, mask);
273 spin_unlock_irqrestore(&sm->lock, flags);
276 static unsigned long pbb_clk_get_rate(struct clk *clk)
278 unsigned long cksel, shift = 0;
280 cksel = sm_readl(&system_manager, PM_CKSEL);
281 if (cksel & SM_BIT(PBBDIV))
282 shift = SM_BFEXT(PBBSEL, cksel) + 1;
284 return bus_clk_get_rate(clk, shift);
287 static struct clk cpu_clk = {
289 .get_rate = cpu_clk_get_rate,
292 static struct clk hsb_clk = {
295 .get_rate = hsb_clk_get_rate,
297 static struct clk pba_clk = {
300 .mode = hsb_clk_mode,
301 .get_rate = pba_clk_get_rate,
304 static struct clk pbb_clk = {
307 .mode = hsb_clk_mode,
308 .get_rate = pbb_clk_get_rate,
313 /* --------------------------------------------------------------------
314 * Generic Clock operations
315 * -------------------------------------------------------------------- */
317 static void genclk_mode(struct clk *clk, int enabled)
321 BUG_ON(clk->index > 7);
323 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
325 control |= SM_BIT(CEN);
327 control &= ~SM_BIT(CEN);
328 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
331 static unsigned long genclk_get_rate(struct clk *clk)
334 unsigned long div = 1;
336 BUG_ON(clk->index > 7);
341 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
342 if (control & SM_BIT(DIVEN))
343 div = 2 * (SM_BFEXT(DIV, control) + 1);
345 return clk->parent->get_rate(clk->parent) / div;
348 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
351 unsigned long parent_rate, actual_rate, div;
353 BUG_ON(clk->index > 7);
358 parent_rate = clk->parent->get_rate(clk->parent);
359 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
361 if (rate > 3 * parent_rate / 4) {
362 actual_rate = parent_rate;
363 control &= ~SM_BIT(DIVEN);
365 div = (parent_rate + rate) / (2 * rate) - 1;
366 control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
367 actual_rate = parent_rate / (2 * (div + 1));
370 printk("clk %s: new rate %lu (actual rate %lu)\n",
371 clk->name, rate, actual_rate);
374 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
380 int genclk_set_parent(struct clk *clk, struct clk *parent)
384 BUG_ON(clk->index > 7);
386 printk("clk %s: new parent %s (was %s)\n",
387 clk->name, parent->name,
388 clk->parent ? clk->parent->name : "(null)");
390 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
392 if (parent == &osc1 || parent == &pll1)
393 control |= SM_BIT(OSCSEL);
394 else if (parent == &osc0 || parent == &pll0)
395 control &= ~SM_BIT(OSCSEL);
399 if (parent == &pll0 || parent == &pll1)
400 control |= SM_BIT(PLLSEL);
402 control &= ~SM_BIT(PLLSEL);
404 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
405 clk->parent = parent;
410 /* --------------------------------------------------------------------
412 * -------------------------------------------------------------------- */
413 static struct resource sm_resource[] = {
415 NAMED_IRQ(19, "eim"),
417 NAMED_IRQ(21, "rtc"),
419 struct platform_device at32_sm_device = {
422 .resource = sm_resource,
423 .num_resources = ARRAY_SIZE(sm_resource),
425 DEV_CLK(pclk, at32_sm, pbb, 0);
427 static struct resource intc0_resource[] = {
430 struct platform_device at32_intc0_device = {
433 .resource = intc0_resource,
434 .num_resources = ARRAY_SIZE(intc0_resource),
436 DEV_CLK(pclk, at32_intc0, pbb, 1);
438 static struct clk ebi_clk = {
441 .mode = hsb_clk_mode,
442 .get_rate = hsb_clk_get_rate,
445 static struct clk hramc_clk = {
448 .mode = hsb_clk_mode,
449 .get_rate = hsb_clk_get_rate,
453 static struct platform_device pdc_device = {
457 DEV_CLK(hclk, pdc, hsb, 4);
458 DEV_CLK(pclk, pdc, pba, 16);
460 static struct clk pico_clk = {
463 .mode = cpu_clk_mode,
464 .get_rate = cpu_clk_get_rate,
468 /* --------------------------------------------------------------------
470 * -------------------------------------------------------------------- */
472 static struct resource pio0_resource[] = {
477 DEV_CLK(mck, pio0, pba, 10);
479 static struct resource pio1_resource[] = {
484 DEV_CLK(mck, pio1, pba, 11);
486 static struct resource pio2_resource[] = {
491 DEV_CLK(mck, pio2, pba, 12);
493 static struct resource pio3_resource[] = {
498 DEV_CLK(mck, pio3, pba, 13);
500 void __init at32_add_system_devices(void)
502 system_manager.eim_first_irq = NR_INTERNAL_IRQS;
504 platform_device_register(&at32_sm_device);
505 platform_device_register(&at32_intc0_device);
506 platform_device_register(&pdc_device);
508 platform_device_register(&pio0_device);
509 platform_device_register(&pio1_device);
510 platform_device_register(&pio2_device);
511 platform_device_register(&pio3_device);
514 /* --------------------------------------------------------------------
516 * -------------------------------------------------------------------- */
518 static struct resource usart0_resource[] = {
522 DEFINE_DEV(usart, 0);
523 DEV_CLK(usart, usart0, pba, 4);
525 static struct resource usart1_resource[] = {
529 DEFINE_DEV(usart, 1);
530 DEV_CLK(usart, usart1, pba, 4);
532 static struct resource usart2_resource[] = {
536 DEFINE_DEV(usart, 2);
537 DEV_CLK(usart, usart2, pba, 5);
539 static struct resource usart3_resource[] = {
543 DEFINE_DEV(usart, 3);
544 DEV_CLK(usart, usart3, pba, 6);
546 static inline void configure_usart0_pins(void)
548 portmux_set_func(PIOA, 8, FUNC_B); /* RXD */
549 portmux_set_func(PIOA, 9, FUNC_B); /* TXD */
552 static inline void configure_usart1_pins(void)
554 portmux_set_func(PIOA, 17, FUNC_A); /* RXD */
555 portmux_set_func(PIOA, 18, FUNC_A); /* TXD */
558 static inline void configure_usart2_pins(void)
560 portmux_set_func(PIOB, 26, FUNC_B); /* RXD */
561 portmux_set_func(PIOB, 27, FUNC_B); /* TXD */
564 static inline void configure_usart3_pins(void)
566 portmux_set_func(PIOB, 18, FUNC_B); /* RXD */
567 portmux_set_func(PIOB, 17, FUNC_B); /* TXD */
570 static struct platform_device *setup_usart(unsigned int id)
572 struct platform_device *pdev;
576 pdev = &usart0_device;
577 configure_usart0_pins();
580 pdev = &usart1_device;
581 configure_usart1_pins();
584 pdev = &usart2_device;
585 configure_usart2_pins();
588 pdev = &usart3_device;
589 configure_usart3_pins();
599 struct platform_device *__init at32_add_device_usart(unsigned int id)
601 struct platform_device *pdev;
603 pdev = setup_usart(id);
605 platform_device_register(pdev);
610 struct platform_device *at91_default_console_device;
612 void __init at32_setup_serial_console(unsigned int usart_id)
614 at91_default_console_device = setup_usart(usart_id);
617 /* --------------------------------------------------------------------
619 * -------------------------------------------------------------------- */
621 static struct eth_platform_data macb0_data;
622 static struct resource macb0_resource[] = {
626 DEFINE_DEV_DATA(macb, 0);
627 DEV_CLK(hclk, macb0, hsb, 8);
628 DEV_CLK(pclk, macb0, pbb, 6);
630 struct platform_device *__init
631 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
633 struct platform_device *pdev;
637 pdev = &macb0_device;
639 portmux_set_func(PIOC, 3, FUNC_A); /* TXD0 */
640 portmux_set_func(PIOC, 4, FUNC_A); /* TXD1 */
641 portmux_set_func(PIOC, 7, FUNC_A); /* TXEN */
642 portmux_set_func(PIOC, 8, FUNC_A); /* TXCK */
643 portmux_set_func(PIOC, 9, FUNC_A); /* RXD0 */
644 portmux_set_func(PIOC, 10, FUNC_A); /* RXD1 */
645 portmux_set_func(PIOC, 13, FUNC_A); /* RXER */
646 portmux_set_func(PIOC, 15, FUNC_A); /* RXDV */
647 portmux_set_func(PIOC, 16, FUNC_A); /* MDC */
648 portmux_set_func(PIOC, 17, FUNC_A); /* MDIO */
650 if (!data->is_rmii) {
651 portmux_set_func(PIOC, 0, FUNC_A); /* COL */
652 portmux_set_func(PIOC, 1, FUNC_A); /* CRS */
653 portmux_set_func(PIOC, 2, FUNC_A); /* TXER */
654 portmux_set_func(PIOC, 5, FUNC_A); /* TXD2 */
655 portmux_set_func(PIOC, 6, FUNC_A); /* TXD3 */
656 portmux_set_func(PIOC, 11, FUNC_A); /* RXD2 */
657 portmux_set_func(PIOC, 12, FUNC_A); /* RXD3 */
658 portmux_set_func(PIOC, 14, FUNC_A); /* RXCK */
659 portmux_set_func(PIOC, 18, FUNC_A); /* SPD */
667 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
668 platform_device_register(pdev);
673 /* --------------------------------------------------------------------
675 * -------------------------------------------------------------------- */
676 static struct resource spi0_resource[] = {
681 DEV_CLK(mck, spi0, pba, 0);
683 struct platform_device *__init at32_add_device_spi(unsigned int id)
685 struct platform_device *pdev;
690 portmux_set_func(PIOA, 0, FUNC_A); /* MISO */
691 portmux_set_func(PIOA, 1, FUNC_A); /* MOSI */
692 portmux_set_func(PIOA, 2, FUNC_A); /* SCK */
693 portmux_set_func(PIOA, 3, FUNC_A); /* NPCS0 */
694 portmux_set_func(PIOA, 4, FUNC_A); /* NPCS1 */
695 portmux_set_func(PIOA, 5, FUNC_A); /* NPCS2 */
702 platform_device_register(pdev);
706 /* --------------------------------------------------------------------
708 * -------------------------------------------------------------------- */
709 static struct lcdc_platform_data lcdc0_data;
710 static struct resource lcdc0_resource[] = {
714 .flags = IORESOURCE_MEM,
718 DEFINE_DEV_DATA(lcdc, 0);
719 DEV_CLK(hclk, lcdc0, hsb, 7);
720 static struct clk lcdc0_pixclk = {
722 .dev = &lcdc0_device.dev,
724 .get_rate = genclk_get_rate,
725 .set_rate = genclk_set_rate,
726 .set_parent = genclk_set_parent,
730 struct platform_device *__init
731 at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data)
733 struct platform_device *pdev;
737 pdev = &lcdc0_device;
738 portmux_set_func(PIOC, 19, FUNC_A); /* CC */
739 portmux_set_func(PIOC, 20, FUNC_A); /* HSYNC */
740 portmux_set_func(PIOC, 21, FUNC_A); /* PCLK */
741 portmux_set_func(PIOC, 22, FUNC_A); /* VSYNC */
742 portmux_set_func(PIOC, 23, FUNC_A); /* DVAL */
743 portmux_set_func(PIOC, 24, FUNC_A); /* MODE */
744 portmux_set_func(PIOC, 25, FUNC_A); /* PWR */
745 portmux_set_func(PIOC, 26, FUNC_A); /* DATA0 */
746 portmux_set_func(PIOC, 27, FUNC_A); /* DATA1 */
747 portmux_set_func(PIOC, 28, FUNC_A); /* DATA2 */
748 portmux_set_func(PIOC, 29, FUNC_A); /* DATA3 */
749 portmux_set_func(PIOC, 30, FUNC_A); /* DATA4 */
750 portmux_set_func(PIOC, 31, FUNC_A); /* DATA5 */
751 portmux_set_func(PIOD, 0, FUNC_A); /* DATA6 */
752 portmux_set_func(PIOD, 1, FUNC_A); /* DATA7 */
753 portmux_set_func(PIOD, 2, FUNC_A); /* DATA8 */
754 portmux_set_func(PIOD, 3, FUNC_A); /* DATA9 */
755 portmux_set_func(PIOD, 4, FUNC_A); /* DATA10 */
756 portmux_set_func(PIOD, 5, FUNC_A); /* DATA11 */
757 portmux_set_func(PIOD, 6, FUNC_A); /* DATA12 */
758 portmux_set_func(PIOD, 7, FUNC_A); /* DATA13 */
759 portmux_set_func(PIOD, 8, FUNC_A); /* DATA14 */
760 portmux_set_func(PIOD, 9, FUNC_A); /* DATA15 */
761 portmux_set_func(PIOD, 10, FUNC_A); /* DATA16 */
762 portmux_set_func(PIOD, 11, FUNC_A); /* DATA17 */
763 portmux_set_func(PIOD, 12, FUNC_A); /* DATA18 */
764 portmux_set_func(PIOD, 13, FUNC_A); /* DATA19 */
765 portmux_set_func(PIOD, 14, FUNC_A); /* DATA20 */
766 portmux_set_func(PIOD, 15, FUNC_A); /* DATA21 */
767 portmux_set_func(PIOD, 16, FUNC_A); /* DATA22 */
768 portmux_set_func(PIOD, 17, FUNC_A); /* DATA23 */
770 clk_set_parent(&lcdc0_pixclk, &pll0);
771 clk_set_rate(&lcdc0_pixclk, clk_get_rate(&pll0));
778 memcpy(pdev->dev.platform_data, data,
779 sizeof(struct lcdc_platform_data));
781 platform_device_register(pdev);
785 struct clk *at32_clock_list[] = {
816 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
818 void __init at32_portmux_init(void)
820 at32_init_pio(&pio0_device);
821 at32_init_pio(&pio1_device);
822 at32_init_pio(&pio2_device);
823 at32_init_pio(&pio3_device);
826 void __init at32_clock_init(void)
828 struct at32_sm *sm = &system_manager;
829 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
832 if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
837 if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
839 if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
843 * Turn on all clocks that have at least one user already, and
844 * turn off everything else. We only do this for module
845 * clocks, and even though it isn't particularly pretty to
846 * check the address of the mode function, it should do the
849 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
850 struct clk *clk = at32_clock_list[i];
852 if (clk->mode == &cpu_clk_mode)
853 cpu_mask |= 1 << clk->index;
854 else if (clk->mode == &hsb_clk_mode)
855 hsb_mask |= 1 << clk->index;
856 else if (clk->mode == &pba_clk_mode)
857 pba_mask |= 1 << clk->index;
858 else if (clk->mode == &pbb_clk_mode)
859 pbb_mask |= 1 << clk->index;
862 sm_writel(sm, PM_CPU_MASK, cpu_mask);
863 sm_writel(sm, PM_HSB_MASK, hsb_mask);
864 sm_writel(sm, PM_PBA_MASK, pba_mask);
865 sm_writel(sm, PM_PBB_MASK, pbb_mask);