2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30 #include <plat/powerdomain.h>
33 * OMAP1510 GPIO registers
35 #define OMAP1510_GPIO_BASE 0xfffce000
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
44 #define OMAP1510_IH_GPIO_BASE 64
47 * OMAP1610 specific GPIO registers
49 #define OMAP1610_GPIO1_BASE 0xfffbe400
50 #define OMAP1610_GPIO2_BASE 0xfffbec00
51 #define OMAP1610_GPIO3_BASE 0xfffbb400
52 #define OMAP1610_GPIO4_BASE 0xfffbbc00
53 #define OMAP1610_GPIO_REVISION 0x0000
54 #define OMAP1610_GPIO_SYSCONFIG 0x0010
55 #define OMAP1610_GPIO_SYSSTATUS 0x0014
56 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
57 #define OMAP1610_GPIO_IRQENABLE1 0x001c
58 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
59 #define OMAP1610_GPIO_DATAIN 0x002c
60 #define OMAP1610_GPIO_DATAOUT 0x0030
61 #define OMAP1610_GPIO_DIRECTION 0x0034
62 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
63 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
64 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
65 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
66 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
67 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
68 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
69 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
72 * OMAP7XX specific GPIO registers
74 #define OMAP7XX_GPIO1_BASE 0xfffbc000
75 #define OMAP7XX_GPIO2_BASE 0xfffbc800
76 #define OMAP7XX_GPIO3_BASE 0xfffbd000
77 #define OMAP7XX_GPIO4_BASE 0xfffbd800
78 #define OMAP7XX_GPIO5_BASE 0xfffbe000
79 #define OMAP7XX_GPIO6_BASE 0xfffbe800
80 #define OMAP7XX_GPIO_DATA_INPUT 0x00
81 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
82 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
83 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
84 #define OMAP7XX_GPIO_INT_MASK 0x10
85 #define OMAP7XX_GPIO_INT_STATUS 0x14
87 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
90 * omap24xx specific GPIO registers
92 #define OMAP242X_GPIO1_BASE 0x48018000
93 #define OMAP242X_GPIO2_BASE 0x4801a000
94 #define OMAP242X_GPIO3_BASE 0x4801c000
95 #define OMAP242X_GPIO4_BASE 0x4801e000
97 #define OMAP243X_GPIO1_BASE 0x4900C000
98 #define OMAP243X_GPIO2_BASE 0x4900E000
99 #define OMAP243X_GPIO3_BASE 0x49010000
100 #define OMAP243X_GPIO4_BASE 0x49012000
101 #define OMAP243X_GPIO5_BASE 0x480B6000
103 #define OMAP24XX_GPIO_REVISION 0x0000
104 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
105 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
106 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
107 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
108 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
109 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
110 #define OMAP24XX_GPIO_WAKE_EN 0x0020
111 #define OMAP24XX_GPIO_CTRL 0x0030
112 #define OMAP24XX_GPIO_OE 0x0034
113 #define OMAP24XX_GPIO_DATAIN 0x0038
114 #define OMAP24XX_GPIO_DATAOUT 0x003c
115 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
116 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
117 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
118 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
119 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
120 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
121 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
122 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
123 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
124 #define OMAP24XX_GPIO_SETWKUENA 0x0084
125 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
126 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
128 #define OMAP4_GPIO_REVISION 0x0000
129 #define OMAP4_GPIO_SYSCONFIG 0x0010
130 #define OMAP4_GPIO_EOI 0x0020
131 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
132 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
133 #define OMAP4_GPIO_IRQSTATUS0 0x002c
134 #define OMAP4_GPIO_IRQSTATUS1 0x0030
135 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
136 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
137 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
138 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
139 #define OMAP4_GPIO_IRQWAKEN0 0x0044
140 #define OMAP4_GPIO_IRQWAKEN1 0x0048
141 #define OMAP4_GPIO_SYSSTATUS 0x0114
142 #define OMAP4_GPIO_IRQENABLE1 0x011c
143 #define OMAP4_GPIO_WAKE_EN 0x0120
144 #define OMAP4_GPIO_IRQSTATUS2 0x0128
145 #define OMAP4_GPIO_IRQENABLE2 0x012c
146 #define OMAP4_GPIO_CTRL 0x0130
147 #define OMAP4_GPIO_OE 0x0134
148 #define OMAP4_GPIO_DATAIN 0x0138
149 #define OMAP4_GPIO_DATAOUT 0x013c
150 #define OMAP4_GPIO_LEVELDETECT0 0x0140
151 #define OMAP4_GPIO_LEVELDETECT1 0x0144
152 #define OMAP4_GPIO_RISINGDETECT 0x0148
153 #define OMAP4_GPIO_FALLINGDETECT 0x014c
154 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
155 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
156 #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
157 #define OMAP4_GPIO_SETIRQENABLE1 0x0164
158 #define OMAP4_GPIO_CLEARWKUENA 0x0180
159 #define OMAP4_GPIO_SETWKUENA 0x0184
160 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
161 #define OMAP4_GPIO_SETDATAOUT 0x0194
163 * omap34xx specific GPIO registers
166 #define OMAP34XX_GPIO1_BASE 0x48310000
167 #define OMAP34XX_GPIO2_BASE 0x49050000
168 #define OMAP34XX_GPIO3_BASE 0x49052000
169 #define OMAP34XX_GPIO4_BASE 0x49054000
170 #define OMAP34XX_GPIO5_BASE 0x49056000
171 #define OMAP34XX_GPIO6_BASE 0x49058000
174 * OMAP44XX specific GPIO registers
176 #define OMAP44XX_GPIO1_BASE 0x4a310000
177 #define OMAP44XX_GPIO2_BASE 0x48055000
178 #define OMAP44XX_GPIO3_BASE 0x48057000
179 #define OMAP44XX_GPIO4_BASE 0x48059000
180 #define OMAP44XX_GPIO5_BASE 0x4805B000
181 #define OMAP44XX_GPIO6_BASE 0x4805D000
187 u16 virtual_irq_start;
189 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
193 #ifdef CONFIG_ARCH_OMAP2PLUS
194 u32 non_wakeup_gpios;
195 u32 enabled_non_wakeup_gpios;
198 u32 saved_fallingdetect;
199 u32 saved_risingdetect;
204 struct gpio_chip chip;
207 u32 dbck_enable_mask;
210 #define METHOD_MPUIO 0
211 #define METHOD_GPIO_1510 1
212 #define METHOD_GPIO_1610 2
213 #define METHOD_GPIO_7XX 3
214 #define METHOD_GPIO_24XX 5
215 #define METHOD_GPIO_44XX 6
217 #ifdef CONFIG_ARCH_OMAP16XX
218 static struct gpio_bank gpio_bank_1610[5] = {
219 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
221 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
223 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
225 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
227 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
232 #ifdef CONFIG_ARCH_OMAP15XX
233 static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
236 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
241 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
242 static struct gpio_bank gpio_bank_7xx[7] = {
243 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
245 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
247 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
249 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
251 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
253 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
255 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
260 #ifdef CONFIG_ARCH_OMAP2
262 static struct gpio_bank gpio_bank_242x[4] = {
263 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
265 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
267 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
269 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
273 static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
276 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
278 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
280 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
282 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
288 #ifdef CONFIG_ARCH_OMAP3
289 static struct gpio_bank gpio_bank_34xx[6] = {
290 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
292 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
294 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
296 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
298 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
300 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
304 struct omap3_gpio_regs {
318 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
321 #ifdef CONFIG_ARCH_OMAP4
322 static struct gpio_bank gpio_bank_44xx[6] = {
323 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
325 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
327 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
329 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
331 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
333 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
339 static struct gpio_bank *gpio_bank;
340 static int gpio_bank_count;
342 static inline struct gpio_bank *get_gpio_bank(int gpio)
344 if (cpu_is_omap15xx()) {
345 if (OMAP_GPIO_IS_MPUIO(gpio))
346 return &gpio_bank[0];
347 return &gpio_bank[1];
349 if (cpu_is_omap16xx()) {
350 if (OMAP_GPIO_IS_MPUIO(gpio))
351 return &gpio_bank[0];
352 return &gpio_bank[1 + (gpio >> 4)];
354 if (cpu_is_omap7xx()) {
355 if (OMAP_GPIO_IS_MPUIO(gpio))
356 return &gpio_bank[0];
357 return &gpio_bank[1 + (gpio >> 5)];
359 if (cpu_is_omap24xx())
360 return &gpio_bank[gpio >> 5];
361 if (cpu_is_omap34xx() || cpu_is_omap44xx())
362 return &gpio_bank[gpio >> 5];
367 static inline int get_gpio_index(int gpio)
369 if (cpu_is_omap7xx())
371 if (cpu_is_omap24xx())
373 if (cpu_is_omap34xx() || cpu_is_omap44xx())
378 static inline int gpio_valid(int gpio)
382 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
383 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
387 if (cpu_is_omap15xx() && gpio < 16)
389 if ((cpu_is_omap16xx()) && gpio < 64)
391 if (cpu_is_omap7xx() && gpio < 192)
393 if (cpu_is_omap24xx() && gpio < 128)
395 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
400 static int check_gpio(int gpio)
402 if (unlikely(gpio_valid(gpio) < 0)) {
403 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
410 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
412 void __iomem *reg = bank->base;
415 switch (bank->method) {
416 #ifdef CONFIG_ARCH_OMAP1
418 reg += OMAP_MPUIO_IO_CNTL;
421 #ifdef CONFIG_ARCH_OMAP15XX
422 case METHOD_GPIO_1510:
423 reg += OMAP1510_GPIO_DIR_CONTROL;
426 #ifdef CONFIG_ARCH_OMAP16XX
427 case METHOD_GPIO_1610:
428 reg += OMAP1610_GPIO_DIRECTION;
431 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
432 case METHOD_GPIO_7XX:
433 reg += OMAP7XX_GPIO_DIR_CONTROL;
436 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
437 case METHOD_GPIO_24XX:
438 reg += OMAP24XX_GPIO_OE;
441 #if defined(CONFIG_ARCH_OMAP4)
442 case METHOD_GPIO_44XX:
443 reg += OMAP4_GPIO_OE;
450 l = __raw_readl(reg);
455 __raw_writel(l, reg);
458 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
460 void __iomem *reg = bank->base;
463 switch (bank->method) {
464 #ifdef CONFIG_ARCH_OMAP1
466 reg += OMAP_MPUIO_OUTPUT;
467 l = __raw_readl(reg);
474 #ifdef CONFIG_ARCH_OMAP15XX
475 case METHOD_GPIO_1510:
476 reg += OMAP1510_GPIO_DATA_OUTPUT;
477 l = __raw_readl(reg);
484 #ifdef CONFIG_ARCH_OMAP16XX
485 case METHOD_GPIO_1610:
487 reg += OMAP1610_GPIO_SET_DATAOUT;
489 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
493 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
494 case METHOD_GPIO_7XX:
495 reg += OMAP7XX_GPIO_DATA_OUTPUT;
496 l = __raw_readl(reg);
503 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
504 case METHOD_GPIO_24XX:
506 reg += OMAP24XX_GPIO_SETDATAOUT;
508 reg += OMAP24XX_GPIO_CLEARDATAOUT;
512 #ifdef CONFIG_ARCH_OMAP4
513 case METHOD_GPIO_44XX:
515 reg += OMAP4_GPIO_SETDATAOUT;
517 reg += OMAP4_GPIO_CLEARDATAOUT;
525 __raw_writel(l, reg);
528 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
532 if (check_gpio(gpio) < 0)
535 switch (bank->method) {
536 #ifdef CONFIG_ARCH_OMAP1
538 reg += OMAP_MPUIO_INPUT_LATCH;
541 #ifdef CONFIG_ARCH_OMAP15XX
542 case METHOD_GPIO_1510:
543 reg += OMAP1510_GPIO_DATA_INPUT;
546 #ifdef CONFIG_ARCH_OMAP16XX
547 case METHOD_GPIO_1610:
548 reg += OMAP1610_GPIO_DATAIN;
551 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
552 case METHOD_GPIO_7XX:
553 reg += OMAP7XX_GPIO_DATA_INPUT;
556 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
557 case METHOD_GPIO_24XX:
558 reg += OMAP24XX_GPIO_DATAIN;
561 #ifdef CONFIG_ARCH_OMAP4
562 case METHOD_GPIO_44XX:
563 reg += OMAP4_GPIO_DATAIN;
569 return (__raw_readl(reg)
570 & (1 << get_gpio_index(gpio))) != 0;
573 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
577 if (check_gpio(gpio) < 0)
581 switch (bank->method) {
582 #ifdef CONFIG_ARCH_OMAP1
584 reg += OMAP_MPUIO_OUTPUT;
587 #ifdef CONFIG_ARCH_OMAP15XX
588 case METHOD_GPIO_1510:
589 reg += OMAP1510_GPIO_DATA_OUTPUT;
592 #ifdef CONFIG_ARCH_OMAP16XX
593 case METHOD_GPIO_1610:
594 reg += OMAP1610_GPIO_DATAOUT;
597 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
598 case METHOD_GPIO_7XX:
599 reg += OMAP7XX_GPIO_DATA_OUTPUT;
602 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
603 case METHOD_GPIO_24XX:
604 reg += OMAP24XX_GPIO_DATAOUT;
607 #ifdef CONFIG_ARCH_OMAP4
608 case METHOD_GPIO_44XX:
609 reg += OMAP4_GPIO_DATAOUT;
616 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
619 #define MOD_REG_BIT(reg, bit_mask, set) \
621 int l = __raw_readl(base + reg); \
622 if (set) l |= bit_mask; \
623 else l &= ~bit_mask; \
624 __raw_writel(l, base + reg); \
627 void omap_set_gpio_debounce(int gpio, int enable)
629 struct gpio_bank *bank;
632 u32 val, l = 1 << get_gpio_index(gpio);
634 if (cpu_class_is_omap1())
637 bank = get_gpio_bank(gpio);
640 if (cpu_is_omap44xx())
641 reg += OMAP4_GPIO_DEBOUNCENABLE;
643 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
645 if (!(bank->mod_usage & l)) {
646 printk(KERN_ERR "GPIO %d not requested\n", gpio);
650 spin_lock_irqsave(&bank->lock, flags);
651 val = __raw_readl(reg);
653 if (enable && !(val & l))
655 else if (!enable && (val & l))
660 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
661 bank->dbck_enable_mask = val;
663 clk_enable(bank->dbck);
665 clk_disable(bank->dbck);
668 __raw_writel(val, reg);
670 spin_unlock_irqrestore(&bank->lock, flags);
672 EXPORT_SYMBOL(omap_set_gpio_debounce);
674 void omap_set_gpio_debounce_time(int gpio, int enc_time)
676 struct gpio_bank *bank;
679 if (cpu_class_is_omap1())
682 bank = get_gpio_bank(gpio);
685 if (!bank->mod_usage) {
686 printk(KERN_ERR "GPIO not requested\n");
692 if (cpu_is_omap44xx())
693 reg += OMAP4_GPIO_DEBOUNCINGTIME;
695 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
697 __raw_writel(enc_time, reg);
699 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
701 #ifdef CONFIG_ARCH_OMAP2PLUS
702 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
705 void __iomem *base = bank->base;
706 u32 gpio_bit = 1 << gpio;
709 if (cpu_is_omap44xx()) {
710 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
711 trigger & IRQ_TYPE_LEVEL_LOW);
712 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
713 trigger & IRQ_TYPE_LEVEL_HIGH);
714 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
715 trigger & IRQ_TYPE_EDGE_RISING);
716 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
717 trigger & IRQ_TYPE_EDGE_FALLING);
719 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
720 trigger & IRQ_TYPE_LEVEL_LOW);
721 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
722 trigger & IRQ_TYPE_LEVEL_HIGH);
723 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
724 trigger & IRQ_TYPE_EDGE_RISING);
725 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
726 trigger & IRQ_TYPE_EDGE_FALLING);
728 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
729 if (cpu_is_omap44xx()) {
731 __raw_writel(1 << gpio, bank->base+
732 OMAP4_GPIO_IRQWAKEN0);
734 val = __raw_readl(bank->base +
735 OMAP4_GPIO_IRQWAKEN0);
736 __raw_writel(val & (~(1 << gpio)), bank->base +
737 OMAP4_GPIO_IRQWAKEN0);
741 * GPIO wakeup request can only be generated on edge
744 if (trigger & IRQ_TYPE_EDGE_BOTH)
745 __raw_writel(1 << gpio, bank->base
746 + OMAP24XX_GPIO_SETWKUENA);
748 __raw_writel(1 << gpio, bank->base
749 + OMAP24XX_GPIO_CLEARWKUENA);
752 /* This part needs to be executed always for OMAP34xx */
753 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
755 * Log the edge gpio and manually trigger the IRQ
756 * after resume if the input level changes
757 * to avoid irq lost during PER RET/OFF mode
758 * Applies for omap2 non-wakeup gpio and all omap3 gpios
760 if (trigger & IRQ_TYPE_EDGE_BOTH)
761 bank->enabled_non_wakeup_gpios |= gpio_bit;
763 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
766 if (cpu_is_omap44xx()) {
768 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
769 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
772 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
773 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
778 #ifdef CONFIG_ARCH_OMAP1
780 * This only applies to chips that can't do both rising and falling edge
781 * detection at once. For all other chips, this function is a noop.
783 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
785 void __iomem *reg = bank->base;
788 switch (bank->method) {
790 reg += OMAP_MPUIO_GPIO_INT_EDGE;
792 #ifdef CONFIG_ARCH_OMAP15XX
793 case METHOD_GPIO_1510:
794 reg += OMAP1510_GPIO_INT_CONTROL;
797 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
798 case METHOD_GPIO_7XX:
799 reg += OMAP7XX_GPIO_INT_CONTROL;
806 l = __raw_readl(reg);
812 __raw_writel(l, reg);
816 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
818 void __iomem *reg = bank->base;
821 switch (bank->method) {
822 #ifdef CONFIG_ARCH_OMAP1
824 reg += OMAP_MPUIO_GPIO_INT_EDGE;
825 l = __raw_readl(reg);
826 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
827 bank->toggle_mask |= 1 << gpio;
828 if (trigger & IRQ_TYPE_EDGE_RISING)
830 else if (trigger & IRQ_TYPE_EDGE_FALLING)
836 #ifdef CONFIG_ARCH_OMAP15XX
837 case METHOD_GPIO_1510:
838 reg += OMAP1510_GPIO_INT_CONTROL;
839 l = __raw_readl(reg);
840 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
841 bank->toggle_mask |= 1 << gpio;
842 if (trigger & IRQ_TYPE_EDGE_RISING)
844 else if (trigger & IRQ_TYPE_EDGE_FALLING)
850 #ifdef CONFIG_ARCH_OMAP16XX
851 case METHOD_GPIO_1610:
853 reg += OMAP1610_GPIO_EDGE_CTRL2;
855 reg += OMAP1610_GPIO_EDGE_CTRL1;
857 l = __raw_readl(reg);
858 l &= ~(3 << (gpio << 1));
859 if (trigger & IRQ_TYPE_EDGE_RISING)
860 l |= 2 << (gpio << 1);
861 if (trigger & IRQ_TYPE_EDGE_FALLING)
862 l |= 1 << (gpio << 1);
864 /* Enable wake-up during idle for dynamic tick */
865 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
867 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
870 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
871 case METHOD_GPIO_7XX:
872 reg += OMAP7XX_GPIO_INT_CONTROL;
873 l = __raw_readl(reg);
874 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
875 bank->toggle_mask |= 1 << gpio;
876 if (trigger & IRQ_TYPE_EDGE_RISING)
878 else if (trigger & IRQ_TYPE_EDGE_FALLING)
884 #ifdef CONFIG_ARCH_OMAP2PLUS
885 case METHOD_GPIO_24XX:
886 case METHOD_GPIO_44XX:
887 set_24xx_gpio_triggering(bank, gpio, trigger);
893 __raw_writel(l, reg);
899 static int gpio_irq_type(unsigned irq, unsigned type)
901 struct gpio_bank *bank;
906 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
907 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
909 gpio = irq - IH_GPIO_BASE;
911 if (check_gpio(gpio) < 0)
914 if (type & ~IRQ_TYPE_SENSE_MASK)
917 /* OMAP1 allows only only edge triggering */
918 if (!cpu_class_is_omap2()
919 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
922 bank = get_irq_chip_data(irq);
923 spin_lock_irqsave(&bank->lock, flags);
924 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
926 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
927 irq_desc[irq].status |= type;
929 spin_unlock_irqrestore(&bank->lock, flags);
931 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
932 __set_irq_handler_unlocked(irq, handle_level_irq);
933 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
934 __set_irq_handler_unlocked(irq, handle_edge_irq);
939 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
941 void __iomem *reg = bank->base;
943 switch (bank->method) {
944 #ifdef CONFIG_ARCH_OMAP1
946 /* MPUIO irqstatus is reset by reading the status register,
947 * so do nothing here */
950 #ifdef CONFIG_ARCH_OMAP15XX
951 case METHOD_GPIO_1510:
952 reg += OMAP1510_GPIO_INT_STATUS;
955 #ifdef CONFIG_ARCH_OMAP16XX
956 case METHOD_GPIO_1610:
957 reg += OMAP1610_GPIO_IRQSTATUS1;
960 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
961 case METHOD_GPIO_7XX:
962 reg += OMAP7XX_GPIO_INT_STATUS;
965 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
966 case METHOD_GPIO_24XX:
967 reg += OMAP24XX_GPIO_IRQSTATUS1;
970 #if defined(CONFIG_ARCH_OMAP4)
971 case METHOD_GPIO_44XX:
972 reg += OMAP4_GPIO_IRQSTATUS0;
979 __raw_writel(gpio_mask, reg);
981 /* Workaround for clearing DSP GPIO interrupts to allow retention */
982 if (cpu_is_omap24xx() || cpu_is_omap34xx())
983 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
984 else if (cpu_is_omap44xx())
985 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
987 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
988 __raw_writel(gpio_mask, reg);
990 /* Flush posted write for the irq status to avoid spurious interrupts */
995 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
997 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
1000 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
1002 void __iomem *reg = bank->base;
1007 switch (bank->method) {
1008 #ifdef CONFIG_ARCH_OMAP1
1010 reg += OMAP_MPUIO_GPIO_MASKIT;
1015 #ifdef CONFIG_ARCH_OMAP15XX
1016 case METHOD_GPIO_1510:
1017 reg += OMAP1510_GPIO_INT_MASK;
1022 #ifdef CONFIG_ARCH_OMAP16XX
1023 case METHOD_GPIO_1610:
1024 reg += OMAP1610_GPIO_IRQENABLE1;
1028 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1029 case METHOD_GPIO_7XX:
1030 reg += OMAP7XX_GPIO_INT_MASK;
1035 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1036 case METHOD_GPIO_24XX:
1037 reg += OMAP24XX_GPIO_IRQENABLE1;
1041 #if defined(CONFIG_ARCH_OMAP4)
1042 case METHOD_GPIO_44XX:
1043 reg += OMAP4_GPIO_IRQSTATUSSET0;
1052 l = __raw_readl(reg);
1059 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1061 void __iomem *reg = bank->base;
1064 switch (bank->method) {
1065 #ifdef CONFIG_ARCH_OMAP1
1067 reg += OMAP_MPUIO_GPIO_MASKIT;
1068 l = __raw_readl(reg);
1075 #ifdef CONFIG_ARCH_OMAP15XX
1076 case METHOD_GPIO_1510:
1077 reg += OMAP1510_GPIO_INT_MASK;
1078 l = __raw_readl(reg);
1085 #ifdef CONFIG_ARCH_OMAP16XX
1086 case METHOD_GPIO_1610:
1088 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1090 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1094 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1095 case METHOD_GPIO_7XX:
1096 reg += OMAP7XX_GPIO_INT_MASK;
1097 l = __raw_readl(reg);
1104 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1105 case METHOD_GPIO_24XX:
1107 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1109 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1113 #ifdef CONFIG_ARCH_OMAP4
1114 case METHOD_GPIO_44XX:
1116 reg += OMAP4_GPIO_IRQSTATUSSET0;
1118 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1126 __raw_writel(l, reg);
1129 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1131 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1135 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1136 * 1510 does not seem to have a wake-up register. If JTAG is connected
1137 * to the target, system will wake up always on GPIO events. While
1138 * system is running all registered GPIO interrupts need to have wake-up
1139 * enabled. When system is suspended, only selected GPIO interrupts need
1140 * to have wake-up enabled.
1142 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1144 unsigned long uninitialized_var(flags);
1146 switch (bank->method) {
1147 #ifdef CONFIG_ARCH_OMAP16XX
1149 case METHOD_GPIO_1610:
1150 spin_lock_irqsave(&bank->lock, flags);
1152 bank->suspend_wakeup |= (1 << gpio);
1154 bank->suspend_wakeup &= ~(1 << gpio);
1155 spin_unlock_irqrestore(&bank->lock, flags);
1158 #ifdef CONFIG_ARCH_OMAP2PLUS
1159 case METHOD_GPIO_24XX:
1160 case METHOD_GPIO_44XX:
1161 if (bank->non_wakeup_gpios & (1 << gpio)) {
1162 printk(KERN_ERR "Unable to modify wakeup on "
1163 "non-wakeup GPIO%d\n",
1164 (bank - gpio_bank) * 32 + gpio);
1167 spin_lock_irqsave(&bank->lock, flags);
1169 bank->suspend_wakeup |= (1 << gpio);
1171 bank->suspend_wakeup &= ~(1 << gpio);
1172 spin_unlock_irqrestore(&bank->lock, flags);
1176 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1182 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1184 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1185 _set_gpio_irqenable(bank, gpio, 0);
1186 _clear_gpio_irqstatus(bank, gpio);
1187 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1190 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1191 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1193 unsigned int gpio = irq - IH_GPIO_BASE;
1194 struct gpio_bank *bank;
1197 if (check_gpio(gpio) < 0)
1199 bank = get_irq_chip_data(irq);
1200 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1205 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1207 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1208 unsigned long flags;
1210 spin_lock_irqsave(&bank->lock, flags);
1212 /* Set trigger to none. You need to enable the desired trigger with
1213 * request_irq() or set_irq_type().
1215 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1217 #ifdef CONFIG_ARCH_OMAP15XX
1218 if (bank->method == METHOD_GPIO_1510) {
1221 /* Claim the pin for MPU */
1222 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1223 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1226 if (!cpu_class_is_omap1()) {
1227 if (!bank->mod_usage) {
1228 void __iomem *reg = bank->base;
1231 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1232 reg += OMAP24XX_GPIO_CTRL;
1233 else if (cpu_is_omap44xx())
1234 reg += OMAP4_GPIO_CTRL;
1235 ctrl = __raw_readl(reg);
1236 /* Module is enabled, clocks are not gated */
1238 __raw_writel(ctrl, reg);
1240 bank->mod_usage |= 1 << offset;
1242 spin_unlock_irqrestore(&bank->lock, flags);
1247 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1249 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1250 unsigned long flags;
1252 spin_lock_irqsave(&bank->lock, flags);
1253 #ifdef CONFIG_ARCH_OMAP16XX
1254 if (bank->method == METHOD_GPIO_1610) {
1255 /* Disable wake-up during idle for dynamic tick */
1256 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1257 __raw_writel(1 << offset, reg);
1260 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1261 if (bank->method == METHOD_GPIO_24XX) {
1262 /* Disable wake-up during idle for dynamic tick */
1263 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1264 __raw_writel(1 << offset, reg);
1267 #ifdef CONFIG_ARCH_OMAP4
1268 if (bank->method == METHOD_GPIO_44XX) {
1269 /* Disable wake-up during idle for dynamic tick */
1270 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1271 __raw_writel(1 << offset, reg);
1274 if (!cpu_class_is_omap1()) {
1275 bank->mod_usage &= ~(1 << offset);
1276 if (!bank->mod_usage) {
1277 void __iomem *reg = bank->base;
1280 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1281 reg += OMAP24XX_GPIO_CTRL;
1282 else if (cpu_is_omap44xx())
1283 reg += OMAP4_GPIO_CTRL;
1284 ctrl = __raw_readl(reg);
1285 /* Module is disabled, clocks are gated */
1287 __raw_writel(ctrl, reg);
1290 _reset_gpio(bank, bank->chip.base + offset);
1291 spin_unlock_irqrestore(&bank->lock, flags);
1295 * We need to unmask the GPIO bank interrupt as soon as possible to
1296 * avoid missing GPIO interrupts for other lines in the bank.
1297 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1298 * in the bank to avoid missing nested interrupts for a GPIO line.
1299 * If we wait to unmask individual GPIO lines in the bank after the
1300 * line's interrupt handler has been run, we may miss some nested
1303 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1305 void __iomem *isr_reg = NULL;
1307 unsigned int gpio_irq, gpio_index;
1308 struct gpio_bank *bank;
1312 desc->chip->ack(irq);
1314 bank = get_irq_data(irq);
1315 #ifdef CONFIG_ARCH_OMAP1
1316 if (bank->method == METHOD_MPUIO)
1317 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1319 #ifdef CONFIG_ARCH_OMAP15XX
1320 if (bank->method == METHOD_GPIO_1510)
1321 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1323 #if defined(CONFIG_ARCH_OMAP16XX)
1324 if (bank->method == METHOD_GPIO_1610)
1325 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1327 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1328 if (bank->method == METHOD_GPIO_7XX)
1329 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1331 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1332 if (bank->method == METHOD_GPIO_24XX)
1333 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1335 #if defined(CONFIG_ARCH_OMAP4)
1336 if (bank->method == METHOD_GPIO_44XX)
1337 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1340 u32 isr_saved, level_mask = 0;
1343 enabled = _get_gpio_irqbank_mask(bank);
1344 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1346 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1349 if (cpu_class_is_omap2()) {
1350 level_mask = bank->level_mask & enabled;
1353 /* clear edge sensitive interrupts before handler(s) are
1354 called so that we don't miss any interrupt occurred while
1356 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1357 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1358 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1360 /* if there is only edge sensitive GPIO pin interrupts
1361 configured, we could unmask GPIO bank interrupt immediately */
1362 if (!level_mask && !unmasked) {
1364 desc->chip->unmask(irq);
1372 gpio_irq = bank->virtual_irq_start;
1373 for (; isr != 0; isr >>= 1, gpio_irq++) {
1374 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1379 #ifdef CONFIG_ARCH_OMAP1
1381 * Some chips can't respond to both rising and falling
1382 * at the same time. If this irq was requested with
1383 * both flags, we need to flip the ICR data for the IRQ
1384 * to respond to the IRQ for the opposite direction.
1385 * This will be indicated in the bank toggle_mask.
1387 if (bank->toggle_mask & (1 << gpio_index))
1388 _toggle_gpio_edge_triggering(bank, gpio_index);
1391 generic_handle_irq(gpio_irq);
1394 /* if bank has any level sensitive GPIO pin interrupt
1395 configured, we must unmask the bank interrupt only after
1396 handler(s) are executed in order to avoid spurious bank
1399 desc->chip->unmask(irq);
1403 static void gpio_irq_shutdown(unsigned int irq)
1405 unsigned int gpio = irq - IH_GPIO_BASE;
1406 struct gpio_bank *bank = get_irq_chip_data(irq);
1408 _reset_gpio(bank, gpio);
1411 static void gpio_ack_irq(unsigned int irq)
1413 unsigned int gpio = irq - IH_GPIO_BASE;
1414 struct gpio_bank *bank = get_irq_chip_data(irq);
1416 _clear_gpio_irqstatus(bank, gpio);
1419 static void gpio_mask_irq(unsigned int irq)
1421 unsigned int gpio = irq - IH_GPIO_BASE;
1422 struct gpio_bank *bank = get_irq_chip_data(irq);
1424 _set_gpio_irqenable(bank, gpio, 0);
1425 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1428 static void gpio_unmask_irq(unsigned int irq)
1430 unsigned int gpio = irq - IH_GPIO_BASE;
1431 struct gpio_bank *bank = get_irq_chip_data(irq);
1432 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1433 struct irq_desc *desc = irq_to_desc(irq);
1434 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1437 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1439 /* For level-triggered GPIOs, the clearing must be done after
1440 * the HW source is cleared, thus after the handler has run */
1441 if (bank->level_mask & irq_mask) {
1442 _set_gpio_irqenable(bank, gpio, 0);
1443 _clear_gpio_irqstatus(bank, gpio);
1446 _set_gpio_irqenable(bank, gpio, 1);
1449 static struct irq_chip gpio_irq_chip = {
1451 .shutdown = gpio_irq_shutdown,
1452 .ack = gpio_ack_irq,
1453 .mask = gpio_mask_irq,
1454 .unmask = gpio_unmask_irq,
1455 .set_type = gpio_irq_type,
1456 .set_wake = gpio_wake_enable,
1459 /*---------------------------------------------------------------------*/
1461 #ifdef CONFIG_ARCH_OMAP1
1463 /* MPUIO uses the always-on 32k clock */
1465 static void mpuio_ack_irq(unsigned int irq)
1467 /* The ISR is reset automatically, so do nothing here. */
1470 static void mpuio_mask_irq(unsigned int irq)
1472 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1473 struct gpio_bank *bank = get_irq_chip_data(irq);
1475 _set_gpio_irqenable(bank, gpio, 0);
1478 static void mpuio_unmask_irq(unsigned int irq)
1480 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1481 struct gpio_bank *bank = get_irq_chip_data(irq);
1483 _set_gpio_irqenable(bank, gpio, 1);
1486 static struct irq_chip mpuio_irq_chip = {
1488 .ack = mpuio_ack_irq,
1489 .mask = mpuio_mask_irq,
1490 .unmask = mpuio_unmask_irq,
1491 .set_type = gpio_irq_type,
1492 #ifdef CONFIG_ARCH_OMAP16XX
1493 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1494 .set_wake = gpio_wake_enable,
1499 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1502 #ifdef CONFIG_ARCH_OMAP16XX
1504 #include <linux/platform_device.h>
1506 static int omap_mpuio_suspend_noirq(struct device *dev)
1508 struct platform_device *pdev = to_platform_device(dev);
1509 struct gpio_bank *bank = platform_get_drvdata(pdev);
1510 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1511 unsigned long flags;
1513 spin_lock_irqsave(&bank->lock, flags);
1514 bank->saved_wakeup = __raw_readl(mask_reg);
1515 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1516 spin_unlock_irqrestore(&bank->lock, flags);
1521 static int omap_mpuio_resume_noirq(struct device *dev)
1523 struct platform_device *pdev = to_platform_device(dev);
1524 struct gpio_bank *bank = platform_get_drvdata(pdev);
1525 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1526 unsigned long flags;
1528 spin_lock_irqsave(&bank->lock, flags);
1529 __raw_writel(bank->saved_wakeup, mask_reg);
1530 spin_unlock_irqrestore(&bank->lock, flags);
1535 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1536 .suspend_noirq = omap_mpuio_suspend_noirq,
1537 .resume_noirq = omap_mpuio_resume_noirq,
1540 /* use platform_driver for this, now that there's no longer any
1541 * point to sys_device (other than not disturbing old code).
1543 static struct platform_driver omap_mpuio_driver = {
1546 .pm = &omap_mpuio_dev_pm_ops,
1550 static struct platform_device omap_mpuio_device = {
1554 .driver = &omap_mpuio_driver.driver,
1556 /* could list the /proc/iomem resources */
1559 static inline void mpuio_init(void)
1561 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1563 if (platform_driver_register(&omap_mpuio_driver) == 0)
1564 (void) platform_device_register(&omap_mpuio_device);
1568 static inline void mpuio_init(void) {}
1573 extern struct irq_chip mpuio_irq_chip;
1575 #define bank_is_mpuio(bank) 0
1576 static inline void mpuio_init(void) {}
1580 /*---------------------------------------------------------------------*/
1582 /* REVISIT these are stupid implementations! replace by ones that
1583 * don't switch on METHOD_* and which mostly avoid spinlocks
1586 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1588 struct gpio_bank *bank;
1589 unsigned long flags;
1591 bank = container_of(chip, struct gpio_bank, chip);
1592 spin_lock_irqsave(&bank->lock, flags);
1593 _set_gpio_direction(bank, offset, 1);
1594 spin_unlock_irqrestore(&bank->lock, flags);
1598 static int gpio_is_input(struct gpio_bank *bank, int mask)
1600 void __iomem *reg = bank->base;
1602 switch (bank->method) {
1604 reg += OMAP_MPUIO_IO_CNTL;
1606 case METHOD_GPIO_1510:
1607 reg += OMAP1510_GPIO_DIR_CONTROL;
1609 case METHOD_GPIO_1610:
1610 reg += OMAP1610_GPIO_DIRECTION;
1612 case METHOD_GPIO_7XX:
1613 reg += OMAP7XX_GPIO_DIR_CONTROL;
1615 case METHOD_GPIO_24XX:
1616 reg += OMAP24XX_GPIO_OE;
1618 case METHOD_GPIO_44XX:
1619 reg += OMAP4_GPIO_OE;
1622 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1625 return __raw_readl(reg) & mask;
1628 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1630 struct gpio_bank *bank;
1635 gpio = chip->base + offset;
1636 bank = get_gpio_bank(gpio);
1638 mask = 1 << get_gpio_index(gpio);
1640 if (gpio_is_input(bank, mask))
1641 return _get_gpio_datain(bank, gpio);
1643 return _get_gpio_dataout(bank, gpio);
1646 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1648 struct gpio_bank *bank;
1649 unsigned long flags;
1651 bank = container_of(chip, struct gpio_bank, chip);
1652 spin_lock_irqsave(&bank->lock, flags);
1653 _set_gpio_dataout(bank, offset, value);
1654 _set_gpio_direction(bank, offset, 0);
1655 spin_unlock_irqrestore(&bank->lock, flags);
1659 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1661 struct gpio_bank *bank;
1662 unsigned long flags;
1664 bank = container_of(chip, struct gpio_bank, chip);
1665 spin_lock_irqsave(&bank->lock, flags);
1666 _set_gpio_dataout(bank, offset, value);
1667 spin_unlock_irqrestore(&bank->lock, flags);
1670 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1672 struct gpio_bank *bank;
1674 bank = container_of(chip, struct gpio_bank, chip);
1675 return bank->virtual_irq_start + offset;
1678 /*---------------------------------------------------------------------*/
1680 static int initialized;
1681 #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1682 static struct clk * gpio_ick;
1685 #if defined(CONFIG_ARCH_OMAP2)
1686 static struct clk * gpio_fck;
1689 #if defined(CONFIG_ARCH_OMAP2430)
1690 static struct clk * gpio5_ick;
1691 static struct clk * gpio5_fck;
1694 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1695 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1698 static void __init omap_gpio_show_rev(void)
1702 if (cpu_is_omap16xx())
1703 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1704 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1705 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1706 else if (cpu_is_omap44xx())
1707 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1711 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1712 (rev >> 4) & 0x0f, rev & 0x0f);
1715 /* This lock class tells lockdep that GPIO irqs are in a different
1716 * category than their parents, so it won't report false recursion.
1718 static struct lock_class_key gpio_lock_class;
1720 static int __init _omap_gpio_init(void)
1724 struct gpio_bank *bank;
1725 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1730 #if defined(CONFIG_ARCH_OMAP1)
1731 if (cpu_is_omap15xx()) {
1732 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1733 if (IS_ERR(gpio_ick))
1734 printk("Could not get arm_gpio_ck\n");
1736 clk_enable(gpio_ick);
1739 #if defined(CONFIG_ARCH_OMAP2)
1740 if (cpu_class_is_omap2()) {
1741 gpio_ick = clk_get(NULL, "gpios_ick");
1742 if (IS_ERR(gpio_ick))
1743 printk("Could not get gpios_ick\n");
1745 clk_enable(gpio_ick);
1746 gpio_fck = clk_get(NULL, "gpios_fck");
1747 if (IS_ERR(gpio_fck))
1748 printk("Could not get gpios_fck\n");
1750 clk_enable(gpio_fck);
1753 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1755 #if defined(CONFIG_ARCH_OMAP2430)
1756 if (cpu_is_omap2430()) {
1757 gpio5_ick = clk_get(NULL, "gpio5_ick");
1758 if (IS_ERR(gpio5_ick))
1759 printk("Could not get gpio5_ick\n");
1761 clk_enable(gpio5_ick);
1762 gpio5_fck = clk_get(NULL, "gpio5_fck");
1763 if (IS_ERR(gpio5_fck))
1764 printk("Could not get gpio5_fck\n");
1766 clk_enable(gpio5_fck);
1772 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1773 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1774 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1775 sprintf(clk_name, "gpio%d_ick", i + 1);
1776 gpio_iclks[i] = clk_get(NULL, clk_name);
1777 if (IS_ERR(gpio_iclks[i]))
1778 printk(KERN_ERR "Could not get %s\n", clk_name);
1780 clk_enable(gpio_iclks[i]);
1786 #ifdef CONFIG_ARCH_OMAP15XX
1787 if (cpu_is_omap15xx()) {
1788 gpio_bank_count = 2;
1789 gpio_bank = gpio_bank_1510;
1793 #if defined(CONFIG_ARCH_OMAP16XX)
1794 if (cpu_is_omap16xx()) {
1795 gpio_bank_count = 5;
1796 gpio_bank = gpio_bank_1610;
1800 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1801 if (cpu_is_omap7xx()) {
1802 gpio_bank_count = 7;
1803 gpio_bank = gpio_bank_7xx;
1807 #ifdef CONFIG_ARCH_OMAP2
1808 if (cpu_is_omap242x()) {
1809 gpio_bank_count = 4;
1810 gpio_bank = gpio_bank_242x;
1812 if (cpu_is_omap243x()) {
1813 gpio_bank_count = 5;
1814 gpio_bank = gpio_bank_243x;
1817 #ifdef CONFIG_ARCH_OMAP3
1818 if (cpu_is_omap34xx()) {
1819 gpio_bank_count = OMAP34XX_NR_GPIOS;
1820 gpio_bank = gpio_bank_34xx;
1823 #ifdef CONFIG_ARCH_OMAP4
1824 if (cpu_is_omap44xx()) {
1825 gpio_bank_count = OMAP34XX_NR_GPIOS;
1826 gpio_bank = gpio_bank_44xx;
1829 for (i = 0; i < gpio_bank_count; i++) {
1830 int j, gpio_count = 16;
1832 bank = &gpio_bank[i];
1833 spin_lock_init(&bank->lock);
1835 /* Static mapping, never released */
1836 bank->base = ioremap(bank->pbase, bank_size);
1838 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1842 if (bank_is_mpuio(bank))
1843 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1844 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1845 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1846 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1848 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1849 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1850 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1851 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1853 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1854 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1855 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1857 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1860 #ifdef CONFIG_ARCH_OMAP2PLUS
1861 if ((bank->method == METHOD_GPIO_24XX) ||
1862 (bank->method == METHOD_GPIO_44XX)) {
1863 static const u32 non_wakeup_gpios[] = {
1864 0xe203ffc0, 0x08700040
1867 if (cpu_is_omap44xx()) {
1868 __raw_writel(0xffffffff, bank->base +
1869 OMAP4_GPIO_IRQSTATUSCLR0);
1870 __raw_writew(0x0015, bank->base +
1871 OMAP4_GPIO_SYSCONFIG);
1872 __raw_writel(0x00000000, bank->base +
1873 OMAP4_GPIO_DEBOUNCENABLE);
1875 * Initialize interface clock ungated,
1878 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1880 __raw_writel(0x00000000, bank->base +
1881 OMAP24XX_GPIO_IRQENABLE1);
1882 __raw_writel(0xffffffff, bank->base +
1883 OMAP24XX_GPIO_IRQSTATUS1);
1884 __raw_writew(0x0015, bank->base +
1885 OMAP24XX_GPIO_SYSCONFIG);
1886 __raw_writel(0x00000000, bank->base +
1887 OMAP24XX_GPIO_DEBOUNCE_EN);
1890 * Initialize interface clock ungated,
1893 __raw_writel(0, bank->base +
1894 OMAP24XX_GPIO_CTRL);
1896 if (cpu_is_omap24xx() &&
1897 i < ARRAY_SIZE(non_wakeup_gpios))
1898 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1903 bank->mod_usage = 0;
1904 /* REVISIT eventually switch from OMAP-specific gpio structs
1905 * over to the generic ones
1907 bank->chip.request = omap_gpio_request;
1908 bank->chip.free = omap_gpio_free;
1909 bank->chip.direction_input = gpio_input;
1910 bank->chip.get = gpio_get;
1911 bank->chip.direction_output = gpio_output;
1912 bank->chip.set = gpio_set;
1913 bank->chip.to_irq = gpio_2irq;
1914 if (bank_is_mpuio(bank)) {
1915 bank->chip.label = "mpuio";
1916 #ifdef CONFIG_ARCH_OMAP16XX
1917 bank->chip.dev = &omap_mpuio_device.dev;
1919 bank->chip.base = OMAP_MPUIO(0);
1921 bank->chip.label = "gpio";
1922 bank->chip.base = gpio;
1925 bank->chip.ngpio = gpio_count;
1927 gpiochip_add(&bank->chip);
1929 for (j = bank->virtual_irq_start;
1930 j < bank->virtual_irq_start + gpio_count; j++) {
1931 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1932 set_irq_chip_data(j, bank);
1933 if (bank_is_mpuio(bank))
1934 set_irq_chip(j, &mpuio_irq_chip);
1936 set_irq_chip(j, &gpio_irq_chip);
1937 set_irq_handler(j, handle_simple_irq);
1938 set_irq_flags(j, IRQF_VALID);
1940 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1941 set_irq_data(bank->irq, bank);
1943 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1944 sprintf(clk_name, "gpio%d_dbck", i + 1);
1945 bank->dbck = clk_get(NULL, clk_name);
1946 if (IS_ERR(bank->dbck))
1947 printk(KERN_ERR "Could not get %s\n", clk_name);
1951 /* Enable system clock for GPIO module.
1952 * The CAM_CLK_CTRL *is* really the right place. */
1953 if (cpu_is_omap16xx())
1954 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1956 /* Enable autoidle for the OCP interface */
1957 if (cpu_is_omap24xx())
1958 omap_writel(1 << 0, 0x48019010);
1959 if (cpu_is_omap34xx())
1960 omap_writel(1 << 0, 0x48306814);
1962 omap_gpio_show_rev();
1967 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1968 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1972 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1975 for (i = 0; i < gpio_bank_count; i++) {
1976 struct gpio_bank *bank = &gpio_bank[i];
1977 void __iomem *wake_status;
1978 void __iomem *wake_clear;
1979 void __iomem *wake_set;
1980 unsigned long flags;
1982 switch (bank->method) {
1983 #ifdef CONFIG_ARCH_OMAP16XX
1984 case METHOD_GPIO_1610:
1985 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1986 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1987 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1990 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1991 case METHOD_GPIO_24XX:
1992 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1993 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1994 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1997 #ifdef CONFIG_ARCH_OMAP4
1998 case METHOD_GPIO_44XX:
1999 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
2000 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2001 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2008 spin_lock_irqsave(&bank->lock, flags);
2009 bank->saved_wakeup = __raw_readl(wake_status);
2010 __raw_writel(0xffffffff, wake_clear);
2011 __raw_writel(bank->suspend_wakeup, wake_set);
2012 spin_unlock_irqrestore(&bank->lock, flags);
2018 static int omap_gpio_resume(struct sys_device *dev)
2022 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
2025 for (i = 0; i < gpio_bank_count; i++) {
2026 struct gpio_bank *bank = &gpio_bank[i];
2027 void __iomem *wake_clear;
2028 void __iomem *wake_set;
2029 unsigned long flags;
2031 switch (bank->method) {
2032 #ifdef CONFIG_ARCH_OMAP16XX
2033 case METHOD_GPIO_1610:
2034 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
2035 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
2038 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
2039 case METHOD_GPIO_24XX:
2040 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
2041 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
2044 #ifdef CONFIG_ARCH_OMAP4
2045 case METHOD_GPIO_44XX:
2046 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2047 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2054 spin_lock_irqsave(&bank->lock, flags);
2055 __raw_writel(0xffffffff, wake_clear);
2056 __raw_writel(bank->saved_wakeup, wake_set);
2057 spin_unlock_irqrestore(&bank->lock, flags);
2063 static struct sysdev_class omap_gpio_sysclass = {
2065 .suspend = omap_gpio_suspend,
2066 .resume = omap_gpio_resume,
2069 static struct sys_device omap_gpio_device = {
2071 .cls = &omap_gpio_sysclass,
2076 #ifdef CONFIG_ARCH_OMAP2PLUS
2078 static int workaround_enabled;
2080 void omap2_gpio_prepare_for_idle(int power_state)
2085 if (cpu_is_omap34xx())
2088 for (i = min; i < gpio_bank_count; i++) {
2089 struct gpio_bank *bank = &gpio_bank[i];
2092 if (bank->dbck_enable_mask)
2093 clk_disable(bank->dbck);
2095 if (power_state > PWRDM_POWER_OFF)
2098 /* If going to OFF, remove triggering for all
2099 * non-wakeup GPIOs. Otherwise spurious IRQs will be
2100 * generated. See OMAP2420 Errata item 1.101. */
2101 if (!(bank->enabled_non_wakeup_gpios))
2104 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2105 bank->saved_datain = __raw_readl(bank->base +
2106 OMAP24XX_GPIO_DATAIN);
2107 l1 = __raw_readl(bank->base +
2108 OMAP24XX_GPIO_FALLINGDETECT);
2109 l2 = __raw_readl(bank->base +
2110 OMAP24XX_GPIO_RISINGDETECT);
2113 if (cpu_is_omap44xx()) {
2114 bank->saved_datain = __raw_readl(bank->base +
2116 l1 = __raw_readl(bank->base +
2117 OMAP4_GPIO_FALLINGDETECT);
2118 l2 = __raw_readl(bank->base +
2119 OMAP4_GPIO_RISINGDETECT);
2122 bank->saved_fallingdetect = l1;
2123 bank->saved_risingdetect = l2;
2124 l1 &= ~bank->enabled_non_wakeup_gpios;
2125 l2 &= ~bank->enabled_non_wakeup_gpios;
2127 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2128 __raw_writel(l1, bank->base +
2129 OMAP24XX_GPIO_FALLINGDETECT);
2130 __raw_writel(l2, bank->base +
2131 OMAP24XX_GPIO_RISINGDETECT);
2134 if (cpu_is_omap44xx()) {
2135 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2136 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2142 workaround_enabled = 0;
2145 workaround_enabled = 1;
2148 void omap2_gpio_resume_after_idle(void)
2153 if (cpu_is_omap34xx())
2155 for (i = min; i < gpio_bank_count; i++) {
2156 struct gpio_bank *bank = &gpio_bank[i];
2157 u32 l, gen, gen0, gen1;
2159 if (bank->dbck_enable_mask)
2160 clk_enable(bank->dbck);
2162 if (!workaround_enabled)
2165 if (!(bank->enabled_non_wakeup_gpios))
2168 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2169 __raw_writel(bank->saved_fallingdetect,
2170 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2171 __raw_writel(bank->saved_risingdetect,
2172 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2173 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2176 if (cpu_is_omap44xx()) {
2177 __raw_writel(bank->saved_fallingdetect,
2178 bank->base + OMAP4_GPIO_FALLINGDETECT);
2179 __raw_writel(bank->saved_risingdetect,
2180 bank->base + OMAP4_GPIO_RISINGDETECT);
2181 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2184 /* Check if any of the non-wakeup interrupt GPIOs have changed
2185 * state. If so, generate an IRQ by software. This is
2186 * horribly racy, but it's the best we can do to work around
2187 * this silicon bug. */
2188 l ^= bank->saved_datain;
2189 l &= bank->enabled_non_wakeup_gpios;
2192 * No need to generate IRQs for the rising edge for gpio IRQs
2193 * configured with falling edge only; and vice versa.
2195 gen0 = l & bank->saved_fallingdetect;
2196 gen0 &= bank->saved_datain;
2198 gen1 = l & bank->saved_risingdetect;
2199 gen1 &= ~(bank->saved_datain);
2201 /* FIXME: Consider GPIO IRQs with level detections properly! */
2202 gen = l & (~(bank->saved_fallingdetect) &
2203 ~(bank->saved_risingdetect));
2204 /* Consider all GPIO IRQs needed to be updated */
2210 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2211 old0 = __raw_readl(bank->base +
2212 OMAP24XX_GPIO_LEVELDETECT0);
2213 old1 = __raw_readl(bank->base +
2214 OMAP24XX_GPIO_LEVELDETECT1);
2215 __raw_writel(old0 | gen, bank->base +
2216 OMAP24XX_GPIO_LEVELDETECT0);
2217 __raw_writel(old1 | gen, bank->base +
2218 OMAP24XX_GPIO_LEVELDETECT1);
2219 __raw_writel(old0, bank->base +
2220 OMAP24XX_GPIO_LEVELDETECT0);
2221 __raw_writel(old1, bank->base +
2222 OMAP24XX_GPIO_LEVELDETECT1);
2225 if (cpu_is_omap44xx()) {
2226 old0 = __raw_readl(bank->base +
2227 OMAP4_GPIO_LEVELDETECT0);
2228 old1 = __raw_readl(bank->base +
2229 OMAP4_GPIO_LEVELDETECT1);
2230 __raw_writel(old0 | l, bank->base +
2231 OMAP4_GPIO_LEVELDETECT0);
2232 __raw_writel(old1 | l, bank->base +
2233 OMAP4_GPIO_LEVELDETECT1);
2234 __raw_writel(old0, bank->base +
2235 OMAP4_GPIO_LEVELDETECT0);
2236 __raw_writel(old1, bank->base +
2237 OMAP4_GPIO_LEVELDETECT1);
2246 #ifdef CONFIG_ARCH_OMAP3
2247 /* save the registers of bank 2-6 */
2248 void omap_gpio_save_context(void)
2252 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2253 for (i = 1; i < gpio_bank_count; i++) {
2254 struct gpio_bank *bank = &gpio_bank[i];
2255 gpio_context[i].sysconfig =
2256 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2257 gpio_context[i].irqenable1 =
2258 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2259 gpio_context[i].irqenable2 =
2260 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2261 gpio_context[i].wake_en =
2262 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2263 gpio_context[i].ctrl =
2264 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2265 gpio_context[i].oe =
2266 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2267 gpio_context[i].leveldetect0 =
2268 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2269 gpio_context[i].leveldetect1 =
2270 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2271 gpio_context[i].risingdetect =
2272 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2273 gpio_context[i].fallingdetect =
2274 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2275 gpio_context[i].dataout =
2276 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2280 /* restore the required registers of bank 2-6 */
2281 void omap_gpio_restore_context(void)
2285 for (i = 1; i < gpio_bank_count; i++) {
2286 struct gpio_bank *bank = &gpio_bank[i];
2287 __raw_writel(gpio_context[i].sysconfig,
2288 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2289 __raw_writel(gpio_context[i].irqenable1,
2290 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2291 __raw_writel(gpio_context[i].irqenable2,
2292 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2293 __raw_writel(gpio_context[i].wake_en,
2294 bank->base + OMAP24XX_GPIO_WAKE_EN);
2295 __raw_writel(gpio_context[i].ctrl,
2296 bank->base + OMAP24XX_GPIO_CTRL);
2297 __raw_writel(gpio_context[i].oe,
2298 bank->base + OMAP24XX_GPIO_OE);
2299 __raw_writel(gpio_context[i].leveldetect0,
2300 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2301 __raw_writel(gpio_context[i].leveldetect1,
2302 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2303 __raw_writel(gpio_context[i].risingdetect,
2304 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2305 __raw_writel(gpio_context[i].fallingdetect,
2306 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2307 __raw_writel(gpio_context[i].dataout,
2308 bank->base + OMAP24XX_GPIO_DATAOUT);
2314 * This may get called early from board specific init
2315 * for boards that have interrupts routed via FPGA.
2317 int __init omap_gpio_init(void)
2320 return _omap_gpio_init();
2325 static int __init omap_gpio_sysinit(void)
2330 ret = _omap_gpio_init();
2334 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2335 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2337 ret = sysdev_class_register(&omap_gpio_sysclass);
2339 ret = sysdev_register(&omap_gpio_device);
2347 arch_initcall(omap_gpio_sysinit);