arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/sched.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/errno.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/irq.h>
  31 #include <linux/io.h>
  32 #include <linux/slab.h>
  33
  34 #include <asm/system.h>
  35 #include <mach/hardware.h>
  36 #include <plat/dma.h>
  37
  38 #include <plat/tc.h>
  39
  40 #undef DEBUG
  41
  42 #ifndef CONFIG_ARCH_OMAP1
  43 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  44         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  45 };
  46
  47 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  48 #endif
  49
  50 #define OMAP_DMA_ACTIVE                 0x01
  51 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  52
  53 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  54
  55 static int enable_1510_mode;
  56
  57 static struct omap_dma_global_context_registers {
  58         u32 dma_irqenable_l0;
  59         u32 dma_ocp_sysconfig;
  60         u32 dma_gcr;
  61 } omap_dma_global_context;
  62
  63 struct omap_dma_lch {
  64         int next_lch;
  65         int dev_id;
  66         u16 saved_csr;
  67         u16 enabled_irqs;
  68         const char *dev_name;
  69         void (*callback)(int lch, u16 ch_status, void *data);
  70         void *data;
  71
  72 #ifndef CONFIG_ARCH_OMAP1
  73         /* required for Dynamic chaining */
  74         int prev_linked_ch;
  75         int next_linked_ch;
  76         int state;
  77         int chain_id;
  78
  79         int status;
  80 #endif
  81         long flags;
  82 };
  83
  84 struct dma_link_info {
  85         int *linked_dmach_q;
  86         int no_of_lchs_linked;
  87
  88         int q_count;
  89         int q_tail;
  90         int q_head;
  91
  92         int chain_state;
  93         int chain_mode;
  94
  95 };
  96
  97 static struct dma_link_info *dma_linked_lch;
  98
  99 #ifndef CONFIG_ARCH_OMAP1
 100
 101 /* Chain handling macros */
 102 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
 103         do {                                                            \
 104                 dma_linked_lch[chain_id].q_head =                       \
 105                 dma_linked_lch[chain_id].q_tail =                       \
 106                 dma_linked_lch[chain_id].q_count = 0;                   \
 107         } while (0)
 108 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 109                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 110                 dma_linked_lch[chain_id].q_count)
 111 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 112         do {                                                            \
 113                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 114                 dma_linked_lch[chain_id].q_count)                       \
 115         } while (0)
 116 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 117                 (0 == dma_linked_lch[chain_id].q_count)
 118 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 119         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 120 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 121         do {                                                            \
 122                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 123                 dma_linked_lch[chain_id].q_count--;                     \
 124         } while (0)
 125
 126 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 127         do {                                                            \
 128                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 129                 dma_linked_lch[chain_id].q_count++; \
 130         } while (0)
 131 #endif
 132
 133 static int dma_lch_count;
 134 static int dma_chan_count;
 135 static int omap_dma_reserve_channels;
 136
 137 static spinlock_t dma_chan_lock;
 138 static struct omap_dma_lch *dma_chan;
 139 static void __iomem *omap_dma_base;
 140
 141 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 142         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 143         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 144         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 145         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 146         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 147 };
 148
 149 static inline void disable_lnk(int lch);
 150 static void omap_disable_channel_irq(int lch);
 151 static inline void omap_enable_channel_irq(int lch);
 152
 153 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 154                                                 __func__);
 155
 156 #define dma_read(reg)                                                   \
 157 ({                                                                      \
 158         u32 __val;                                                      \
 159         if (cpu_class_is_omap1())                                       \
 160                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 161         else                                                            \
 162                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 163         __val;                                                          \
 164 })
 165
 166 #define dma_write(val, reg)                                             \
 167 ({                                                                      \
 168         if (cpu_class_is_omap1())                                       \
 169                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 170         else                                                            \
 171                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 172 })
 173
 174 #ifdef CONFIG_ARCH_OMAP15XX
 175 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 176 int omap_dma_in_1510_mode(void)
 177 {
 178         return enable_1510_mode;
 179 }
 180 #else
 181 #define omap_dma_in_1510_mode()         0
 182 #endif
 183
 184 #ifdef CONFIG_ARCH_OMAP1
 185 static inline int get_gdma_dev(int req)
 186 {
 187         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 188         int shift = ((req - 1) % 5) * 6;
 189
 190         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 191 }
 192
 193 static inline void set_gdma_dev(int req, int dev)
 194 {
 195         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 196         int shift = ((req - 1) % 5) * 6;
 197         u32 l;
 198
 199         l = omap_readl(reg);
 200         l &= ~(0x3f << shift);
 201         l |= (dev - 1) << shift;
 202         omap_writel(l, reg);
 203 }
 204 #else
 205 #define set_gdma_dev(req, dev)  do {} while (0)
 206 #endif
 207
 208 /* Omap1 only */
 209 static void clear_lch_regs(int lch)
 210 {
 211         int i;
 212         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 213
 214         for (i = 0; i < 0x2c; i += 2)
 215                 __raw_writew(0, lch_base + i);
 216 }
 217
 218 void omap_set_dma_priority(int lch, int dst_port, int priority)
 219 {
 220         unsigned long reg;
 221         u32 l;
 222
 223         if (cpu_class_is_omap1()) {
 224                 switch (dst_port) {
 225                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 226                         reg = OMAP_TC_OCPT1_PRIOR;
 227                         break;
 228                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 229                         reg = OMAP_TC_OCPT2_PRIOR;
 230                         break;
 231                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 232                         reg = OMAP_TC_EMIFF_PRIOR;
 233                         break;
 234                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 235                         reg = OMAP_TC_EMIFS_PRIOR;
 236                         break;
 237                 default:
 238                         BUG();
 239                         return;
 240                 }
 241                 l = omap_readl(reg);
 242                 l &= ~(0xf << 8);
 243                 l |= (priority & 0xf) << 8;
 244                 omap_writel(l, reg);
 245         }
 246
 247         if (cpu_class_is_omap2()) {
 248                 u32 ccr;
 249
 250                 ccr = dma_read(CCR(lch));
 251                 if (priority)
 252                         ccr |= (1 << 6);
 253                 else
 254                         ccr &= ~(1 << 6);
 255                 dma_write(ccr, CCR(lch));
 256         }
 257 }
 258 EXPORT_SYMBOL(omap_set_dma_priority);
 259
 260 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 261                                   int frame_count, int sync_mode,
 262                                   int dma_trigger, int src_or_dst_synch)
 263 {
 264         u32 l;
 265
 266         l = dma_read(CSDP(lch));
 267         l &= ~0x03;
 268         l |= data_type;
 269         dma_write(l, CSDP(lch));
 270
 271         if (cpu_class_is_omap1()) {
 272                 u16 ccr;
 273
 274                 ccr = dma_read(CCR(lch));
 275                 ccr &= ~(1 << 5);
 276                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 277                         ccr |= 1 << 5;
 278                 dma_write(ccr, CCR(lch));
 279
 280                 ccr = dma_read(CCR2(lch));
 281                 ccr &= ~(1 << 2);
 282                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 283                         ccr |= 1 << 2;
 284                 dma_write(ccr, CCR2(lch));
 285         }
 286
 287         if (cpu_class_is_omap2() && dma_trigger) {
 288                 u32 val;
 289
 290                 val = dma_read(CCR(lch));
 291
 292                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 293                 val &= ~((3 << 19) | 0x1f);
 294                 val |= (dma_trigger & ~0x1f) << 14;
 295                 val |= dma_trigger & 0x1f;
 296
 297                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 298                         val |= 1 << 5;
 299                 else
 300                         val &= ~(1 << 5);
 301
 302                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 303                         val |= 1 << 18;
 304                 else
 305                         val &= ~(1 << 18);
 306
 307                 if (src_or_dst_synch)
 308                         val |= 1 << 24;         /* source synch */
 309                 else
 310                         val &= ~(1 << 24);      /* dest synch */
 311
 312                 dma_write(val, CCR(lch));
 313         }
 314
 315         dma_write(elem_count, CEN(lch));
 316         dma_write(frame_count, CFN(lch));
 317 }
 318 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 319
 320 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 321 {
 322         BUG_ON(omap_dma_in_1510_mode());
 323
 324         if (cpu_class_is_omap1()) {
 325                 u16 w;
 326
 327                 w = dma_read(CCR2(lch));
 328                 w &= ~0x03;
 329
 330                 switch (mode) {
 331                 case OMAP_DMA_CONSTANT_FILL:
 332                         w |= 0x01;
 333                         break;
 334                 case OMAP_DMA_TRANSPARENT_COPY:
 335                         w |= 0x02;
 336                         break;
 337                 case OMAP_DMA_COLOR_DIS:
 338                         break;
 339                 default:
 340                         BUG();
 341                 }
 342                 dma_write(w, CCR2(lch));
 343
 344                 w = dma_read(LCH_CTRL(lch));
 345                 w &= ~0x0f;
 346                 /* Default is channel type 2D */
 347                 if (mode) {
 348                         dma_write((u16)color, COLOR_L(lch));
 349                         dma_write((u16)(color >> 16), COLOR_U(lch));
 350                         w |= 1;         /* Channel type G */
 351                 }
 352                 dma_write(w, LCH_CTRL(lch));
 353         }
 354
 355         if (cpu_class_is_omap2()) {
 356                 u32 val;
 357
 358                 val = dma_read(CCR(lch));
 359                 val &= ~((1 << 17) | (1 << 16));
 360
 361                 switch (mode) {
 362                 case OMAP_DMA_CONSTANT_FILL:
 363                         val |= 1 << 16;
 364                         break;
 365                 case OMAP_DMA_TRANSPARENT_COPY:
 366                         val |= 1 << 17;
 367                         break;
 368                 case OMAP_DMA_COLOR_DIS:
 369                         break;
 370                 default:
 371                         BUG();
 372                 }
 373                 dma_write(val, CCR(lch));
 374
 375                 color &= 0xffffff;
 376                 dma_write(color, COLOR(lch));
 377         }
 378 }
 379 EXPORT_SYMBOL(omap_set_dma_color_mode);
 380
 381 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 382 {
 383         if (cpu_class_is_omap2()) {
 384                 u32 csdp;
 385
 386                 csdp = dma_read(CSDP(lch));
 387                 csdp &= ~(0x3 << 16);
 388                 csdp |= (mode << 16);
 389                 dma_write(csdp, CSDP(lch));
 390         }
 391 }
 392 EXPORT_SYMBOL(omap_set_dma_write_mode);
 393
 394 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 395 {
 396         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 397                 u32 l;
 398
 399                 l = dma_read(LCH_CTRL(lch));
 400                 l &= ~0x7;
 401                 l |= mode;
 402                 dma_write(l, LCH_CTRL(lch));
 403         }
 404 }
 405 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 406
 407 /* Note that src_port is only for omap1 */
 408 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 409                              unsigned long src_start,
 410                              int src_ei, int src_fi)
 411 {
 412         u32 l;
 413
 414         if (cpu_class_is_omap1()) {
 415                 u16 w;
 416
 417                 w = dma_read(CSDP(lch));
 418                 w &= ~(0x1f << 2);
 419                 w |= src_port << 2;
 420                 dma_write(w, CSDP(lch));
 421         }
 422
 423         l = dma_read(CCR(lch));
 424         l &= ~(0x03 << 12);
 425         l |= src_amode << 12;
 426         dma_write(l, CCR(lch));
 427
 428         if (cpu_class_is_omap1()) {
 429                 dma_write(src_start >> 16, CSSA_U(lch));
 430                 dma_write((u16)src_start, CSSA_L(lch));
 431         }
 432
 433         if (cpu_class_is_omap2())
 434                 dma_write(src_start, CSSA(lch));
 435
 436         dma_write(src_ei, CSEI(lch));
 437         dma_write(src_fi, CSFI(lch));
 438 }
 439 EXPORT_SYMBOL(omap_set_dma_src_params);
 440
 441 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 442 {
 443         omap_set_dma_transfer_params(lch, params->data_type,
 444                                      params->elem_count, params->frame_count,
 445                                      params->sync_mode, params->trigger,
 446                                      params->src_or_dst_synch);
 447         omap_set_dma_src_params(lch, params->src_port,
 448                                 params->src_amode, params->src_start,
 449                                 params->src_ei, params->src_fi);
 450
 451         omap_set_dma_dest_params(lch, params->dst_port,
 452                                  params->dst_amode, params->dst_start,
 453                                  params->dst_ei, params->dst_fi);
 454         if (params->read_prio || params->write_prio)
 455                 omap_dma_set_prio_lch(lch, params->read_prio,
 456                                       params->write_prio);
 457 }
 458 EXPORT_SYMBOL(omap_set_dma_params);
 459
 460 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 461 {
 462         if (cpu_class_is_omap2())
 463                 return;
 464
 465         dma_write(eidx, CSEI(lch));
 466         dma_write(fidx, CSFI(lch));
 467 }
 468 EXPORT_SYMBOL(omap_set_dma_src_index);
 469
 470 void omap_set_dma_src_data_pack(int lch, int enable)
 471 {
 472         u32 l;
 473
 474         l = dma_read(CSDP(lch));
 475         l &= ~(1 << 6);
 476         if (enable)
 477                 l |= (1 << 6);
 478         dma_write(l, CSDP(lch));
 479 }
 480 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 481
 482 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 483 {
 484         unsigned int burst = 0;
 485         u32 l;
 486
 487         l = dma_read(CSDP(lch));
 488         l &= ~(0x03 << 7);
 489
 490         switch (burst_mode) {
 491         case OMAP_DMA_DATA_BURST_DIS:
 492                 break;
 493         case OMAP_DMA_DATA_BURST_4:
 494                 if (cpu_class_is_omap2())
 495                         burst = 0x1;
 496                 else
 497                         burst = 0x2;
 498                 break;
 499         case OMAP_DMA_DATA_BURST_8:
 500                 if (cpu_class_is_omap2()) {
 501                         burst = 0x2;
 502                         break;
 503                 }
 504                 /* not supported by current hardware on OMAP1
 505                  * w |= (0x03 << 7);
 506                  * fall through
 507                  */
 508         case OMAP_DMA_DATA_BURST_16:
 509                 if (cpu_class_is_omap2()) {
 510                         burst = 0x3;
 511                         break;
 512                 }
 513                 /* OMAP1 don't support burst 16
 514                  * fall through
 515                  */
 516         default:
 517                 BUG();
 518         }
 519
 520         l |= (burst << 7);
 521         dma_write(l, CSDP(lch));
 522 }
 523 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 524
 525 /* Note that dest_port is only for OMAP1 */
 526 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 527                               unsigned long dest_start,
 528                               int dst_ei, int dst_fi)
 529 {
 530         u32 l;
 531
 532         if (cpu_class_is_omap1()) {
 533                 l = dma_read(CSDP(lch));
 534                 l &= ~(0x1f << 9);
 535                 l |= dest_port << 9;
 536                 dma_write(l, CSDP(lch));
 537         }
 538
 539         l = dma_read(CCR(lch));
 540         l &= ~(0x03 << 14);
 541         l |= dest_amode << 14;
 542         dma_write(l, CCR(lch));
 543
 544         if (cpu_class_is_omap1()) {
 545                 dma_write(dest_start >> 16, CDSA_U(lch));
 546                 dma_write(dest_start, CDSA_L(lch));
 547         }
 548
 549         if (cpu_class_is_omap2())
 550                 dma_write(dest_start, CDSA(lch));
 551
 552         dma_write(dst_ei, CDEI(lch));
 553         dma_write(dst_fi, CDFI(lch));
 554 }
 555 EXPORT_SYMBOL(omap_set_dma_dest_params);
 556
 557 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 558 {
 559         if (cpu_class_is_omap2())
 560                 return;
 561
 562         dma_write(eidx, CDEI(lch));
 563         dma_write(fidx, CDFI(lch));
 564 }
 565 EXPORT_SYMBOL(omap_set_dma_dest_index);
 566
 567 void omap_set_dma_dest_data_pack(int lch, int enable)
 568 {
 569         u32 l;
 570
 571         l = dma_read(CSDP(lch));
 572         l &= ~(1 << 13);
 573         if (enable)
 574                 l |= 1 << 13;
 575         dma_write(l, CSDP(lch));
 576 }
 577 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 578
 579 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 580 {
 581         unsigned int burst = 0;
 582         u32 l;
 583
 584         l = dma_read(CSDP(lch));
 585         l &= ~(0x03 << 14);
 586
 587         switch (burst_mode) {
 588         case OMAP_DMA_DATA_BURST_DIS:
 589                 break;
 590         case OMAP_DMA_DATA_BURST_4:
 591                 if (cpu_class_is_omap2())
 592                         burst = 0x1;
 593                 else
 594                         burst = 0x2;
 595                 break;
 596         case OMAP_DMA_DATA_BURST_8:
 597                 if (cpu_class_is_omap2())
 598                         burst = 0x2;
 599                 else
 600                         burst = 0x3;
 601                 break;
 602         case OMAP_DMA_DATA_BURST_16:
 603                 if (cpu_class_is_omap2()) {
 604                         burst = 0x3;
 605                         break;
 606                 }
 607                 /* OMAP1 don't support burst 16
 608                  * fall through
 609                  */
 610         default:
 611                 printk(KERN_ERR "Invalid DMA burst mode\n");
 612                 BUG();
 613                 return;
 614         }
 615         l |= (burst << 14);
 616         dma_write(l, CSDP(lch));
 617 }
 618 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 619
 620 static inline void omap_enable_channel_irq(int lch)
 621 {
 622         u32 status;
 623
 624         /* Clear CSR */
 625         if (cpu_class_is_omap1())
 626                 status = dma_read(CSR(lch));
 627         else if (cpu_class_is_omap2())
 628                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 629
 630         /* Enable some nice interrupts. */
 631         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 632 }
 633
 634 static void omap_disable_channel_irq(int lch)
 635 {
 636         if (cpu_class_is_omap2())
 637                 dma_write(0, CICR(lch));
 638 }
 639
 640 void omap_enable_dma_irq(int lch, u16 bits)
 641 {
 642         dma_chan[lch].enabled_irqs |= bits;
 643 }
 644 EXPORT_SYMBOL(omap_enable_dma_irq);
 645
 646 void omap_disable_dma_irq(int lch, u16 bits)
 647 {
 648         dma_chan[lch].enabled_irqs &= ~bits;
 649 }
 650 EXPORT_SYMBOL(omap_disable_dma_irq);
 651
 652 static inline void enable_lnk(int lch)
 653 {
 654         u32 l;
 655
 656         l = dma_read(CLNK_CTRL(lch));
 657
 658         if (cpu_class_is_omap1())
 659                 l &= ~(1 << 14);
 660
 661         /* Set the ENABLE_LNK bits */
 662         if (dma_chan[lch].next_lch != -1)
 663                 l = dma_chan[lch].next_lch | (1 << 15);
 664
 665 #ifndef CONFIG_ARCH_OMAP1
 666         if (cpu_class_is_omap2())
 667                 if (dma_chan[lch].next_linked_ch != -1)
 668                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 669 #endif
 670
 671         dma_write(l, CLNK_CTRL(lch));
 672 }
 673
 674 static inline void disable_lnk(int lch)
 675 {
 676         u32 l;
 677
 678         l = dma_read(CLNK_CTRL(lch));
 679
 680         /* Disable interrupts */
 681         if (cpu_class_is_omap1()) {
 682                 dma_write(0, CICR(lch));
 683                 /* Set the STOP_LNK bit */
 684                 l |= 1 << 14;
 685         }
 686
 687         if (cpu_class_is_omap2()) {
 688                 omap_disable_channel_irq(lch);
 689                 /* Clear the ENABLE_LNK bit */
 690                 l &= ~(1 << 15);
 691         }
 692
 693         dma_write(l, CLNK_CTRL(lch));
 694         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 695 }
 696
 697 static inline void omap2_enable_irq_lch(int lch)
 698 {
 699         u32 val;
 700         unsigned long flags;
 701
 702         if (!cpu_class_is_omap2())
 703                 return;
 704
 705         spin_lock_irqsave(&dma_chan_lock, flags);
 706         val = dma_read(IRQENABLE_L0);
 707         val |= 1 << lch;
 708         dma_write(val, IRQENABLE_L0);
 709         spin_unlock_irqrestore(&dma_chan_lock, flags);
 710 }
 711
 712 static inline void omap2_disable_irq_lch(int lch)
 713 {
 714         u32 val;
 715         unsigned long flags;
 716
 717         if (!cpu_class_is_omap2())
 718                 return;
 719
 720         spin_lock_irqsave(&dma_chan_lock, flags);
 721         val = dma_read(IRQENABLE_L0);
 722         val &= ~(1 << lch);
 723         dma_write(val, IRQENABLE_L0);
 724         spin_unlock_irqrestore(&dma_chan_lock, flags);
 725 }
 726
 727 int omap_request_dma(int dev_id, const char *dev_name,
 728                      void (*callback)(int lch, u16 ch_status, void *data),
 729                      void *data, int *dma_ch_out)
 730 {
 731         int ch, free_ch = -1;
 732         unsigned long flags;
 733         struct omap_dma_lch *chan;
 734
 735         spin_lock_irqsave(&dma_chan_lock, flags);
 736         for (ch = 0; ch < dma_chan_count; ch++) {
 737                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 738                         free_ch = ch;
 739                         if (dev_id == 0)
 740                                 break;
 741                 }
 742         }
 743         if (free_ch == -1) {
 744                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 745                 return -EBUSY;
 746         }
 747         chan = dma_chan + free_ch;
 748         chan->dev_id = dev_id;
 749
 750         if (cpu_class_is_omap1())
 751                 clear_lch_regs(free_ch);
 752
 753         if (cpu_class_is_omap2())
 754                 omap_clear_dma(free_ch);
 755
 756         spin_unlock_irqrestore(&dma_chan_lock, flags);
 757
 758         chan->dev_name = dev_name;
 759         chan->callback = callback;
 760         chan->data = data;
 761         chan->flags = 0;
 762
 763 #ifndef CONFIG_ARCH_OMAP1
 764         if (cpu_class_is_omap2()) {
 765                 chan->chain_id = -1;
 766                 chan->next_linked_ch = -1;
 767         }
 768 #endif
 769
 770         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 771
 772         if (cpu_class_is_omap1())
 773                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 774         else if (cpu_class_is_omap2())
 775                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 776                         OMAP2_DMA_TRANS_ERR_IRQ;
 777
 778         if (cpu_is_omap16xx()) {
 779                 /* If the sync device is set, configure it dynamically. */
 780                 if (dev_id != 0) {
 781                         set_gdma_dev(free_ch + 1, dev_id);
 782                         dev_id = free_ch + 1;
 783                 }
 784                 /*
 785                  * Disable the 1510 compatibility mode and set the sync device
 786                  * id.
 787                  */
 788                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 789         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 790                 dma_write(dev_id, CCR(free_ch));
 791         }
 792
 793         if (cpu_class_is_omap2()) {
 794                 omap2_enable_irq_lch(free_ch);
 795                 omap_enable_channel_irq(free_ch);
 796                 /* Clear the CSR register and IRQ status register */
 797                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 798                 dma_write(1 << free_ch, IRQSTATUS_L0);
 799         }
 800
 801         *dma_ch_out = free_ch;
 802
 803         return 0;
 804 }
 805 EXPORT_SYMBOL(omap_request_dma);
 806
 807 void omap_free_dma(int lch)
 808 {
 809         unsigned long flags;
 810
 811         if (dma_chan[lch].dev_id == -1) {
 812                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 813                        lch);
 814                 return;
 815         }
 816
 817         if (cpu_class_is_omap1()) {
 818                 /* Disable all DMA interrupts for the channel. */
 819                 dma_write(0, CICR(lch));
 820                 /* Make sure the DMA transfer is stopped. */
 821                 dma_write(0, CCR(lch));
 822         }
 823
 824         if (cpu_class_is_omap2()) {
 825                 omap2_disable_irq_lch(lch);
 826
 827                 /* Clear the CSR register and IRQ status register */
 828                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 829                 dma_write(1 << lch, IRQSTATUS_L0);
 830
 831                 /* Disable all DMA interrupts for the channel. */
 832                 dma_write(0, CICR(lch));
 833
 834                 /* Make sure the DMA transfer is stopped. */
 835                 dma_write(0, CCR(lch));
 836                 omap_clear_dma(lch);
 837         }
 838
 839         spin_lock_irqsave(&dma_chan_lock, flags);
 840         dma_chan[lch].dev_id = -1;
 841         dma_chan[lch].next_lch = -1;
 842         dma_chan[lch].callback = NULL;
 843         spin_unlock_irqrestore(&dma_chan_lock, flags);
 844 }
 845 EXPORT_SYMBOL(omap_free_dma);
 846
 847 /**
 848  * @brief omap_dma_set_global_params : Set global priority settings for dma
 849  *
 850  * @param arb_rate
 851  * @param max_fifo_depth
 852  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 853  *                                                 DMA_THREAD_RESERVE_ONET
 854  *                                                 DMA_THREAD_RESERVE_TWOT
 855  *                                                 DMA_THREAD_RESERVE_THREET
 856  */
 857 void
 858 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 859 {
 860         u32 reg;
 861
 862         if (!cpu_class_is_omap2()) {
 863                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 864                 return;
 865         }
 866
 867         if (max_fifo_depth == 0)
 868                 max_fifo_depth = 1;
 869         if (arb_rate == 0)
 870                 arb_rate = 1;
 871
 872         reg = 0xff & max_fifo_depth;
 873         reg |= (0x3 & tparams) << 12;
 874         reg |= (arb_rate & 0xff) << 16;
 875
 876         dma_write(reg, GCR);
 877 }
 878 EXPORT_SYMBOL(omap_dma_set_global_params);
 879
 880 /**
 881  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 882  *
 883  * @param lch
 884  * @param read_prio - Read priority
 885  * @param write_prio - Write priority
 886  * Both of the above can be set with one of the following values :
 887  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 888  */
 889 int
 890 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 891                       unsigned char write_prio)
 892 {
 893         u32 l;
 894
 895         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 896                 printk(KERN_ERR "Invalid channel id\n");
 897                 return -EINVAL;
 898         }
 899         l = dma_read(CCR(lch));
 900         l &= ~((1 << 6) | (1 << 26));
 901         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
 902                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 903         else
 904                 l |= ((read_prio & 0x1) << 6);
 905
 906         dma_write(l, CCR(lch));
 907
 908         return 0;
 909 }
 910 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 911
 912 /*
 913  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 914  * through omap_start_dma(). Any buffers in flight are discarded.
 915  */
 916 void omap_clear_dma(int lch)
 917 {
 918         unsigned long flags;
 919
 920         local_irq_save(flags);
 921
 922         if (cpu_class_is_omap1()) {
 923                 u32 l;
 924
 925                 l = dma_read(CCR(lch));
 926                 l &= ~OMAP_DMA_CCR_EN;
 927                 dma_write(l, CCR(lch));
 928
 929                 /* Clear pending interrupts */
 930                 l = dma_read(CSR(lch));
 931         }
 932
 933         if (cpu_class_is_omap2()) {
 934                 int i;
 935                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 936                 for (i = 0; i < 0x44; i += 4)
 937                         __raw_writel(0, lch_base + i);
 938         }
 939
 940         local_irq_restore(flags);
 941 }
 942 EXPORT_SYMBOL(omap_clear_dma);
 943
 944 void omap_start_dma(int lch)
 945 {
 946         u32 l;
 947
 948         /*
 949          * The CPC/CDAC register needs to be initialized to zero
 950          * before starting dma transfer.
 951          */
 952         if (cpu_is_omap15xx())
 953                 dma_write(0, CPC(lch));
 954         else
 955                 dma_write(0, CDAC(lch));
 956
 957         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 958                 int next_lch, cur_lch;
 959                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 960
 961                 dma_chan_link_map[lch] = 1;
 962                 /* Set the link register of the first channel */
 963                 enable_lnk(lch);
 964
 965                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 966                 cur_lch = dma_chan[lch].next_lch;
 967                 do {
 968                         next_lch = dma_chan[cur_lch].next_lch;
 969
 970                         /* The loop case: we've been here already */
 971                         if (dma_chan_link_map[cur_lch])
 972                                 break;
 973                         /* Mark the current channel */
 974                         dma_chan_link_map[cur_lch] = 1;
 975
 976                         enable_lnk(cur_lch);
 977                         omap_enable_channel_irq(cur_lch);
 978
 979                         cur_lch = next_lch;
 980                 } while (next_lch != -1);
 981         } else if (cpu_is_omap242x() ||
 982                 (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
 983
 984                 /* Errata: Need to write lch even if not using chaining */
 985                 dma_write(lch, CLNK_CTRL(lch));
 986         }
 987
 988         omap_enable_channel_irq(lch);
 989
 990         l = dma_read(CCR(lch));
 991
 992         /*
 993          * Errata: On ES2.0 BUFFERING disable must be set.
 994          * This will always fail on ES1.0
 995          */
 996         if (cpu_is_omap24xx())
 997                 l |= OMAP_DMA_CCR_EN;
 998
 999         l |= OMAP_DMA_CCR_EN;
1000         dma_write(l, CCR(lch));
1001
1002         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1003 }
1004 EXPORT_SYMBOL(omap_start_dma);
1005
1006 void omap_stop_dma(int lch)
1007 {
1008         u32 l;
1009
1010         /* Disable all interrupts on the channel */
1011         if (cpu_class_is_omap1())
1012                 dma_write(0, CICR(lch));
1013
1014         l = dma_read(CCR(lch));
1015         l &= ~OMAP_DMA_CCR_EN;
1016         dma_write(l, CCR(lch));
1017
1018         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
1019                 int next_lch, cur_lch = lch;
1020                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
1021
1022                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
1023                 do {
1024                         /* The loop case: we've been here already */
1025                         if (dma_chan_link_map[cur_lch])
1026                                 break;
1027                         /* Mark the current channel */
1028                         dma_chan_link_map[cur_lch] = 1;
1029
1030                         disable_lnk(cur_lch);
1031
1032                         next_lch = dma_chan[cur_lch].next_lch;
1033                         cur_lch = next_lch;
1034                 } while (next_lch != -1);
1035         }
1036
1037         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1038 }
1039 EXPORT_SYMBOL(omap_stop_dma);
1040
1041 /*
1042  * Allows changing the DMA callback function or data. This may be needed if
1043  * the driver shares a single DMA channel for multiple dma triggers.
1044  */
1045 int omap_set_dma_callback(int lch,
1046                           void (*callback)(int lch, u16 ch_status, void *data),
1047                           void *data)
1048 {
1049         unsigned long flags;
1050
1051         if (lch < 0)
1052                 return -ENODEV;
1053
1054         spin_lock_irqsave(&dma_chan_lock, flags);
1055         if (dma_chan[lch].dev_id == -1) {
1056                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1057                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1058                 return -EINVAL;
1059         }
1060         dma_chan[lch].callback = callback;
1061         dma_chan[lch].data = data;
1062         spin_unlock_irqrestore(&dma_chan_lock, flags);
1063
1064         return 0;
1065 }
1066 EXPORT_SYMBOL(omap_set_dma_callback);
1067
1068 /*
1069  * Returns current physical source address for the given DMA channel.
1070  * If the channel is running the caller must disable interrupts prior calling
1071  * this function and process the returned value before re-enabling interrupt to
1072  * prevent races with the interrupt handler. Note that in continuous mode there
1073  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1074  * in incorrect return value.
1075  */
1076 dma_addr_t omap_get_dma_src_pos(int lch)
1077 {
1078         dma_addr_t offset = 0;
1079
1080         if (cpu_is_omap15xx())
1081                 offset = dma_read(CPC(lch));
1082         else
1083                 offset = dma_read(CSAC(lch));
1084
1085         /*
1086          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1087          * read before the DMA controller finished disabling the channel.
1088          */
1089         if (!cpu_is_omap15xx() && offset == 0)
1090                 offset = dma_read(CSAC(lch));
1091
1092         if (cpu_class_is_omap1())
1093                 offset |= (dma_read(CSSA_U(lch)) << 16);
1094
1095         return offset;
1096 }
1097 EXPORT_SYMBOL(omap_get_dma_src_pos);
1098
1099 /*
1100  * Returns current physical destination address for the given DMA channel.
1101  * If the channel is running the caller must disable interrupts prior calling
1102  * this function and process the returned value before re-enabling interrupt to
1103  * prevent races with the interrupt handler. Note that in continuous mode there
1104  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1105  * in incorrect return value.
1106  */
1107 dma_addr_t omap_get_dma_dst_pos(int lch)
1108 {
1109         dma_addr_t offset = 0;
1110
1111         if (cpu_is_omap15xx())
1112                 offset = dma_read(CPC(lch));
1113         else
1114                 offset = dma_read(CDAC(lch));
1115
1116         /*
1117          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1118          * read before the DMA controller finished disabling the channel.
1119          */
1120         if (!cpu_is_omap15xx() && offset == 0)
1121                 offset = dma_read(CDAC(lch));
1122
1123         if (cpu_class_is_omap1())
1124                 offset |= (dma_read(CDSA_U(lch)) << 16);
1125
1126         return offset;
1127 }
1128 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1129
1130 int omap_get_dma_active_status(int lch)
1131 {
1132         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1133 }
1134 EXPORT_SYMBOL(omap_get_dma_active_status);
1135
1136 int omap_dma_running(void)
1137 {
1138         int lch;
1139
1140         if (cpu_class_is_omap1())
1141                 if (omap_lcd_dma_running())
1142                         return 1;
1143
1144         for (lch = 0; lch < dma_chan_count; lch++)
1145                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1146                         return 1;
1147
1148         return 0;
1149 }
1150
1151 /*
1152  * lch_queue DMA will start right after lch_head one is finished.
1153  * For this DMA link to start, you still need to start (see omap_start_dma)
1154  * the first one. That will fire up the entire queue.
1155  */
1156 void omap_dma_link_lch(int lch_head, int lch_queue)
1157 {
1158         if (omap_dma_in_1510_mode()) {
1159                 if (lch_head == lch_queue) {
1160                         dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1161                                                                 CCR(lch_head));
1162                         return;
1163                 }
1164                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1165                 BUG();
1166                 return;
1167         }
1168
1169         if ((dma_chan[lch_head].dev_id == -1) ||
1170             (dma_chan[lch_queue].dev_id == -1)) {
1171                 printk(KERN_ERR "omap_dma: trying to link "
1172                        "non requested channels\n");
1173                 dump_stack();
1174         }
1175
1176         dma_chan[lch_head].next_lch = lch_queue;
1177 }
1178 EXPORT_SYMBOL(omap_dma_link_lch);
1179
1180 /*
1181  * Once the DMA queue is stopped, we can destroy it.
1182  */
1183 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1184 {
1185         if (omap_dma_in_1510_mode()) {
1186                 if (lch_head == lch_queue) {
1187                         dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1188                                                                 CCR(lch_head));
1189                         return;
1190                 }
1191                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1192                 BUG();
1193                 return;
1194         }
1195
1196         if (dma_chan[lch_head].next_lch != lch_queue ||
1197             dma_chan[lch_head].next_lch == -1) {
1198                 printk(KERN_ERR "omap_dma: trying to unlink "
1199                        "non linked channels\n");
1200                 dump_stack();
1201         }
1202
1203         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1204             (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1205                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1206                        "before unlinking\n");
1207                 dump_stack();
1208         }
1209
1210         dma_chan[lch_head].next_lch = -1;
1211 }
1212 EXPORT_SYMBOL(omap_dma_unlink_lch);
1213
1214 /*----------------------------------------------------------------------------*/
1215
1216 #ifndef CONFIG_ARCH_OMAP1
1217 /* Create chain of DMA channesls */
1218 static void create_dma_lch_chain(int lch_head, int lch_queue)
1219 {
1220         u32 l;
1221
1222         /* Check if this is the first link in chain */
1223         if (dma_chan[lch_head].next_linked_ch == -1) {
1224                 dma_chan[lch_head].next_linked_ch = lch_queue;
1225                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1226                 dma_chan[lch_queue].next_linked_ch = lch_head;
1227                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1228         }
1229
1230         /* a link exists, link the new channel in circular chain */
1231         else {
1232                 dma_chan[lch_queue].next_linked_ch =
1233                                         dma_chan[lch_head].next_linked_ch;
1234                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1235                 dma_chan[lch_head].next_linked_ch = lch_queue;
1236                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1237                                         lch_queue;
1238         }
1239
1240         l = dma_read(CLNK_CTRL(lch_head));
1241         l &= ~(0x1f);
1242         l |= lch_queue;
1243         dma_write(l, CLNK_CTRL(lch_head));
1244
1245         l = dma_read(CLNK_CTRL(lch_queue));
1246         l &= ~(0x1f);
1247         l |= (dma_chan[lch_queue].next_linked_ch);
1248         dma_write(l, CLNK_CTRL(lch_queue));
1249 }
1250
1251 /**
1252  * @brief omap_request_dma_chain : Request a chain of DMA channels
1253  *
1254  * @param dev_id - Device id using the dma channel
1255  * @param dev_name - Device name
1256  * @param callback - Call back function
1257  * @chain_id -
1258  * @no_of_chans - Number of channels requested
1259  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1260  *                                            OMAP_DMA_DYNAMIC_CHAIN
1261  * @params - Channel parameters
1262  *
1263  * @return - Success : 0
1264  *           Failure: -EINVAL/-ENOMEM
1265  */
1266 int omap_request_dma_chain(int dev_id, const char *dev_name,
1267                            void (*callback) (int lch, u16 ch_status,
1268                                              void *data),
1269                            int *chain_id, int no_of_chans, int chain_mode,
1270                            struct omap_dma_channel_params params)
1271 {
1272         int *channels;
1273         int i, err;
1274
1275         /* Is the chain mode valid ? */
1276         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1277                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1278                 printk(KERN_ERR "Invalid chain mode requested\n");
1279                 return -EINVAL;
1280         }
1281
1282         if (unlikely((no_of_chans < 1
1283                         || no_of_chans > dma_lch_count))) {
1284                 printk(KERN_ERR "Invalid Number of channels requested\n");
1285                 return -EINVAL;
1286         }
1287
1288         /* Allocate a queue to maintain the status of the channels
1289          * in the chain */
1290         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1291         if (channels == NULL) {
1292                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1293                 return -ENOMEM;
1294         }
1295
1296         /* request and reserve DMA channels for the chain */
1297         for (i = 0; i < no_of_chans; i++) {
1298                 err = omap_request_dma(dev_id, dev_name,
1299                                         callback, NULL, &channels[i]);
1300                 if (err < 0) {
1301                         int j;
1302                         for (j = 0; j < i; j++)
1303                                 omap_free_dma(channels[j]);
1304                         kfree(channels);
1305                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1306                         return err;
1307                 }
1308                 dma_chan[channels[i]].prev_linked_ch = -1;
1309                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1310
1311                 /*
1312                  * Allowing client drivers to set common parameters now,
1313                  * so that later only relevant (src_start, dest_start
1314                  * and element count) can be set
1315                  */
1316                 omap_set_dma_params(channels[i], &params);
1317         }
1318
1319         *chain_id = channels[0];
1320         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1321         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1322         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1323         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1324
1325         for (i = 0; i < no_of_chans; i++)
1326                 dma_chan[channels[i]].chain_id = *chain_id;
1327
1328         /* Reset the Queue pointers */
1329         OMAP_DMA_CHAIN_QINIT(*chain_id);
1330
1331         /* Set up the chain */
1332         if (no_of_chans == 1)
1333                 create_dma_lch_chain(channels[0], channels[0]);
1334         else {
1335                 for (i = 0; i < (no_of_chans - 1); i++)
1336                         create_dma_lch_chain(channels[i], channels[i + 1]);
1337         }
1338
1339         return 0;
1340 }
1341 EXPORT_SYMBOL(omap_request_dma_chain);
1342
1343 /**
1344  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1345  * params after setting it. Dont do this while dma is running!!
1346  *
1347  * @param chain_id - Chained logical channel id.
1348  * @param params
1349  *
1350  * @return - Success : 0
1351  *           Failure : -EINVAL
1352  */
1353 int omap_modify_dma_chain_params(int chain_id,
1354                                 struct omap_dma_channel_params params)
1355 {
1356         int *channels;
1357         u32 i;
1358
1359         /* Check for input params */
1360         if (unlikely((chain_id < 0
1361                         || chain_id >= dma_lch_count))) {
1362                 printk(KERN_ERR "Invalid chain id\n");
1363                 return -EINVAL;
1364         }
1365
1366         /* Check if the chain exists */
1367         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1368                 printk(KERN_ERR "Chain doesn't exists\n");
1369                 return -EINVAL;
1370         }
1371         channels = dma_linked_lch[chain_id].linked_dmach_q;
1372
1373         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1374                 /*
1375                  * Allowing client drivers to set common parameters now,
1376                  * so that later only relevant (src_start, dest_start
1377                  * and element count) can be set
1378                  */
1379                 omap_set_dma_params(channels[i], &params);
1380         }
1381
1382         return 0;
1383 }
1384 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1385
1386 /**
1387  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1388  *
1389  * @param chain_id
1390  *
1391  * @return - Success : 0
1392  *           Failure : -EINVAL
1393  */
1394 int omap_free_dma_chain(int chain_id)
1395 {
1396         int *channels;
1397         u32 i;
1398
1399         /* Check for input params */
1400         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1401                 printk(KERN_ERR "Invalid chain id\n");
1402                 return -EINVAL;
1403         }
1404
1405         /* Check if the chain exists */
1406         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1407                 printk(KERN_ERR "Chain doesn't exists\n");
1408                 return -EINVAL;
1409         }
1410
1411         channels = dma_linked_lch[chain_id].linked_dmach_q;
1412         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1413                 dma_chan[channels[i]].next_linked_ch = -1;
1414                 dma_chan[channels[i]].prev_linked_ch = -1;
1415                 dma_chan[channels[i]].chain_id = -1;
1416                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1417                 omap_free_dma(channels[i]);
1418         }
1419
1420         kfree(channels);
1421
1422         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1423         dma_linked_lch[chain_id].chain_mode = -1;
1424         dma_linked_lch[chain_id].chain_state = -1;
1425
1426         return (0);
1427 }
1428 EXPORT_SYMBOL(omap_free_dma_chain);
1429
1430 /**
1431  * @brief omap_dma_chain_status - Check if the chain is in
1432  * active / inactive state.
1433  * @param chain_id
1434  *
1435  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1436  *           Failure : -EINVAL
1437  */
1438 int omap_dma_chain_status(int chain_id)
1439 {
1440         /* Check for input params */
1441         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1442                 printk(KERN_ERR "Invalid chain id\n");
1443                 return -EINVAL;
1444         }
1445
1446         /* Check if the chain exists */
1447         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1448                 printk(KERN_ERR "Chain doesn't exists\n");
1449                 return -EINVAL;
1450         }
1451         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1452                         dma_linked_lch[chain_id].q_count);
1453
1454         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1455                 return OMAP_DMA_CHAIN_INACTIVE;
1456
1457         return OMAP_DMA_CHAIN_ACTIVE;
1458 }
1459 EXPORT_SYMBOL(omap_dma_chain_status);
1460
1461 /**
1462  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1463  * set the params and start the transfer.
1464  *
1465  * @param chain_id
1466  * @param src_start - buffer start address
1467  * @param dest_start - Dest address
1468  * @param elem_count
1469  * @param frame_count
1470  * @param callbk_data - channel callback parameter data.
1471  *
1472  * @return  - Success : 0
1473  *            Failure: -EINVAL/-EBUSY
1474  */
1475 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1476                         int elem_count, int frame_count, void *callbk_data)
1477 {
1478         int *channels;
1479         u32 l, lch;
1480         int start_dma = 0;
1481
1482         /*
1483          * if buffer size is less than 1 then there is
1484          * no use of starting the chain
1485          */
1486         if (elem_count < 1) {
1487                 printk(KERN_ERR "Invalid buffer size\n");
1488                 return -EINVAL;
1489         }
1490
1491         /* Check for input params */
1492         if (unlikely((chain_id < 0
1493                         || chain_id >= dma_lch_count))) {
1494                 printk(KERN_ERR "Invalid chain id\n");
1495                 return -EINVAL;
1496         }
1497
1498         /* Check if the chain exists */
1499         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1500                 printk(KERN_ERR "Chain doesn't exist\n");
1501                 return -EINVAL;
1502         }
1503
1504         /* Check if all the channels in chain are in use */
1505         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1506                 return -EBUSY;
1507
1508         /* Frame count may be negative in case of indexed transfers */
1509         channels = dma_linked_lch[chain_id].linked_dmach_q;
1510
1511         /* Get a free channel */
1512         lch = channels[dma_linked_lch[chain_id].q_tail];
1513
1514         /* Store the callback data */
1515         dma_chan[lch].data = callbk_data;
1516
1517         /* Increment the q_tail */
1518         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1519
1520         /* Set the params to the free channel */
1521         if (src_start != 0)
1522                 dma_write(src_start, CSSA(lch));
1523         if (dest_start != 0)
1524                 dma_write(dest_start, CDSA(lch));
1525
1526         /* Write the buffer size */
1527         dma_write(elem_count, CEN(lch));
1528         dma_write(frame_count, CFN(lch));
1529
1530         /*
1531          * If the chain is dynamically linked,
1532          * then we may have to start the chain if its not active
1533          */
1534         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1535
1536                 /*
1537                  * In Dynamic chain, if the chain is not started,
1538                  * queue the channel
1539                  */
1540                 if (dma_linked_lch[chain_id].chain_state ==
1541                                                 DMA_CHAIN_NOTSTARTED) {
1542                         /* Enable the link in previous channel */
1543                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1544                                                                 DMA_CH_QUEUED)
1545                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1546                         dma_chan[lch].state = DMA_CH_QUEUED;
1547                 }
1548
1549                 /*
1550                  * Chain is already started, make sure its active,
1551                  * if not then start the chain
1552                  */
1553                 else {
1554                         start_dma = 1;
1555
1556                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1557                                                         DMA_CH_STARTED) {
1558                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1559                                 dma_chan[lch].state = DMA_CH_QUEUED;
1560                                 start_dma = 0;
1561                                 if (0 == ((1 << 7) & dma_read(
1562                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1563                                         disable_lnk(dma_chan[lch].
1564                                                     prev_linked_ch);
1565                                         pr_debug("\n prev ch is stopped\n");
1566                                         start_dma = 1;
1567                                 }
1568                         }
1569
1570                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1571                                                         == DMA_CH_QUEUED) {
1572                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1573                                 dma_chan[lch].state = DMA_CH_QUEUED;
1574                                 start_dma = 0;
1575                         }
1576                         omap_enable_channel_irq(lch);
1577
1578                         l = dma_read(CCR(lch));
1579
1580                         if ((0 == (l & (1 << 24))))
1581                                 l &= ~(1 << 25);
1582                         else
1583                                 l |= (1 << 25);
1584                         if (start_dma == 1) {
1585                                 if (0 == (l & (1 << 7))) {
1586                                         l |= (1 << 7);
1587                                         dma_chan[lch].state = DMA_CH_STARTED;
1588                                         pr_debug("starting %d\n", lch);
1589                                         dma_write(l, CCR(lch));
1590                                 } else
1591                                         start_dma = 0;
1592                         } else {
1593                                 if (0 == (l & (1 << 7)))
1594                                         dma_write(l, CCR(lch));
1595                         }
1596                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1597                 }
1598         }
1599
1600         return 0;
1601 }
1602 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1603
1604 /**
1605  * @brief omap_start_dma_chain_transfers - Start the chain
1606  *
1607  * @param chain_id
1608  *
1609  * @return - Success : 0
1610  *           Failure : -EINVAL/-EBUSY
1611  */
1612 int omap_start_dma_chain_transfers(int chain_id)
1613 {
1614         int *channels;
1615         u32 l, i;
1616
1617         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1618                 printk(KERN_ERR "Invalid chain id\n");
1619                 return -EINVAL;
1620         }
1621
1622         channels = dma_linked_lch[chain_id].linked_dmach_q;
1623
1624         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1625                 printk(KERN_ERR "Chain is already started\n");
1626                 return -EBUSY;
1627         }
1628
1629         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1630                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1631                                                                         i++) {
1632                         enable_lnk(channels[i]);
1633                         omap_enable_channel_irq(channels[i]);
1634                 }
1635         } else {
1636                 omap_enable_channel_irq(channels[0]);
1637         }
1638
1639         l = dma_read(CCR(channels[0]));
1640         l |= (1 << 7);
1641         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1642         dma_chan[channels[0]].state = DMA_CH_STARTED;
1643
1644         if ((0 == (l & (1 << 24))))
1645                 l &= ~(1 << 25);
1646         else
1647                 l |= (1 << 25);
1648         dma_write(l, CCR(channels[0]));
1649
1650         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1651
1652         return 0;
1653 }
1654 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1655
1656 /**
1657  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1658  *
1659  * @param chain_id
1660  *
1661  * @return - Success : 0
1662  *           Failure : EINVAL
1663  */
1664 int omap_stop_dma_chain_transfers(int chain_id)
1665 {
1666         int *channels;
1667         u32 l, i;
1668         u32 sys_cf;
1669
1670         /* Check for input params */
1671         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1672                 printk(KERN_ERR "Invalid chain id\n");
1673                 return -EINVAL;
1674         }
1675
1676         /* Check if the chain exists */
1677         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1678                 printk(KERN_ERR "Chain doesn't exists\n");
1679                 return -EINVAL;
1680         }
1681         channels = dma_linked_lch[chain_id].linked_dmach_q;
1682
1683         /*
1684          * DMA Errata:
1685          * Special programming model needed to disable DMA before end of block
1686          */
1687         sys_cf = dma_read(OCP_SYSCONFIG);
1688         l = sys_cf;
1689         /* Middle mode reg set no Standby */
1690         l &= ~((1 << 12)|(1 << 13));
1691         dma_write(l, OCP_SYSCONFIG);
1692
1693         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1694
1695                 /* Stop the Channel transmission */
1696                 l = dma_read(CCR(channels[i]));
1697                 l &= ~(1 << 7);
1698                 dma_write(l, CCR(channels[i]));
1699
1700                 /* Disable the link in all the channels */
1701                 disable_lnk(channels[i]);
1702                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1703
1704         }
1705         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1706
1707         /* Reset the Queue pointers */
1708         OMAP_DMA_CHAIN_QINIT(chain_id);
1709
1710         /* Errata - put in the old value */
1711         dma_write(sys_cf, OCP_SYSCONFIG);
1712
1713         return 0;
1714 }
1715 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1716
1717 /* Get the index of the ongoing DMA in chain */
1718 /**
1719  * @brief omap_get_dma_chain_index - Get the element and frame index
1720  * of the ongoing DMA in chain
1721  *
1722  * @param chain_id
1723  * @param ei - Element index
1724  * @param fi - Frame index
1725  *
1726  * @return - Success : 0
1727  *           Failure : -EINVAL
1728  */
1729 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1730 {
1731         int lch;
1732         int *channels;
1733
1734         /* Check for input params */
1735         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1736                 printk(KERN_ERR "Invalid chain id\n");
1737                 return -EINVAL;
1738         }
1739
1740         /* Check if the chain exists */
1741         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1742                 printk(KERN_ERR "Chain doesn't exists\n");
1743                 return -EINVAL;
1744         }
1745         if ((!ei) || (!fi))
1746                 return -EINVAL;
1747
1748         channels = dma_linked_lch[chain_id].linked_dmach_q;
1749
1750         /* Get the current channel */
1751         lch = channels[dma_linked_lch[chain_id].q_head];
1752
1753         *ei = dma_read(CCEN(lch));
1754         *fi = dma_read(CCFN(lch));
1755
1756         return 0;
1757 }
1758 EXPORT_SYMBOL(omap_get_dma_chain_index);
1759
1760 /**
1761  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1762  * ongoing DMA in chain
1763  *
1764  * @param chain_id
1765  *
1766  * @return - Success : Destination position
1767  *           Failure : -EINVAL
1768  */
1769 int omap_get_dma_chain_dst_pos(int chain_id)
1770 {
1771         int lch;
1772         int *channels;
1773
1774         /* Check for input params */
1775         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1776                 printk(KERN_ERR "Invalid chain id\n");
1777                 return -EINVAL;
1778         }
1779
1780         /* Check if the chain exists */
1781         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1782                 printk(KERN_ERR "Chain doesn't exists\n");
1783                 return -EINVAL;
1784         }
1785
1786         channels = dma_linked_lch[chain_id].linked_dmach_q;
1787
1788         /* Get the current channel */
1789         lch = channels[dma_linked_lch[chain_id].q_head];
1790
1791         return dma_read(CDAC(lch));
1792 }
1793 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1794
1795 /**
1796  * @brief omap_get_dma_chain_src_pos - Get the source position
1797  * of the ongoing DMA in chain
1798  * @param chain_id
1799  *
1800  * @return - Success : Destination position
1801  *           Failure : -EINVAL
1802  */
1803 int omap_get_dma_chain_src_pos(int chain_id)
1804 {
1805         int lch;
1806         int *channels;
1807
1808         /* Check for input params */
1809         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1810                 printk(KERN_ERR "Invalid chain id\n");
1811                 return -EINVAL;
1812         }
1813
1814         /* Check if the chain exists */
1815         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1816                 printk(KERN_ERR "Chain doesn't exists\n");
1817                 return -EINVAL;
1818         }
1819
1820         channels = dma_linked_lch[chain_id].linked_dmach_q;
1821
1822         /* Get the current channel */
1823         lch = channels[dma_linked_lch[chain_id].q_head];
1824
1825         return dma_read(CSAC(lch));
1826 }
1827 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1828 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1829
1830 /*----------------------------------------------------------------------------*/
1831
1832 #ifdef CONFIG_ARCH_OMAP1
1833
1834 static int omap1_dma_handle_ch(int ch)
1835 {
1836         u32 csr;
1837
1838         if (enable_1510_mode && ch >= 6) {
1839                 csr = dma_chan[ch].saved_csr;
1840                 dma_chan[ch].saved_csr = 0;
1841         } else
1842                 csr = dma_read(CSR(ch));
1843         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1844                 dma_chan[ch + 6].saved_csr = csr >> 7;
1845                 csr &= 0x7f;
1846         }
1847         if ((csr & 0x3f) == 0)
1848                 return 0;
1849         if (unlikely(dma_chan[ch].dev_id == -1)) {
1850                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1851                        "%d (CSR %04x)\n", ch, csr);
1852                 return 0;
1853         }
1854         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1855                 printk(KERN_WARNING "DMA timeout with device %d\n",
1856                        dma_chan[ch].dev_id);
1857         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1858                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1859                        "with device %d\n", dma_chan[ch].dev_id);
1860         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1861                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1862         if (likely(dma_chan[ch].callback != NULL))
1863                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1864
1865         return 1;
1866 }
1867
1868 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1869 {
1870         int ch = ((int) dev_id) - 1;
1871         int handled = 0;
1872
1873         for (;;) {
1874                 int handled_now = 0;
1875
1876                 handled_now += omap1_dma_handle_ch(ch);
1877                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1878                         handled_now += omap1_dma_handle_ch(ch + 6);
1879                 if (!handled_now)
1880                         break;
1881                 handled += handled_now;
1882         }
1883
1884         return handled ? IRQ_HANDLED : IRQ_NONE;
1885 }
1886
1887 #else
1888 #define omap1_dma_irq_handler   NULL
1889 #endif
1890
1891 #ifdef CONFIG_ARCH_OMAP2PLUS
1892
1893 static int omap2_dma_handle_ch(int ch)
1894 {
1895         u32 status = dma_read(CSR(ch));
1896
1897         if (!status) {
1898                 if (printk_ratelimit())
1899                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1900                                 ch);
1901                 dma_write(1 << ch, IRQSTATUS_L0);
1902                 return 0;
1903         }
1904         if (unlikely(dma_chan[ch].dev_id == -1)) {
1905                 if (printk_ratelimit())
1906                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1907                                         "channel %d\n", status, ch);
1908                 return 0;
1909         }
1910         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1911                 printk(KERN_INFO
1912                        "DMA synchronization event drop occurred with device "
1913                        "%d\n", dma_chan[ch].dev_id);
1914         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1915                 printk(KERN_INFO "DMA transaction error with device %d\n",
1916                        dma_chan[ch].dev_id);
1917                 if (cpu_class_is_omap2()) {
1918                         /* Errata: sDMA Channel is not disabled
1919                          * after a transaction error. So we explicitely
1920                          * disable the channel
1921                          */
1922                         u32 ccr;
1923
1924                         ccr = dma_read(CCR(ch));
1925                         ccr &= ~OMAP_DMA_CCR_EN;
1926                         dma_write(ccr, CCR(ch));
1927                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1928                 }
1929         }
1930         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1931                 printk(KERN_INFO "DMA secure error with device %d\n",
1932                        dma_chan[ch].dev_id);
1933         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1934                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1935                        dma_chan[ch].dev_id);
1936
1937         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1938         dma_write(1 << ch, IRQSTATUS_L0);
1939
1940         /* If the ch is not chained then chain_id will be -1 */
1941         if (dma_chan[ch].chain_id != -1) {
1942                 int chain_id = dma_chan[ch].chain_id;
1943                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1944                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1945                         dma_chan[dma_chan[ch].next_linked_ch].state =
1946                                                         DMA_CH_STARTED;
1947                 if (dma_linked_lch[chain_id].chain_mode ==
1948                                                 OMAP_DMA_DYNAMIC_CHAIN)
1949                         disable_lnk(ch);
1950
1951                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1952                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1953
1954                 status = dma_read(CSR(ch));
1955         }
1956
1957         dma_write(status, CSR(ch));
1958
1959         if (likely(dma_chan[ch].callback != NULL))
1960                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1961
1962         return 0;
1963 }
1964
1965 /* STATUS register count is from 1-32 while our is 0-31 */
1966 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1967 {
1968         u32 val, enable_reg;
1969         int i;
1970
1971         val = dma_read(IRQSTATUS_L0);
1972         if (val == 0) {
1973                 if (printk_ratelimit())
1974                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1975                 return IRQ_HANDLED;
1976         }
1977         enable_reg = dma_read(IRQENABLE_L0);
1978         val &= enable_reg; /* Dispatch only relevant interrupts */
1979         for (i = 0; i < dma_lch_count && val != 0; i++) {
1980                 if (val & 1)
1981                         omap2_dma_handle_ch(i);
1982                 val >>= 1;
1983         }
1984
1985         return IRQ_HANDLED;
1986 }
1987
1988 static struct irqaction omap24xx_dma_irq = {
1989         .name = "DMA",
1990         .handler = omap2_dma_irq_handler,
1991         .flags = IRQF_DISABLED
1992 };
1993
1994 #else
1995 static struct irqaction omap24xx_dma_irq;
1996 #endif
1997
1998 /*----------------------------------------------------------------------------*/
1999
2000 void omap_dma_global_context_save(void)
2001 {
2002         omap_dma_global_context.dma_irqenable_l0 =
2003                 dma_read(IRQENABLE_L0);
2004         omap_dma_global_context.dma_ocp_sysconfig =
2005                 dma_read(OCP_SYSCONFIG);
2006         omap_dma_global_context.dma_gcr = dma_read(GCR);
2007 }
2008
2009 void omap_dma_global_context_restore(void)
2010 {
2011         int ch;
2012
2013         dma_write(omap_dma_global_context.dma_gcr, GCR);
2014         dma_write(omap_dma_global_context.dma_ocp_sysconfig,
2015                 OCP_SYSCONFIG);
2016         dma_write(omap_dma_global_context.dma_irqenable_l0,
2017                 IRQENABLE_L0);
2018
2019         /*
2020          * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
2021          * after secure sram context save and restore. Hence we need to
2022          * manually clear those IRQs to avoid spurious interrupts. This
2023          * affects only secure devices.
2024          */
2025         if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
2026                 dma_write(0x3 , IRQSTATUS_L0);
2027
2028         for (ch = 0; ch < dma_chan_count; ch++)
2029                 if (dma_chan[ch].dev_id != -1)
2030                         omap_clear_dma(ch);
2031 }
2032
2033 /*----------------------------------------------------------------------------*/
2034
2035 static int __init omap_init_dma(void)
2036 {
2037         unsigned long base;
2038         int ch, r;
2039
2040         if (cpu_class_is_omap1()) {
2041                 base = OMAP1_DMA_BASE;
2042                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2043         } else if (cpu_is_omap24xx()) {
2044                 base = OMAP24XX_DMA4_BASE;
2045                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2046         } else if (cpu_is_omap34xx()) {
2047                 base = OMAP34XX_DMA4_BASE;
2048                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2049         } else if (cpu_is_omap44xx()) {
2050                 base = OMAP44XX_DMA4_BASE;
2051                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2052         } else {
2053                 pr_err("DMA init failed for unsupported omap\n");
2054                 return -ENODEV;
2055         }
2056
2057         omap_dma_base = ioremap(base, SZ_4K);
2058         BUG_ON(!omap_dma_base);
2059
2060         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2061                         && (omap_dma_reserve_channels <= dma_lch_count))
2062                 dma_lch_count = omap_dma_reserve_channels;
2063
2064         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2065                                 GFP_KERNEL);
2066         if (!dma_chan) {
2067                 r = -ENOMEM;
2068                 goto out_unmap;
2069         }
2070
2071         if (cpu_class_is_omap2()) {
2072                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2073                                                 dma_lch_count, GFP_KERNEL);
2074                 if (!dma_linked_lch) {
2075                         r = -ENOMEM;
2076                         goto out_free;
2077                 }
2078         }
2079
2080         if (cpu_is_omap15xx()) {
2081                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2082                 dma_chan_count = 9;
2083                 enable_1510_mode = 1;
2084         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2085                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2086                        dma_read(HW_ID));
2087                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2088                        (dma_read(CAPS_0_U) << 16) |
2089                        dma_read(CAPS_0_L),
2090                        (dma_read(CAPS_1_U) << 16) |
2091                        dma_read(CAPS_1_L),
2092                        dma_read(CAPS_2), dma_read(CAPS_3),
2093                        dma_read(CAPS_4));
2094                 if (!enable_1510_mode) {
2095                         u16 w;
2096
2097                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2098                         w = dma_read(GSCR);
2099                         w |= 1 << 3;
2100                         dma_write(w, GSCR);
2101                         dma_chan_count = 16;
2102                 } else
2103                         dma_chan_count = 9;
2104         } else if (cpu_class_is_omap2()) {
2105                 u8 revision = dma_read(REVISION) & 0xff;
2106                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2107                        revision >> 4, revision & 0xf);
2108                 dma_chan_count = dma_lch_count;
2109         } else {
2110                 dma_chan_count = 0;
2111                 return 0;
2112         }
2113
2114         spin_lock_init(&dma_chan_lock);
2115
2116         for (ch = 0; ch < dma_chan_count; ch++) {
2117                 omap_clear_dma(ch);
2118                 if (cpu_class_is_omap2())
2119                         omap2_disable_irq_lch(ch);
2120
2121                 dma_chan[ch].dev_id = -1;
2122                 dma_chan[ch].next_lch = -1;
2123
2124                 if (ch >= 6 && enable_1510_mode)
2125                         continue;
2126
2127                 if (cpu_class_is_omap1()) {
2128                         /*
2129                          * request_irq() doesn't like dev_id (ie. ch) being
2130                          * zero, so we have to kludge around this.
2131                          */
2132                         r = request_irq(omap1_dma_irq[ch],
2133                                         omap1_dma_irq_handler, 0, "DMA",
2134                                         (void *) (ch + 1));
2135                         if (r != 0) {
2136                                 int i;
2137
2138                                 printk(KERN_ERR "unable to request IRQ %d "
2139                                        "for DMA (error %d)\n",
2140                                        omap1_dma_irq[ch], r);
2141                                 for (i = 0; i < ch; i++)
2142                                         free_irq(omap1_dma_irq[i],
2143                                                  (void *) (i + 1));
2144                                 goto out_free;
2145                         }
2146                 }
2147         }
2148
2149         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2150                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2151                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2152
2153         if (cpu_class_is_omap2()) {
2154                 int irq;
2155                 if (cpu_is_omap44xx())
2156                         irq = OMAP44XX_IRQ_SDMA_0;
2157                 else
2158                         irq = INT_24XX_SDMA_IRQ0;
2159                 setup_irq(irq, &omap24xx_dma_irq);
2160         }
2161
2162         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
2163                 /* Enable smartidle idlemodes and autoidle */
2164                 u32 v = dma_read(OCP_SYSCONFIG);
2165                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2166                                 DMA_SYSCONFIG_SIDLEMODE_MASK |
2167                                 DMA_SYSCONFIG_AUTOIDLE);
2168                 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2169                         DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2170                         DMA_SYSCONFIG_AUTOIDLE);
2171                 dma_write(v , OCP_SYSCONFIG);
2172                 /* reserve dma channels 0 and 1 in high security devices */
2173                 if (cpu_is_omap34xx() &&
2174                         (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2175                         printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2176                                         "HS ROM code\n");
2177                         dma_chan[0].dev_id = 0;
2178                         dma_chan[1].dev_id = 1;
2179                 }
2180         }
2181
2182         return 0;
2183
2184 out_free:
2185         kfree(dma_chan);
2186
2187 out_unmap:
2188         iounmap(omap_dma_base);
2189
2190         return r;
2191 }
2192
2193 arch_initcall(omap_init_dma);
2194
2195 /*
2196  * Reserve the omap SDMA channels using cmdline bootarg
2197  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2198  */
2199 static int __init omap_dma_cmdline_reserve_ch(char *str)
2200 {
2201         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2202                 omap_dma_reserve_channels = 0;
2203         return 1;
2204 }
2205
2206 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2207
2208