arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/io.h>
  29 #include <linux/smsc911x.h>
  30 #include <linux/ata_platform.h>
  31 #include <linux/amba/mmci.h>
  32 #include <linux/gfp.h>
  33
  34 #include <asm/clkdev.h>
  35 #include <asm/system.h>
  36 #include <mach/hardware.h>
  37 #include <asm/irq.h>
  38 #include <asm/leds.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/hardware/arm_timer.h>
  41 #include <asm/hardware/icst.h>
  42
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/flash.h>
  45 #include <asm/mach/irq.h>
  46 #include <asm/mach/map.h>
  47
  48 #include <asm/hardware/gic.h>
  49
  50 #include <mach/clkdev.h>
  51 #include <mach/platform.h>
  52 #include <mach/irqs.h>
  53 #include <plat/timer-sp.h>
  54
  55 #include "core.h"
  56
  57 /* used by entry-macro.S and platsmp.c */
  58 void __iomem *gic_cpu_base_addr;
  59
  60 #ifdef CONFIG_ZONE_DMA
  61 /*
  62  * Adjust the zones if there are restrictions for DMA access.
  63  */
  64 void __init realview_adjust_zones(int node, unsigned long *size,
  65                                   unsigned long *hole)
  66 {
  67         unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
  68
  69         if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
  70                 return;
  71
  72         size[ZONE_NORMAL] = size[0] - dma_size;
  73         size[ZONE_DMA] = dma_size;
  74         hole[ZONE_NORMAL] = hole[0];
  75         hole[ZONE_DMA] = 0;
  76 }
  77 #endif
  78
  79
  80 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  81
  82 static int realview_flash_init(void)
  83 {
  84         u32 val;
  85
  86         val = __raw_readl(REALVIEW_FLASHCTRL);
  87         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  88         __raw_writel(val, REALVIEW_FLASHCTRL);
  89
  90         return 0;
  91 }
  92
  93 static void realview_flash_exit(void)
  94 {
  95         u32 val;
  96
  97         val = __raw_readl(REALVIEW_FLASHCTRL);
  98         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  99         __raw_writel(val, REALVIEW_FLASHCTRL);
 100 }
 101
 102 static void realview_flash_set_vpp(int on)
 103 {
 104         u32 val;
 105
 106         val = __raw_readl(REALVIEW_FLASHCTRL);
 107         if (on)
 108                 val |= REALVIEW_FLASHPROG_FLVPPEN;
 109         else
 110                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 111         __raw_writel(val, REALVIEW_FLASHCTRL);
 112 }
 113
 114 static struct flash_platform_data realview_flash_data = {
 115         .map_name               = "cfi_probe",
 116         .width                  = 4,
 117         .init                   = realview_flash_init,
 118         .exit                   = realview_flash_exit,
 119         .set_vpp                = realview_flash_set_vpp,
 120 };
 121
 122 struct platform_device realview_flash_device = {
 123         .name                   = "armflash",
 124         .id                     = 0,
 125         .dev                    = {
 126                 .platform_data  = &realview_flash_data,
 127         },
 128 };
 129
 130 int realview_flash_register(struct resource *res, u32 num)
 131 {
 132         realview_flash_device.resource = res;
 133         realview_flash_device.num_resources = num;
 134         return platform_device_register(&realview_flash_device);
 135 }
 136
 137 static struct smsc911x_platform_config smsc911x_config = {
 138         .flags          = SMSC911X_USE_32BIT,
 139         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
 140         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
 141         .phy_interface  = PHY_INTERFACE_MODE_MII,
 142 };
 143
 144 static struct platform_device realview_eth_device = {
 145         .name           = "smsc911x",
 146         .id             = 0,
 147         .num_resources  = 2,
 148 };
 149
 150 int realview_eth_register(const char *name, struct resource *res)
 151 {
 152         if (name)
 153                 realview_eth_device.name = name;
 154         realview_eth_device.resource = res;
 155         if (strcmp(realview_eth_device.name, "smsc911x") == 0)
 156                 realview_eth_device.dev.platform_data = &smsc911x_config;
 157
 158         return platform_device_register(&realview_eth_device);
 159 }
 160
 161 struct platform_device realview_usb_device = {
 162         .name                   = "isp1760",
 163         .num_resources          = 2,
 164 };
 165
 166 int realview_usb_register(struct resource *res)
 167 {
 168         realview_usb_device.resource = res;
 169         return platform_device_register(&realview_usb_device);
 170 }
 171
 172 static struct pata_platform_info pata_platform_data = {
 173         .ioport_shift           = 1,
 174 };
 175
 176 static struct resource pata_resources[] = {
 177         [0] = {
 178                 .start          = REALVIEW_CF_BASE,
 179                 .end            = REALVIEW_CF_BASE + 0xff,
 180                 .flags          = IORESOURCE_MEM,
 181         },
 182         [1] = {
 183                 .start          = REALVIEW_CF_BASE + 0x100,
 184                 .end            = REALVIEW_CF_BASE + SZ_4K - 1,
 185                 .flags          = IORESOURCE_MEM,
 186         },
 187 };
 188
 189 struct platform_device realview_cf_device = {
 190         .name                   = "pata_platform",
 191         .id                     = -1,
 192         .num_resources          = ARRAY_SIZE(pata_resources),
 193         .resource               = pata_resources,
 194         .dev                    = {
 195                 .platform_data  = &pata_platform_data,
 196         },
 197 };
 198
 199 static struct resource realview_i2c_resource = {
 200         .start          = REALVIEW_I2C_BASE,
 201         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 202         .flags          = IORESOURCE_MEM,
 203 };
 204
 205 struct platform_device realview_i2c_device = {
 206         .name           = "versatile-i2c",
 207         .id             = 0,
 208         .num_resources  = 1,
 209         .resource       = &realview_i2c_resource,
 210 };
 211
 212 static struct i2c_board_info realview_i2c_board_info[] = {
 213         {
 214                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 215         },
 216 };
 217
 218 static int __init realview_i2c_init(void)
 219 {
 220         return i2c_register_board_info(0, realview_i2c_board_info,
 221                                        ARRAY_SIZE(realview_i2c_board_info));
 222 }
 223 arch_initcall(realview_i2c_init);
 224
 225 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 226
 227 /*
 228  * This is only used if GPIOLIB support is disabled
 229  */
 230 static unsigned int realview_mmc_status(struct device *dev)
 231 {
 232         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 233         u32 mask;
 234
 235         if (machine_is_realview_pb1176()) {
 236                 static bool inserted = false;
 237
 238                 /*
 239                  * The PB1176 does not have the status register,
 240                  * assume it is inserted at startup, then invert
 241                  * for each call so card insertion/removal will
 242                  * be detected anyway. This will not be called if
 243                  * GPIO on PL061 is active, which is the proper
 244                  * way to do this on the PB1176.
 245                  */
 246                 inserted = !inserted;
 247                 return inserted ? 0 : 1;
 248         }
 249
 250         if (adev->res.start == REALVIEW_MMCI0_BASE)
 251                 mask = 1;
 252         else
 253                 mask = 2;
 254
 255         return !(readl(REALVIEW_SYSMCI) & mask);
 256 }
 257
 258 struct mmci_platform_data realview_mmc0_plat_data = {
 259         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 260         .status         = realview_mmc_status,
 261         .gpio_wp        = 17,
 262         .gpio_cd        = 16,
 263 };
 264
 265 struct mmci_platform_data realview_mmc1_plat_data = {
 266         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 267         .status         = realview_mmc_status,
 268         .gpio_wp        = 19,
 269         .gpio_cd        = 18,
 270 };
 271
 272 /*
 273  * Clock handling
 274  */
 275 static const struct icst_params realview_oscvco_params = {
 276         .ref            = 24000000,
 277         .vco_max        = ICST307_VCO_MAX,
 278         .vco_min        = ICST307_VCO_MIN,
 279         .vd_min         = 4 + 8,
 280         .vd_max         = 511 + 8,
 281         .rd_min         = 1 + 2,
 282         .rd_max         = 127 + 2,
 283         .s2div          = icst307_s2div,
 284         .idx2s          = icst307_idx2s,
 285 };
 286
 287 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
 288 {
 289         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 290         u32 val;
 291
 292         val = readl(clk->vcoreg) & ~0x7ffff;
 293         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 294
 295         writel(0xa05f, sys_lock);
 296         writel(val, clk->vcoreg);
 297         writel(0, sys_lock);
 298 }
 299
 300 static const struct clk_ops oscvco_clk_ops = {
 301         .round  = icst_clk_round,
 302         .set    = icst_clk_set,
 303         .setvco = realview_oscvco_set,
 304 };
 305
 306 static struct clk oscvco_clk = {
 307         .ops    = &oscvco_clk_ops,
 308         .params = &realview_oscvco_params,
 309 };
 310
 311 /*
 312  * These are fixed clocks.
 313  */
 314 static struct clk ref24_clk = {
 315         .rate   = 24000000,
 316 };
 317
 318 static struct clk_lookup lookups[] = {
 319         {       /* UART0 */
 320                 .dev_id         = "dev:uart0",
 321                 .clk            = &ref24_clk,
 322         }, {    /* UART1 */
 323                 .dev_id         = "dev:uart1",
 324                 .clk            = &ref24_clk,
 325         }, {    /* UART2 */
 326                 .dev_id         = "dev:uart2",
 327                 .clk            = &ref24_clk,
 328         }, {    /* UART3 */
 329                 .dev_id         = "fpga:uart3",
 330                 .clk            = &ref24_clk,
 331         }, {    /* UART3 is on the dev chip in PB1176 */
 332                 .dev_id         = "dev:uart3",
 333                 .clk            = &ref24_clk,
 334         }, {    /* UART4 only exists in PB1176 */
 335                 .dev_id         = "fpga:uart4",
 336                 .clk            = &ref24_clk,
 337         }, {    /* KMI0 */
 338                 .dev_id         = "fpga:kmi0",
 339                 .clk            = &ref24_clk,
 340         }, {    /* KMI1 */
 341                 .dev_id         = "fpga:kmi1",
 342                 .clk            = &ref24_clk,
 343         }, {    /* MMC0 */
 344                 .dev_id         = "fpga:mmc0",
 345                 .clk            = &ref24_clk,
 346         }, {    /* CLCD is in the PB1176 and EB DevChip */
 347                 .dev_id         = "dev:clcd",
 348                 .clk            = &oscvco_clk,
 349         }, {    /* PB:CLCD */
 350                 .dev_id         = "issp:clcd",
 351                 .clk            = &oscvco_clk,
 352         }
 353 };
 354
 355 static int __init clk_init(void)
 356 {
 357         if (machine_is_realview_pb1176())
 358                 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
 359         else
 360                 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 361
 362         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 363
 364         return 0;
 365 }
 366 arch_initcall(clk_init);
 367
 368 /*
 369  * CLCD support.
 370  */
 371 #define SYS_CLCD_NLCDIOON       (1 << 2)
 372 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 373 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 374 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 375 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 376 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 377 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 378 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 379 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 380
 381 static struct clcd_panel vga = {
 382         .mode           = {
 383                 .name           = "VGA",
 384                 .refresh        = 60,
 385                 .xres           = 640,
 386                 .yres           = 480,
 387                 .pixclock       = 39721,
 388                 .left_margin    = 40,
 389                 .right_margin   = 24,
 390                 .upper_margin   = 32,
 391                 .lower_margin   = 11,
 392                 .hsync_len      = 96,
 393                 .vsync_len      = 2,
 394                 .sync           = 0,
 395                 .vmode          = FB_VMODE_NONINTERLACED,
 396         },
 397         .width          = -1,
 398         .height         = -1,
 399         .tim2           = TIM2_BCD | TIM2_IPC,
 400         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 401         .bpp            = 16,
 402 };
 403
 404 static struct clcd_panel xvga = {
 405         .mode           = {
 406                 .name           = "XVGA",
 407                 .refresh        = 60,
 408                 .xres           = 1024,
 409                 .yres           = 768,
 410                 .pixclock       = 15748,
 411                 .left_margin    = 152,
 412                 .right_margin   = 48,
 413                 .upper_margin   = 23,
 414                 .lower_margin   = 3,
 415                 .hsync_len      = 104,
 416                 .vsync_len      = 4,
 417                 .sync           = 0,
 418                 .vmode          = FB_VMODE_NONINTERLACED,
 419         },
 420         .width          = -1,
 421         .height         = -1,
 422         .tim2           = TIM2_BCD | TIM2_IPC,
 423         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 424         .bpp            = 16,
 425 };
 426
 427 static struct clcd_panel sanyo_3_8_in = {
 428         .mode           = {
 429                 .name           = "Sanyo QVGA",
 430                 .refresh        = 116,
 431                 .xres           = 320,
 432                 .yres           = 240,
 433                 .pixclock       = 100000,
 434                 .left_margin    = 6,
 435                 .right_margin   = 6,
 436                 .upper_margin   = 5,
 437                 .lower_margin   = 5,
 438                 .hsync_len      = 6,
 439                 .vsync_len      = 6,
 440                 .sync           = 0,
 441                 .vmode          = FB_VMODE_NONINTERLACED,
 442         },
 443         .width          = -1,
 444         .height         = -1,
 445         .tim2           = TIM2_BCD,
 446         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 447         .bpp            = 16,
 448 };
 449
 450 static struct clcd_panel sanyo_2_5_in = {
 451         .mode           = {
 452                 .name           = "Sanyo QVGA Portrait",
 453                 .refresh        = 116,
 454                 .xres           = 240,
 455                 .yres           = 320,
 456                 .pixclock       = 100000,
 457                 .left_margin    = 20,
 458                 .right_margin   = 10,
 459                 .upper_margin   = 2,
 460                 .lower_margin   = 2,
 461                 .hsync_len      = 10,
 462                 .vsync_len      = 2,
 463                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 464                 .vmode          = FB_VMODE_NONINTERLACED,
 465         },
 466         .width          = -1,
 467         .height         = -1,
 468         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 469         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 470         .bpp            = 16,
 471 };
 472
 473 static struct clcd_panel epson_2_2_in = {
 474         .mode           = {
 475                 .name           = "Epson QCIF",
 476                 .refresh        = 390,
 477                 .xres           = 176,
 478                 .yres           = 220,
 479                 .pixclock       = 62500,
 480                 .left_margin    = 3,
 481                 .right_margin   = 2,
 482                 .upper_margin   = 1,
 483                 .lower_margin   = 0,
 484                 .hsync_len      = 3,
 485                 .vsync_len      = 2,
 486                 .sync           = 0,
 487                 .vmode          = FB_VMODE_NONINTERLACED,
 488         },
 489         .width          = -1,
 490         .height         = -1,
 491         .tim2           = TIM2_BCD | TIM2_IPC,
 492         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 493         .bpp            = 16,
 494 };
 495
 496 /*
 497  * Detect which LCD panel is connected, and return the appropriate
 498  * clcd_panel structure.  Note: we do not have any information on
 499  * the required timings for the 8.4in panel, so we presently assume
 500  * VGA timings.
 501  */
 502 static struct clcd_panel *realview_clcd_panel(void)
 503 {
 504         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 505         struct clcd_panel *vga_panel;
 506         struct clcd_panel *panel;
 507         u32 val;
 508
 509         if (machine_is_realview_eb())
 510                 vga_panel = &vga;
 511         else
 512                 vga_panel = &xvga;
 513
 514         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 515         if (val == SYS_CLCD_ID_SANYO_3_8)
 516                 panel = &sanyo_3_8_in;
 517         else if (val == SYS_CLCD_ID_SANYO_2_5)
 518                 panel = &sanyo_2_5_in;
 519         else if (val == SYS_CLCD_ID_EPSON_2_2)
 520                 panel = &epson_2_2_in;
 521         else if (val == SYS_CLCD_ID_VGA)
 522                 panel = vga_panel;
 523         else {
 524                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 525                         val);
 526                 panel = vga_panel;
 527         }
 528
 529         return panel;
 530 }
 531
 532 /*
 533  * Disable all display connectors on the interface module.
 534  */
 535 static void realview_clcd_disable(struct clcd_fb *fb)
 536 {
 537         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 538         u32 val;
 539
 540         val = readl(sys_clcd);
 541         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 542         writel(val, sys_clcd);
 543 }
 544
 545 /*
 546  * Enable the relevant connector on the interface module.
 547  */
 548 static void realview_clcd_enable(struct clcd_fb *fb)
 549 {
 550         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 551         u32 val;
 552
 553         /*
 554          * Enable the PSUs
 555          */
 556         val = readl(sys_clcd);
 557         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 558         writel(val, sys_clcd);
 559 }
 560
 561 static int realview_clcd_setup(struct clcd_fb *fb)
 562 {
 563         unsigned long framesize;
 564         dma_addr_t dma;
 565
 566         if (machine_is_realview_eb())
 567                 /* VGA, 16bpp */
 568                 framesize = 640 * 480 * 2;
 569         else
 570                 /* XVGA, 16bpp */
 571                 framesize = 1024 * 768 * 2;
 572
 573         fb->panel               = realview_clcd_panel();
 574
 575         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 576                                                     &dma, GFP_KERNEL | GFP_DMA);
 577         if (!fb->fb.screen_base) {
 578                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 579                 return -ENOMEM;
 580         }
 581
 582         fb->fb.fix.smem_start   = dma;
 583         fb->fb.fix.smem_len     = framesize;
 584
 585         return 0;
 586 }
 587
 588 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 589 {
 590         return dma_mmap_writecombine(&fb->dev->dev, vma,
 591                                      fb->fb.screen_base,
 592                                      fb->fb.fix.smem_start,
 593                                      fb->fb.fix.smem_len);
 594 }
 595
 596 static void realview_clcd_remove(struct clcd_fb *fb)
 597 {
 598         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 599                               fb->fb.screen_base, fb->fb.fix.smem_start);
 600 }
 601
 602 struct clcd_board clcd_plat_data = {
 603         .name           = "RealView",
 604         .check          = clcdfb_check,
 605         .decode         = clcdfb_decode,
 606         .disable        = realview_clcd_disable,
 607         .enable         = realview_clcd_enable,
 608         .setup          = realview_clcd_setup,
 609         .mmap           = realview_clcd_mmap,
 610         .remove         = realview_clcd_remove,
 611 };
 612
 613 #ifdef CONFIG_LEDS
 614 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 615
 616 void realview_leds_event(led_event_t ledevt)
 617 {
 618         unsigned long flags;
 619         u32 val;
 620         u32 led = 1 << smp_processor_id();
 621
 622         local_irq_save(flags);
 623         val = readl(VA_LEDS_BASE);
 624
 625         switch (ledevt) {
 626         case led_idle_start:
 627                 val = val & ~led;
 628                 break;
 629
 630         case led_idle_end:
 631                 val = val | led;
 632                 break;
 633
 634         case led_timer:
 635                 val = val ^ REALVIEW_SYS_LED7;
 636                 break;
 637
 638         case led_halted:
 639                 val = 0;
 640                 break;
 641
 642         default:
 643                 break;
 644         }
 645
 646         writel(val, VA_LEDS_BASE);
 647         local_irq_restore(flags);
 648 }
 649 #endif  /* CONFIG_LEDS */
 650
 651 /*
 652  * Where is the timer (VA)?
 653  */
 654 void __iomem *timer0_va_base;
 655 void __iomem *timer1_va_base;
 656 void __iomem *timer2_va_base;
 657 void __iomem *timer3_va_base;
 658
 659 /*
 660  * Set up the clock source and clock events devices
 661  */
 662 void __init realview_timer_init(unsigned int timer_irq)
 663 {
 664         u32 val;
 665
 666         /*
 667          * set clock frequency:
 668          *      REALVIEW_REFCLK is 32KHz
 669          *      REALVIEW_TIMCLK is 1MHz
 670          */
 671         val = readl(__io_address(REALVIEW_SCTL_BASE));
 672         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 673                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 674                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 675                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 676                __io_address(REALVIEW_SCTL_BASE));
 677
 678         /*
 679          * Initialise to a known state (all timers off)
 680          */
 681         writel(0, timer0_va_base + TIMER_CTRL);
 682         writel(0, timer1_va_base + TIMER_CTRL);
 683         writel(0, timer2_va_base + TIMER_CTRL);
 684         writel(0, timer3_va_base + TIMER_CTRL);
 685
 686         sp804_clocksource_init(timer3_va_base);
 687         sp804_clockevents_init(timer0_va_base, timer_irq);
 688 }
 689
 690 /*
 691  * Setup the memory banks.
 692  */
 693 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
 694                     struct meminfo *meminfo)
 695 {
 696         /*
 697          * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
 698          * Half of this is mirrored at 0.
 699          */
 700 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
 701         meminfo->bank[0].start = 0x70000000;
 702         meminfo->bank[0].size = SZ_512M;
 703         meminfo->nr_banks = 1;
 704 #else
 705         meminfo->bank[0].start = 0;
 706         meminfo->bank[0].size = SZ_256M;
 707         meminfo->nr_banks = 1;
 708 #endif
 709 }