arch/arm/mach-omap2/serial.c

   1 /*
   2  * arch/arm/mach-omap2/serial.c
   3  *
   4  * OMAP2 serial support.
   5  *
   6  * Copyright (C) 2005-2008 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * Major rework for PM support by Kevin Hilman
  10  *
  11  * Based off of arch/arm/mach-omap/omap1/serial.c
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License. See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/serial_8250.h>
  23 #include <linux/serial_reg.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26
  27 #include <plat/common.h>
  28 #include <plat/board.h>
  29 #include <plat/clock.h>
  30 #include <plat/control.h>
  31
  32 #include "prm.h"
  33 #include "pm.h"
  34 #include "prm-regbits-34xx.h"
  35
  36 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
  37 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
  38
  39 /*
  40  * NOTE: By default the serial timeout is disabled as it causes lost characters
  41  * over the serial ports. This means that the UART clocks will stay on until
  42  * disabled via sysfs. This also causes that any deeper omap sleep states are
  43  * blocked.
  44  */
  45 #define DEFAULT_TIMEOUT 0
  46
  47 struct omap_uart_state {
  48         int num;
  49         int can_sleep;
  50         struct timer_list timer;
  51         u32 timeout;
  52
  53         void __iomem *wk_st;
  54         void __iomem *wk_en;
  55         u32 wk_mask;
  56         u32 padconf;
  57
  58         struct clk *ick;
  59         struct clk *fck;
  60         int clocked;
  61
  62         struct plat_serial8250_port *p;
  63         struct list_head node;
  64         struct platform_device pdev;
  65
  66 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  67         int context_valid;
  68
  69         /* Registers to be saved/restored for OFF-mode */
  70         u16 dll;
  71         u16 dlh;
  72         u16 ier;
  73         u16 sysc;
  74         u16 scr;
  75         u16 wer;
  76 #endif
  77 };
  78
  79 static LIST_HEAD(uart_list);
  80
  81 static struct plat_serial8250_port serial_platform_data0[] = {
  82         {
  83                 .irq            = 72,
  84                 .flags          = UPF_BOOT_AUTOCONF,
  85                 .iotype         = UPIO_MEM,
  86                 .regshift       = 2,
  87                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
  88         }, {
  89                 .flags          = 0
  90         }
  91 };
  92
  93 static struct plat_serial8250_port serial_platform_data1[] = {
  94         {
  95                 .irq            = 73,
  96                 .flags          = UPF_BOOT_AUTOCONF,
  97                 .iotype         = UPIO_MEM,
  98                 .regshift       = 2,
  99                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 100         }, {
 101                 .flags          = 0
 102         }
 103 };
 104
 105 static struct plat_serial8250_port serial_platform_data2[] = {
 106         {
 107                 .irq            = 74,
 108                 .flags          = UPF_BOOT_AUTOCONF,
 109                 .iotype         = UPIO_MEM,
 110                 .regshift       = 2,
 111                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 112         }, {
 113                 .flags          = 0
 114         }
 115 };
 116
 117 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 118 static struct plat_serial8250_port serial_platform_data3[] = {
 119         {
 120                 .irq            = 70,
 121                 .flags          = UPF_BOOT_AUTOCONF,
 122                 .iotype         = UPIO_MEM,
 123                 .regshift       = 2,
 124                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 125         }, {
 126                 .flags          = 0
 127         }
 128 };
 129
 130 static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals)
 131 {
 132         serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
 133 }
 134 #else
 135 static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals)
 136 {
 137 }
 138 #endif
 139
 140 void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
 141 {
 142         serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
 143         serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
 144         serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
 145         if (cpu_is_omap3630() || cpu_is_omap44xx())
 146                 omap2_set_globals_uart4(omap2_globals);
 147 }
 148
 149 static inline unsigned int __serial_read_reg(struct uart_port *up,
 150                                            int offset)
 151 {
 152         offset <<= up->regshift;
 153         return (unsigned int)__raw_readb(up->membase + offset);
 154 }
 155
 156 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
 157                                            int offset)
 158 {
 159         offset <<= up->regshift;
 160         return (unsigned int)__raw_readb(up->membase + offset);
 161 }
 162
 163 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
 164                                     int value)
 165 {
 166         offset <<= p->regshift;
 167         __raw_writeb(value, p->membase + offset);
 168 }
 169
 170 /*
 171  * Internal UARTs need to be initialized for the 8250 autoconfig to work
 172  * properly. Note that the TX watermark initialization may not be needed
 173  * once the 8250.c watermark handling code is merged.
 174  */
 175 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 176 {
 177         struct plat_serial8250_port *p = uart->p;
 178
 179         serial_write_reg(p, UART_OMAP_MDR1, 0x07);
 180         serial_write_reg(p, UART_OMAP_SCR, 0x08);
 181         serial_write_reg(p, UART_OMAP_MDR1, 0x00);
 182         serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
 183 }
 184
 185 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 186
 187 static void omap_uart_save_context(struct omap_uart_state *uart)
 188 {
 189         u16 lcr = 0;
 190         struct plat_serial8250_port *p = uart->p;
 191
 192         if (!enable_off_mode)
 193                 return;
 194
 195         lcr = serial_read_reg(p, UART_LCR);
 196         serial_write_reg(p, UART_LCR, 0xBF);
 197         uart->dll = serial_read_reg(p, UART_DLL);
 198         uart->dlh = serial_read_reg(p, UART_DLM);
 199         serial_write_reg(p, UART_LCR, lcr);
 200         uart->ier = serial_read_reg(p, UART_IER);
 201         uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
 202         uart->scr = serial_read_reg(p, UART_OMAP_SCR);
 203         uart->wer = serial_read_reg(p, UART_OMAP_WER);
 204
 205         uart->context_valid = 1;
 206 }
 207
 208 static void omap_uart_restore_context(struct omap_uart_state *uart)
 209 {
 210         u16 efr = 0;
 211         struct plat_serial8250_port *p = uart->p;
 212
 213         if (!enable_off_mode)
 214                 return;
 215
 216         if (!uart->context_valid)
 217                 return;
 218
 219         uart->context_valid = 0;
 220
 221         serial_write_reg(p, UART_OMAP_MDR1, 0x7);
 222         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 223         efr = serial_read_reg(p, UART_EFR);
 224         serial_write_reg(p, UART_EFR, UART_EFR_ECB);
 225         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
 226         serial_write_reg(p, UART_IER, 0x0);
 227         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 228         serial_write_reg(p, UART_DLL, uart->dll);
 229         serial_write_reg(p, UART_DLM, uart->dlh);
 230         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
 231         serial_write_reg(p, UART_IER, uart->ier);
 232         serial_write_reg(p, UART_FCR, 0xA1);
 233         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 234         serial_write_reg(p, UART_EFR, efr);
 235         serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
 236         serial_write_reg(p, UART_OMAP_SCR, uart->scr);
 237         serial_write_reg(p, UART_OMAP_WER, uart->wer);
 238         serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
 239         serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
 240 }
 241 #else
 242 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
 243 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
 244 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
 245
 246 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 247 {
 248         if (uart->clocked)
 249                 return;
 250
 251         clk_enable(uart->ick);
 252         clk_enable(uart->fck);
 253         uart->clocked = 1;
 254         omap_uart_restore_context(uart);
 255 }
 256
 257 #ifdef CONFIG_PM
 258
 259 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 260 {
 261         if (!uart->clocked)
 262                 return;
 263
 264         omap_uart_save_context(uart);
 265         uart->clocked = 0;
 266         clk_disable(uart->ick);
 267         clk_disable(uart->fck);
 268 }
 269
 270 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
 271 {
 272         /* Set wake-enable bit */
 273         if (uart->wk_en && uart->wk_mask) {
 274                 u32 v = __raw_readl(uart->wk_en);
 275                 v |= uart->wk_mask;
 276                 __raw_writel(v, uart->wk_en);
 277         }
 278
 279         /* Ensure IOPAD wake-enables are set */
 280         if (cpu_is_omap34xx() && uart->padconf) {
 281                 u16 v = omap_ctrl_readw(uart->padconf);
 282                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
 283                 omap_ctrl_writew(v, uart->padconf);
 284         }
 285 }
 286
 287 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 288 {
 289         /* Clear wake-enable bit */
 290         if (uart->wk_en && uart->wk_mask) {
 291                 u32 v = __raw_readl(uart->wk_en);
 292                 v &= ~uart->wk_mask;
 293                 __raw_writel(v, uart->wk_en);
 294         }
 295
 296         /* Ensure IOPAD wake-enables are cleared */
 297         if (cpu_is_omap34xx() && uart->padconf) {
 298                 u16 v = omap_ctrl_readw(uart->padconf);
 299                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
 300                 omap_ctrl_writew(v, uart->padconf);
 301         }
 302 }
 303
 304 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
 305                                           int enable)
 306 {
 307         struct plat_serial8250_port *p = uart->p;
 308         u16 sysc;
 309
 310         sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
 311         if (enable)
 312                 sysc |= 0x2 << 3;
 313         else
 314                 sysc |= 0x1 << 3;
 315
 316         serial_write_reg(p, UART_OMAP_SYSC, sysc);
 317 }
 318
 319 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 320 {
 321         omap_uart_enable_clocks(uart);
 322
 323         omap_uart_smart_idle_enable(uart, 0);
 324         uart->can_sleep = 0;
 325         if (uart->timeout)
 326                 mod_timer(&uart->timer, jiffies + uart->timeout);
 327         else
 328                 del_timer(&uart->timer);
 329 }
 330
 331 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 332 {
 333         if (device_may_wakeup(&uart->pdev.dev))
 334                 omap_uart_enable_wakeup(uart);
 335         else
 336                 omap_uart_disable_wakeup(uart);
 337
 338         if (!uart->clocked)
 339                 return;
 340
 341         omap_uart_smart_idle_enable(uart, 1);
 342         uart->can_sleep = 1;
 343         del_timer(&uart->timer);
 344 }
 345
 346 static void omap_uart_idle_timer(unsigned long data)
 347 {
 348         struct omap_uart_state *uart = (struct omap_uart_state *)data;
 349
 350         omap_uart_allow_sleep(uart);
 351 }
 352
 353 void omap_uart_prepare_idle(int num)
 354 {
 355         struct omap_uart_state *uart;
 356
 357         list_for_each_entry(uart, &uart_list, node) {
 358                 if (num == uart->num && uart->can_sleep) {
 359                         omap_uart_disable_clocks(uart);
 360                         return;
 361                 }
 362         }
 363 }
 364
 365 void omap_uart_resume_idle(int num)
 366 {
 367         struct omap_uart_state *uart;
 368
 369         list_for_each_entry(uart, &uart_list, node) {
 370                 if (num == uart->num) {
 371                         omap_uart_enable_clocks(uart);
 372
 373                         /* Check for IO pad wakeup */
 374                         if (cpu_is_omap34xx() && uart->padconf) {
 375                                 u16 p = omap_ctrl_readw(uart->padconf);
 376
 377                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
 378                                         omap_uart_block_sleep(uart);
 379                         }
 380
 381                         /* Check for normal UART wakeup */
 382                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
 383                                 omap_uart_block_sleep(uart);
 384                         return;
 385                 }
 386         }
 387 }
 388
 389 void omap_uart_prepare_suspend(void)
 390 {
 391         struct omap_uart_state *uart;
 392
 393         list_for_each_entry(uart, &uart_list, node) {
 394                 omap_uart_allow_sleep(uart);
 395         }
 396 }
 397
 398 int omap_uart_can_sleep(void)
 399 {
 400         struct omap_uart_state *uart;
 401         int can_sleep = 1;
 402
 403         list_for_each_entry(uart, &uart_list, node) {
 404                 if (!uart->clocked)
 405                         continue;
 406
 407                 if (!uart->can_sleep) {
 408                         can_sleep = 0;
 409                         continue;
 410                 }
 411
 412                 /* This UART can now safely sleep. */
 413                 omap_uart_allow_sleep(uart);
 414         }
 415
 416         return can_sleep;
 417 }
 418
 419 /**
 420  * omap_uart_interrupt()
 421  *
 422  * This handler is used only to detect that *any* UART interrupt has
 423  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 424  * any UART interrupt will trigger the inactivity timer so the
 425  * UART will not idle or sleep for its timeout period.
 426  *
 427  **/
 428 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 429 {
 430         struct omap_uart_state *uart = dev_id;
 431
 432         omap_uart_block_sleep(uart);
 433
 434         return IRQ_NONE;
 435 }
 436
 437 static void omap_uart_idle_init(struct omap_uart_state *uart)
 438 {
 439         struct plat_serial8250_port *p = uart->p;
 440         int ret;
 441
 442         uart->can_sleep = 0;
 443         uart->timeout = DEFAULT_TIMEOUT;
 444         setup_timer(&uart->timer, omap_uart_idle_timer,
 445                     (unsigned long) uart);
 446         if (uart->timeout)
 447                 mod_timer(&uart->timer, jiffies + uart->timeout);
 448         omap_uart_smart_idle_enable(uart, 0);
 449
 450         if (cpu_is_omap34xx()) {
 451                 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
 452                 u32 wk_mask = 0;
 453                 u32 padconf = 0;
 454
 455                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
 456                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
 457                 switch (uart->num) {
 458                 case 0:
 459                         wk_mask = OMAP3430_ST_UART1_MASK;
 460                         padconf = 0x182;
 461                         break;
 462                 case 1:
 463                         wk_mask = OMAP3430_ST_UART2_MASK;
 464                         padconf = 0x17a;
 465                         break;
 466                 case 2:
 467                         wk_mask = OMAP3430_ST_UART3_MASK;
 468                         padconf = 0x19e;
 469                         break;
 470                 }
 471                 uart->wk_mask = wk_mask;
 472                 uart->padconf = padconf;
 473         } else if (cpu_is_omap24xx()) {
 474                 u32 wk_mask = 0;
 475
 476                 if (cpu_is_omap2430()) {
 477                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
 478                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
 479                 } else if (cpu_is_omap2420()) {
 480                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
 481                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
 482                 }
 483                 switch (uart->num) {
 484                 case 0:
 485                         wk_mask = OMAP24XX_ST_UART1_MASK;
 486                         break;
 487                 case 1:
 488                         wk_mask = OMAP24XX_ST_UART2_MASK;
 489                         break;
 490                 case 2:
 491                         wk_mask = OMAP24XX_ST_UART3_MASK;
 492                         break;
 493                 }
 494                 uart->wk_mask = wk_mask;
 495         } else {
 496                 uart->wk_en = 0;
 497                 uart->wk_st = 0;
 498                 uart->wk_mask = 0;
 499                 uart->padconf = 0;
 500         }
 501
 502         p->irqflags |= IRQF_SHARED;
 503         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
 504                           "serial idle", (void *)uart);
 505         WARN_ON(ret);
 506 }
 507
 508 void omap_uart_enable_irqs(int enable)
 509 {
 510         int ret;
 511         struct omap_uart_state *uart;
 512
 513         list_for_each_entry(uart, &uart_list, node) {
 514                 if (enable)
 515                         ret = request_irq(uart->p->irq, omap_uart_interrupt,
 516                                 IRQF_SHARED, "serial idle", (void *)uart);
 517                 else
 518                         free_irq(uart->p->irq, (void *)uart);
 519         }
 520 }
 521
 522 static ssize_t sleep_timeout_show(struct device *dev,
 523                                   struct device_attribute *attr,
 524                                   char *buf)
 525 {
 526         struct platform_device *pdev = container_of(dev,
 527                                         struct platform_device, dev);
 528         struct omap_uart_state *uart = container_of(pdev,
 529                                         struct omap_uart_state, pdev);
 530
 531         return sprintf(buf, "%u\n", uart->timeout / HZ);
 532 }
 533
 534 static ssize_t sleep_timeout_store(struct device *dev,
 535                                    struct device_attribute *attr,
 536                                    const char *buf, size_t n)
 537 {
 538         struct platform_device *pdev = container_of(dev,
 539                                         struct platform_device, dev);
 540         struct omap_uart_state *uart = container_of(pdev,
 541                                         struct omap_uart_state, pdev);
 542         unsigned int value;
 543
 544         if (sscanf(buf, "%u", &value) != 1) {
 545                 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
 546                 return -EINVAL;
 547         }
 548
 549         uart->timeout = value * HZ;
 550         if (uart->timeout)
 551                 mod_timer(&uart->timer, jiffies + uart->timeout);
 552         else
 553                 /* A zero value means disable timeout feature */
 554                 omap_uart_block_sleep(uart);
 555
 556         return n;
 557 }
 558
 559 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
 560 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 561 #else
 562 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
 563 #define DEV_CREATE_FILE(dev, attr)
 564 #endif /* CONFIG_PM */
 565
 566 static struct omap_uart_state omap_uart[] = {
 567         {
 568                 .pdev = {
 569                         .name                   = "serial8250",
 570                         .id                     = PLAT8250_DEV_PLATFORM,
 571                         .dev                    = {
 572                                 .platform_data  = serial_platform_data0,
 573                         },
 574                 },
 575         }, {
 576                 .pdev = {
 577                         .name                   = "serial8250",
 578                         .id                     = PLAT8250_DEV_PLATFORM1,
 579                         .dev                    = {
 580                                 .platform_data  = serial_platform_data1,
 581                         },
 582                 },
 583         }, {
 584                 .pdev = {
 585                         .name                   = "serial8250",
 586                         .id                     = PLAT8250_DEV_PLATFORM2,
 587                         .dev                    = {
 588                                 .platform_data  = serial_platform_data2,
 589                         },
 590                 },
 591         },
 592 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 593         {
 594                 .pdev = {
 595                         .name                   = "serial8250",
 596                         .id                     = 3,
 597                         .dev                    = {
 598                                 .platform_data  = serial_platform_data3,
 599                         },
 600                 },
 601         },
 602 #endif
 603 };
 604
 605 /*
 606  * Override the default 8250 read handler: mem_serial_in()
 607  * Empty RX fifo read causes an abort on omap3630 and omap4
 608  * This function makes sure that an empty rx fifo is not read on these silicons
 609  * (OMAP1/2/3430 are not affected)
 610  */
 611 static unsigned int serial_in_override(struct uart_port *up, int offset)
 612 {
 613         if (UART_RX == offset) {
 614                 unsigned int lsr;
 615                 lsr = __serial_read_reg(up, UART_LSR);
 616                 if (!(lsr & UART_LSR_DR))
 617                         return -EPERM;
 618         }
 619
 620         return __serial_read_reg(up, offset);
 621 }
 622
 623 void __init omap_serial_early_init(void)
 624 {
 625         int i;
 626         char name[16];
 627
 628         /*
 629          * Make sure the serial ports are muxed on at this point.
 630          * You have to mux them off in device drivers later on
 631          * if not needed.
 632          */
 633
 634         for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
 635                 struct omap_uart_state *uart = &omap_uart[i];
 636                 struct platform_device *pdev = &uart->pdev;
 637                 struct device *dev = &pdev->dev;
 638                 struct plat_serial8250_port *p = dev->platform_data;
 639
 640                 /*
 641                  * Module 4KB + L4 interconnect 4KB
 642                  * Static mapping, never released
 643                  */
 644                 p->membase = ioremap(p->mapbase, SZ_8K);
 645                 if (!p->membase) {
 646                         printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
 647                         continue;
 648                 }
 649
 650                 sprintf(name, "uart%d_ick", i+1);
 651                 uart->ick = clk_get(NULL, name);
 652                 if (IS_ERR(uart->ick)) {
 653                         printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
 654                         uart->ick = NULL;
 655                 }
 656
 657                 sprintf(name, "uart%d_fck", i+1);
 658                 uart->fck = clk_get(NULL, name);
 659                 if (IS_ERR(uart->fck)) {
 660                         printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
 661                         uart->fck = NULL;
 662                 }
 663
 664                 /* FIXME: Remove this once the clkdev is ready */
 665                 if (!cpu_is_omap44xx()) {
 666                         if (!uart->ick || !uart->fck)
 667                                 continue;
 668                 }
 669
 670                 uart->num = i;
 671                 p->private_data = uart;
 672                 uart->p = p;
 673
 674                 if (cpu_is_omap44xx())
 675                         p->irq += 32;
 676         }
 677 }
 678
 679 /**
 680  * omap_serial_init_port() - initialize single serial port
 681  * @port: serial port number (0-3)
 682  *
 683  * This function initialies serial driver for given @port only.
 684  * Platforms can call this function instead of omap_serial_init()
 685  * if they don't plan to use all available UARTs as serial ports.
 686  *
 687  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 688  * use only one of the two.
 689  */
 690 void __init omap_serial_init_port(int port)
 691 {
 692         struct omap_uart_state *uart;
 693         struct platform_device *pdev;
 694         struct device *dev;
 695
 696         BUG_ON(port < 0);
 697         BUG_ON(port >= ARRAY_SIZE(omap_uart));
 698
 699         uart = &omap_uart[port];
 700         pdev = &uart->pdev;
 701         dev = &pdev->dev;
 702
 703         omap_uart_enable_clocks(uart);
 704
 705         omap_uart_reset(uart);
 706         omap_uart_idle_init(uart);
 707
 708         list_add_tail(&uart->node, &uart_list);
 709
 710         if (WARN_ON(platform_device_register(pdev)))
 711                 return;
 712
 713         if ((cpu_is_omap34xx() && uart->padconf) ||
 714             (uart->wk_en && uart->wk_mask)) {
 715                 device_init_wakeup(dev, true);
 716                 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
 717         }
 718
 719                 /* omap44xx: Never read empty UART fifo
 720                  * omap3xxx: Never read empty UART fifo on UARTs
 721                  * with IP rev >=0x52
 722                  */
 723                 if (cpu_is_omap44xx())
 724                         uart->p->serial_in = serial_in_override;
 725                 else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
 726                                 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
 727                         uart->p->serial_in = serial_in_override;
 728 }
 729
 730 /**
 731  * omap_serial_init() - intialize all supported serial ports
 732  *
 733  * Initializes all available UARTs as serial ports. Platforms
 734  * can call this function when they want to have default behaviour
 735  * for serial ports (e.g initialize them all as serial ports).
 736  */
 737 void __init omap_serial_init(void)
 738 {
 739         int i, nr_ports;
 740
 741         if (!(cpu_is_omap3630() || cpu_is_omap4430()))
 742                 nr_ports = 3;
 743         else
 744                 nr_ports = ARRAY_SIZE(omap_uart);
 745
 746         for (i = 0; i < nr_ports; i++)
 747                 omap_serial_init_port(i);
 748 }