arch/arm/mach-omap2/include/mach/entry-macro.S

   1 /*
   2  * arch/arm/plat-omap/include/mach/entry-macro.S
   3  *
   4  * Low-level IRQ helper macros for OMAP-based platforms
   5  *
   6  * Copyright (C) 2009 Texas Instruments
   7  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This file is licensed under  the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13 #include <mach/hardware.h>
  14 #include <mach/io.h>
  15 #include <mach/irqs.h>
  16 #include <asm/hardware/gic.h>
  17
  18 #include <plat/omap24xx.h>
  19 #include <plat/omap34xx.h>
  20 #include <plat/omap44xx.h>
  21
  22 #define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
  23 #define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
  24 #define OMAP4_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
  25 #define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
  26 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
  27
  28                 .macro  disable_fiq
  29                 .endm
  30
  31                 .macro  arch_ret_to_user, tmp1, tmp2
  32                 .endm
  33
  34 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  35
  36                 .pushsection .data
  37 omap_irq_base:  .word   0
  38                 .popsection
  39
  40 #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARCH_OMAP3)
  41                 /* Configure the interrupt base on the first interrupt */
  42                 .macro  get_irqnr_preamble, base, tmp
  43 9:
  44                 ldr     \base, =omap_irq_base   @ irq base address
  45                 ldr     \base, [\base, #0]      @ irq base value
  46                 cmp     \base, #0               @ already configured?
  47                 bne     9998f                   @ nothing to do
  48
  49                 mrc     p15, 0, \tmp, c0, c0, 0 @ get processor revision
  50                 and     \tmp, \tmp, #0x000f0000 @ only check architecture
  51                 cmp     \tmp, #0x00060000       @ is v6?
  52                 beq     2400f                   @ found v6 so it's omap24xx
  53                 cmp     \tmp, #0x000f0000       @ is cortex?
  54                 beq     3400f                   @ found v7 so it's omap34xx
  55 2400:           ldr     \base, =OMAP2_IRQ_BASE
  56                 ldr     \tmp, =omap_irq_base
  57                 str     \base, [\tmp, #0]
  58                 b       9b
  59 3400:           ldr     \base, =OMAP3_IRQ_BASE
  60                 ldr     \tmp, =omap_irq_base
  61                 str     \base, [\tmp, #0]
  62                 b       9b
  63 9998:
  64                 .endm
  65 #else
  66                 .macro  get_irqnr_preamble, base, tmp
  67 #ifdef CONFIG_ARCH_OMAP2
  68                 ldr     \base, =OMAP2_IRQ_BASE
  69 #else
  70                 ldr     \base, =OMAP3_IRQ_BASE
  71 #endif
  72                 .endm
  73 #endif
  74                 /* Check the pending interrupts. Note that base already set */
  75                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  76                 ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
  77                 cmp     \irqnr, #0x0
  78                 bne     9999f
  79                 ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
  80                 cmp     \irqnr, #0x0
  81                 bne     9999f
  82                 ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
  83                 cmp     \irqnr, #0x0
  84 9999:
  85                 ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
  86                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
  87
  88                 .endm
  89 #endif
  90
  91
  92 #ifdef CONFIG_ARCH_OMAP4
  93
  94                 .macro  get_irqnr_preamble, base, tmp
  95                 .endm
  96
  97                 /*
  98                  * The interrupt numbering scheme is defined in the
  99                  * interrupt controller spec.  To wit:
 100                  *
 101                  * Interrupts 0-15 are IPI
 102                  * 16-28 are reserved
 103                  * 29-31 are local.  We allow 30 to be used for the watchdog.
 104                  * 32-1020 are global
 105                  * 1021-1022 are reserved
 106                  * 1023 is "spurious" (no interrupt)
 107                  *
 108                  * For now, we ignore all local interrupts so only return an
 109                  * interrupt if it's between 30 and 1020.  The test_for_ipi
 110                  * routine below will pick up on IPIs.
 111                  * A simple read from the controller will tell us the number
 112                  * of the highest priority enabled interrupt.
 113                  * We then just need to check whether it is in the
 114                  * valid range for an IRQ (30-1020 inclusive).
 115                  */
 116                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 117                 ldr     \base, =OMAP4_IRQ_BASE
 118                 ldr     \irqstat, [\base, #GIC_CPU_INTACK]
 119
 120                 ldr     \tmp, =1021
 121
 122                 bic     \irqnr, \irqstat, #0x1c00
 123
 124                 cmp     \irqnr, #29
 125                 cmpcc   \irqnr, \irqnr
 126                 cmpne   \irqnr, \tmp
 127                 cmpcs   \irqnr, \irqnr
 128                 .endm
 129
 130                 /* We assume that irqstat (the raw value of the IRQ acknowledge
 131                  * register) is preserved from the macro above.
 132                  * If there is an IPI, we immediately signal end of interrupt
 133                  * on the controller, since this requires the original irqstat
 134                  * value which we won't easily be able to recreate later.
 135                  */
 136
 137                 .macro test_for_ipi, irqnr, irqstat, base, tmp
 138                 bic     \irqnr, \irqstat, #0x1c00
 139                 cmp     \irqnr, #16
 140                 it      cc
 141                 strcc   \irqstat, [\base, #GIC_CPU_EOI]
 142                 it      cs
 143                 cmpcs   \irqnr, \irqnr
 144                 .endm
 145
 146                 /* As above, this assumes that irqstat and base are preserved */
 147
 148                 .macro test_for_ltirq, irqnr, irqstat, base, tmp
 149                 bic     \irqnr, \irqstat, #0x1c00
 150                 mov     \tmp, #0
 151                 cmp     \irqnr, #29
 152                 itt     eq
 153                 moveq   \tmp, #1
 154                 streq   \irqstat, [\base, #GIC_CPU_EOI]
 155                 cmp     \tmp, #0
 156                 .endm
 157 #endif
 158
 159                 .macro  irq_prio_table
 160                 .endm