arch/arm/mach-omap1/clock_data.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock_data.c
   3  *
   4  *  Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16
  17 #include <asm/mach-types.h>  /* for machine_is_* */
  18
  19 #include <plat/clock.h>
  20 #include <plat/cpu.h>
  21 #include <plat/clkdev_omap.h>
  22 #include <plat/usb.h>   /* for OTG_BASE */
  23
  24 #include "clock.h"
  25
  26 /*------------------------------------------------------------------------
  27  * Omap1 clocks
  28  *-------------------------------------------------------------------------*/
  29
  30 /* XXX is this necessary? */
  31 static struct clk dummy_ck = {
  32         .name   = "dummy",
  33         .ops    = &clkops_dummy,
  34 };
  35
  36 static struct clk ck_ref = {
  37         .name           = "ck_ref",
  38         .ops            = &clkops_null,
  39         .rate           = 12000000,
  40 };
  41
  42 static struct clk ck_dpll1 = {
  43         .name           = "ck_dpll1",
  44         .ops            = &clkops_null,
  45         .parent         = &ck_ref,
  46 };
  47
  48 /*
  49  * FIXME: This clock seems to be necessary but no-one has asked for its
  50  * activation.  [ FIX: SoSSI, SSR ]
  51  */
  52 static struct arm_idlect1_clk ck_dpll1out = {
  53         .clk = {
  54                 .name           = "ck_dpll1out",
  55                 .ops            = &clkops_generic,
  56                 .parent         = &ck_dpll1,
  57                 .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
  58                                   ENABLE_ON_INIT,
  59                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
  60                 .enable_bit     = EN_CKOUT_ARM,
  61                 .recalc         = &followparent_recalc,
  62         },
  63         .idlect_shift   = 12,
  64 };
  65
  66 static struct clk sossi_ck = {
  67         .name           = "ck_sossi",
  68         .ops            = &clkops_generic,
  69         .parent         = &ck_dpll1out.clk,
  70         .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
  71         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
  72         .enable_bit     = 16,
  73         .recalc         = &omap1_sossi_recalc,
  74         .set_rate       = &omap1_set_sossi_rate,
  75 };
  76
  77 static struct clk arm_ck = {
  78         .name           = "arm_ck",
  79         .ops            = &clkops_null,
  80         .parent         = &ck_dpll1,
  81         .rate_offset    = CKCTL_ARMDIV_OFFSET,
  82         .recalc         = &omap1_ckctl_recalc,
  83         .round_rate     = omap1_clk_round_rate_ckctl_arm,
  84         .set_rate       = omap1_clk_set_rate_ckctl_arm,
  85 };
  86
  87 static struct arm_idlect1_clk armper_ck = {
  88         .clk = {
  89                 .name           = "armper_ck",
  90                 .ops            = &clkops_generic,
  91                 .parent         = &ck_dpll1,
  92                 .flags          = CLOCK_IDLE_CONTROL,
  93                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
  94                 .enable_bit     = EN_PERCK,
  95                 .rate_offset    = CKCTL_PERDIV_OFFSET,
  96                 .recalc         = &omap1_ckctl_recalc,
  97                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
  98                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
  99         },
 100         .idlect_shift   = 2,
 101 };
 102
 103 /*
 104  * FIXME: This clock seems to be necessary but no-one has asked for its
 105  * activation.  [ GPIO code for 1510 ]
 106  */
 107 static struct clk arm_gpio_ck = {
 108         .name           = "arm_gpio_ck",
 109         .ops            = &clkops_generic,
 110         .parent         = &ck_dpll1,
 111         .flags          = ENABLE_ON_INIT,
 112         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 113         .enable_bit     = EN_GPIOCK,
 114         .recalc         = &followparent_recalc,
 115 };
 116
 117 static struct arm_idlect1_clk armxor_ck = {
 118         .clk = {
 119                 .name           = "armxor_ck",
 120                 .ops            = &clkops_generic,
 121                 .parent         = &ck_ref,
 122                 .flags          = CLOCK_IDLE_CONTROL,
 123                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 124                 .enable_bit     = EN_XORPCK,
 125                 .recalc         = &followparent_recalc,
 126         },
 127         .idlect_shift   = 1,
 128 };
 129
 130 static struct arm_idlect1_clk armtim_ck = {
 131         .clk = {
 132                 .name           = "armtim_ck",
 133                 .ops            = &clkops_generic,
 134                 .parent         = &ck_ref,
 135                 .flags          = CLOCK_IDLE_CONTROL,
 136                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 137                 .enable_bit     = EN_TIMCK,
 138                 .recalc         = &followparent_recalc,
 139         },
 140         .idlect_shift   = 9,
 141 };
 142
 143 static struct arm_idlect1_clk armwdt_ck = {
 144         .clk = {
 145                 .name           = "armwdt_ck",
 146                 .ops            = &clkops_generic,
 147                 .parent         = &ck_ref,
 148                 .flags          = CLOCK_IDLE_CONTROL,
 149                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 150                 .enable_bit     = EN_WDTCK,
 151                 .fixed_div      = 14,
 152                 .recalc         = &omap_fixed_divisor_recalc,
 153         },
 154         .idlect_shift   = 0,
 155 };
 156
 157 static struct clk arminth_ck16xx = {
 158         .name           = "arminth_ck",
 159         .ops            = &clkops_null,
 160         .parent         = &arm_ck,
 161         .recalc         = &followparent_recalc,
 162         /* Note: On 16xx the frequency can be divided by 2 by programming
 163          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 164          *
 165          * 1510 version is in TC clocks.
 166          */
 167 };
 168
 169 static struct clk dsp_ck = {
 170         .name           = "dsp_ck",
 171         .ops            = &clkops_generic,
 172         .parent         = &ck_dpll1,
 173         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 174         .enable_bit     = EN_DSPCK,
 175         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 176         .recalc         = &omap1_ckctl_recalc,
 177         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 178         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 179 };
 180
 181 static struct clk dspmmu_ck = {
 182         .name           = "dspmmu_ck",
 183         .ops            = &clkops_null,
 184         .parent         = &ck_dpll1,
 185         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 186         .recalc         = &omap1_ckctl_recalc,
 187         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 188         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 189 };
 190
 191 static struct clk dspper_ck = {
 192         .name           = "dspper_ck",
 193         .ops            = &clkops_dspck,
 194         .parent         = &ck_dpll1,
 195         .enable_reg     = DSP_IDLECT2,
 196         .enable_bit     = EN_PERCK,
 197         .rate_offset    = CKCTL_PERDIV_OFFSET,
 198         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 199         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 200         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 201 };
 202
 203 static struct clk dspxor_ck = {
 204         .name           = "dspxor_ck",
 205         .ops            = &clkops_dspck,
 206         .parent         = &ck_ref,
 207         .enable_reg     = DSP_IDLECT2,
 208         .enable_bit     = EN_XORPCK,
 209         .recalc         = &followparent_recalc,
 210 };
 211
 212 static struct clk dsptim_ck = {
 213         .name           = "dsptim_ck",
 214         .ops            = &clkops_dspck,
 215         .parent         = &ck_ref,
 216         .enable_reg     = DSP_IDLECT2,
 217         .enable_bit     = EN_DSPTIMCK,
 218         .recalc         = &followparent_recalc,
 219 };
 220
 221 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 222 static struct arm_idlect1_clk tc_ck = {
 223         .clk = {
 224                 .name           = "tc_ck",
 225                 .ops            = &clkops_null,
 226                 .parent         = &ck_dpll1,
 227                 .flags          = CLOCK_IDLE_CONTROL,
 228                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 229                 .recalc         = &omap1_ckctl_recalc,
 230                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 231                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 232         },
 233         .idlect_shift   = 6,
 234 };
 235
 236 static struct clk arminth_ck1510 = {
 237         .name           = "arminth_ck",
 238         .ops            = &clkops_null,
 239         .parent         = &tc_ck.clk,
 240         .recalc         = &followparent_recalc,
 241         /* Note: On 1510 the frequency follows TC_CK
 242          *
 243          * 16xx version is in MPU clocks.
 244          */
 245 };
 246
 247 static struct clk tipb_ck = {
 248         /* No-idle controlled by "tc_ck" */
 249         .name           = "tipb_ck",
 250         .ops            = &clkops_null,
 251         .parent         = &tc_ck.clk,
 252         .recalc         = &followparent_recalc,
 253 };
 254
 255 static struct clk l3_ocpi_ck = {
 256         /* No-idle controlled by "tc_ck" */
 257         .name           = "l3_ocpi_ck",
 258         .ops            = &clkops_generic,
 259         .parent         = &tc_ck.clk,
 260         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 261         .enable_bit     = EN_OCPI_CK,
 262         .recalc         = &followparent_recalc,
 263 };
 264
 265 static struct clk tc1_ck = {
 266         .name           = "tc1_ck",
 267         .ops            = &clkops_generic,
 268         .parent         = &tc_ck.clk,
 269         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 270         .enable_bit     = EN_TC1_CK,
 271         .recalc         = &followparent_recalc,
 272 };
 273
 274 /*
 275  * FIXME: This clock seems to be necessary but no-one has asked for its
 276  * activation.  [ pm.c (SRAM), CCP, Camera ]
 277  */
 278 static struct clk tc2_ck = {
 279         .name           = "tc2_ck",
 280         .ops            = &clkops_generic,
 281         .parent         = &tc_ck.clk,
 282         .flags          = ENABLE_ON_INIT,
 283         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 284         .enable_bit     = EN_TC2_CK,
 285         .recalc         = &followparent_recalc,
 286 };
 287
 288 static struct clk dma_ck = {
 289         /* No-idle controlled by "tc_ck" */
 290         .name           = "dma_ck",
 291         .ops            = &clkops_null,
 292         .parent         = &tc_ck.clk,
 293         .recalc         = &followparent_recalc,
 294 };
 295
 296 static struct clk dma_lcdfree_ck = {
 297         .name           = "dma_lcdfree_ck",
 298         .ops            = &clkops_null,
 299         .parent         = &tc_ck.clk,
 300         .recalc         = &followparent_recalc,
 301 };
 302
 303 static struct arm_idlect1_clk api_ck = {
 304         .clk = {
 305                 .name           = "api_ck",
 306                 .ops            = &clkops_generic,
 307                 .parent         = &tc_ck.clk,
 308                 .flags          = CLOCK_IDLE_CONTROL,
 309                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 310                 .enable_bit     = EN_APICK,
 311                 .recalc         = &followparent_recalc,
 312         },
 313         .idlect_shift   = 8,
 314 };
 315
 316 static struct arm_idlect1_clk lb_ck = {
 317         .clk = {
 318                 .name           = "lb_ck",
 319                 .ops            = &clkops_generic,
 320                 .parent         = &tc_ck.clk,
 321                 .flags          = CLOCK_IDLE_CONTROL,
 322                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 323                 .enable_bit     = EN_LBCK,
 324                 .recalc         = &followparent_recalc,
 325         },
 326         .idlect_shift   = 4,
 327 };
 328
 329 static struct clk rhea1_ck = {
 330         .name           = "rhea1_ck",
 331         .ops            = &clkops_null,
 332         .parent         = &tc_ck.clk,
 333         .recalc         = &followparent_recalc,
 334 };
 335
 336 static struct clk rhea2_ck = {
 337         .name           = "rhea2_ck",
 338         .ops            = &clkops_null,
 339         .parent         = &tc_ck.clk,
 340         .recalc         = &followparent_recalc,
 341 };
 342
 343 static struct clk lcd_ck_16xx = {
 344         .name           = "lcd_ck",
 345         .ops            = &clkops_generic,
 346         .parent         = &ck_dpll1,
 347         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 348         .enable_bit     = EN_LCDCK,
 349         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 350         .recalc         = &omap1_ckctl_recalc,
 351         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 352         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 353 };
 354
 355 static struct arm_idlect1_clk lcd_ck_1510 = {
 356         .clk = {
 357                 .name           = "lcd_ck",
 358                 .ops            = &clkops_generic,
 359                 .parent         = &ck_dpll1,
 360                 .flags          = CLOCK_IDLE_CONTROL,
 361                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 362                 .enable_bit     = EN_LCDCK,
 363                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 364                 .recalc         = &omap1_ckctl_recalc,
 365                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 366                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 367         },
 368         .idlect_shift   = 3,
 369 };
 370
 371 static struct clk uart1_1510 = {
 372         .name           = "uart1_ck",
 373         .ops            = &clkops_null,
 374         /* Direct from ULPD, no real parent */
 375         .parent         = &armper_ck.clk,
 376         .rate           = 12000000,
 377         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 378         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 379         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 380         .set_rate       = &omap1_set_uart_rate,
 381         .recalc         = &omap1_uart_recalc,
 382 };
 383
 384 static struct uart_clk uart1_16xx = {
 385         .clk    = {
 386                 .name           = "uart1_ck",
 387                 .ops            = &clkops_uart,
 388                 /* Direct from ULPD, no real parent */
 389                 .parent         = &armper_ck.clk,
 390                 .rate           = 48000000,
 391                 .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 392                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 393                 .enable_bit     = 29,
 394         },
 395         .sysc_addr      = 0xfffb0054,
 396 };
 397
 398 static struct clk uart2_ck = {
 399         .name           = "uart2_ck",
 400         .ops            = &clkops_null,
 401         /* Direct from ULPD, no real parent */
 402         .parent         = &armper_ck.clk,
 403         .rate           = 12000000,
 404         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 405         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 406         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 407         .set_rate       = &omap1_set_uart_rate,
 408         .recalc         = &omap1_uart_recalc,
 409 };
 410
 411 static struct clk uart3_1510 = {
 412         .name           = "uart3_ck",
 413         .ops            = &clkops_null,
 414         /* Direct from ULPD, no real parent */
 415         .parent         = &armper_ck.clk,
 416         .rate           = 12000000,
 417         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 418         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 419         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 420         .set_rate       = &omap1_set_uart_rate,
 421         .recalc         = &omap1_uart_recalc,
 422 };
 423
 424 static struct uart_clk uart3_16xx = {
 425         .clk    = {
 426                 .name           = "uart3_ck",
 427                 .ops            = &clkops_uart,
 428                 /* Direct from ULPD, no real parent */
 429                 .parent         = &armper_ck.clk,
 430                 .rate           = 48000000,
 431                 .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 432                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 433                 .enable_bit     = 31,
 434         },
 435         .sysc_addr      = 0xfffb9854,
 436 };
 437
 438 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 439         .name           = "usb_clko",
 440         .ops            = &clkops_generic,
 441         /* Direct from ULPD, no parent */
 442         .rate           = 6000000,
 443         .flags          = ENABLE_REG_32BIT,
 444         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 445         .enable_bit     = USB_MCLK_EN_BIT,
 446 };
 447
 448 static struct clk usb_hhc_ck1510 = {
 449         .name           = "usb_hhc_ck",
 450         .ops            = &clkops_generic,
 451         /* Direct from ULPD, no parent */
 452         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 453         .flags          = ENABLE_REG_32BIT,
 454         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 455         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 456 };
 457
 458 static struct clk usb_hhc_ck16xx = {
 459         .name           = "usb_hhc_ck",
 460         .ops            = &clkops_generic,
 461         /* Direct from ULPD, no parent */
 462         .rate           = 48000000,
 463         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 464         .flags          = ENABLE_REG_32BIT,
 465         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 466         .enable_bit     = 8 /* UHOST_EN */,
 467 };
 468
 469 static struct clk usb_dc_ck = {
 470         .name           = "usb_dc_ck",
 471         .ops            = &clkops_generic,
 472         /* Direct from ULPD, no parent */
 473         .rate           = 48000000,
 474         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 475         .enable_bit     = 4,
 476 };
 477
 478 static struct clk usb_dc_ck7xx = {
 479         .name           = "usb_dc_ck",
 480         .ops            = &clkops_generic,
 481         /* Direct from ULPD, no parent */
 482         .rate           = 48000000,
 483         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 484         .enable_bit     = 8,
 485 };
 486
 487 static struct clk mclk_1510 = {
 488         .name           = "mclk",
 489         .ops            = &clkops_generic,
 490         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 491         .rate           = 12000000,
 492         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 493         .enable_bit     = 6,
 494 };
 495
 496 static struct clk mclk_16xx = {
 497         .name           = "mclk",
 498         .ops            = &clkops_generic,
 499         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 500         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 501         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 502         .set_rate       = &omap1_set_ext_clk_rate,
 503         .round_rate     = &omap1_round_ext_clk_rate,
 504         .init           = &omap1_init_ext_clk,
 505 };
 506
 507 static struct clk bclk_1510 = {
 508         .name           = "bclk",
 509         .ops            = &clkops_generic,
 510         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 511         .rate           = 12000000,
 512 };
 513
 514 static struct clk bclk_16xx = {
 515         .name           = "bclk",
 516         .ops            = &clkops_generic,
 517         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 518         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 519         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 520         .set_rate       = &omap1_set_ext_clk_rate,
 521         .round_rate     = &omap1_round_ext_clk_rate,
 522         .init           = &omap1_init_ext_clk,
 523 };
 524
 525 static struct clk mmc1_ck = {
 526         .name           = "mmc1_ck",
 527         .ops            = &clkops_generic,
 528         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 529         .parent         = &armper_ck.clk,
 530         .rate           = 48000000,
 531         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 532         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 533         .enable_bit     = 23,
 534 };
 535
 536 static struct clk mmc2_ck = {
 537         .name           = "mmc2_ck",
 538         .ops            = &clkops_generic,
 539         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 540         .parent         = &armper_ck.clk,
 541         .rate           = 48000000,
 542         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 543         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 544         .enable_bit     = 20,
 545 };
 546
 547 static struct clk mmc3_ck = {
 548         .name           = "mmc3_ck",
 549         .ops            = &clkops_generic,
 550         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 551         .parent         = &armper_ck.clk,
 552         .rate           = 48000000,
 553         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 554         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 555         .enable_bit     = 12,
 556 };
 557
 558 static struct clk virtual_ck_mpu = {
 559         .name           = "mpu",
 560         .ops            = &clkops_null,
 561         .parent         = &arm_ck, /* Is smarter alias for */
 562         .recalc         = &followparent_recalc,
 563         .set_rate       = &omap1_select_table_rate,
 564         .round_rate     = &omap1_round_to_table_rate,
 565 };
 566
 567 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 568 remains active during MPU idle whenever this is enabled */
 569 static struct clk i2c_fck = {
 570         .name           = "i2c_fck",
 571         .ops            = &clkops_null,
 572         .flags          = CLOCK_NO_IDLE_PARENT,
 573         .parent         = &armxor_ck.clk,
 574         .recalc         = &followparent_recalc,
 575 };
 576
 577 static struct clk i2c_ick = {
 578         .name           = "i2c_ick",
 579         .ops            = &clkops_null,
 580         .flags          = CLOCK_NO_IDLE_PARENT,
 581         .parent         = &armper_ck.clk,
 582         .recalc         = &followparent_recalc,
 583 };
 584
 585 /*
 586  * clkdev integration
 587  */
 588
 589 static struct omap_clk omap_clks[] = {
 590         /* non-ULPD clocks */
 591         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
 592         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310 | CK_7XX),
 593         /* CK_GEN1 clocks */
 594         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
 595         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
 596         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
 597         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 598         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
 599         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 600         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
 601         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
 602         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
 603         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
 604         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
 605         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
 606         /* CK_GEN2 clocks */
 607         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
 608         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
 609         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
 610         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 611         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
 612         /* CK_GEN3 clocks */
 613         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
 614         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 615         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
 616         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 617         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 618         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 619         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 620         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310 | CK_7XX),
 621         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 622         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 623         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 624         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
 625         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 626         /* ULPD clocks */
 627         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 628         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 629         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 630         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 631         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 632         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 633         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 634         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 635         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 636         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
 637         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 638         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 639         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 640         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 641         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 642         CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
 643         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 644         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 645         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 646         /* Virtual clocks */
 647         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 648         CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
 649         CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
 650         CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
 651         CLK("omap1_spi100k.1", "fck",   &dummy_ck,      CK_7XX),
 652         CLK("omap1_spi100k.1", "ick",   &dummy_ck,      CK_7XX),
 653         CLK("omap1_spi100k.2", "fck",   &dummy_ck,      CK_7XX),
 654         CLK("omap1_spi100k.2", "ick",   &dummy_ck,      CK_7XX),
 655         CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 656         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 657         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 658         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 659         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 660         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 661         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 662         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 663         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 664         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 665 };
 666
 667 /*
 668  * init
 669  */
 670
 671 static struct clk_functions omap1_clk_functions = {
 672         .clk_enable             = omap1_clk_enable,
 673         .clk_disable            = omap1_clk_disable,
 674         .clk_round_rate         = omap1_clk_round_rate,
 675         .clk_set_rate           = omap1_clk_set_rate,
 676         .clk_disable_unused     = omap1_clk_disable_unused,
 677 };
 678
 679 int __init omap1_clk_init(void)
 680 {
 681         struct omap_clk *c;
 682         const struct omap_clock_config *info;
 683         int crystal_type = 0; /* Default 12 MHz */
 684         u32 reg, cpu_mask;
 685
 686 #ifdef CONFIG_DEBUG_LL
 687         /*
 688          * Resets some clocks that may be left on from bootloader,
 689          * but leaves serial clocks on.
 690          */
 691         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 692 #endif
 693
 694         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 695         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 696         omap_writew(reg, SOFT_REQ_REG);
 697         if (!cpu_is_omap15xx())
 698                 omap_writew(0, SOFT_REQ_REG2);
 699
 700         clk_init(&omap1_clk_functions);
 701
 702         /* By default all idlect1 clocks are allowed to idle */
 703         arm_idlect1_mask = ~0;
 704
 705         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 706                 clk_preinit(c->lk.clk);
 707
 708         cpu_mask = 0;
 709         if (cpu_is_omap16xx())
 710                 cpu_mask |= CK_16XX;
 711         if (cpu_is_omap1510())
 712                 cpu_mask |= CK_1510;
 713         if (cpu_is_omap7xx())
 714                 cpu_mask |= CK_7XX;
 715         if (cpu_is_omap310())
 716                 cpu_mask |= CK_310;
 717
 718         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 719                 if (c->cpu & cpu_mask) {
 720                         clkdev_add(&c->lk);
 721                         clk_register(c->lk.clk);
 722                 }
 723
 724         /* Pointers to these clocks are needed by code in clock.c */
 725         api_ck_p = clk_get(NULL, "api_ck");
 726         ck_dpll1_p = clk_get(NULL, "ck_dpll1");
 727         ck_ref_p = clk_get(NULL, "ck_ref");
 728
 729         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 730         if (info != NULL) {
 731                 if (!cpu_is_omap15xx())
 732                         crystal_type = info->system_clock_type;
 733         }
 734
 735 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 736         ck_ref.rate = 13000000;
 737 #elif defined(CONFIG_ARCH_OMAP16XX)
 738         if (crystal_type == 2)
 739                 ck_ref.rate = 19200000;
 740 #endif
 741
 742         pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
 743                 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 744                 omap_readw(ARM_CKCTL));
 745
 746         /* We want to be in syncronous scalable mode */
 747         omap_writew(0x1000, ARM_SYSST);
 748
 749 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 750         /* Use values set by bootloader. Determine PLL rate and recalculate
 751          * dependent clocks as if kernel had changed PLL or divisors.
 752          */
 753         {
 754                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 755
 756                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 757                 if (pll_ctl_val & 0x10) {
 758                         /* PLL enabled, apply multiplier and divisor */
 759                         if (pll_ctl_val & 0xf80)
 760                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 761                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 762                 } else {
 763                         /* PLL disabled, apply bypass divisor */
 764                         switch (pll_ctl_val & 0xc) {
 765                         case 0:
 766                                 break;
 767                         case 0x4:
 768                                 ck_dpll1.rate /= 2;
 769                                 break;
 770                         default:
 771                                 ck_dpll1.rate /= 4;
 772                                 break;
 773                         }
 774                 }
 775         }
 776 #else
 777         /* Find the highest supported frequency and enable it */
 778         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 779                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 780                 /* Guess sane values (60MHz) */
 781                 omap_writew(0x2290, DPLL_CTL);
 782                 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
 783                 ck_dpll1.rate = 60000000;
 784         }
 785 #endif
 786         propagate_rate(&ck_dpll1);
 787         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 788         propagate_rate(&ck_ref);
 789         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 790                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 791                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 792                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 793                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 794
 795 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 796         /* Select slicer output as OMAP input clock */
 797         omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
 798 #endif
 799
 800         /* Amstrad Delta wants BCLK high when inactive */
 801         if (machine_is_ams_delta())
 802                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 803                                 (1 << SDW_MCLK_INV_BIT),
 804                                 ULPD_CLOCK_CTRL);
 805
 806         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 807         /* (on 730, bit 13 must not be cleared) */
 808         if (cpu_is_omap7xx())
 809                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 810         else
 811                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 812
 813         /* Put DSP/MPUI into reset until needed */
 814         omap_writew(0, ARM_RSTCT1);
 815         omap_writew(1, ARM_RSTCT2);
 816         omap_writew(0x400, ARM_IDLECT1);
 817
 818         /*
 819          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 820          * of the ARM_IDLECT2 register must be set to zero. The power-on
 821          * default value of this bit is one.
 822          */
 823         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 824
 825         /*
 826          * Only enable those clocks we will need, let the drivers
 827          * enable other clocks as necessary
 828          */
 829         clk_enable(&armper_ck.clk);
 830         clk_enable(&armxor_ck.clk);
 831         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 832
 833         if (cpu_is_omap15xx())
 834                 clk_enable(&arm_gpio_ck);
 835
 836         return 0;
 837 }