2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
15 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
16 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/platform_device.h>
36 #include <linux/gpio.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/serial.h>
40 #include <mach/irqs.h>
41 #include <mach/hardware.h>
42 #include <mach/common.h>
47 #if defined(CONFIG_ARCH_MX1)
48 static struct resource imx1_camera_resources[] = {
52 .flags = IORESOURCE_MEM,
56 .flags = IORESOURCE_IRQ,
60 static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
62 struct platform_device imx1_camera_device = {
64 .id = 0, /* This is used to put cameras on this interface */
66 .dma_mask = &imx1_camera_dmamask,
67 .coherent_dma_mask = DMA_BIT_MASK(32),
69 .resource = imx1_camera_resources,
70 .num_resources = ARRAY_SIZE(imx1_camera_resources),
73 #define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts) \
74 static struct resource imx1_uart_resources ## n[] = { \
77 .end = baseaddr + 0xd0, \
78 .flags = IORESOURCE_MEM, \
82 .flags = IORESOURCE_IRQ, \
86 .flags = IORESOURCE_IRQ, \
90 .flags = IORESOURCE_IRQ, \
94 struct platform_device imx1_uart_device ## n = { \
97 .num_resources = ARRAY_SIZE(imx1_uart_resources ## n), \
98 .resource = imx1_uart_resources ## n, \
101 DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR, MX1_UART1_MINT_RX, MX1_UART1_MINT_TX, MX1_UART1_MINT_RTS);
102 DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR, MX1_UART2_MINT_RX, MX1_UART2_MINT_TX, MX1_UART2_MINT_RTS);
104 static struct resource imx_rtc_resources[] = {
108 .flags = IORESOURCE_MEM,
110 .start = MX1_RTC_INT,
112 .flags = IORESOURCE_IRQ,
114 .start = MX1_RTC_SAMINT,
115 .end = MX1_RTC_SAMINT,
116 .flags = IORESOURCE_IRQ,
120 struct platform_device imx_rtc_device = {
123 .resource = imx_rtc_resources,
124 .num_resources = ARRAY_SIZE(imx_rtc_resources),
127 static struct resource imx_wdt_resources[] = {
131 .flags = IORESOURCE_MEM,
133 .start = MX1_WDT_INT,
135 .flags = IORESOURCE_IRQ,
139 struct platform_device imx_wdt_device = {
142 .resource = imx_wdt_resources,
143 .num_resources = ARRAY_SIZE(imx_wdt_resources),
146 static struct resource imx_usb_resources[] = {
150 .flags = IORESOURCE_MEM,
152 .start = MX1_USBD_INT0,
153 .end = MX1_USBD_INT0,
154 .flags = IORESOURCE_IRQ,
156 .start = MX1_USBD_INT1,
157 .end = MX1_USBD_INT1,
158 .flags = IORESOURCE_IRQ,
160 .start = MX1_USBD_INT2,
161 .end = MX1_USBD_INT2,
162 .flags = IORESOURCE_IRQ,
164 .start = MX1_USBD_INT3,
165 .end = MX1_USBD_INT3,
166 .flags = IORESOURCE_IRQ,
168 .start = MX1_USBD_INT4,
169 .end = MX1_USBD_INT4,
170 .flags = IORESOURCE_IRQ,
172 .start = MX1_USBD_INT5,
173 .end = MX1_USBD_INT5,
174 .flags = IORESOURCE_IRQ,
176 .start = MX1_USBD_INT6,
177 .end = MX1_USBD_INT6,
178 .flags = IORESOURCE_IRQ,
182 struct platform_device imx_usb_device = {
185 .num_resources = ARRAY_SIZE(imx_usb_resources),
186 .resource = imx_usb_resources,
189 /* GPIO port description */
190 static struct mxc_gpio_port imx_gpio_ports[] = {
192 .chip.label = "gpio-0",
193 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
194 .irq = MX1_GPIO_INT_PORTA,
195 .virtual_irq_start = MXC_GPIO_IRQ_START,
197 .chip.label = "gpio-1",
198 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
199 .irq = MX1_GPIO_INT_PORTB,
200 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
202 .chip.label = "gpio-2",
203 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
204 .irq = MX1_GPIO_INT_PORTC,
205 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
207 .chip.label = "gpio-3",
208 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
209 .irq = MX1_GPIO_INT_PORTD,
210 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
214 int __init imx1_register_gpios(void)
216 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
220 #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
222 * SPI master controller
224 * - i.MX1: 2 channel (slighly different register setting)
225 * - i.MX21: 2 channel
226 * - i.MX27: 3 channel
228 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
229 static struct resource mxc_spi_resources ## n[] = { \
232 .end = baseaddr + SZ_4K - 1, \
233 .flags = IORESOURCE_MEM, \
237 .flags = IORESOURCE_IRQ, \
241 struct platform_device mxc_spi_device ## n = { \
244 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
245 .resource = mxc_spi_resources ## n, \
248 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
249 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
251 #ifdef CONFIG_MACH_MX27
252 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
256 * General Purpose Timer
260 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
261 static struct resource timer ## n ##_resources[] = { \
264 .end = baseaddr + SZ_4K - 1, \
265 .flags = IORESOURCE_MEM, \
269 .flags = IORESOURCE_IRQ, \
273 struct platform_device mxc_gpt ## n = { \
276 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
277 .resource = timer ## n ## _resources, \
280 /* We use gpt1 as system timer, so do not add a device for this one */
281 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
282 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
284 #ifdef CONFIG_MACH_MX27
285 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
286 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
287 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
290 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
291 static struct resource mxc_wdt_resources[] = {
293 .start = MX2x_WDOG_BASE_ADDR,
294 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
295 .flags = IORESOURCE_MEM,
299 struct platform_device mxc_wdt = {
302 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
303 .resource = mxc_wdt_resources,
306 static struct resource mxc_w1_master_resources[] = {
308 .start = MX2x_OWIRE_BASE_ADDR,
309 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
310 .flags = IORESOURCE_MEM,
314 struct platform_device mxc_w1_master_device = {
317 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
318 .resource = mxc_w1_master_resources,
323 * - i.MX1: the basic controller
324 * - i.MX21: to be checked
325 * - i.MX27: like i.MX1, with slightly variations
327 static struct resource mxc_fb[] = {
329 .start = MX2x_LCDC_BASE_ADDR,
330 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
331 .flags = IORESOURCE_MEM,
333 .start = MX2x_INT_LCDC,
334 .end = MX2x_INT_LCDC,
335 .flags = IORESOURCE_IRQ,
340 struct platform_device mxc_fb_device = {
343 .num_resources = ARRAY_SIZE(mxc_fb),
346 .coherent_dma_mask = DMA_BIT_MASK(32),
350 #ifdef CONFIG_MACH_MX27
351 static struct resource mxc_fec_resources[] = {
353 .start = MX27_FEC_BASE_ADDR,
354 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
355 .flags = IORESOURCE_MEM,
357 .start = MX27_INT_FEC,
359 .flags = IORESOURCE_IRQ,
363 struct platform_device mxc_fec_device = {
366 .num_resources = ARRAY_SIZE(mxc_fec_resources),
367 .resource = mxc_fec_resources,
371 #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
372 static struct resource mxc_i2c_resources ## n[] = { \
375 .end = baseaddr + SZ_4K - 1, \
376 .flags = IORESOURCE_MEM, \
380 .flags = IORESOURCE_IRQ, \
384 struct platform_device mxc_i2c_device ## n = { \
387 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
388 .resource = mxc_i2c_resources ## n, \
391 DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
393 #ifdef CONFIG_MACH_MX27
394 DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
397 static struct resource mxc_pwm_resources[] = {
399 .start = MX2x_PWM_BASE_ADDR,
400 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
401 .flags = IORESOURCE_MEM,
403 .start = MX2x_INT_PWM,
405 .flags = IORESOURCE_IRQ,
409 struct platform_device mxc_pwm_device = {
412 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
413 .resource = mxc_pwm_resources,
416 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
417 static struct resource mxc_sdhc_resources ## n[] = { \
420 .end = baseaddr + SZ_4K - 1, \
421 .flags = IORESOURCE_MEM, \
425 .flags = IORESOURCE_IRQ, \
429 .flags = IORESOURCE_DMA, \
433 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
435 struct platform_device mxc_sdhc_device ## n = { \
439 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
440 .coherent_dma_mask = DMA_BIT_MASK(32), \
442 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
443 .resource = mxc_sdhc_resources ## n, \
446 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
447 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
449 #ifdef CONFIG_MACH_MX27
450 static struct resource otg_resources[] = {
452 .start = MX27_USBOTG_BASE_ADDR,
453 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
454 .flags = IORESOURCE_MEM,
456 .start = MX27_INT_USB3,
457 .end = MX27_INT_USB3,
458 .flags = IORESOURCE_IRQ,
462 static u64 otg_dmamask = DMA_BIT_MASK(32);
464 /* OTG gadget device */
465 struct platform_device mxc_otg_udc_device = {
466 .name = "fsl-usb2-udc",
469 .dma_mask = &otg_dmamask,
470 .coherent_dma_mask = DMA_BIT_MASK(32),
472 .resource = otg_resources,
473 .num_resources = ARRAY_SIZE(otg_resources),
477 struct platform_device mxc_otg_host = {
481 .coherent_dma_mask = DMA_BIT_MASK(32),
482 .dma_mask = &otg_dmamask,
484 .resource = otg_resources,
485 .num_resources = ARRAY_SIZE(otg_resources),
490 static u64 usbh1_dmamask = DMA_BIT_MASK(32);
492 static struct resource mxc_usbh1_resources[] = {
494 .start = MX27_USBOTG_BASE_ADDR + 0x200,
495 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
496 .flags = IORESOURCE_MEM,
498 .start = MX27_INT_USB1,
499 .end = MX27_INT_USB1,
500 .flags = IORESOURCE_IRQ,
504 struct platform_device mxc_usbh1 = {
508 .coherent_dma_mask = DMA_BIT_MASK(32),
509 .dma_mask = &usbh1_dmamask,
511 .resource = mxc_usbh1_resources,
512 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
516 static u64 usbh2_dmamask = DMA_BIT_MASK(32);
518 static struct resource mxc_usbh2_resources[] = {
520 .start = MX27_USBOTG_BASE_ADDR + 0x400,
521 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
522 .flags = IORESOURCE_MEM,
524 .start = MX27_INT_USB2,
525 .end = MX27_INT_USB2,
526 .flags = IORESOURCE_IRQ,
530 struct platform_device mxc_usbh2 = {
534 .coherent_dma_mask = DMA_BIT_MASK(32),
535 .dma_mask = &usbh2_dmamask,
537 .resource = mxc_usbh2_resources,
538 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
542 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
545 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
546 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
547 .flags = IORESOURCE_DMA, \
550 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
551 static struct resource imx_ssi_resources ## n[] = { \
553 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
554 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
555 .flags = IORESOURCE_MEM, \
557 .start = MX2x_INT_SSI1, \
558 .end = MX2x_INT_SSI1, \
559 .flags = IORESOURCE_IRQ, \
561 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
562 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
563 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
564 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
567 struct platform_device imx_ssi_device ## n = { \
570 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
571 .resource = imx_ssi_resources ## n, \
574 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
575 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
577 #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \
578 static struct resource imx2x_uart_resources ## n[] = { \
581 .end = baseaddr + 0xb5, \
582 .flags = IORESOURCE_MEM, \
586 .flags = IORESOURCE_IRQ, \
590 struct platform_device imx2x_uart_device ## n = { \
591 .name = "imx-uart", \
593 .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
594 .resource = imx2x_uart_resources ## n, \
597 DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
598 DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
599 DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
600 DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
602 #ifdef CONFIG_MACH_MX27
603 DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
604 DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
607 /* GPIO port description */
608 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
610 .chip.label = "gpio-" #n, \
612 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
614 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
617 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
619 .chip.label = "gpio-" #n, \
620 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
622 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
625 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
626 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
627 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
628 DEFINE_MXC_GPIO_PORT(SOC, 1), \
629 DEFINE_MXC_GPIO_PORT(SOC, 2), \
630 DEFINE_MXC_GPIO_PORT(SOC, 3), \
631 DEFINE_MXC_GPIO_PORT(SOC, 4), \
632 DEFINE_MXC_GPIO_PORT(SOC, 5), \
635 #ifdef CONFIG_MACH_MX21
636 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
638 int __init imx21_register_gpios(void)
640 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
644 #ifdef CONFIG_MACH_MX27
645 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
647 int __init imx27_register_gpios(void)
649 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
653 #ifdef CONFIG_MACH_MX21
654 static struct resource mx21_usbhc_resources[] = {
656 .start = MX21_USBOTG_BASE_ADDR,
657 .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
658 .flags = IORESOURCE_MEM,
661 .start = MX21_INT_USBHOST,
662 .end = MX21_INT_USBHOST,
663 .flags = IORESOURCE_IRQ,
667 struct platform_device mx21_usbhc_device = {
671 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
672 .coherent_dma_mask = DMA_BIT_MASK(32),
674 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
675 .resource = mx21_usbhc_resources,