arch/arm/mach-davinci/devices-tnetv107x.c

   1 /*
   2  * Texas Instruments TNETV107X SoC devices
   3  *
   4  * Copyright (C) 2010 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/clk.h>
  20 #include <linux/slab.h>
  21
  22 #include <mach/common.h>
  23 #include <mach/irqs.h>
  24 #include <mach/edma.h>
  25 #include <mach/tnetv107x.h>
  26
  27 #include "clock.h"
  28
  29 /* Base addresses for on-chip devices */
  30 #define TNETV107X_TPCC_BASE                     0x01c00000
  31 #define TNETV107X_TPTC0_BASE                    0x01c10000
  32 #define TNETV107X_TPTC1_BASE                    0x01c10400
  33 #define TNETV107X_WDOG_BASE                     0x08086700
  34 #define TNETV107X_SDIO0_BASE                    0x08088700
  35 #define TNETV107X_SDIO1_BASE                    0x08088800
  36 #define TNETV107X_ASYNC_EMIF_CNTRL_BASE         0x08200000
  37 #define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE      0x30000000
  38 #define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE      0x40000000
  39 #define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE      0x44000000
  40 #define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE      0x48000000
  41
  42 /* TNETV107X specific EDMA3 information */
  43 #define EDMA_TNETV107X_NUM_DMACH        64
  44 #define EDMA_TNETV107X_NUM_TCC          64
  45 #define EDMA_TNETV107X_NUM_PARAMENTRY   128
  46 #define EDMA_TNETV107X_NUM_EVQUE        2
  47 #define EDMA_TNETV107X_NUM_TC           2
  48 #define EDMA_TNETV107X_CHMAP_EXIST      0
  49 #define EDMA_TNETV107X_NUM_REGIONS      4
  50 #define TNETV107X_DMACH2EVENT_MAP0      0x3C0CE000u
  51 #define TNETV107X_DMACH2EVENT_MAP1      0x000FFFFFu
  52
  53 #define TNETV107X_DMACH_SDIO0_RX                26
  54 #define TNETV107X_DMACH_SDIO0_TX                27
  55 #define TNETV107X_DMACH_SDIO1_RX                28
  56 #define TNETV107X_DMACH_SDIO1_TX                29
  57
  58 static const s8 edma_tc_mapping[][2] = {
  59         /* event queue no       TC no   */
  60         {        0,              0      },
  61         {        1,              1      },
  62         {       -1,             -1      }
  63 };
  64
  65 static const s8 edma_priority_mapping[][2] = {
  66         /* event queue no       Prio    */
  67         {        0,              3      },
  68         {        1,              7      },
  69         {       -1,             -1      }
  70 };
  71
  72 static struct edma_soc_info edma_info[] = {
  73         {
  74                 .n_channel              = EDMA_TNETV107X_NUM_DMACH,
  75                 .n_region               = EDMA_TNETV107X_NUM_REGIONS,
  76                 .n_slot                 = EDMA_TNETV107X_NUM_PARAMENTRY,
  77                 .n_tc                   = EDMA_TNETV107X_NUM_TC,
  78                 .n_cc                   = 1,
  79                 .queue_tc_mapping       = edma_tc_mapping,
  80                 .queue_priority_mapping = edma_priority_mapping,
  81         },
  82 };
  83
  84 static struct resource edma_resources[] = {
  85         {
  86                 .name   = "edma_cc0",
  87                 .start  = TNETV107X_TPCC_BASE,
  88                 .end    = TNETV107X_TPCC_BASE + SZ_32K - 1,
  89                 .flags  = IORESOURCE_MEM,
  90         },
  91         {
  92                 .name   = "edma_tc0",
  93                 .start  = TNETV107X_TPTC0_BASE,
  94                 .end    = TNETV107X_TPTC0_BASE + SZ_1K - 1,
  95                 .flags  = IORESOURCE_MEM,
  96         },
  97         {
  98                 .name   = "edma_tc1",
  99                 .start  = TNETV107X_TPTC1_BASE,
 100                 .end    = TNETV107X_TPTC1_BASE + SZ_1K - 1,
 101                 .flags  = IORESOURCE_MEM,
 102         },
 103         {
 104                 .name   = "edma0",
 105                 .start  = IRQ_TNETV107X_TPCC,
 106                 .flags  = IORESOURCE_IRQ,
 107         },
 108         {
 109                 .name   = "edma0_err",
 110                 .start  = IRQ_TNETV107X_TPCC_ERR,
 111                 .flags  = IORESOURCE_IRQ,
 112         },
 113 };
 114
 115 static struct platform_device edma_device = {
 116         .name           = "edma",
 117         .id             = -1,
 118         .num_resources  = ARRAY_SIZE(edma_resources),
 119         .resource       = edma_resources,
 120         .dev.platform_data = edma_info,
 121 };
 122
 123 static struct plat_serial8250_port serial_data[] = {
 124         {
 125                 .mapbase        = TNETV107X_UART0_BASE,
 126                 .irq            = IRQ_TNETV107X_UART0,
 127                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 128                                         UPF_FIXED_TYPE | UPF_IOREMAP,
 129                 .type           = PORT_AR7,
 130                 .iotype         = UPIO_MEM32,
 131                 .regshift       = 2,
 132         },
 133         {
 134                 .mapbase        = TNETV107X_UART1_BASE,
 135                 .irq            = IRQ_TNETV107X_UART1,
 136                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 137                                         UPF_FIXED_TYPE | UPF_IOREMAP,
 138                 .type           = PORT_AR7,
 139                 .iotype         = UPIO_MEM32,
 140                 .regshift       = 2,
 141         },
 142         {
 143                 .mapbase        = TNETV107X_UART2_BASE,
 144                 .irq            = IRQ_TNETV107X_UART2,
 145                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 146                                         UPF_FIXED_TYPE | UPF_IOREMAP,
 147                 .type           = PORT_AR7,
 148                 .iotype         = UPIO_MEM32,
 149                 .regshift       = 2,
 150         },
 151         {
 152                 .flags  = 0,
 153         },
 154 };
 155
 156 struct platform_device tnetv107x_serial_device = {
 157         .name                   = "serial8250",
 158         .id                     = PLAT8250_DEV_PLATFORM,
 159         .dev.platform_data      = serial_data,
 160 };
 161
 162 static struct resource mmc0_resources[] = {
 163         { /* Memory mapped registers */
 164                 .start  = TNETV107X_SDIO0_BASE,
 165                 .end    = TNETV107X_SDIO0_BASE + 0x0ff,
 166                 .flags  = IORESOURCE_MEM
 167         },
 168         { /* MMC interrupt */
 169                 .start  = IRQ_TNETV107X_MMC0,
 170                 .flags  = IORESOURCE_IRQ
 171         },
 172         { /* SDIO interrupt */
 173                 .start  = IRQ_TNETV107X_SDIO0,
 174                 .flags  = IORESOURCE_IRQ
 175         },
 176         { /* DMA RX */
 177                 .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
 178                 .flags  = IORESOURCE_DMA
 179         },
 180         { /* DMA TX */
 181                 .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
 182                 .flags  = IORESOURCE_DMA
 183         },
 184 };
 185
 186 static struct resource mmc1_resources[] = {
 187         { /* Memory mapped registers */
 188                 .start  = TNETV107X_SDIO1_BASE,
 189                 .end    = TNETV107X_SDIO1_BASE + 0x0ff,
 190                 .flags  = IORESOURCE_MEM
 191         },
 192         { /* MMC interrupt */
 193                 .start  = IRQ_TNETV107X_MMC1,
 194                 .flags  = IORESOURCE_IRQ
 195         },
 196         { /* SDIO interrupt */
 197                 .start  = IRQ_TNETV107X_SDIO1,
 198                 .flags  = IORESOURCE_IRQ
 199         },
 200         { /* DMA RX */
 201                 .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
 202                 .flags  = IORESOURCE_DMA
 203         },
 204         { /* DMA TX */
 205                 .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
 206                 .flags  = IORESOURCE_DMA
 207         },
 208 };
 209
 210 static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
 211 static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
 212
 213 static struct platform_device mmc_devices[2] = {
 214         {
 215                 .name           = "davinci_mmc",
 216                 .id             = 0,
 217                 .dev            = {
 218                         .dma_mask               = &mmc0_dma_mask,
 219                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 220                 },
 221                 .num_resources  = ARRAY_SIZE(mmc0_resources),
 222                 .resource       = mmc0_resources
 223         },
 224         {
 225                 .name           = "davinci_mmc",
 226                 .id             = 1,
 227                 .dev            = {
 228                         .dma_mask               = &mmc1_dma_mask,
 229                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 230                 },
 231                 .num_resources  = ARRAY_SIZE(mmc1_resources),
 232                 .resource       = mmc1_resources
 233         },
 234 };
 235
 236 static const u32 emif_windows[] = {
 237         TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
 238         TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
 239 };
 240
 241 static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
 242
 243 static struct resource wdt_resources[] = {
 244         {
 245                 .start  = TNETV107X_WDOG_BASE,
 246                 .end    = TNETV107X_WDOG_BASE + SZ_4K - 1,
 247                 .flags  = IORESOURCE_MEM,
 248         },
 249 };
 250
 251 struct platform_device tnetv107x_wdt_device = {
 252         .name           = "tnetv107x_wdt",
 253         .id             = 0,
 254         .num_resources  = ARRAY_SIZE(wdt_resources),
 255         .resource       = wdt_resources,
 256 };
 257
 258 static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
 259 {
 260         struct resource res[2];
 261         struct platform_device *pdev;
 262         u32     range;
 263         int     ret;
 264
 265         /* Figure out the resource range from the ale/cle masks */
 266         range = max(data->mask_cle, data->mask_ale);
 267         range = PAGE_ALIGN(range + 4) - 1;
 268
 269         if (range >= emif_window_sizes[chipsel])
 270                 return -EINVAL;
 271
 272         pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
 273         if (!pdev)
 274                 return -ENOMEM;
 275
 276         pdev->name              = "davinci_nand";
 277         pdev->id                = chipsel;
 278         pdev->dev.platform_data = data;
 279
 280         memset(res, 0, sizeof(res));
 281
 282         res[0].start    = emif_windows[chipsel];
 283         res[0].end      = res[0].start + range;
 284         res[0].flags    = IORESOURCE_MEM;
 285
 286         res[1].start    = TNETV107X_ASYNC_EMIF_CNTRL_BASE;
 287         res[1].end      = res[1].start + SZ_4K - 1;
 288         res[1].flags    = IORESOURCE_MEM;
 289
 290         ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
 291         if (ret < 0) {
 292                 kfree(pdev);
 293                 return ret;
 294         }
 295
 296         return platform_device_register(pdev);
 297 }
 298
 299 void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
 300 {
 301         int i;
 302
 303         platform_device_register(&edma_device);
 304         platform_device_register(&tnetv107x_wdt_device);
 305
 306         if (info->serial_config)
 307                 davinci_serial_init(info->serial_config);
 308
 309         for (i = 0; i < 2; i++)
 310                 if (info->mmc_config[i]) {
 311                         mmc_devices[i].dev.platform_data = info->mmc_config[i];
 312                         platform_device_register(&mmc_devices[i]);
 313                 }
 314
 315         for (i = 0; i < 4; i++)
 316                 if (info->nand_config[i])
 317                         nand_init(i, info->nand_config[i]);
 318 }