arch/arm/mach-davinci/devices-da8xx.c

   1 /*
   2  * DA8XX/OMAP L1XX platform device data
   3  *
   4  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
   5  * Derived from code that was:
   6  *      Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/serial_8250.h>
  17
  18 #include <mach/cputype.h>
  19 #include <mach/common.h>
  20 #include <mach/time.h>
  21 #include <mach/da8xx.h>
  22 #include <mach/cpuidle.h>
  23
  24 #include "clock.h"
  25
  26 #define DA8XX_TPCC_BASE                 0x01c00000
  27 #define DA850_MMCSD1_BASE               0x01e1b000
  28 #define DA850_TPCC1_BASE                0x01e30000
  29 #define DA8XX_TPTC0_BASE                0x01c08000
  30 #define DA8XX_TPTC1_BASE                0x01c08400
  31 #define DA850_TPTC2_BASE                0x01e38000
  32 #define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
  33 #define DA8XX_I2C0_BASE                 0x01c22000
  34 #define DA8XX_RTC_BASE                  0x01C23000
  35 #define DA8XX_EMAC_CPPI_PORT_BASE       0x01e20000
  36 #define DA8XX_EMAC_CPGMACSS_BASE        0x01e22000
  37 #define DA8XX_EMAC_CPGMAC_BASE          0x01e23000
  38 #define DA8XX_EMAC_MDIO_BASE            0x01e24000
  39 #define DA8XX_GPIO_BASE                 0x01e26000
  40 #define DA8XX_I2C1_BASE                 0x01e28000
  41
  42 #define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
  43 #define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
  44 #define DA8XX_EMAC_RAM_OFFSET           0x0000
  45 #define DA8XX_MDIO_REG_OFFSET           0x4000
  46 #define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
  47
  48 void __iomem *da8xx_syscfg0_base;
  49 void __iomem *da8xx_syscfg1_base;
  50
  51 static struct plat_serial8250_port da8xx_serial_pdata[] = {
  52         {
  53                 .mapbase        = DA8XX_UART0_BASE,
  54                 .irq            = IRQ_DA8XX_UARTINT0,
  55                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  56                                         UPF_IOREMAP,
  57                 .iotype         = UPIO_MEM,
  58                 .regshift       = 2,
  59         },
  60         {
  61                 .mapbase        = DA8XX_UART1_BASE,
  62                 .irq            = IRQ_DA8XX_UARTINT1,
  63                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  64                                         UPF_IOREMAP,
  65                 .iotype         = UPIO_MEM,
  66                 .regshift       = 2,
  67         },
  68         {
  69                 .mapbase        = DA8XX_UART2_BASE,
  70                 .irq            = IRQ_DA8XX_UARTINT2,
  71                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  72                                         UPF_IOREMAP,
  73                 .iotype         = UPIO_MEM,
  74                 .regshift       = 2,
  75         },
  76         {
  77                 .flags  = 0,
  78         },
  79 };
  80
  81 struct platform_device da8xx_serial_device = {
  82         .name   = "serial8250",
  83         .id     = PLAT8250_DEV_PLATFORM,
  84         .dev    = {
  85                 .platform_data  = da8xx_serial_pdata,
  86         },
  87 };
  88
  89 static const s8 da8xx_queue_tc_mapping[][2] = {
  90         /* {event queue no, TC no} */
  91         {0, 0},
  92         {1, 1},
  93         {-1, -1}
  94 };
  95
  96 static const s8 da8xx_queue_priority_mapping[][2] = {
  97         /* {event queue no, Priority} */
  98         {0, 3},
  99         {1, 7},
 100         {-1, -1}
 101 };
 102
 103 static const s8 da850_queue_tc_mapping[][2] = {
 104         /* {event queue no, TC no} */
 105         {0, 0},
 106         {-1, -1}
 107 };
 108
 109 static const s8 da850_queue_priority_mapping[][2] = {
 110         /* {event queue no, Priority} */
 111         {0, 3},
 112         {-1, -1}
 113 };
 114
 115 static struct edma_soc_info da830_edma_cc0_info = {
 116         .n_channel              = 32,
 117         .n_region               = 4,
 118         .n_slot                 = 128,
 119         .n_tc                   = 2,
 120         .n_cc                   = 1,
 121         .queue_tc_mapping       = da8xx_queue_tc_mapping,
 122         .queue_priority_mapping = da8xx_queue_priority_mapping,
 123 };
 124
 125 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
 126         &da830_edma_cc0_info,
 127 };
 128
 129 static struct edma_soc_info da850_edma_cc_info[] = {
 130         {
 131                 .n_channel              = 32,
 132                 .n_region               = 4,
 133                 .n_slot                 = 128,
 134                 .n_tc                   = 2,
 135                 .n_cc                   = 1,
 136                 .queue_tc_mapping       = da8xx_queue_tc_mapping,
 137                 .queue_priority_mapping = da8xx_queue_priority_mapping,
 138         },
 139         {
 140                 .n_channel              = 32,
 141                 .n_region               = 4,
 142                 .n_slot                 = 128,
 143                 .n_tc                   = 1,
 144                 .n_cc                   = 1,
 145                 .queue_tc_mapping       = da850_queue_tc_mapping,
 146                 .queue_priority_mapping = da850_queue_priority_mapping,
 147         },
 148 };
 149
 150 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
 151         &da850_edma_cc_info[0],
 152         &da850_edma_cc_info[1],
 153 };
 154
 155 static struct resource da830_edma_resources[] = {
 156         {
 157                 .name   = "edma_cc0",
 158                 .start  = DA8XX_TPCC_BASE,
 159                 .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
 160                 .flags  = IORESOURCE_MEM,
 161         },
 162         {
 163                 .name   = "edma_tc0",
 164                 .start  = DA8XX_TPTC0_BASE,
 165                 .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
 166                 .flags  = IORESOURCE_MEM,
 167         },
 168         {
 169                 .name   = "edma_tc1",
 170                 .start  = DA8XX_TPTC1_BASE,
 171                 .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
 172                 .flags  = IORESOURCE_MEM,
 173         },
 174         {
 175                 .name   = "edma0",
 176                 .start  = IRQ_DA8XX_CCINT0,
 177                 .flags  = IORESOURCE_IRQ,
 178         },
 179         {
 180                 .name   = "edma0_err",
 181                 .start  = IRQ_DA8XX_CCERRINT,
 182                 .flags  = IORESOURCE_IRQ,
 183         },
 184 };
 185
 186 static struct resource da850_edma_resources[] = {
 187         {
 188                 .name   = "edma_cc0",
 189                 .start  = DA8XX_TPCC_BASE,
 190                 .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
 191                 .flags  = IORESOURCE_MEM,
 192         },
 193         {
 194                 .name   = "edma_tc0",
 195                 .start  = DA8XX_TPTC0_BASE,
 196                 .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
 197                 .flags  = IORESOURCE_MEM,
 198         },
 199         {
 200                 .name   = "edma_tc1",
 201                 .start  = DA8XX_TPTC1_BASE,
 202                 .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
 203                 .flags  = IORESOURCE_MEM,
 204         },
 205         {
 206                 .name   = "edma_cc1",
 207                 .start  = DA850_TPCC1_BASE,
 208                 .end    = DA850_TPCC1_BASE + SZ_32K - 1,
 209                 .flags  = IORESOURCE_MEM,
 210         },
 211         {
 212                 .name   = "edma_tc2",
 213                 .start  = DA850_TPTC2_BASE,
 214                 .end    = DA850_TPTC2_BASE + SZ_1K - 1,
 215                 .flags  = IORESOURCE_MEM,
 216         },
 217         {
 218                 .name   = "edma0",
 219                 .start  = IRQ_DA8XX_CCINT0,
 220                 .flags  = IORESOURCE_IRQ,
 221         },
 222         {
 223                 .name   = "edma0_err",
 224                 .start  = IRQ_DA8XX_CCERRINT,
 225                 .flags  = IORESOURCE_IRQ,
 226         },
 227         {
 228                 .name   = "edma1",
 229                 .start  = IRQ_DA850_CCINT1,
 230                 .flags  = IORESOURCE_IRQ,
 231         },
 232         {
 233                 .name   = "edma1_err",
 234                 .start  = IRQ_DA850_CCERRINT1,
 235                 .flags  = IORESOURCE_IRQ,
 236         },
 237 };
 238
 239 static struct platform_device da830_edma_device = {
 240         .name           = "edma",
 241         .id             = -1,
 242         .dev = {
 243                 .platform_data = da830_edma_info,
 244         },
 245         .num_resources  = ARRAY_SIZE(da830_edma_resources),
 246         .resource       = da830_edma_resources,
 247 };
 248
 249 static struct platform_device da850_edma_device = {
 250         .name           = "edma",
 251         .id             = -1,
 252         .dev = {
 253                 .platform_data = da850_edma_info,
 254         },
 255         .num_resources  = ARRAY_SIZE(da850_edma_resources),
 256         .resource       = da850_edma_resources,
 257 };
 258
 259 int __init da830_register_edma(struct edma_rsv_info *rsv)
 260 {
 261         da830_edma_cc0_info.rsv = rsv;
 262
 263         return platform_device_register(&da830_edma_device);
 264 }
 265
 266 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
 267 {
 268         if (rsv) {
 269                 da850_edma_cc_info[0].rsv = rsv[0];
 270                 da850_edma_cc_info[1].rsv = rsv[1];
 271         }
 272
 273         return platform_device_register(&da850_edma_device);
 274 }
 275
 276 static struct resource da8xx_i2c_resources0[] = {
 277         {
 278                 .start  = DA8XX_I2C0_BASE,
 279                 .end    = DA8XX_I2C0_BASE + SZ_4K - 1,
 280                 .flags  = IORESOURCE_MEM,
 281         },
 282         {
 283                 .start  = IRQ_DA8XX_I2CINT0,
 284                 .end    = IRQ_DA8XX_I2CINT0,
 285                 .flags  = IORESOURCE_IRQ,
 286         },
 287 };
 288
 289 static struct platform_device da8xx_i2c_device0 = {
 290         .name           = "i2c_davinci",
 291         .id             = 1,
 292         .num_resources  = ARRAY_SIZE(da8xx_i2c_resources0),
 293         .resource       = da8xx_i2c_resources0,
 294 };
 295
 296 static struct resource da8xx_i2c_resources1[] = {
 297         {
 298                 .start  = DA8XX_I2C1_BASE,
 299                 .end    = DA8XX_I2C1_BASE + SZ_4K - 1,
 300                 .flags  = IORESOURCE_MEM,
 301         },
 302         {
 303                 .start  = IRQ_DA8XX_I2CINT1,
 304                 .end    = IRQ_DA8XX_I2CINT1,
 305                 .flags  = IORESOURCE_IRQ,
 306         },
 307 };
 308
 309 static struct platform_device da8xx_i2c_device1 = {
 310         .name           = "i2c_davinci",
 311         .id             = 2,
 312         .num_resources  = ARRAY_SIZE(da8xx_i2c_resources1),
 313         .resource       = da8xx_i2c_resources1,
 314 };
 315
 316 int __init da8xx_register_i2c(int instance,
 317                 struct davinci_i2c_platform_data *pdata)
 318 {
 319         struct platform_device *pdev;
 320
 321         if (instance == 0)
 322                 pdev = &da8xx_i2c_device0;
 323         else if (instance == 1)
 324                 pdev = &da8xx_i2c_device1;
 325         else
 326                 return -EINVAL;
 327
 328         pdev->dev.platform_data = pdata;
 329         return platform_device_register(pdev);
 330 }
 331
 332 static struct resource da8xx_watchdog_resources[] = {
 333         {
 334                 .start  = DA8XX_WDOG_BASE,
 335                 .end    = DA8XX_WDOG_BASE + SZ_4K - 1,
 336                 .flags  = IORESOURCE_MEM,
 337         },
 338 };
 339
 340 struct platform_device da8xx_wdt_device = {
 341         .name           = "watchdog",
 342         .id             = -1,
 343         .num_resources  = ARRAY_SIZE(da8xx_watchdog_resources),
 344         .resource       = da8xx_watchdog_resources,
 345 };
 346
 347 int __init da8xx_register_watchdog(void)
 348 {
 349         return platform_device_register(&da8xx_wdt_device);
 350 }
 351
 352 static struct resource da8xx_emac_resources[] = {
 353         {
 354                 .start  = DA8XX_EMAC_CPPI_PORT_BASE,
 355                 .end    = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
 356                 .flags  = IORESOURCE_MEM,
 357         },
 358         {
 359                 .start  = IRQ_DA8XX_C0_RX_THRESH_PULSE,
 360                 .end    = IRQ_DA8XX_C0_RX_THRESH_PULSE,
 361                 .flags  = IORESOURCE_IRQ,
 362         },
 363         {
 364                 .start  = IRQ_DA8XX_C0_RX_PULSE,
 365                 .end    = IRQ_DA8XX_C0_RX_PULSE,
 366                 .flags  = IORESOURCE_IRQ,
 367         },
 368         {
 369                 .start  = IRQ_DA8XX_C0_TX_PULSE,
 370                 .end    = IRQ_DA8XX_C0_TX_PULSE,
 371                 .flags  = IORESOURCE_IRQ,
 372         },
 373         {
 374                 .start  = IRQ_DA8XX_C0_MISC_PULSE,
 375                 .end    = IRQ_DA8XX_C0_MISC_PULSE,
 376                 .flags  = IORESOURCE_IRQ,
 377         },
 378 };
 379
 380 struct emac_platform_data da8xx_emac_pdata = {
 381         .ctrl_reg_offset        = DA8XX_EMAC_CTRL_REG_OFFSET,
 382         .ctrl_mod_reg_offset    = DA8XX_EMAC_MOD_REG_OFFSET,
 383         .ctrl_ram_offset        = DA8XX_EMAC_RAM_OFFSET,
 384         .mdio_reg_offset        = DA8XX_MDIO_REG_OFFSET,
 385         .ctrl_ram_size          = DA8XX_EMAC_CTRL_RAM_SIZE,
 386         .version                = EMAC_VERSION_2,
 387 };
 388
 389 static struct platform_device da8xx_emac_device = {
 390         .name           = "davinci_emac",
 391         .id             = 1,
 392         .dev = {
 393                 .platform_data  = &da8xx_emac_pdata,
 394         },
 395         .num_resources  = ARRAY_SIZE(da8xx_emac_resources),
 396         .resource       = da8xx_emac_resources,
 397 };
 398
 399 int __init da8xx_register_emac(void)
 400 {
 401         return platform_device_register(&da8xx_emac_device);
 402 }
 403
 404 static struct resource da830_mcasp1_resources[] = {
 405         {
 406                 .name   = "mcasp1",
 407                 .start  = DAVINCI_DA830_MCASP1_REG_BASE,
 408                 .end    = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
 409                 .flags  = IORESOURCE_MEM,
 410         },
 411         /* TX event */
 412         {
 413                 .start  = DAVINCI_DA830_DMA_MCASP1_AXEVT,
 414                 .end    = DAVINCI_DA830_DMA_MCASP1_AXEVT,
 415                 .flags  = IORESOURCE_DMA,
 416         },
 417         /* RX event */
 418         {
 419                 .start  = DAVINCI_DA830_DMA_MCASP1_AREVT,
 420                 .end    = DAVINCI_DA830_DMA_MCASP1_AREVT,
 421                 .flags  = IORESOURCE_DMA,
 422         },
 423 };
 424
 425 static struct platform_device da830_mcasp1_device = {
 426         .name           = "davinci-mcasp",
 427         .id             = 1,
 428         .num_resources  = ARRAY_SIZE(da830_mcasp1_resources),
 429         .resource       = da830_mcasp1_resources,
 430 };
 431
 432 static struct resource da850_mcasp_resources[] = {
 433         {
 434                 .name   = "mcasp",
 435                 .start  = DAVINCI_DA8XX_MCASP0_REG_BASE,
 436                 .end    = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
 437                 .flags  = IORESOURCE_MEM,
 438         },
 439         /* TX event */
 440         {
 441                 .start  = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 442                 .end    = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 443                 .flags  = IORESOURCE_DMA,
 444         },
 445         /* RX event */
 446         {
 447                 .start  = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 448                 .end    = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 449                 .flags  = IORESOURCE_DMA,
 450         },
 451 };
 452
 453 static struct platform_device da850_mcasp_device = {
 454         .name           = "davinci-mcasp",
 455         .id             = 0,
 456         .num_resources  = ARRAY_SIZE(da850_mcasp_resources),
 457         .resource       = da850_mcasp_resources,
 458 };
 459
 460 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 461 {
 462         /* DA830/OMAP-L137 has 3 instances of McASP */
 463         if (cpu_is_davinci_da830() && id == 1) {
 464                 da830_mcasp1_device.dev.platform_data = pdata;
 465                 platform_device_register(&da830_mcasp1_device);
 466         } else if (cpu_is_davinci_da850()) {
 467                 da850_mcasp_device.dev.platform_data = pdata;
 468                 platform_device_register(&da850_mcasp_device);
 469         }
 470 }
 471
 472 static const struct display_panel disp_panel = {
 473         QVGA,
 474         16,
 475         16,
 476         COLOR_ACTIVE,
 477 };
 478
 479 static struct lcd_ctrl_config lcd_cfg = {
 480         &disp_panel,
 481         .ac_bias                = 255,
 482         .ac_bias_intrpt         = 0,
 483         .dma_burst_sz           = 16,
 484         .bpp                    = 16,
 485         .fdd                    = 255,
 486         .tft_alt_mode           = 0,
 487         .stn_565_mode           = 0,
 488         .mono_8bit_mode         = 0,
 489         .invert_line_clock      = 1,
 490         .invert_frm_clock       = 1,
 491         .sync_edge              = 0,
 492         .sync_ctrl              = 1,
 493         .raster_order           = 0,
 494 };
 495
 496 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
 497         .manu_name              = "sharp",
 498         .controller_data        = &lcd_cfg,
 499         .type                   = "Sharp_LCD035Q3DG01",
 500 };
 501
 502 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
 503         .manu_name              = "sharp",
 504         .controller_data        = &lcd_cfg,
 505         .type                   = "Sharp_LK043T1DG01",
 506 };
 507
 508 static struct resource da8xx_lcdc_resources[] = {
 509         [0] = { /* registers */
 510                 .start  = DA8XX_LCD_CNTRL_BASE,
 511                 .end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
 512                 .flags  = IORESOURCE_MEM,
 513         },
 514         [1] = { /* interrupt */
 515                 .start  = IRQ_DA8XX_LCDINT,
 516                 .end    = IRQ_DA8XX_LCDINT,
 517                 .flags  = IORESOURCE_IRQ,
 518         },
 519 };
 520
 521 static struct platform_device da8xx_lcdc_device = {
 522         .name           = "da8xx_lcdc",
 523         .id             = 0,
 524         .num_resources  = ARRAY_SIZE(da8xx_lcdc_resources),
 525         .resource       = da8xx_lcdc_resources,
 526 };
 527
 528 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
 529 {
 530         da8xx_lcdc_device.dev.platform_data = pdata;
 531         return platform_device_register(&da8xx_lcdc_device);
 532 }
 533
 534 static struct resource da8xx_mmcsd0_resources[] = {
 535         {               /* registers */
 536                 .start  = DA8XX_MMCSD0_BASE,
 537                 .end    = DA8XX_MMCSD0_BASE + SZ_4K - 1,
 538                 .flags  = IORESOURCE_MEM,
 539         },
 540         {               /* interrupt */
 541                 .start  = IRQ_DA8XX_MMCSDINT0,
 542                 .end    = IRQ_DA8XX_MMCSDINT0,
 543                 .flags  = IORESOURCE_IRQ,
 544         },
 545         {               /* DMA RX */
 546                 .start  = EDMA_CTLR_CHAN(0, 16),
 547                 .end    = EDMA_CTLR_CHAN(0, 16),
 548                 .flags  = IORESOURCE_DMA,
 549         },
 550         {               /* DMA TX */
 551                 .start  = EDMA_CTLR_CHAN(0, 17),
 552                 .end    = EDMA_CTLR_CHAN(0, 17),
 553                 .flags  = IORESOURCE_DMA,
 554         },
 555 };
 556
 557 static struct platform_device da8xx_mmcsd0_device = {
 558         .name           = "davinci_mmc",
 559         .id             = 0,
 560         .num_resources  = ARRAY_SIZE(da8xx_mmcsd0_resources),
 561         .resource       = da8xx_mmcsd0_resources,
 562 };
 563
 564 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
 565 {
 566         da8xx_mmcsd0_device.dev.platform_data = config;
 567         return platform_device_register(&da8xx_mmcsd0_device);
 568 }
 569
 570 #ifdef CONFIG_ARCH_DAVINCI_DA850
 571 static struct resource da850_mmcsd1_resources[] = {
 572         {               /* registers */
 573                 .start  = DA850_MMCSD1_BASE,
 574                 .end    = DA850_MMCSD1_BASE + SZ_4K - 1,
 575                 .flags  = IORESOURCE_MEM,
 576         },
 577         {               /* interrupt */
 578                 .start  = IRQ_DA850_MMCSDINT0_1,
 579                 .end    = IRQ_DA850_MMCSDINT0_1,
 580                 .flags  = IORESOURCE_IRQ,
 581         },
 582         {               /* DMA RX */
 583                 .start  = EDMA_CTLR_CHAN(1, 28),
 584                 .end    = EDMA_CTLR_CHAN(1, 28),
 585                 .flags  = IORESOURCE_DMA,
 586         },
 587         {               /* DMA TX */
 588                 .start  = EDMA_CTLR_CHAN(1, 29),
 589                 .end    = EDMA_CTLR_CHAN(1, 29),
 590                 .flags  = IORESOURCE_DMA,
 591         },
 592 };
 593
 594 static struct platform_device da850_mmcsd1_device = {
 595         .name           = "davinci_mmc",
 596         .id             = 1,
 597         .num_resources  = ARRAY_SIZE(da850_mmcsd1_resources),
 598         .resource       = da850_mmcsd1_resources,
 599 };
 600
 601 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
 602 {
 603         da850_mmcsd1_device.dev.platform_data = config;
 604         return platform_device_register(&da850_mmcsd1_device);
 605 }
 606 #endif
 607
 608 static struct resource da8xx_rtc_resources[] = {
 609         {
 610                 .start          = DA8XX_RTC_BASE,
 611                 .end            = DA8XX_RTC_BASE + SZ_4K - 1,
 612                 .flags          = IORESOURCE_MEM,
 613         },
 614         { /* timer irq */
 615                 .start          = IRQ_DA8XX_RTC,
 616                 .end            = IRQ_DA8XX_RTC,
 617                 .flags          = IORESOURCE_IRQ,
 618         },
 619         { /* alarm irq */
 620                 .start          = IRQ_DA8XX_RTC,
 621                 .end            = IRQ_DA8XX_RTC,
 622                 .flags          = IORESOURCE_IRQ,
 623         },
 624 };
 625
 626 static struct platform_device da8xx_rtc_device = {
 627         .name           = "omap_rtc",
 628         .id             = -1,
 629         .num_resources  = ARRAY_SIZE(da8xx_rtc_resources),
 630         .resource       = da8xx_rtc_resources,
 631 };
 632
 633 int da8xx_register_rtc(void)
 634 {
 635         int ret;
 636         void __iomem *base;
 637
 638         base = ioremap(DA8XX_RTC_BASE, SZ_4K);
 639         if (WARN_ON(!base))
 640                 return -ENOMEM;
 641
 642         /* Unlock the rtc's registers */
 643         __raw_writel(0x83e70b13, base + 0x6c);
 644         __raw_writel(0x95a4f1e0, base + 0x70);
 645
 646         iounmap(base);
 647
 648         ret = platform_device_register(&da8xx_rtc_device);
 649         if (!ret)
 650                 /* Atleast on DA850, RTC is a wakeup source */
 651                 device_init_wakeup(&da8xx_rtc_device.dev, true);
 652
 653         return ret;
 654 }
 655
 656 static void __iomem *da8xx_ddr2_ctlr_base;
 657 void __iomem * __init da8xx_get_mem_ctlr(void)
 658 {
 659         if (da8xx_ddr2_ctlr_base)
 660                 return da8xx_ddr2_ctlr_base;
 661
 662         da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
 663         if (!da8xx_ddr2_ctlr_base)
 664                 pr_warning("%s: Unable to map DDR2 controller", __func__);
 665
 666         return da8xx_ddr2_ctlr_base;
 667 }
 668
 669 static struct resource da8xx_cpuidle_resources[] = {
 670         {
 671                 .start          = DA8XX_DDR2_CTL_BASE,
 672                 .end            = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
 673                 .flags          = IORESOURCE_MEM,
 674         },
 675 };
 676
 677 /* DA8XX devices support DDR2 power down */
 678 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
 679         .ddr2_pdown     = 1,
 680 };
 681
 682
 683 static struct platform_device da8xx_cpuidle_device = {
 684         .name                   = "cpuidle-davinci",
 685         .num_resources          = ARRAY_SIZE(da8xx_cpuidle_resources),
 686         .resource               = da8xx_cpuidle_resources,
 687         .dev = {
 688                 .platform_data  = &da8xx_cpuidle_pdata,
 689         },
 690 };
 691
 692 int __init da8xx_register_cpuidle(void)
 693 {
 694         da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
 695
 696         return platform_device_register(&da8xx_cpuidle_device);
 697 }