2 * TI DaVinci clock definitions
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #ifndef __ARCH_ARM_DAVINCI_CLOCK_H
13 #define __ARCH_ARM_DAVINCI_CLOCK_H
15 #include <linux/list.h>
16 #include <asm/clkdev.h>
18 #define DAVINCI_PLL1_BASE 0x01c40800
19 #define DAVINCI_PLL2_BASE 0x01c40c00
22 /* PLL/Reset register offsets */
24 #define PLLCTL_PLLEN BIT(0)
25 #define PLLCTL_PLLPWRDN BIT(1)
26 #define PLLCTL_PLLRST BIT(3)
27 #define PLLCTL_PLLDIS BIT(4)
28 #define PLLCTL_PLLENSRC BIT(5)
29 #define PLLCTL_CLKMODE BIT(8)
32 #define PLLM_PLLM_MASK 0xff
42 #define PLLALNCTL 0x140
43 #define PLLDCHANGE 0x144
45 #define PLLCKSTAT 0x14c
46 #define PLLSYSTAT 0x150
53 #define PLLDIV_EN BIT(15)
54 #define PLLDIV_RATIO_MASK 0x1f
57 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
58 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
59 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
60 * is ~25MHz. Units are micro seconds.
62 #define PLL_BYPASS_TIME 1
63 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
64 #define PLL_RESET_TIME 1
66 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
67 * Units are micro seconds.
69 #define PLL_LOCK_TIME 20
78 #define PLL_HAS_PREDIV 0x01
79 #define PLL_HAS_POSTDIV 0x02
82 struct list_head node;
91 struct list_head children; /* list of children */
92 struct list_head childnode; /* parent's child list node */
93 struct pll_data *pll_data;
95 unsigned long (*recalc) (struct clk *);
96 int (*set_rate) (struct clk *clk, unsigned long rate);
97 int (*round_rate) (struct clk *clk, unsigned long rate);
100 /* Clock flags: SoC-specific flags start at BIT(16) */
101 #define ALWAYS_ENABLED BIT(1)
102 #define CLK_PSC BIT(2)
103 #define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
104 #define CLK_PLL BIT(4) /* PLL-derived clock */
105 #define PRE_PLL BIT(5) /* source is before PLL mult/div */
108 struct clk_lookup lk;
111 #define CLK(dev, con, ck) \
120 int davinci_clk_init(struct davinci_clk *clocks);
121 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
122 unsigned int mult, unsigned int postdiv);
124 extern struct platform_device davinci_wdt_device;