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tg3: Prevent rx producer ring overruns
[net-next-2.6.git] / drivers / net / tg3.c
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CommitLineData
1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
26#include <linux/in.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/phy.h>
36#include <linux/brcmphy.h>
37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
41#include <linux/prefetch.h>
42#include <linux/dma-mapping.h>
43#include <linux/firmware.h>
44
45#include <net/checksum.h>
46#include <net/ip.h>
47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
53#ifdef CONFIG_SPARC
54#include <asm/idprom.h>
55#include <asm/prom.h>
56#endif
57
58#define BAR_0 0
59#define BAR_2 2
60
61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
71#define DRV_MODULE_VERSION "3.106"
72#define DRV_MODULE_RELDATE "January 12, 2010"
73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105#define TG3_RSS_INDIR_TBL_SIZE 128
106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125 TG3_RX_RCB_RING_SIZE(tp))
126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139
140#define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143#define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
146/* minimum number of free TX descriptors required to wake up TX process */
147#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
148
149#define TG3_RAW_IP_ALIGN 2
150
151/* number of ETHTOOL_GSTATS u64's */
152#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
154#define TG3_NUM_TEST 6
155
156#define FIRMWARE_TG3 "tigon/tg3.bin"
157#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
160static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165MODULE_LICENSE("GPL");
166MODULE_VERSION(DRV_MODULE_VERSION);
167MODULE_FIRMWARE(FIRMWARE_TG3);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
171#define TG3_RSS_MIN_NUM_MSIX_VECS 2
172
173static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174module_param(tg3_debug, int, 0);
175MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
177static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
253 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
254 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
255 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
256 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
257 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
258 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
259 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
260 {}
261};
262
263MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
264
265static const struct {
266 const char string[ETH_GSTRING_LEN];
267} ethtool_stats_keys[TG3_NUM_STATS] = {
268 { "rx_octets" },
269 { "rx_fragments" },
270 { "rx_ucast_packets" },
271 { "rx_mcast_packets" },
272 { "rx_bcast_packets" },
273 { "rx_fcs_errors" },
274 { "rx_align_errors" },
275 { "rx_xon_pause_rcvd" },
276 { "rx_xoff_pause_rcvd" },
277 { "rx_mac_ctrl_rcvd" },
278 { "rx_xoff_entered" },
279 { "rx_frame_too_long_errors" },
280 { "rx_jabbers" },
281 { "rx_undersize_packets" },
282 { "rx_in_length_errors" },
283 { "rx_out_length_errors" },
284 { "rx_64_or_less_octet_packets" },
285 { "rx_65_to_127_octet_packets" },
286 { "rx_128_to_255_octet_packets" },
287 { "rx_256_to_511_octet_packets" },
288 { "rx_512_to_1023_octet_packets" },
289 { "rx_1024_to_1522_octet_packets" },
290 { "rx_1523_to_2047_octet_packets" },
291 { "rx_2048_to_4095_octet_packets" },
292 { "rx_4096_to_8191_octet_packets" },
293 { "rx_8192_to_9022_octet_packets" },
294
295 { "tx_octets" },
296 { "tx_collisions" },
297
298 { "tx_xon_sent" },
299 { "tx_xoff_sent" },
300 { "tx_flow_control" },
301 { "tx_mac_errors" },
302 { "tx_single_collisions" },
303 { "tx_mult_collisions" },
304 { "tx_deferred" },
305 { "tx_excessive_collisions" },
306 { "tx_late_collisions" },
307 { "tx_collide_2times" },
308 { "tx_collide_3times" },
309 { "tx_collide_4times" },
310 { "tx_collide_5times" },
311 { "tx_collide_6times" },
312 { "tx_collide_7times" },
313 { "tx_collide_8times" },
314 { "tx_collide_9times" },
315 { "tx_collide_10times" },
316 { "tx_collide_11times" },
317 { "tx_collide_12times" },
318 { "tx_collide_13times" },
319 { "tx_collide_14times" },
320 { "tx_collide_15times" },
321 { "tx_ucast_packets" },
322 { "tx_mcast_packets" },
323 { "tx_bcast_packets" },
324 { "tx_carrier_sense_errors" },
325 { "tx_discards" },
326 { "tx_errors" },
327
328 { "dma_writeq_full" },
329 { "dma_write_prioq_full" },
330 { "rxbds_empty" },
331 { "rx_discards" },
332 { "rx_errors" },
333 { "rx_threshold_hit" },
334
335 { "dma_readq_full" },
336 { "dma_read_prioq_full" },
337 { "tx_comp_queue_full" },
338
339 { "ring_set_send_prod_index" },
340 { "ring_status_update" },
341 { "nic_irqs" },
342 { "nic_avoided_irqs" },
343 { "nic_tx_threshold_hit" }
344};
345
346static const struct {
347 const char string[ETH_GSTRING_LEN];
348} ethtool_test_keys[TG3_NUM_TEST] = {
349 { "nvram test (online) " },
350 { "link test (online) " },
351 { "register test (offline)" },
352 { "memory test (offline)" },
353 { "loopback test (offline)" },
354 { "interrupt test (offline)" },
355};
356
357static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
358{
359 writel(val, tp->regs + off);
360}
361
362static u32 tg3_read32(struct tg3 *tp, u32 off)
363{
364 return (readl(tp->regs + off));
365}
366
367static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
368{
369 writel(val, tp->aperegs + off);
370}
371
372static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
373{
374 return (readl(tp->aperegs + off));
375}
376
377static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
378{
379 unsigned long flags;
380
381 spin_lock_irqsave(&tp->indirect_lock, flags);
382 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
383 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
384 spin_unlock_irqrestore(&tp->indirect_lock, flags);
385}
386
387static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
388{
389 writel(val, tp->regs + off);
390 readl(tp->regs + off);
391}
392
393static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
394{
395 unsigned long flags;
396 u32 val;
397
398 spin_lock_irqsave(&tp->indirect_lock, flags);
399 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
400 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
401 spin_unlock_irqrestore(&tp->indirect_lock, flags);
402 return val;
403}
404
405static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
406{
407 unsigned long flags;
408
409 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
410 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
411 TG3_64BIT_REG_LOW, val);
412 return;
413 }
414 if (off == TG3_RX_STD_PROD_IDX_REG) {
415 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
416 TG3_64BIT_REG_LOW, val);
417 return;
418 }
419
420 spin_lock_irqsave(&tp->indirect_lock, flags);
421 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
422 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
423 spin_unlock_irqrestore(&tp->indirect_lock, flags);
424
425 /* In indirect mode when disabling interrupts, we also need
426 * to clear the interrupt bit in the GRC local ctrl register.
427 */
428 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
429 (val == 0x1)) {
430 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
431 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
432 }
433}
434
435static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
436{
437 unsigned long flags;
438 u32 val;
439
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
442 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
444 return val;
445}
446
447/* usec_wait specifies the wait time in usec when writing to certain registers
448 * where it is unsafe to read back the register without some delay.
449 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
450 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
451 */
452static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
453{
454 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
455 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
456 /* Non-posted methods */
457 tp->write32(tp, off, val);
458 else {
459 /* Posted method */
460 tg3_write32(tp, off, val);
461 if (usec_wait)
462 udelay(usec_wait);
463 tp->read32(tp, off);
464 }
465 /* Wait again after the read for the posted method to guarantee that
466 * the wait time is met.
467 */
468 if (usec_wait)
469 udelay(usec_wait);
470}
471
472static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
473{
474 tp->write32_mbox(tp, off, val);
475 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
476 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
477 tp->read32_mbox(tp, off);
478}
479
480static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
481{
482 void __iomem *mbox = tp->regs + off;
483 writel(val, mbox);
484 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
485 writel(val, mbox);
486 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
487 readl(mbox);
488}
489
490static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
491{
492 return (readl(tp->regs + off + GRCMBOX_BASE));
493}
494
495static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
496{
497 writel(val, tp->regs + off + GRCMBOX_BASE);
498}
499
500#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
501#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
502#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
503#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
504#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
505
506#define tw32(reg,val) tp->write32(tp, reg, val)
507#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
508#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
509#define tr32(reg) tp->read32(tp, reg)
510
511static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
512{
513 unsigned long flags;
514
515 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
516 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
517 return;
518
519 spin_lock_irqsave(&tp->indirect_lock, flags);
520 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
521 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
523
524 /* Always leave this as zero. */
525 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 } else {
527 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
528 tw32_f(TG3PCI_MEM_WIN_DATA, val);
529
530 /* Always leave this as zero. */
531 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
532 }
533 spin_unlock_irqrestore(&tp->indirect_lock, flags);
534}
535
536static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
537{
538 unsigned long flags;
539
540 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
541 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
542 *val = 0;
543 return;
544 }
545
546 spin_lock_irqsave(&tp->indirect_lock, flags);
547 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
548 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
549 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
550
551 /* Always leave this as zero. */
552 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
553 } else {
554 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
555 *val = tr32(TG3PCI_MEM_WIN_DATA);
556
557 /* Always leave this as zero. */
558 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
559 }
560 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561}
562
563static void tg3_ape_lock_init(struct tg3 *tp)
564{
565 int i;
566
567 /* Make sure the driver hasn't any stale locks. */
568 for (i = 0; i < 8; i++)
569 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
570 APE_LOCK_GRANT_DRIVER);
571}
572
573static int tg3_ape_lock(struct tg3 *tp, int locknum)
574{
575 int i, off;
576 int ret = 0;
577 u32 status;
578
579 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
580 return 0;
581
582 switch (locknum) {
583 case TG3_APE_LOCK_GRC:
584 case TG3_APE_LOCK_MEM:
585 break;
586 default:
587 return -EINVAL;
588 }
589
590 off = 4 * locknum;
591
592 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
593
594 /* Wait for up to 1 millisecond to acquire lock. */
595 for (i = 0; i < 100; i++) {
596 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
597 if (status == APE_LOCK_GRANT_DRIVER)
598 break;
599 udelay(10);
600 }
601
602 if (status != APE_LOCK_GRANT_DRIVER) {
603 /* Revoke the lock request. */
604 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
605 APE_LOCK_GRANT_DRIVER);
606
607 ret = -EBUSY;
608 }
609
610 return ret;
611}
612
613static void tg3_ape_unlock(struct tg3 *tp, int locknum)
614{
615 int off;
616
617 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
618 return;
619
620 switch (locknum) {
621 case TG3_APE_LOCK_GRC:
622 case TG3_APE_LOCK_MEM:
623 break;
624 default:
625 return;
626 }
627
628 off = 4 * locknum;
629 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
630}
631
632static void tg3_disable_ints(struct tg3 *tp)
633{
634 int i;
635
636 tw32(TG3PCI_MISC_HOST_CTRL,
637 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
638 for (i = 0; i < tp->irq_max; i++)
639 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
640}
641
642static void tg3_enable_ints(struct tg3 *tp)
643{
644 int i;
645 u32 coal_now = 0;
646
647 tp->irq_sync = 0;
648 wmb();
649
650 tw32(TG3PCI_MISC_HOST_CTRL,
651 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
652
653 for (i = 0; i < tp->irq_cnt; i++) {
654 struct tg3_napi *tnapi = &tp->napi[i];
655 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
656 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
657 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
658
659 coal_now |= tnapi->coal_now;
660 }
661
662 /* Force an initial interrupt */
663 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
664 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
665 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
666 else
667 tw32(HOSTCC_MODE, tp->coalesce_mode |
668 HOSTCC_MODE_ENABLE | coal_now);
669}
670
671static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
672{
673 struct tg3 *tp = tnapi->tp;
674 struct tg3_hw_status *sblk = tnapi->hw_status;
675 unsigned int work_exists = 0;
676
677 /* check for phy events */
678 if (!(tp->tg3_flags &
679 (TG3_FLAG_USE_LINKCHG_REG |
680 TG3_FLAG_POLL_SERDES))) {
681 if (sblk->status & SD_STATUS_LINK_CHG)
682 work_exists = 1;
683 }
684 /* check for RX/TX work to do */
685 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
686 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
687 work_exists = 1;
688
689 return work_exists;
690}
691
692/* tg3_int_reenable
693 * similar to tg3_enable_ints, but it accurately determines whether there
694 * is new work pending and can return without flushing the PIO write
695 * which reenables interrupts
696 */
697static void tg3_int_reenable(struct tg3_napi *tnapi)
698{
699 struct tg3 *tp = tnapi->tp;
700
701 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
702 mmiowb();
703
704 /* When doing tagged status, this work check is unnecessary.
705 * The last_tag we write above tells the chip which piece of
706 * work we've completed.
707 */
708 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
709 tg3_has_work(tnapi))
710 tw32(HOSTCC_MODE, tp->coalesce_mode |
711 HOSTCC_MODE_ENABLE | tnapi->coal_now);
712}
713
714static void tg3_napi_disable(struct tg3 *tp)
715{
716 int i;
717
718 for (i = tp->irq_cnt - 1; i >= 0; i--)
719 napi_disable(&tp->napi[i].napi);
720}
721
722static void tg3_napi_enable(struct tg3 *tp)
723{
724 int i;
725
726 for (i = 0; i < tp->irq_cnt; i++)
727 napi_enable(&tp->napi[i].napi);
728}
729
730static inline void tg3_netif_stop(struct tg3 *tp)
731{
732 tp->dev->trans_start = jiffies; /* prevent tx timeout */
733 tg3_napi_disable(tp);
734 netif_tx_disable(tp->dev);
735}
736
737static inline void tg3_netif_start(struct tg3 *tp)
738{
739 /* NOTE: unconditional netif_tx_wake_all_queues is only
740 * appropriate so long as all callers are assured to
741 * have free tx slots (such as after tg3_init_hw)
742 */
743 netif_tx_wake_all_queues(tp->dev);
744
745 tg3_napi_enable(tp);
746 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
747 tg3_enable_ints(tp);
748}
749
750static void tg3_switch_clocks(struct tg3 *tp)
751{
752 u32 clock_ctrl;
753 u32 orig_clock_ctrl;
754
755 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
756 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
757 return;
758
759 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
760
761 orig_clock_ctrl = clock_ctrl;
762 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
763 CLOCK_CTRL_CLKRUN_OENABLE |
764 0x1f);
765 tp->pci_clock_ctrl = clock_ctrl;
766
767 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
768 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
769 tw32_wait_f(TG3PCI_CLOCK_CTRL,
770 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
771 }
772 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
773 tw32_wait_f(TG3PCI_CLOCK_CTRL,
774 clock_ctrl |
775 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
776 40);
777 tw32_wait_f(TG3PCI_CLOCK_CTRL,
778 clock_ctrl | (CLOCK_CTRL_ALTCLK),
779 40);
780 }
781 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
782}
783
784#define PHY_BUSY_LOOPS 5000
785
786static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
787{
788 u32 frame_val;
789 unsigned int loops;
790 int ret;
791
792 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
793 tw32_f(MAC_MI_MODE,
794 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
795 udelay(80);
796 }
797
798 *val = 0x0;
799
800 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
801 MI_COM_PHY_ADDR_MASK);
802 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
803 MI_COM_REG_ADDR_MASK);
804 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
805
806 tw32_f(MAC_MI_COM, frame_val);
807
808 loops = PHY_BUSY_LOOPS;
809 while (loops != 0) {
810 udelay(10);
811 frame_val = tr32(MAC_MI_COM);
812
813 if ((frame_val & MI_COM_BUSY) == 0) {
814 udelay(5);
815 frame_val = tr32(MAC_MI_COM);
816 break;
817 }
818 loops -= 1;
819 }
820
821 ret = -EBUSY;
822 if (loops != 0) {
823 *val = frame_val & MI_COM_DATA_MASK;
824 ret = 0;
825 }
826
827 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
828 tw32_f(MAC_MI_MODE, tp->mi_mode);
829 udelay(80);
830 }
831
832 return ret;
833}
834
835static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
836{
837 u32 frame_val;
838 unsigned int loops;
839 int ret;
840
841 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
842 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
843 return 0;
844
845 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
846 tw32_f(MAC_MI_MODE,
847 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
848 udelay(80);
849 }
850
851 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
852 MI_COM_PHY_ADDR_MASK);
853 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
854 MI_COM_REG_ADDR_MASK);
855 frame_val |= (val & MI_COM_DATA_MASK);
856 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
857
858 tw32_f(MAC_MI_COM, frame_val);
859
860 loops = PHY_BUSY_LOOPS;
861 while (loops != 0) {
862 udelay(10);
863 frame_val = tr32(MAC_MI_COM);
864 if ((frame_val & MI_COM_BUSY) == 0) {
865 udelay(5);
866 frame_val = tr32(MAC_MI_COM);
867 break;
868 }
869 loops -= 1;
870 }
871
872 ret = -EBUSY;
873 if (loops != 0)
874 ret = 0;
875
876 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
877 tw32_f(MAC_MI_MODE, tp->mi_mode);
878 udelay(80);
879 }
880
881 return ret;
882}
883
884static int tg3_bmcr_reset(struct tg3 *tp)
885{
886 u32 phy_control;
887 int limit, err;
888
889 /* OK, reset it, and poll the BMCR_RESET bit until it
890 * clears or we time out.
891 */
892 phy_control = BMCR_RESET;
893 err = tg3_writephy(tp, MII_BMCR, phy_control);
894 if (err != 0)
895 return -EBUSY;
896
897 limit = 5000;
898 while (limit--) {
899 err = tg3_readphy(tp, MII_BMCR, &phy_control);
900 if (err != 0)
901 return -EBUSY;
902
903 if ((phy_control & BMCR_RESET) == 0) {
904 udelay(40);
905 break;
906 }
907 udelay(10);
908 }
909 if (limit < 0)
910 return -EBUSY;
911
912 return 0;
913}
914
915static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
916{
917 struct tg3 *tp = bp->priv;
918 u32 val;
919
920 spin_lock_bh(&tp->lock);
921
922 if (tg3_readphy(tp, reg, &val))
923 val = -EIO;
924
925 spin_unlock_bh(&tp->lock);
926
927 return val;
928}
929
930static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
931{
932 struct tg3 *tp = bp->priv;
933 u32 ret = 0;
934
935 spin_lock_bh(&tp->lock);
936
937 if (tg3_writephy(tp, reg, val))
938 ret = -EIO;
939
940 spin_unlock_bh(&tp->lock);
941
942 return ret;
943}
944
945static int tg3_mdio_reset(struct mii_bus *bp)
946{
947 return 0;
948}
949
950static void tg3_mdio_config_5785(struct tg3 *tp)
951{
952 u32 val;
953 struct phy_device *phydev;
954
955 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
956 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
957 case TG3_PHY_ID_BCM50610:
958 case TG3_PHY_ID_BCM50610M:
959 val = MAC_PHYCFG2_50610_LED_MODES;
960 break;
961 case TG3_PHY_ID_BCMAC131:
962 val = MAC_PHYCFG2_AC131_LED_MODES;
963 break;
964 case TG3_PHY_ID_RTL8211C:
965 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
966 break;
967 case TG3_PHY_ID_RTL8201E:
968 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
969 break;
970 default:
971 return;
972 }
973
974 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
975 tw32(MAC_PHYCFG2, val);
976
977 val = tr32(MAC_PHYCFG1);
978 val &= ~(MAC_PHYCFG1_RGMII_INT |
979 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
980 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
981 tw32(MAC_PHYCFG1, val);
982
983 return;
984 }
985
986 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
987 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
988 MAC_PHYCFG2_FMODE_MASK_MASK |
989 MAC_PHYCFG2_GMODE_MASK_MASK |
990 MAC_PHYCFG2_ACT_MASK_MASK |
991 MAC_PHYCFG2_QUAL_MASK_MASK |
992 MAC_PHYCFG2_INBAND_ENABLE;
993
994 tw32(MAC_PHYCFG2, val);
995
996 val = tr32(MAC_PHYCFG1);
997 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
998 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
999 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1000 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1001 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1002 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1003 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1004 }
1005 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1006 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1007 tw32(MAC_PHYCFG1, val);
1008
1009 val = tr32(MAC_EXT_RGMII_MODE);
1010 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1011 MAC_RGMII_MODE_RX_QUALITY |
1012 MAC_RGMII_MODE_RX_ACTIVITY |
1013 MAC_RGMII_MODE_RX_ENG_DET |
1014 MAC_RGMII_MODE_TX_ENABLE |
1015 MAC_RGMII_MODE_TX_LOWPWR |
1016 MAC_RGMII_MODE_TX_RESET);
1017 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1018 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1019 val |= MAC_RGMII_MODE_RX_INT_B |
1020 MAC_RGMII_MODE_RX_QUALITY |
1021 MAC_RGMII_MODE_RX_ACTIVITY |
1022 MAC_RGMII_MODE_RX_ENG_DET;
1023 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1024 val |= MAC_RGMII_MODE_TX_ENABLE |
1025 MAC_RGMII_MODE_TX_LOWPWR |
1026 MAC_RGMII_MODE_TX_RESET;
1027 }
1028 tw32(MAC_EXT_RGMII_MODE, val);
1029}
1030
1031static void tg3_mdio_start(struct tg3 *tp)
1032{
1033 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1034 tw32_f(MAC_MI_MODE, tp->mi_mode);
1035 udelay(80);
1036
1037 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1038 u32 funcnum, is_serdes;
1039
1040 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1041 if (funcnum)
1042 tp->phy_addr = 2;
1043 else
1044 tp->phy_addr = 1;
1045
1046 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1047 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1048 else
1049 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1050 TG3_CPMU_PHY_STRAP_IS_SERDES;
1051 if (is_serdes)
1052 tp->phy_addr += 7;
1053 } else
1054 tp->phy_addr = TG3_PHY_MII_ADDR;
1055
1056 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1058 tg3_mdio_config_5785(tp);
1059}
1060
1061static int tg3_mdio_init(struct tg3 *tp)
1062{
1063 int i;
1064 u32 reg;
1065 struct phy_device *phydev;
1066
1067 tg3_mdio_start(tp);
1068
1069 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1070 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1071 return 0;
1072
1073 tp->mdio_bus = mdiobus_alloc();
1074 if (tp->mdio_bus == NULL)
1075 return -ENOMEM;
1076
1077 tp->mdio_bus->name = "tg3 mdio bus";
1078 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1079 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1080 tp->mdio_bus->priv = tp;
1081 tp->mdio_bus->parent = &tp->pdev->dev;
1082 tp->mdio_bus->read = &tg3_mdio_read;
1083 tp->mdio_bus->write = &tg3_mdio_write;
1084 tp->mdio_bus->reset = &tg3_mdio_reset;
1085 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1086 tp->mdio_bus->irq = &tp->mdio_irq[0];
1087
1088 for (i = 0; i < PHY_MAX_ADDR; i++)
1089 tp->mdio_bus->irq[i] = PHY_POLL;
1090
1091 /* The bus registration will look for all the PHYs on the mdio bus.
1092 * Unfortunately, it does not ensure the PHY is powered up before
1093 * accessing the PHY ID registers. A chip reset is the
1094 * quickest way to bring the device back to an operational state..
1095 */
1096 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1097 tg3_bmcr_reset(tp);
1098
1099 i = mdiobus_register(tp->mdio_bus);
1100 if (i) {
1101 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1102 tp->dev->name, i);
1103 mdiobus_free(tp->mdio_bus);
1104 return i;
1105 }
1106
1107 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1108
1109 if (!phydev || !phydev->drv) {
1110 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1111 mdiobus_unregister(tp->mdio_bus);
1112 mdiobus_free(tp->mdio_bus);
1113 return -ENODEV;
1114 }
1115
1116 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1117 case TG3_PHY_ID_BCM57780:
1118 phydev->interface = PHY_INTERFACE_MODE_GMII;
1119 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1120 break;
1121 case TG3_PHY_ID_BCM50610:
1122 case TG3_PHY_ID_BCM50610M:
1123 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1124 PHY_BRCM_RX_REFCLK_UNUSED |
1125 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1126 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1127 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1128 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1129 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1130 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1131 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1132 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1133 /* fallthru */
1134 case TG3_PHY_ID_RTL8211C:
1135 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1136 break;
1137 case TG3_PHY_ID_RTL8201E:
1138 case TG3_PHY_ID_BCMAC131:
1139 phydev->interface = PHY_INTERFACE_MODE_MII;
1140 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1141 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1142 break;
1143 }
1144
1145 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1146
1147 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1148 tg3_mdio_config_5785(tp);
1149
1150 return 0;
1151}
1152
1153static void tg3_mdio_fini(struct tg3 *tp)
1154{
1155 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1156 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1157 mdiobus_unregister(tp->mdio_bus);
1158 mdiobus_free(tp->mdio_bus);
1159 }
1160}
1161
1162/* tp->lock is held. */
1163static inline void tg3_generate_fw_event(struct tg3 *tp)
1164{
1165 u32 val;
1166
1167 val = tr32(GRC_RX_CPU_EVENT);
1168 val |= GRC_RX_CPU_DRIVER_EVENT;
1169 tw32_f(GRC_RX_CPU_EVENT, val);
1170
1171 tp->last_event_jiffies = jiffies;
1172}
1173
1174#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1175
1176/* tp->lock is held. */
1177static void tg3_wait_for_event_ack(struct tg3 *tp)
1178{
1179 int i;
1180 unsigned int delay_cnt;
1181 long time_remain;
1182
1183 /* If enough time has passed, no wait is necessary. */
1184 time_remain = (long)(tp->last_event_jiffies + 1 +
1185 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1186 (long)jiffies;
1187 if (time_remain < 0)
1188 return;
1189
1190 /* Check if we can shorten the wait time. */
1191 delay_cnt = jiffies_to_usecs(time_remain);
1192 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1193 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1194 delay_cnt = (delay_cnt >> 3) + 1;
1195
1196 for (i = 0; i < delay_cnt; i++) {
1197 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1198 break;
1199 udelay(8);
1200 }
1201}
1202
1203/* tp->lock is held. */
1204static void tg3_ump_link_report(struct tg3 *tp)
1205{
1206 u32 reg;
1207 u32 val;
1208
1209 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1210 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1211 return;
1212
1213 tg3_wait_for_event_ack(tp);
1214
1215 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1216
1217 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1218
1219 val = 0;
1220 if (!tg3_readphy(tp, MII_BMCR, &reg))
1221 val = reg << 16;
1222 if (!tg3_readphy(tp, MII_BMSR, &reg))
1223 val |= (reg & 0xffff);
1224 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1225
1226 val = 0;
1227 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1228 val = reg << 16;
1229 if (!tg3_readphy(tp, MII_LPA, &reg))
1230 val |= (reg & 0xffff);
1231 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1232
1233 val = 0;
1234 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1235 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1236 val = reg << 16;
1237 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1238 val |= (reg & 0xffff);
1239 }
1240 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1241
1242 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1243 val = reg << 16;
1244 else
1245 val = 0;
1246 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1247
1248 tg3_generate_fw_event(tp);
1249}
1250
1251static void tg3_link_report(struct tg3 *tp)
1252{
1253 if (!netif_carrier_ok(tp->dev)) {
1254 if (netif_msg_link(tp))
1255 printk(KERN_INFO PFX "%s: Link is down.\n",
1256 tp->dev->name);
1257 tg3_ump_link_report(tp);
1258 } else if (netif_msg_link(tp)) {
1259 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1260 tp->dev->name,
1261 (tp->link_config.active_speed == SPEED_1000 ?
1262 1000 :
1263 (tp->link_config.active_speed == SPEED_100 ?
1264 100 : 10)),
1265 (tp->link_config.active_duplex == DUPLEX_FULL ?
1266 "full" : "half"));
1267
1268 printk(KERN_INFO PFX
1269 "%s: Flow control is %s for TX and %s for RX.\n",
1270 tp->dev->name,
1271 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1272 "on" : "off",
1273 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1274 "on" : "off");
1275 tg3_ump_link_report(tp);
1276 }
1277}
1278
1279static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1280{
1281 u16 miireg;
1282
1283 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1284 miireg = ADVERTISE_PAUSE_CAP;
1285 else if (flow_ctrl & FLOW_CTRL_TX)
1286 miireg = ADVERTISE_PAUSE_ASYM;
1287 else if (flow_ctrl & FLOW_CTRL_RX)
1288 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1289 else
1290 miireg = 0;
1291
1292 return miireg;
1293}
1294
1295static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1296{
1297 u16 miireg;
1298
1299 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1300 miireg = ADVERTISE_1000XPAUSE;
1301 else if (flow_ctrl & FLOW_CTRL_TX)
1302 miireg = ADVERTISE_1000XPSE_ASYM;
1303 else if (flow_ctrl & FLOW_CTRL_RX)
1304 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1305 else
1306 miireg = 0;
1307
1308 return miireg;
1309}
1310
1311static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1312{
1313 u8 cap = 0;
1314
1315 if (lcladv & ADVERTISE_1000XPAUSE) {
1316 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1317 if (rmtadv & LPA_1000XPAUSE)
1318 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1319 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1320 cap = FLOW_CTRL_RX;
1321 } else {
1322 if (rmtadv & LPA_1000XPAUSE)
1323 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1324 }
1325 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1326 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1327 cap = FLOW_CTRL_TX;
1328 }
1329
1330 return cap;
1331}
1332
1333static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1334{
1335 u8 autoneg;
1336 u8 flowctrl = 0;
1337 u32 old_rx_mode = tp->rx_mode;
1338 u32 old_tx_mode = tp->tx_mode;
1339
1340 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1341 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1342 else
1343 autoneg = tp->link_config.autoneg;
1344
1345 if (autoneg == AUTONEG_ENABLE &&
1346 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1347 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1348 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1349 else
1350 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1351 } else
1352 flowctrl = tp->link_config.flowctrl;
1353
1354 tp->link_config.active_flowctrl = flowctrl;
1355
1356 if (flowctrl & FLOW_CTRL_RX)
1357 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1358 else
1359 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1360
1361 if (old_rx_mode != tp->rx_mode)
1362 tw32_f(MAC_RX_MODE, tp->rx_mode);
1363
1364 if (flowctrl & FLOW_CTRL_TX)
1365 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1366 else
1367 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1368
1369 if (old_tx_mode != tp->tx_mode)
1370 tw32_f(MAC_TX_MODE, tp->tx_mode);
1371}
1372
1373static void tg3_adjust_link(struct net_device *dev)
1374{
1375 u8 oldflowctrl, linkmesg = 0;
1376 u32 mac_mode, lcl_adv, rmt_adv;
1377 struct tg3 *tp = netdev_priv(dev);
1378 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1379
1380 spin_lock_bh(&tp->lock);
1381
1382 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1383 MAC_MODE_HALF_DUPLEX);
1384
1385 oldflowctrl = tp->link_config.active_flowctrl;
1386
1387 if (phydev->link) {
1388 lcl_adv = 0;
1389 rmt_adv = 0;
1390
1391 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1392 mac_mode |= MAC_MODE_PORT_MODE_MII;
1393 else if (phydev->speed == SPEED_1000 ||
1394 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1395 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1396 else
1397 mac_mode |= MAC_MODE_PORT_MODE_MII;
1398
1399 if (phydev->duplex == DUPLEX_HALF)
1400 mac_mode |= MAC_MODE_HALF_DUPLEX;
1401 else {
1402 lcl_adv = tg3_advert_flowctrl_1000T(
1403 tp->link_config.flowctrl);
1404
1405 if (phydev->pause)
1406 rmt_adv = LPA_PAUSE_CAP;
1407 if (phydev->asym_pause)
1408 rmt_adv |= LPA_PAUSE_ASYM;
1409 }
1410
1411 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1412 } else
1413 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1414
1415 if (mac_mode != tp->mac_mode) {
1416 tp->mac_mode = mac_mode;
1417 tw32_f(MAC_MODE, tp->mac_mode);
1418 udelay(40);
1419 }
1420
1421 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1422 if (phydev->speed == SPEED_10)
1423 tw32(MAC_MI_STAT,
1424 MAC_MI_STAT_10MBPS_MODE |
1425 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1426 else
1427 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1428 }
1429
1430 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1431 tw32(MAC_TX_LENGTHS,
1432 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1433 (6 << TX_LENGTHS_IPG_SHIFT) |
1434 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1435 else
1436 tw32(MAC_TX_LENGTHS,
1437 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1438 (6 << TX_LENGTHS_IPG_SHIFT) |
1439 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1440
1441 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1442 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1443 phydev->speed != tp->link_config.active_speed ||
1444 phydev->duplex != tp->link_config.active_duplex ||
1445 oldflowctrl != tp->link_config.active_flowctrl)
1446 linkmesg = 1;
1447
1448 tp->link_config.active_speed = phydev->speed;
1449 tp->link_config.active_duplex = phydev->duplex;
1450
1451 spin_unlock_bh(&tp->lock);
1452
1453 if (linkmesg)
1454 tg3_link_report(tp);
1455}
1456
1457static int tg3_phy_init(struct tg3 *tp)
1458{
1459 struct phy_device *phydev;
1460
1461 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1462 return 0;
1463
1464 /* Bring the PHY back to a known state. */
1465 tg3_bmcr_reset(tp);
1466
1467 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1468
1469 /* Attach the MAC to the PHY. */
1470 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1471 phydev->dev_flags, phydev->interface);
1472 if (IS_ERR(phydev)) {
1473 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1474 return PTR_ERR(phydev);
1475 }
1476
1477 /* Mask with MAC supported features. */
1478 switch (phydev->interface) {
1479 case PHY_INTERFACE_MODE_GMII:
1480 case PHY_INTERFACE_MODE_RGMII:
1481 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1482 phydev->supported &= (PHY_GBIT_FEATURES |
1483 SUPPORTED_Pause |
1484 SUPPORTED_Asym_Pause);
1485 break;
1486 }
1487 /* fallthru */
1488 case PHY_INTERFACE_MODE_MII:
1489 phydev->supported &= (PHY_BASIC_FEATURES |
1490 SUPPORTED_Pause |
1491 SUPPORTED_Asym_Pause);
1492 break;
1493 default:
1494 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1495 return -EINVAL;
1496 }
1497
1498 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1499
1500 phydev->advertising = phydev->supported;
1501
1502 return 0;
1503}
1504
1505static void tg3_phy_start(struct tg3 *tp)
1506{
1507 struct phy_device *phydev;
1508
1509 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1510 return;
1511
1512 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1513
1514 if (tp->link_config.phy_is_low_power) {
1515 tp->link_config.phy_is_low_power = 0;
1516 phydev->speed = tp->link_config.orig_speed;
1517 phydev->duplex = tp->link_config.orig_duplex;
1518 phydev->autoneg = tp->link_config.orig_autoneg;
1519 phydev->advertising = tp->link_config.orig_advertising;
1520 }
1521
1522 phy_start(phydev);
1523
1524 phy_start_aneg(phydev);
1525}
1526
1527static void tg3_phy_stop(struct tg3 *tp)
1528{
1529 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1530 return;
1531
1532 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1533}
1534
1535static void tg3_phy_fini(struct tg3 *tp)
1536{
1537 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1538 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1540 }
1541}
1542
1543static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1544{
1545 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1546 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1547}
1548
1549static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1550{
1551 u32 phytest;
1552
1553 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1554 u32 phy;
1555
1556 tg3_writephy(tp, MII_TG3_FET_TEST,
1557 phytest | MII_TG3_FET_SHADOW_EN);
1558 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1559 if (enable)
1560 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1561 else
1562 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1563 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1564 }
1565 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1566 }
1567}
1568
1569static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1570{
1571 u32 reg;
1572
1573 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1574 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1575 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1576 return;
1577
1578 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1579 tg3_phy_fet_toggle_apd(tp, enable);
1580 return;
1581 }
1582
1583 reg = MII_TG3_MISC_SHDW_WREN |
1584 MII_TG3_MISC_SHDW_SCR5_SEL |
1585 MII_TG3_MISC_SHDW_SCR5_LPED |
1586 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1587 MII_TG3_MISC_SHDW_SCR5_SDTL |
1588 MII_TG3_MISC_SHDW_SCR5_C125OE;
1589 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1590 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1591
1592 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1593
1594
1595 reg = MII_TG3_MISC_SHDW_WREN |
1596 MII_TG3_MISC_SHDW_APD_SEL |
1597 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1598 if (enable)
1599 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1600
1601 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1602}
1603
1604static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1605{
1606 u32 phy;
1607
1608 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1609 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1610 return;
1611
1612 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1613 u32 ephy;
1614
1615 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1616 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1617
1618 tg3_writephy(tp, MII_TG3_FET_TEST,
1619 ephy | MII_TG3_FET_SHADOW_EN);
1620 if (!tg3_readphy(tp, reg, &phy)) {
1621 if (enable)
1622 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1623 else
1624 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1625 tg3_writephy(tp, reg, phy);
1626 }
1627 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1628 }
1629 } else {
1630 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1631 MII_TG3_AUXCTL_SHDWSEL_MISC;
1632 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1633 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1634 if (enable)
1635 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1636 else
1637 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1638 phy |= MII_TG3_AUXCTL_MISC_WREN;
1639 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1640 }
1641 }
1642}
1643
1644static void tg3_phy_set_wirespeed(struct tg3 *tp)
1645{
1646 u32 val;
1647
1648 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1649 return;
1650
1651 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1652 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1653 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1654 (val | (1 << 15) | (1 << 4)));
1655}
1656
1657static void tg3_phy_apply_otp(struct tg3 *tp)
1658{
1659 u32 otp, phy;
1660
1661 if (!tp->phy_otp)
1662 return;
1663
1664 otp = tp->phy_otp;
1665
1666 /* Enable SM_DSP clock and tx 6dB coding. */
1667 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1668 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1669 MII_TG3_AUXCTL_ACTL_TX_6DB;
1670 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1671
1672 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1673 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1674 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1675
1676 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1677 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1678 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1679
1680 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1681 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1682 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1683
1684 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1685 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1686
1687 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1688 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1689
1690 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1691 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1692 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1693
1694 /* Turn off SM_DSP clock. */
1695 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1696 MII_TG3_AUXCTL_ACTL_TX_6DB;
1697 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1698}
1699
1700static int tg3_wait_macro_done(struct tg3 *tp)
1701{
1702 int limit = 100;
1703
1704 while (limit--) {
1705 u32 tmp32;
1706
1707 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1708 if ((tmp32 & 0x1000) == 0)
1709 break;
1710 }
1711 }
1712 if (limit < 0)
1713 return -EBUSY;
1714
1715 return 0;
1716}
1717
1718static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1719{
1720 static const u32 test_pat[4][6] = {
1721 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1722 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1723 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1724 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1725 };
1726 int chan;
1727
1728 for (chan = 0; chan < 4; chan++) {
1729 int i;
1730
1731 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1732 (chan * 0x2000) | 0x0200);
1733 tg3_writephy(tp, 0x16, 0x0002);
1734
1735 for (i = 0; i < 6; i++)
1736 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1737 test_pat[chan][i]);
1738
1739 tg3_writephy(tp, 0x16, 0x0202);
1740 if (tg3_wait_macro_done(tp)) {
1741 *resetp = 1;
1742 return -EBUSY;
1743 }
1744
1745 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1746 (chan * 0x2000) | 0x0200);
1747 tg3_writephy(tp, 0x16, 0x0082);
1748 if (tg3_wait_macro_done(tp)) {
1749 *resetp = 1;
1750 return -EBUSY;
1751 }
1752
1753 tg3_writephy(tp, 0x16, 0x0802);
1754 if (tg3_wait_macro_done(tp)) {
1755 *resetp = 1;
1756 return -EBUSY;
1757 }
1758
1759 for (i = 0; i < 6; i += 2) {
1760 u32 low, high;
1761
1762 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1763 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1764 tg3_wait_macro_done(tp)) {
1765 *resetp = 1;
1766 return -EBUSY;
1767 }
1768 low &= 0x7fff;
1769 high &= 0x000f;
1770 if (low != test_pat[chan][i] ||
1771 high != test_pat[chan][i+1]) {
1772 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1773 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1775
1776 return -EBUSY;
1777 }
1778 }
1779 }
1780
1781 return 0;
1782}
1783
1784static int tg3_phy_reset_chanpat(struct tg3 *tp)
1785{
1786 int chan;
1787
1788 for (chan = 0; chan < 4; chan++) {
1789 int i;
1790
1791 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1792 (chan * 0x2000) | 0x0200);
1793 tg3_writephy(tp, 0x16, 0x0002);
1794 for (i = 0; i < 6; i++)
1795 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1796 tg3_writephy(tp, 0x16, 0x0202);
1797 if (tg3_wait_macro_done(tp))
1798 return -EBUSY;
1799 }
1800
1801 return 0;
1802}
1803
1804static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1805{
1806 u32 reg32, phy9_orig;
1807 int retries, do_phy_reset, err;
1808
1809 retries = 10;
1810 do_phy_reset = 1;
1811 do {
1812 if (do_phy_reset) {
1813 err = tg3_bmcr_reset(tp);
1814 if (err)
1815 return err;
1816 do_phy_reset = 0;
1817 }
1818
1819 /* Disable transmitter and interrupt. */
1820 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1821 continue;
1822
1823 reg32 |= 0x3000;
1824 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1825
1826 /* Set full-duplex, 1000 mbps. */
1827 tg3_writephy(tp, MII_BMCR,
1828 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1829
1830 /* Set to master mode. */
1831 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1832 continue;
1833
1834 tg3_writephy(tp, MII_TG3_CTRL,
1835 (MII_TG3_CTRL_AS_MASTER |
1836 MII_TG3_CTRL_ENABLE_AS_MASTER));
1837
1838 /* Enable SM_DSP_CLOCK and 6dB. */
1839 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1840
1841 /* Block the PHY control access. */
1842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1844
1845 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1846 if (!err)
1847 break;
1848 } while (--retries);
1849
1850 err = tg3_phy_reset_chanpat(tp);
1851 if (err)
1852 return err;
1853
1854 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1855 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1856
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1858 tg3_writephy(tp, 0x16, 0x0000);
1859
1860 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1861 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1862 /* Set Extended packet length bit for jumbo frames */
1863 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1864 }
1865 else {
1866 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1867 }
1868
1869 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1870
1871 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1872 reg32 &= ~0x3000;
1873 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1874 } else if (!err)
1875 err = -EBUSY;
1876
1877 return err;
1878}
1879
1880/* This will reset the tigon3 PHY if there is no valid
1881 * link unless the FORCE argument is non-zero.
1882 */
1883static int tg3_phy_reset(struct tg3 *tp)
1884{
1885 u32 cpmuctrl;
1886 u32 phy_status;
1887 int err;
1888
1889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1890 u32 val;
1891
1892 val = tr32(GRC_MISC_CFG);
1893 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1894 udelay(40);
1895 }
1896 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1897 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1898 if (err != 0)
1899 return -EBUSY;
1900
1901 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1902 netif_carrier_off(tp->dev);
1903 tg3_link_report(tp);
1904 }
1905
1906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1907 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1909 err = tg3_phy_reset_5703_4_5(tp);
1910 if (err)
1911 return err;
1912 goto out;
1913 }
1914
1915 cpmuctrl = 0;
1916 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1917 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1918 cpmuctrl = tr32(TG3_CPMU_CTRL);
1919 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1920 tw32(TG3_CPMU_CTRL,
1921 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1922 }
1923
1924 err = tg3_bmcr_reset(tp);
1925 if (err)
1926 return err;
1927
1928 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1929 u32 phy;
1930
1931 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1932 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1933
1934 tw32(TG3_CPMU_CTRL, cpmuctrl);
1935 }
1936
1937 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1938 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1939 u32 val;
1940
1941 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1942 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1943 CPMU_LSPD_1000MB_MACCLK_12_5) {
1944 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1945 udelay(40);
1946 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1947 }
1948 }
1949
1950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1951 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1952 return 0;
1953
1954 tg3_phy_apply_otp(tp);
1955
1956 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1957 tg3_phy_toggle_apd(tp, true);
1958 else
1959 tg3_phy_toggle_apd(tp, false);
1960
1961out:
1962 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1963 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1964 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1965 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1966 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1967 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1968 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969 }
1970 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1971 tg3_writephy(tp, 0x1c, 0x8d68);
1972 tg3_writephy(tp, 0x1c, 0x8d68);
1973 }
1974 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1975 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1976 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1977 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1978 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1979 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1980 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1981 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1982 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1983 }
1984 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1985 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1986 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1987 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1988 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1989 tg3_writephy(tp, MII_TG3_TEST1,
1990 MII_TG3_TEST1_TRIM_EN | 0x4);
1991 } else
1992 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1993 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1994 }
1995 /* Set Extended packet length bit (bit 14) on all chips that */
1996 /* support jumbo frames */
1997 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1998 /* Cannot do read-modify-write on 5401 */
1999 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2000 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2001 u32 phy_reg;
2002
2003 /* Set bit 14 with read-modify-write to preserve other bits */
2004 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2005 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2006 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2007 }
2008
2009 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2010 * jumbo frames transmission.
2011 */
2012 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2013 u32 phy_reg;
2014
2015 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2016 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2017 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2018 }
2019
2020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2021 /* adjust output voltage */
2022 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2023 }
2024
2025 tg3_phy_toggle_automdix(tp, 1);
2026 tg3_phy_set_wirespeed(tp);
2027 return 0;
2028}
2029
2030static void tg3_frob_aux_power(struct tg3 *tp)
2031{
2032 struct tg3 *tp_peer = tp;
2033
2034 /* The GPIOs do something completely different on 57765. */
2035 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2037 return;
2038
2039 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2040 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2042 struct net_device *dev_peer;
2043
2044 dev_peer = pci_get_drvdata(tp->pdev_peer);
2045 /* remove_one() may have been run on the peer. */
2046 if (!dev_peer)
2047 tp_peer = tp;
2048 else
2049 tp_peer = netdev_priv(dev_peer);
2050 }
2051
2052 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2053 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2054 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2055 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2058 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2059 (GRC_LCLCTRL_GPIO_OE0 |
2060 GRC_LCLCTRL_GPIO_OE1 |
2061 GRC_LCLCTRL_GPIO_OE2 |
2062 GRC_LCLCTRL_GPIO_OUTPUT0 |
2063 GRC_LCLCTRL_GPIO_OUTPUT1),
2064 100);
2065 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2066 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2067 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2068 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2069 GRC_LCLCTRL_GPIO_OE1 |
2070 GRC_LCLCTRL_GPIO_OE2 |
2071 GRC_LCLCTRL_GPIO_OUTPUT0 |
2072 GRC_LCLCTRL_GPIO_OUTPUT1 |
2073 tp->grc_local_ctrl;
2074 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2075
2076 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2077 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2078
2079 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2080 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2081 } else {
2082 u32 no_gpio2;
2083 u32 grc_local_ctrl = 0;
2084
2085 if (tp_peer != tp &&
2086 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2087 return;
2088
2089 /* Workaround to prevent overdrawing Amps. */
2090 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2091 ASIC_REV_5714) {
2092 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094 grc_local_ctrl, 100);
2095 }
2096
2097 /* On 5753 and variants, GPIO2 cannot be used. */
2098 no_gpio2 = tp->nic_sram_data_cfg &
2099 NIC_SRAM_DATA_CFG_NO_GPIO2;
2100
2101 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2102 GRC_LCLCTRL_GPIO_OE1 |
2103 GRC_LCLCTRL_GPIO_OE2 |
2104 GRC_LCLCTRL_GPIO_OUTPUT1 |
2105 GRC_LCLCTRL_GPIO_OUTPUT2;
2106 if (no_gpio2) {
2107 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2108 GRC_LCLCTRL_GPIO_OUTPUT2);
2109 }
2110 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2111 grc_local_ctrl, 100);
2112
2113 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2114
2115 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2116 grc_local_ctrl, 100);
2117
2118 if (!no_gpio2) {
2119 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121 grc_local_ctrl, 100);
2122 }
2123 }
2124 } else {
2125 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2126 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2127 if (tp_peer != tp &&
2128 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2129 return;
2130
2131 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2132 (GRC_LCLCTRL_GPIO_OE1 |
2133 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2134
2135 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2136 GRC_LCLCTRL_GPIO_OE1, 100);
2137
2138 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2139 (GRC_LCLCTRL_GPIO_OE1 |
2140 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2141 }
2142 }
2143}
2144
2145static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2146{
2147 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2148 return 1;
2149 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2150 if (speed != SPEED_10)
2151 return 1;
2152 } else if (speed == SPEED_10)
2153 return 1;
2154
2155 return 0;
2156}
2157
2158static int tg3_setup_phy(struct tg3 *, int);
2159
2160#define RESET_KIND_SHUTDOWN 0
2161#define RESET_KIND_INIT 1
2162#define RESET_KIND_SUSPEND 2
2163
2164static void tg3_write_sig_post_reset(struct tg3 *, int);
2165static int tg3_halt_cpu(struct tg3 *, u32);
2166
2167static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2168{
2169 u32 val;
2170
2171 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2173 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2174 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2175
2176 sg_dig_ctrl |=
2177 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2178 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2179 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2180 }
2181 return;
2182 }
2183
2184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2185 tg3_bmcr_reset(tp);
2186 val = tr32(GRC_MISC_CFG);
2187 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2188 udelay(40);
2189 return;
2190 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2191 u32 phytest;
2192 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2193 u32 phy;
2194
2195 tg3_writephy(tp, MII_ADVERTISE, 0);
2196 tg3_writephy(tp, MII_BMCR,
2197 BMCR_ANENABLE | BMCR_ANRESTART);
2198
2199 tg3_writephy(tp, MII_TG3_FET_TEST,
2200 phytest | MII_TG3_FET_SHADOW_EN);
2201 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2202 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2203 tg3_writephy(tp,
2204 MII_TG3_FET_SHDW_AUXMODE4,
2205 phy);
2206 }
2207 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2208 }
2209 return;
2210 } else if (do_low_power) {
2211 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2212 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2213
2214 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2215 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2216 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2217 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2218 MII_TG3_AUXCTL_PCTL_VREG_11V);
2219 }
2220
2221 /* The PHY should not be powered down on some chips because
2222 * of bugs.
2223 */
2224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2226 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2227 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2228 return;
2229
2230 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2231 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2232 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2233 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2234 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2235 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2236 }
2237
2238 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2239}
2240
2241/* tp->lock is held. */
2242static int tg3_nvram_lock(struct tg3 *tp)
2243{
2244 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2245 int i;
2246
2247 if (tp->nvram_lock_cnt == 0) {
2248 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2249 for (i = 0; i < 8000; i++) {
2250 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2251 break;
2252 udelay(20);
2253 }
2254 if (i == 8000) {
2255 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2256 return -ENODEV;
2257 }
2258 }
2259 tp->nvram_lock_cnt++;
2260 }
2261 return 0;
2262}
2263
2264/* tp->lock is held. */
2265static void tg3_nvram_unlock(struct tg3 *tp)
2266{
2267 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2268 if (tp->nvram_lock_cnt > 0)
2269 tp->nvram_lock_cnt--;
2270 if (tp->nvram_lock_cnt == 0)
2271 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2272 }
2273}
2274
2275/* tp->lock is held. */
2276static void tg3_enable_nvram_access(struct tg3 *tp)
2277{
2278 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2279 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2280 u32 nvaccess = tr32(NVRAM_ACCESS);
2281
2282 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2283 }
2284}
2285
2286/* tp->lock is held. */
2287static void tg3_disable_nvram_access(struct tg3 *tp)
2288{
2289 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2290 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2291 u32 nvaccess = tr32(NVRAM_ACCESS);
2292
2293 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2294 }
2295}
2296
2297static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2298 u32 offset, u32 *val)
2299{
2300 u32 tmp;
2301 int i;
2302
2303 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2304 return -EINVAL;
2305
2306 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2307 EEPROM_ADDR_DEVID_MASK |
2308 EEPROM_ADDR_READ);
2309 tw32(GRC_EEPROM_ADDR,
2310 tmp |
2311 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2312 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2313 EEPROM_ADDR_ADDR_MASK) |
2314 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2315
2316 for (i = 0; i < 1000; i++) {
2317 tmp = tr32(GRC_EEPROM_ADDR);
2318
2319 if (tmp & EEPROM_ADDR_COMPLETE)
2320 break;
2321 msleep(1);
2322 }
2323 if (!(tmp & EEPROM_ADDR_COMPLETE))
2324 return -EBUSY;
2325
2326 tmp = tr32(GRC_EEPROM_DATA);
2327
2328 /*
2329 * The data will always be opposite the native endian
2330 * format. Perform a blind byteswap to compensate.
2331 */
2332 *val = swab32(tmp);
2333
2334 return 0;
2335}
2336
2337#define NVRAM_CMD_TIMEOUT 10000
2338
2339static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2340{
2341 int i;
2342
2343 tw32(NVRAM_CMD, nvram_cmd);
2344 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2345 udelay(10);
2346 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2347 udelay(10);
2348 break;
2349 }
2350 }
2351
2352 if (i == NVRAM_CMD_TIMEOUT)
2353 return -EBUSY;
2354
2355 return 0;
2356}
2357
2358static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2359{
2360 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2361 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2362 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2363 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2364 (tp->nvram_jedecnum == JEDEC_ATMEL))
2365
2366 addr = ((addr / tp->nvram_pagesize) <<
2367 ATMEL_AT45DB0X1B_PAGE_POS) +
2368 (addr % tp->nvram_pagesize);
2369
2370 return addr;
2371}
2372
2373static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2374{
2375 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2376 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2377 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2378 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2379 (tp->nvram_jedecnum == JEDEC_ATMEL))
2380
2381 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2382 tp->nvram_pagesize) +
2383 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2384
2385 return addr;
2386}
2387
2388/* NOTE: Data read in from NVRAM is byteswapped according to
2389 * the byteswapping settings for all other register accesses.
2390 * tg3 devices are BE devices, so on a BE machine, the data
2391 * returned will be exactly as it is seen in NVRAM. On a LE
2392 * machine, the 32-bit value will be byteswapped.
2393 */
2394static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2395{
2396 int ret;
2397
2398 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2399 return tg3_nvram_read_using_eeprom(tp, offset, val);
2400
2401 offset = tg3_nvram_phys_addr(tp, offset);
2402
2403 if (offset > NVRAM_ADDR_MSK)
2404 return -EINVAL;
2405
2406 ret = tg3_nvram_lock(tp);
2407 if (ret)
2408 return ret;
2409
2410 tg3_enable_nvram_access(tp);
2411
2412 tw32(NVRAM_ADDR, offset);
2413 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2414 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2415
2416 if (ret == 0)
2417 *val = tr32(NVRAM_RDDATA);
2418
2419 tg3_disable_nvram_access(tp);
2420
2421 tg3_nvram_unlock(tp);
2422
2423 return ret;
2424}
2425
2426/* Ensures NVRAM data is in bytestream format. */
2427static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2428{
2429 u32 v;
2430 int res = tg3_nvram_read(tp, offset, &v);
2431 if (!res)
2432 *val = cpu_to_be32(v);
2433 return res;
2434}
2435
2436/* tp->lock is held. */
2437static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2438{
2439 u32 addr_high, addr_low;
2440 int i;
2441
2442 addr_high = ((tp->dev->dev_addr[0] << 8) |
2443 tp->dev->dev_addr[1]);
2444 addr_low = ((tp->dev->dev_addr[2] << 24) |
2445 (tp->dev->dev_addr[3] << 16) |
2446 (tp->dev->dev_addr[4] << 8) |
2447 (tp->dev->dev_addr[5] << 0));
2448 for (i = 0; i < 4; i++) {
2449 if (i == 1 && skip_mac_1)
2450 continue;
2451 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2452 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2453 }
2454
2455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2456 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2457 for (i = 0; i < 12; i++) {
2458 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2459 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2460 }
2461 }
2462
2463 addr_high = (tp->dev->dev_addr[0] +
2464 tp->dev->dev_addr[1] +
2465 tp->dev->dev_addr[2] +
2466 tp->dev->dev_addr[3] +
2467 tp->dev->dev_addr[4] +
2468 tp->dev->dev_addr[5]) &
2469 TX_BACKOFF_SEED_MASK;
2470 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2471}
2472
2473static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2474{
2475 u32 misc_host_ctrl;
2476 bool device_should_wake, do_low_power;
2477
2478 /* Make sure register accesses (indirect or otherwise)
2479 * will function correctly.
2480 */
2481 pci_write_config_dword(tp->pdev,
2482 TG3PCI_MISC_HOST_CTRL,
2483 tp->misc_host_ctrl);
2484
2485 switch (state) {
2486 case PCI_D0:
2487 pci_enable_wake(tp->pdev, state, false);
2488 pci_set_power_state(tp->pdev, PCI_D0);
2489
2490 /* Switch out of Vaux if it is a NIC */
2491 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2492 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2493
2494 return 0;
2495
2496 case PCI_D1:
2497 case PCI_D2:
2498 case PCI_D3hot:
2499 break;
2500
2501 default:
2502 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2503 tp->dev->name, state);
2504 return -EINVAL;
2505 }
2506
2507 /* Restore the CLKREQ setting. */
2508 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2509 u16 lnkctl;
2510
2511 pci_read_config_word(tp->pdev,
2512 tp->pcie_cap + PCI_EXP_LNKCTL,
2513 &lnkctl);
2514 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2515 pci_write_config_word(tp->pdev,
2516 tp->pcie_cap + PCI_EXP_LNKCTL,
2517 lnkctl);
2518 }
2519
2520 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2521 tw32(TG3PCI_MISC_HOST_CTRL,
2522 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2523
2524 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2525 device_may_wakeup(&tp->pdev->dev) &&
2526 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2527
2528 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2529 do_low_power = false;
2530 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2531 !tp->link_config.phy_is_low_power) {
2532 struct phy_device *phydev;
2533 u32 phyid, advertising;
2534
2535 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2536
2537 tp->link_config.phy_is_low_power = 1;
2538
2539 tp->link_config.orig_speed = phydev->speed;
2540 tp->link_config.orig_duplex = phydev->duplex;
2541 tp->link_config.orig_autoneg = phydev->autoneg;
2542 tp->link_config.orig_advertising = phydev->advertising;
2543
2544 advertising = ADVERTISED_TP |
2545 ADVERTISED_Pause |
2546 ADVERTISED_Autoneg |
2547 ADVERTISED_10baseT_Half;
2548
2549 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2550 device_should_wake) {
2551 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2552 advertising |=
2553 ADVERTISED_100baseT_Half |
2554 ADVERTISED_100baseT_Full |
2555 ADVERTISED_10baseT_Full;
2556 else
2557 advertising |= ADVERTISED_10baseT_Full;
2558 }
2559
2560 phydev->advertising = advertising;
2561
2562 phy_start_aneg(phydev);
2563
2564 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2565 if (phyid != TG3_PHY_ID_BCMAC131) {
2566 phyid &= TG3_PHY_OUI_MASK;
2567 if (phyid == TG3_PHY_OUI_1 ||
2568 phyid == TG3_PHY_OUI_2 ||
2569 phyid == TG3_PHY_OUI_3)
2570 do_low_power = true;
2571 }
2572 }
2573 } else {
2574 do_low_power = true;
2575
2576 if (tp->link_config.phy_is_low_power == 0) {
2577 tp->link_config.phy_is_low_power = 1;
2578 tp->link_config.orig_speed = tp->link_config.speed;
2579 tp->link_config.orig_duplex = tp->link_config.duplex;
2580 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2581 }
2582
2583 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2584 tp->link_config.speed = SPEED_10;
2585 tp->link_config.duplex = DUPLEX_HALF;
2586 tp->link_config.autoneg = AUTONEG_ENABLE;
2587 tg3_setup_phy(tp, 0);
2588 }
2589 }
2590
2591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2592 u32 val;
2593
2594 val = tr32(GRC_VCPU_EXT_CTRL);
2595 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2596 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2597 int i;
2598 u32 val;
2599
2600 for (i = 0; i < 200; i++) {
2601 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2602 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2603 break;
2604 msleep(1);
2605 }
2606 }
2607 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2608 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2609 WOL_DRV_STATE_SHUTDOWN |
2610 WOL_DRV_WOL |
2611 WOL_SET_MAGIC_PKT);
2612
2613 if (device_should_wake) {
2614 u32 mac_mode;
2615
2616 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2617 if (do_low_power) {
2618 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2619 udelay(40);
2620 }
2621
2622 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2623 mac_mode = MAC_MODE_PORT_MODE_GMII;
2624 else
2625 mac_mode = MAC_MODE_PORT_MODE_MII;
2626
2627 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2628 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2629 ASIC_REV_5700) {
2630 u32 speed = (tp->tg3_flags &
2631 TG3_FLAG_WOL_SPEED_100MB) ?
2632 SPEED_100 : SPEED_10;
2633 if (tg3_5700_link_polarity(tp, speed))
2634 mac_mode |= MAC_MODE_LINK_POLARITY;
2635 else
2636 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2637 }
2638 } else {
2639 mac_mode = MAC_MODE_PORT_MODE_TBI;
2640 }
2641
2642 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2643 tw32(MAC_LED_CTRL, tp->led_ctrl);
2644
2645 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2646 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2647 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2648 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2649 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2650 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2651
2652 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2653 mac_mode |= tp->mac_mode &
2654 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2655 if (mac_mode & MAC_MODE_APE_TX_EN)
2656 mac_mode |= MAC_MODE_TDE_ENABLE;
2657 }
2658
2659 tw32_f(MAC_MODE, mac_mode);
2660 udelay(100);
2661
2662 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2663 udelay(10);
2664 }
2665
2666 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2667 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2669 u32 base_val;
2670
2671 base_val = tp->pci_clock_ctrl;
2672 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2673 CLOCK_CTRL_TXCLK_DISABLE);
2674
2675 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2676 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2677 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2678 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2679 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2680 /* do nothing */
2681 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2682 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2683 u32 newbits1, newbits2;
2684
2685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2686 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2687 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2688 CLOCK_CTRL_TXCLK_DISABLE |
2689 CLOCK_CTRL_ALTCLK);
2690 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2691 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2692 newbits1 = CLOCK_CTRL_625_CORE;
2693 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2694 } else {
2695 newbits1 = CLOCK_CTRL_ALTCLK;
2696 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2697 }
2698
2699 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2700 40);
2701
2702 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2703 40);
2704
2705 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2706 u32 newbits3;
2707
2708 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2709 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2710 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2711 CLOCK_CTRL_TXCLK_DISABLE |
2712 CLOCK_CTRL_44MHZ_CORE);
2713 } else {
2714 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2715 }
2716
2717 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2718 tp->pci_clock_ctrl | newbits3, 40);
2719 }
2720 }
2721
2722 if (!(device_should_wake) &&
2723 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2724 tg3_power_down_phy(tp, do_low_power);
2725
2726 tg3_frob_aux_power(tp);
2727
2728 /* Workaround for unstable PLL clock */
2729 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2730 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2731 u32 val = tr32(0x7d00);
2732
2733 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2734 tw32(0x7d00, val);
2735 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2736 int err;
2737
2738 err = tg3_nvram_lock(tp);
2739 tg3_halt_cpu(tp, RX_CPU_BASE);
2740 if (!err)
2741 tg3_nvram_unlock(tp);
2742 }
2743 }
2744
2745 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2746
2747 if (device_should_wake)
2748 pci_enable_wake(tp->pdev, state, true);
2749
2750 /* Finally, set the new power state. */
2751 pci_set_power_state(tp->pdev, state);
2752
2753 return 0;
2754}
2755
2756static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2757{
2758 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2759 case MII_TG3_AUX_STAT_10HALF:
2760 *speed = SPEED_10;
2761 *duplex = DUPLEX_HALF;
2762 break;
2763
2764 case MII_TG3_AUX_STAT_10FULL:
2765 *speed = SPEED_10;
2766 *duplex = DUPLEX_FULL;
2767 break;
2768
2769 case MII_TG3_AUX_STAT_100HALF:
2770 *speed = SPEED_100;
2771 *duplex = DUPLEX_HALF;
2772 break;
2773
2774 case MII_TG3_AUX_STAT_100FULL:
2775 *speed = SPEED_100;
2776 *duplex = DUPLEX_FULL;
2777 break;
2778
2779 case MII_TG3_AUX_STAT_1000HALF:
2780 *speed = SPEED_1000;
2781 *duplex = DUPLEX_HALF;
2782 break;
2783
2784 case MII_TG3_AUX_STAT_1000FULL:
2785 *speed = SPEED_1000;
2786 *duplex = DUPLEX_FULL;
2787 break;
2788
2789 default:
2790 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2791 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2792 SPEED_10;
2793 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2794 DUPLEX_HALF;
2795 break;
2796 }
2797 *speed = SPEED_INVALID;
2798 *duplex = DUPLEX_INVALID;
2799 break;
2800 }
2801}
2802
2803static void tg3_phy_copper_begin(struct tg3 *tp)
2804{
2805 u32 new_adv;
2806 int i;
2807
2808 if (tp->link_config.phy_is_low_power) {
2809 /* Entering low power mode. Disable gigabit and
2810 * 100baseT advertisements.
2811 */
2812 tg3_writephy(tp, MII_TG3_CTRL, 0);
2813
2814 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2815 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2816 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2817 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2818
2819 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2820 } else if (tp->link_config.speed == SPEED_INVALID) {
2821 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2822 tp->link_config.advertising &=
2823 ~(ADVERTISED_1000baseT_Half |
2824 ADVERTISED_1000baseT_Full);
2825
2826 new_adv = ADVERTISE_CSMA;
2827 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2828 new_adv |= ADVERTISE_10HALF;
2829 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2830 new_adv |= ADVERTISE_10FULL;
2831 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2832 new_adv |= ADVERTISE_100HALF;
2833 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2834 new_adv |= ADVERTISE_100FULL;
2835
2836 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2837
2838 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2839
2840 if (tp->link_config.advertising &
2841 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2842 new_adv = 0;
2843 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2844 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2845 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2846 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2847 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2848 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2849 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2850 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2851 MII_TG3_CTRL_ENABLE_AS_MASTER);
2852 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2853 } else {
2854 tg3_writephy(tp, MII_TG3_CTRL, 0);
2855 }
2856 } else {
2857 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2858 new_adv |= ADVERTISE_CSMA;
2859
2860 /* Asking for a specific link mode. */
2861 if (tp->link_config.speed == SPEED_1000) {
2862 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2863
2864 if (tp->link_config.duplex == DUPLEX_FULL)
2865 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2866 else
2867 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2868 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2869 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2870 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2871 MII_TG3_CTRL_ENABLE_AS_MASTER);
2872 } else {
2873 if (tp->link_config.speed == SPEED_100) {
2874 if (tp->link_config.duplex == DUPLEX_FULL)
2875 new_adv |= ADVERTISE_100FULL;
2876 else
2877 new_adv |= ADVERTISE_100HALF;
2878 } else {
2879 if (tp->link_config.duplex == DUPLEX_FULL)
2880 new_adv |= ADVERTISE_10FULL;
2881 else
2882 new_adv |= ADVERTISE_10HALF;
2883 }
2884 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2885
2886 new_adv = 0;
2887 }
2888
2889 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2890 }
2891
2892 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2893 tp->link_config.speed != SPEED_INVALID) {
2894 u32 bmcr, orig_bmcr;
2895
2896 tp->link_config.active_speed = tp->link_config.speed;
2897 tp->link_config.active_duplex = tp->link_config.duplex;
2898
2899 bmcr = 0;
2900 switch (tp->link_config.speed) {
2901 default:
2902 case SPEED_10:
2903 break;
2904
2905 case SPEED_100:
2906 bmcr |= BMCR_SPEED100;
2907 break;
2908
2909 case SPEED_1000:
2910 bmcr |= TG3_BMCR_SPEED1000;
2911 break;
2912 }
2913
2914 if (tp->link_config.duplex == DUPLEX_FULL)
2915 bmcr |= BMCR_FULLDPLX;
2916
2917 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2918 (bmcr != orig_bmcr)) {
2919 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2920 for (i = 0; i < 1500; i++) {
2921 u32 tmp;
2922
2923 udelay(10);
2924 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2925 tg3_readphy(tp, MII_BMSR, &tmp))
2926 continue;
2927 if (!(tmp & BMSR_LSTATUS)) {
2928 udelay(40);
2929 break;
2930 }
2931 }
2932 tg3_writephy(tp, MII_BMCR, bmcr);
2933 udelay(40);
2934 }
2935 } else {
2936 tg3_writephy(tp, MII_BMCR,
2937 BMCR_ANENABLE | BMCR_ANRESTART);
2938 }
2939}
2940
2941static int tg3_init_5401phy_dsp(struct tg3 *tp)
2942{
2943 int err;
2944
2945 /* Turn off tap power management. */
2946 /* Set Extended packet length bit */
2947 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2948
2949 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2950 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2951
2952 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2953 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2954
2955 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2956 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2957
2958 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2959 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2960
2961 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2962 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2963
2964 udelay(40);
2965
2966 return err;
2967}
2968
2969static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2970{
2971 u32 adv_reg, all_mask = 0;
2972
2973 if (mask & ADVERTISED_10baseT_Half)
2974 all_mask |= ADVERTISE_10HALF;
2975 if (mask & ADVERTISED_10baseT_Full)
2976 all_mask |= ADVERTISE_10FULL;
2977 if (mask & ADVERTISED_100baseT_Half)
2978 all_mask |= ADVERTISE_100HALF;
2979 if (mask & ADVERTISED_100baseT_Full)
2980 all_mask |= ADVERTISE_100FULL;
2981
2982 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2983 return 0;
2984
2985 if ((adv_reg & all_mask) != all_mask)
2986 return 0;
2987 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2988 u32 tg3_ctrl;
2989
2990 all_mask = 0;
2991 if (mask & ADVERTISED_1000baseT_Half)
2992 all_mask |= ADVERTISE_1000HALF;
2993 if (mask & ADVERTISED_1000baseT_Full)
2994 all_mask |= ADVERTISE_1000FULL;
2995
2996 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2997 return 0;
2998
2999 if ((tg3_ctrl & all_mask) != all_mask)
3000 return 0;
3001 }
3002 return 1;
3003}
3004
3005static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3006{
3007 u32 curadv, reqadv;
3008
3009 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3010 return 1;
3011
3012 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3013 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3014
3015 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3016 if (curadv != reqadv)
3017 return 0;
3018
3019 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3020 tg3_readphy(tp, MII_LPA, rmtadv);
3021 } else {
3022 /* Reprogram the advertisement register, even if it
3023 * does not affect the current link. If the link
3024 * gets renegotiated in the future, we can save an
3025 * additional renegotiation cycle by advertising
3026 * it correctly in the first place.
3027 */
3028 if (curadv != reqadv) {
3029 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3030 ADVERTISE_PAUSE_ASYM);
3031 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3032 }
3033 }
3034
3035 return 1;
3036}
3037
3038static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3039{
3040 int current_link_up;
3041 u32 bmsr, dummy;
3042 u32 lcl_adv, rmt_adv;
3043 u16 current_speed;
3044 u8 current_duplex;
3045 int i, err;
3046
3047 tw32(MAC_EVENT, 0);
3048
3049 tw32_f(MAC_STATUS,
3050 (MAC_STATUS_SYNC_CHANGED |
3051 MAC_STATUS_CFG_CHANGED |
3052 MAC_STATUS_MI_COMPLETION |
3053 MAC_STATUS_LNKSTATE_CHANGED));
3054 udelay(40);
3055
3056 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3057 tw32_f(MAC_MI_MODE,
3058 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3059 udelay(80);
3060 }
3061
3062 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3063
3064 /* Some third-party PHYs need to be reset on link going
3065 * down.
3066 */
3067 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3068 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3070 netif_carrier_ok(tp->dev)) {
3071 tg3_readphy(tp, MII_BMSR, &bmsr);
3072 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3073 !(bmsr & BMSR_LSTATUS))
3074 force_reset = 1;
3075 }
3076 if (force_reset)
3077 tg3_phy_reset(tp);
3078
3079 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3080 tg3_readphy(tp, MII_BMSR, &bmsr);
3081 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3082 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3083 bmsr = 0;
3084
3085 if (!(bmsr & BMSR_LSTATUS)) {
3086 err = tg3_init_5401phy_dsp(tp);
3087 if (err)
3088 return err;
3089
3090 tg3_readphy(tp, MII_BMSR, &bmsr);
3091 for (i = 0; i < 1000; i++) {
3092 udelay(10);
3093 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3094 (bmsr & BMSR_LSTATUS)) {
3095 udelay(40);
3096 break;
3097 }
3098 }
3099
3100 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3101 !(bmsr & BMSR_LSTATUS) &&
3102 tp->link_config.active_speed == SPEED_1000) {
3103 err = tg3_phy_reset(tp);
3104 if (!err)
3105 err = tg3_init_5401phy_dsp(tp);
3106 if (err)
3107 return err;
3108 }
3109 }
3110 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3111 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3112 /* 5701 {A0,B0} CRC bug workaround */
3113 tg3_writephy(tp, 0x15, 0x0a75);
3114 tg3_writephy(tp, 0x1c, 0x8c68);
3115 tg3_writephy(tp, 0x1c, 0x8d68);
3116 tg3_writephy(tp, 0x1c, 0x8c68);
3117 }
3118
3119 /* Clear pending interrupts... */
3120 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3121 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3122
3123 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3124 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3125 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3126 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3127
3128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3129 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3130 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3131 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3132 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3133 else
3134 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3135 }
3136
3137 current_link_up = 0;
3138 current_speed = SPEED_INVALID;
3139 current_duplex = DUPLEX_INVALID;
3140
3141 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3142 u32 val;
3143
3144 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3145 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3146 if (!(val & (1 << 10))) {
3147 val |= (1 << 10);
3148 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3149 goto relink;
3150 }
3151 }
3152
3153 bmsr = 0;
3154 for (i = 0; i < 100; i++) {
3155 tg3_readphy(tp, MII_BMSR, &bmsr);
3156 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3157 (bmsr & BMSR_LSTATUS))
3158 break;
3159 udelay(40);
3160 }
3161
3162 if (bmsr & BMSR_LSTATUS) {
3163 u32 aux_stat, bmcr;
3164
3165 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3166 for (i = 0; i < 2000; i++) {
3167 udelay(10);
3168 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3169 aux_stat)
3170 break;
3171 }
3172
3173 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3174 &current_speed,
3175 &current_duplex);
3176
3177 bmcr = 0;
3178 for (i = 0; i < 200; i++) {
3179 tg3_readphy(tp, MII_BMCR, &bmcr);
3180 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3181 continue;
3182 if (bmcr && bmcr != 0x7fff)
3183 break;
3184 udelay(10);
3185 }
3186
3187 lcl_adv = 0;
3188 rmt_adv = 0;
3189
3190 tp->link_config.active_speed = current_speed;
3191 tp->link_config.active_duplex = current_duplex;
3192
3193 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3194 if ((bmcr & BMCR_ANENABLE) &&
3195 tg3_copper_is_advertising_all(tp,
3196 tp->link_config.advertising)) {
3197 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3198 &rmt_adv))
3199 current_link_up = 1;
3200 }
3201 } else {
3202 if (!(bmcr & BMCR_ANENABLE) &&
3203 tp->link_config.speed == current_speed &&
3204 tp->link_config.duplex == current_duplex &&
3205 tp->link_config.flowctrl ==
3206 tp->link_config.active_flowctrl) {
3207 current_link_up = 1;
3208 }
3209 }
3210
3211 if (current_link_up == 1 &&
3212 tp->link_config.active_duplex == DUPLEX_FULL)
3213 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3214 }
3215
3216relink:
3217 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3218 u32 tmp;
3219
3220 tg3_phy_copper_begin(tp);
3221
3222 tg3_readphy(tp, MII_BMSR, &tmp);
3223 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3224 (tmp & BMSR_LSTATUS))
3225 current_link_up = 1;
3226 }
3227
3228 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3229 if (current_link_up == 1) {
3230 if (tp->link_config.active_speed == SPEED_100 ||
3231 tp->link_config.active_speed == SPEED_10)
3232 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3233 else
3234 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3235 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3236 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3237 else
3238 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3239
3240 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3241 if (tp->link_config.active_duplex == DUPLEX_HALF)
3242 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3243
3244 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3245 if (current_link_up == 1 &&
3246 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3247 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3248 else
3249 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3250 }
3251
3252 /* ??? Without this setting Netgear GA302T PHY does not
3253 * ??? send/receive packets...
3254 */
3255 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3256 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3257 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3258 tw32_f(MAC_MI_MODE, tp->mi_mode);
3259 udelay(80);
3260 }
3261
3262 tw32_f(MAC_MODE, tp->mac_mode);
3263 udelay(40);
3264
3265 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3266 /* Polled via timer. */
3267 tw32_f(MAC_EVENT, 0);
3268 } else {
3269 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3270 }
3271 udelay(40);
3272
3273 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3274 current_link_up == 1 &&
3275 tp->link_config.active_speed == SPEED_1000 &&
3276 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3277 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3278 udelay(120);
3279 tw32_f(MAC_STATUS,
3280 (MAC_STATUS_SYNC_CHANGED |
3281 MAC_STATUS_CFG_CHANGED));
3282 udelay(40);
3283 tg3_write_mem(tp,
3284 NIC_SRAM_FIRMWARE_MBOX,
3285 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3286 }
3287
3288 /* Prevent send BD corruption. */
3289 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3290 u16 oldlnkctl, newlnkctl;
3291
3292 pci_read_config_word(tp->pdev,
3293 tp->pcie_cap + PCI_EXP_LNKCTL,
3294 &oldlnkctl);
3295 if (tp->link_config.active_speed == SPEED_100 ||
3296 tp->link_config.active_speed == SPEED_10)
3297 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3298 else
3299 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3300 if (newlnkctl != oldlnkctl)
3301 pci_write_config_word(tp->pdev,
3302 tp->pcie_cap + PCI_EXP_LNKCTL,
3303 newlnkctl);
3304 }
3305
3306 if (current_link_up != netif_carrier_ok(tp->dev)) {
3307 if (current_link_up)
3308 netif_carrier_on(tp->dev);
3309 else
3310 netif_carrier_off(tp->dev);
3311 tg3_link_report(tp);
3312 }
3313
3314 return 0;
3315}
3316
3317struct tg3_fiber_aneginfo {
3318 int state;
3319#define ANEG_STATE_UNKNOWN 0
3320#define ANEG_STATE_AN_ENABLE 1
3321#define ANEG_STATE_RESTART_INIT 2
3322#define ANEG_STATE_RESTART 3
3323#define ANEG_STATE_DISABLE_LINK_OK 4
3324#define ANEG_STATE_ABILITY_DETECT_INIT 5
3325#define ANEG_STATE_ABILITY_DETECT 6
3326#define ANEG_STATE_ACK_DETECT_INIT 7
3327#define ANEG_STATE_ACK_DETECT 8
3328#define ANEG_STATE_COMPLETE_ACK_INIT 9
3329#define ANEG_STATE_COMPLETE_ACK 10
3330#define ANEG_STATE_IDLE_DETECT_INIT 11
3331#define ANEG_STATE_IDLE_DETECT 12
3332#define ANEG_STATE_LINK_OK 13
3333#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3334#define ANEG_STATE_NEXT_PAGE_WAIT 15
3335
3336 u32 flags;
3337#define MR_AN_ENABLE 0x00000001
3338#define MR_RESTART_AN 0x00000002
3339#define MR_AN_COMPLETE 0x00000004
3340#define MR_PAGE_RX 0x00000008
3341#define MR_NP_LOADED 0x00000010
3342#define MR_TOGGLE_TX 0x00000020
3343#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3344#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3345#define MR_LP_ADV_SYM_PAUSE 0x00000100
3346#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3347#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3348#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3349#define MR_LP_ADV_NEXT_PAGE 0x00001000
3350#define MR_TOGGLE_RX 0x00002000
3351#define MR_NP_RX 0x00004000
3352
3353#define MR_LINK_OK 0x80000000
3354
3355 unsigned long link_time, cur_time;
3356
3357 u32 ability_match_cfg;
3358 int ability_match_count;
3359
3360 char ability_match, idle_match, ack_match;
3361
3362 u32 txconfig, rxconfig;
3363#define ANEG_CFG_NP 0x00000080
3364#define ANEG_CFG_ACK 0x00000040
3365#define ANEG_CFG_RF2 0x00000020
3366#define ANEG_CFG_RF1 0x00000010
3367#define ANEG_CFG_PS2 0x00000001
3368#define ANEG_CFG_PS1 0x00008000
3369#define ANEG_CFG_HD 0x00004000
3370#define ANEG_CFG_FD 0x00002000
3371#define ANEG_CFG_INVAL 0x00001f06
3372
3373};
3374#define ANEG_OK 0
3375#define ANEG_DONE 1
3376#define ANEG_TIMER_ENAB 2
3377#define ANEG_FAILED -1
3378
3379#define ANEG_STATE_SETTLE_TIME 10000
3380
3381static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3382 struct tg3_fiber_aneginfo *ap)
3383{
3384 u16 flowctrl;
3385 unsigned long delta;
3386 u32 rx_cfg_reg;
3387 int ret;
3388
3389 if (ap->state == ANEG_STATE_UNKNOWN) {
3390 ap->rxconfig = 0;
3391 ap->link_time = 0;
3392 ap->cur_time = 0;
3393 ap->ability_match_cfg = 0;
3394 ap->ability_match_count = 0;
3395 ap->ability_match = 0;
3396 ap->idle_match = 0;
3397 ap->ack_match = 0;
3398 }
3399 ap->cur_time++;
3400
3401 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3402 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3403
3404 if (rx_cfg_reg != ap->ability_match_cfg) {
3405 ap->ability_match_cfg = rx_cfg_reg;
3406 ap->ability_match = 0;
3407 ap->ability_match_count = 0;
3408 } else {
3409 if (++ap->ability_match_count > 1) {
3410 ap->ability_match = 1;
3411 ap->ability_match_cfg = rx_cfg_reg;
3412 }
3413 }
3414 if (rx_cfg_reg & ANEG_CFG_ACK)
3415 ap->ack_match = 1;
3416 else
3417 ap->ack_match = 0;
3418
3419 ap->idle_match = 0;
3420 } else {
3421 ap->idle_match = 1;
3422 ap->ability_match_cfg = 0;
3423 ap->ability_match_count = 0;
3424 ap->ability_match = 0;
3425 ap->ack_match = 0;
3426
3427 rx_cfg_reg = 0;
3428 }
3429
3430 ap->rxconfig = rx_cfg_reg;
3431 ret = ANEG_OK;
3432
3433 switch(ap->state) {
3434 case ANEG_STATE_UNKNOWN:
3435 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3436 ap->state = ANEG_STATE_AN_ENABLE;
3437
3438 /* fallthru */
3439 case ANEG_STATE_AN_ENABLE:
3440 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3441 if (ap->flags & MR_AN_ENABLE) {
3442 ap->link_time = 0;
3443 ap->cur_time = 0;
3444 ap->ability_match_cfg = 0;
3445 ap->ability_match_count = 0;
3446 ap->ability_match = 0;
3447 ap->idle_match = 0;
3448 ap->ack_match = 0;
3449
3450 ap->state = ANEG_STATE_RESTART_INIT;
3451 } else {
3452 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3453 }
3454 break;
3455
3456 case ANEG_STATE_RESTART_INIT:
3457 ap->link_time = ap->cur_time;
3458 ap->flags &= ~(MR_NP_LOADED);
3459 ap->txconfig = 0;
3460 tw32(MAC_TX_AUTO_NEG, 0);
3461 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3462 tw32_f(MAC_MODE, tp->mac_mode);
3463 udelay(40);
3464
3465 ret = ANEG_TIMER_ENAB;
3466 ap->state = ANEG_STATE_RESTART;
3467
3468 /* fallthru */
3469 case ANEG_STATE_RESTART:
3470 delta = ap->cur_time - ap->link_time;
3471 if (delta > ANEG_STATE_SETTLE_TIME) {
3472 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3473 } else {
3474 ret = ANEG_TIMER_ENAB;
3475 }
3476 break;
3477
3478 case ANEG_STATE_DISABLE_LINK_OK:
3479 ret = ANEG_DONE;
3480 break;
3481
3482 case ANEG_STATE_ABILITY_DETECT_INIT:
3483 ap->flags &= ~(MR_TOGGLE_TX);
3484 ap->txconfig = ANEG_CFG_FD;
3485 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3486 if (flowctrl & ADVERTISE_1000XPAUSE)
3487 ap->txconfig |= ANEG_CFG_PS1;
3488 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3489 ap->txconfig |= ANEG_CFG_PS2;
3490 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3491 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3492 tw32_f(MAC_MODE, tp->mac_mode);
3493 udelay(40);
3494
3495 ap->state = ANEG_STATE_ABILITY_DETECT;
3496 break;
3497
3498 case ANEG_STATE_ABILITY_DETECT:
3499 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3500 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3501 }
3502 break;
3503
3504 case ANEG_STATE_ACK_DETECT_INIT:
3505 ap->txconfig |= ANEG_CFG_ACK;
3506 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3507 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3508 tw32_f(MAC_MODE, tp->mac_mode);
3509 udelay(40);
3510
3511 ap->state = ANEG_STATE_ACK_DETECT;
3512
3513 /* fallthru */
3514 case ANEG_STATE_ACK_DETECT:
3515 if (ap->ack_match != 0) {
3516 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3517 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3518 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3519 } else {
3520 ap->state = ANEG_STATE_AN_ENABLE;
3521 }
3522 } else if (ap->ability_match != 0 &&
3523 ap->rxconfig == 0) {
3524 ap->state = ANEG_STATE_AN_ENABLE;
3525 }
3526 break;
3527
3528 case ANEG_STATE_COMPLETE_ACK_INIT:
3529 if (ap->rxconfig & ANEG_CFG_INVAL) {
3530 ret = ANEG_FAILED;
3531 break;
3532 }
3533 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3534 MR_LP_ADV_HALF_DUPLEX |
3535 MR_LP_ADV_SYM_PAUSE |
3536 MR_LP_ADV_ASYM_PAUSE |
3537 MR_LP_ADV_REMOTE_FAULT1 |
3538 MR_LP_ADV_REMOTE_FAULT2 |
3539 MR_LP_ADV_NEXT_PAGE |
3540 MR_TOGGLE_RX |
3541 MR_NP_RX);
3542 if (ap->rxconfig & ANEG_CFG_FD)
3543 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3544 if (ap->rxconfig & ANEG_CFG_HD)
3545 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3546 if (ap->rxconfig & ANEG_CFG_PS1)
3547 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3548 if (ap->rxconfig & ANEG_CFG_PS2)
3549 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3550 if (ap->rxconfig & ANEG_CFG_RF1)
3551 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3552 if (ap->rxconfig & ANEG_CFG_RF2)
3553 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3554 if (ap->rxconfig & ANEG_CFG_NP)
3555 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3556
3557 ap->link_time = ap->cur_time;
3558
3559 ap->flags ^= (MR_TOGGLE_TX);
3560 if (ap->rxconfig & 0x0008)
3561 ap->flags |= MR_TOGGLE_RX;
3562 if (ap->rxconfig & ANEG_CFG_NP)
3563 ap->flags |= MR_NP_RX;
3564 ap->flags |= MR_PAGE_RX;
3565
3566 ap->state = ANEG_STATE_COMPLETE_ACK;
3567 ret = ANEG_TIMER_ENAB;
3568 break;
3569
3570 case ANEG_STATE_COMPLETE_ACK:
3571 if (ap->ability_match != 0 &&
3572 ap->rxconfig == 0) {
3573 ap->state = ANEG_STATE_AN_ENABLE;
3574 break;
3575 }
3576 delta = ap->cur_time - ap->link_time;
3577 if (delta > ANEG_STATE_SETTLE_TIME) {
3578 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3579 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3580 } else {
3581 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3582 !(ap->flags & MR_NP_RX)) {
3583 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3584 } else {
3585 ret = ANEG_FAILED;
3586 }
3587 }
3588 }
3589 break;
3590
3591 case ANEG_STATE_IDLE_DETECT_INIT:
3592 ap->link_time = ap->cur_time;
3593 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3594 tw32_f(MAC_MODE, tp->mac_mode);
3595 udelay(40);
3596
3597 ap->state = ANEG_STATE_IDLE_DETECT;
3598 ret = ANEG_TIMER_ENAB;
3599 break;
3600
3601 case ANEG_STATE_IDLE_DETECT:
3602 if (ap->ability_match != 0 &&
3603 ap->rxconfig == 0) {
3604 ap->state = ANEG_STATE_AN_ENABLE;
3605 break;
3606 }
3607 delta = ap->cur_time - ap->link_time;
3608 if (delta > ANEG_STATE_SETTLE_TIME) {
3609 /* XXX another gem from the Broadcom driver :( */
3610 ap->state = ANEG_STATE_LINK_OK;
3611 }
3612 break;
3613
3614 case ANEG_STATE_LINK_OK:
3615 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3616 ret = ANEG_DONE;
3617 break;
3618
3619 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3620 /* ??? unimplemented */
3621 break;
3622
3623 case ANEG_STATE_NEXT_PAGE_WAIT:
3624 /* ??? unimplemented */
3625 break;
3626
3627 default:
3628 ret = ANEG_FAILED;
3629 break;
3630 }
3631
3632 return ret;
3633}
3634
3635static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3636{
3637 int res = 0;
3638 struct tg3_fiber_aneginfo aninfo;
3639 int status = ANEG_FAILED;
3640 unsigned int tick;
3641 u32 tmp;
3642
3643 tw32_f(MAC_TX_AUTO_NEG, 0);
3644
3645 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3646 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3647 udelay(40);
3648
3649 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3650 udelay(40);
3651
3652 memset(&aninfo, 0, sizeof(aninfo));
3653 aninfo.flags |= MR_AN_ENABLE;
3654 aninfo.state = ANEG_STATE_UNKNOWN;
3655 aninfo.cur_time = 0;
3656 tick = 0;
3657 while (++tick < 195000) {
3658 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3659 if (status == ANEG_DONE || status == ANEG_FAILED)
3660 break;
3661
3662 udelay(1);
3663 }
3664
3665 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3666 tw32_f(MAC_MODE, tp->mac_mode);
3667 udelay(40);
3668
3669 *txflags = aninfo.txconfig;
3670 *rxflags = aninfo.flags;
3671
3672 if (status == ANEG_DONE &&
3673 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3674 MR_LP_ADV_FULL_DUPLEX)))
3675 res = 1;
3676
3677 return res;
3678}
3679
3680static void tg3_init_bcm8002(struct tg3 *tp)
3681{
3682 u32 mac_status = tr32(MAC_STATUS);
3683 int i;
3684
3685 /* Reset when initting first time or we have a link. */
3686 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3687 !(mac_status & MAC_STATUS_PCS_SYNCED))
3688 return;
3689
3690 /* Set PLL lock range. */
3691 tg3_writephy(tp, 0x16, 0x8007);
3692
3693 /* SW reset */
3694 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3695
3696 /* Wait for reset to complete. */
3697 /* XXX schedule_timeout() ... */
3698 for (i = 0; i < 500; i++)
3699 udelay(10);
3700
3701 /* Config mode; select PMA/Ch 1 regs. */
3702 tg3_writephy(tp, 0x10, 0x8411);
3703
3704 /* Enable auto-lock and comdet, select txclk for tx. */
3705 tg3_writephy(tp, 0x11, 0x0a10);
3706
3707 tg3_writephy(tp, 0x18, 0x00a0);
3708 tg3_writephy(tp, 0x16, 0x41ff);
3709
3710 /* Assert and deassert POR. */
3711 tg3_writephy(tp, 0x13, 0x0400);
3712 udelay(40);
3713 tg3_writephy(tp, 0x13, 0x0000);
3714
3715 tg3_writephy(tp, 0x11, 0x0a50);
3716 udelay(40);
3717 tg3_writephy(tp, 0x11, 0x0a10);
3718
3719 /* Wait for signal to stabilize */
3720 /* XXX schedule_timeout() ... */
3721 for (i = 0; i < 15000; i++)
3722 udelay(10);
3723
3724 /* Deselect the channel register so we can read the PHYID
3725 * later.
3726 */
3727 tg3_writephy(tp, 0x10, 0x8011);
3728}
3729
3730static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3731{
3732 u16 flowctrl;
3733 u32 sg_dig_ctrl, sg_dig_status;
3734 u32 serdes_cfg, expected_sg_dig_ctrl;
3735 int workaround, port_a;
3736 int current_link_up;
3737
3738 serdes_cfg = 0;
3739 expected_sg_dig_ctrl = 0;
3740 workaround = 0;
3741 port_a = 1;
3742 current_link_up = 0;
3743
3744 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3745 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3746 workaround = 1;
3747 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3748 port_a = 0;
3749
3750 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3751 /* preserve bits 20-23 for voltage regulator */
3752 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3753 }
3754
3755 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3756
3757 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3758 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3759 if (workaround) {
3760 u32 val = serdes_cfg;
3761
3762 if (port_a)
3763 val |= 0xc010000;
3764 else
3765 val |= 0x4010000;
3766 tw32_f(MAC_SERDES_CFG, val);
3767 }
3768
3769 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3770 }
3771 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3772 tg3_setup_flow_control(tp, 0, 0);
3773 current_link_up = 1;
3774 }
3775 goto out;
3776 }
3777
3778 /* Want auto-negotiation. */
3779 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3780
3781 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3782 if (flowctrl & ADVERTISE_1000XPAUSE)
3783 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3784 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3785 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3786
3787 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3788 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3789 tp->serdes_counter &&
3790 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3791 MAC_STATUS_RCVD_CFG)) ==
3792 MAC_STATUS_PCS_SYNCED)) {
3793 tp->serdes_counter--;
3794 current_link_up = 1;
3795 goto out;
3796 }
3797restart_autoneg:
3798 if (workaround)
3799 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3800 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3801 udelay(5);
3802 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3803
3804 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3805 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3806 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3807 MAC_STATUS_SIGNAL_DET)) {
3808 sg_dig_status = tr32(SG_DIG_STATUS);
3809 mac_status = tr32(MAC_STATUS);
3810
3811 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3812 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3813 u32 local_adv = 0, remote_adv = 0;
3814
3815 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3816 local_adv |= ADVERTISE_1000XPAUSE;
3817 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3818 local_adv |= ADVERTISE_1000XPSE_ASYM;
3819
3820 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3821 remote_adv |= LPA_1000XPAUSE;
3822 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3823 remote_adv |= LPA_1000XPAUSE_ASYM;
3824
3825 tg3_setup_flow_control(tp, local_adv, remote_adv);
3826 current_link_up = 1;
3827 tp->serdes_counter = 0;
3828 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3829 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3830 if (tp->serdes_counter)
3831 tp->serdes_counter--;
3832 else {
3833 if (workaround) {
3834 u32 val = serdes_cfg;
3835
3836 if (port_a)
3837 val |= 0xc010000;
3838 else
3839 val |= 0x4010000;
3840
3841 tw32_f(MAC_SERDES_CFG, val);
3842 }
3843
3844 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3845 udelay(40);
3846
3847 /* Link parallel detection - link is up */
3848 /* only if we have PCS_SYNC and not */
3849 /* receiving config code words */
3850 mac_status = tr32(MAC_STATUS);
3851 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3852 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3853 tg3_setup_flow_control(tp, 0, 0);
3854 current_link_up = 1;
3855 tp->tg3_flags2 |=
3856 TG3_FLG2_PARALLEL_DETECT;
3857 tp->serdes_counter =
3858 SERDES_PARALLEL_DET_TIMEOUT;
3859 } else
3860 goto restart_autoneg;
3861 }
3862 }
3863 } else {
3864 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3865 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3866 }
3867
3868out:
3869 return current_link_up;
3870}
3871
3872static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3873{
3874 int current_link_up = 0;
3875
3876 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3877 goto out;
3878
3879 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3880 u32 txflags, rxflags;
3881 int i;
3882
3883 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3884 u32 local_adv = 0, remote_adv = 0;
3885
3886 if (txflags & ANEG_CFG_PS1)
3887 local_adv |= ADVERTISE_1000XPAUSE;
3888 if (txflags & ANEG_CFG_PS2)
3889 local_adv |= ADVERTISE_1000XPSE_ASYM;
3890
3891 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3892 remote_adv |= LPA_1000XPAUSE;
3893 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3894 remote_adv |= LPA_1000XPAUSE_ASYM;
3895
3896 tg3_setup_flow_control(tp, local_adv, remote_adv);
3897
3898 current_link_up = 1;
3899 }
3900 for (i = 0; i < 30; i++) {
3901 udelay(20);
3902 tw32_f(MAC_STATUS,
3903 (MAC_STATUS_SYNC_CHANGED |
3904 MAC_STATUS_CFG_CHANGED));
3905 udelay(40);
3906 if ((tr32(MAC_STATUS) &
3907 (MAC_STATUS_SYNC_CHANGED |
3908 MAC_STATUS_CFG_CHANGED)) == 0)
3909 break;
3910 }
3911
3912 mac_status = tr32(MAC_STATUS);
3913 if (current_link_up == 0 &&
3914 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3915 !(mac_status & MAC_STATUS_RCVD_CFG))
3916 current_link_up = 1;
3917 } else {
3918 tg3_setup_flow_control(tp, 0, 0);
3919
3920 /* Forcing 1000FD link up. */
3921 current_link_up = 1;
3922
3923 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3924 udelay(40);
3925
3926 tw32_f(MAC_MODE, tp->mac_mode);
3927 udelay(40);
3928 }
3929
3930out:
3931 return current_link_up;
3932}
3933
3934static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3935{
3936 u32 orig_pause_cfg;
3937 u16 orig_active_speed;
3938 u8 orig_active_duplex;
3939 u32 mac_status;
3940 int current_link_up;
3941 int i;
3942
3943 orig_pause_cfg = tp->link_config.active_flowctrl;
3944 orig_active_speed = tp->link_config.active_speed;
3945 orig_active_duplex = tp->link_config.active_duplex;
3946
3947 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3948 netif_carrier_ok(tp->dev) &&
3949 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3950 mac_status = tr32(MAC_STATUS);
3951 mac_status &= (MAC_STATUS_PCS_SYNCED |
3952 MAC_STATUS_SIGNAL_DET |
3953 MAC_STATUS_CFG_CHANGED |
3954 MAC_STATUS_RCVD_CFG);
3955 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3956 MAC_STATUS_SIGNAL_DET)) {
3957 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3958 MAC_STATUS_CFG_CHANGED));
3959 return 0;
3960 }
3961 }
3962
3963 tw32_f(MAC_TX_AUTO_NEG, 0);
3964
3965 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3966 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3967 tw32_f(MAC_MODE, tp->mac_mode);
3968 udelay(40);
3969
3970 if (tp->phy_id == PHY_ID_BCM8002)
3971 tg3_init_bcm8002(tp);
3972
3973 /* Enable link change event even when serdes polling. */
3974 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3975 udelay(40);
3976
3977 current_link_up = 0;
3978 mac_status = tr32(MAC_STATUS);
3979
3980 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3981 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3982 else
3983 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3984
3985 tp->napi[0].hw_status->status =
3986 (SD_STATUS_UPDATED |
3987 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3988
3989 for (i = 0; i < 100; i++) {
3990 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3991 MAC_STATUS_CFG_CHANGED));
3992 udelay(5);
3993 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3994 MAC_STATUS_CFG_CHANGED |
3995 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3996 break;
3997 }
3998
3999 mac_status = tr32(MAC_STATUS);
4000 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4001 current_link_up = 0;
4002 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4003 tp->serdes_counter == 0) {
4004 tw32_f(MAC_MODE, (tp->mac_mode |
4005 MAC_MODE_SEND_CONFIGS));
4006 udelay(1);
4007 tw32_f(MAC_MODE, tp->mac_mode);
4008 }
4009 }
4010
4011 if (current_link_up == 1) {
4012 tp->link_config.active_speed = SPEED_1000;
4013 tp->link_config.active_duplex = DUPLEX_FULL;
4014 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4015 LED_CTRL_LNKLED_OVERRIDE |
4016 LED_CTRL_1000MBPS_ON));
4017 } else {
4018 tp->link_config.active_speed = SPEED_INVALID;
4019 tp->link_config.active_duplex = DUPLEX_INVALID;
4020 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4021 LED_CTRL_LNKLED_OVERRIDE |
4022 LED_CTRL_TRAFFIC_OVERRIDE));
4023 }
4024
4025 if (current_link_up != netif_carrier_ok(tp->dev)) {
4026 if (current_link_up)
4027 netif_carrier_on(tp->dev);
4028 else
4029 netif_carrier_off(tp->dev);
4030 tg3_link_report(tp);
4031 } else {
4032 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4033 if (orig_pause_cfg != now_pause_cfg ||
4034 orig_active_speed != tp->link_config.active_speed ||
4035 orig_active_duplex != tp->link_config.active_duplex)
4036 tg3_link_report(tp);
4037 }
4038
4039 return 0;
4040}
4041
4042static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4043{
4044 int current_link_up, err = 0;
4045 u32 bmsr, bmcr;
4046 u16 current_speed;
4047 u8 current_duplex;
4048 u32 local_adv, remote_adv;
4049
4050 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4051 tw32_f(MAC_MODE, tp->mac_mode);
4052 udelay(40);
4053
4054 tw32(MAC_EVENT, 0);
4055
4056 tw32_f(MAC_STATUS,
4057 (MAC_STATUS_SYNC_CHANGED |
4058 MAC_STATUS_CFG_CHANGED |
4059 MAC_STATUS_MI_COMPLETION |
4060 MAC_STATUS_LNKSTATE_CHANGED));
4061 udelay(40);
4062
4063 if (force_reset)
4064 tg3_phy_reset(tp);
4065
4066 current_link_up = 0;
4067 current_speed = SPEED_INVALID;
4068 current_duplex = DUPLEX_INVALID;
4069
4070 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4071 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4073 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4074 bmsr |= BMSR_LSTATUS;
4075 else
4076 bmsr &= ~BMSR_LSTATUS;
4077 }
4078
4079 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4080
4081 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4082 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4083 /* do nothing, just check for link up at the end */
4084 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4085 u32 adv, new_adv;
4086
4087 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4088 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4089 ADVERTISE_1000XPAUSE |
4090 ADVERTISE_1000XPSE_ASYM |
4091 ADVERTISE_SLCT);
4092
4093 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4094
4095 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4096 new_adv |= ADVERTISE_1000XHALF;
4097 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4098 new_adv |= ADVERTISE_1000XFULL;
4099
4100 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4101 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4102 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4103 tg3_writephy(tp, MII_BMCR, bmcr);
4104
4105 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4106 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4107 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4108
4109 return err;
4110 }
4111 } else {
4112 u32 new_bmcr;
4113
4114 bmcr &= ~BMCR_SPEED1000;
4115 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4116
4117 if (tp->link_config.duplex == DUPLEX_FULL)
4118 new_bmcr |= BMCR_FULLDPLX;
4119
4120 if (new_bmcr != bmcr) {
4121 /* BMCR_SPEED1000 is a reserved bit that needs
4122 * to be set on write.
4123 */
4124 new_bmcr |= BMCR_SPEED1000;
4125
4126 /* Force a linkdown */
4127 if (netif_carrier_ok(tp->dev)) {
4128 u32 adv;
4129
4130 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4131 adv &= ~(ADVERTISE_1000XFULL |
4132 ADVERTISE_1000XHALF |
4133 ADVERTISE_SLCT);
4134 tg3_writephy(tp, MII_ADVERTISE, adv);
4135 tg3_writephy(tp, MII_BMCR, bmcr |
4136 BMCR_ANRESTART |
4137 BMCR_ANENABLE);
4138 udelay(10);
4139 netif_carrier_off(tp->dev);
4140 }
4141 tg3_writephy(tp, MII_BMCR, new_bmcr);
4142 bmcr = new_bmcr;
4143 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4144 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4145 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4146 ASIC_REV_5714) {
4147 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4148 bmsr |= BMSR_LSTATUS;
4149 else
4150 bmsr &= ~BMSR_LSTATUS;
4151 }
4152 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4153 }
4154 }
4155
4156 if (bmsr & BMSR_LSTATUS) {
4157 current_speed = SPEED_1000;
4158 current_link_up = 1;
4159 if (bmcr & BMCR_FULLDPLX)
4160 current_duplex = DUPLEX_FULL;
4161 else
4162 current_duplex = DUPLEX_HALF;
4163
4164 local_adv = 0;
4165 remote_adv = 0;
4166
4167 if (bmcr & BMCR_ANENABLE) {
4168 u32 common;
4169
4170 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4171 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4172 common = local_adv & remote_adv;
4173 if (common & (ADVERTISE_1000XHALF |
4174 ADVERTISE_1000XFULL)) {
4175 if (common & ADVERTISE_1000XFULL)
4176 current_duplex = DUPLEX_FULL;
4177 else
4178 current_duplex = DUPLEX_HALF;
4179 }
4180 else
4181 current_link_up = 0;
4182 }
4183 }
4184
4185 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4186 tg3_setup_flow_control(tp, local_adv, remote_adv);
4187
4188 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4189 if (tp->link_config.active_duplex == DUPLEX_HALF)
4190 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4191
4192 tw32_f(MAC_MODE, tp->mac_mode);
4193 udelay(40);
4194
4195 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4196
4197 tp->link_config.active_speed = current_speed;
4198 tp->link_config.active_duplex = current_duplex;
4199
4200 if (current_link_up != netif_carrier_ok(tp->dev)) {
4201 if (current_link_up)
4202 netif_carrier_on(tp->dev);
4203 else {
4204 netif_carrier_off(tp->dev);
4205 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4206 }
4207 tg3_link_report(tp);
4208 }
4209 return err;
4210}
4211
4212static void tg3_serdes_parallel_detect(struct tg3 *tp)
4213{
4214 if (tp->serdes_counter) {
4215 /* Give autoneg time to complete. */
4216 tp->serdes_counter--;
4217 return;
4218 }
4219 if (!netif_carrier_ok(tp->dev) &&
4220 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4221 u32 bmcr;
4222
4223 tg3_readphy(tp, MII_BMCR, &bmcr);
4224 if (bmcr & BMCR_ANENABLE) {
4225 u32 phy1, phy2;
4226
4227 /* Select shadow register 0x1f */
4228 tg3_writephy(tp, 0x1c, 0x7c00);
4229 tg3_readphy(tp, 0x1c, &phy1);
4230
4231 /* Select expansion interrupt status register */
4232 tg3_writephy(tp, 0x17, 0x0f01);
4233 tg3_readphy(tp, 0x15, &phy2);
4234 tg3_readphy(tp, 0x15, &phy2);
4235
4236 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4237 /* We have signal detect and not receiving
4238 * config code words, link is up by parallel
4239 * detection.
4240 */
4241
4242 bmcr &= ~BMCR_ANENABLE;
4243 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4244 tg3_writephy(tp, MII_BMCR, bmcr);
4245 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4246 }
4247 }
4248 }
4249 else if (netif_carrier_ok(tp->dev) &&
4250 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4251 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4252 u32 phy2;
4253
4254 /* Select expansion interrupt status register */
4255 tg3_writephy(tp, 0x17, 0x0f01);
4256 tg3_readphy(tp, 0x15, &phy2);
4257 if (phy2 & 0x20) {
4258 u32 bmcr;
4259
4260 /* Config code words received, turn on autoneg. */
4261 tg3_readphy(tp, MII_BMCR, &bmcr);
4262 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4263
4264 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4265
4266 }
4267 }
4268}
4269
4270static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4271{
4272 int err;
4273
4274 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4275 err = tg3_setup_fiber_phy(tp, force_reset);
4276 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4277 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4278 } else {
4279 err = tg3_setup_copper_phy(tp, force_reset);
4280 }
4281
4282 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4283 u32 val, scale;
4284
4285 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4286 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4287 scale = 65;
4288 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4289 scale = 6;
4290 else
4291 scale = 12;
4292
4293 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4294 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4295 tw32(GRC_MISC_CFG, val);
4296 }
4297
4298 if (tp->link_config.active_speed == SPEED_1000 &&
4299 tp->link_config.active_duplex == DUPLEX_HALF)
4300 tw32(MAC_TX_LENGTHS,
4301 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4302 (6 << TX_LENGTHS_IPG_SHIFT) |
4303 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4304 else
4305 tw32(MAC_TX_LENGTHS,
4306 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4307 (6 << TX_LENGTHS_IPG_SHIFT) |
4308 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4309
4310 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4311 if (netif_carrier_ok(tp->dev)) {
4312 tw32(HOSTCC_STAT_COAL_TICKS,
4313 tp->coal.stats_block_coalesce_usecs);
4314 } else {
4315 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4316 }
4317 }
4318
4319 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4320 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4321 if (!netif_carrier_ok(tp->dev))
4322 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4323 tp->pwrmgmt_thresh;
4324 else
4325 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4326 tw32(PCIE_PWR_MGMT_THRESH, val);
4327 }
4328
4329 return err;
4330}
4331
4332/* This is called whenever we suspect that the system chipset is re-
4333 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4334 * is bogus tx completions. We try to recover by setting the
4335 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4336 * in the workqueue.
4337 */
4338static void tg3_tx_recover(struct tg3 *tp)
4339{
4340 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4341 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4342
4343 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4344 "mapped I/O cycles to the network device, attempting to "
4345 "recover. Please report the problem to the driver maintainer "
4346 "and include system chipset information.\n", tp->dev->name);
4347
4348 spin_lock(&tp->lock);
4349 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4350 spin_unlock(&tp->lock);
4351}
4352
4353static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4354{
4355 smp_mb();
4356 return tnapi->tx_pending -
4357 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4358}
4359
4360/* Tigon3 never reports partial packet sends. So we do not
4361 * need special logic to handle SKBs that have not had all
4362 * of their frags sent yet, like SunGEM does.
4363 */
4364static void tg3_tx(struct tg3_napi *tnapi)
4365{
4366 struct tg3 *tp = tnapi->tp;
4367 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4368 u32 sw_idx = tnapi->tx_cons;
4369 struct netdev_queue *txq;
4370 int index = tnapi - tp->napi;
4371
4372 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4373 index--;
4374
4375 txq = netdev_get_tx_queue(tp->dev, index);
4376
4377 while (sw_idx != hw_idx) {
4378 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4379 struct sk_buff *skb = ri->skb;
4380 int i, tx_bug = 0;
4381
4382 if (unlikely(skb == NULL)) {
4383 tg3_tx_recover(tp);
4384 return;
4385 }
4386
4387 pci_unmap_single(tp->pdev,
4388 pci_unmap_addr(ri, mapping),
4389 skb_headlen(skb),
4390 PCI_DMA_TODEVICE);
4391
4392 ri->skb = NULL;
4393
4394 sw_idx = NEXT_TX(sw_idx);
4395
4396 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4397 ri = &tnapi->tx_buffers[sw_idx];
4398 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4399 tx_bug = 1;
4400
4401 pci_unmap_page(tp->pdev,
4402 pci_unmap_addr(ri, mapping),
4403 skb_shinfo(skb)->frags[i].size,
4404 PCI_DMA_TODEVICE);
4405 sw_idx = NEXT_TX(sw_idx);
4406 }
4407
4408 dev_kfree_skb(skb);
4409
4410 if (unlikely(tx_bug)) {
4411 tg3_tx_recover(tp);
4412 return;
4413 }
4414 }
4415
4416 tnapi->tx_cons = sw_idx;
4417
4418 /* Need to make the tx_cons update visible to tg3_start_xmit()
4419 * before checking for netif_queue_stopped(). Without the
4420 * memory barrier, there is a small possibility that tg3_start_xmit()
4421 * will miss it and cause the queue to be stopped forever.
4422 */
4423 smp_mb();
4424
4425 if (unlikely(netif_tx_queue_stopped(txq) &&
4426 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4427 __netif_tx_lock(txq, smp_processor_id());
4428 if (netif_tx_queue_stopped(txq) &&
4429 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4430 netif_tx_wake_queue(txq);
4431 __netif_tx_unlock(txq);
4432 }
4433}
4434
4435static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4436{
4437 if (!ri->skb)
4438 return;
4439
4440 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4441 map_sz, PCI_DMA_FROMDEVICE);
4442 dev_kfree_skb_any(ri->skb);
4443 ri->skb = NULL;
4444}
4445
4446/* Returns size of skb allocated or < 0 on error.
4447 *
4448 * We only need to fill in the address because the other members
4449 * of the RX descriptor are invariant, see tg3_init_rings.
4450 *
4451 * Note the purposeful assymetry of cpu vs. chip accesses. For
4452 * posting buffers we only dirty the first cache line of the RX
4453 * descriptor (containing the address). Whereas for the RX status
4454 * buffers the cpu only reads the last cacheline of the RX descriptor
4455 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4456 */
4457static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4458 u32 opaque_key, u32 dest_idx_unmasked)
4459{
4460 struct tg3_rx_buffer_desc *desc;
4461 struct ring_info *map, *src_map;
4462 struct sk_buff *skb;
4463 dma_addr_t mapping;
4464 int skb_size, dest_idx;
4465
4466 src_map = NULL;
4467 switch (opaque_key) {
4468 case RXD_OPAQUE_RING_STD:
4469 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4470 desc = &tpr->rx_std[dest_idx];
4471 map = &tpr->rx_std_buffers[dest_idx];
4472 skb_size = tp->rx_pkt_map_sz;
4473 break;
4474
4475 case RXD_OPAQUE_RING_JUMBO:
4476 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4477 desc = &tpr->rx_jmb[dest_idx].std;
4478 map = &tpr->rx_jmb_buffers[dest_idx];
4479 skb_size = TG3_RX_JMB_MAP_SZ;
4480 break;
4481
4482 default:
4483 return -EINVAL;
4484 }
4485
4486 /* Do not overwrite any of the map or rp information
4487 * until we are sure we can commit to a new buffer.
4488 *
4489 * Callers depend upon this behavior and assume that
4490 * we leave everything unchanged if we fail.
4491 */
4492 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4493 if (skb == NULL)
4494 return -ENOMEM;
4495
4496 skb_reserve(skb, tp->rx_offset);
4497
4498 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4499 PCI_DMA_FROMDEVICE);
4500 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4501 dev_kfree_skb(skb);
4502 return -EIO;
4503 }
4504
4505 map->skb = skb;
4506 pci_unmap_addr_set(map, mapping, mapping);
4507
4508 desc->addr_hi = ((u64)mapping >> 32);
4509 desc->addr_lo = ((u64)mapping & 0xffffffff);
4510
4511 return skb_size;
4512}
4513
4514/* We only need to move over in the address because the other
4515 * members of the RX descriptor are invariant. See notes above
4516 * tg3_alloc_rx_skb for full details.
4517 */
4518static void tg3_recycle_rx(struct tg3_napi *tnapi,
4519 struct tg3_rx_prodring_set *dpr,
4520 u32 opaque_key, int src_idx,
4521 u32 dest_idx_unmasked)
4522{
4523 struct tg3 *tp = tnapi->tp;
4524 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4525 struct ring_info *src_map, *dest_map;
4526 int dest_idx;
4527 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4528
4529 switch (opaque_key) {
4530 case RXD_OPAQUE_RING_STD:
4531 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4532 dest_desc = &dpr->rx_std[dest_idx];
4533 dest_map = &dpr->rx_std_buffers[dest_idx];
4534 src_desc = &spr->rx_std[src_idx];
4535 src_map = &spr->rx_std_buffers[src_idx];
4536 break;
4537
4538 case RXD_OPAQUE_RING_JUMBO:
4539 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4540 dest_desc = &dpr->rx_jmb[dest_idx].std;
4541 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4542 src_desc = &spr->rx_jmb[src_idx].std;
4543 src_map = &spr->rx_jmb_buffers[src_idx];
4544 break;
4545
4546 default:
4547 return;
4548 }
4549
4550 dest_map->skb = src_map->skb;
4551 pci_unmap_addr_set(dest_map, mapping,
4552 pci_unmap_addr(src_map, mapping));
4553 dest_desc->addr_hi = src_desc->addr_hi;
4554 dest_desc->addr_lo = src_desc->addr_lo;
4555
4556 /* Ensure that the update to the skb happens after the physical
4557 * addresses have been transferred to the new BD location.
4558 */
4559 smp_wmb();
4560
4561 src_map->skb = NULL;
4562}
4563
4564/* The RX ring scheme is composed of multiple rings which post fresh
4565 * buffers to the chip, and one special ring the chip uses to report
4566 * status back to the host.
4567 *
4568 * The special ring reports the status of received packets to the
4569 * host. The chip does not write into the original descriptor the
4570 * RX buffer was obtained from. The chip simply takes the original
4571 * descriptor as provided by the host, updates the status and length
4572 * field, then writes this into the next status ring entry.
4573 *
4574 * Each ring the host uses to post buffers to the chip is described
4575 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4576 * it is first placed into the on-chip ram. When the packet's length
4577 * is known, it walks down the TG3_BDINFO entries to select the ring.
4578 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4579 * which is within the range of the new packet's length is chosen.
4580 *
4581 * The "separate ring for rx status" scheme may sound queer, but it makes
4582 * sense from a cache coherency perspective. If only the host writes
4583 * to the buffer post rings, and only the chip writes to the rx status
4584 * rings, then cache lines never move beyond shared-modified state.
4585 * If both the host and chip were to write into the same ring, cache line
4586 * eviction could occur since both entities want it in an exclusive state.
4587 */
4588static int tg3_rx(struct tg3_napi *tnapi, int budget)
4589{
4590 struct tg3 *tp = tnapi->tp;
4591 u32 work_mask, rx_std_posted = 0;
4592 u32 std_prod_idx, jmb_prod_idx;
4593 u32 sw_idx = tnapi->rx_rcb_ptr;
4594 u16 hw_idx;
4595 int received;
4596 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4597
4598 hw_idx = *(tnapi->rx_rcb_prod_idx);
4599 /*
4600 * We need to order the read of hw_idx and the read of
4601 * the opaque cookie.
4602 */
4603 rmb();
4604 work_mask = 0;
4605 received = 0;
4606 std_prod_idx = tpr->rx_std_prod_idx;
4607 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4608 while (sw_idx != hw_idx && budget > 0) {
4609 struct ring_info *ri;
4610 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4611 unsigned int len;
4612 struct sk_buff *skb;
4613 dma_addr_t dma_addr;
4614 u32 opaque_key, desc_idx, *post_ptr;
4615
4616 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4617 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4618 if (opaque_key == RXD_OPAQUE_RING_STD) {
4619 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4620 dma_addr = pci_unmap_addr(ri, mapping);
4621 skb = ri->skb;
4622 post_ptr = &std_prod_idx;
4623 rx_std_posted++;
4624 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4625 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4626 dma_addr = pci_unmap_addr(ri, mapping);
4627 skb = ri->skb;
4628 post_ptr = &jmb_prod_idx;
4629 } else
4630 goto next_pkt_nopost;
4631
4632 work_mask |= opaque_key;
4633
4634 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4635 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4636 drop_it:
4637 tg3_recycle_rx(tnapi, tpr, opaque_key,
4638 desc_idx, *post_ptr);
4639 drop_it_no_recycle:
4640 /* Other statistics kept track of by card. */
4641 tp->net_stats.rx_dropped++;
4642 goto next_pkt;
4643 }
4644
4645 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4646 ETH_FCS_LEN;
4647
4648 if (len > RX_COPY_THRESHOLD &&
4649 tp->rx_offset == NET_IP_ALIGN) {
4650 /* rx_offset will likely not equal NET_IP_ALIGN
4651 * if this is a 5701 card running in PCI-X mode
4652 * [see tg3_get_invariants()]
4653 */
4654 int skb_size;
4655
4656 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4657 *post_ptr);
4658 if (skb_size < 0)
4659 goto drop_it;
4660
4661 ri->skb = NULL;
4662
4663 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4664 PCI_DMA_FROMDEVICE);
4665
4666 skb_put(skb, len);
4667 } else {
4668 struct sk_buff *copy_skb;
4669
4670 tg3_recycle_rx(tnapi, tpr, opaque_key,
4671 desc_idx, *post_ptr);
4672
4673 copy_skb = netdev_alloc_skb(tp->dev,
4674 len + TG3_RAW_IP_ALIGN);
4675 if (copy_skb == NULL)
4676 goto drop_it_no_recycle;
4677
4678 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4679 skb_put(copy_skb, len);
4680 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4681 skb_copy_from_linear_data(skb, copy_skb->data, len);
4682 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4683
4684 /* We'll reuse the original ring buffer. */
4685 skb = copy_skb;
4686 }
4687
4688 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4689 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4690 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4691 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4692 skb->ip_summed = CHECKSUM_UNNECESSARY;
4693 else
4694 skb->ip_summed = CHECKSUM_NONE;
4695
4696 skb->protocol = eth_type_trans(skb, tp->dev);
4697
4698 if (len > (tp->dev->mtu + ETH_HLEN) &&
4699 skb->protocol != htons(ETH_P_8021Q)) {
4700 dev_kfree_skb(skb);
4701 goto next_pkt;
4702 }
4703
4704#if TG3_VLAN_TAG_USED
4705 if (tp->vlgrp != NULL &&
4706 desc->type_flags & RXD_FLAG_VLAN) {
4707 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4708 desc->err_vlan & RXD_VLAN_MASK, skb);
4709 } else
4710#endif
4711 napi_gro_receive(&tnapi->napi, skb);
4712
4713 received++;
4714 budget--;
4715
4716next_pkt:
4717 (*post_ptr)++;
4718
4719 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4720 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4721 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4722 tpr->rx_std_prod_idx);
4723 work_mask &= ~RXD_OPAQUE_RING_STD;
4724 rx_std_posted = 0;
4725 }
4726next_pkt_nopost:
4727 sw_idx++;
4728 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4729
4730 /* Refresh hw_idx to see if there is new work */
4731 if (sw_idx == hw_idx) {
4732 hw_idx = *(tnapi->rx_rcb_prod_idx);
4733 rmb();
4734 }
4735 }
4736
4737 /* ACK the status ring. */
4738 tnapi->rx_rcb_ptr = sw_idx;
4739 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4740
4741 /* Refill RX ring(s). */
4742 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4743 if (work_mask & RXD_OPAQUE_RING_STD) {
4744 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4745 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4746 tpr->rx_std_prod_idx);
4747 }
4748 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4749 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4750 TG3_RX_JUMBO_RING_SIZE;
4751 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4752 tpr->rx_jmb_prod_idx);
4753 }
4754 mmiowb();
4755 } else if (work_mask) {
4756 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4757 * updated before the producer indices can be updated.
4758 */
4759 smp_wmb();
4760
4761 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4762 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4763
4764 if (tnapi != &tp->napi[1])
4765 napi_schedule(&tp->napi[1].napi);
4766 }
4767
4768 return received;
4769}
4770
4771static void tg3_poll_link(struct tg3 *tp)
4772{
4773 /* handle link change and other phy events */
4774 if (!(tp->tg3_flags &
4775 (TG3_FLAG_USE_LINKCHG_REG |
4776 TG3_FLAG_POLL_SERDES))) {
4777 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4778
4779 if (sblk->status & SD_STATUS_LINK_CHG) {
4780 sblk->status = SD_STATUS_UPDATED |
4781 (sblk->status & ~SD_STATUS_LINK_CHG);
4782 spin_lock(&tp->lock);
4783 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4784 tw32_f(MAC_STATUS,
4785 (MAC_STATUS_SYNC_CHANGED |
4786 MAC_STATUS_CFG_CHANGED |
4787 MAC_STATUS_MI_COMPLETION |
4788 MAC_STATUS_LNKSTATE_CHANGED));
4789 udelay(40);
4790 } else
4791 tg3_setup_phy(tp, 0);
4792 spin_unlock(&tp->lock);
4793 }
4794 }
4795}
4796
4797static void tg3_rx_prodring_xfer(struct tg3 *tp,
4798 struct tg3_rx_prodring_set *dpr,
4799 struct tg3_rx_prodring_set *spr)
4800{
4801 u32 si, di, cpycnt, src_prod_idx;
4802 int i;
4803
4804 while (1) {
4805 src_prod_idx = spr->rx_std_prod_idx;
4806
4807 /* Make sure updates to the rx_std_buffers[] entries and the
4808 * standard producer index are seen in the correct order.
4809 */
4810 smp_rmb();
4811
4812 if (spr->rx_std_cons_idx == src_prod_idx)
4813 break;
4814
4815 if (spr->rx_std_cons_idx < src_prod_idx)
4816 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4817 else
4818 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4819
4820 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4821
4822 si = spr->rx_std_cons_idx;
4823 di = dpr->rx_std_prod_idx;
4824
4825 for (i = di; i < di + cpycnt; i++) {
4826 if (dpr->rx_std_buffers[i].skb) {
4827 cpycnt = i - di;
4828 break;
4829 }
4830 }
4831
4832 if (!cpycnt)
4833 break;
4834
4835 /* Ensure that updates to the rx_std_buffers ring and the
4836 * shadowed hardware producer ring from tg3_recycle_skb() are
4837 * ordered correctly WRT the skb check above.
4838 */
4839 smp_rmb();
4840
4841 memcpy(&dpr->rx_std_buffers[di],
4842 &spr->rx_std_buffers[si],
4843 cpycnt * sizeof(struct ring_info));
4844
4845 for (i = 0; i < cpycnt; i++, di++, si++) {
4846 struct tg3_rx_buffer_desc *sbd, *dbd;
4847 sbd = &spr->rx_std[si];
4848 dbd = &dpr->rx_std[di];
4849 dbd->addr_hi = sbd->addr_hi;
4850 dbd->addr_lo = sbd->addr_lo;
4851 }
4852
4853 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4854 TG3_RX_RING_SIZE;
4855 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4856 TG3_RX_RING_SIZE;
4857 }
4858
4859 while (1) {
4860 src_prod_idx = spr->rx_jmb_prod_idx;
4861
4862 /* Make sure updates to the rx_jmb_buffers[] entries and
4863 * the jumbo producer index are seen in the correct order.
4864 */
4865 smp_rmb();
4866
4867 if (spr->rx_jmb_cons_idx == src_prod_idx)
4868 break;
4869
4870 if (spr->rx_jmb_cons_idx < src_prod_idx)
4871 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4872 else
4873 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4874
4875 cpycnt = min(cpycnt,
4876 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4877
4878 si = spr->rx_jmb_cons_idx;
4879 di = dpr->rx_jmb_prod_idx;
4880
4881 for (i = di; i < di + cpycnt; i++) {
4882 if (dpr->rx_jmb_buffers[i].skb) {
4883 cpycnt = i - di;
4884 break;
4885 }
4886 }
4887
4888 if (!cpycnt)
4889 break;
4890
4891 /* Ensure that updates to the rx_jmb_buffers ring and the
4892 * shadowed hardware producer ring from tg3_recycle_skb() are
4893 * ordered correctly WRT the skb check above.
4894 */
4895 smp_rmb();
4896
4897 memcpy(&dpr->rx_jmb_buffers[di],
4898 &spr->rx_jmb_buffers[si],
4899 cpycnt * sizeof(struct ring_info));
4900
4901 for (i = 0; i < cpycnt; i++, di++, si++) {
4902 struct tg3_rx_buffer_desc *sbd, *dbd;
4903 sbd = &spr->rx_jmb[si].std;
4904 dbd = &dpr->rx_jmb[di].std;
4905 dbd->addr_hi = sbd->addr_hi;
4906 dbd->addr_lo = sbd->addr_lo;
4907 }
4908
4909 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4910 TG3_RX_JUMBO_RING_SIZE;
4911 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4912 TG3_RX_JUMBO_RING_SIZE;
4913 }
4914}
4915
4916static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4917{
4918 struct tg3 *tp = tnapi->tp;
4919
4920 /* run TX completion thread */
4921 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4922 tg3_tx(tnapi);
4923 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4924 return work_done;
4925 }
4926
4927 /* run RX thread, within the bounds set by NAPI.
4928 * All RX "locking" is done by ensuring outside
4929 * code synchronizes with tg3->napi.poll()
4930 */
4931 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4932 work_done += tg3_rx(tnapi, budget - work_done);
4933
4934 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4935 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4936 int i;
4937 u32 std_prod_idx = dpr->rx_std_prod_idx;
4938 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4939
4940 for (i = 1; i < tp->irq_cnt; i++)
4941 tg3_rx_prodring_xfer(tp, dpr, tp->napi[i].prodring);
4942
4943 wmb();
4944
4945 if (std_prod_idx != dpr->rx_std_prod_idx)
4946 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4947 dpr->rx_std_prod_idx);
4948
4949 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4950 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4951 dpr->rx_jmb_prod_idx);
4952
4953 mmiowb();
4954 }
4955
4956 return work_done;
4957}
4958
4959static int tg3_poll_msix(struct napi_struct *napi, int budget)
4960{
4961 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4962 struct tg3 *tp = tnapi->tp;
4963 int work_done = 0;
4964 struct tg3_hw_status *sblk = tnapi->hw_status;
4965
4966 while (1) {
4967 work_done = tg3_poll_work(tnapi, work_done, budget);
4968
4969 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4970 goto tx_recovery;
4971
4972 if (unlikely(work_done >= budget))
4973 break;
4974
4975 /* tp->last_tag is used in tg3_restart_ints() below
4976 * to tell the hw how much work has been processed,
4977 * so we must read it before checking for more work.
4978 */
4979 tnapi->last_tag = sblk->status_tag;
4980 tnapi->last_irq_tag = tnapi->last_tag;
4981 rmb();
4982
4983 /* check for RX/TX work to do */
4984 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4985 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4986 napi_complete(napi);
4987 /* Reenable interrupts. */
4988 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4989 mmiowb();
4990 break;
4991 }
4992 }
4993
4994 return work_done;
4995
4996tx_recovery:
4997 /* work_done is guaranteed to be less than budget. */
4998 napi_complete(napi);
4999 schedule_work(&tp->reset_task);
5000 return work_done;
5001}
5002
5003static int tg3_poll(struct napi_struct *napi, int budget)
5004{
5005 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5006 struct tg3 *tp = tnapi->tp;
5007 int work_done = 0;
5008 struct tg3_hw_status *sblk = tnapi->hw_status;
5009
5010 while (1) {
5011 tg3_poll_link(tp);
5012
5013 work_done = tg3_poll_work(tnapi, work_done, budget);
5014
5015 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5016 goto tx_recovery;
5017
5018 if (unlikely(work_done >= budget))
5019 break;
5020
5021 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5022 /* tp->last_tag is used in tg3_int_reenable() below
5023 * to tell the hw how much work has been processed,
5024 * so we must read it before checking for more work.
5025 */
5026 tnapi->last_tag = sblk->status_tag;
5027 tnapi->last_irq_tag = tnapi->last_tag;
5028 rmb();
5029 } else
5030 sblk->status &= ~SD_STATUS_UPDATED;
5031
5032 if (likely(!tg3_has_work(tnapi))) {
5033 napi_complete(napi);
5034 tg3_int_reenable(tnapi);
5035 break;
5036 }
5037 }
5038
5039 return work_done;
5040
5041tx_recovery:
5042 /* work_done is guaranteed to be less than budget. */
5043 napi_complete(napi);
5044 schedule_work(&tp->reset_task);
5045 return work_done;
5046}
5047
5048static void tg3_irq_quiesce(struct tg3 *tp)
5049{
5050 int i;
5051
5052 BUG_ON(tp->irq_sync);
5053
5054 tp->irq_sync = 1;
5055 smp_mb();
5056
5057 for (i = 0; i < tp->irq_cnt; i++)
5058 synchronize_irq(tp->napi[i].irq_vec);
5059}
5060
5061static inline int tg3_irq_sync(struct tg3 *tp)
5062{
5063 return tp->irq_sync;
5064}
5065
5066/* Fully shutdown all tg3 driver activity elsewhere in the system.
5067 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5068 * with as well. Most of the time, this is not necessary except when
5069 * shutting down the device.
5070 */
5071static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5072{
5073 spin_lock_bh(&tp->lock);
5074 if (irq_sync)
5075 tg3_irq_quiesce(tp);
5076}
5077
5078static inline void tg3_full_unlock(struct tg3 *tp)
5079{
5080 spin_unlock_bh(&tp->lock);
5081}
5082
5083/* One-shot MSI handler - Chip automatically disables interrupt
5084 * after sending MSI so driver doesn't have to do it.
5085 */
5086static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5087{
5088 struct tg3_napi *tnapi = dev_id;
5089 struct tg3 *tp = tnapi->tp;
5090
5091 prefetch(tnapi->hw_status);
5092 if (tnapi->rx_rcb)
5093 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5094
5095 if (likely(!tg3_irq_sync(tp)))
5096 napi_schedule(&tnapi->napi);
5097
5098 return IRQ_HANDLED;
5099}
5100
5101/* MSI ISR - No need to check for interrupt sharing and no need to
5102 * flush status block and interrupt mailbox. PCI ordering rules
5103 * guarantee that MSI will arrive after the status block.
5104 */
5105static irqreturn_t tg3_msi(int irq, void *dev_id)
5106{
5107 struct tg3_napi *tnapi = dev_id;
5108 struct tg3 *tp = tnapi->tp;
5109
5110 prefetch(tnapi->hw_status);
5111 if (tnapi->rx_rcb)
5112 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5113 /*
5114 * Writing any value to intr-mbox-0 clears PCI INTA# and
5115 * chip-internal interrupt pending events.
5116 * Writing non-zero to intr-mbox-0 additional tells the
5117 * NIC to stop sending us irqs, engaging "in-intr-handler"
5118 * event coalescing.
5119 */
5120 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5121 if (likely(!tg3_irq_sync(tp)))
5122 napi_schedule(&tnapi->napi);
5123
5124 return IRQ_RETVAL(1);
5125}
5126
5127static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5128{
5129 struct tg3_napi *tnapi = dev_id;
5130 struct tg3 *tp = tnapi->tp;
5131 struct tg3_hw_status *sblk = tnapi->hw_status;
5132 unsigned int handled = 1;
5133
5134 /* In INTx mode, it is possible for the interrupt to arrive at
5135 * the CPU before the status block posted prior to the interrupt.
5136 * Reading the PCI State register will confirm whether the
5137 * interrupt is ours and will flush the status block.
5138 */
5139 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5140 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5141 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5142 handled = 0;
5143 goto out;
5144 }
5145 }
5146
5147 /*
5148 * Writing any value to intr-mbox-0 clears PCI INTA# and
5149 * chip-internal interrupt pending events.
5150 * Writing non-zero to intr-mbox-0 additional tells the
5151 * NIC to stop sending us irqs, engaging "in-intr-handler"
5152 * event coalescing.
5153 *
5154 * Flush the mailbox to de-assert the IRQ immediately to prevent
5155 * spurious interrupts. The flush impacts performance but
5156 * excessive spurious interrupts can be worse in some cases.
5157 */
5158 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5159 if (tg3_irq_sync(tp))
5160 goto out;
5161 sblk->status &= ~SD_STATUS_UPDATED;
5162 if (likely(tg3_has_work(tnapi))) {
5163 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5164 napi_schedule(&tnapi->napi);
5165 } else {
5166 /* No work, shared interrupt perhaps? re-enable
5167 * interrupts, and flush that PCI write
5168 */
5169 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5170 0x00000000);
5171 }
5172out:
5173 return IRQ_RETVAL(handled);
5174}
5175
5176static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5177{
5178 struct tg3_napi *tnapi = dev_id;
5179 struct tg3 *tp = tnapi->tp;
5180 struct tg3_hw_status *sblk = tnapi->hw_status;
5181 unsigned int handled = 1;
5182
5183 /* In INTx mode, it is possible for the interrupt to arrive at
5184 * the CPU before the status block posted prior to the interrupt.
5185 * Reading the PCI State register will confirm whether the
5186 * interrupt is ours and will flush the status block.
5187 */
5188 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5189 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5190 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5191 handled = 0;
5192 goto out;
5193 }
5194 }
5195
5196 /*
5197 * writing any value to intr-mbox-0 clears PCI INTA# and
5198 * chip-internal interrupt pending events.
5199 * writing non-zero to intr-mbox-0 additional tells the
5200 * NIC to stop sending us irqs, engaging "in-intr-handler"
5201 * event coalescing.
5202 *
5203 * Flush the mailbox to de-assert the IRQ immediately to prevent
5204 * spurious interrupts. The flush impacts performance but
5205 * excessive spurious interrupts can be worse in some cases.
5206 */
5207 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5208
5209 /*
5210 * In a shared interrupt configuration, sometimes other devices'
5211 * interrupts will scream. We record the current status tag here
5212 * so that the above check can report that the screaming interrupts
5213 * are unhandled. Eventually they will be silenced.
5214 */
5215 tnapi->last_irq_tag = sblk->status_tag;
5216
5217 if (tg3_irq_sync(tp))
5218 goto out;
5219
5220 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5221
5222 napi_schedule(&tnapi->napi);
5223
5224out:
5225 return IRQ_RETVAL(handled);
5226}
5227
5228/* ISR for interrupt test */
5229static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5230{
5231 struct tg3_napi *tnapi = dev_id;
5232 struct tg3 *tp = tnapi->tp;
5233 struct tg3_hw_status *sblk = tnapi->hw_status;
5234
5235 if ((sblk->status & SD_STATUS_UPDATED) ||
5236 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5237 tg3_disable_ints(tp);
5238 return IRQ_RETVAL(1);
5239 }
5240 return IRQ_RETVAL(0);
5241}
5242
5243static int tg3_init_hw(struct tg3 *, int);
5244static int tg3_halt(struct tg3 *, int, int);
5245
5246/* Restart hardware after configuration changes, self-test, etc.
5247 * Invoked with tp->lock held.
5248 */
5249static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5250 __releases(tp->lock)
5251 __acquires(tp->lock)
5252{
5253 int err;
5254
5255 err = tg3_init_hw(tp, reset_phy);
5256 if (err) {
5257 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5258 "aborting.\n", tp->dev->name);
5259 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5260 tg3_full_unlock(tp);
5261 del_timer_sync(&tp->timer);
5262 tp->irq_sync = 0;
5263 tg3_napi_enable(tp);
5264 dev_close(tp->dev);
5265 tg3_full_lock(tp, 0);
5266 }
5267 return err;
5268}
5269
5270#ifdef CONFIG_NET_POLL_CONTROLLER
5271static void tg3_poll_controller(struct net_device *dev)
5272{
5273 int i;
5274 struct tg3 *tp = netdev_priv(dev);
5275
5276 for (i = 0; i < tp->irq_cnt; i++)
5277 tg3_interrupt(tp->napi[i].irq_vec, dev);
5278}
5279#endif
5280
5281static void tg3_reset_task(struct work_struct *work)
5282{
5283 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5284 int err;
5285 unsigned int restart_timer;
5286
5287 tg3_full_lock(tp, 0);
5288
5289 if (!netif_running(tp->dev)) {
5290 tg3_full_unlock(tp);
5291 return;
5292 }
5293
5294 tg3_full_unlock(tp);
5295
5296 tg3_phy_stop(tp);
5297
5298 tg3_netif_stop(tp);
5299
5300 tg3_full_lock(tp, 1);
5301
5302 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5303 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5304
5305 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5306 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5307 tp->write32_rx_mbox = tg3_write_flush_reg32;
5308 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5309 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5310 }
5311
5312 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5313 err = tg3_init_hw(tp, 1);
5314 if (err)
5315 goto out;
5316
5317 tg3_netif_start(tp);
5318
5319 if (restart_timer)
5320 mod_timer(&tp->timer, jiffies + 1);
5321
5322out:
5323 tg3_full_unlock(tp);
5324
5325 if (!err)
5326 tg3_phy_start(tp);
5327}
5328
5329static void tg3_dump_short_state(struct tg3 *tp)
5330{
5331 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5332 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5333 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5334 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5335}
5336
5337static void tg3_tx_timeout(struct net_device *dev)
5338{
5339 struct tg3 *tp = netdev_priv(dev);
5340
5341 if (netif_msg_tx_err(tp)) {
5342 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5343 dev->name);
5344 tg3_dump_short_state(tp);
5345 }
5346
5347 schedule_work(&tp->reset_task);
5348}
5349
5350/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5351static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5352{
5353 u32 base = (u32) mapping & 0xffffffff;
5354
5355 return ((base > 0xffffdcc0) &&
5356 (base + len + 8 < base));
5357}
5358
5359/* Test for DMA addresses > 40-bit */
5360static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5361 int len)
5362{
5363#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5364 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5365 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5366 return 0;
5367#else
5368 return 0;
5369#endif
5370}
5371
5372static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5373
5374/* Workaround 4GB and 40-bit hardware DMA bugs. */
5375static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5376 struct sk_buff *skb, u32 last_plus_one,
5377 u32 *start, u32 base_flags, u32 mss)
5378{
5379 struct tg3 *tp = tnapi->tp;
5380 struct sk_buff *new_skb;
5381 dma_addr_t new_addr = 0;
5382 u32 entry = *start;
5383 int i, ret = 0;
5384
5385 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5386 new_skb = skb_copy(skb, GFP_ATOMIC);
5387 else {
5388 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5389
5390 new_skb = skb_copy_expand(skb,
5391 skb_headroom(skb) + more_headroom,
5392 skb_tailroom(skb), GFP_ATOMIC);
5393 }
5394
5395 if (!new_skb) {
5396 ret = -1;
5397 } else {
5398 /* New SKB is guaranteed to be linear. */
5399 entry = *start;
5400 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5401 PCI_DMA_TODEVICE);
5402 /* Make sure the mapping succeeded */
5403 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5404 ret = -1;
5405 dev_kfree_skb(new_skb);
5406 new_skb = NULL;
5407
5408 /* Make sure new skb does not cross any 4G boundaries.
5409 * Drop the packet if it does.
5410 */
5411 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5412 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5413 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5414 PCI_DMA_TODEVICE);
5415 ret = -1;
5416 dev_kfree_skb(new_skb);
5417 new_skb = NULL;
5418 } else {
5419 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5420 base_flags, 1 | (mss << 1));
5421 *start = NEXT_TX(entry);
5422 }
5423 }
5424
5425 /* Now clean up the sw ring entries. */
5426 i = 0;
5427 while (entry != last_plus_one) {
5428 int len;
5429
5430 if (i == 0)
5431 len = skb_headlen(skb);
5432 else
5433 len = skb_shinfo(skb)->frags[i-1].size;
5434
5435 pci_unmap_single(tp->pdev,
5436 pci_unmap_addr(&tnapi->tx_buffers[entry],
5437 mapping),
5438 len, PCI_DMA_TODEVICE);
5439 if (i == 0) {
5440 tnapi->tx_buffers[entry].skb = new_skb;
5441 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5442 new_addr);
5443 } else {
5444 tnapi->tx_buffers[entry].skb = NULL;
5445 }
5446 entry = NEXT_TX(entry);
5447 i++;
5448 }
5449
5450 dev_kfree_skb(skb);
5451
5452 return ret;
5453}
5454
5455static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5456 dma_addr_t mapping, int len, u32 flags,
5457 u32 mss_and_is_end)
5458{
5459 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5460 int is_end = (mss_and_is_end & 0x1);
5461 u32 mss = (mss_and_is_end >> 1);
5462 u32 vlan_tag = 0;
5463
5464 if (is_end)
5465 flags |= TXD_FLAG_END;
5466 if (flags & TXD_FLAG_VLAN) {
5467 vlan_tag = flags >> 16;
5468 flags &= 0xffff;
5469 }
5470 vlan_tag |= (mss << TXD_MSS_SHIFT);
5471
5472 txd->addr_hi = ((u64) mapping >> 32);
5473 txd->addr_lo = ((u64) mapping & 0xffffffff);
5474 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5475 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5476}
5477
5478/* hard_start_xmit for devices that don't have any bugs and
5479 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5480 */
5481static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5482 struct net_device *dev)
5483{
5484 struct tg3 *tp = netdev_priv(dev);
5485 u32 len, entry, base_flags, mss;
5486 dma_addr_t mapping;
5487 struct tg3_napi *tnapi;
5488 struct netdev_queue *txq;
5489 unsigned int i, last;
5490
5491
5492 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5493 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5494 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5495 tnapi++;
5496
5497 /* We are running in BH disabled context with netif_tx_lock
5498 * and TX reclaim runs via tp->napi.poll inside of a software
5499 * interrupt. Furthermore, IRQ processing runs lockless so we have
5500 * no IRQ context deadlocks to worry about either. Rejoice!
5501 */
5502 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5503 if (!netif_tx_queue_stopped(txq)) {
5504 netif_tx_stop_queue(txq);
5505
5506 /* This is a hard error, log it. */
5507 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5508 "queue awake!\n", dev->name);
5509 }
5510 return NETDEV_TX_BUSY;
5511 }
5512
5513 entry = tnapi->tx_prod;
5514 base_flags = 0;
5515 mss = 0;
5516 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5517 int tcp_opt_len, ip_tcp_len;
5518 u32 hdrlen;
5519
5520 if (skb_header_cloned(skb) &&
5521 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5522 dev_kfree_skb(skb);
5523 goto out_unlock;
5524 }
5525
5526 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5527 hdrlen = skb_headlen(skb) - ETH_HLEN;
5528 else {
5529 struct iphdr *iph = ip_hdr(skb);
5530
5531 tcp_opt_len = tcp_optlen(skb);
5532 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5533
5534 iph->check = 0;
5535 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5536 hdrlen = ip_tcp_len + tcp_opt_len;
5537 }
5538
5539 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5540 mss |= (hdrlen & 0xc) << 12;
5541 if (hdrlen & 0x10)
5542 base_flags |= 0x00000010;
5543 base_flags |= (hdrlen & 0x3e0) << 5;
5544 } else
5545 mss |= hdrlen << 9;
5546
5547 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5548 TXD_FLAG_CPU_POST_DMA);
5549
5550 tcp_hdr(skb)->check = 0;
5551
5552 }
5553 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5554 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5555#if TG3_VLAN_TAG_USED
5556 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5557 base_flags |= (TXD_FLAG_VLAN |
5558 (vlan_tx_tag_get(skb) << 16));
5559#endif
5560
5561 len = skb_headlen(skb);
5562
5563 /* Queue skb data, a.k.a. the main skb fragment. */
5564 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5565 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5566 dev_kfree_skb(skb);
5567 goto out_unlock;
5568 }
5569
5570 tnapi->tx_buffers[entry].skb = skb;
5571 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5572
5573 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5574 !mss && skb->len > ETH_DATA_LEN)
5575 base_flags |= TXD_FLAG_JMB_PKT;
5576
5577 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5578 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5579
5580 entry = NEXT_TX(entry);
5581
5582 /* Now loop through additional data fragments, and queue them. */
5583 if (skb_shinfo(skb)->nr_frags > 0) {
5584 last = skb_shinfo(skb)->nr_frags - 1;
5585 for (i = 0; i <= last; i++) {
5586 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5587
5588 len = frag->size;
5589 mapping = pci_map_page(tp->pdev,
5590 frag->page,
5591 frag->page_offset,
5592 len, PCI_DMA_TODEVICE);
5593 if (pci_dma_mapping_error(tp->pdev, mapping))
5594 goto dma_error;
5595
5596 tnapi->tx_buffers[entry].skb = NULL;
5597 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5598 mapping);
5599
5600 tg3_set_txd(tnapi, entry, mapping, len,
5601 base_flags, (i == last) | (mss << 1));
5602
5603 entry = NEXT_TX(entry);
5604 }
5605 }
5606
5607 /* Packets are ready, update Tx producer idx local and on card. */
5608 tw32_tx_mbox(tnapi->prodmbox, entry);
5609
5610 tnapi->tx_prod = entry;
5611 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5612 netif_tx_stop_queue(txq);
5613 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5614 netif_tx_wake_queue(txq);
5615 }
5616
5617out_unlock:
5618 mmiowb();
5619
5620 return NETDEV_TX_OK;
5621
5622dma_error:
5623 last = i;
5624 entry = tnapi->tx_prod;
5625 tnapi->tx_buffers[entry].skb = NULL;
5626 pci_unmap_single(tp->pdev,
5627 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5628 skb_headlen(skb),
5629 PCI_DMA_TODEVICE);
5630 for (i = 0; i <= last; i++) {
5631 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5632 entry = NEXT_TX(entry);
5633
5634 pci_unmap_page(tp->pdev,
5635 pci_unmap_addr(&tnapi->tx_buffers[entry],
5636 mapping),
5637 frag->size, PCI_DMA_TODEVICE);
5638 }
5639
5640 dev_kfree_skb(skb);
5641 return NETDEV_TX_OK;
5642}
5643
5644static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5645 struct net_device *);
5646
5647/* Use GSO to workaround a rare TSO bug that may be triggered when the
5648 * TSO header is greater than 80 bytes.
5649 */
5650static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5651{
5652 struct sk_buff *segs, *nskb;
5653 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5654
5655 /* Estimate the number of fragments in the worst case */
5656 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5657 netif_stop_queue(tp->dev);
5658 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5659 return NETDEV_TX_BUSY;
5660
5661 netif_wake_queue(tp->dev);
5662 }
5663
5664 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5665 if (IS_ERR(segs))
5666 goto tg3_tso_bug_end;
5667
5668 do {
5669 nskb = segs;
5670 segs = segs->next;
5671 nskb->next = NULL;
5672 tg3_start_xmit_dma_bug(nskb, tp->dev);
5673 } while (segs);
5674
5675tg3_tso_bug_end:
5676 dev_kfree_skb(skb);
5677
5678 return NETDEV_TX_OK;
5679}
5680
5681/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5682 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5683 */
5684static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5685 struct net_device *dev)
5686{
5687 struct tg3 *tp = netdev_priv(dev);
5688 u32 len, entry, base_flags, mss;
5689 int would_hit_hwbug;
5690 dma_addr_t mapping;
5691 struct tg3_napi *tnapi;
5692 struct netdev_queue *txq;
5693 unsigned int i, last;
5694
5695
5696 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5697 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5698 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5699 tnapi++;
5700
5701 /* We are running in BH disabled context with netif_tx_lock
5702 * and TX reclaim runs via tp->napi.poll inside of a software
5703 * interrupt. Furthermore, IRQ processing runs lockless so we have
5704 * no IRQ context deadlocks to worry about either. Rejoice!
5705 */
5706 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5707 if (!netif_tx_queue_stopped(txq)) {
5708 netif_tx_stop_queue(txq);
5709
5710 /* This is a hard error, log it. */
5711 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5712 "queue awake!\n", dev->name);
5713 }
5714 return NETDEV_TX_BUSY;
5715 }
5716
5717 entry = tnapi->tx_prod;
5718 base_flags = 0;
5719 if (skb->ip_summed == CHECKSUM_PARTIAL)
5720 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5721
5722 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5723 struct iphdr *iph;
5724 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5725
5726 if (skb_header_cloned(skb) &&
5727 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5728 dev_kfree_skb(skb);
5729 goto out_unlock;
5730 }
5731
5732 tcp_opt_len = tcp_optlen(skb);
5733 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5734
5735 hdr_len = ip_tcp_len + tcp_opt_len;
5736 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5737 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5738 return (tg3_tso_bug(tp, skb));
5739
5740 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5741 TXD_FLAG_CPU_POST_DMA);
5742
5743 iph = ip_hdr(skb);
5744 iph->check = 0;
5745 iph->tot_len = htons(mss + hdr_len);
5746 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5747 tcp_hdr(skb)->check = 0;
5748 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5749 } else
5750 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5751 iph->daddr, 0,
5752 IPPROTO_TCP,
5753 0);
5754
5755 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5756 mss |= (hdr_len & 0xc) << 12;
5757 if (hdr_len & 0x10)
5758 base_flags |= 0x00000010;
5759 base_flags |= (hdr_len & 0x3e0) << 5;
5760 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5761 mss |= hdr_len << 9;
5762 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5763 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5764 if (tcp_opt_len || iph->ihl > 5) {
5765 int tsflags;
5766
5767 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5768 mss |= (tsflags << 11);
5769 }
5770 } else {
5771 if (tcp_opt_len || iph->ihl > 5) {
5772 int tsflags;
5773
5774 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5775 base_flags |= tsflags << 12;
5776 }
5777 }
5778 }
5779#if TG3_VLAN_TAG_USED
5780 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5781 base_flags |= (TXD_FLAG_VLAN |
5782 (vlan_tx_tag_get(skb) << 16));
5783#endif
5784
5785 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5786 !mss && skb->len > ETH_DATA_LEN)
5787 base_flags |= TXD_FLAG_JMB_PKT;
5788
5789 len = skb_headlen(skb);
5790
5791 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5792 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5793 dev_kfree_skb(skb);
5794 goto out_unlock;
5795 }
5796
5797 tnapi->tx_buffers[entry].skb = skb;
5798 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5799
5800 would_hit_hwbug = 0;
5801
5802 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5803 would_hit_hwbug = 1;
5804
5805 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5806 tg3_4g_overflow_test(mapping, len))
5807 would_hit_hwbug = 1;
5808
5809 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5810 tg3_40bit_overflow_test(tp, mapping, len))
5811 would_hit_hwbug = 1;
5812
5813 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5814 would_hit_hwbug = 1;
5815
5816 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5817 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5818
5819 entry = NEXT_TX(entry);
5820
5821 /* Now loop through additional data fragments, and queue them. */
5822 if (skb_shinfo(skb)->nr_frags > 0) {
5823 last = skb_shinfo(skb)->nr_frags - 1;
5824 for (i = 0; i <= last; i++) {
5825 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5826
5827 len = frag->size;
5828 mapping = pci_map_page(tp->pdev,
5829 frag->page,
5830 frag->page_offset,
5831 len, PCI_DMA_TODEVICE);
5832
5833 tnapi->tx_buffers[entry].skb = NULL;
5834 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5835 mapping);
5836 if (pci_dma_mapping_error(tp->pdev, mapping))
5837 goto dma_error;
5838
5839 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5840 len <= 8)
5841 would_hit_hwbug = 1;
5842
5843 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5844 tg3_4g_overflow_test(mapping, len))
5845 would_hit_hwbug = 1;
5846
5847 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5848 tg3_40bit_overflow_test(tp, mapping, len))
5849 would_hit_hwbug = 1;
5850
5851 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5852 tg3_set_txd(tnapi, entry, mapping, len,
5853 base_flags, (i == last)|(mss << 1));
5854 else
5855 tg3_set_txd(tnapi, entry, mapping, len,
5856 base_flags, (i == last));
5857
5858 entry = NEXT_TX(entry);
5859 }
5860 }
5861
5862 if (would_hit_hwbug) {
5863 u32 last_plus_one = entry;
5864 u32 start;
5865
5866 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5867 start &= (TG3_TX_RING_SIZE - 1);
5868
5869 /* If the workaround fails due to memory/mapping
5870 * failure, silently drop this packet.
5871 */
5872 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5873 &start, base_flags, mss))
5874 goto out_unlock;
5875
5876 entry = start;
5877 }
5878
5879 /* Packets are ready, update Tx producer idx local and on card. */
5880 tw32_tx_mbox(tnapi->prodmbox, entry);
5881
5882 tnapi->tx_prod = entry;
5883 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5884 netif_tx_stop_queue(txq);
5885 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5886 netif_tx_wake_queue(txq);
5887 }
5888
5889out_unlock:
5890 mmiowb();
5891
5892 return NETDEV_TX_OK;
5893
5894dma_error:
5895 last = i;
5896 entry = tnapi->tx_prod;
5897 tnapi->tx_buffers[entry].skb = NULL;
5898 pci_unmap_single(tp->pdev,
5899 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5900 skb_headlen(skb),
5901 PCI_DMA_TODEVICE);
5902 for (i = 0; i <= last; i++) {
5903 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5904 entry = NEXT_TX(entry);
5905
5906 pci_unmap_page(tp->pdev,
5907 pci_unmap_addr(&tnapi->tx_buffers[entry],
5908 mapping),
5909 frag->size, PCI_DMA_TODEVICE);
5910 }
5911
5912 dev_kfree_skb(skb);
5913 return NETDEV_TX_OK;
5914}
5915
5916static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5917 int new_mtu)
5918{
5919 dev->mtu = new_mtu;
5920
5921 if (new_mtu > ETH_DATA_LEN) {
5922 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5923 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5924 ethtool_op_set_tso(dev, 0);
5925 }
5926 else
5927 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5928 } else {
5929 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5930 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5931 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5932 }
5933}
5934
5935static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5936{
5937 struct tg3 *tp = netdev_priv(dev);
5938 int err;
5939
5940 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5941 return -EINVAL;
5942
5943 if (!netif_running(dev)) {
5944 /* We'll just catch it later when the
5945 * device is up'd.
5946 */
5947 tg3_set_mtu(dev, tp, new_mtu);
5948 return 0;
5949 }
5950
5951 tg3_phy_stop(tp);
5952
5953 tg3_netif_stop(tp);
5954
5955 tg3_full_lock(tp, 1);
5956
5957 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5958
5959 tg3_set_mtu(dev, tp, new_mtu);
5960
5961 err = tg3_restart_hw(tp, 0);
5962
5963 if (!err)
5964 tg3_netif_start(tp);
5965
5966 tg3_full_unlock(tp);
5967
5968 if (!err)
5969 tg3_phy_start(tp);
5970
5971 return err;
5972}
5973
5974static void tg3_rx_prodring_free(struct tg3 *tp,
5975 struct tg3_rx_prodring_set *tpr)
5976{
5977 int i;
5978
5979 if (tpr != &tp->prodring[0]) {
5980 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5981 i = (i + 1) % TG3_RX_RING_SIZE)
5982 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5983 tp->rx_pkt_map_sz);
5984
5985 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5986 for (i = tpr->rx_jmb_cons_idx;
5987 i != tpr->rx_jmb_prod_idx;
5988 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5989 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5990 TG3_RX_JMB_MAP_SZ);
5991 }
5992 }
5993
5994 return;
5995 }
5996
5997 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5998 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5999 tp->rx_pkt_map_sz);
6000
6001 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6002 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6003 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6004 TG3_RX_JMB_MAP_SZ);
6005 }
6006}
6007
6008/* Initialize tx/rx rings for packet processing.
6009 *
6010 * The chip has been shut down and the driver detached from
6011 * the networking, so no interrupts or new tx packets will
6012 * end up in the driver. tp->{tx,}lock are held and thus
6013 * we may not sleep.
6014 */
6015static int tg3_rx_prodring_alloc(struct tg3 *tp,
6016 struct tg3_rx_prodring_set *tpr)
6017{
6018 u32 i, rx_pkt_dma_sz;
6019
6020 tpr->rx_std_cons_idx = 0;
6021 tpr->rx_std_prod_idx = 0;
6022 tpr->rx_jmb_cons_idx = 0;
6023 tpr->rx_jmb_prod_idx = 0;
6024
6025 if (tpr != &tp->prodring[0]) {
6026 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6027 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6028 memset(&tpr->rx_jmb_buffers[0], 0,
6029 TG3_RX_JMB_BUFF_RING_SIZE);
6030 goto done;
6031 }
6032
6033 /* Zero out all descriptors. */
6034 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6035
6036 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6037 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6038 tp->dev->mtu > ETH_DATA_LEN)
6039 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6040 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6041
6042 /* Initialize invariants of the rings, we only set this
6043 * stuff once. This works because the card does not
6044 * write into the rx buffer posting rings.
6045 */
6046 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6047 struct tg3_rx_buffer_desc *rxd;
6048
6049 rxd = &tpr->rx_std[i];
6050 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6051 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6052 rxd->opaque = (RXD_OPAQUE_RING_STD |
6053 (i << RXD_OPAQUE_INDEX_SHIFT));
6054 }
6055
6056 /* Now allocate fresh SKBs for each rx ring. */
6057 for (i = 0; i < tp->rx_pending; i++) {
6058 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6059 printk(KERN_WARNING PFX
6060 "%s: Using a smaller RX standard ring, "
6061 "only %d out of %d buffers were allocated "
6062 "successfully.\n",
6063 tp->dev->name, i, tp->rx_pending);
6064 if (i == 0)
6065 goto initfail;
6066 tp->rx_pending = i;
6067 break;
6068 }
6069 }
6070
6071 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6072 goto done;
6073
6074 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6075
6076 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6077 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6078 struct tg3_rx_buffer_desc *rxd;
6079
6080 rxd = &tpr->rx_jmb[i].std;
6081 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6082 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6083 RXD_FLAG_JUMBO;
6084 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6085 (i << RXD_OPAQUE_INDEX_SHIFT));
6086 }
6087
6088 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6089 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6090 i) < 0) {
6091 printk(KERN_WARNING PFX
6092 "%s: Using a smaller RX jumbo ring, "
6093 "only %d out of %d buffers were "
6094 "allocated successfully.\n",
6095 tp->dev->name, i, tp->rx_jumbo_pending);
6096 if (i == 0)
6097 goto initfail;
6098 tp->rx_jumbo_pending = i;
6099 break;
6100 }
6101 }
6102 }
6103
6104done:
6105 return 0;
6106
6107initfail:
6108 tg3_rx_prodring_free(tp, tpr);
6109 return -ENOMEM;
6110}
6111
6112static void tg3_rx_prodring_fini(struct tg3 *tp,
6113 struct tg3_rx_prodring_set *tpr)
6114{
6115 kfree(tpr->rx_std_buffers);
6116 tpr->rx_std_buffers = NULL;
6117 kfree(tpr->rx_jmb_buffers);
6118 tpr->rx_jmb_buffers = NULL;
6119 if (tpr->rx_std) {
6120 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6121 tpr->rx_std, tpr->rx_std_mapping);
6122 tpr->rx_std = NULL;
6123 }
6124 if (tpr->rx_jmb) {
6125 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6126 tpr->rx_jmb, tpr->rx_jmb_mapping);
6127 tpr->rx_jmb = NULL;
6128 }
6129}
6130
6131static int tg3_rx_prodring_init(struct tg3 *tp,
6132 struct tg3_rx_prodring_set *tpr)
6133{
6134 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6135 if (!tpr->rx_std_buffers)
6136 return -ENOMEM;
6137
6138 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6139 &tpr->rx_std_mapping);
6140 if (!tpr->rx_std)
6141 goto err_out;
6142
6143 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6144 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6145 GFP_KERNEL);
6146 if (!tpr->rx_jmb_buffers)
6147 goto err_out;
6148
6149 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6150 TG3_RX_JUMBO_RING_BYTES,
6151 &tpr->rx_jmb_mapping);
6152 if (!tpr->rx_jmb)
6153 goto err_out;
6154 }
6155
6156 return 0;
6157
6158err_out:
6159 tg3_rx_prodring_fini(tp, tpr);
6160 return -ENOMEM;
6161}
6162
6163/* Free up pending packets in all rx/tx rings.
6164 *
6165 * The chip has been shut down and the driver detached from
6166 * the networking, so no interrupts or new tx packets will
6167 * end up in the driver. tp->{tx,}lock is not held and we are not
6168 * in an interrupt context and thus may sleep.
6169 */
6170static void tg3_free_rings(struct tg3 *tp)
6171{
6172 int i, j;
6173
6174 for (j = 0; j < tp->irq_cnt; j++) {
6175 struct tg3_napi *tnapi = &tp->napi[j];
6176
6177 if (!tnapi->tx_buffers)
6178 continue;
6179
6180 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6181 struct ring_info *txp;
6182 struct sk_buff *skb;
6183 unsigned int k;
6184
6185 txp = &tnapi->tx_buffers[i];
6186 skb = txp->skb;
6187
6188 if (skb == NULL) {
6189 i++;
6190 continue;
6191 }
6192
6193 pci_unmap_single(tp->pdev,
6194 pci_unmap_addr(txp, mapping),
6195 skb_headlen(skb),
6196 PCI_DMA_TODEVICE);
6197 txp->skb = NULL;
6198
6199 i++;
6200
6201 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6202 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6203 pci_unmap_page(tp->pdev,
6204 pci_unmap_addr(txp, mapping),
6205 skb_shinfo(skb)->frags[k].size,
6206 PCI_DMA_TODEVICE);
6207 i++;
6208 }
6209
6210 dev_kfree_skb_any(skb);
6211 }
6212
6213 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6214 }
6215}
6216
6217/* Initialize tx/rx rings for packet processing.
6218 *
6219 * The chip has been shut down and the driver detached from
6220 * the networking, so no interrupts or new tx packets will
6221 * end up in the driver. tp->{tx,}lock are held and thus
6222 * we may not sleep.
6223 */
6224static int tg3_init_rings(struct tg3 *tp)
6225{
6226 int i;
6227
6228 /* Free up all the SKBs. */
6229 tg3_free_rings(tp);
6230
6231 for (i = 0; i < tp->irq_cnt; i++) {
6232 struct tg3_napi *tnapi = &tp->napi[i];
6233
6234 tnapi->last_tag = 0;
6235 tnapi->last_irq_tag = 0;
6236 tnapi->hw_status->status = 0;
6237 tnapi->hw_status->status_tag = 0;
6238 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6239
6240 tnapi->tx_prod = 0;
6241 tnapi->tx_cons = 0;
6242 if (tnapi->tx_ring)
6243 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6244
6245 tnapi->rx_rcb_ptr = 0;
6246 if (tnapi->rx_rcb)
6247 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6248
6249 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6250 tg3_free_rings(tp);
6251 return -ENOMEM;
6252 }
6253 }
6254
6255 return 0;
6256}
6257
6258/*
6259 * Must not be invoked with interrupt sources disabled and
6260 * the hardware shutdown down.
6261 */
6262static void tg3_free_consistent(struct tg3 *tp)
6263{
6264 int i;
6265
6266 for (i = 0; i < tp->irq_cnt; i++) {
6267 struct tg3_napi *tnapi = &tp->napi[i];
6268
6269 if (tnapi->tx_ring) {
6270 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6271 tnapi->tx_ring, tnapi->tx_desc_mapping);
6272 tnapi->tx_ring = NULL;
6273 }
6274
6275 kfree(tnapi->tx_buffers);
6276 tnapi->tx_buffers = NULL;
6277
6278 if (tnapi->rx_rcb) {
6279 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6280 tnapi->rx_rcb,
6281 tnapi->rx_rcb_mapping);
6282 tnapi->rx_rcb = NULL;
6283 }
6284
6285 if (tnapi->hw_status) {
6286 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6287 tnapi->hw_status,
6288 tnapi->status_mapping);
6289 tnapi->hw_status = NULL;
6290 }
6291 }
6292
6293 if (tp->hw_stats) {
6294 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6295 tp->hw_stats, tp->stats_mapping);
6296 tp->hw_stats = NULL;
6297 }
6298
6299 for (i = 0; i < tp->irq_cnt; i++)
6300 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6301}
6302
6303/*
6304 * Must not be invoked with interrupt sources disabled and
6305 * the hardware shutdown down. Can sleep.
6306 */
6307static int tg3_alloc_consistent(struct tg3 *tp)
6308{
6309 int i;
6310
6311 for (i = 0; i < tp->irq_cnt; i++) {
6312 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6313 goto err_out;
6314 }
6315
6316 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6317 sizeof(struct tg3_hw_stats),
6318 &tp->stats_mapping);
6319 if (!tp->hw_stats)
6320 goto err_out;
6321
6322 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6323
6324 for (i = 0; i < tp->irq_cnt; i++) {
6325 struct tg3_napi *tnapi = &tp->napi[i];
6326 struct tg3_hw_status *sblk;
6327
6328 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6329 TG3_HW_STATUS_SIZE,
6330 &tnapi->status_mapping);
6331 if (!tnapi->hw_status)
6332 goto err_out;
6333
6334 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6335 sblk = tnapi->hw_status;
6336
6337 /* If multivector TSS is enabled, vector 0 does not handle
6338 * tx interrupts. Don't allocate any resources for it.
6339 */
6340 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6341 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6342 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6343 TG3_TX_RING_SIZE,
6344 GFP_KERNEL);
6345 if (!tnapi->tx_buffers)
6346 goto err_out;
6347
6348 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6349 TG3_TX_RING_BYTES,
6350 &tnapi->tx_desc_mapping);
6351 if (!tnapi->tx_ring)
6352 goto err_out;
6353 }
6354
6355 /*
6356 * When RSS is enabled, the status block format changes
6357 * slightly. The "rx_jumbo_consumer", "reserved",
6358 * and "rx_mini_consumer" members get mapped to the
6359 * other three rx return ring producer indexes.
6360 */
6361 switch (i) {
6362 default:
6363 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6364 break;
6365 case 2:
6366 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6367 break;
6368 case 3:
6369 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6370 break;
6371 case 4:
6372 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6373 break;
6374 }
6375
6376 tnapi->prodring = &tp->prodring[i];
6377
6378 /*
6379 * If multivector RSS is enabled, vector 0 does not handle
6380 * rx or tx interrupts. Don't allocate any resources for it.
6381 */
6382 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6383 continue;
6384
6385 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6386 TG3_RX_RCB_RING_BYTES(tp),
6387 &tnapi->rx_rcb_mapping);
6388 if (!tnapi->rx_rcb)
6389 goto err_out;
6390
6391 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6392 }
6393
6394 return 0;
6395
6396err_out:
6397 tg3_free_consistent(tp);
6398 return -ENOMEM;
6399}
6400
6401#define MAX_WAIT_CNT 1000
6402
6403/* To stop a block, clear the enable bit and poll till it
6404 * clears. tp->lock is held.
6405 */
6406static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6407{
6408 unsigned int i;
6409 u32 val;
6410
6411 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6412 switch (ofs) {
6413 case RCVLSC_MODE:
6414 case DMAC_MODE:
6415 case MBFREE_MODE:
6416 case BUFMGR_MODE:
6417 case MEMARB_MODE:
6418 /* We can't enable/disable these bits of the
6419 * 5705/5750, just say success.
6420 */
6421 return 0;
6422
6423 default:
6424 break;
6425 }
6426 }
6427
6428 val = tr32(ofs);
6429 val &= ~enable_bit;
6430 tw32_f(ofs, val);
6431
6432 for (i = 0; i < MAX_WAIT_CNT; i++) {
6433 udelay(100);
6434 val = tr32(ofs);
6435 if ((val & enable_bit) == 0)
6436 break;
6437 }
6438
6439 if (i == MAX_WAIT_CNT && !silent) {
6440 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6441 "ofs=%lx enable_bit=%x\n",
6442 ofs, enable_bit);
6443 return -ENODEV;
6444 }
6445
6446 return 0;
6447}
6448
6449/* tp->lock is held. */
6450static int tg3_abort_hw(struct tg3 *tp, int silent)
6451{
6452 int i, err;
6453
6454 tg3_disable_ints(tp);
6455
6456 tp->rx_mode &= ~RX_MODE_ENABLE;
6457 tw32_f(MAC_RX_MODE, tp->rx_mode);
6458 udelay(10);
6459
6460 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6461 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6462 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6463 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6464 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6465 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6466
6467 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6468 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6469 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6470 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6471 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6472 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6473 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6474
6475 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6476 tw32_f(MAC_MODE, tp->mac_mode);
6477 udelay(40);
6478
6479 tp->tx_mode &= ~TX_MODE_ENABLE;
6480 tw32_f(MAC_TX_MODE, tp->tx_mode);
6481
6482 for (i = 0; i < MAX_WAIT_CNT; i++) {
6483 udelay(100);
6484 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6485 break;
6486 }
6487 if (i >= MAX_WAIT_CNT) {
6488 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6489 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6490 tp->dev->name, tr32(MAC_TX_MODE));
6491 err |= -ENODEV;
6492 }
6493
6494 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6495 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6496 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6497
6498 tw32(FTQ_RESET, 0xffffffff);
6499 tw32(FTQ_RESET, 0x00000000);
6500
6501 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6502 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6503
6504 for (i = 0; i < tp->irq_cnt; i++) {
6505 struct tg3_napi *tnapi = &tp->napi[i];
6506 if (tnapi->hw_status)
6507 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6508 }
6509 if (tp->hw_stats)
6510 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6511
6512 return err;
6513}
6514
6515static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6516{
6517 int i;
6518 u32 apedata;
6519
6520 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6521 if (apedata != APE_SEG_SIG_MAGIC)
6522 return;
6523
6524 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6525 if (!(apedata & APE_FW_STATUS_READY))
6526 return;
6527
6528 /* Wait for up to 1 millisecond for APE to service previous event. */
6529 for (i = 0; i < 10; i++) {
6530 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6531 return;
6532
6533 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6534
6535 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6536 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6537 event | APE_EVENT_STATUS_EVENT_PENDING);
6538
6539 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6540
6541 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6542 break;
6543
6544 udelay(100);
6545 }
6546
6547 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6548 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6549}
6550
6551static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6552{
6553 u32 event;
6554 u32 apedata;
6555
6556 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6557 return;
6558
6559 switch (kind) {
6560 case RESET_KIND_INIT:
6561 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6562 APE_HOST_SEG_SIG_MAGIC);
6563 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6564 APE_HOST_SEG_LEN_MAGIC);
6565 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6566 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6567 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6568 APE_HOST_DRIVER_ID_MAGIC);
6569 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6570 APE_HOST_BEHAV_NO_PHYLOCK);
6571
6572 event = APE_EVENT_STATUS_STATE_START;
6573 break;
6574 case RESET_KIND_SHUTDOWN:
6575 /* With the interface we are currently using,
6576 * APE does not track driver state. Wiping
6577 * out the HOST SEGMENT SIGNATURE forces
6578 * the APE to assume OS absent status.
6579 */
6580 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6581
6582 event = APE_EVENT_STATUS_STATE_UNLOAD;
6583 break;
6584 case RESET_KIND_SUSPEND:
6585 event = APE_EVENT_STATUS_STATE_SUSPEND;
6586 break;
6587 default:
6588 return;
6589 }
6590
6591 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6592
6593 tg3_ape_send_event(tp, event);
6594}
6595
6596/* tp->lock is held. */
6597static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6598{
6599 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6600 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6601
6602 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6603 switch (kind) {
6604 case RESET_KIND_INIT:
6605 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6606 DRV_STATE_START);
6607 break;
6608
6609 case RESET_KIND_SHUTDOWN:
6610 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6611 DRV_STATE_UNLOAD);
6612 break;
6613
6614 case RESET_KIND_SUSPEND:
6615 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6616 DRV_STATE_SUSPEND);
6617 break;
6618
6619 default:
6620 break;
6621 }
6622 }
6623
6624 if (kind == RESET_KIND_INIT ||
6625 kind == RESET_KIND_SUSPEND)
6626 tg3_ape_driver_state_change(tp, kind);
6627}
6628
6629/* tp->lock is held. */
6630static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6631{
6632 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6633 switch (kind) {
6634 case RESET_KIND_INIT:
6635 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6636 DRV_STATE_START_DONE);
6637 break;
6638
6639 case RESET_KIND_SHUTDOWN:
6640 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6641 DRV_STATE_UNLOAD_DONE);
6642 break;
6643
6644 default:
6645 break;
6646 }
6647 }
6648
6649 if (kind == RESET_KIND_SHUTDOWN)
6650 tg3_ape_driver_state_change(tp, kind);
6651}
6652
6653/* tp->lock is held. */
6654static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6655{
6656 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6657 switch (kind) {
6658 case RESET_KIND_INIT:
6659 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6660 DRV_STATE_START);
6661 break;
6662
6663 case RESET_KIND_SHUTDOWN:
6664 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6665 DRV_STATE_UNLOAD);
6666 break;
6667
6668 case RESET_KIND_SUSPEND:
6669 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6670 DRV_STATE_SUSPEND);
6671 break;
6672
6673 default:
6674 break;
6675 }
6676 }
6677}
6678
6679static int tg3_poll_fw(struct tg3 *tp)
6680{
6681 int i;
6682 u32 val;
6683
6684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6685 /* Wait up to 20ms for init done. */
6686 for (i = 0; i < 200; i++) {
6687 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6688 return 0;
6689 udelay(100);
6690 }
6691 return -ENODEV;
6692 }
6693
6694 /* Wait for firmware initialization to complete. */
6695 for (i = 0; i < 100000; i++) {
6696 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6697 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6698 break;
6699 udelay(10);
6700 }
6701
6702 /* Chip might not be fitted with firmware. Some Sun onboard
6703 * parts are configured like that. So don't signal the timeout
6704 * of the above loop as an error, but do report the lack of
6705 * running firmware once.
6706 */
6707 if (i >= 100000 &&
6708 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6709 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6710
6711 printk(KERN_INFO PFX "%s: No firmware running.\n",
6712 tp->dev->name);
6713 }
6714
6715 return 0;
6716}
6717
6718/* Save PCI command register before chip reset */
6719static void tg3_save_pci_state(struct tg3 *tp)
6720{
6721 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6722}
6723
6724/* Restore PCI state after chip reset */
6725static void tg3_restore_pci_state(struct tg3 *tp)
6726{
6727 u32 val;
6728
6729 /* Re-enable indirect register accesses. */
6730 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6731 tp->misc_host_ctrl);
6732
6733 /* Set MAX PCI retry to zero. */
6734 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6735 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6736 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6737 val |= PCISTATE_RETRY_SAME_DMA;
6738 /* Allow reads and writes to the APE register and memory space. */
6739 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6740 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6741 PCISTATE_ALLOW_APE_SHMEM_WR;
6742 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6743
6744 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6745
6746 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6747 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6748 pcie_set_readrq(tp->pdev, 4096);
6749 else {
6750 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6751 tp->pci_cacheline_sz);
6752 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6753 tp->pci_lat_timer);
6754 }
6755 }
6756
6757 /* Make sure PCI-X relaxed ordering bit is clear. */
6758 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6759 u16 pcix_cmd;
6760
6761 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6762 &pcix_cmd);
6763 pcix_cmd &= ~PCI_X_CMD_ERO;
6764 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6765 pcix_cmd);
6766 }
6767
6768 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6769
6770 /* Chip reset on 5780 will reset MSI enable bit,
6771 * so need to restore it.
6772 */
6773 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6774 u16 ctrl;
6775
6776 pci_read_config_word(tp->pdev,
6777 tp->msi_cap + PCI_MSI_FLAGS,
6778 &ctrl);
6779 pci_write_config_word(tp->pdev,
6780 tp->msi_cap + PCI_MSI_FLAGS,
6781 ctrl | PCI_MSI_FLAGS_ENABLE);
6782 val = tr32(MSGINT_MODE);
6783 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6784 }
6785 }
6786}
6787
6788static void tg3_stop_fw(struct tg3 *);
6789
6790/* tp->lock is held. */
6791static int tg3_chip_reset(struct tg3 *tp)
6792{
6793 u32 val;
6794 void (*write_op)(struct tg3 *, u32, u32);
6795 int i, err;
6796
6797 tg3_nvram_lock(tp);
6798
6799 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6800
6801 /* No matching tg3_nvram_unlock() after this because
6802 * chip reset below will undo the nvram lock.
6803 */
6804 tp->nvram_lock_cnt = 0;
6805
6806 /* GRC_MISC_CFG core clock reset will clear the memory
6807 * enable bit in PCI register 4 and the MSI enable bit
6808 * on some chips, so we save relevant registers here.
6809 */
6810 tg3_save_pci_state(tp);
6811
6812 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6813 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6814 tw32(GRC_FASTBOOT_PC, 0);
6815
6816 /*
6817 * We must avoid the readl() that normally takes place.
6818 * It locks machines, causes machine checks, and other
6819 * fun things. So, temporarily disable the 5701
6820 * hardware workaround, while we do the reset.
6821 */
6822 write_op = tp->write32;
6823 if (write_op == tg3_write_flush_reg32)
6824 tp->write32 = tg3_write32;
6825
6826 /* Prevent the irq handler from reading or writing PCI registers
6827 * during chip reset when the memory enable bit in the PCI command
6828 * register may be cleared. The chip does not generate interrupt
6829 * at this time, but the irq handler may still be called due to irq
6830 * sharing or irqpoll.
6831 */
6832 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6833 for (i = 0; i < tp->irq_cnt; i++) {
6834 struct tg3_napi *tnapi = &tp->napi[i];
6835 if (tnapi->hw_status) {
6836 tnapi->hw_status->status = 0;
6837 tnapi->hw_status->status_tag = 0;
6838 }
6839 tnapi->last_tag = 0;
6840 tnapi->last_irq_tag = 0;
6841 }
6842 smp_mb();
6843
6844 for (i = 0; i < tp->irq_cnt; i++)
6845 synchronize_irq(tp->napi[i].irq_vec);
6846
6847 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6848 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6849 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6850 }
6851
6852 /* do the reset */
6853 val = GRC_MISC_CFG_CORECLK_RESET;
6854
6855 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6856 if (tr32(0x7e2c) == 0x60) {
6857 tw32(0x7e2c, 0x20);
6858 }
6859 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6860 tw32(GRC_MISC_CFG, (1 << 29));
6861 val |= (1 << 29);
6862 }
6863 }
6864
6865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6866 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6867 tw32(GRC_VCPU_EXT_CTRL,
6868 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6869 }
6870
6871 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6872 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6873 tw32(GRC_MISC_CFG, val);
6874
6875 /* restore 5701 hardware bug workaround write method */
6876 tp->write32 = write_op;
6877
6878 /* Unfortunately, we have to delay before the PCI read back.
6879 * Some 575X chips even will not respond to a PCI cfg access
6880 * when the reset command is given to the chip.
6881 *
6882 * How do these hardware designers expect things to work
6883 * properly if the PCI write is posted for a long period
6884 * of time? It is always necessary to have some method by
6885 * which a register read back can occur to push the write
6886 * out which does the reset.
6887 *
6888 * For most tg3 variants the trick below was working.
6889 * Ho hum...
6890 */
6891 udelay(120);
6892
6893 /* Flush PCI posted writes. The normal MMIO registers
6894 * are inaccessible at this time so this is the only
6895 * way to make this reliably (actually, this is no longer
6896 * the case, see above). I tried to use indirect
6897 * register read/write but this upset some 5701 variants.
6898 */
6899 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6900
6901 udelay(120);
6902
6903 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6904 u16 val16;
6905
6906 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6907 int i;
6908 u32 cfg_val;
6909
6910 /* Wait for link training to complete. */
6911 for (i = 0; i < 5000; i++)
6912 udelay(100);
6913
6914 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6915 pci_write_config_dword(tp->pdev, 0xc4,
6916 cfg_val | (1 << 15));
6917 }
6918
6919 /* Clear the "no snoop" and "relaxed ordering" bits. */
6920 pci_read_config_word(tp->pdev,
6921 tp->pcie_cap + PCI_EXP_DEVCTL,
6922 &val16);
6923 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6924 PCI_EXP_DEVCTL_NOSNOOP_EN);
6925 /*
6926 * Older PCIe devices only support the 128 byte
6927 * MPS setting. Enforce the restriction.
6928 */
6929 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6930 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6931 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6932 pci_write_config_word(tp->pdev,
6933 tp->pcie_cap + PCI_EXP_DEVCTL,
6934 val16);
6935
6936 pcie_set_readrq(tp->pdev, 4096);
6937
6938 /* Clear error status */
6939 pci_write_config_word(tp->pdev,
6940 tp->pcie_cap + PCI_EXP_DEVSTA,
6941 PCI_EXP_DEVSTA_CED |
6942 PCI_EXP_DEVSTA_NFED |
6943 PCI_EXP_DEVSTA_FED |
6944 PCI_EXP_DEVSTA_URD);
6945 }
6946
6947 tg3_restore_pci_state(tp);
6948
6949 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6950
6951 val = 0;
6952 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6953 val = tr32(MEMARB_MODE);
6954 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6955
6956 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6957 tg3_stop_fw(tp);
6958 tw32(0x5000, 0x400);
6959 }
6960
6961 tw32(GRC_MODE, tp->grc_mode);
6962
6963 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6964 val = tr32(0xc4);
6965
6966 tw32(0xc4, val | (1 << 15));
6967 }
6968
6969 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6970 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6971 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6972 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6973 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6974 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6975 }
6976
6977 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6978 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6979 tw32_f(MAC_MODE, tp->mac_mode);
6980 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6981 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6982 tw32_f(MAC_MODE, tp->mac_mode);
6983 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6984 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6985 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6986 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6987 tw32_f(MAC_MODE, tp->mac_mode);
6988 } else
6989 tw32_f(MAC_MODE, 0);
6990 udelay(40);
6991
6992 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6993
6994 err = tg3_poll_fw(tp);
6995 if (err)
6996 return err;
6997
6998 tg3_mdio_start(tp);
6999
7000 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7001 u8 phy_addr;
7002
7003 phy_addr = tp->phy_addr;
7004 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7005
7006 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7007 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7008 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7009 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7010 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7011 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7012 udelay(10);
7013
7014 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7015 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7016 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7017 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7018 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7019 udelay(10);
7020
7021 tp->phy_addr = phy_addr;
7022 }
7023
7024 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7025 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7026 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7027 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7028 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7029 val = tr32(0x7c00);
7030
7031 tw32(0x7c00, val | (1 << 25));
7032 }
7033
7034 /* Reprobe ASF enable state. */
7035 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7036 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7037 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7038 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7039 u32 nic_cfg;
7040
7041 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7042 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7043 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7044 tp->last_event_jiffies = jiffies;
7045 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7046 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7047 }
7048 }
7049
7050 return 0;
7051}
7052
7053/* tp->lock is held. */
7054static void tg3_stop_fw(struct tg3 *tp)
7055{
7056 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7057 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7058 /* Wait for RX cpu to ACK the previous event. */
7059 tg3_wait_for_event_ack(tp);
7060
7061 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7062
7063 tg3_generate_fw_event(tp);
7064
7065 /* Wait for RX cpu to ACK this event. */
7066 tg3_wait_for_event_ack(tp);
7067 }
7068}
7069
7070/* tp->lock is held. */
7071static int tg3_halt(struct tg3 *tp, int kind, int silent)
7072{
7073 int err;
7074
7075 tg3_stop_fw(tp);
7076
7077 tg3_write_sig_pre_reset(tp, kind);
7078
7079 tg3_abort_hw(tp, silent);
7080 err = tg3_chip_reset(tp);
7081
7082 __tg3_set_mac_addr(tp, 0);
7083
7084 tg3_write_sig_legacy(tp, kind);
7085 tg3_write_sig_post_reset(tp, kind);
7086
7087 if (err)
7088 return err;
7089
7090 return 0;
7091}
7092
7093#define RX_CPU_SCRATCH_BASE 0x30000
7094#define RX_CPU_SCRATCH_SIZE 0x04000
7095#define TX_CPU_SCRATCH_BASE 0x34000
7096#define TX_CPU_SCRATCH_SIZE 0x04000
7097
7098/* tp->lock is held. */
7099static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7100{
7101 int i;
7102
7103 BUG_ON(offset == TX_CPU_BASE &&
7104 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7105
7106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7107 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7108
7109 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7110 return 0;
7111 }
7112 if (offset == RX_CPU_BASE) {
7113 for (i = 0; i < 10000; i++) {
7114 tw32(offset + CPU_STATE, 0xffffffff);
7115 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7116 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7117 break;
7118 }
7119
7120 tw32(offset + CPU_STATE, 0xffffffff);
7121 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7122 udelay(10);
7123 } else {
7124 for (i = 0; i < 10000; i++) {
7125 tw32(offset + CPU_STATE, 0xffffffff);
7126 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7127 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7128 break;
7129 }
7130 }
7131
7132 if (i >= 10000) {
7133 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7134 "and %s CPU\n",
7135 tp->dev->name,
7136 (offset == RX_CPU_BASE ? "RX" : "TX"));
7137 return -ENODEV;
7138 }
7139
7140 /* Clear firmware's nvram arbitration. */
7141 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7142 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7143 return 0;
7144}
7145
7146struct fw_info {
7147 unsigned int fw_base;
7148 unsigned int fw_len;
7149 const __be32 *fw_data;
7150};
7151
7152/* tp->lock is held. */
7153static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7154 int cpu_scratch_size, struct fw_info *info)
7155{
7156 int err, lock_err, i;
7157 void (*write_op)(struct tg3 *, u32, u32);
7158
7159 if (cpu_base == TX_CPU_BASE &&
7160 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7161 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7162 "TX cpu firmware on %s which is 5705.\n",
7163 tp->dev->name);
7164 return -EINVAL;
7165 }
7166
7167 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7168 write_op = tg3_write_mem;
7169 else
7170 write_op = tg3_write_indirect_reg32;
7171
7172 /* It is possible that bootcode is still loading at this point.
7173 * Get the nvram lock first before halting the cpu.
7174 */
7175 lock_err = tg3_nvram_lock(tp);
7176 err = tg3_halt_cpu(tp, cpu_base);
7177 if (!lock_err)
7178 tg3_nvram_unlock(tp);
7179 if (err)
7180 goto out;
7181
7182 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7183 write_op(tp, cpu_scratch_base + i, 0);
7184 tw32(cpu_base + CPU_STATE, 0xffffffff);
7185 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7186 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7187 write_op(tp, (cpu_scratch_base +
7188 (info->fw_base & 0xffff) +
7189 (i * sizeof(u32))),
7190 be32_to_cpu(info->fw_data[i]));
7191
7192 err = 0;
7193
7194out:
7195 return err;
7196}
7197
7198/* tp->lock is held. */
7199static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7200{
7201 struct fw_info info;
7202 const __be32 *fw_data;
7203 int err, i;
7204
7205 fw_data = (void *)tp->fw->data;
7206
7207 /* Firmware blob starts with version numbers, followed by
7208 start address and length. We are setting complete length.
7209 length = end_address_of_bss - start_address_of_text.
7210 Remainder is the blob to be loaded contiguously
7211 from start address. */
7212
7213 info.fw_base = be32_to_cpu(fw_data[1]);
7214 info.fw_len = tp->fw->size - 12;
7215 info.fw_data = &fw_data[3];
7216
7217 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7218 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7219 &info);
7220 if (err)
7221 return err;
7222
7223 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7224 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7225 &info);
7226 if (err)
7227 return err;
7228
7229 /* Now startup only the RX cpu. */
7230 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7231 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7232
7233 for (i = 0; i < 5; i++) {
7234 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7235 break;
7236 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7237 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7238 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7239 udelay(1000);
7240 }
7241 if (i >= 5) {
7242 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7243 "to set RX CPU PC, is %08x should be %08x\n",
7244 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7245 info.fw_base);
7246 return -ENODEV;
7247 }
7248 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7249 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7250
7251 return 0;
7252}
7253
7254/* 5705 needs a special version of the TSO firmware. */
7255
7256/* tp->lock is held. */
7257static int tg3_load_tso_firmware(struct tg3 *tp)
7258{
7259 struct fw_info info;
7260 const __be32 *fw_data;
7261 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7262 int err, i;
7263
7264 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7265 return 0;
7266
7267 fw_data = (void *)tp->fw->data;
7268
7269 /* Firmware blob starts with version numbers, followed by
7270 start address and length. We are setting complete length.
7271 length = end_address_of_bss - start_address_of_text.
7272 Remainder is the blob to be loaded contiguously
7273 from start address. */
7274
7275 info.fw_base = be32_to_cpu(fw_data[1]);
7276 cpu_scratch_size = tp->fw_len;
7277 info.fw_len = tp->fw->size - 12;
7278 info.fw_data = &fw_data[3];
7279
7280 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7281 cpu_base = RX_CPU_BASE;
7282 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7283 } else {
7284 cpu_base = TX_CPU_BASE;
7285 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7286 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7287 }
7288
7289 err = tg3_load_firmware_cpu(tp, cpu_base,
7290 cpu_scratch_base, cpu_scratch_size,
7291 &info);
7292 if (err)
7293 return err;
7294
7295 /* Now startup the cpu. */
7296 tw32(cpu_base + CPU_STATE, 0xffffffff);
7297 tw32_f(cpu_base + CPU_PC, info.fw_base);
7298
7299 for (i = 0; i < 5; i++) {
7300 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7301 break;
7302 tw32(cpu_base + CPU_STATE, 0xffffffff);
7303 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7304 tw32_f(cpu_base + CPU_PC, info.fw_base);
7305 udelay(1000);
7306 }
7307 if (i >= 5) {
7308 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7309 "to set CPU PC, is %08x should be %08x\n",
7310 tp->dev->name, tr32(cpu_base + CPU_PC),
7311 info.fw_base);
7312 return -ENODEV;
7313 }
7314 tw32(cpu_base + CPU_STATE, 0xffffffff);
7315 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7316 return 0;
7317}
7318
7319
7320static int tg3_set_mac_addr(struct net_device *dev, void *p)
7321{
7322 struct tg3 *tp = netdev_priv(dev);
7323 struct sockaddr *addr = p;
7324 int err = 0, skip_mac_1 = 0;
7325
7326 if (!is_valid_ether_addr(addr->sa_data))
7327 return -EINVAL;
7328
7329 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7330
7331 if (!netif_running(dev))
7332 return 0;
7333
7334 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7335 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7336
7337 addr0_high = tr32(MAC_ADDR_0_HIGH);
7338 addr0_low = tr32(MAC_ADDR_0_LOW);
7339 addr1_high = tr32(MAC_ADDR_1_HIGH);
7340 addr1_low = tr32(MAC_ADDR_1_LOW);
7341
7342 /* Skip MAC addr 1 if ASF is using it. */
7343 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7344 !(addr1_high == 0 && addr1_low == 0))
7345 skip_mac_1 = 1;
7346 }
7347 spin_lock_bh(&tp->lock);
7348 __tg3_set_mac_addr(tp, skip_mac_1);
7349 spin_unlock_bh(&tp->lock);
7350
7351 return err;
7352}
7353
7354/* tp->lock is held. */
7355static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7356 dma_addr_t mapping, u32 maxlen_flags,
7357 u32 nic_addr)
7358{
7359 tg3_write_mem(tp,
7360 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7361 ((u64) mapping >> 32));
7362 tg3_write_mem(tp,
7363 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7364 ((u64) mapping & 0xffffffff));
7365 tg3_write_mem(tp,
7366 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7367 maxlen_flags);
7368
7369 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7370 tg3_write_mem(tp,
7371 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7372 nic_addr);
7373}
7374
7375static void __tg3_set_rx_mode(struct net_device *);
7376static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7377{
7378 int i;
7379
7380 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7381 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7382 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7383 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7384 } else {
7385 tw32(HOSTCC_TXCOL_TICKS, 0);
7386 tw32(HOSTCC_TXMAX_FRAMES, 0);
7387 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7388 }
7389
7390 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7391 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7392 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7393 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7394 } else {
7395 tw32(HOSTCC_RXCOL_TICKS, 0);
7396 tw32(HOSTCC_RXMAX_FRAMES, 0);
7397 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7398 }
7399
7400 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7401 u32 val = ec->stats_block_coalesce_usecs;
7402
7403 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7404 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7405
7406 if (!netif_carrier_ok(tp->dev))
7407 val = 0;
7408
7409 tw32(HOSTCC_STAT_COAL_TICKS, val);
7410 }
7411
7412 for (i = 0; i < tp->irq_cnt - 1; i++) {
7413 u32 reg;
7414
7415 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7416 tw32(reg, ec->rx_coalesce_usecs);
7417 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7418 tw32(reg, ec->rx_max_coalesced_frames);
7419 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7420 tw32(reg, ec->rx_max_coalesced_frames_irq);
7421
7422 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7423 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7424 tw32(reg, ec->tx_coalesce_usecs);
7425 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7426 tw32(reg, ec->tx_max_coalesced_frames);
7427 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7428 tw32(reg, ec->tx_max_coalesced_frames_irq);
7429 }
7430 }
7431
7432 for (; i < tp->irq_max - 1; i++) {
7433 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7434 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7435 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7436
7437 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7438 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7439 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7440 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7441 }
7442 }
7443}
7444
7445/* tp->lock is held. */
7446static void tg3_rings_reset(struct tg3 *tp)
7447{
7448 int i;
7449 u32 stblk, txrcb, rxrcb, limit;
7450 struct tg3_napi *tnapi = &tp->napi[0];
7451
7452 /* Disable all transmit rings but the first. */
7453 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7454 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7455 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7456 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7457 else
7458 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7459
7460 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7461 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7462 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7463 BDINFO_FLAGS_DISABLED);
7464
7465
7466 /* Disable all receive return rings but the first. */
7467 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7468 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7469 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7470 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7471 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7472 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7473 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7474 else
7475 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7476
7477 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7478 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7479 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7480 BDINFO_FLAGS_DISABLED);
7481
7482 /* Disable interrupts */
7483 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7484
7485 /* Zero mailbox registers. */
7486 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7487 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7488 tp->napi[i].tx_prod = 0;
7489 tp->napi[i].tx_cons = 0;
7490 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7491 tw32_mailbox(tp->napi[i].prodmbox, 0);
7492 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7493 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7494 }
7495 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7496 tw32_mailbox(tp->napi[0].prodmbox, 0);
7497 } else {
7498 tp->napi[0].tx_prod = 0;
7499 tp->napi[0].tx_cons = 0;
7500 tw32_mailbox(tp->napi[0].prodmbox, 0);
7501 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7502 }
7503
7504 /* Make sure the NIC-based send BD rings are disabled. */
7505 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7506 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7507 for (i = 0; i < 16; i++)
7508 tw32_tx_mbox(mbox + i * 8, 0);
7509 }
7510
7511 txrcb = NIC_SRAM_SEND_RCB;
7512 rxrcb = NIC_SRAM_RCV_RET_RCB;
7513
7514 /* Clear status block in ram. */
7515 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7516
7517 /* Set status block DMA address */
7518 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7519 ((u64) tnapi->status_mapping >> 32));
7520 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7521 ((u64) tnapi->status_mapping & 0xffffffff));
7522
7523 if (tnapi->tx_ring) {
7524 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7525 (TG3_TX_RING_SIZE <<
7526 BDINFO_FLAGS_MAXLEN_SHIFT),
7527 NIC_SRAM_TX_BUFFER_DESC);
7528 txrcb += TG3_BDINFO_SIZE;
7529 }
7530
7531 if (tnapi->rx_rcb) {
7532 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7533 (TG3_RX_RCB_RING_SIZE(tp) <<
7534 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7535 rxrcb += TG3_BDINFO_SIZE;
7536 }
7537
7538 stblk = HOSTCC_STATBLCK_RING1;
7539
7540 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7541 u64 mapping = (u64)tnapi->status_mapping;
7542 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7543 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7544
7545 /* Clear status block in ram. */
7546 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7547
7548 if (tnapi->tx_ring) {
7549 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7550 (TG3_TX_RING_SIZE <<
7551 BDINFO_FLAGS_MAXLEN_SHIFT),
7552 NIC_SRAM_TX_BUFFER_DESC);
7553 txrcb += TG3_BDINFO_SIZE;
7554 }
7555
7556 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7557 (TG3_RX_RCB_RING_SIZE(tp) <<
7558 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7559
7560 stblk += 8;
7561 rxrcb += TG3_BDINFO_SIZE;
7562 }
7563}
7564
7565/* tp->lock is held. */
7566static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7567{
7568 u32 val, rdmac_mode;
7569 int i, err, limit;
7570 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7571
7572 tg3_disable_ints(tp);
7573
7574 tg3_stop_fw(tp);
7575
7576 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7577
7578 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7579 tg3_abort_hw(tp, 1);
7580 }
7581
7582 if (reset_phy &&
7583 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7584 tg3_phy_reset(tp);
7585
7586 err = tg3_chip_reset(tp);
7587 if (err)
7588 return err;
7589
7590 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7591
7592 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7593 val = tr32(TG3_CPMU_CTRL);
7594 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7595 tw32(TG3_CPMU_CTRL, val);
7596
7597 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7598 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7599 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7600 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7601
7602 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7603 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7604 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7605 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7606
7607 val = tr32(TG3_CPMU_HST_ACC);
7608 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7609 val |= CPMU_HST_ACC_MACCLK_6_25;
7610 tw32(TG3_CPMU_HST_ACC, val);
7611 }
7612
7613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7614 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7615 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7616 PCIE_PWR_MGMT_L1_THRESH_4MS;
7617 tw32(PCIE_PWR_MGMT_THRESH, val);
7618
7619 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7620 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7621
7622 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7623
7624 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7625 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7626 }
7627
7628 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7629 u32 grc_mode = tr32(GRC_MODE);
7630
7631 /* Access the lower 1K of PL PCIE block registers. */
7632 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7633 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7634
7635 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7636 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7637 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7638
7639 tw32(GRC_MODE, grc_mode);
7640 }
7641
7642 /* This works around an issue with Athlon chipsets on
7643 * B3 tigon3 silicon. This bit has no effect on any
7644 * other revision. But do not set this on PCI Express
7645 * chips and don't even touch the clocks if the CPMU is present.
7646 */
7647 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7648 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7649 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7650 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7651 }
7652
7653 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7654 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7655 val = tr32(TG3PCI_PCISTATE);
7656 val |= PCISTATE_RETRY_SAME_DMA;
7657 tw32(TG3PCI_PCISTATE, val);
7658 }
7659
7660 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7661 /* Allow reads and writes to the
7662 * APE register and memory space.
7663 */
7664 val = tr32(TG3PCI_PCISTATE);
7665 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7666 PCISTATE_ALLOW_APE_SHMEM_WR;
7667 tw32(TG3PCI_PCISTATE, val);
7668 }
7669
7670 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7671 /* Enable some hw fixes. */
7672 val = tr32(TG3PCI_MSI_DATA);
7673 val |= (1 << 26) | (1 << 28) | (1 << 29);
7674 tw32(TG3PCI_MSI_DATA, val);
7675 }
7676
7677 /* Descriptor ring init may make accesses to the
7678 * NIC SRAM area to setup the TX descriptors, so we
7679 * can only do this after the hardware has been
7680 * successfully reset.
7681 */
7682 err = tg3_init_rings(tp);
7683 if (err)
7684 return err;
7685
7686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7688 val = tr32(TG3PCI_DMA_RW_CTRL) &
7689 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7690 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7691 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7692 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7693 /* This value is determined during the probe time DMA
7694 * engine test, tg3_test_dma.
7695 */
7696 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7697 }
7698
7699 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7700 GRC_MODE_4X_NIC_SEND_RINGS |
7701 GRC_MODE_NO_TX_PHDR_CSUM |
7702 GRC_MODE_NO_RX_PHDR_CSUM);
7703 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7704
7705 /* Pseudo-header checksum is done by hardware logic and not
7706 * the offload processers, so make the chip do the pseudo-
7707 * header checksums on receive. For transmit it is more
7708 * convenient to do the pseudo-header checksum in software
7709 * as Linux does that on transmit for us in all cases.
7710 */
7711 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7712
7713 tw32(GRC_MODE,
7714 tp->grc_mode |
7715 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7716
7717 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7718 val = tr32(GRC_MISC_CFG);
7719 val &= ~0xff;
7720 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7721 tw32(GRC_MISC_CFG, val);
7722
7723 /* Initialize MBUF/DESC pool. */
7724 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7725 /* Do nothing. */
7726 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7727 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7729 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7730 else
7731 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7732 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7733 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7734 }
7735 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7736 int fw_len;
7737
7738 fw_len = tp->fw_len;
7739 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7740 tw32(BUFMGR_MB_POOL_ADDR,
7741 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7742 tw32(BUFMGR_MB_POOL_SIZE,
7743 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7744 }
7745
7746 if (tp->dev->mtu <= ETH_DATA_LEN) {
7747 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7748 tp->bufmgr_config.mbuf_read_dma_low_water);
7749 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7750 tp->bufmgr_config.mbuf_mac_rx_low_water);
7751 tw32(BUFMGR_MB_HIGH_WATER,
7752 tp->bufmgr_config.mbuf_high_water);
7753 } else {
7754 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7755 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7756 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7757 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7758 tw32(BUFMGR_MB_HIGH_WATER,
7759 tp->bufmgr_config.mbuf_high_water_jumbo);
7760 }
7761 tw32(BUFMGR_DMA_LOW_WATER,
7762 tp->bufmgr_config.dma_low_water);
7763 tw32(BUFMGR_DMA_HIGH_WATER,
7764 tp->bufmgr_config.dma_high_water);
7765
7766 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7767 for (i = 0; i < 2000; i++) {
7768 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7769 break;
7770 udelay(10);
7771 }
7772 if (i >= 2000) {
7773 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7774 tp->dev->name);
7775 return -ENODEV;
7776 }
7777
7778 /* Setup replenish threshold. */
7779 val = tp->rx_pending / 8;
7780 if (val == 0)
7781 val = 1;
7782 else if (val > tp->rx_std_max_post)
7783 val = tp->rx_std_max_post;
7784 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7785 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7786 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7787
7788 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7789 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7790 }
7791
7792 tw32(RCVBDI_STD_THRESH, val);
7793
7794 /* Initialize TG3_BDINFO's at:
7795 * RCVDBDI_STD_BD: standard eth size rx ring
7796 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7797 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7798 *
7799 * like so:
7800 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7801 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7802 * ring attribute flags
7803 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7804 *
7805 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7806 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7807 *
7808 * The size of each ring is fixed in the firmware, but the location is
7809 * configurable.
7810 */
7811 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7812 ((u64) tpr->rx_std_mapping >> 32));
7813 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7814 ((u64) tpr->rx_std_mapping & 0xffffffff));
7815 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7816 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7817 NIC_SRAM_RX_BUFFER_DESC);
7818
7819 /* Disable the mini ring */
7820 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7821 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7822 BDINFO_FLAGS_DISABLED);
7823
7824 /* Program the jumbo buffer descriptor ring control
7825 * blocks on those devices that have them.
7826 */
7827 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7828 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7829 /* Setup replenish threshold. */
7830 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7831
7832 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7833 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7834 ((u64) tpr->rx_jmb_mapping >> 32));
7835 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7836 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7837 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7838 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7839 BDINFO_FLAGS_USE_EXT_RECV);
7840 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7841 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7842 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7843 } else {
7844 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7845 BDINFO_FLAGS_DISABLED);
7846 }
7847
7848 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7850 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7851 (RX_STD_MAX_SIZE << 2);
7852 else
7853 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7854 } else
7855 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7856
7857 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7858
7859 tpr->rx_std_prod_idx = tp->rx_pending;
7860 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7861
7862 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7863 tp->rx_jumbo_pending : 0;
7864 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7865
7866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7868 tw32(STD_REPLENISH_LWM, 32);
7869 tw32(JMB_REPLENISH_LWM, 16);
7870 }
7871
7872 tg3_rings_reset(tp);
7873
7874 /* Initialize MAC address and backoff seed. */
7875 __tg3_set_mac_addr(tp, 0);
7876
7877 /* MTU + ethernet header + FCS + optional VLAN tag */
7878 tw32(MAC_RX_MTU_SIZE,
7879 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7880
7881 /* The slot time is changed by tg3_setup_phy if we
7882 * run at gigabit with half duplex.
7883 */
7884 tw32(MAC_TX_LENGTHS,
7885 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7886 (6 << TX_LENGTHS_IPG_SHIFT) |
7887 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7888
7889 /* Receive rules. */
7890 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7891 tw32(RCVLPC_CONFIG, 0x0181);
7892
7893 /* Calculate RDMAC_MODE setting early, we need it to determine
7894 * the RCVLPC_STATE_ENABLE mask.
7895 */
7896 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7897 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7898 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7899 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7900 RDMAC_MODE_LNGREAD_ENAB);
7901
7902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7903 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7904 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7905 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7906 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7907 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7908
7909 /* If statement applies to 5705 and 5750 PCI devices only */
7910 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7911 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7912 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7913 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7914 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7915 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7916 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7917 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7918 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7919 }
7920 }
7921
7922 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7923 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7924
7925 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7926 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7927
7928 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7931 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7932
7933 /* Receive/send statistics. */
7934 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7935 val = tr32(RCVLPC_STATS_ENABLE);
7936 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7937 tw32(RCVLPC_STATS_ENABLE, val);
7938 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7939 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7940 val = tr32(RCVLPC_STATS_ENABLE);
7941 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7942 tw32(RCVLPC_STATS_ENABLE, val);
7943 } else {
7944 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7945 }
7946 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7947 tw32(SNDDATAI_STATSENAB, 0xffffff);
7948 tw32(SNDDATAI_STATSCTRL,
7949 (SNDDATAI_SCTRL_ENABLE |
7950 SNDDATAI_SCTRL_FASTUPD));
7951
7952 /* Setup host coalescing engine. */
7953 tw32(HOSTCC_MODE, 0);
7954 for (i = 0; i < 2000; i++) {
7955 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7956 break;
7957 udelay(10);
7958 }
7959
7960 __tg3_set_coalesce(tp, &tp->coal);
7961
7962 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7963 /* Status/statistics block address. See tg3_timer,
7964 * the tg3_periodic_fetch_stats call there, and
7965 * tg3_get_stats to see how this works for 5705/5750 chips.
7966 */
7967 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7968 ((u64) tp->stats_mapping >> 32));
7969 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7970 ((u64) tp->stats_mapping & 0xffffffff));
7971 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7972
7973 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7974
7975 /* Clear statistics and status block memory areas */
7976 for (i = NIC_SRAM_STATS_BLK;
7977 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7978 i += sizeof(u32)) {
7979 tg3_write_mem(tp, i, 0);
7980 udelay(40);
7981 }
7982 }
7983
7984 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7985
7986 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7987 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7988 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7989 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7990
7991 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7992 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7993 /* reset to prevent losing 1st rx packet intermittently */
7994 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7995 udelay(10);
7996 }
7997
7998 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7999 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8000 else
8001 tp->mac_mode = 0;
8002 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8003 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8004 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8005 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8006 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8007 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8008 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8009 udelay(40);
8010
8011 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8012 * If TG3_FLG2_IS_NIC is zero, we should read the
8013 * register to preserve the GPIO settings for LOMs. The GPIOs,
8014 * whether used as inputs or outputs, are set by boot code after
8015 * reset.
8016 */
8017 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8018 u32 gpio_mask;
8019
8020 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8021 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8022 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8023
8024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8025 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8026 GRC_LCLCTRL_GPIO_OUTPUT3;
8027
8028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8029 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8030
8031 tp->grc_local_ctrl &= ~gpio_mask;
8032 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8033
8034 /* GPIO1 must be driven high for eeprom write protect */
8035 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8036 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8037 GRC_LCLCTRL_GPIO_OUTPUT1);
8038 }
8039 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8040 udelay(100);
8041
8042 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8043 val = tr32(MSGINT_MODE);
8044 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8045 tw32(MSGINT_MODE, val);
8046 }
8047
8048 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8049 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8050 udelay(40);
8051 }
8052
8053 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8054 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8055 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8056 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8057 WDMAC_MODE_LNGREAD_ENAB);
8058
8059 /* If statement applies to 5705 and 5750 PCI devices only */
8060 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8061 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8063 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8064 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8065 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8066 /* nothing */
8067 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8068 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8069 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8070 val |= WDMAC_MODE_RX_ACCEL;
8071 }
8072 }
8073
8074 /* Enable host coalescing bug fix */
8075 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8076 val |= WDMAC_MODE_STATUS_TAG_FIX;
8077
8078 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8079 val |= WDMAC_MODE_BURST_ALL_DATA;
8080
8081 tw32_f(WDMAC_MODE, val);
8082 udelay(40);
8083
8084 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8085 u16 pcix_cmd;
8086
8087 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8088 &pcix_cmd);
8089 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8090 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8091 pcix_cmd |= PCI_X_CMD_READ_2K;
8092 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8093 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8094 pcix_cmd |= PCI_X_CMD_READ_2K;
8095 }
8096 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8097 pcix_cmd);
8098 }
8099
8100 tw32_f(RDMAC_MODE, rdmac_mode);
8101 udelay(40);
8102
8103 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8104 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8105 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8106
8107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8108 tw32(SNDDATAC_MODE,
8109 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8110 else
8111 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8112
8113 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8114 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8115 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8116 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8117 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8118 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8119 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8120 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8121 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8122 tw32(SNDBDI_MODE, val);
8123 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8124
8125 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8126 err = tg3_load_5701_a0_firmware_fix(tp);
8127 if (err)
8128 return err;
8129 }
8130
8131 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8132 err = tg3_load_tso_firmware(tp);
8133 if (err)
8134 return err;
8135 }
8136
8137 tp->tx_mode = TX_MODE_ENABLE;
8138 tw32_f(MAC_TX_MODE, tp->tx_mode);
8139 udelay(100);
8140
8141 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8142 u32 reg = MAC_RSS_INDIR_TBL_0;
8143 u8 *ent = (u8 *)&val;
8144
8145 /* Setup the indirection table */
8146 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8147 int idx = i % sizeof(val);
8148
8149 ent[idx] = i % (tp->irq_cnt - 1);
8150 if (idx == sizeof(val) - 1) {
8151 tw32(reg, val);
8152 reg += 4;
8153 }
8154 }
8155
8156 /* Setup the "secret" hash key. */
8157 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8158 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8159 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8160 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8161 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8162 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8163 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8164 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8165 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8166 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8167 }
8168
8169 tp->rx_mode = RX_MODE_ENABLE;
8170 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8171 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8172
8173 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8174 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8175 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8176 RX_MODE_RSS_IPV6_HASH_EN |
8177 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8178 RX_MODE_RSS_IPV4_HASH_EN |
8179 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8180
8181 tw32_f(MAC_RX_MODE, tp->rx_mode);
8182 udelay(10);
8183
8184 tw32(MAC_LED_CTRL, tp->led_ctrl);
8185
8186 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8187 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8188 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8189 udelay(10);
8190 }
8191 tw32_f(MAC_RX_MODE, tp->rx_mode);
8192 udelay(10);
8193
8194 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8195 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8196 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8197 /* Set drive transmission level to 1.2V */
8198 /* only if the signal pre-emphasis bit is not set */
8199 val = tr32(MAC_SERDES_CFG);
8200 val &= 0xfffff000;
8201 val |= 0x880;
8202 tw32(MAC_SERDES_CFG, val);
8203 }
8204 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8205 tw32(MAC_SERDES_CFG, 0x616000);
8206 }
8207
8208 /* Prevent chip from dropping frames when flow control
8209 * is enabled.
8210 */
8211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8212 val = 1;
8213 else
8214 val = 2;
8215 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8216
8217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8218 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8219 /* Use hardware link auto-negotiation */
8220 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8221 }
8222
8223 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8224 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8225 u32 tmp;
8226
8227 tmp = tr32(SERDES_RX_CTRL);
8228 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8229 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8230 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8231 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8232 }
8233
8234 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8235 if (tp->link_config.phy_is_low_power) {
8236 tp->link_config.phy_is_low_power = 0;
8237 tp->link_config.speed = tp->link_config.orig_speed;
8238 tp->link_config.duplex = tp->link_config.orig_duplex;
8239 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8240 }
8241
8242 err = tg3_setup_phy(tp, 0);
8243 if (err)
8244 return err;
8245
8246 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8247 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8248 u32 tmp;
8249
8250 /* Clear CRC stats. */
8251 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8252 tg3_writephy(tp, MII_TG3_TEST1,
8253 tmp | MII_TG3_TEST1_CRC_EN);
8254 tg3_readphy(tp, 0x14, &tmp);
8255 }
8256 }
8257 }
8258
8259 __tg3_set_rx_mode(tp->dev);
8260
8261 /* Initialize receive rules. */
8262 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8263 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8264 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8265 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8266
8267 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8268 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8269 limit = 8;
8270 else
8271 limit = 16;
8272 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8273 limit -= 4;
8274 switch (limit) {
8275 case 16:
8276 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8277 case 15:
8278 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8279 case 14:
8280 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8281 case 13:
8282 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8283 case 12:
8284 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8285 case 11:
8286 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8287 case 10:
8288 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8289 case 9:
8290 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8291 case 8:
8292 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8293 case 7:
8294 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8295 case 6:
8296 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8297 case 5:
8298 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8299 case 4:
8300 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8301 case 3:
8302 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8303 case 2:
8304 case 1:
8305
8306 default:
8307 break;
8308 }
8309
8310 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8311 /* Write our heartbeat update interval to APE. */
8312 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8313 APE_HOST_HEARTBEAT_INT_DISABLE);
8314
8315 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8316
8317 return 0;
8318}
8319
8320/* Called at device open time to get the chip ready for
8321 * packet processing. Invoked with tp->lock held.
8322 */
8323static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8324{
8325 tg3_switch_clocks(tp);
8326
8327 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8328
8329 return tg3_reset_hw(tp, reset_phy);
8330}
8331
8332#define TG3_STAT_ADD32(PSTAT, REG) \
8333do { u32 __val = tr32(REG); \
8334 (PSTAT)->low += __val; \
8335 if ((PSTAT)->low < __val) \
8336 (PSTAT)->high += 1; \
8337} while (0)
8338
8339static void tg3_periodic_fetch_stats(struct tg3 *tp)
8340{
8341 struct tg3_hw_stats *sp = tp->hw_stats;
8342
8343 if (!netif_carrier_ok(tp->dev))
8344 return;
8345
8346 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8347 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8348 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8349 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8350 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8351 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8352 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8353 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8354 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8355 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8356 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8357 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8358 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8359
8360 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8361 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8362 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8363 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8364 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8365 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8366 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8367 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8368 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8369 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8370 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8371 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8372 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8373 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8374
8375 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8376 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8377 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8378}
8379
8380static void tg3_timer(unsigned long __opaque)
8381{
8382 struct tg3 *tp = (struct tg3 *) __opaque;
8383
8384 if (tp->irq_sync)
8385 goto restart_timer;
8386
8387 spin_lock(&tp->lock);
8388
8389 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8390 /* All of this garbage is because when using non-tagged
8391 * IRQ status the mailbox/status_block protocol the chip
8392 * uses with the cpu is race prone.
8393 */
8394 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8395 tw32(GRC_LOCAL_CTRL,
8396 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8397 } else {
8398 tw32(HOSTCC_MODE, tp->coalesce_mode |
8399 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8400 }
8401
8402 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8403 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8404 spin_unlock(&tp->lock);
8405 schedule_work(&tp->reset_task);
8406 return;
8407 }
8408 }
8409
8410 /* This part only runs once per second. */
8411 if (!--tp->timer_counter) {
8412 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8413 tg3_periodic_fetch_stats(tp);
8414
8415 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8416 u32 mac_stat;
8417 int phy_event;
8418
8419 mac_stat = tr32(MAC_STATUS);
8420
8421 phy_event = 0;
8422 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8423 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8424 phy_event = 1;
8425 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8426 phy_event = 1;
8427
8428 if (phy_event)
8429 tg3_setup_phy(tp, 0);
8430 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8431 u32 mac_stat = tr32(MAC_STATUS);
8432 int need_setup = 0;
8433
8434 if (netif_carrier_ok(tp->dev) &&
8435 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8436 need_setup = 1;
8437 }
8438 if (! netif_carrier_ok(tp->dev) &&
8439 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8440 MAC_STATUS_SIGNAL_DET))) {
8441 need_setup = 1;
8442 }
8443 if (need_setup) {
8444 if (!tp->serdes_counter) {
8445 tw32_f(MAC_MODE,
8446 (tp->mac_mode &
8447 ~MAC_MODE_PORT_MODE_MASK));
8448 udelay(40);
8449 tw32_f(MAC_MODE, tp->mac_mode);
8450 udelay(40);
8451 }
8452 tg3_setup_phy(tp, 0);
8453 }
8454 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8455 tg3_serdes_parallel_detect(tp);
8456
8457 tp->timer_counter = tp->timer_multiplier;
8458 }
8459
8460 /* Heartbeat is only sent once every 2 seconds.
8461 *
8462 * The heartbeat is to tell the ASF firmware that the host
8463 * driver is still alive. In the event that the OS crashes,
8464 * ASF needs to reset the hardware to free up the FIFO space
8465 * that may be filled with rx packets destined for the host.
8466 * If the FIFO is full, ASF will no longer function properly.
8467 *
8468 * Unintended resets have been reported on real time kernels
8469 * where the timer doesn't run on time. Netpoll will also have
8470 * same problem.
8471 *
8472 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8473 * to check the ring condition when the heartbeat is expiring
8474 * before doing the reset. This will prevent most unintended
8475 * resets.
8476 */
8477 if (!--tp->asf_counter) {
8478 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8479 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8480 tg3_wait_for_event_ack(tp);
8481
8482 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8483 FWCMD_NICDRV_ALIVE3);
8484 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8485 /* 5 seconds timeout */
8486 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8487
8488 tg3_generate_fw_event(tp);
8489 }
8490 tp->asf_counter = tp->asf_multiplier;
8491 }
8492
8493 spin_unlock(&tp->lock);
8494
8495restart_timer:
8496 tp->timer.expires = jiffies + tp->timer_offset;
8497 add_timer(&tp->timer);
8498}
8499
8500static int tg3_request_irq(struct tg3 *tp, int irq_num)
8501{
8502 irq_handler_t fn;
8503 unsigned long flags;
8504 char *name;
8505 struct tg3_napi *tnapi = &tp->napi[irq_num];
8506
8507 if (tp->irq_cnt == 1)
8508 name = tp->dev->name;
8509 else {
8510 name = &tnapi->irq_lbl[0];
8511 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8512 name[IFNAMSIZ-1] = 0;
8513 }
8514
8515 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8516 fn = tg3_msi;
8517 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8518 fn = tg3_msi_1shot;
8519 flags = IRQF_SAMPLE_RANDOM;
8520 } else {
8521 fn = tg3_interrupt;
8522 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8523 fn = tg3_interrupt_tagged;
8524 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8525 }
8526
8527 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8528}
8529
8530static int tg3_test_interrupt(struct tg3 *tp)
8531{
8532 struct tg3_napi *tnapi = &tp->napi[0];
8533 struct net_device *dev = tp->dev;
8534 int err, i, intr_ok = 0;
8535 u32 val;
8536
8537 if (!netif_running(dev))
8538 return -ENODEV;
8539
8540 tg3_disable_ints(tp);
8541
8542 free_irq(tnapi->irq_vec, tnapi);
8543
8544 /*
8545 * Turn off MSI one shot mode. Otherwise this test has no
8546 * observable way to know whether the interrupt was delivered.
8547 */
8548 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8549 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8550 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8551 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8552 tw32(MSGINT_MODE, val);
8553 }
8554
8555 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8556 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8557 if (err)
8558 return err;
8559
8560 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8561 tg3_enable_ints(tp);
8562
8563 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8564 tnapi->coal_now);
8565
8566 for (i = 0; i < 5; i++) {
8567 u32 int_mbox, misc_host_ctrl;
8568
8569 int_mbox = tr32_mailbox(tnapi->int_mbox);
8570 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8571
8572 if ((int_mbox != 0) ||
8573 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8574 intr_ok = 1;
8575 break;
8576 }
8577
8578 msleep(10);
8579 }
8580
8581 tg3_disable_ints(tp);
8582
8583 free_irq(tnapi->irq_vec, tnapi);
8584
8585 err = tg3_request_irq(tp, 0);
8586
8587 if (err)
8588 return err;
8589
8590 if (intr_ok) {
8591 /* Reenable MSI one shot mode. */
8592 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8593 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8594 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8595 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8596 tw32(MSGINT_MODE, val);
8597 }
8598 return 0;
8599 }
8600
8601 return -EIO;
8602}
8603
8604/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8605 * successfully restored
8606 */
8607static int tg3_test_msi(struct tg3 *tp)
8608{
8609 int err;
8610 u16 pci_cmd;
8611
8612 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8613 return 0;
8614
8615 /* Turn off SERR reporting in case MSI terminates with Master
8616 * Abort.
8617 */
8618 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8619 pci_write_config_word(tp->pdev, PCI_COMMAND,
8620 pci_cmd & ~PCI_COMMAND_SERR);
8621
8622 err = tg3_test_interrupt(tp);
8623
8624 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8625
8626 if (!err)
8627 return 0;
8628
8629 /* other failures */
8630 if (err != -EIO)
8631 return err;
8632
8633 /* MSI test failed, go back to INTx mode */
8634 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8635 "switching to INTx mode. Please report this failure to "
8636 "the PCI maintainer and include system chipset information.\n",
8637 tp->dev->name);
8638
8639 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8640
8641 pci_disable_msi(tp->pdev);
8642
8643 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8644
8645 err = tg3_request_irq(tp, 0);
8646 if (err)
8647 return err;
8648
8649 /* Need to reset the chip because the MSI cycle may have terminated
8650 * with Master Abort.
8651 */
8652 tg3_full_lock(tp, 1);
8653
8654 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8655 err = tg3_init_hw(tp, 1);
8656
8657 tg3_full_unlock(tp);
8658
8659 if (err)
8660 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8661
8662 return err;
8663}
8664
8665static int tg3_request_firmware(struct tg3 *tp)
8666{
8667 const __be32 *fw_data;
8668
8669 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8670 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8671 tp->dev->name, tp->fw_needed);
8672 return -ENOENT;
8673 }
8674
8675 fw_data = (void *)tp->fw->data;
8676
8677 /* Firmware blob starts with version numbers, followed by
8678 * start address and _full_ length including BSS sections
8679 * (which must be longer than the actual data, of course
8680 */
8681
8682 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8683 if (tp->fw_len < (tp->fw->size - 12)) {
8684 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8685 tp->dev->name, tp->fw_len, tp->fw_needed);
8686 release_firmware(tp->fw);
8687 tp->fw = NULL;
8688 return -EINVAL;
8689 }
8690
8691 /* We no longer need firmware; we have it. */
8692 tp->fw_needed = NULL;
8693 return 0;
8694}
8695
8696static bool tg3_enable_msix(struct tg3 *tp)
8697{
8698 int i, rc, cpus = num_online_cpus();
8699 struct msix_entry msix_ent[tp->irq_max];
8700
8701 if (cpus == 1)
8702 /* Just fallback to the simpler MSI mode. */
8703 return false;
8704
8705 /*
8706 * We want as many rx rings enabled as there are cpus.
8707 * The first MSIX vector only deals with link interrupts, etc,
8708 * so we add one to the number of vectors we are requesting.
8709 */
8710 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8711
8712 for (i = 0; i < tp->irq_max; i++) {
8713 msix_ent[i].entry = i;
8714 msix_ent[i].vector = 0;
8715 }
8716
8717 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8718 if (rc != 0) {
8719 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8720 return false;
8721 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8722 return false;
8723 printk(KERN_NOTICE
8724 "%s: Requested %d MSI-X vectors, received %d\n",
8725 tp->dev->name, tp->irq_cnt, rc);
8726 tp->irq_cnt = rc;
8727 }
8728
8729 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8730
8731 for (i = 0; i < tp->irq_max; i++)
8732 tp->napi[i].irq_vec = msix_ent[i].vector;
8733
8734 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8735 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8736 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8737 } else
8738 tp->dev->real_num_tx_queues = 1;
8739
8740 return true;
8741}
8742
8743static void tg3_ints_init(struct tg3 *tp)
8744{
8745 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8746 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8747 /* All MSI supporting chips should support tagged
8748 * status. Assert that this is the case.
8749 */
8750 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8751 "Not using MSI.\n", tp->dev->name);
8752 goto defcfg;
8753 }
8754
8755 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8756 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8757 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8758 pci_enable_msi(tp->pdev) == 0)
8759 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8760
8761 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8762 u32 msi_mode = tr32(MSGINT_MODE);
8763 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8764 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8765 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8766 }
8767defcfg:
8768 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8769 tp->irq_cnt = 1;
8770 tp->napi[0].irq_vec = tp->pdev->irq;
8771 tp->dev->real_num_tx_queues = 1;
8772 }
8773}
8774
8775static void tg3_ints_fini(struct tg3 *tp)
8776{
8777 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8778 pci_disable_msix(tp->pdev);
8779 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8780 pci_disable_msi(tp->pdev);
8781 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8782 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8783}
8784
8785static int tg3_open(struct net_device *dev)
8786{
8787 struct tg3 *tp = netdev_priv(dev);
8788 int i, err;
8789
8790 if (tp->fw_needed) {
8791 err = tg3_request_firmware(tp);
8792 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8793 if (err)
8794 return err;
8795 } else if (err) {
8796 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8797 tp->dev->name);
8798 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8799 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8800 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8801 tp->dev->name);
8802 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8803 }
8804 }
8805
8806 netif_carrier_off(tp->dev);
8807
8808 err = tg3_set_power_state(tp, PCI_D0);
8809 if (err)
8810 return err;
8811
8812 tg3_full_lock(tp, 0);
8813
8814 tg3_disable_ints(tp);
8815 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8816
8817 tg3_full_unlock(tp);
8818
8819 /*
8820 * Setup interrupts first so we know how
8821 * many NAPI resources to allocate
8822 */
8823 tg3_ints_init(tp);
8824
8825 /* The placement of this call is tied
8826 * to the setup and use of Host TX descriptors.
8827 */
8828 err = tg3_alloc_consistent(tp);
8829 if (err)
8830 goto err_out1;
8831
8832 tg3_napi_enable(tp);
8833
8834 for (i = 0; i < tp->irq_cnt; i++) {
8835 struct tg3_napi *tnapi = &tp->napi[i];
8836 err = tg3_request_irq(tp, i);
8837 if (err) {
8838 for (i--; i >= 0; i--)
8839 free_irq(tnapi->irq_vec, tnapi);
8840 break;
8841 }
8842 }
8843
8844 if (err)
8845 goto err_out2;
8846
8847 tg3_full_lock(tp, 0);
8848
8849 err = tg3_init_hw(tp, 1);
8850 if (err) {
8851 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8852 tg3_free_rings(tp);
8853 } else {
8854 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8855 tp->timer_offset = HZ;
8856 else
8857 tp->timer_offset = HZ / 10;
8858
8859 BUG_ON(tp->timer_offset > HZ);
8860 tp->timer_counter = tp->timer_multiplier =
8861 (HZ / tp->timer_offset);
8862 tp->asf_counter = tp->asf_multiplier =
8863 ((HZ / tp->timer_offset) * 2);
8864
8865 init_timer(&tp->timer);
8866 tp->timer.expires = jiffies + tp->timer_offset;
8867 tp->timer.data = (unsigned long) tp;
8868 tp->timer.function = tg3_timer;
8869 }
8870
8871 tg3_full_unlock(tp);
8872
8873 if (err)
8874 goto err_out3;
8875
8876 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8877 err = tg3_test_msi(tp);
8878
8879 if (err) {
8880 tg3_full_lock(tp, 0);
8881 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8882 tg3_free_rings(tp);
8883 tg3_full_unlock(tp);
8884
8885 goto err_out2;
8886 }
8887
8888 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8889 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8890 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8891 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8892 u32 val = tr32(PCIE_TRANSACTION_CFG);
8893
8894 tw32(PCIE_TRANSACTION_CFG,
8895 val | PCIE_TRANS_CFG_1SHOT_MSI);
8896 }
8897 }
8898
8899 tg3_phy_start(tp);
8900
8901 tg3_full_lock(tp, 0);
8902
8903 add_timer(&tp->timer);
8904 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8905 tg3_enable_ints(tp);
8906
8907 tg3_full_unlock(tp);
8908
8909 netif_tx_start_all_queues(dev);
8910
8911 return 0;
8912
8913err_out3:
8914 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8915 struct tg3_napi *tnapi = &tp->napi[i];
8916 free_irq(tnapi->irq_vec, tnapi);
8917 }
8918
8919err_out2:
8920 tg3_napi_disable(tp);
8921 tg3_free_consistent(tp);
8922
8923err_out1:
8924 tg3_ints_fini(tp);
8925 return err;
8926}
8927
8928#if 0
8929/*static*/ void tg3_dump_state(struct tg3 *tp)
8930{
8931 u32 val32, val32_2, val32_3, val32_4, val32_5;
8932 u16 val16;
8933 int i;
8934 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8935
8936 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8937 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8938 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8939 val16, val32);
8940
8941 /* MAC block */
8942 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8943 tr32(MAC_MODE), tr32(MAC_STATUS));
8944 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8945 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8946 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8947 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8948 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8949 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8950
8951 /* Send data initiator control block */
8952 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8953 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8954 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8955 tr32(SNDDATAI_STATSCTRL));
8956
8957 /* Send data completion control block */
8958 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8959
8960 /* Send BD ring selector block */
8961 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8962 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8963
8964 /* Send BD initiator control block */
8965 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8966 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8967
8968 /* Send BD completion control block */
8969 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8970
8971 /* Receive list placement control block */
8972 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8973 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8974 printk(" RCVLPC_STATSCTRL[%08x]\n",
8975 tr32(RCVLPC_STATSCTRL));
8976
8977 /* Receive data and receive BD initiator control block */
8978 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8979 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8980
8981 /* Receive data completion control block */
8982 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8983 tr32(RCVDCC_MODE));
8984
8985 /* Receive BD initiator control block */
8986 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8987 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8988
8989 /* Receive BD completion control block */
8990 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8991 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8992
8993 /* Receive list selector control block */
8994 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8995 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8996
8997 /* Mbuf cluster free block */
8998 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8999 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
9000
9001 /* Host coalescing control block */
9002 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
9003 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
9004 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
9005 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9006 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9007 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
9008 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9009 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9010 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9011 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9012 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9013 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9014
9015 /* Memory arbiter control block */
9016 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9017 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9018
9019 /* Buffer manager control block */
9020 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9021 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9022 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9023 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9024 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9025 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9026 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9027 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9028
9029 /* Read DMA control block */
9030 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9031 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9032
9033 /* Write DMA control block */
9034 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9035 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9036
9037 /* DMA completion block */
9038 printk("DEBUG: DMAC_MODE[%08x]\n",
9039 tr32(DMAC_MODE));
9040
9041 /* GRC block */
9042 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9043 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9044 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9045 tr32(GRC_LOCAL_CTRL));
9046
9047 /* TG3_BDINFOs */
9048 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9049 tr32(RCVDBDI_JUMBO_BD + 0x0),
9050 tr32(RCVDBDI_JUMBO_BD + 0x4),
9051 tr32(RCVDBDI_JUMBO_BD + 0x8),
9052 tr32(RCVDBDI_JUMBO_BD + 0xc));
9053 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9054 tr32(RCVDBDI_STD_BD + 0x0),
9055 tr32(RCVDBDI_STD_BD + 0x4),
9056 tr32(RCVDBDI_STD_BD + 0x8),
9057 tr32(RCVDBDI_STD_BD + 0xc));
9058 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9059 tr32(RCVDBDI_MINI_BD + 0x0),
9060 tr32(RCVDBDI_MINI_BD + 0x4),
9061 tr32(RCVDBDI_MINI_BD + 0x8),
9062 tr32(RCVDBDI_MINI_BD + 0xc));
9063
9064 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9065 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9066 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9067 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9068 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9069 val32, val32_2, val32_3, val32_4);
9070
9071 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9072 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9073 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9074 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9075 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9076 val32, val32_2, val32_3, val32_4);
9077
9078 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9079 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9080 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9081 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9082 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9083 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9084 val32, val32_2, val32_3, val32_4, val32_5);
9085
9086 /* SW status block */
9087 printk(KERN_DEBUG
9088 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9089 sblk->status,
9090 sblk->status_tag,
9091 sblk->rx_jumbo_consumer,
9092 sblk->rx_consumer,
9093 sblk->rx_mini_consumer,
9094 sblk->idx[0].rx_producer,
9095 sblk->idx[0].tx_consumer);
9096
9097 /* SW statistics block */
9098 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9099 ((u32 *)tp->hw_stats)[0],
9100 ((u32 *)tp->hw_stats)[1],
9101 ((u32 *)tp->hw_stats)[2],
9102 ((u32 *)tp->hw_stats)[3]);
9103
9104 /* Mailboxes */
9105 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9106 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9107 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9108 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9109 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9110
9111 /* NIC side send descriptors. */
9112 for (i = 0; i < 6; i++) {
9113 unsigned long txd;
9114
9115 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9116 + (i * sizeof(struct tg3_tx_buffer_desc));
9117 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9118 i,
9119 readl(txd + 0x0), readl(txd + 0x4),
9120 readl(txd + 0x8), readl(txd + 0xc));
9121 }
9122
9123 /* NIC side RX descriptors. */
9124 for (i = 0; i < 6; i++) {
9125 unsigned long rxd;
9126
9127 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9128 + (i * sizeof(struct tg3_rx_buffer_desc));
9129 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9130 i,
9131 readl(rxd + 0x0), readl(rxd + 0x4),
9132 readl(rxd + 0x8), readl(rxd + 0xc));
9133 rxd += (4 * sizeof(u32));
9134 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9135 i,
9136 readl(rxd + 0x0), readl(rxd + 0x4),
9137 readl(rxd + 0x8), readl(rxd + 0xc));
9138 }
9139
9140 for (i = 0; i < 6; i++) {
9141 unsigned long rxd;
9142
9143 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9144 + (i * sizeof(struct tg3_rx_buffer_desc));
9145 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9146 i,
9147 readl(rxd + 0x0), readl(rxd + 0x4),
9148 readl(rxd + 0x8), readl(rxd + 0xc));
9149 rxd += (4 * sizeof(u32));
9150 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9151 i,
9152 readl(rxd + 0x0), readl(rxd + 0x4),
9153 readl(rxd + 0x8), readl(rxd + 0xc));
9154 }
9155}
9156#endif
9157
9158static struct net_device_stats *tg3_get_stats(struct net_device *);
9159static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9160
9161static int tg3_close(struct net_device *dev)
9162{
9163 int i;
9164 struct tg3 *tp = netdev_priv(dev);
9165
9166 tg3_napi_disable(tp);
9167 cancel_work_sync(&tp->reset_task);
9168
9169 netif_tx_stop_all_queues(dev);
9170
9171 del_timer_sync(&tp->timer);
9172
9173 tg3_phy_stop(tp);
9174
9175 tg3_full_lock(tp, 1);
9176#if 0
9177 tg3_dump_state(tp);
9178#endif
9179
9180 tg3_disable_ints(tp);
9181
9182 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9183 tg3_free_rings(tp);
9184 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9185
9186 tg3_full_unlock(tp);
9187
9188 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9189 struct tg3_napi *tnapi = &tp->napi[i];
9190 free_irq(tnapi->irq_vec, tnapi);
9191 }
9192
9193 tg3_ints_fini(tp);
9194
9195 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9196 sizeof(tp->net_stats_prev));
9197 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9198 sizeof(tp->estats_prev));
9199
9200 tg3_free_consistent(tp);
9201
9202 tg3_set_power_state(tp, PCI_D3hot);
9203
9204 netif_carrier_off(tp->dev);
9205
9206 return 0;
9207}
9208
9209static inline unsigned long get_stat64(tg3_stat64_t *val)
9210{
9211 unsigned long ret;
9212
9213#if (BITS_PER_LONG == 32)
9214 ret = val->low;
9215#else
9216 ret = ((u64)val->high << 32) | ((u64)val->low);
9217#endif
9218 return ret;
9219}
9220
9221static inline u64 get_estat64(tg3_stat64_t *val)
9222{
9223 return ((u64)val->high << 32) | ((u64)val->low);
9224}
9225
9226static unsigned long calc_crc_errors(struct tg3 *tp)
9227{
9228 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9229
9230 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9231 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9232 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9233 u32 val;
9234
9235 spin_lock_bh(&tp->lock);
9236 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9237 tg3_writephy(tp, MII_TG3_TEST1,
9238 val | MII_TG3_TEST1_CRC_EN);
9239 tg3_readphy(tp, 0x14, &val);
9240 } else
9241 val = 0;
9242 spin_unlock_bh(&tp->lock);
9243
9244 tp->phy_crc_errors += val;
9245
9246 return tp->phy_crc_errors;
9247 }
9248
9249 return get_stat64(&hw_stats->rx_fcs_errors);
9250}
9251
9252#define ESTAT_ADD(member) \
9253 estats->member = old_estats->member + \
9254 get_estat64(&hw_stats->member)
9255
9256static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9257{
9258 struct tg3_ethtool_stats *estats = &tp->estats;
9259 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9260 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9261
9262 if (!hw_stats)
9263 return old_estats;
9264
9265 ESTAT_ADD(rx_octets);
9266 ESTAT_ADD(rx_fragments);
9267 ESTAT_ADD(rx_ucast_packets);
9268 ESTAT_ADD(rx_mcast_packets);
9269 ESTAT_ADD(rx_bcast_packets);
9270 ESTAT_ADD(rx_fcs_errors);
9271 ESTAT_ADD(rx_align_errors);
9272 ESTAT_ADD(rx_xon_pause_rcvd);
9273 ESTAT_ADD(rx_xoff_pause_rcvd);
9274 ESTAT_ADD(rx_mac_ctrl_rcvd);
9275 ESTAT_ADD(rx_xoff_entered);
9276 ESTAT_ADD(rx_frame_too_long_errors);
9277 ESTAT_ADD(rx_jabbers);
9278 ESTAT_ADD(rx_undersize_packets);
9279 ESTAT_ADD(rx_in_length_errors);
9280 ESTAT_ADD(rx_out_length_errors);
9281 ESTAT_ADD(rx_64_or_less_octet_packets);
9282 ESTAT_ADD(rx_65_to_127_octet_packets);
9283 ESTAT_ADD(rx_128_to_255_octet_packets);
9284 ESTAT_ADD(rx_256_to_511_octet_packets);
9285 ESTAT_ADD(rx_512_to_1023_octet_packets);
9286 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9287 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9288 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9289 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9290 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9291
9292 ESTAT_ADD(tx_octets);
9293 ESTAT_ADD(tx_collisions);
9294 ESTAT_ADD(tx_xon_sent);
9295 ESTAT_ADD(tx_xoff_sent);
9296 ESTAT_ADD(tx_flow_control);
9297 ESTAT_ADD(tx_mac_errors);
9298 ESTAT_ADD(tx_single_collisions);
9299 ESTAT_ADD(tx_mult_collisions);
9300 ESTAT_ADD(tx_deferred);
9301 ESTAT_ADD(tx_excessive_collisions);
9302 ESTAT_ADD(tx_late_collisions);
9303 ESTAT_ADD(tx_collide_2times);
9304 ESTAT_ADD(tx_collide_3times);
9305 ESTAT_ADD(tx_collide_4times);
9306 ESTAT_ADD(tx_collide_5times);
9307 ESTAT_ADD(tx_collide_6times);
9308 ESTAT_ADD(tx_collide_7times);
9309 ESTAT_ADD(tx_collide_8times);
9310 ESTAT_ADD(tx_collide_9times);
9311 ESTAT_ADD(tx_collide_10times);
9312 ESTAT_ADD(tx_collide_11times);
9313 ESTAT_ADD(tx_collide_12times);
9314 ESTAT_ADD(tx_collide_13times);
9315 ESTAT_ADD(tx_collide_14times);
9316 ESTAT_ADD(tx_collide_15times);
9317 ESTAT_ADD(tx_ucast_packets);
9318 ESTAT_ADD(tx_mcast_packets);
9319 ESTAT_ADD(tx_bcast_packets);
9320 ESTAT_ADD(tx_carrier_sense_errors);
9321 ESTAT_ADD(tx_discards);
9322 ESTAT_ADD(tx_errors);
9323
9324 ESTAT_ADD(dma_writeq_full);
9325 ESTAT_ADD(dma_write_prioq_full);
9326 ESTAT_ADD(rxbds_empty);
9327 ESTAT_ADD(rx_discards);
9328 ESTAT_ADD(rx_errors);
9329 ESTAT_ADD(rx_threshold_hit);
9330
9331 ESTAT_ADD(dma_readq_full);
9332 ESTAT_ADD(dma_read_prioq_full);
9333 ESTAT_ADD(tx_comp_queue_full);
9334
9335 ESTAT_ADD(ring_set_send_prod_index);
9336 ESTAT_ADD(ring_status_update);
9337 ESTAT_ADD(nic_irqs);
9338 ESTAT_ADD(nic_avoided_irqs);
9339 ESTAT_ADD(nic_tx_threshold_hit);
9340
9341 return estats;
9342}
9343
9344static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9345{
9346 struct tg3 *tp = netdev_priv(dev);
9347 struct net_device_stats *stats = &tp->net_stats;
9348 struct net_device_stats *old_stats = &tp->net_stats_prev;
9349 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9350
9351 if (!hw_stats)
9352 return old_stats;
9353
9354 stats->rx_packets = old_stats->rx_packets +
9355 get_stat64(&hw_stats->rx_ucast_packets) +
9356 get_stat64(&hw_stats->rx_mcast_packets) +
9357 get_stat64(&hw_stats->rx_bcast_packets);
9358
9359 stats->tx_packets = old_stats->tx_packets +
9360 get_stat64(&hw_stats->tx_ucast_packets) +
9361 get_stat64(&hw_stats->tx_mcast_packets) +
9362 get_stat64(&hw_stats->tx_bcast_packets);
9363
9364 stats->rx_bytes = old_stats->rx_bytes +
9365 get_stat64(&hw_stats->rx_octets);
9366 stats->tx_bytes = old_stats->tx_bytes +
9367 get_stat64(&hw_stats->tx_octets);
9368
9369 stats->rx_errors = old_stats->rx_errors +
9370 get_stat64(&hw_stats->rx_errors);
9371 stats->tx_errors = old_stats->tx_errors +
9372 get_stat64(&hw_stats->tx_errors) +
9373 get_stat64(&hw_stats->tx_mac_errors) +
9374 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9375 get_stat64(&hw_stats->tx_discards);
9376
9377 stats->multicast = old_stats->multicast +
9378 get_stat64(&hw_stats->rx_mcast_packets);
9379 stats->collisions = old_stats->collisions +
9380 get_stat64(&hw_stats->tx_collisions);
9381
9382 stats->rx_length_errors = old_stats->rx_length_errors +
9383 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9384 get_stat64(&hw_stats->rx_undersize_packets);
9385
9386 stats->rx_over_errors = old_stats->rx_over_errors +
9387 get_stat64(&hw_stats->rxbds_empty);
9388 stats->rx_frame_errors = old_stats->rx_frame_errors +
9389 get_stat64(&hw_stats->rx_align_errors);
9390 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9391 get_stat64(&hw_stats->tx_discards);
9392 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9393 get_stat64(&hw_stats->tx_carrier_sense_errors);
9394
9395 stats->rx_crc_errors = old_stats->rx_crc_errors +
9396 calc_crc_errors(tp);
9397
9398 stats->rx_missed_errors = old_stats->rx_missed_errors +
9399 get_stat64(&hw_stats->rx_discards);
9400
9401 return stats;
9402}
9403
9404static inline u32 calc_crc(unsigned char *buf, int len)
9405{
9406 u32 reg;
9407 u32 tmp;
9408 int j, k;
9409
9410 reg = 0xffffffff;
9411
9412 for (j = 0; j < len; j++) {
9413 reg ^= buf[j];
9414
9415 for (k = 0; k < 8; k++) {
9416 tmp = reg & 0x01;
9417
9418 reg >>= 1;
9419
9420 if (tmp) {
9421 reg ^= 0xedb88320;
9422 }
9423 }
9424 }
9425
9426 return ~reg;
9427}
9428
9429static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9430{
9431 /* accept or reject all multicast frames */
9432 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9433 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9434 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9435 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9436}
9437
9438static void __tg3_set_rx_mode(struct net_device *dev)
9439{
9440 struct tg3 *tp = netdev_priv(dev);
9441 u32 rx_mode;
9442
9443 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9444 RX_MODE_KEEP_VLAN_TAG);
9445
9446 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9447 * flag clear.
9448 */
9449#if TG3_VLAN_TAG_USED
9450 if (!tp->vlgrp &&
9451 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9452 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9453#else
9454 /* By definition, VLAN is disabled always in this
9455 * case.
9456 */
9457 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9458 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9459#endif
9460
9461 if (dev->flags & IFF_PROMISC) {
9462 /* Promiscuous mode. */
9463 rx_mode |= RX_MODE_PROMISC;
9464 } else if (dev->flags & IFF_ALLMULTI) {
9465 /* Accept all multicast. */
9466 tg3_set_multi (tp, 1);
9467 } else if (netdev_mc_empty(dev)) {
9468 /* Reject all multicast. */
9469 tg3_set_multi (tp, 0);
9470 } else {
9471 /* Accept one or more multicast(s). */
9472 struct dev_mc_list *mclist;
9473 unsigned int i;
9474 u32 mc_filter[4] = { 0, };
9475 u32 regidx;
9476 u32 bit;
9477 u32 crc;
9478
9479 for (i = 0, mclist = dev->mc_list; mclist && i < netdev_mc_count(dev);
9480 i++, mclist = mclist->next) {
9481
9482 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9483 bit = ~crc & 0x7f;
9484 regidx = (bit & 0x60) >> 5;
9485 bit &= 0x1f;
9486 mc_filter[regidx] |= (1 << bit);
9487 }
9488
9489 tw32(MAC_HASH_REG_0, mc_filter[0]);
9490 tw32(MAC_HASH_REG_1, mc_filter[1]);
9491 tw32(MAC_HASH_REG_2, mc_filter[2]);
9492 tw32(MAC_HASH_REG_3, mc_filter[3]);
9493 }
9494
9495 if (rx_mode != tp->rx_mode) {
9496 tp->rx_mode = rx_mode;
9497 tw32_f(MAC_RX_MODE, rx_mode);
9498 udelay(10);
9499 }
9500}
9501
9502static void tg3_set_rx_mode(struct net_device *dev)
9503{
9504 struct tg3 *tp = netdev_priv(dev);
9505
9506 if (!netif_running(dev))
9507 return;
9508
9509 tg3_full_lock(tp, 0);
9510 __tg3_set_rx_mode(dev);
9511 tg3_full_unlock(tp);
9512}
9513
9514#define TG3_REGDUMP_LEN (32 * 1024)
9515
9516static int tg3_get_regs_len(struct net_device *dev)
9517{
9518 return TG3_REGDUMP_LEN;
9519}
9520
9521static void tg3_get_regs(struct net_device *dev,
9522 struct ethtool_regs *regs, void *_p)
9523{
9524 u32 *p = _p;
9525 struct tg3 *tp = netdev_priv(dev);
9526 u8 *orig_p = _p;
9527 int i;
9528
9529 regs->version = 0;
9530
9531 memset(p, 0, TG3_REGDUMP_LEN);
9532
9533 if (tp->link_config.phy_is_low_power)
9534 return;
9535
9536 tg3_full_lock(tp, 0);
9537
9538#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9539#define GET_REG32_LOOP(base,len) \
9540do { p = (u32 *)(orig_p + (base)); \
9541 for (i = 0; i < len; i += 4) \
9542 __GET_REG32((base) + i); \
9543} while (0)
9544#define GET_REG32_1(reg) \
9545do { p = (u32 *)(orig_p + (reg)); \
9546 __GET_REG32((reg)); \
9547} while (0)
9548
9549 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9550 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9551 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9552 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9553 GET_REG32_1(SNDDATAC_MODE);
9554 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9555 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9556 GET_REG32_1(SNDBDC_MODE);
9557 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9558 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9559 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9560 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9561 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9562 GET_REG32_1(RCVDCC_MODE);
9563 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9564 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9565 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9566 GET_REG32_1(MBFREE_MODE);
9567 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9568 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9569 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9570 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9571 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9572 GET_REG32_1(RX_CPU_MODE);
9573 GET_REG32_1(RX_CPU_STATE);
9574 GET_REG32_1(RX_CPU_PGMCTR);
9575 GET_REG32_1(RX_CPU_HWBKPT);
9576 GET_REG32_1(TX_CPU_MODE);
9577 GET_REG32_1(TX_CPU_STATE);
9578 GET_REG32_1(TX_CPU_PGMCTR);
9579 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9580 GET_REG32_LOOP(FTQ_RESET, 0x120);
9581 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9582 GET_REG32_1(DMAC_MODE);
9583 GET_REG32_LOOP(GRC_MODE, 0x4c);
9584 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9585 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9586
9587#undef __GET_REG32
9588#undef GET_REG32_LOOP
9589#undef GET_REG32_1
9590
9591 tg3_full_unlock(tp);
9592}
9593
9594static int tg3_get_eeprom_len(struct net_device *dev)
9595{
9596 struct tg3 *tp = netdev_priv(dev);
9597
9598 return tp->nvram_size;
9599}
9600
9601static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9602{
9603 struct tg3 *tp = netdev_priv(dev);
9604 int ret;
9605 u8 *pd;
9606 u32 i, offset, len, b_offset, b_count;
9607 __be32 val;
9608
9609 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9610 return -EINVAL;
9611
9612 if (tp->link_config.phy_is_low_power)
9613 return -EAGAIN;
9614
9615 offset = eeprom->offset;
9616 len = eeprom->len;
9617 eeprom->len = 0;
9618
9619 eeprom->magic = TG3_EEPROM_MAGIC;
9620
9621 if (offset & 3) {
9622 /* adjustments to start on required 4 byte boundary */
9623 b_offset = offset & 3;
9624 b_count = 4 - b_offset;
9625 if (b_count > len) {
9626 /* i.e. offset=1 len=2 */
9627 b_count = len;
9628 }
9629 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9630 if (ret)
9631 return ret;
9632 memcpy(data, ((char*)&val) + b_offset, b_count);
9633 len -= b_count;
9634 offset += b_count;
9635 eeprom->len += b_count;
9636 }
9637
9638 /* read bytes upto the last 4 byte boundary */
9639 pd = &data[eeprom->len];
9640 for (i = 0; i < (len - (len & 3)); i += 4) {
9641 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9642 if (ret) {
9643 eeprom->len += i;
9644 return ret;
9645 }
9646 memcpy(pd + i, &val, 4);
9647 }
9648 eeprom->len += i;
9649
9650 if (len & 3) {
9651 /* read last bytes not ending on 4 byte boundary */
9652 pd = &data[eeprom->len];
9653 b_count = len & 3;
9654 b_offset = offset + len - b_count;
9655 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9656 if (ret)
9657 return ret;
9658 memcpy(pd, &val, b_count);
9659 eeprom->len += b_count;
9660 }
9661 return 0;
9662}
9663
9664static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9665
9666static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9667{
9668 struct tg3 *tp = netdev_priv(dev);
9669 int ret;
9670 u32 offset, len, b_offset, odd_len;
9671 u8 *buf;
9672 __be32 start, end;
9673
9674 if (tp->link_config.phy_is_low_power)
9675 return -EAGAIN;
9676
9677 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9678 eeprom->magic != TG3_EEPROM_MAGIC)
9679 return -EINVAL;
9680
9681 offset = eeprom->offset;
9682 len = eeprom->len;
9683
9684 if ((b_offset = (offset & 3))) {
9685 /* adjustments to start on required 4 byte boundary */
9686 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9687 if (ret)
9688 return ret;
9689 len += b_offset;
9690 offset &= ~3;
9691 if (len < 4)
9692 len = 4;
9693 }
9694
9695 odd_len = 0;
9696 if (len & 3) {
9697 /* adjustments to end on required 4 byte boundary */
9698 odd_len = 1;
9699 len = (len + 3) & ~3;
9700 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9701 if (ret)
9702 return ret;
9703 }
9704
9705 buf = data;
9706 if (b_offset || odd_len) {
9707 buf = kmalloc(len, GFP_KERNEL);
9708 if (!buf)
9709 return -ENOMEM;
9710 if (b_offset)
9711 memcpy(buf, &start, 4);
9712 if (odd_len)
9713 memcpy(buf+len-4, &end, 4);
9714 memcpy(buf + b_offset, data, eeprom->len);
9715 }
9716
9717 ret = tg3_nvram_write_block(tp, offset, len, buf);
9718
9719 if (buf != data)
9720 kfree(buf);
9721
9722 return ret;
9723}
9724
9725static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9726{
9727 struct tg3 *tp = netdev_priv(dev);
9728
9729 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9730 struct phy_device *phydev;
9731 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9732 return -EAGAIN;
9733 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9734 return phy_ethtool_gset(phydev, cmd);
9735 }
9736
9737 cmd->supported = (SUPPORTED_Autoneg);
9738
9739 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9740 cmd->supported |= (SUPPORTED_1000baseT_Half |
9741 SUPPORTED_1000baseT_Full);
9742
9743 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9744 cmd->supported |= (SUPPORTED_100baseT_Half |
9745 SUPPORTED_100baseT_Full |
9746 SUPPORTED_10baseT_Half |
9747 SUPPORTED_10baseT_Full |
9748 SUPPORTED_TP);
9749 cmd->port = PORT_TP;
9750 } else {
9751 cmd->supported |= SUPPORTED_FIBRE;
9752 cmd->port = PORT_FIBRE;
9753 }
9754
9755 cmd->advertising = tp->link_config.advertising;
9756 if (netif_running(dev)) {
9757 cmd->speed = tp->link_config.active_speed;
9758 cmd->duplex = tp->link_config.active_duplex;
9759 }
9760 cmd->phy_address = tp->phy_addr;
9761 cmd->transceiver = XCVR_INTERNAL;
9762 cmd->autoneg = tp->link_config.autoneg;
9763 cmd->maxtxpkt = 0;
9764 cmd->maxrxpkt = 0;
9765 return 0;
9766}
9767
9768static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9769{
9770 struct tg3 *tp = netdev_priv(dev);
9771
9772 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9773 struct phy_device *phydev;
9774 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9775 return -EAGAIN;
9776 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9777 return phy_ethtool_sset(phydev, cmd);
9778 }
9779
9780 if (cmd->autoneg != AUTONEG_ENABLE &&
9781 cmd->autoneg != AUTONEG_DISABLE)
9782 return -EINVAL;
9783
9784 if (cmd->autoneg == AUTONEG_DISABLE &&
9785 cmd->duplex != DUPLEX_FULL &&
9786 cmd->duplex != DUPLEX_HALF)
9787 return -EINVAL;
9788
9789 if (cmd->autoneg == AUTONEG_ENABLE) {
9790 u32 mask = ADVERTISED_Autoneg |
9791 ADVERTISED_Pause |
9792 ADVERTISED_Asym_Pause;
9793
9794 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9795 mask |= ADVERTISED_1000baseT_Half |
9796 ADVERTISED_1000baseT_Full;
9797
9798 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9799 mask |= ADVERTISED_100baseT_Half |
9800 ADVERTISED_100baseT_Full |
9801 ADVERTISED_10baseT_Half |
9802 ADVERTISED_10baseT_Full |
9803 ADVERTISED_TP;
9804 else
9805 mask |= ADVERTISED_FIBRE;
9806
9807 if (cmd->advertising & ~mask)
9808 return -EINVAL;
9809
9810 mask &= (ADVERTISED_1000baseT_Half |
9811 ADVERTISED_1000baseT_Full |
9812 ADVERTISED_100baseT_Half |
9813 ADVERTISED_100baseT_Full |
9814 ADVERTISED_10baseT_Half |
9815 ADVERTISED_10baseT_Full);
9816
9817 cmd->advertising &= mask;
9818 } else {
9819 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9820 if (cmd->speed != SPEED_1000)
9821 return -EINVAL;
9822
9823 if (cmd->duplex != DUPLEX_FULL)
9824 return -EINVAL;
9825 } else {
9826 if (cmd->speed != SPEED_100 &&
9827 cmd->speed != SPEED_10)
9828 return -EINVAL;
9829 }
9830 }
9831
9832 tg3_full_lock(tp, 0);
9833
9834 tp->link_config.autoneg = cmd->autoneg;
9835 if (cmd->autoneg == AUTONEG_ENABLE) {
9836 tp->link_config.advertising = (cmd->advertising |
9837 ADVERTISED_Autoneg);
9838 tp->link_config.speed = SPEED_INVALID;
9839 tp->link_config.duplex = DUPLEX_INVALID;
9840 } else {
9841 tp->link_config.advertising = 0;
9842 tp->link_config.speed = cmd->speed;
9843 tp->link_config.duplex = cmd->duplex;
9844 }
9845
9846 tp->link_config.orig_speed = tp->link_config.speed;
9847 tp->link_config.orig_duplex = tp->link_config.duplex;
9848 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9849
9850 if (netif_running(dev))
9851 tg3_setup_phy(tp, 1);
9852
9853 tg3_full_unlock(tp);
9854
9855 return 0;
9856}
9857
9858static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9859{
9860 struct tg3 *tp = netdev_priv(dev);
9861
9862 strcpy(info->driver, DRV_MODULE_NAME);
9863 strcpy(info->version, DRV_MODULE_VERSION);
9864 strcpy(info->fw_version, tp->fw_ver);
9865 strcpy(info->bus_info, pci_name(tp->pdev));
9866}
9867
9868static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9869{
9870 struct tg3 *tp = netdev_priv(dev);
9871
9872 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9873 device_can_wakeup(&tp->pdev->dev))
9874 wol->supported = WAKE_MAGIC;
9875 else
9876 wol->supported = 0;
9877 wol->wolopts = 0;
9878 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9879 device_can_wakeup(&tp->pdev->dev))
9880 wol->wolopts = WAKE_MAGIC;
9881 memset(&wol->sopass, 0, sizeof(wol->sopass));
9882}
9883
9884static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9885{
9886 struct tg3 *tp = netdev_priv(dev);
9887 struct device *dp = &tp->pdev->dev;
9888
9889 if (wol->wolopts & ~WAKE_MAGIC)
9890 return -EINVAL;
9891 if ((wol->wolopts & WAKE_MAGIC) &&
9892 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9893 return -EINVAL;
9894
9895 spin_lock_bh(&tp->lock);
9896 if (wol->wolopts & WAKE_MAGIC) {
9897 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9898 device_set_wakeup_enable(dp, true);
9899 } else {
9900 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9901 device_set_wakeup_enable(dp, false);
9902 }
9903 spin_unlock_bh(&tp->lock);
9904
9905 return 0;
9906}
9907
9908static u32 tg3_get_msglevel(struct net_device *dev)
9909{
9910 struct tg3 *tp = netdev_priv(dev);
9911 return tp->msg_enable;
9912}
9913
9914static void tg3_set_msglevel(struct net_device *dev, u32 value)
9915{
9916 struct tg3 *tp = netdev_priv(dev);
9917 tp->msg_enable = value;
9918}
9919
9920static int tg3_set_tso(struct net_device *dev, u32 value)
9921{
9922 struct tg3 *tp = netdev_priv(dev);
9923
9924 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9925 if (value)
9926 return -EINVAL;
9927 return 0;
9928 }
9929 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9930 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9931 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9932 if (value) {
9933 dev->features |= NETIF_F_TSO6;
9934 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9935 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9936 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9937 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9940 dev->features |= NETIF_F_TSO_ECN;
9941 } else
9942 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9943 }
9944 return ethtool_op_set_tso(dev, value);
9945}
9946
9947static int tg3_nway_reset(struct net_device *dev)
9948{
9949 struct tg3 *tp = netdev_priv(dev);
9950 int r;
9951
9952 if (!netif_running(dev))
9953 return -EAGAIN;
9954
9955 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9956 return -EINVAL;
9957
9958 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9959 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9960 return -EAGAIN;
9961 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9962 } else {
9963 u32 bmcr;
9964
9965 spin_lock_bh(&tp->lock);
9966 r = -EINVAL;
9967 tg3_readphy(tp, MII_BMCR, &bmcr);
9968 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9969 ((bmcr & BMCR_ANENABLE) ||
9970 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9971 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9972 BMCR_ANENABLE);
9973 r = 0;
9974 }
9975 spin_unlock_bh(&tp->lock);
9976 }
9977
9978 return r;
9979}
9980
9981static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9982{
9983 struct tg3 *tp = netdev_priv(dev);
9984
9985 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9986 ering->rx_mini_max_pending = 0;
9987 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9988 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9989 else
9990 ering->rx_jumbo_max_pending = 0;
9991
9992 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9993
9994 ering->rx_pending = tp->rx_pending;
9995 ering->rx_mini_pending = 0;
9996 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9997 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9998 else
9999 ering->rx_jumbo_pending = 0;
10000
10001 ering->tx_pending = tp->napi[0].tx_pending;
10002}
10003
10004static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10005{
10006 struct tg3 *tp = netdev_priv(dev);
10007 int i, irq_sync = 0, err = 0;
10008
10009 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
10010 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
10011 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10012 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10013 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10014 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10015 return -EINVAL;
10016
10017 if (netif_running(dev)) {
10018 tg3_phy_stop(tp);
10019 tg3_netif_stop(tp);
10020 irq_sync = 1;
10021 }
10022
10023 tg3_full_lock(tp, irq_sync);
10024
10025 tp->rx_pending = ering->rx_pending;
10026
10027 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10028 tp->rx_pending > 63)
10029 tp->rx_pending = 63;
10030 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10031
10032 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10033 tp->napi[i].tx_pending = ering->tx_pending;
10034
10035 if (netif_running(dev)) {
10036 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10037 err = tg3_restart_hw(tp, 1);
10038 if (!err)
10039 tg3_netif_start(tp);
10040 }
10041
10042 tg3_full_unlock(tp);
10043
10044 if (irq_sync && !err)
10045 tg3_phy_start(tp);
10046
10047 return err;
10048}
10049
10050static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10051{
10052 struct tg3 *tp = netdev_priv(dev);
10053
10054 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10055
10056 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10057 epause->rx_pause = 1;
10058 else
10059 epause->rx_pause = 0;
10060
10061 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10062 epause->tx_pause = 1;
10063 else
10064 epause->tx_pause = 0;
10065}
10066
10067static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10068{
10069 struct tg3 *tp = netdev_priv(dev);
10070 int err = 0;
10071
10072 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10073 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10074 return -EAGAIN;
10075
10076 if (epause->autoneg) {
10077 u32 newadv;
10078 struct phy_device *phydev;
10079
10080 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10081
10082 if (epause->rx_pause) {
10083 if (epause->tx_pause)
10084 newadv = ADVERTISED_Pause;
10085 else
10086 newadv = ADVERTISED_Pause |
10087 ADVERTISED_Asym_Pause;
10088 } else if (epause->tx_pause) {
10089 newadv = ADVERTISED_Asym_Pause;
10090 } else
10091 newadv = 0;
10092
10093 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10094 u32 oldadv = phydev->advertising &
10095 (ADVERTISED_Pause |
10096 ADVERTISED_Asym_Pause);
10097 if (oldadv != newadv) {
10098 phydev->advertising &=
10099 ~(ADVERTISED_Pause |
10100 ADVERTISED_Asym_Pause);
10101 phydev->advertising |= newadv;
10102 err = phy_start_aneg(phydev);
10103 }
10104 } else {
10105 tp->link_config.advertising &=
10106 ~(ADVERTISED_Pause |
10107 ADVERTISED_Asym_Pause);
10108 tp->link_config.advertising |= newadv;
10109 }
10110 } else {
10111 if (epause->rx_pause)
10112 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10113 else
10114 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10115
10116 if (epause->tx_pause)
10117 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10118 else
10119 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10120
10121 if (netif_running(dev))
10122 tg3_setup_flow_control(tp, 0, 0);
10123 }
10124 } else {
10125 int irq_sync = 0;
10126
10127 if (netif_running(dev)) {
10128 tg3_netif_stop(tp);
10129 irq_sync = 1;
10130 }
10131
10132 tg3_full_lock(tp, irq_sync);
10133
10134 if (epause->autoneg)
10135 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10136 else
10137 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10138 if (epause->rx_pause)
10139 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10140 else
10141 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10142 if (epause->tx_pause)
10143 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10144 else
10145 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10146
10147 if (netif_running(dev)) {
10148 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10149 err = tg3_restart_hw(tp, 1);
10150 if (!err)
10151 tg3_netif_start(tp);
10152 }
10153
10154 tg3_full_unlock(tp);
10155 }
10156
10157 return err;
10158}
10159
10160static u32 tg3_get_rx_csum(struct net_device *dev)
10161{
10162 struct tg3 *tp = netdev_priv(dev);
10163 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10164}
10165
10166static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10167{
10168 struct tg3 *tp = netdev_priv(dev);
10169
10170 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10171 if (data != 0)
10172 return -EINVAL;
10173 return 0;
10174 }
10175
10176 spin_lock_bh(&tp->lock);
10177 if (data)
10178 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10179 else
10180 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10181 spin_unlock_bh(&tp->lock);
10182
10183 return 0;
10184}
10185
10186static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10187{
10188 struct tg3 *tp = netdev_priv(dev);
10189
10190 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10191 if (data != 0)
10192 return -EINVAL;
10193 return 0;
10194 }
10195
10196 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10197 ethtool_op_set_tx_ipv6_csum(dev, data);
10198 else
10199 ethtool_op_set_tx_csum(dev, data);
10200
10201 return 0;
10202}
10203
10204static int tg3_get_sset_count (struct net_device *dev, int sset)
10205{
10206 switch (sset) {
10207 case ETH_SS_TEST:
10208 return TG3_NUM_TEST;
10209 case ETH_SS_STATS:
10210 return TG3_NUM_STATS;
10211 default:
10212 return -EOPNOTSUPP;
10213 }
10214}
10215
10216static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10217{
10218 switch (stringset) {
10219 case ETH_SS_STATS:
10220 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10221 break;
10222 case ETH_SS_TEST:
10223 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10224 break;
10225 default:
10226 WARN_ON(1); /* we need a WARN() */
10227 break;
10228 }
10229}
10230
10231static int tg3_phys_id(struct net_device *dev, u32 data)
10232{
10233 struct tg3 *tp = netdev_priv(dev);
10234 int i;
10235
10236 if (!netif_running(tp->dev))
10237 return -EAGAIN;
10238
10239 if (data == 0)
10240 data = UINT_MAX / 2;
10241
10242 for (i = 0; i < (data * 2); i++) {
10243 if ((i % 2) == 0)
10244 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10245 LED_CTRL_1000MBPS_ON |
10246 LED_CTRL_100MBPS_ON |
10247 LED_CTRL_10MBPS_ON |
10248 LED_CTRL_TRAFFIC_OVERRIDE |
10249 LED_CTRL_TRAFFIC_BLINK |
10250 LED_CTRL_TRAFFIC_LED);
10251
10252 else
10253 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10254 LED_CTRL_TRAFFIC_OVERRIDE);
10255
10256 if (msleep_interruptible(500))
10257 break;
10258 }
10259 tw32(MAC_LED_CTRL, tp->led_ctrl);
10260 return 0;
10261}
10262
10263static void tg3_get_ethtool_stats (struct net_device *dev,
10264 struct ethtool_stats *estats, u64 *tmp_stats)
10265{
10266 struct tg3 *tp = netdev_priv(dev);
10267 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10268}
10269
10270#define NVRAM_TEST_SIZE 0x100
10271#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10272#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10273#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10274#define NVRAM_SELFBOOT_HW_SIZE 0x20
10275#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10276
10277static int tg3_test_nvram(struct tg3 *tp)
10278{
10279 u32 csum, magic;
10280 __be32 *buf;
10281 int i, j, k, err = 0, size;
10282
10283 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10284 return 0;
10285
10286 if (tg3_nvram_read(tp, 0, &magic) != 0)
10287 return -EIO;
10288
10289 if (magic == TG3_EEPROM_MAGIC)
10290 size = NVRAM_TEST_SIZE;
10291 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10292 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10293 TG3_EEPROM_SB_FORMAT_1) {
10294 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10295 case TG3_EEPROM_SB_REVISION_0:
10296 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10297 break;
10298 case TG3_EEPROM_SB_REVISION_2:
10299 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10300 break;
10301 case TG3_EEPROM_SB_REVISION_3:
10302 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10303 break;
10304 default:
10305 return 0;
10306 }
10307 } else
10308 return 0;
10309 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10310 size = NVRAM_SELFBOOT_HW_SIZE;
10311 else
10312 return -EIO;
10313
10314 buf = kmalloc(size, GFP_KERNEL);
10315 if (buf == NULL)
10316 return -ENOMEM;
10317
10318 err = -EIO;
10319 for (i = 0, j = 0; i < size; i += 4, j++) {
10320 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10321 if (err)
10322 break;
10323 }
10324 if (i < size)
10325 goto out;
10326
10327 /* Selfboot format */
10328 magic = be32_to_cpu(buf[0]);
10329 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10330 TG3_EEPROM_MAGIC_FW) {
10331 u8 *buf8 = (u8 *) buf, csum8 = 0;
10332
10333 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10334 TG3_EEPROM_SB_REVISION_2) {
10335 /* For rev 2, the csum doesn't include the MBA. */
10336 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10337 csum8 += buf8[i];
10338 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10339 csum8 += buf8[i];
10340 } else {
10341 for (i = 0; i < size; i++)
10342 csum8 += buf8[i];
10343 }
10344
10345 if (csum8 == 0) {
10346 err = 0;
10347 goto out;
10348 }
10349
10350 err = -EIO;
10351 goto out;
10352 }
10353
10354 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10355 TG3_EEPROM_MAGIC_HW) {
10356 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10357 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10358 u8 *buf8 = (u8 *) buf;
10359
10360 /* Separate the parity bits and the data bytes. */
10361 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10362 if ((i == 0) || (i == 8)) {
10363 int l;
10364 u8 msk;
10365
10366 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10367 parity[k++] = buf8[i] & msk;
10368 i++;
10369 }
10370 else if (i == 16) {
10371 int l;
10372 u8 msk;
10373
10374 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10375 parity[k++] = buf8[i] & msk;
10376 i++;
10377
10378 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10379 parity[k++] = buf8[i] & msk;
10380 i++;
10381 }
10382 data[j++] = buf8[i];
10383 }
10384
10385 err = -EIO;
10386 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10387 u8 hw8 = hweight8(data[i]);
10388
10389 if ((hw8 & 0x1) && parity[i])
10390 goto out;
10391 else if (!(hw8 & 0x1) && !parity[i])
10392 goto out;
10393 }
10394 err = 0;
10395 goto out;
10396 }
10397
10398 /* Bootstrap checksum at offset 0x10 */
10399 csum = calc_crc((unsigned char *) buf, 0x10);
10400 if (csum != be32_to_cpu(buf[0x10/4]))
10401 goto out;
10402
10403 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10404 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10405 if (csum != be32_to_cpu(buf[0xfc/4]))
10406 goto out;
10407
10408 err = 0;
10409
10410out:
10411 kfree(buf);
10412 return err;
10413}
10414
10415#define TG3_SERDES_TIMEOUT_SEC 2
10416#define TG3_COPPER_TIMEOUT_SEC 6
10417
10418static int tg3_test_link(struct tg3 *tp)
10419{
10420 int i, max;
10421
10422 if (!netif_running(tp->dev))
10423 return -ENODEV;
10424
10425 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10426 max = TG3_SERDES_TIMEOUT_SEC;
10427 else
10428 max = TG3_COPPER_TIMEOUT_SEC;
10429
10430 for (i = 0; i < max; i++) {
10431 if (netif_carrier_ok(tp->dev))
10432 return 0;
10433
10434 if (msleep_interruptible(1000))
10435 break;
10436 }
10437
10438 return -EIO;
10439}
10440
10441/* Only test the commonly used registers */
10442static int tg3_test_registers(struct tg3 *tp)
10443{
10444 int i, is_5705, is_5750;
10445 u32 offset, read_mask, write_mask, val, save_val, read_val;
10446 static struct {
10447 u16 offset;
10448 u16 flags;
10449#define TG3_FL_5705 0x1
10450#define TG3_FL_NOT_5705 0x2
10451#define TG3_FL_NOT_5788 0x4
10452#define TG3_FL_NOT_5750 0x8
10453 u32 read_mask;
10454 u32 write_mask;
10455 } reg_tbl[] = {
10456 /* MAC Control Registers */
10457 { MAC_MODE, TG3_FL_NOT_5705,
10458 0x00000000, 0x00ef6f8c },
10459 { MAC_MODE, TG3_FL_5705,
10460 0x00000000, 0x01ef6b8c },
10461 { MAC_STATUS, TG3_FL_NOT_5705,
10462 0x03800107, 0x00000000 },
10463 { MAC_STATUS, TG3_FL_5705,
10464 0x03800100, 0x00000000 },
10465 { MAC_ADDR_0_HIGH, 0x0000,
10466 0x00000000, 0x0000ffff },
10467 { MAC_ADDR_0_LOW, 0x0000,
10468 0x00000000, 0xffffffff },
10469 { MAC_RX_MTU_SIZE, 0x0000,
10470 0x00000000, 0x0000ffff },
10471 { MAC_TX_MODE, 0x0000,
10472 0x00000000, 0x00000070 },
10473 { MAC_TX_LENGTHS, 0x0000,
10474 0x00000000, 0x00003fff },
10475 { MAC_RX_MODE, TG3_FL_NOT_5705,
10476 0x00000000, 0x000007fc },
10477 { MAC_RX_MODE, TG3_FL_5705,
10478 0x00000000, 0x000007dc },
10479 { MAC_HASH_REG_0, 0x0000,
10480 0x00000000, 0xffffffff },
10481 { MAC_HASH_REG_1, 0x0000,
10482 0x00000000, 0xffffffff },
10483 { MAC_HASH_REG_2, 0x0000,
10484 0x00000000, 0xffffffff },
10485 { MAC_HASH_REG_3, 0x0000,
10486 0x00000000, 0xffffffff },
10487
10488 /* Receive Data and Receive BD Initiator Control Registers. */
10489 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10490 0x00000000, 0xffffffff },
10491 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10492 0x00000000, 0xffffffff },
10493 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10494 0x00000000, 0x00000003 },
10495 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10496 0x00000000, 0xffffffff },
10497 { RCVDBDI_STD_BD+0, 0x0000,
10498 0x00000000, 0xffffffff },
10499 { RCVDBDI_STD_BD+4, 0x0000,
10500 0x00000000, 0xffffffff },
10501 { RCVDBDI_STD_BD+8, 0x0000,
10502 0x00000000, 0xffff0002 },
10503 { RCVDBDI_STD_BD+0xc, 0x0000,
10504 0x00000000, 0xffffffff },
10505
10506 /* Receive BD Initiator Control Registers. */
10507 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10508 0x00000000, 0xffffffff },
10509 { RCVBDI_STD_THRESH, TG3_FL_5705,
10510 0x00000000, 0x000003ff },
10511 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10512 0x00000000, 0xffffffff },
10513
10514 /* Host Coalescing Control Registers. */
10515 { HOSTCC_MODE, TG3_FL_NOT_5705,
10516 0x00000000, 0x00000004 },
10517 { HOSTCC_MODE, TG3_FL_5705,
10518 0x00000000, 0x000000f6 },
10519 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10520 0x00000000, 0xffffffff },
10521 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10522 0x00000000, 0x000003ff },
10523 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10524 0x00000000, 0xffffffff },
10525 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10526 0x00000000, 0x000003ff },
10527 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10528 0x00000000, 0xffffffff },
10529 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10530 0x00000000, 0x000000ff },
10531 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10532 0x00000000, 0xffffffff },
10533 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10534 0x00000000, 0x000000ff },
10535 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10536 0x00000000, 0xffffffff },
10537 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10538 0x00000000, 0xffffffff },
10539 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10540 0x00000000, 0xffffffff },
10541 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10542 0x00000000, 0x000000ff },
10543 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10544 0x00000000, 0xffffffff },
10545 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10546 0x00000000, 0x000000ff },
10547 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10548 0x00000000, 0xffffffff },
10549 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10550 0x00000000, 0xffffffff },
10551 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10552 0x00000000, 0xffffffff },
10553 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10554 0x00000000, 0xffffffff },
10555 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10556 0x00000000, 0xffffffff },
10557 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10558 0xffffffff, 0x00000000 },
10559 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10560 0xffffffff, 0x00000000 },
10561
10562 /* Buffer Manager Control Registers. */
10563 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10564 0x00000000, 0x007fff80 },
10565 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10566 0x00000000, 0x007fffff },
10567 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10568 0x00000000, 0x0000003f },
10569 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10570 0x00000000, 0x000001ff },
10571 { BUFMGR_MB_HIGH_WATER, 0x0000,
10572 0x00000000, 0x000001ff },
10573 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10574 0xffffffff, 0x00000000 },
10575 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10576 0xffffffff, 0x00000000 },
10577
10578 /* Mailbox Registers */
10579 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10580 0x00000000, 0x000001ff },
10581 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10582 0x00000000, 0x000001ff },
10583 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10584 0x00000000, 0x000007ff },
10585 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10586 0x00000000, 0x000001ff },
10587
10588 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10589 };
10590
10591 is_5705 = is_5750 = 0;
10592 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10593 is_5705 = 1;
10594 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10595 is_5750 = 1;
10596 }
10597
10598 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10599 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10600 continue;
10601
10602 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10603 continue;
10604
10605 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10606 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10607 continue;
10608
10609 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10610 continue;
10611
10612 offset = (u32) reg_tbl[i].offset;
10613 read_mask = reg_tbl[i].read_mask;
10614 write_mask = reg_tbl[i].write_mask;
10615
10616 /* Save the original register content */
10617 save_val = tr32(offset);
10618
10619 /* Determine the read-only value. */
10620 read_val = save_val & read_mask;
10621
10622 /* Write zero to the register, then make sure the read-only bits
10623 * are not changed and the read/write bits are all zeros.
10624 */
10625 tw32(offset, 0);
10626
10627 val = tr32(offset);
10628
10629 /* Test the read-only and read/write bits. */
10630 if (((val & read_mask) != read_val) || (val & write_mask))
10631 goto out;
10632
10633 /* Write ones to all the bits defined by RdMask and WrMask, then
10634 * make sure the read-only bits are not changed and the
10635 * read/write bits are all ones.
10636 */
10637 tw32(offset, read_mask | write_mask);
10638
10639 val = tr32(offset);
10640
10641 /* Test the read-only bits. */
10642 if ((val & read_mask) != read_val)
10643 goto out;
10644
10645 /* Test the read/write bits. */
10646 if ((val & write_mask) != write_mask)
10647 goto out;
10648
10649 tw32(offset, save_val);
10650 }
10651
10652 return 0;
10653
10654out:
10655 if (netif_msg_hw(tp))
10656 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10657 offset);
10658 tw32(offset, save_val);
10659 return -EIO;
10660}
10661
10662static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10663{
10664 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10665 int i;
10666 u32 j;
10667
10668 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10669 for (j = 0; j < len; j += 4) {
10670 u32 val;
10671
10672 tg3_write_mem(tp, offset + j, test_pattern[i]);
10673 tg3_read_mem(tp, offset + j, &val);
10674 if (val != test_pattern[i])
10675 return -EIO;
10676 }
10677 }
10678 return 0;
10679}
10680
10681static int tg3_test_memory(struct tg3 *tp)
10682{
10683 static struct mem_entry {
10684 u32 offset;
10685 u32 len;
10686 } mem_tbl_570x[] = {
10687 { 0x00000000, 0x00b50},
10688 { 0x00002000, 0x1c000},
10689 { 0xffffffff, 0x00000}
10690 }, mem_tbl_5705[] = {
10691 { 0x00000100, 0x0000c},
10692 { 0x00000200, 0x00008},
10693 { 0x00004000, 0x00800},
10694 { 0x00006000, 0x01000},
10695 { 0x00008000, 0x02000},
10696 { 0x00010000, 0x0e000},
10697 { 0xffffffff, 0x00000}
10698 }, mem_tbl_5755[] = {
10699 { 0x00000200, 0x00008},
10700 { 0x00004000, 0x00800},
10701 { 0x00006000, 0x00800},
10702 { 0x00008000, 0x02000},
10703 { 0x00010000, 0x0c000},
10704 { 0xffffffff, 0x00000}
10705 }, mem_tbl_5906[] = {
10706 { 0x00000200, 0x00008},
10707 { 0x00004000, 0x00400},
10708 { 0x00006000, 0x00400},
10709 { 0x00008000, 0x01000},
10710 { 0x00010000, 0x01000},
10711 { 0xffffffff, 0x00000}
10712 }, mem_tbl_5717[] = {
10713 { 0x00000200, 0x00008},
10714 { 0x00010000, 0x0a000},
10715 { 0x00020000, 0x13c00},
10716 { 0xffffffff, 0x00000}
10717 }, mem_tbl_57765[] = {
10718 { 0x00000200, 0x00008},
10719 { 0x00004000, 0x00800},
10720 { 0x00006000, 0x09800},
10721 { 0x00010000, 0x0a000},
10722 { 0xffffffff, 0x00000}
10723 };
10724 struct mem_entry *mem_tbl;
10725 int err = 0;
10726 int i;
10727
10728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10729 mem_tbl = mem_tbl_5717;
10730 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10731 mem_tbl = mem_tbl_57765;
10732 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10733 mem_tbl = mem_tbl_5755;
10734 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10735 mem_tbl = mem_tbl_5906;
10736 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10737 mem_tbl = mem_tbl_5705;
10738 else
10739 mem_tbl = mem_tbl_570x;
10740
10741 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10742 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10743 mem_tbl[i].len)) != 0)
10744 break;
10745 }
10746
10747 return err;
10748}
10749
10750#define TG3_MAC_LOOPBACK 0
10751#define TG3_PHY_LOOPBACK 1
10752
10753static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10754{
10755 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10756 u32 desc_idx, coal_now;
10757 struct sk_buff *skb, *rx_skb;
10758 u8 *tx_data;
10759 dma_addr_t map;
10760 int num_pkts, tx_len, rx_len, i, err;
10761 struct tg3_rx_buffer_desc *desc;
10762 struct tg3_napi *tnapi, *rnapi;
10763 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10764
10765 if (tp->irq_cnt > 1) {
10766 tnapi = &tp->napi[1];
10767 rnapi = &tp->napi[1];
10768 } else {
10769 tnapi = &tp->napi[0];
10770 rnapi = &tp->napi[0];
10771 }
10772 coal_now = tnapi->coal_now | rnapi->coal_now;
10773
10774 if (loopback_mode == TG3_MAC_LOOPBACK) {
10775 /* HW errata - mac loopback fails in some cases on 5780.
10776 * Normal traffic and PHY loopback are not affected by
10777 * errata.
10778 */
10779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10780 return 0;
10781
10782 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10783 MAC_MODE_PORT_INT_LPBACK;
10784 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10785 mac_mode |= MAC_MODE_LINK_POLARITY;
10786 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10787 mac_mode |= MAC_MODE_PORT_MODE_MII;
10788 else
10789 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10790 tw32(MAC_MODE, mac_mode);
10791 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10792 u32 val;
10793
10794 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10795 tg3_phy_fet_toggle_apd(tp, false);
10796 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10797 } else
10798 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10799
10800 tg3_phy_toggle_automdix(tp, 0);
10801
10802 tg3_writephy(tp, MII_BMCR, val);
10803 udelay(40);
10804
10805 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10806 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10807 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10808 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10809 mac_mode |= MAC_MODE_PORT_MODE_MII;
10810 } else
10811 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10812
10813 /* reset to prevent losing 1st rx packet intermittently */
10814 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10815 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10816 udelay(10);
10817 tw32_f(MAC_RX_MODE, tp->rx_mode);
10818 }
10819 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10820 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10821 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10822 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10823 mac_mode |= MAC_MODE_LINK_POLARITY;
10824 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10825 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10826 }
10827 tw32(MAC_MODE, mac_mode);
10828 }
10829 else
10830 return -EINVAL;
10831
10832 err = -EIO;
10833
10834 tx_len = 1514;
10835 skb = netdev_alloc_skb(tp->dev, tx_len);
10836 if (!skb)
10837 return -ENOMEM;
10838
10839 tx_data = skb_put(skb, tx_len);
10840 memcpy(tx_data, tp->dev->dev_addr, 6);
10841 memset(tx_data + 6, 0x0, 8);
10842
10843 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10844
10845 for (i = 14; i < tx_len; i++)
10846 tx_data[i] = (u8) (i & 0xff);
10847
10848 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10849 if (pci_dma_mapping_error(tp->pdev, map)) {
10850 dev_kfree_skb(skb);
10851 return -EIO;
10852 }
10853
10854 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10855 rnapi->coal_now);
10856
10857 udelay(10);
10858
10859 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10860
10861 num_pkts = 0;
10862
10863 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10864
10865 tnapi->tx_prod++;
10866 num_pkts++;
10867
10868 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10869 tr32_mailbox(tnapi->prodmbox);
10870
10871 udelay(10);
10872
10873 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10874 for (i = 0; i < 35; i++) {
10875 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10876 coal_now);
10877
10878 udelay(10);
10879
10880 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10881 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10882 if ((tx_idx == tnapi->tx_prod) &&
10883 (rx_idx == (rx_start_idx + num_pkts)))
10884 break;
10885 }
10886
10887 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10888 dev_kfree_skb(skb);
10889
10890 if (tx_idx != tnapi->tx_prod)
10891 goto out;
10892
10893 if (rx_idx != rx_start_idx + num_pkts)
10894 goto out;
10895
10896 desc = &rnapi->rx_rcb[rx_start_idx];
10897 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10898 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10899 if (opaque_key != RXD_OPAQUE_RING_STD)
10900 goto out;
10901
10902 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10903 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10904 goto out;
10905
10906 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10907 if (rx_len != tx_len)
10908 goto out;
10909
10910 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10911
10912 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10913 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10914
10915 for (i = 14; i < tx_len; i++) {
10916 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10917 goto out;
10918 }
10919 err = 0;
10920
10921 /* tg3_free_rings will unmap and free the rx_skb */
10922out:
10923 return err;
10924}
10925
10926#define TG3_MAC_LOOPBACK_FAILED 1
10927#define TG3_PHY_LOOPBACK_FAILED 2
10928#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10929 TG3_PHY_LOOPBACK_FAILED)
10930
10931static int tg3_test_loopback(struct tg3 *tp)
10932{
10933 int err = 0;
10934 u32 cpmuctrl = 0;
10935
10936 if (!netif_running(tp->dev))
10937 return TG3_LOOPBACK_FAILED;
10938
10939 err = tg3_reset_hw(tp, 1);
10940 if (err)
10941 return TG3_LOOPBACK_FAILED;
10942
10943 /* Turn off gphy autopowerdown. */
10944 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10945 tg3_phy_toggle_apd(tp, false);
10946
10947 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10948 int i;
10949 u32 status;
10950
10951 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10952
10953 /* Wait for up to 40 microseconds to acquire lock. */
10954 for (i = 0; i < 4; i++) {
10955 status = tr32(TG3_CPMU_MUTEX_GNT);
10956 if (status == CPMU_MUTEX_GNT_DRIVER)
10957 break;
10958 udelay(10);
10959 }
10960
10961 if (status != CPMU_MUTEX_GNT_DRIVER)
10962 return TG3_LOOPBACK_FAILED;
10963
10964 /* Turn off link-based power management. */
10965 cpmuctrl = tr32(TG3_CPMU_CTRL);
10966 tw32(TG3_CPMU_CTRL,
10967 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10968 CPMU_CTRL_LINK_AWARE_MODE));
10969 }
10970
10971 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10972 err |= TG3_MAC_LOOPBACK_FAILED;
10973
10974 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10975 tw32(TG3_CPMU_CTRL, cpmuctrl);
10976
10977 /* Release the mutex */
10978 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10979 }
10980
10981 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10982 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10983 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10984 err |= TG3_PHY_LOOPBACK_FAILED;
10985 }
10986
10987 /* Re-enable gphy autopowerdown. */
10988 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10989 tg3_phy_toggle_apd(tp, true);
10990
10991 return err;
10992}
10993
10994static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10995 u64 *data)
10996{
10997 struct tg3 *tp = netdev_priv(dev);
10998
10999 if (tp->link_config.phy_is_low_power)
11000 tg3_set_power_state(tp, PCI_D0);
11001
11002 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11003
11004 if (tg3_test_nvram(tp) != 0) {
11005 etest->flags |= ETH_TEST_FL_FAILED;
11006 data[0] = 1;
11007 }
11008 if (tg3_test_link(tp) != 0) {
11009 etest->flags |= ETH_TEST_FL_FAILED;
11010 data[1] = 1;
11011 }
11012 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11013 int err, err2 = 0, irq_sync = 0;
11014
11015 if (netif_running(dev)) {
11016 tg3_phy_stop(tp);
11017 tg3_netif_stop(tp);
11018 irq_sync = 1;
11019 }
11020
11021 tg3_full_lock(tp, irq_sync);
11022
11023 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11024 err = tg3_nvram_lock(tp);
11025 tg3_halt_cpu(tp, RX_CPU_BASE);
11026 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11027 tg3_halt_cpu(tp, TX_CPU_BASE);
11028 if (!err)
11029 tg3_nvram_unlock(tp);
11030
11031 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11032 tg3_phy_reset(tp);
11033
11034 if (tg3_test_registers(tp) != 0) {
11035 etest->flags |= ETH_TEST_FL_FAILED;
11036 data[2] = 1;
11037 }
11038 if (tg3_test_memory(tp) != 0) {
11039 etest->flags |= ETH_TEST_FL_FAILED;
11040 data[3] = 1;
11041 }
11042 if ((data[4] = tg3_test_loopback(tp)) != 0)
11043 etest->flags |= ETH_TEST_FL_FAILED;
11044
11045 tg3_full_unlock(tp);
11046
11047 if (tg3_test_interrupt(tp) != 0) {
11048 etest->flags |= ETH_TEST_FL_FAILED;
11049 data[5] = 1;
11050 }
11051
11052 tg3_full_lock(tp, 0);
11053
11054 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11055 if (netif_running(dev)) {
11056 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11057 err2 = tg3_restart_hw(tp, 1);
11058 if (!err2)
11059 tg3_netif_start(tp);
11060 }
11061
11062 tg3_full_unlock(tp);
11063
11064 if (irq_sync && !err2)
11065 tg3_phy_start(tp);
11066 }
11067 if (tp->link_config.phy_is_low_power)
11068 tg3_set_power_state(tp, PCI_D3hot);
11069
11070}
11071
11072static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11073{
11074 struct mii_ioctl_data *data = if_mii(ifr);
11075 struct tg3 *tp = netdev_priv(dev);
11076 int err;
11077
11078 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11079 struct phy_device *phydev;
11080 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11081 return -EAGAIN;
11082 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11083 return phy_mii_ioctl(phydev, data, cmd);
11084 }
11085
11086 switch(cmd) {
11087 case SIOCGMIIPHY:
11088 data->phy_id = tp->phy_addr;
11089
11090 /* fallthru */
11091 case SIOCGMIIREG: {
11092 u32 mii_regval;
11093
11094 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11095 break; /* We have no PHY */
11096
11097 if (tp->link_config.phy_is_low_power)
11098 return -EAGAIN;
11099
11100 spin_lock_bh(&tp->lock);
11101 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11102 spin_unlock_bh(&tp->lock);
11103
11104 data->val_out = mii_regval;
11105
11106 return err;
11107 }
11108
11109 case SIOCSMIIREG:
11110 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11111 break; /* We have no PHY */
11112
11113 if (tp->link_config.phy_is_low_power)
11114 return -EAGAIN;
11115
11116 spin_lock_bh(&tp->lock);
11117 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11118 spin_unlock_bh(&tp->lock);
11119
11120 return err;
11121
11122 default:
11123 /* do nothing */
11124 break;
11125 }
11126 return -EOPNOTSUPP;
11127}
11128
11129#if TG3_VLAN_TAG_USED
11130static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11131{
11132 struct tg3 *tp = netdev_priv(dev);
11133
11134 if (!netif_running(dev)) {
11135 tp->vlgrp = grp;
11136 return;
11137 }
11138
11139 tg3_netif_stop(tp);
11140
11141 tg3_full_lock(tp, 0);
11142
11143 tp->vlgrp = grp;
11144
11145 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11146 __tg3_set_rx_mode(dev);
11147
11148 tg3_netif_start(tp);
11149
11150 tg3_full_unlock(tp);
11151}
11152#endif
11153
11154static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11155{
11156 struct tg3 *tp = netdev_priv(dev);
11157
11158 memcpy(ec, &tp->coal, sizeof(*ec));
11159 return 0;
11160}
11161
11162static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11163{
11164 struct tg3 *tp = netdev_priv(dev);
11165 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11166 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11167
11168 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11169 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11170 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11171 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11172 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11173 }
11174
11175 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11176 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11177 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11178 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11179 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11180 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11181 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11182 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11183 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11184 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11185 return -EINVAL;
11186
11187 /* No rx interrupts will be generated if both are zero */
11188 if ((ec->rx_coalesce_usecs == 0) &&
11189 (ec->rx_max_coalesced_frames == 0))
11190 return -EINVAL;
11191
11192 /* No tx interrupts will be generated if both are zero */
11193 if ((ec->tx_coalesce_usecs == 0) &&
11194 (ec->tx_max_coalesced_frames == 0))
11195 return -EINVAL;
11196
11197 /* Only copy relevant parameters, ignore all others. */
11198 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11199 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11200 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11201 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11202 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11203 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11204 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11205 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11206 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11207
11208 if (netif_running(dev)) {
11209 tg3_full_lock(tp, 0);
11210 __tg3_set_coalesce(tp, &tp->coal);
11211 tg3_full_unlock(tp);
11212 }
11213 return 0;
11214}
11215
11216static const struct ethtool_ops tg3_ethtool_ops = {
11217 .get_settings = tg3_get_settings,
11218 .set_settings = tg3_set_settings,
11219 .get_drvinfo = tg3_get_drvinfo,
11220 .get_regs_len = tg3_get_regs_len,
11221 .get_regs = tg3_get_regs,
11222 .get_wol = tg3_get_wol,
11223 .set_wol = tg3_set_wol,
11224 .get_msglevel = tg3_get_msglevel,
11225 .set_msglevel = tg3_set_msglevel,
11226 .nway_reset = tg3_nway_reset,
11227 .get_link = ethtool_op_get_link,
11228 .get_eeprom_len = tg3_get_eeprom_len,
11229 .get_eeprom = tg3_get_eeprom,
11230 .set_eeprom = tg3_set_eeprom,
11231 .get_ringparam = tg3_get_ringparam,
11232 .set_ringparam = tg3_set_ringparam,
11233 .get_pauseparam = tg3_get_pauseparam,
11234 .set_pauseparam = tg3_set_pauseparam,
11235 .get_rx_csum = tg3_get_rx_csum,
11236 .set_rx_csum = tg3_set_rx_csum,
11237 .set_tx_csum = tg3_set_tx_csum,
11238 .set_sg = ethtool_op_set_sg,
11239 .set_tso = tg3_set_tso,
11240 .self_test = tg3_self_test,
11241 .get_strings = tg3_get_strings,
11242 .phys_id = tg3_phys_id,
11243 .get_ethtool_stats = tg3_get_ethtool_stats,
11244 .get_coalesce = tg3_get_coalesce,
11245 .set_coalesce = tg3_set_coalesce,
11246 .get_sset_count = tg3_get_sset_count,
11247};
11248
11249static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11250{
11251 u32 cursize, val, magic;
11252
11253 tp->nvram_size = EEPROM_CHIP_SIZE;
11254
11255 if (tg3_nvram_read(tp, 0, &magic) != 0)
11256 return;
11257
11258 if ((magic != TG3_EEPROM_MAGIC) &&
11259 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11260 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11261 return;
11262
11263 /*
11264 * Size the chip by reading offsets at increasing powers of two.
11265 * When we encounter our validation signature, we know the addressing
11266 * has wrapped around, and thus have our chip size.
11267 */
11268 cursize = 0x10;
11269
11270 while (cursize < tp->nvram_size) {
11271 if (tg3_nvram_read(tp, cursize, &val) != 0)
11272 return;
11273
11274 if (val == magic)
11275 break;
11276
11277 cursize <<= 1;
11278 }
11279
11280 tp->nvram_size = cursize;
11281}
11282
11283static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11284{
11285 u32 val;
11286
11287 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11288 tg3_nvram_read(tp, 0, &val) != 0)
11289 return;
11290
11291 /* Selfboot format */
11292 if (val != TG3_EEPROM_MAGIC) {
11293 tg3_get_eeprom_size(tp);
11294 return;
11295 }
11296
11297 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11298 if (val != 0) {
11299 /* This is confusing. We want to operate on the
11300 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11301 * call will read from NVRAM and byteswap the data
11302 * according to the byteswapping settings for all
11303 * other register accesses. This ensures the data we
11304 * want will always reside in the lower 16-bits.
11305 * However, the data in NVRAM is in LE format, which
11306 * means the data from the NVRAM read will always be
11307 * opposite the endianness of the CPU. The 16-bit
11308 * byteswap then brings the data to CPU endianness.
11309 */
11310 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11311 return;
11312 }
11313 }
11314 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11315}
11316
11317static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11318{
11319 u32 nvcfg1;
11320
11321 nvcfg1 = tr32(NVRAM_CFG1);
11322 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11323 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11324 } else {
11325 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11326 tw32(NVRAM_CFG1, nvcfg1);
11327 }
11328
11329 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11330 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11331 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11332 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11333 tp->nvram_jedecnum = JEDEC_ATMEL;
11334 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11335 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11336 break;
11337 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11338 tp->nvram_jedecnum = JEDEC_ATMEL;
11339 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11340 break;
11341 case FLASH_VENDOR_ATMEL_EEPROM:
11342 tp->nvram_jedecnum = JEDEC_ATMEL;
11343 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11344 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11345 break;
11346 case FLASH_VENDOR_ST:
11347 tp->nvram_jedecnum = JEDEC_ST;
11348 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11349 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11350 break;
11351 case FLASH_VENDOR_SAIFUN:
11352 tp->nvram_jedecnum = JEDEC_SAIFUN;
11353 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11354 break;
11355 case FLASH_VENDOR_SST_SMALL:
11356 case FLASH_VENDOR_SST_LARGE:
11357 tp->nvram_jedecnum = JEDEC_SST;
11358 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11359 break;
11360 }
11361 } else {
11362 tp->nvram_jedecnum = JEDEC_ATMEL;
11363 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11364 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11365 }
11366}
11367
11368static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11369{
11370 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11371 case FLASH_5752PAGE_SIZE_256:
11372 tp->nvram_pagesize = 256;
11373 break;
11374 case FLASH_5752PAGE_SIZE_512:
11375 tp->nvram_pagesize = 512;
11376 break;
11377 case FLASH_5752PAGE_SIZE_1K:
11378 tp->nvram_pagesize = 1024;
11379 break;
11380 case FLASH_5752PAGE_SIZE_2K:
11381 tp->nvram_pagesize = 2048;
11382 break;
11383 case FLASH_5752PAGE_SIZE_4K:
11384 tp->nvram_pagesize = 4096;
11385 break;
11386 case FLASH_5752PAGE_SIZE_264:
11387 tp->nvram_pagesize = 264;
11388 break;
11389 case FLASH_5752PAGE_SIZE_528:
11390 tp->nvram_pagesize = 528;
11391 break;
11392 }
11393}
11394
11395static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11396{
11397 u32 nvcfg1;
11398
11399 nvcfg1 = tr32(NVRAM_CFG1);
11400
11401 /* NVRAM protection for TPM */
11402 if (nvcfg1 & (1 << 27))
11403 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11404
11405 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11406 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11407 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11408 tp->nvram_jedecnum = JEDEC_ATMEL;
11409 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11410 break;
11411 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11412 tp->nvram_jedecnum = JEDEC_ATMEL;
11413 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11414 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11415 break;
11416 case FLASH_5752VENDOR_ST_M45PE10:
11417 case FLASH_5752VENDOR_ST_M45PE20:
11418 case FLASH_5752VENDOR_ST_M45PE40:
11419 tp->nvram_jedecnum = JEDEC_ST;
11420 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11421 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11422 break;
11423 }
11424
11425 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11426 tg3_nvram_get_pagesize(tp, nvcfg1);
11427 } else {
11428 /* For eeprom, set pagesize to maximum eeprom size */
11429 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11430
11431 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11432 tw32(NVRAM_CFG1, nvcfg1);
11433 }
11434}
11435
11436static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11437{
11438 u32 nvcfg1, protect = 0;
11439
11440 nvcfg1 = tr32(NVRAM_CFG1);
11441
11442 /* NVRAM protection for TPM */
11443 if (nvcfg1 & (1 << 27)) {
11444 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11445 protect = 1;
11446 }
11447
11448 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11449 switch (nvcfg1) {
11450 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11451 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11452 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11453 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11454 tp->nvram_jedecnum = JEDEC_ATMEL;
11455 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11456 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11457 tp->nvram_pagesize = 264;
11458 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11459 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11460 tp->nvram_size = (protect ? 0x3e200 :
11461 TG3_NVRAM_SIZE_512KB);
11462 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11463 tp->nvram_size = (protect ? 0x1f200 :
11464 TG3_NVRAM_SIZE_256KB);
11465 else
11466 tp->nvram_size = (protect ? 0x1f200 :
11467 TG3_NVRAM_SIZE_128KB);
11468 break;
11469 case FLASH_5752VENDOR_ST_M45PE10:
11470 case FLASH_5752VENDOR_ST_M45PE20:
11471 case FLASH_5752VENDOR_ST_M45PE40:
11472 tp->nvram_jedecnum = JEDEC_ST;
11473 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11474 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11475 tp->nvram_pagesize = 256;
11476 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11477 tp->nvram_size = (protect ?
11478 TG3_NVRAM_SIZE_64KB :
11479 TG3_NVRAM_SIZE_128KB);
11480 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11481 tp->nvram_size = (protect ?
11482 TG3_NVRAM_SIZE_64KB :
11483 TG3_NVRAM_SIZE_256KB);
11484 else
11485 tp->nvram_size = (protect ?
11486 TG3_NVRAM_SIZE_128KB :
11487 TG3_NVRAM_SIZE_512KB);
11488 break;
11489 }
11490}
11491
11492static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11493{
11494 u32 nvcfg1;
11495
11496 nvcfg1 = tr32(NVRAM_CFG1);
11497
11498 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11499 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11500 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11501 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11502 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11503 tp->nvram_jedecnum = JEDEC_ATMEL;
11504 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11505 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11506
11507 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11508 tw32(NVRAM_CFG1, nvcfg1);
11509 break;
11510 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11511 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11512 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11513 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11514 tp->nvram_jedecnum = JEDEC_ATMEL;
11515 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11516 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11517 tp->nvram_pagesize = 264;
11518 break;
11519 case FLASH_5752VENDOR_ST_M45PE10:
11520 case FLASH_5752VENDOR_ST_M45PE20:
11521 case FLASH_5752VENDOR_ST_M45PE40:
11522 tp->nvram_jedecnum = JEDEC_ST;
11523 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11524 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11525 tp->nvram_pagesize = 256;
11526 break;
11527 }
11528}
11529
11530static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11531{
11532 u32 nvcfg1, protect = 0;
11533
11534 nvcfg1 = tr32(NVRAM_CFG1);
11535
11536 /* NVRAM protection for TPM */
11537 if (nvcfg1 & (1 << 27)) {
11538 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11539 protect = 1;
11540 }
11541
11542 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11543 switch (nvcfg1) {
11544 case FLASH_5761VENDOR_ATMEL_ADB021D:
11545 case FLASH_5761VENDOR_ATMEL_ADB041D:
11546 case FLASH_5761VENDOR_ATMEL_ADB081D:
11547 case FLASH_5761VENDOR_ATMEL_ADB161D:
11548 case FLASH_5761VENDOR_ATMEL_MDB021D:
11549 case FLASH_5761VENDOR_ATMEL_MDB041D:
11550 case FLASH_5761VENDOR_ATMEL_MDB081D:
11551 case FLASH_5761VENDOR_ATMEL_MDB161D:
11552 tp->nvram_jedecnum = JEDEC_ATMEL;
11553 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11554 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11555 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11556 tp->nvram_pagesize = 256;
11557 break;
11558 case FLASH_5761VENDOR_ST_A_M45PE20:
11559 case FLASH_5761VENDOR_ST_A_M45PE40:
11560 case FLASH_5761VENDOR_ST_A_M45PE80:
11561 case FLASH_5761VENDOR_ST_A_M45PE16:
11562 case FLASH_5761VENDOR_ST_M_M45PE20:
11563 case FLASH_5761VENDOR_ST_M_M45PE40:
11564 case FLASH_5761VENDOR_ST_M_M45PE80:
11565 case FLASH_5761VENDOR_ST_M_M45PE16:
11566 tp->nvram_jedecnum = JEDEC_ST;
11567 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11568 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11569 tp->nvram_pagesize = 256;
11570 break;
11571 }
11572
11573 if (protect) {
11574 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11575 } else {
11576 switch (nvcfg1) {
11577 case FLASH_5761VENDOR_ATMEL_ADB161D:
11578 case FLASH_5761VENDOR_ATMEL_MDB161D:
11579 case FLASH_5761VENDOR_ST_A_M45PE16:
11580 case FLASH_5761VENDOR_ST_M_M45PE16:
11581 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11582 break;
11583 case FLASH_5761VENDOR_ATMEL_ADB081D:
11584 case FLASH_5761VENDOR_ATMEL_MDB081D:
11585 case FLASH_5761VENDOR_ST_A_M45PE80:
11586 case FLASH_5761VENDOR_ST_M_M45PE80:
11587 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11588 break;
11589 case FLASH_5761VENDOR_ATMEL_ADB041D:
11590 case FLASH_5761VENDOR_ATMEL_MDB041D:
11591 case FLASH_5761VENDOR_ST_A_M45PE40:
11592 case FLASH_5761VENDOR_ST_M_M45PE40:
11593 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11594 break;
11595 case FLASH_5761VENDOR_ATMEL_ADB021D:
11596 case FLASH_5761VENDOR_ATMEL_MDB021D:
11597 case FLASH_5761VENDOR_ST_A_M45PE20:
11598 case FLASH_5761VENDOR_ST_M_M45PE20:
11599 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11600 break;
11601 }
11602 }
11603}
11604
11605static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11606{
11607 tp->nvram_jedecnum = JEDEC_ATMEL;
11608 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11609 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11610}
11611
11612static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11613{
11614 u32 nvcfg1;
11615
11616 nvcfg1 = tr32(NVRAM_CFG1);
11617
11618 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11619 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11620 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11621 tp->nvram_jedecnum = JEDEC_ATMEL;
11622 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11623 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11624
11625 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11626 tw32(NVRAM_CFG1, nvcfg1);
11627 return;
11628 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11629 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11630 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11631 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11632 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11633 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11634 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11635 tp->nvram_jedecnum = JEDEC_ATMEL;
11636 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11637 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11638
11639 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11640 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11641 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11642 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11643 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11644 break;
11645 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11646 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11647 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11648 break;
11649 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11650 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11651 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11652 break;
11653 }
11654 break;
11655 case FLASH_5752VENDOR_ST_M45PE10:
11656 case FLASH_5752VENDOR_ST_M45PE20:
11657 case FLASH_5752VENDOR_ST_M45PE40:
11658 tp->nvram_jedecnum = JEDEC_ST;
11659 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11660 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11661
11662 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11663 case FLASH_5752VENDOR_ST_M45PE10:
11664 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11665 break;
11666 case FLASH_5752VENDOR_ST_M45PE20:
11667 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11668 break;
11669 case FLASH_5752VENDOR_ST_M45PE40:
11670 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11671 break;
11672 }
11673 break;
11674 default:
11675 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11676 return;
11677 }
11678
11679 tg3_nvram_get_pagesize(tp, nvcfg1);
11680 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11681 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11682}
11683
11684
11685static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11686{
11687 u32 nvcfg1;
11688
11689 nvcfg1 = tr32(NVRAM_CFG1);
11690
11691 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11692 case FLASH_5717VENDOR_ATMEL_EEPROM:
11693 case FLASH_5717VENDOR_MICRO_EEPROM:
11694 tp->nvram_jedecnum = JEDEC_ATMEL;
11695 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11696 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11697
11698 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11699 tw32(NVRAM_CFG1, nvcfg1);
11700 return;
11701 case FLASH_5717VENDOR_ATMEL_MDB011D:
11702 case FLASH_5717VENDOR_ATMEL_ADB011B:
11703 case FLASH_5717VENDOR_ATMEL_ADB011D:
11704 case FLASH_5717VENDOR_ATMEL_MDB021D:
11705 case FLASH_5717VENDOR_ATMEL_ADB021B:
11706 case FLASH_5717VENDOR_ATMEL_ADB021D:
11707 case FLASH_5717VENDOR_ATMEL_45USPT:
11708 tp->nvram_jedecnum = JEDEC_ATMEL;
11709 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11710 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11711
11712 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11713 case FLASH_5717VENDOR_ATMEL_MDB021D:
11714 case FLASH_5717VENDOR_ATMEL_ADB021B:
11715 case FLASH_5717VENDOR_ATMEL_ADB021D:
11716 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11717 break;
11718 default:
11719 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11720 break;
11721 }
11722 break;
11723 case FLASH_5717VENDOR_ST_M_M25PE10:
11724 case FLASH_5717VENDOR_ST_A_M25PE10:
11725 case FLASH_5717VENDOR_ST_M_M45PE10:
11726 case FLASH_5717VENDOR_ST_A_M45PE10:
11727 case FLASH_5717VENDOR_ST_M_M25PE20:
11728 case FLASH_5717VENDOR_ST_A_M25PE20:
11729 case FLASH_5717VENDOR_ST_M_M45PE20:
11730 case FLASH_5717VENDOR_ST_A_M45PE20:
11731 case FLASH_5717VENDOR_ST_25USPT:
11732 case FLASH_5717VENDOR_ST_45USPT:
11733 tp->nvram_jedecnum = JEDEC_ST;
11734 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11735 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11736
11737 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11738 case FLASH_5717VENDOR_ST_M_M25PE20:
11739 case FLASH_5717VENDOR_ST_A_M25PE20:
11740 case FLASH_5717VENDOR_ST_M_M45PE20:
11741 case FLASH_5717VENDOR_ST_A_M45PE20:
11742 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11743 break;
11744 default:
11745 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11746 break;
11747 }
11748 break;
11749 default:
11750 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11751 return;
11752 }
11753
11754 tg3_nvram_get_pagesize(tp, nvcfg1);
11755 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11756 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11757}
11758
11759/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11760static void __devinit tg3_nvram_init(struct tg3 *tp)
11761{
11762 tw32_f(GRC_EEPROM_ADDR,
11763 (EEPROM_ADDR_FSM_RESET |
11764 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11765 EEPROM_ADDR_CLKPERD_SHIFT)));
11766
11767 msleep(1);
11768
11769 /* Enable seeprom accesses. */
11770 tw32_f(GRC_LOCAL_CTRL,
11771 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11772 udelay(100);
11773
11774 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11775 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11776 tp->tg3_flags |= TG3_FLAG_NVRAM;
11777
11778 if (tg3_nvram_lock(tp)) {
11779 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11780 "tg3_nvram_init failed.\n", tp->dev->name);
11781 return;
11782 }
11783 tg3_enable_nvram_access(tp);
11784
11785 tp->nvram_size = 0;
11786
11787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11788 tg3_get_5752_nvram_info(tp);
11789 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11790 tg3_get_5755_nvram_info(tp);
11791 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11792 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11793 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11794 tg3_get_5787_nvram_info(tp);
11795 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11796 tg3_get_5761_nvram_info(tp);
11797 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11798 tg3_get_5906_nvram_info(tp);
11799 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11800 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11801 tg3_get_57780_nvram_info(tp);
11802 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11803 tg3_get_5717_nvram_info(tp);
11804 else
11805 tg3_get_nvram_info(tp);
11806
11807 if (tp->nvram_size == 0)
11808 tg3_get_nvram_size(tp);
11809
11810 tg3_disable_nvram_access(tp);
11811 tg3_nvram_unlock(tp);
11812
11813 } else {
11814 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11815
11816 tg3_get_eeprom_size(tp);
11817 }
11818}
11819
11820static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11821 u32 offset, u32 len, u8 *buf)
11822{
11823 int i, j, rc = 0;
11824 u32 val;
11825
11826 for (i = 0; i < len; i += 4) {
11827 u32 addr;
11828 __be32 data;
11829
11830 addr = offset + i;
11831
11832 memcpy(&data, buf + i, 4);
11833
11834 /*
11835 * The SEEPROM interface expects the data to always be opposite
11836 * the native endian format. We accomplish this by reversing
11837 * all the operations that would have been performed on the
11838 * data from a call to tg3_nvram_read_be32().
11839 */
11840 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11841
11842 val = tr32(GRC_EEPROM_ADDR);
11843 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11844
11845 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11846 EEPROM_ADDR_READ);
11847 tw32(GRC_EEPROM_ADDR, val |
11848 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11849 (addr & EEPROM_ADDR_ADDR_MASK) |
11850 EEPROM_ADDR_START |
11851 EEPROM_ADDR_WRITE);
11852
11853 for (j = 0; j < 1000; j++) {
11854 val = tr32(GRC_EEPROM_ADDR);
11855
11856 if (val & EEPROM_ADDR_COMPLETE)
11857 break;
11858 msleep(1);
11859 }
11860 if (!(val & EEPROM_ADDR_COMPLETE)) {
11861 rc = -EBUSY;
11862 break;
11863 }
11864 }
11865
11866 return rc;
11867}
11868
11869/* offset and length are dword aligned */
11870static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11871 u8 *buf)
11872{
11873 int ret = 0;
11874 u32 pagesize = tp->nvram_pagesize;
11875 u32 pagemask = pagesize - 1;
11876 u32 nvram_cmd;
11877 u8 *tmp;
11878
11879 tmp = kmalloc(pagesize, GFP_KERNEL);
11880 if (tmp == NULL)
11881 return -ENOMEM;
11882
11883 while (len) {
11884 int j;
11885 u32 phy_addr, page_off, size;
11886
11887 phy_addr = offset & ~pagemask;
11888
11889 for (j = 0; j < pagesize; j += 4) {
11890 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11891 (__be32 *) (tmp + j));
11892 if (ret)
11893 break;
11894 }
11895 if (ret)
11896 break;
11897
11898 page_off = offset & pagemask;
11899 size = pagesize;
11900 if (len < size)
11901 size = len;
11902
11903 len -= size;
11904
11905 memcpy(tmp + page_off, buf, size);
11906
11907 offset = offset + (pagesize - page_off);
11908
11909 tg3_enable_nvram_access(tp);
11910
11911 /*
11912 * Before we can erase the flash page, we need
11913 * to issue a special "write enable" command.
11914 */
11915 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11916
11917 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11918 break;
11919
11920 /* Erase the target page */
11921 tw32(NVRAM_ADDR, phy_addr);
11922
11923 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11924 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11925
11926 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11927 break;
11928
11929 /* Issue another write enable to start the write. */
11930 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11931
11932 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11933 break;
11934
11935 for (j = 0; j < pagesize; j += 4) {
11936 __be32 data;
11937
11938 data = *((__be32 *) (tmp + j));
11939
11940 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11941
11942 tw32(NVRAM_ADDR, phy_addr + j);
11943
11944 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11945 NVRAM_CMD_WR;
11946
11947 if (j == 0)
11948 nvram_cmd |= NVRAM_CMD_FIRST;
11949 else if (j == (pagesize - 4))
11950 nvram_cmd |= NVRAM_CMD_LAST;
11951
11952 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11953 break;
11954 }
11955 if (ret)
11956 break;
11957 }
11958
11959 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11960 tg3_nvram_exec_cmd(tp, nvram_cmd);
11961
11962 kfree(tmp);
11963
11964 return ret;
11965}
11966
11967/* offset and length are dword aligned */
11968static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11969 u8 *buf)
11970{
11971 int i, ret = 0;
11972
11973 for (i = 0; i < len; i += 4, offset += 4) {
11974 u32 page_off, phy_addr, nvram_cmd;
11975 __be32 data;
11976
11977 memcpy(&data, buf + i, 4);
11978 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11979
11980 page_off = offset % tp->nvram_pagesize;
11981
11982 phy_addr = tg3_nvram_phys_addr(tp, offset);
11983
11984 tw32(NVRAM_ADDR, phy_addr);
11985
11986 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11987
11988 if ((page_off == 0) || (i == 0))
11989 nvram_cmd |= NVRAM_CMD_FIRST;
11990 if (page_off == (tp->nvram_pagesize - 4))
11991 nvram_cmd |= NVRAM_CMD_LAST;
11992
11993 if (i == (len - 4))
11994 nvram_cmd |= NVRAM_CMD_LAST;
11995
11996 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11997 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11998 (tp->nvram_jedecnum == JEDEC_ST) &&
11999 (nvram_cmd & NVRAM_CMD_FIRST)) {
12000
12001 if ((ret = tg3_nvram_exec_cmd(tp,
12002 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12003 NVRAM_CMD_DONE)))
12004
12005 break;
12006 }
12007 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12008 /* We always do complete word writes to eeprom. */
12009 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12010 }
12011
12012 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12013 break;
12014 }
12015 return ret;
12016}
12017
12018/* offset and length are dword aligned */
12019static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12020{
12021 int ret;
12022
12023 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12024 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12025 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12026 udelay(40);
12027 }
12028
12029 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12030 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12031 }
12032 else {
12033 u32 grc_mode;
12034
12035 ret = tg3_nvram_lock(tp);
12036 if (ret)
12037 return ret;
12038
12039 tg3_enable_nvram_access(tp);
12040 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12041 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12042 tw32(NVRAM_WRITE1, 0x406);
12043
12044 grc_mode = tr32(GRC_MODE);
12045 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12046
12047 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12048 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12049
12050 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12051 buf);
12052 }
12053 else {
12054 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12055 buf);
12056 }
12057
12058 grc_mode = tr32(GRC_MODE);
12059 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12060
12061 tg3_disable_nvram_access(tp);
12062 tg3_nvram_unlock(tp);
12063 }
12064
12065 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12066 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12067 udelay(40);
12068 }
12069
12070 return ret;
12071}
12072
12073struct subsys_tbl_ent {
12074 u16 subsys_vendor, subsys_devid;
12075 u32 phy_id;
12076};
12077
12078static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12079 /* Broadcom boards. */
12080 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12081 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12082 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12083 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
12084 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12085 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12086 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
12087 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12088 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12089 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12090 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12091
12092 /* 3com boards. */
12093 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12094 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12095 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
12096 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12097 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12098
12099 /* DELL boards. */
12100 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12101 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12102 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12103 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12104
12105 /* Compaq boards. */
12106 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12107 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12108 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
12109 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12110 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12111
12112 /* IBM boards. */
12113 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12114};
12115
12116static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12117{
12118 int i;
12119
12120 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12121 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12122 tp->pdev->subsystem_vendor) &&
12123 (subsys_id_to_phy_id[i].subsys_devid ==
12124 tp->pdev->subsystem_device))
12125 return &subsys_id_to_phy_id[i];
12126 }
12127 return NULL;
12128}
12129
12130static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12131{
12132 u32 val;
12133 u16 pmcsr;
12134
12135 /* On some early chips the SRAM cannot be accessed in D3hot state,
12136 * so need make sure we're in D0.
12137 */
12138 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12139 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12140 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12141 msleep(1);
12142
12143 /* Make sure register accesses (indirect or otherwise)
12144 * will function correctly.
12145 */
12146 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12147 tp->misc_host_ctrl);
12148
12149 /* The memory arbiter has to be enabled in order for SRAM accesses
12150 * to succeed. Normally on powerup the tg3 chip firmware will make
12151 * sure it is enabled, but other entities such as system netboot
12152 * code might disable it.
12153 */
12154 val = tr32(MEMARB_MODE);
12155 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12156
12157 tp->phy_id = PHY_ID_INVALID;
12158 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12159
12160 /* Assume an onboard device and WOL capable by default. */
12161 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12162
12163 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12164 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12165 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12166 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12167 }
12168 val = tr32(VCPU_CFGSHDW);
12169 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12170 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12171 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12172 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12173 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12174 goto done;
12175 }
12176
12177 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12178 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12179 u32 nic_cfg, led_cfg;
12180 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12181 int eeprom_phy_serdes = 0;
12182
12183 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12184 tp->nic_sram_data_cfg = nic_cfg;
12185
12186 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12187 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12188 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12189 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12190 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12191 (ver > 0) && (ver < 0x100))
12192 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12193
12194 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12195 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12196
12197 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12198 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12199 eeprom_phy_serdes = 1;
12200
12201 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12202 if (nic_phy_id != 0) {
12203 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12204 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12205
12206 eeprom_phy_id = (id1 >> 16) << 10;
12207 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12208 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12209 } else
12210 eeprom_phy_id = 0;
12211
12212 tp->phy_id = eeprom_phy_id;
12213 if (eeprom_phy_serdes) {
12214 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12215 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12216 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12217 else
12218 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12219 }
12220
12221 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12222 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12223 SHASTA_EXT_LED_MODE_MASK);
12224 else
12225 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12226
12227 switch (led_cfg) {
12228 default:
12229 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12230 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12231 break;
12232
12233 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12234 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12235 break;
12236
12237 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12238 tp->led_ctrl = LED_CTRL_MODE_MAC;
12239
12240 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12241 * read on some older 5700/5701 bootcode.
12242 */
12243 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12244 ASIC_REV_5700 ||
12245 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12246 ASIC_REV_5701)
12247 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12248
12249 break;
12250
12251 case SHASTA_EXT_LED_SHARED:
12252 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12253 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12254 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12255 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12256 LED_CTRL_MODE_PHY_2);
12257 break;
12258
12259 case SHASTA_EXT_LED_MAC:
12260 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12261 break;
12262
12263 case SHASTA_EXT_LED_COMBO:
12264 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12265 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12266 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12267 LED_CTRL_MODE_PHY_2);
12268 break;
12269
12270 }
12271
12272 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12273 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12274 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12275 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12276
12277 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12278 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12279
12280 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12281 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12282 if ((tp->pdev->subsystem_vendor ==
12283 PCI_VENDOR_ID_ARIMA) &&
12284 (tp->pdev->subsystem_device == 0x205a ||
12285 tp->pdev->subsystem_device == 0x2063))
12286 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12287 } else {
12288 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12289 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12290 }
12291
12292 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12293 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12294 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12295 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12296 }
12297
12298 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12299 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12300 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12301
12302 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12303 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12304 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12305
12306 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12307 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12308 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12309
12310 if (cfg2 & (1 << 17))
12311 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12312
12313 /* serdes signal pre-emphasis in register 0x590 set by */
12314 /* bootcode if bit 18 is set */
12315 if (cfg2 & (1 << 18))
12316 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12317
12318 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12319 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12320 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12321 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12322
12323 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12324 u32 cfg3;
12325
12326 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12327 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12328 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12329 }
12330
12331 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12332 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12333 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12334 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12335 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12336 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12337 }
12338done:
12339 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12340 device_set_wakeup_enable(&tp->pdev->dev,
12341 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12342}
12343
12344static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12345{
12346 int i;
12347 u32 val;
12348
12349 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12350 tw32(OTP_CTRL, cmd);
12351
12352 /* Wait for up to 1 ms for command to execute. */
12353 for (i = 0; i < 100; i++) {
12354 val = tr32(OTP_STATUS);
12355 if (val & OTP_STATUS_CMD_DONE)
12356 break;
12357 udelay(10);
12358 }
12359
12360 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12361}
12362
12363/* Read the gphy configuration from the OTP region of the chip. The gphy
12364 * configuration is a 32-bit value that straddles the alignment boundary.
12365 * We do two 32-bit reads and then shift and merge the results.
12366 */
12367static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12368{
12369 u32 bhalf_otp, thalf_otp;
12370
12371 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12372
12373 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12374 return 0;
12375
12376 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12377
12378 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12379 return 0;
12380
12381 thalf_otp = tr32(OTP_READ_DATA);
12382
12383 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12384
12385 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12386 return 0;
12387
12388 bhalf_otp = tr32(OTP_READ_DATA);
12389
12390 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12391}
12392
12393static int __devinit tg3_phy_probe(struct tg3 *tp)
12394{
12395 u32 hw_phy_id_1, hw_phy_id_2;
12396 u32 hw_phy_id, hw_phy_id_masked;
12397 int err;
12398
12399 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12400 return tg3_phy_init(tp);
12401
12402 /* Reading the PHY ID register can conflict with ASF
12403 * firmware access to the PHY hardware.
12404 */
12405 err = 0;
12406 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12407 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12408 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12409 } else {
12410 /* Now read the physical PHY_ID from the chip and verify
12411 * that it is sane. If it doesn't look good, we fall back
12412 * to either the hard-coded table based PHY_ID and failing
12413 * that the value found in the eeprom area.
12414 */
12415 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12416 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12417
12418 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12419 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12420 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12421
12422 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12423 }
12424
12425 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12426 tp->phy_id = hw_phy_id;
12427 if (hw_phy_id_masked == PHY_ID_BCM8002)
12428 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12429 else
12430 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12431 } else {
12432 if (tp->phy_id != PHY_ID_INVALID) {
12433 /* Do nothing, phy ID already set up in
12434 * tg3_get_eeprom_hw_cfg().
12435 */
12436 } else {
12437 struct subsys_tbl_ent *p;
12438
12439 /* No eeprom signature? Try the hardcoded
12440 * subsys device table.
12441 */
12442 p = lookup_by_subsys(tp);
12443 if (!p)
12444 return -ENODEV;
12445
12446 tp->phy_id = p->phy_id;
12447 if (!tp->phy_id ||
12448 tp->phy_id == PHY_ID_BCM8002)
12449 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12450 }
12451 }
12452
12453 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12454 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12455 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12456 u32 bmsr, adv_reg, tg3_ctrl, mask;
12457
12458 tg3_readphy(tp, MII_BMSR, &bmsr);
12459 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12460 (bmsr & BMSR_LSTATUS))
12461 goto skip_phy_reset;
12462
12463 err = tg3_phy_reset(tp);
12464 if (err)
12465 return err;
12466
12467 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12468 ADVERTISE_100HALF | ADVERTISE_100FULL |
12469 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12470 tg3_ctrl = 0;
12471 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12472 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12473 MII_TG3_CTRL_ADV_1000_FULL);
12474 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12475 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12476 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12477 MII_TG3_CTRL_ENABLE_AS_MASTER);
12478 }
12479
12480 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12481 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12482 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12483 if (!tg3_copper_is_advertising_all(tp, mask)) {
12484 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12485
12486 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12487 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12488
12489 tg3_writephy(tp, MII_BMCR,
12490 BMCR_ANENABLE | BMCR_ANRESTART);
12491 }
12492 tg3_phy_set_wirespeed(tp);
12493
12494 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12495 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12496 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12497 }
12498
12499skip_phy_reset:
12500 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12501 err = tg3_init_5401phy_dsp(tp);
12502 if (err)
12503 return err;
12504 }
12505
12506 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12507 err = tg3_init_5401phy_dsp(tp);
12508 }
12509
12510 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12511 tp->link_config.advertising =
12512 (ADVERTISED_1000baseT_Half |
12513 ADVERTISED_1000baseT_Full |
12514 ADVERTISED_Autoneg |
12515 ADVERTISED_FIBRE);
12516 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12517 tp->link_config.advertising &=
12518 ~(ADVERTISED_1000baseT_Half |
12519 ADVERTISED_1000baseT_Full);
12520
12521 return err;
12522}
12523
12524static void __devinit tg3_read_partno(struct tg3 *tp)
12525{
12526 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
12527 unsigned int i;
12528 u32 magic;
12529
12530 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12531 tg3_nvram_read(tp, 0x0, &magic))
12532 goto out_not_found;
12533
12534 if (magic == TG3_EEPROM_MAGIC) {
12535 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12536 u32 tmp;
12537
12538 /* The data is in little-endian format in NVRAM.
12539 * Use the big-endian read routines to preserve
12540 * the byte order as it exists in NVRAM.
12541 */
12542 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12543 goto out_not_found;
12544
12545 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12546 }
12547 } else {
12548 ssize_t cnt;
12549 unsigned int pos = 0, i = 0;
12550
12551 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12552 cnt = pci_read_vpd(tp->pdev, pos,
12553 TG3_NVM_VPD_LEN - pos,
12554 &vpd_data[pos]);
12555 if (cnt == -ETIMEDOUT || -EINTR)
12556 cnt = 0;
12557 else if (cnt < 0)
12558 goto out_not_found;
12559 }
12560 if (pos != TG3_NVM_VPD_LEN)
12561 goto out_not_found;
12562 }
12563
12564 /* Now parse and find the part number. */
12565 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
12566 unsigned char val = vpd_data[i];
12567 unsigned int block_end;
12568
12569 if (val == 0x82 || val == 0x91) {
12570 i = (i + 3 +
12571 (vpd_data[i + 1] +
12572 (vpd_data[i + 2] << 8)));
12573 continue;
12574 }
12575
12576 if (val != 0x90)
12577 goto out_not_found;
12578
12579 block_end = (i + 3 +
12580 (vpd_data[i + 1] +
12581 (vpd_data[i + 2] << 8)));
12582 i += 3;
12583
12584 if (block_end > TG3_NVM_VPD_LEN)
12585 goto out_not_found;
12586
12587 while (i < (block_end - 2)) {
12588 if (vpd_data[i + 0] == 'P' &&
12589 vpd_data[i + 1] == 'N') {
12590 int partno_len = vpd_data[i + 2];
12591
12592 i += 3;
12593 if (partno_len > TG3_BPN_SIZE ||
12594 (partno_len + i) > TG3_NVM_VPD_LEN)
12595 goto out_not_found;
12596
12597 memcpy(tp->board_part_number,
12598 &vpd_data[i], partno_len);
12599
12600 /* Success. */
12601 return;
12602 }
12603 i += 3 + vpd_data[i + 2];
12604 }
12605
12606 /* Part number not found. */
12607 goto out_not_found;
12608 }
12609
12610out_not_found:
12611 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12612 strcpy(tp->board_part_number, "BCM95906");
12613 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12614 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12615 strcpy(tp->board_part_number, "BCM57780");
12616 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12617 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12618 strcpy(tp->board_part_number, "BCM57760");
12619 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12620 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12621 strcpy(tp->board_part_number, "BCM57790");
12622 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12623 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12624 strcpy(tp->board_part_number, "BCM57788");
12625 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12626 strcpy(tp->board_part_number, "BCM57765");
12627 else
12628 strcpy(tp->board_part_number, "none");
12629}
12630
12631static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12632{
12633 u32 val;
12634
12635 if (tg3_nvram_read(tp, offset, &val) ||
12636 (val & 0xfc000000) != 0x0c000000 ||
12637 tg3_nvram_read(tp, offset + 4, &val) ||
12638 val != 0)
12639 return 0;
12640
12641 return 1;
12642}
12643
12644static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12645{
12646 u32 val, offset, start, ver_offset;
12647 int i;
12648 bool newver = false;
12649
12650 if (tg3_nvram_read(tp, 0xc, &offset) ||
12651 tg3_nvram_read(tp, 0x4, &start))
12652 return;
12653
12654 offset = tg3_nvram_logical_addr(tp, offset);
12655
12656 if (tg3_nvram_read(tp, offset, &val))
12657 return;
12658
12659 if ((val & 0xfc000000) == 0x0c000000) {
12660 if (tg3_nvram_read(tp, offset + 4, &val))
12661 return;
12662
12663 if (val == 0)
12664 newver = true;
12665 }
12666
12667 if (newver) {
12668 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12669 return;
12670
12671 offset = offset + ver_offset - start;
12672 for (i = 0; i < 16; i += 4) {
12673 __be32 v;
12674 if (tg3_nvram_read_be32(tp, offset + i, &v))
12675 return;
12676
12677 memcpy(tp->fw_ver + i, &v, sizeof(v));
12678 }
12679 } else {
12680 u32 major, minor;
12681
12682 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12683 return;
12684
12685 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12686 TG3_NVM_BCVER_MAJSFT;
12687 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12688 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12689 }
12690}
12691
12692static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12693{
12694 u32 val, major, minor;
12695
12696 /* Use native endian representation */
12697 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12698 return;
12699
12700 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12701 TG3_NVM_HWSB_CFG1_MAJSFT;
12702 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12703 TG3_NVM_HWSB_CFG1_MINSFT;
12704
12705 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12706}
12707
12708static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12709{
12710 u32 offset, major, minor, build;
12711
12712 tp->fw_ver[0] = 's';
12713 tp->fw_ver[1] = 'b';
12714 tp->fw_ver[2] = '\0';
12715
12716 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12717 return;
12718
12719 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12720 case TG3_EEPROM_SB_REVISION_0:
12721 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12722 break;
12723 case TG3_EEPROM_SB_REVISION_2:
12724 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12725 break;
12726 case TG3_EEPROM_SB_REVISION_3:
12727 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12728 break;
12729 default:
12730 return;
12731 }
12732
12733 if (tg3_nvram_read(tp, offset, &val))
12734 return;
12735
12736 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12737 TG3_EEPROM_SB_EDH_BLD_SHFT;
12738 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12739 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12740 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12741
12742 if (minor > 99 || build > 26)
12743 return;
12744
12745 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12746
12747 if (build > 0) {
12748 tp->fw_ver[8] = 'a' + build - 1;
12749 tp->fw_ver[9] = '\0';
12750 }
12751}
12752
12753static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12754{
12755 u32 val, offset, start;
12756 int i, vlen;
12757
12758 for (offset = TG3_NVM_DIR_START;
12759 offset < TG3_NVM_DIR_END;
12760 offset += TG3_NVM_DIRENT_SIZE) {
12761 if (tg3_nvram_read(tp, offset, &val))
12762 return;
12763
12764 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12765 break;
12766 }
12767
12768 if (offset == TG3_NVM_DIR_END)
12769 return;
12770
12771 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12772 start = 0x08000000;
12773 else if (tg3_nvram_read(tp, offset - 4, &start))
12774 return;
12775
12776 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12777 !tg3_fw_img_is_valid(tp, offset) ||
12778 tg3_nvram_read(tp, offset + 8, &val))
12779 return;
12780
12781 offset += val - start;
12782
12783 vlen = strlen(tp->fw_ver);
12784
12785 tp->fw_ver[vlen++] = ',';
12786 tp->fw_ver[vlen++] = ' ';
12787
12788 for (i = 0; i < 4; i++) {
12789 __be32 v;
12790 if (tg3_nvram_read_be32(tp, offset, &v))
12791 return;
12792
12793 offset += sizeof(v);
12794
12795 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12796 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12797 break;
12798 }
12799
12800 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12801 vlen += sizeof(v);
12802 }
12803}
12804
12805static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12806{
12807 int vlen;
12808 u32 apedata;
12809
12810 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12811 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12812 return;
12813
12814 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12815 if (apedata != APE_SEG_SIG_MAGIC)
12816 return;
12817
12818 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12819 if (!(apedata & APE_FW_STATUS_READY))
12820 return;
12821
12822 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12823
12824 vlen = strlen(tp->fw_ver);
12825
12826 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12827 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12828 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12829 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12830 (apedata & APE_FW_VERSION_BLDMSK));
12831}
12832
12833static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12834{
12835 u32 val;
12836
12837 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12838 tp->fw_ver[0] = 's';
12839 tp->fw_ver[1] = 'b';
12840 tp->fw_ver[2] = '\0';
12841
12842 return;
12843 }
12844
12845 if (tg3_nvram_read(tp, 0, &val))
12846 return;
12847
12848 if (val == TG3_EEPROM_MAGIC)
12849 tg3_read_bc_ver(tp);
12850 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12851 tg3_read_sb_ver(tp, val);
12852 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12853 tg3_read_hwsb_ver(tp);
12854 else
12855 return;
12856
12857 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12858 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12859 return;
12860
12861 tg3_read_mgmtfw_ver(tp);
12862
12863 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12864}
12865
12866static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12867
12868static int __devinit tg3_get_invariants(struct tg3 *tp)
12869{
12870 static struct pci_device_id write_reorder_chipsets[] = {
12871 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12872 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12873 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12874 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12875 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12876 PCI_DEVICE_ID_VIA_8385_0) },
12877 { },
12878 };
12879 u32 misc_ctrl_reg;
12880 u32 pci_state_reg, grc_misc_cfg;
12881 u32 val;
12882 u16 pci_cmd;
12883 int err;
12884
12885 /* Force memory write invalidate off. If we leave it on,
12886 * then on 5700_BX chips we have to enable a workaround.
12887 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12888 * to match the cacheline size. The Broadcom driver have this
12889 * workaround but turns MWI off all the times so never uses
12890 * it. This seems to suggest that the workaround is insufficient.
12891 */
12892 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12893 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12894 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12895
12896 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12897 * has the register indirect write enable bit set before
12898 * we try to access any of the MMIO registers. It is also
12899 * critical that the PCI-X hw workaround situation is decided
12900 * before that as well.
12901 */
12902 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12903 &misc_ctrl_reg);
12904
12905 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12906 MISC_HOST_CTRL_CHIPREV_SHIFT);
12907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12908 u32 prod_id_asic_rev;
12909
12910 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12911 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12912 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12913 pci_read_config_dword(tp->pdev,
12914 TG3PCI_GEN2_PRODID_ASICREV,
12915 &prod_id_asic_rev);
12916 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12917 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12918 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12919 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12920 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12921 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12922 pci_read_config_dword(tp->pdev,
12923 TG3PCI_GEN15_PRODID_ASICREV,
12924 &prod_id_asic_rev);
12925 else
12926 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12927 &prod_id_asic_rev);
12928
12929 tp->pci_chip_rev_id = prod_id_asic_rev;
12930 }
12931
12932 /* Wrong chip ID in 5752 A0. This code can be removed later
12933 * as A0 is not in production.
12934 */
12935 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12936 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12937
12938 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12939 * we need to disable memory and use config. cycles
12940 * only to access all registers. The 5702/03 chips
12941 * can mistakenly decode the special cycles from the
12942 * ICH chipsets as memory write cycles, causing corruption
12943 * of register and memory space. Only certain ICH bridges
12944 * will drive special cycles with non-zero data during the
12945 * address phase which can fall within the 5703's address
12946 * range. This is not an ICH bug as the PCI spec allows
12947 * non-zero address during special cycles. However, only
12948 * these ICH bridges are known to drive non-zero addresses
12949 * during special cycles.
12950 *
12951 * Since special cycles do not cross PCI bridges, we only
12952 * enable this workaround if the 5703 is on the secondary
12953 * bus of these ICH bridges.
12954 */
12955 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12956 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12957 static struct tg3_dev_id {
12958 u32 vendor;
12959 u32 device;
12960 u32 rev;
12961 } ich_chipsets[] = {
12962 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12963 PCI_ANY_ID },
12964 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12965 PCI_ANY_ID },
12966 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12967 0xa },
12968 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12969 PCI_ANY_ID },
12970 { },
12971 };
12972 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12973 struct pci_dev *bridge = NULL;
12974
12975 while (pci_id->vendor != 0) {
12976 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12977 bridge);
12978 if (!bridge) {
12979 pci_id++;
12980 continue;
12981 }
12982 if (pci_id->rev != PCI_ANY_ID) {
12983 if (bridge->revision > pci_id->rev)
12984 continue;
12985 }
12986 if (bridge->subordinate &&
12987 (bridge->subordinate->number ==
12988 tp->pdev->bus->number)) {
12989
12990 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12991 pci_dev_put(bridge);
12992 break;
12993 }
12994 }
12995 }
12996
12997 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12998 static struct tg3_dev_id {
12999 u32 vendor;
13000 u32 device;
13001 } bridge_chipsets[] = {
13002 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13003 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13004 { },
13005 };
13006 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13007 struct pci_dev *bridge = NULL;
13008
13009 while (pci_id->vendor != 0) {
13010 bridge = pci_get_device(pci_id->vendor,
13011 pci_id->device,
13012 bridge);
13013 if (!bridge) {
13014 pci_id++;
13015 continue;
13016 }
13017 if (bridge->subordinate &&
13018 (bridge->subordinate->number <=
13019 tp->pdev->bus->number) &&
13020 (bridge->subordinate->subordinate >=
13021 tp->pdev->bus->number)) {
13022 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13023 pci_dev_put(bridge);
13024 break;
13025 }
13026 }
13027 }
13028
13029 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13030 * DMA addresses > 40-bit. This bridge may have other additional
13031 * 57xx devices behind it in some 4-port NIC designs for example.
13032 * Any tg3 device found behind the bridge will also need the 40-bit
13033 * DMA workaround.
13034 */
13035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13037 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13038 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13039 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13040 }
13041 else {
13042 struct pci_dev *bridge = NULL;
13043
13044 do {
13045 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13046 PCI_DEVICE_ID_SERVERWORKS_EPB,
13047 bridge);
13048 if (bridge && bridge->subordinate &&
13049 (bridge->subordinate->number <=
13050 tp->pdev->bus->number) &&
13051 (bridge->subordinate->subordinate >=
13052 tp->pdev->bus->number)) {
13053 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13054 pci_dev_put(bridge);
13055 break;
13056 }
13057 } while (bridge);
13058 }
13059
13060 /* Initialize misc host control in PCI block. */
13061 tp->misc_host_ctrl |= (misc_ctrl_reg &
13062 MISC_HOST_CTRL_CHIPREV);
13063 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13064 tp->misc_host_ctrl);
13065
13066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13067 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13068 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13069 tp->pdev_peer = tg3_find_peer(tp);
13070
13071 /* Intentionally exclude ASIC_REV_5906 */
13072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13073 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13074 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13075 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13076 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13077 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13078 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13079 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13080 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13081
13082 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13083 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13085 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13086 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13087 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13088
13089 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13090 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13091 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13092
13093 /* 5700 B0 chips do not support checksumming correctly due
13094 * to hardware bugs.
13095 */
13096 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13097 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13098 else {
13099 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13100 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13101 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13102 tp->dev->features |= NETIF_F_IPV6_CSUM;
13103 }
13104
13105 /* Determine TSO capabilities */
13106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13108 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13109 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13111 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13112 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13113 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13115 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13116 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13117 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13118 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13119 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13120 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13121 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13122 tp->fw_needed = FIRMWARE_TG3TSO5;
13123 else
13124 tp->fw_needed = FIRMWARE_TG3TSO;
13125 }
13126
13127 tp->irq_max = 1;
13128
13129 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13130 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13131 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13132 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13133 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13134 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13135 tp->pdev_peer == tp->pdev))
13136 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13137
13138 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13139 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13140 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13141 }
13142
13143 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13144 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13145 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13146 tp->irq_max = TG3_IRQ_MAX_VECS;
13147 }
13148 }
13149
13150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13152 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13153 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13154 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13155 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13156 }
13157
13158 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13159 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13160 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13161
13162 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13163 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13164 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13165 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13166
13167 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13168 &pci_state_reg);
13169
13170 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13171 if (tp->pcie_cap != 0) {
13172 u16 lnkctl;
13173
13174 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13175
13176 pcie_set_readrq(tp->pdev, 4096);
13177
13178 pci_read_config_word(tp->pdev,
13179 tp->pcie_cap + PCI_EXP_LNKCTL,
13180 &lnkctl);
13181 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13182 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13183 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13185 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13186 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13187 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13188 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13189 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13190 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13191 }
13192 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13193 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13194 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13195 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13196 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13197 if (!tp->pcix_cap) {
13198 printk(KERN_ERR PFX "Cannot find PCI-X "
13199 "capability, aborting.\n");
13200 return -EIO;
13201 }
13202
13203 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13204 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13205 }
13206
13207 /* If we have an AMD 762 or VIA K8T800 chipset, write
13208 * reordering to the mailbox registers done by the host
13209 * controller can cause major troubles. We read back from
13210 * every mailbox register write to force the writes to be
13211 * posted to the chip in order.
13212 */
13213 if (pci_dev_present(write_reorder_chipsets) &&
13214 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13215 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13216
13217 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13218 &tp->pci_cacheline_sz);
13219 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13220 &tp->pci_lat_timer);
13221 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13222 tp->pci_lat_timer < 64) {
13223 tp->pci_lat_timer = 64;
13224 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13225 tp->pci_lat_timer);
13226 }
13227
13228 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13229 /* 5700 BX chips need to have their TX producer index
13230 * mailboxes written twice to workaround a bug.
13231 */
13232 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13233
13234 /* If we are in PCI-X mode, enable register write workaround.
13235 *
13236 * The workaround is to use indirect register accesses
13237 * for all chip writes not to mailbox registers.
13238 */
13239 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13240 u32 pm_reg;
13241
13242 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13243
13244 /* The chip can have it's power management PCI config
13245 * space registers clobbered due to this bug.
13246 * So explicitly force the chip into D0 here.
13247 */
13248 pci_read_config_dword(tp->pdev,
13249 tp->pm_cap + PCI_PM_CTRL,
13250 &pm_reg);
13251 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13252 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13253 pci_write_config_dword(tp->pdev,
13254 tp->pm_cap + PCI_PM_CTRL,
13255 pm_reg);
13256
13257 /* Also, force SERR#/PERR# in PCI command. */
13258 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13259 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13260 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13261 }
13262 }
13263
13264 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13265 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13266 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13267 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13268
13269 /* Chip-specific fixup from Broadcom driver */
13270 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13271 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13272 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13273 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13274 }
13275
13276 /* Default fast path register access methods */
13277 tp->read32 = tg3_read32;
13278 tp->write32 = tg3_write32;
13279 tp->read32_mbox = tg3_read32;
13280 tp->write32_mbox = tg3_write32;
13281 tp->write32_tx_mbox = tg3_write32;
13282 tp->write32_rx_mbox = tg3_write32;
13283
13284 /* Various workaround register access methods */
13285 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13286 tp->write32 = tg3_write_indirect_reg32;
13287 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13288 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13289 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13290 /*
13291 * Back to back register writes can cause problems on these
13292 * chips, the workaround is to read back all reg writes
13293 * except those to mailbox regs.
13294 *
13295 * See tg3_write_indirect_reg32().
13296 */
13297 tp->write32 = tg3_write_flush_reg32;
13298 }
13299
13300 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13301 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13302 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13303 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13304 tp->write32_rx_mbox = tg3_write_flush_reg32;
13305 }
13306
13307 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13308 tp->read32 = tg3_read_indirect_reg32;
13309 tp->write32 = tg3_write_indirect_reg32;
13310 tp->read32_mbox = tg3_read_indirect_mbox;
13311 tp->write32_mbox = tg3_write_indirect_mbox;
13312 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13313 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13314
13315 iounmap(tp->regs);
13316 tp->regs = NULL;
13317
13318 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13319 pci_cmd &= ~PCI_COMMAND_MEMORY;
13320 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13321 }
13322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13323 tp->read32_mbox = tg3_read32_mbox_5906;
13324 tp->write32_mbox = tg3_write32_mbox_5906;
13325 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13326 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13327 }
13328
13329 if (tp->write32 == tg3_write_indirect_reg32 ||
13330 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13331 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13332 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13333 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13334
13335 /* Get eeprom hw config before calling tg3_set_power_state().
13336 * In particular, the TG3_FLG2_IS_NIC flag must be
13337 * determined before calling tg3_set_power_state() so that
13338 * we know whether or not to switch out of Vaux power.
13339 * When the flag is set, it means that GPIO1 is used for eeprom
13340 * write protect and also implies that it is a LOM where GPIOs
13341 * are not used to switch power.
13342 */
13343 tg3_get_eeprom_hw_cfg(tp);
13344
13345 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13346 /* Allow reads and writes to the
13347 * APE register and memory space.
13348 */
13349 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13350 PCISTATE_ALLOW_APE_SHMEM_WR;
13351 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13352 pci_state_reg);
13353 }
13354
13355 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13356 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13357 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13358 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13359 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13360 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13361 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13362
13363 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13364 * GPIO1 driven high will bring 5700's external PHY out of reset.
13365 * It is also used as eeprom write protect on LOMs.
13366 */
13367 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13368 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13369 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13370 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13371 GRC_LCLCTRL_GPIO_OUTPUT1);
13372 /* Unused GPIO3 must be driven as output on 5752 because there
13373 * are no pull-up resistors on unused GPIO pins.
13374 */
13375 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13376 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13377
13378 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13379 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13380 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13381 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13382
13383 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13384 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13385 /* Turn off the debug UART. */
13386 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13387 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13388 /* Keep VMain power. */
13389 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13390 GRC_LCLCTRL_GPIO_OUTPUT0;
13391 }
13392
13393 /* Force the chip into D0. */
13394 err = tg3_set_power_state(tp, PCI_D0);
13395 if (err) {
13396 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13397 pci_name(tp->pdev));
13398 return err;
13399 }
13400
13401 /* Derive initial jumbo mode from MTU assigned in
13402 * ether_setup() via the alloc_etherdev() call
13403 */
13404 if (tp->dev->mtu > ETH_DATA_LEN &&
13405 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13406 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13407
13408 /* Determine WakeOnLan speed to use. */
13409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13410 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13411 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13412 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13413 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13414 } else {
13415 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13416 }
13417
13418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13419 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13420
13421 /* A few boards don't want Ethernet@WireSpeed phy feature */
13422 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13423 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13424 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13425 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13426 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13427 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13428 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13429
13430 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13431 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13432 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13433 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13434 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13435
13436 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13437 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13438 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13439 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13440 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13441 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13443 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13444 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13445 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13446 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13447 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13448 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13449 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13450 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13451 } else
13452 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13453 }
13454
13455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13456 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13457 tp->phy_otp = tg3_read_otp_phycfg(tp);
13458 if (tp->phy_otp == 0)
13459 tp->phy_otp = TG3_OTP_DEFAULT;
13460 }
13461
13462 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13463 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13464 else
13465 tp->mi_mode = MAC_MI_MODE_BASE;
13466
13467 tp->coalesce_mode = 0;
13468 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13469 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13470 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13471
13472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13474 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13475
13476 err = tg3_mdio_init(tp);
13477 if (err)
13478 return err;
13479
13480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13481 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13482 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13483 return -ENOTSUPP;
13484
13485 /* Initialize data/descriptor byte/word swapping. */
13486 val = tr32(GRC_MODE);
13487 val &= GRC_MODE_HOST_STACKUP;
13488 tw32(GRC_MODE, val | tp->grc_mode);
13489
13490 tg3_switch_clocks(tp);
13491
13492 /* Clear this out for sanity. */
13493 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13494
13495 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13496 &pci_state_reg);
13497 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13498 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13499 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13500
13501 if (chiprevid == CHIPREV_ID_5701_A0 ||
13502 chiprevid == CHIPREV_ID_5701_B0 ||
13503 chiprevid == CHIPREV_ID_5701_B2 ||
13504 chiprevid == CHIPREV_ID_5701_B5) {
13505 void __iomem *sram_base;
13506
13507 /* Write some dummy words into the SRAM status block
13508 * area, see if it reads back correctly. If the return
13509 * value is bad, force enable the PCIX workaround.
13510 */
13511 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13512
13513 writel(0x00000000, sram_base);
13514 writel(0x00000000, sram_base + 4);
13515 writel(0xffffffff, sram_base + 4);
13516 if (readl(sram_base) != 0x00000000)
13517 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13518 }
13519 }
13520
13521 udelay(50);
13522 tg3_nvram_init(tp);
13523
13524 grc_misc_cfg = tr32(GRC_MISC_CFG);
13525 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13526
13527 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13528 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13529 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13530 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13531
13532 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13533 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13534 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13535 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13536 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13537 HOSTCC_MODE_CLRTICK_TXBD);
13538
13539 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13540 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13541 tp->misc_host_ctrl);
13542 }
13543
13544 /* Preserve the APE MAC_MODE bits */
13545 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13546 tp->mac_mode = tr32(MAC_MODE) |
13547 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13548 else
13549 tp->mac_mode = TG3_DEF_MAC_MODE;
13550
13551 /* these are limited to 10/100 only */
13552 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13553 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13554 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13555 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13556 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13557 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13558 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13559 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13560 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13561 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13562 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13563 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13564 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13565 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13566
13567 err = tg3_phy_probe(tp);
13568 if (err) {
13569 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13570 pci_name(tp->pdev), err);
13571 /* ... but do not return immediately ... */
13572 tg3_mdio_fini(tp);
13573 }
13574
13575 tg3_read_partno(tp);
13576 tg3_read_fw_ver(tp);
13577
13578 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13579 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13580 } else {
13581 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13582 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13583 else
13584 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13585 }
13586
13587 /* 5700 {AX,BX} chips have a broken status block link
13588 * change bit implementation, so we must use the
13589 * status register in those cases.
13590 */
13591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13592 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13593 else
13594 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13595
13596 /* The led_ctrl is set during tg3_phy_probe, here we might
13597 * have to force the link status polling mechanism based
13598 * upon subsystem IDs.
13599 */
13600 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13601 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13602 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13603 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13604 TG3_FLAG_USE_LINKCHG_REG);
13605 }
13606
13607 /* For all SERDES we poll the MAC status register. */
13608 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13609 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13610 else
13611 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13612
13613 tp->rx_offset = NET_IP_ALIGN;
13614 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13615 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13616 tp->rx_offset = 0;
13617
13618 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13619
13620 /* Increment the rx prod index on the rx std ring by at most
13621 * 8 for these chips to workaround hw errata.
13622 */
13623 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13624 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13625 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13626 tp->rx_std_max_post = 8;
13627
13628 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13629 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13630 PCIE_PWR_MGMT_L1_THRESH_MSK;
13631
13632 return err;
13633}
13634
13635#ifdef CONFIG_SPARC
13636static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13637{
13638 struct net_device *dev = tp->dev;
13639 struct pci_dev *pdev = tp->pdev;
13640 struct device_node *dp = pci_device_to_OF_node(pdev);
13641 const unsigned char *addr;
13642 int len;
13643
13644 addr = of_get_property(dp, "local-mac-address", &len);
13645 if (addr && len == 6) {
13646 memcpy(dev->dev_addr, addr, 6);
13647 memcpy(dev->perm_addr, dev->dev_addr, 6);
13648 return 0;
13649 }
13650 return -ENODEV;
13651}
13652
13653static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13654{
13655 struct net_device *dev = tp->dev;
13656
13657 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13658 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13659 return 0;
13660}
13661#endif
13662
13663static int __devinit tg3_get_device_address(struct tg3 *tp)
13664{
13665 struct net_device *dev = tp->dev;
13666 u32 hi, lo, mac_offset;
13667 int addr_ok = 0;
13668
13669#ifdef CONFIG_SPARC
13670 if (!tg3_get_macaddr_sparc(tp))
13671 return 0;
13672#endif
13673
13674 mac_offset = 0x7c;
13675 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13676 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13677 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13678 mac_offset = 0xcc;
13679 if (tg3_nvram_lock(tp))
13680 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13681 else
13682 tg3_nvram_unlock(tp);
13683 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13684 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13685 mac_offset = 0xcc;
13686 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13687 mac_offset = 0x10;
13688
13689 /* First try to get it from MAC address mailbox. */
13690 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13691 if ((hi >> 16) == 0x484b) {
13692 dev->dev_addr[0] = (hi >> 8) & 0xff;
13693 dev->dev_addr[1] = (hi >> 0) & 0xff;
13694
13695 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13696 dev->dev_addr[2] = (lo >> 24) & 0xff;
13697 dev->dev_addr[3] = (lo >> 16) & 0xff;
13698 dev->dev_addr[4] = (lo >> 8) & 0xff;
13699 dev->dev_addr[5] = (lo >> 0) & 0xff;
13700
13701 /* Some old bootcode may report a 0 MAC address in SRAM */
13702 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13703 }
13704 if (!addr_ok) {
13705 /* Next, try NVRAM. */
13706 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13707 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13708 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13709 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13710 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13711 }
13712 /* Finally just fetch it out of the MAC control regs. */
13713 else {
13714 hi = tr32(MAC_ADDR_0_HIGH);
13715 lo = tr32(MAC_ADDR_0_LOW);
13716
13717 dev->dev_addr[5] = lo & 0xff;
13718 dev->dev_addr[4] = (lo >> 8) & 0xff;
13719 dev->dev_addr[3] = (lo >> 16) & 0xff;
13720 dev->dev_addr[2] = (lo >> 24) & 0xff;
13721 dev->dev_addr[1] = hi & 0xff;
13722 dev->dev_addr[0] = (hi >> 8) & 0xff;
13723 }
13724 }
13725
13726 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13727#ifdef CONFIG_SPARC
13728 if (!tg3_get_default_macaddr_sparc(tp))
13729 return 0;
13730#endif
13731 return -EINVAL;
13732 }
13733 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13734 return 0;
13735}
13736
13737#define BOUNDARY_SINGLE_CACHELINE 1
13738#define BOUNDARY_MULTI_CACHELINE 2
13739
13740static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13741{
13742 int cacheline_size;
13743 u8 byte;
13744 int goal;
13745
13746 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13747 if (byte == 0)
13748 cacheline_size = 1024;
13749 else
13750 cacheline_size = (int) byte * 4;
13751
13752 /* On 5703 and later chips, the boundary bits have no
13753 * effect.
13754 */
13755 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13756 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13757 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13758 goto out;
13759
13760#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13761 goal = BOUNDARY_MULTI_CACHELINE;
13762#else
13763#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13764 goal = BOUNDARY_SINGLE_CACHELINE;
13765#else
13766 goal = 0;
13767#endif
13768#endif
13769
13770 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13771 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13772 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13773 goto out;
13774 }
13775
13776 if (!goal)
13777 goto out;
13778
13779 /* PCI controllers on most RISC systems tend to disconnect
13780 * when a device tries to burst across a cache-line boundary.
13781 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13782 *
13783 * Unfortunately, for PCI-E there are only limited
13784 * write-side controls for this, and thus for reads
13785 * we will still get the disconnects. We'll also waste
13786 * these PCI cycles for both read and write for chips
13787 * other than 5700 and 5701 which do not implement the
13788 * boundary bits.
13789 */
13790 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13791 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13792 switch (cacheline_size) {
13793 case 16:
13794 case 32:
13795 case 64:
13796 case 128:
13797 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13798 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13799 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13800 } else {
13801 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13802 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13803 }
13804 break;
13805
13806 case 256:
13807 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13808 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13809 break;
13810
13811 default:
13812 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13813 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13814 break;
13815 }
13816 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13817 switch (cacheline_size) {
13818 case 16:
13819 case 32:
13820 case 64:
13821 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13822 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13823 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13824 break;
13825 }
13826 /* fallthrough */
13827 case 128:
13828 default:
13829 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13830 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13831 break;
13832 }
13833 } else {
13834 switch (cacheline_size) {
13835 case 16:
13836 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13837 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13838 DMA_RWCTRL_WRITE_BNDRY_16);
13839 break;
13840 }
13841 /* fallthrough */
13842 case 32:
13843 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13844 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13845 DMA_RWCTRL_WRITE_BNDRY_32);
13846 break;
13847 }
13848 /* fallthrough */
13849 case 64:
13850 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13851 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13852 DMA_RWCTRL_WRITE_BNDRY_64);
13853 break;
13854 }
13855 /* fallthrough */
13856 case 128:
13857 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13858 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13859 DMA_RWCTRL_WRITE_BNDRY_128);
13860 break;
13861 }
13862 /* fallthrough */
13863 case 256:
13864 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13865 DMA_RWCTRL_WRITE_BNDRY_256);
13866 break;
13867 case 512:
13868 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13869 DMA_RWCTRL_WRITE_BNDRY_512);
13870 break;
13871 case 1024:
13872 default:
13873 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13874 DMA_RWCTRL_WRITE_BNDRY_1024);
13875 break;
13876 }
13877 }
13878
13879out:
13880 return val;
13881}
13882
13883static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13884{
13885 struct tg3_internal_buffer_desc test_desc;
13886 u32 sram_dma_descs;
13887 int i, ret;
13888
13889 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13890
13891 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13892 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13893 tw32(RDMAC_STATUS, 0);
13894 tw32(WDMAC_STATUS, 0);
13895
13896 tw32(BUFMGR_MODE, 0);
13897 tw32(FTQ_RESET, 0);
13898
13899 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13900 test_desc.addr_lo = buf_dma & 0xffffffff;
13901 test_desc.nic_mbuf = 0x00002100;
13902 test_desc.len = size;
13903
13904 /*
13905 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13906 * the *second* time the tg3 driver was getting loaded after an
13907 * initial scan.
13908 *
13909 * Broadcom tells me:
13910 * ...the DMA engine is connected to the GRC block and a DMA
13911 * reset may affect the GRC block in some unpredictable way...
13912 * The behavior of resets to individual blocks has not been tested.
13913 *
13914 * Broadcom noted the GRC reset will also reset all sub-components.
13915 */
13916 if (to_device) {
13917 test_desc.cqid_sqid = (13 << 8) | 2;
13918
13919 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13920 udelay(40);
13921 } else {
13922 test_desc.cqid_sqid = (16 << 8) | 7;
13923
13924 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13925 udelay(40);
13926 }
13927 test_desc.flags = 0x00000005;
13928
13929 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13930 u32 val;
13931
13932 val = *(((u32 *)&test_desc) + i);
13933 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13934 sram_dma_descs + (i * sizeof(u32)));
13935 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13936 }
13937 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13938
13939 if (to_device) {
13940 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13941 } else {
13942 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13943 }
13944
13945 ret = -ENODEV;
13946 for (i = 0; i < 40; i++) {
13947 u32 val;
13948
13949 if (to_device)
13950 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13951 else
13952 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13953 if ((val & 0xffff) == sram_dma_descs) {
13954 ret = 0;
13955 break;
13956 }
13957
13958 udelay(100);
13959 }
13960
13961 return ret;
13962}
13963
13964#define TEST_BUFFER_SIZE 0x2000
13965
13966static int __devinit tg3_test_dma(struct tg3 *tp)
13967{
13968 dma_addr_t buf_dma;
13969 u32 *buf, saved_dma_rwctrl;
13970 int ret = 0;
13971
13972 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13973 if (!buf) {
13974 ret = -ENOMEM;
13975 goto out_nofree;
13976 }
13977
13978 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13979 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13980
13981 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13982
13983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13985 goto out;
13986
13987 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13988 /* DMA read watermark not used on PCIE */
13989 tp->dma_rwctrl |= 0x00180000;
13990 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13993 tp->dma_rwctrl |= 0x003f0000;
13994 else
13995 tp->dma_rwctrl |= 0x003f000f;
13996 } else {
13997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13999 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14000 u32 read_water = 0x7;
14001
14002 /* If the 5704 is behind the EPB bridge, we can
14003 * do the less restrictive ONE_DMA workaround for
14004 * better performance.
14005 */
14006 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14007 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14008 tp->dma_rwctrl |= 0x8000;
14009 else if (ccval == 0x6 || ccval == 0x7)
14010 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14011
14012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14013 read_water = 4;
14014 /* Set bit 23 to enable PCIX hw bug fix */
14015 tp->dma_rwctrl |=
14016 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14017 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14018 (1 << 23);
14019 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14020 /* 5780 always in PCIX mode */
14021 tp->dma_rwctrl |= 0x00144000;
14022 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14023 /* 5714 always in PCIX mode */
14024 tp->dma_rwctrl |= 0x00148000;
14025 } else {
14026 tp->dma_rwctrl |= 0x001b000f;
14027 }
14028 }
14029
14030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14032 tp->dma_rwctrl &= 0xfffffff0;
14033
14034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14036 /* Remove this if it causes problems for some boards. */
14037 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14038
14039 /* On 5700/5701 chips, we need to set this bit.
14040 * Otherwise the chip will issue cacheline transactions
14041 * to streamable DMA memory with not all the byte
14042 * enables turned on. This is an error on several
14043 * RISC PCI controllers, in particular sparc64.
14044 *
14045 * On 5703/5704 chips, this bit has been reassigned
14046 * a different meaning. In particular, it is used
14047 * on those chips to enable a PCI-X workaround.
14048 */
14049 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14050 }
14051
14052 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14053
14054#if 0
14055 /* Unneeded, already done by tg3_get_invariants. */
14056 tg3_switch_clocks(tp);
14057#endif
14058
14059 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14060 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14061 goto out;
14062
14063 /* It is best to perform DMA test with maximum write burst size
14064 * to expose the 5700/5701 write DMA bug.
14065 */
14066 saved_dma_rwctrl = tp->dma_rwctrl;
14067 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14068 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14069
14070 while (1) {
14071 u32 *p = buf, i;
14072
14073 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14074 p[i] = i;
14075
14076 /* Send the buffer to the chip. */
14077 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14078 if (ret) {
14079 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14080 break;
14081 }
14082
14083#if 0
14084 /* validate data reached card RAM correctly. */
14085 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14086 u32 val;
14087 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14088 if (le32_to_cpu(val) != p[i]) {
14089 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
14090 /* ret = -ENODEV here? */
14091 }
14092 p[i] = 0;
14093 }
14094#endif
14095 /* Now read it back. */
14096 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14097 if (ret) {
14098 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14099
14100 break;
14101 }
14102
14103 /* Verify it. */
14104 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14105 if (p[i] == i)
14106 continue;
14107
14108 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14109 DMA_RWCTRL_WRITE_BNDRY_16) {
14110 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14111 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14112 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14113 break;
14114 } else {
14115 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14116 ret = -ENODEV;
14117 goto out;
14118 }
14119 }
14120
14121 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14122 /* Success. */
14123 ret = 0;
14124 break;
14125 }
14126 }
14127 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14128 DMA_RWCTRL_WRITE_BNDRY_16) {
14129 static struct pci_device_id dma_wait_state_chipsets[] = {
14130 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14131 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14132 { },
14133 };
14134
14135 /* DMA test passed without adjusting DMA boundary,
14136 * now look for chipsets that are known to expose the
14137 * DMA bug without failing the test.
14138 */
14139 if (pci_dev_present(dma_wait_state_chipsets)) {
14140 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14141 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14142 }
14143 else
14144 /* Safe to use the calculated DMA boundary. */
14145 tp->dma_rwctrl = saved_dma_rwctrl;
14146
14147 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14148 }
14149
14150out:
14151 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14152out_nofree:
14153 return ret;
14154}
14155
14156static void __devinit tg3_init_link_config(struct tg3 *tp)
14157{
14158 tp->link_config.advertising =
14159 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14160 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14161 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14162 ADVERTISED_Autoneg | ADVERTISED_MII);
14163 tp->link_config.speed = SPEED_INVALID;
14164 tp->link_config.duplex = DUPLEX_INVALID;
14165 tp->link_config.autoneg = AUTONEG_ENABLE;
14166 tp->link_config.active_speed = SPEED_INVALID;
14167 tp->link_config.active_duplex = DUPLEX_INVALID;
14168 tp->link_config.phy_is_low_power = 0;
14169 tp->link_config.orig_speed = SPEED_INVALID;
14170 tp->link_config.orig_duplex = DUPLEX_INVALID;
14171 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14172}
14173
14174static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14175{
14176 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14177 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14178 tp->bufmgr_config.mbuf_read_dma_low_water =
14179 DEFAULT_MB_RDMA_LOW_WATER_5705;
14180 tp->bufmgr_config.mbuf_mac_rx_low_water =
14181 DEFAULT_MB_MACRX_LOW_WATER_57765;
14182 tp->bufmgr_config.mbuf_high_water =
14183 DEFAULT_MB_HIGH_WATER_57765;
14184
14185 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14186 DEFAULT_MB_RDMA_LOW_WATER_5705;
14187 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14188 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14189 tp->bufmgr_config.mbuf_high_water_jumbo =
14190 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14191 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14192 tp->bufmgr_config.mbuf_read_dma_low_water =
14193 DEFAULT_MB_RDMA_LOW_WATER_5705;
14194 tp->bufmgr_config.mbuf_mac_rx_low_water =
14195 DEFAULT_MB_MACRX_LOW_WATER_5705;
14196 tp->bufmgr_config.mbuf_high_water =
14197 DEFAULT_MB_HIGH_WATER_5705;
14198 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14199 tp->bufmgr_config.mbuf_mac_rx_low_water =
14200 DEFAULT_MB_MACRX_LOW_WATER_5906;
14201 tp->bufmgr_config.mbuf_high_water =
14202 DEFAULT_MB_HIGH_WATER_5906;
14203 }
14204
14205 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14206 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14207 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14208 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14209 tp->bufmgr_config.mbuf_high_water_jumbo =
14210 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14211 } else {
14212 tp->bufmgr_config.mbuf_read_dma_low_water =
14213 DEFAULT_MB_RDMA_LOW_WATER;
14214 tp->bufmgr_config.mbuf_mac_rx_low_water =
14215 DEFAULT_MB_MACRX_LOW_WATER;
14216 tp->bufmgr_config.mbuf_high_water =
14217 DEFAULT_MB_HIGH_WATER;
14218
14219 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14220 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14221 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14222 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14223 tp->bufmgr_config.mbuf_high_water_jumbo =
14224 DEFAULT_MB_HIGH_WATER_JUMBO;
14225 }
14226
14227 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14228 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14229}
14230
14231static char * __devinit tg3_phy_string(struct tg3 *tp)
14232{
14233 switch (tp->phy_id & PHY_ID_MASK) {
14234 case PHY_ID_BCM5400: return "5400";
14235 case PHY_ID_BCM5401: return "5401";
14236 case PHY_ID_BCM5411: return "5411";
14237 case PHY_ID_BCM5701: return "5701";
14238 case PHY_ID_BCM5703: return "5703";
14239 case PHY_ID_BCM5704: return "5704";
14240 case PHY_ID_BCM5705: return "5705";
14241 case PHY_ID_BCM5750: return "5750";
14242 case PHY_ID_BCM5752: return "5752";
14243 case PHY_ID_BCM5714: return "5714";
14244 case PHY_ID_BCM5780: return "5780";
14245 case PHY_ID_BCM5755: return "5755";
14246 case PHY_ID_BCM5787: return "5787";
14247 case PHY_ID_BCM5784: return "5784";
14248 case PHY_ID_BCM5756: return "5722/5756";
14249 case PHY_ID_BCM5906: return "5906";
14250 case PHY_ID_BCM5761: return "5761";
14251 case PHY_ID_BCM5718C: return "5718C";
14252 case PHY_ID_BCM5718S: return "5718S";
14253 case PHY_ID_BCM57765: return "57765";
14254 case PHY_ID_BCM8002: return "8002/serdes";
14255 case 0: return "serdes";
14256 default: return "unknown";
14257 }
14258}
14259
14260static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14261{
14262 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14263 strcpy(str, "PCI Express");
14264 return str;
14265 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14266 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14267
14268 strcpy(str, "PCIX:");
14269
14270 if ((clock_ctrl == 7) ||
14271 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14272 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14273 strcat(str, "133MHz");
14274 else if (clock_ctrl == 0)
14275 strcat(str, "33MHz");
14276 else if (clock_ctrl == 2)
14277 strcat(str, "50MHz");
14278 else if (clock_ctrl == 4)
14279 strcat(str, "66MHz");
14280 else if (clock_ctrl == 6)
14281 strcat(str, "100MHz");
14282 } else {
14283 strcpy(str, "PCI:");
14284 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14285 strcat(str, "66MHz");
14286 else
14287 strcat(str, "33MHz");
14288 }
14289 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14290 strcat(str, ":32-bit");
14291 else
14292 strcat(str, ":64-bit");
14293 return str;
14294}
14295
14296static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14297{
14298 struct pci_dev *peer;
14299 unsigned int func, devnr = tp->pdev->devfn & ~7;
14300
14301 for (func = 0; func < 8; func++) {
14302 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14303 if (peer && peer != tp->pdev)
14304 break;
14305 pci_dev_put(peer);
14306 }
14307 /* 5704 can be configured in single-port mode, set peer to
14308 * tp->pdev in that case.
14309 */
14310 if (!peer) {
14311 peer = tp->pdev;
14312 return peer;
14313 }
14314
14315 /*
14316 * We don't need to keep the refcount elevated; there's no way
14317 * to remove one half of this device without removing the other
14318 */
14319 pci_dev_put(peer);
14320
14321 return peer;
14322}
14323
14324static void __devinit tg3_init_coal(struct tg3 *tp)
14325{
14326 struct ethtool_coalesce *ec = &tp->coal;
14327
14328 memset(ec, 0, sizeof(*ec));
14329 ec->cmd = ETHTOOL_GCOALESCE;
14330 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14331 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14332 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14333 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14334 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14335 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14336 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14337 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14338 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14339
14340 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14341 HOSTCC_MODE_CLRTICK_TXBD)) {
14342 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14343 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14344 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14345 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14346 }
14347
14348 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14349 ec->rx_coalesce_usecs_irq = 0;
14350 ec->tx_coalesce_usecs_irq = 0;
14351 ec->stats_block_coalesce_usecs = 0;
14352 }
14353}
14354
14355static const struct net_device_ops tg3_netdev_ops = {
14356 .ndo_open = tg3_open,
14357 .ndo_stop = tg3_close,
14358 .ndo_start_xmit = tg3_start_xmit,
14359 .ndo_get_stats = tg3_get_stats,
14360 .ndo_validate_addr = eth_validate_addr,
14361 .ndo_set_multicast_list = tg3_set_rx_mode,
14362 .ndo_set_mac_address = tg3_set_mac_addr,
14363 .ndo_do_ioctl = tg3_ioctl,
14364 .ndo_tx_timeout = tg3_tx_timeout,
14365 .ndo_change_mtu = tg3_change_mtu,
14366#if TG3_VLAN_TAG_USED
14367 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14368#endif
14369#ifdef CONFIG_NET_POLL_CONTROLLER
14370 .ndo_poll_controller = tg3_poll_controller,
14371#endif
14372};
14373
14374static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14375 .ndo_open = tg3_open,
14376 .ndo_stop = tg3_close,
14377 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14378 .ndo_get_stats = tg3_get_stats,
14379 .ndo_validate_addr = eth_validate_addr,
14380 .ndo_set_multicast_list = tg3_set_rx_mode,
14381 .ndo_set_mac_address = tg3_set_mac_addr,
14382 .ndo_do_ioctl = tg3_ioctl,
14383 .ndo_tx_timeout = tg3_tx_timeout,
14384 .ndo_change_mtu = tg3_change_mtu,
14385#if TG3_VLAN_TAG_USED
14386 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14387#endif
14388#ifdef CONFIG_NET_POLL_CONTROLLER
14389 .ndo_poll_controller = tg3_poll_controller,
14390#endif
14391};
14392
14393static int __devinit tg3_init_one(struct pci_dev *pdev,
14394 const struct pci_device_id *ent)
14395{
14396 static int tg3_version_printed = 0;
14397 struct net_device *dev;
14398 struct tg3 *tp;
14399 int i, err, pm_cap;
14400 u32 sndmbx, rcvmbx, intmbx;
14401 char str[40];
14402 u64 dma_mask, persist_dma_mask;
14403
14404 if (tg3_version_printed++ == 0)
14405 printk(KERN_INFO "%s", version);
14406
14407 err = pci_enable_device(pdev);
14408 if (err) {
14409 printk(KERN_ERR PFX "Cannot enable PCI device, "
14410 "aborting.\n");
14411 return err;
14412 }
14413
14414 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14415 if (err) {
14416 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14417 "aborting.\n");
14418 goto err_out_disable_pdev;
14419 }
14420
14421 pci_set_master(pdev);
14422
14423 /* Find power-management capability. */
14424 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14425 if (pm_cap == 0) {
14426 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14427 "aborting.\n");
14428 err = -EIO;
14429 goto err_out_free_res;
14430 }
14431
14432 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14433 if (!dev) {
14434 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14435 err = -ENOMEM;
14436 goto err_out_free_res;
14437 }
14438
14439 SET_NETDEV_DEV(dev, &pdev->dev);
14440
14441#if TG3_VLAN_TAG_USED
14442 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14443#endif
14444
14445 tp = netdev_priv(dev);
14446 tp->pdev = pdev;
14447 tp->dev = dev;
14448 tp->pm_cap = pm_cap;
14449 tp->rx_mode = TG3_DEF_RX_MODE;
14450 tp->tx_mode = TG3_DEF_TX_MODE;
14451
14452 if (tg3_debug > 0)
14453 tp->msg_enable = tg3_debug;
14454 else
14455 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14456
14457 /* The word/byte swap controls here control register access byte
14458 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14459 * setting below.
14460 */
14461 tp->misc_host_ctrl =
14462 MISC_HOST_CTRL_MASK_PCI_INT |
14463 MISC_HOST_CTRL_WORD_SWAP |
14464 MISC_HOST_CTRL_INDIR_ACCESS |
14465 MISC_HOST_CTRL_PCISTATE_RW;
14466
14467 /* The NONFRM (non-frame) byte/word swap controls take effect
14468 * on descriptor entries, anything which isn't packet data.
14469 *
14470 * The StrongARM chips on the board (one for tx, one for rx)
14471 * are running in big-endian mode.
14472 */
14473 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14474 GRC_MODE_WSWAP_NONFRM_DATA);
14475#ifdef __BIG_ENDIAN
14476 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14477#endif
14478 spin_lock_init(&tp->lock);
14479 spin_lock_init(&tp->indirect_lock);
14480 INIT_WORK(&tp->reset_task, tg3_reset_task);
14481
14482 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14483 if (!tp->regs) {
14484 printk(KERN_ERR PFX "Cannot map device registers, "
14485 "aborting.\n");
14486 err = -ENOMEM;
14487 goto err_out_free_dev;
14488 }
14489
14490 tg3_init_link_config(tp);
14491
14492 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14493 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14494
14495 dev->ethtool_ops = &tg3_ethtool_ops;
14496 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14497 dev->irq = pdev->irq;
14498
14499 err = tg3_get_invariants(tp);
14500 if (err) {
14501 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14502 "aborting.\n");
14503 goto err_out_iounmap;
14504 }
14505
14506 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14507 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14508 dev->netdev_ops = &tg3_netdev_ops;
14509 else
14510 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14511
14512
14513 /* The EPB bridge inside 5714, 5715, and 5780 and any
14514 * device behind the EPB cannot support DMA addresses > 40-bit.
14515 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14516 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14517 * do DMA address check in tg3_start_xmit().
14518 */
14519 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14520 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14521 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14522 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14523#ifdef CONFIG_HIGHMEM
14524 dma_mask = DMA_BIT_MASK(64);
14525#endif
14526 } else
14527 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14528
14529 /* Configure DMA attributes. */
14530 if (dma_mask > DMA_BIT_MASK(32)) {
14531 err = pci_set_dma_mask(pdev, dma_mask);
14532 if (!err) {
14533 dev->features |= NETIF_F_HIGHDMA;
14534 err = pci_set_consistent_dma_mask(pdev,
14535 persist_dma_mask);
14536 if (err < 0) {
14537 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14538 "DMA for consistent allocations\n");
14539 goto err_out_iounmap;
14540 }
14541 }
14542 }
14543 if (err || dma_mask == DMA_BIT_MASK(32)) {
14544 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14545 if (err) {
14546 printk(KERN_ERR PFX "No usable DMA configuration, "
14547 "aborting.\n");
14548 goto err_out_iounmap;
14549 }
14550 }
14551
14552 tg3_init_bufmgr_config(tp);
14553
14554 /* Selectively allow TSO based on operating conditions */
14555 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14556 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14557 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14558 else {
14559 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14560 tp->fw_needed = NULL;
14561 }
14562
14563 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14564 tp->fw_needed = FIRMWARE_TG3;
14565
14566 /* TSO is on by default on chips that support hardware TSO.
14567 * Firmware TSO on older chips gives lower performance, so it
14568 * is off by default, but can be enabled using ethtool.
14569 */
14570 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14571 (dev->features & NETIF_F_IP_CSUM))
14572 dev->features |= NETIF_F_TSO;
14573
14574 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14575 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14576 if (dev->features & NETIF_F_IPV6_CSUM)
14577 dev->features |= NETIF_F_TSO6;
14578 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14579 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14580 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14581 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14582 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14583 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14584 dev->features |= NETIF_F_TSO_ECN;
14585 }
14586
14587 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14588 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14589 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14590 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14591 tp->rx_pending = 63;
14592 }
14593
14594 err = tg3_get_device_address(tp);
14595 if (err) {
14596 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14597 "aborting.\n");
14598 goto err_out_iounmap;
14599 }
14600
14601 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14602 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14603 if (!tp->aperegs) {
14604 printk(KERN_ERR PFX "Cannot map APE registers, "
14605 "aborting.\n");
14606 err = -ENOMEM;
14607 goto err_out_iounmap;
14608 }
14609
14610 tg3_ape_lock_init(tp);
14611
14612 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14613 tg3_read_dash_ver(tp);
14614 }
14615
14616 /*
14617 * Reset chip in case UNDI or EFI driver did not shutdown
14618 * DMA self test will enable WDMAC and we'll see (spurious)
14619 * pending DMA on the PCI bus at that point.
14620 */
14621 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14622 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14623 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14624 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14625 }
14626
14627 err = tg3_test_dma(tp);
14628 if (err) {
14629 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14630 goto err_out_apeunmap;
14631 }
14632
14633 /* flow control autonegotiation is default behavior */
14634 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14635 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14636
14637 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14638 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14639 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14640 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14641 struct tg3_napi *tnapi = &tp->napi[i];
14642
14643 tnapi->tp = tp;
14644 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14645
14646 tnapi->int_mbox = intmbx;
14647 if (i < 4)
14648 intmbx += 0x8;
14649 else
14650 intmbx += 0x4;
14651
14652 tnapi->consmbox = rcvmbx;
14653 tnapi->prodmbox = sndmbx;
14654
14655 if (i) {
14656 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14657 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14658 } else {
14659 tnapi->coal_now = HOSTCC_MODE_NOW;
14660 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14661 }
14662
14663 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14664 break;
14665
14666 /*
14667 * If we support MSIX, we'll be using RSS. If we're using
14668 * RSS, the first vector only handles link interrupts and the
14669 * remaining vectors handle rx and tx interrupts. Reuse the
14670 * mailbox values for the next iteration. The values we setup
14671 * above are still useful for the single vectored mode.
14672 */
14673 if (!i)
14674 continue;
14675
14676 rcvmbx += 0x8;
14677
14678 if (sndmbx & 0x4)
14679 sndmbx -= 0x4;
14680 else
14681 sndmbx += 0xc;
14682 }
14683
14684 tg3_init_coal(tp);
14685
14686 pci_set_drvdata(pdev, dev);
14687
14688 err = register_netdev(dev);
14689 if (err) {
14690 printk(KERN_ERR PFX "Cannot register net device, "
14691 "aborting.\n");
14692 goto err_out_apeunmap;
14693 }
14694
14695 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14696 dev->name,
14697 tp->board_part_number,
14698 tp->pci_chip_rev_id,
14699 tg3_bus_string(tp, str),
14700 dev->dev_addr);
14701
14702 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14703 struct phy_device *phydev;
14704 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14705 printk(KERN_INFO
14706 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14707 tp->dev->name, phydev->drv->name,
14708 dev_name(&phydev->dev));
14709 } else
14710 printk(KERN_INFO
14711 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14712 tp->dev->name, tg3_phy_string(tp),
14713 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14714 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14715 "10/100/1000Base-T")),
14716 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14717
14718 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14719 dev->name,
14720 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14721 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14722 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14723 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14724 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14725 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14726 dev->name, tp->dma_rwctrl,
14727 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14728 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14729
14730 return 0;
14731
14732err_out_apeunmap:
14733 if (tp->aperegs) {
14734 iounmap(tp->aperegs);
14735 tp->aperegs = NULL;
14736 }
14737
14738err_out_iounmap:
14739 if (tp->regs) {
14740 iounmap(tp->regs);
14741 tp->regs = NULL;
14742 }
14743
14744err_out_free_dev:
14745 free_netdev(dev);
14746
14747err_out_free_res:
14748 pci_release_regions(pdev);
14749
14750err_out_disable_pdev:
14751 pci_disable_device(pdev);
14752 pci_set_drvdata(pdev, NULL);
14753 return err;
14754}
14755
14756static void __devexit tg3_remove_one(struct pci_dev *pdev)
14757{
14758 struct net_device *dev = pci_get_drvdata(pdev);
14759
14760 if (dev) {
14761 struct tg3 *tp = netdev_priv(dev);
14762
14763 if (tp->fw)
14764 release_firmware(tp->fw);
14765
14766 flush_scheduled_work();
14767
14768 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14769 tg3_phy_fini(tp);
14770 tg3_mdio_fini(tp);
14771 }
14772
14773 unregister_netdev(dev);
14774 if (tp->aperegs) {
14775 iounmap(tp->aperegs);
14776 tp->aperegs = NULL;
14777 }
14778 if (tp->regs) {
14779 iounmap(tp->regs);
14780 tp->regs = NULL;
14781 }
14782 free_netdev(dev);
14783 pci_release_regions(pdev);
14784 pci_disable_device(pdev);
14785 pci_set_drvdata(pdev, NULL);
14786 }
14787}
14788
14789static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14790{
14791 struct net_device *dev = pci_get_drvdata(pdev);
14792 struct tg3 *tp = netdev_priv(dev);
14793 pci_power_t target_state;
14794 int err;
14795
14796 /* PCI register 4 needs to be saved whether netif_running() or not.
14797 * MSI address and data need to be saved if using MSI and
14798 * netif_running().
14799 */
14800 pci_save_state(pdev);
14801
14802 if (!netif_running(dev))
14803 return 0;
14804
14805 flush_scheduled_work();
14806 tg3_phy_stop(tp);
14807 tg3_netif_stop(tp);
14808
14809 del_timer_sync(&tp->timer);
14810
14811 tg3_full_lock(tp, 1);
14812 tg3_disable_ints(tp);
14813 tg3_full_unlock(tp);
14814
14815 netif_device_detach(dev);
14816
14817 tg3_full_lock(tp, 0);
14818 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14819 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14820 tg3_full_unlock(tp);
14821
14822 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14823
14824 err = tg3_set_power_state(tp, target_state);
14825 if (err) {
14826 int err2;
14827
14828 tg3_full_lock(tp, 0);
14829
14830 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14831 err2 = tg3_restart_hw(tp, 1);
14832 if (err2)
14833 goto out;
14834
14835 tp->timer.expires = jiffies + tp->timer_offset;
14836 add_timer(&tp->timer);
14837
14838 netif_device_attach(dev);
14839 tg3_netif_start(tp);
14840
14841out:
14842 tg3_full_unlock(tp);
14843
14844 if (!err2)
14845 tg3_phy_start(tp);
14846 }
14847
14848 return err;
14849}
14850
14851static int tg3_resume(struct pci_dev *pdev)
14852{
14853 struct net_device *dev = pci_get_drvdata(pdev);
14854 struct tg3 *tp = netdev_priv(dev);
14855 int err;
14856
14857 pci_restore_state(tp->pdev);
14858
14859 if (!netif_running(dev))
14860 return 0;
14861
14862 err = tg3_set_power_state(tp, PCI_D0);
14863 if (err)
14864 return err;
14865
14866 netif_device_attach(dev);
14867
14868 tg3_full_lock(tp, 0);
14869
14870 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14871 err = tg3_restart_hw(tp, 1);
14872 if (err)
14873 goto out;
14874
14875 tp->timer.expires = jiffies + tp->timer_offset;
14876 add_timer(&tp->timer);
14877
14878 tg3_netif_start(tp);
14879
14880out:
14881 tg3_full_unlock(tp);
14882
14883 if (!err)
14884 tg3_phy_start(tp);
14885
14886 return err;
14887}
14888
14889static struct pci_driver tg3_driver = {
14890 .name = DRV_MODULE_NAME,
14891 .id_table = tg3_pci_tbl,
14892 .probe = tg3_init_one,
14893 .remove = __devexit_p(tg3_remove_one),
14894 .suspend = tg3_suspend,
14895 .resume = tg3_resume
14896};
14897
14898static int __init tg3_init(void)
14899{
14900 return pci_register_driver(&tg3_driver);
14901}
14902
14903static void __exit tg3_cleanup(void)
14904{
14905 pci_unregister_driver(&tg3_driver);
14906}
14907
14908module_init(tg3_init);
14909module_exit(tg3_cleanup);
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