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1 | /* | |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
7 | * Copyright (C) 2005-2007 Broadcom Corporation. | |
8 | * | |
9 | * Firmware is: | |
10 | * Derived from proprietary unpublished source code, | |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
16 | */ | |
17 | ||
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/compiler.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/in.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/mii.h> | |
35 | #include <linux/phy.h> | |
36 | #include <linux/brcmphy.h> | |
37 | #include <linux/if_vlan.h> | |
38 | #include <linux/ip.h> | |
39 | #include <linux/tcp.h> | |
40 | #include <linux/workqueue.h> | |
41 | #include <linux/prefetch.h> | |
42 | #include <linux/dma-mapping.h> | |
43 | #include <linux/firmware.h> | |
44 | ||
45 | #include <net/checksum.h> | |
46 | #include <net/ip.h> | |
47 | ||
48 | #include <asm/system.h> | |
49 | #include <asm/io.h> | |
50 | #include <asm/byteorder.h> | |
51 | #include <asm/uaccess.h> | |
52 | ||
53 | #ifdef CONFIG_SPARC | |
54 | #include <asm/idprom.h> | |
55 | #include <asm/prom.h> | |
56 | #endif | |
57 | ||
58 | #define BAR_0 0 | |
59 | #define BAR_2 2 | |
60 | ||
61 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
62 | #define TG3_VLAN_TAG_USED 1 | |
63 | #else | |
64 | #define TG3_VLAN_TAG_USED 0 | |
65 | #endif | |
66 | ||
67 | #include "tg3.h" | |
68 | ||
69 | #define DRV_MODULE_NAME "tg3" | |
70 | #define PFX DRV_MODULE_NAME ": " | |
71 | #define DRV_MODULE_VERSION "3.97" | |
72 | #define DRV_MODULE_RELDATE "December 10, 2008" | |
73 | ||
74 | #define TG3_DEF_MAC_MODE 0 | |
75 | #define TG3_DEF_RX_MODE 0 | |
76 | #define TG3_DEF_TX_MODE 0 | |
77 | #define TG3_DEF_MSG_ENABLE \ | |
78 | (NETIF_MSG_DRV | \ | |
79 | NETIF_MSG_PROBE | \ | |
80 | NETIF_MSG_LINK | \ | |
81 | NETIF_MSG_TIMER | \ | |
82 | NETIF_MSG_IFDOWN | \ | |
83 | NETIF_MSG_IFUP | \ | |
84 | NETIF_MSG_RX_ERR | \ | |
85 | NETIF_MSG_TX_ERR) | |
86 | ||
87 | /* length of time before we decide the hardware is borked, | |
88 | * and dev->tx_timeout() should be called to fix the problem | |
89 | */ | |
90 | #define TG3_TX_TIMEOUT (5 * HZ) | |
91 | ||
92 | /* hardware minimum and maximum for a single frame's data payload */ | |
93 | #define TG3_MIN_MTU 60 | |
94 | #define TG3_MAX_MTU(tp) \ | |
95 | ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500) | |
96 | ||
97 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
98 | * You can't change the ring sizes, but you can change where you place | |
99 | * them in the NIC onboard memory. | |
100 | */ | |
101 | #define TG3_RX_RING_SIZE 512 | |
102 | #define TG3_DEF_RX_RING_PENDING 200 | |
103 | #define TG3_RX_JUMBO_RING_SIZE 256 | |
104 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 | |
105 | ||
106 | /* Do not place this n-ring entries value into the tp struct itself, | |
107 | * we really want to expose these constants to GCC so that modulo et | |
108 | * al. operations are done with shifts and masks instead of with | |
109 | * hw multiply/modulo instructions. Another solution would be to | |
110 | * replace things like '% foo' with '& (foo - 1)'. | |
111 | */ | |
112 | #define TG3_RX_RCB_RING_SIZE(tp) \ | |
113 | ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024) | |
114 | ||
115 | #define TG3_TX_RING_SIZE 512 | |
116 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
117 | ||
118 | #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \ | |
119 | TG3_RX_RING_SIZE) | |
120 | #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \ | |
121 | TG3_RX_JUMBO_RING_SIZE) | |
122 | #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \ | |
123 | TG3_RX_RCB_RING_SIZE(tp)) | |
124 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ | |
125 | TG3_TX_RING_SIZE) | |
126 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) | |
127 | ||
128 | #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64) | |
129 | #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64) | |
130 | ||
131 | /* minimum number of free TX descriptors required to wake up TX process */ | |
132 | #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4) | |
133 | ||
134 | #define TG3_RAW_IP_ALIGN 2 | |
135 | ||
136 | /* number of ETHTOOL_GSTATS u64's */ | |
137 | #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64)) | |
138 | ||
139 | #define TG3_NUM_TEST 6 | |
140 | ||
141 | #define FIRMWARE_TG3 "tigon/tg3.bin" | |
142 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
143 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
144 | ||
145 | static char version[] __devinitdata = | |
146 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | |
147 | ||
148 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
149 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
150 | MODULE_LICENSE("GPL"); | |
151 | MODULE_VERSION(DRV_MODULE_VERSION); | |
152 | MODULE_FIRMWARE(FIRMWARE_TG3); | |
153 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
154 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
155 | ||
156 | ||
157 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ | |
158 | module_param(tg3_debug, int, 0); | |
159 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
160 | ||
161 | static struct pci_device_id tg3_pci_tbl[] = { | |
162 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, | |
163 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
164 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
165 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
166 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
167 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
168 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
169 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
170 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
171 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
172 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
173 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
174 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
175 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
176 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
177 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
178 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
179 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
180 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
181 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
182 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
183 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
184 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)}, | |
185 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, | |
186 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, | |
187 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)}, | |
188 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, | |
189 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)}, | |
190 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, | |
191 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
192 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
193 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
194 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
195 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
196 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
197 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
198 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
199 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
200 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
201 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, | |
202 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, | |
203 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
204 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
205 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, | |
206 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, | |
207 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
208 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
209 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
210 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
211 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
212 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
213 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, | |
214 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
215 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, | |
216 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
217 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, | |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, | |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, | |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)}, | |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, | |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)}, | |
227 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, | |
228 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
234 | {} | |
235 | }; | |
236 | ||
237 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
238 | ||
239 | static const struct { | |
240 | const char string[ETH_GSTRING_LEN]; | |
241 | } ethtool_stats_keys[TG3_NUM_STATS] = { | |
242 | { "rx_octets" }, | |
243 | { "rx_fragments" }, | |
244 | { "rx_ucast_packets" }, | |
245 | { "rx_mcast_packets" }, | |
246 | { "rx_bcast_packets" }, | |
247 | { "rx_fcs_errors" }, | |
248 | { "rx_align_errors" }, | |
249 | { "rx_xon_pause_rcvd" }, | |
250 | { "rx_xoff_pause_rcvd" }, | |
251 | { "rx_mac_ctrl_rcvd" }, | |
252 | { "rx_xoff_entered" }, | |
253 | { "rx_frame_too_long_errors" }, | |
254 | { "rx_jabbers" }, | |
255 | { "rx_undersize_packets" }, | |
256 | { "rx_in_length_errors" }, | |
257 | { "rx_out_length_errors" }, | |
258 | { "rx_64_or_less_octet_packets" }, | |
259 | { "rx_65_to_127_octet_packets" }, | |
260 | { "rx_128_to_255_octet_packets" }, | |
261 | { "rx_256_to_511_octet_packets" }, | |
262 | { "rx_512_to_1023_octet_packets" }, | |
263 | { "rx_1024_to_1522_octet_packets" }, | |
264 | { "rx_1523_to_2047_octet_packets" }, | |
265 | { "rx_2048_to_4095_octet_packets" }, | |
266 | { "rx_4096_to_8191_octet_packets" }, | |
267 | { "rx_8192_to_9022_octet_packets" }, | |
268 | ||
269 | { "tx_octets" }, | |
270 | { "tx_collisions" }, | |
271 | ||
272 | { "tx_xon_sent" }, | |
273 | { "tx_xoff_sent" }, | |
274 | { "tx_flow_control" }, | |
275 | { "tx_mac_errors" }, | |
276 | { "tx_single_collisions" }, | |
277 | { "tx_mult_collisions" }, | |
278 | { "tx_deferred" }, | |
279 | { "tx_excessive_collisions" }, | |
280 | { "tx_late_collisions" }, | |
281 | { "tx_collide_2times" }, | |
282 | { "tx_collide_3times" }, | |
283 | { "tx_collide_4times" }, | |
284 | { "tx_collide_5times" }, | |
285 | { "tx_collide_6times" }, | |
286 | { "tx_collide_7times" }, | |
287 | { "tx_collide_8times" }, | |
288 | { "tx_collide_9times" }, | |
289 | { "tx_collide_10times" }, | |
290 | { "tx_collide_11times" }, | |
291 | { "tx_collide_12times" }, | |
292 | { "tx_collide_13times" }, | |
293 | { "tx_collide_14times" }, | |
294 | { "tx_collide_15times" }, | |
295 | { "tx_ucast_packets" }, | |
296 | { "tx_mcast_packets" }, | |
297 | { "tx_bcast_packets" }, | |
298 | { "tx_carrier_sense_errors" }, | |
299 | { "tx_discards" }, | |
300 | { "tx_errors" }, | |
301 | ||
302 | { "dma_writeq_full" }, | |
303 | { "dma_write_prioq_full" }, | |
304 | { "rxbds_empty" }, | |
305 | { "rx_discards" }, | |
306 | { "rx_errors" }, | |
307 | { "rx_threshold_hit" }, | |
308 | ||
309 | { "dma_readq_full" }, | |
310 | { "dma_read_prioq_full" }, | |
311 | { "tx_comp_queue_full" }, | |
312 | ||
313 | { "ring_set_send_prod_index" }, | |
314 | { "ring_status_update" }, | |
315 | { "nic_irqs" }, | |
316 | { "nic_avoided_irqs" }, | |
317 | { "nic_tx_threshold_hit" } | |
318 | }; | |
319 | ||
320 | static const struct { | |
321 | const char string[ETH_GSTRING_LEN]; | |
322 | } ethtool_test_keys[TG3_NUM_TEST] = { | |
323 | { "nvram test (online) " }, | |
324 | { "link test (online) " }, | |
325 | { "register test (offline)" }, | |
326 | { "memory test (offline)" }, | |
327 | { "loopback test (offline)" }, | |
328 | { "interrupt test (offline)" }, | |
329 | }; | |
330 | ||
331 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) | |
332 | { | |
333 | writel(val, tp->regs + off); | |
334 | } | |
335 | ||
336 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
337 | { | |
338 | return (readl(tp->regs + off)); | |
339 | } | |
340 | ||
341 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) | |
342 | { | |
343 | writel(val, tp->aperegs + off); | |
344 | } | |
345 | ||
346 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
347 | { | |
348 | return (readl(tp->aperegs + off)); | |
349 | } | |
350 | ||
351 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) | |
352 | { | |
353 | unsigned long flags; | |
354 | ||
355 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
356 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
357 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
358 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
359 | } | |
360 | ||
361 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
362 | { | |
363 | writel(val, tp->regs + off); | |
364 | readl(tp->regs + off); | |
365 | } | |
366 | ||
367 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) | |
368 | { | |
369 | unsigned long flags; | |
370 | u32 val; | |
371 | ||
372 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
373 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
374 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
375 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
376 | return val; | |
377 | } | |
378 | ||
379 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
380 | { | |
381 | unsigned long flags; | |
382 | ||
383 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
384 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
385 | TG3_64BIT_REG_LOW, val); | |
386 | return; | |
387 | } | |
388 | if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) { | |
389 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + | |
390 | TG3_64BIT_REG_LOW, val); | |
391 | return; | |
392 | } | |
393 | ||
394 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
395 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
396 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
397 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
398 | ||
399 | /* In indirect mode when disabling interrupts, we also need | |
400 | * to clear the interrupt bit in the GRC local ctrl register. | |
401 | */ | |
402 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
403 | (val == 0x1)) { | |
404 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
405 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
406 | } | |
407 | } | |
408 | ||
409 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
410 | { | |
411 | unsigned long flags; | |
412 | u32 val; | |
413 | ||
414 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
415 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
416 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
417 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
418 | return val; | |
419 | } | |
420 | ||
421 | /* usec_wait specifies the wait time in usec when writing to certain registers | |
422 | * where it is unsafe to read back the register without some delay. | |
423 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
424 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
425 | */ | |
426 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
427 | { | |
428 | if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) || | |
429 | (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
430 | /* Non-posted methods */ | |
431 | tp->write32(tp, off, val); | |
432 | else { | |
433 | /* Posted method */ | |
434 | tg3_write32(tp, off, val); | |
435 | if (usec_wait) | |
436 | udelay(usec_wait); | |
437 | tp->read32(tp, off); | |
438 | } | |
439 | /* Wait again after the read for the posted method to guarantee that | |
440 | * the wait time is met. | |
441 | */ | |
442 | if (usec_wait) | |
443 | udelay(usec_wait); | |
444 | } | |
445 | ||
446 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) | |
447 | { | |
448 | tp->write32_mbox(tp, off, val); | |
449 | if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && | |
450 | !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
451 | tp->read32_mbox(tp, off); | |
452 | } | |
453 | ||
454 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) | |
455 | { | |
456 | void __iomem *mbox = tp->regs + off; | |
457 | writel(val, mbox); | |
458 | if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) | |
459 | writel(val, mbox); | |
460 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
461 | readl(mbox); | |
462 | } | |
463 | ||
464 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) | |
465 | { | |
466 | return (readl(tp->regs + off + GRCMBOX_BASE)); | |
467 | } | |
468 | ||
469 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
470 | { | |
471 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
472 | } | |
473 | ||
474 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) | |
475 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) | |
476 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) | |
477 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
478 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
479 | ||
480 | #define tw32(reg,val) tp->write32(tp, reg, val) | |
481 | #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0) | |
482 | #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us)) | |
483 | #define tr32(reg) tp->read32(tp, reg) | |
484 | ||
485 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
486 | { | |
487 | unsigned long flags; | |
488 | ||
489 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && | |
490 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | |
491 | return; | |
492 | ||
493 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
494 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { | |
495 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
496 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
497 | ||
498 | /* Always leave this as zero. */ | |
499 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
500 | } else { | |
501 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
502 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
503 | ||
504 | /* Always leave this as zero. */ | |
505 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
506 | } | |
507 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
508 | } | |
509 | ||
510 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) | |
511 | { | |
512 | unsigned long flags; | |
513 | ||
514 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && | |
515 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | |
516 | *val = 0; | |
517 | return; | |
518 | } | |
519 | ||
520 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
521 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { | |
522 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
523 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
524 | ||
525 | /* Always leave this as zero. */ | |
526 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
527 | } else { | |
528 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
529 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
530 | ||
531 | /* Always leave this as zero. */ | |
532 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
533 | } | |
534 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
535 | } | |
536 | ||
537 | static void tg3_ape_lock_init(struct tg3 *tp) | |
538 | { | |
539 | int i; | |
540 | ||
541 | /* Make sure the driver hasn't any stale locks. */ | |
542 | for (i = 0; i < 8; i++) | |
543 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i, | |
544 | APE_LOCK_GRANT_DRIVER); | |
545 | } | |
546 | ||
547 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
548 | { | |
549 | int i, off; | |
550 | int ret = 0; | |
551 | u32 status; | |
552 | ||
553 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
554 | return 0; | |
555 | ||
556 | switch (locknum) { | |
557 | case TG3_APE_LOCK_GRC: | |
558 | case TG3_APE_LOCK_MEM: | |
559 | break; | |
560 | default: | |
561 | return -EINVAL; | |
562 | } | |
563 | ||
564 | off = 4 * locknum; | |
565 | ||
566 | tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER); | |
567 | ||
568 | /* Wait for up to 1 millisecond to acquire lock. */ | |
569 | for (i = 0; i < 100; i++) { | |
570 | status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off); | |
571 | if (status == APE_LOCK_GRANT_DRIVER) | |
572 | break; | |
573 | udelay(10); | |
574 | } | |
575 | ||
576 | if (status != APE_LOCK_GRANT_DRIVER) { | |
577 | /* Revoke the lock request. */ | |
578 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, | |
579 | APE_LOCK_GRANT_DRIVER); | |
580 | ||
581 | ret = -EBUSY; | |
582 | } | |
583 | ||
584 | return ret; | |
585 | } | |
586 | ||
587 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
588 | { | |
589 | int off; | |
590 | ||
591 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
592 | return; | |
593 | ||
594 | switch (locknum) { | |
595 | case TG3_APE_LOCK_GRC: | |
596 | case TG3_APE_LOCK_MEM: | |
597 | break; | |
598 | default: | |
599 | return; | |
600 | } | |
601 | ||
602 | off = 4 * locknum; | |
603 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER); | |
604 | } | |
605 | ||
606 | static void tg3_disable_ints(struct tg3 *tp) | |
607 | { | |
608 | tw32(TG3PCI_MISC_HOST_CTRL, | |
609 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
610 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
611 | } | |
612 | ||
613 | static inline void tg3_cond_int(struct tg3 *tp) | |
614 | { | |
615 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
616 | (tp->hw_status->status & SD_STATUS_UPDATED)) | |
617 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
618 | else | |
619 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
620 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); | |
621 | } | |
622 | ||
623 | static void tg3_enable_ints(struct tg3 *tp) | |
624 | { | |
625 | tp->irq_sync = 0; | |
626 | wmb(); | |
627 | ||
628 | tw32(TG3PCI_MISC_HOST_CTRL, | |
629 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
630 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
631 | (tp->last_tag << 24)); | |
632 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
633 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
634 | (tp->last_tag << 24)); | |
635 | tg3_cond_int(tp); | |
636 | } | |
637 | ||
638 | static inline unsigned int tg3_has_work(struct tg3 *tp) | |
639 | { | |
640 | struct tg3_hw_status *sblk = tp->hw_status; | |
641 | unsigned int work_exists = 0; | |
642 | ||
643 | /* check for phy events */ | |
644 | if (!(tp->tg3_flags & | |
645 | (TG3_FLAG_USE_LINKCHG_REG | | |
646 | TG3_FLAG_POLL_SERDES))) { | |
647 | if (sblk->status & SD_STATUS_LINK_CHG) | |
648 | work_exists = 1; | |
649 | } | |
650 | /* check for RX/TX work to do */ | |
651 | if (sblk->idx[0].tx_consumer != tp->tx_cons || | |
652 | sblk->idx[0].rx_producer != tp->rx_rcb_ptr) | |
653 | work_exists = 1; | |
654 | ||
655 | return work_exists; | |
656 | } | |
657 | ||
658 | /* tg3_restart_ints | |
659 | * similar to tg3_enable_ints, but it accurately determines whether there | |
660 | * is new work pending and can return without flushing the PIO write | |
661 | * which reenables interrupts | |
662 | */ | |
663 | static void tg3_restart_ints(struct tg3 *tp) | |
664 | { | |
665 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
666 | tp->last_tag << 24); | |
667 | mmiowb(); | |
668 | ||
669 | /* When doing tagged status, this work check is unnecessary. | |
670 | * The last_tag we write above tells the chip which piece of | |
671 | * work we've completed. | |
672 | */ | |
673 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
674 | tg3_has_work(tp)) | |
675 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
676 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); | |
677 | } | |
678 | ||
679 | static inline void tg3_netif_stop(struct tg3 *tp) | |
680 | { | |
681 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
682 | napi_disable(&tp->napi); | |
683 | netif_tx_disable(tp->dev); | |
684 | } | |
685 | ||
686 | static inline void tg3_netif_start(struct tg3 *tp) | |
687 | { | |
688 | netif_wake_queue(tp->dev); | |
689 | /* NOTE: unconditional netif_wake_queue is only appropriate | |
690 | * so long as all callers are assured to have free tx slots | |
691 | * (such as after tg3_init_hw) | |
692 | */ | |
693 | napi_enable(&tp->napi); | |
694 | tp->hw_status->status |= SD_STATUS_UPDATED; | |
695 | tg3_enable_ints(tp); | |
696 | } | |
697 | ||
698 | static void tg3_switch_clocks(struct tg3 *tp) | |
699 | { | |
700 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); | |
701 | u32 orig_clock_ctrl; | |
702 | ||
703 | if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || | |
704 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
705 | return; | |
706 | ||
707 | orig_clock_ctrl = clock_ctrl; | |
708 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
709 | CLOCK_CTRL_CLKRUN_OENABLE | | |
710 | 0x1f); | |
711 | tp->pci_clock_ctrl = clock_ctrl; | |
712 | ||
713 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
714 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { | |
715 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
716 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
717 | } | |
718 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
719 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
720 | clock_ctrl | | |
721 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
722 | 40); | |
723 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
724 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
725 | 40); | |
726 | } | |
727 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); | |
728 | } | |
729 | ||
730 | #define PHY_BUSY_LOOPS 5000 | |
731 | ||
732 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
733 | { | |
734 | u32 frame_val; | |
735 | unsigned int loops; | |
736 | int ret; | |
737 | ||
738 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
739 | tw32_f(MAC_MI_MODE, | |
740 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
741 | udelay(80); | |
742 | } | |
743 | ||
744 | *val = 0x0; | |
745 | ||
746 | frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) & | |
747 | MI_COM_PHY_ADDR_MASK); | |
748 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
749 | MI_COM_REG_ADDR_MASK); | |
750 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
751 | ||
752 | tw32_f(MAC_MI_COM, frame_val); | |
753 | ||
754 | loops = PHY_BUSY_LOOPS; | |
755 | while (loops != 0) { | |
756 | udelay(10); | |
757 | frame_val = tr32(MAC_MI_COM); | |
758 | ||
759 | if ((frame_val & MI_COM_BUSY) == 0) { | |
760 | udelay(5); | |
761 | frame_val = tr32(MAC_MI_COM); | |
762 | break; | |
763 | } | |
764 | loops -= 1; | |
765 | } | |
766 | ||
767 | ret = -EBUSY; | |
768 | if (loops != 0) { | |
769 | *val = frame_val & MI_COM_DATA_MASK; | |
770 | ret = 0; | |
771 | } | |
772 | ||
773 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
774 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
775 | udelay(80); | |
776 | } | |
777 | ||
778 | return ret; | |
779 | } | |
780 | ||
781 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
782 | { | |
783 | u32 frame_val; | |
784 | unsigned int loops; | |
785 | int ret; | |
786 | ||
787 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && | |
788 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) | |
789 | return 0; | |
790 | ||
791 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
792 | tw32_f(MAC_MI_MODE, | |
793 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
794 | udelay(80); | |
795 | } | |
796 | ||
797 | frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) & | |
798 | MI_COM_PHY_ADDR_MASK); | |
799 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
800 | MI_COM_REG_ADDR_MASK); | |
801 | frame_val |= (val & MI_COM_DATA_MASK); | |
802 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
803 | ||
804 | tw32_f(MAC_MI_COM, frame_val); | |
805 | ||
806 | loops = PHY_BUSY_LOOPS; | |
807 | while (loops != 0) { | |
808 | udelay(10); | |
809 | frame_val = tr32(MAC_MI_COM); | |
810 | if ((frame_val & MI_COM_BUSY) == 0) { | |
811 | udelay(5); | |
812 | frame_val = tr32(MAC_MI_COM); | |
813 | break; | |
814 | } | |
815 | loops -= 1; | |
816 | } | |
817 | ||
818 | ret = -EBUSY; | |
819 | if (loops != 0) | |
820 | ret = 0; | |
821 | ||
822 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
823 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
824 | udelay(80); | |
825 | } | |
826 | ||
827 | return ret; | |
828 | } | |
829 | ||
830 | static int tg3_bmcr_reset(struct tg3 *tp) | |
831 | { | |
832 | u32 phy_control; | |
833 | int limit, err; | |
834 | ||
835 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
836 | * clears or we time out. | |
837 | */ | |
838 | phy_control = BMCR_RESET; | |
839 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
840 | if (err != 0) | |
841 | return -EBUSY; | |
842 | ||
843 | limit = 5000; | |
844 | while (limit--) { | |
845 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
846 | if (err != 0) | |
847 | return -EBUSY; | |
848 | ||
849 | if ((phy_control & BMCR_RESET) == 0) { | |
850 | udelay(40); | |
851 | break; | |
852 | } | |
853 | udelay(10); | |
854 | } | |
855 | if (limit < 0) | |
856 | return -EBUSY; | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
861 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) | |
862 | { | |
863 | struct tg3 *tp = bp->priv; | |
864 | u32 val; | |
865 | ||
866 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED) | |
867 | return -EAGAIN; | |
868 | ||
869 | if (tg3_readphy(tp, reg, &val)) | |
870 | return -EIO; | |
871 | ||
872 | return val; | |
873 | } | |
874 | ||
875 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
876 | { | |
877 | struct tg3 *tp = bp->priv; | |
878 | ||
879 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED) | |
880 | return -EAGAIN; | |
881 | ||
882 | if (tg3_writephy(tp, reg, val)) | |
883 | return -EIO; | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
888 | static int tg3_mdio_reset(struct mii_bus *bp) | |
889 | { | |
890 | return 0; | |
891 | } | |
892 | ||
893 | static void tg3_mdio_config_5785(struct tg3 *tp) | |
894 | { | |
895 | u32 val; | |
896 | struct phy_device *phydev; | |
897 | ||
898 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; | |
899 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
900 | case TG3_PHY_ID_BCM50610: | |
901 | val = MAC_PHYCFG2_50610_LED_MODES; | |
902 | break; | |
903 | case TG3_PHY_ID_BCMAC131: | |
904 | val = MAC_PHYCFG2_AC131_LED_MODES; | |
905 | break; | |
906 | case TG3_PHY_ID_RTL8211C: | |
907 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; | |
908 | break; | |
909 | case TG3_PHY_ID_RTL8201E: | |
910 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; | |
911 | break; | |
912 | default: | |
913 | return; | |
914 | } | |
915 | ||
916 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
917 | tw32(MAC_PHYCFG2, val); | |
918 | ||
919 | val = tr32(MAC_PHYCFG1); | |
920 | val &= ~MAC_PHYCFG1_RGMII_INT; | |
921 | tw32(MAC_PHYCFG1, val); | |
922 | ||
923 | return; | |
924 | } | |
925 | ||
926 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) | |
927 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | | |
928 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
929 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
930 | MAC_PHYCFG2_ACT_MASK_MASK | | |
931 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
932 | MAC_PHYCFG2_INBAND_ENABLE; | |
933 | ||
934 | tw32(MAC_PHYCFG2, val); | |
935 | ||
936 | val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC | | |
937 | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
938 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) { | |
939 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
940 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; | |
941 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
942 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; | |
943 | } | |
944 | tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV); | |
945 | ||
946 | val = tr32(MAC_EXT_RGMII_MODE); | |
947 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
948 | MAC_RGMII_MODE_RX_QUALITY | | |
949 | MAC_RGMII_MODE_RX_ACTIVITY | | |
950 | MAC_RGMII_MODE_RX_ENG_DET | | |
951 | MAC_RGMII_MODE_TX_ENABLE | | |
952 | MAC_RGMII_MODE_TX_LOWPWR | | |
953 | MAC_RGMII_MODE_TX_RESET); | |
954 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) { | |
955 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
956 | val |= MAC_RGMII_MODE_RX_INT_B | | |
957 | MAC_RGMII_MODE_RX_QUALITY | | |
958 | MAC_RGMII_MODE_RX_ACTIVITY | | |
959 | MAC_RGMII_MODE_RX_ENG_DET; | |
960 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
961 | val |= MAC_RGMII_MODE_TX_ENABLE | | |
962 | MAC_RGMII_MODE_TX_LOWPWR | | |
963 | MAC_RGMII_MODE_TX_RESET; | |
964 | } | |
965 | tw32(MAC_EXT_RGMII_MODE, val); | |
966 | } | |
967 | ||
968 | static void tg3_mdio_start(struct tg3 *tp) | |
969 | { | |
970 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
971 | mutex_lock(&tp->mdio_bus->mdio_lock); | |
972 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED; | |
973 | mutex_unlock(&tp->mdio_bus->mdio_lock); | |
974 | } | |
975 | ||
976 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; | |
977 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
978 | udelay(80); | |
979 | ||
980 | if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && | |
981 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
982 | tg3_mdio_config_5785(tp); | |
983 | } | |
984 | ||
985 | static void tg3_mdio_stop(struct tg3 *tp) | |
986 | { | |
987 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
988 | mutex_lock(&tp->mdio_bus->mdio_lock); | |
989 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED; | |
990 | mutex_unlock(&tp->mdio_bus->mdio_lock); | |
991 | } | |
992 | } | |
993 | ||
994 | static int tg3_mdio_init(struct tg3 *tp) | |
995 | { | |
996 | int i; | |
997 | u32 reg; | |
998 | struct phy_device *phydev; | |
999 | ||
1000 | tg3_mdio_start(tp); | |
1001 | ||
1002 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) || | |
1003 | (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)) | |
1004 | return 0; | |
1005 | ||
1006 | tp->mdio_bus = mdiobus_alloc(); | |
1007 | if (tp->mdio_bus == NULL) | |
1008 | return -ENOMEM; | |
1009 | ||
1010 | tp->mdio_bus->name = "tg3 mdio bus"; | |
1011 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
1012 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); | |
1013 | tp->mdio_bus->priv = tp; | |
1014 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1015 | tp->mdio_bus->read = &tg3_mdio_read; | |
1016 | tp->mdio_bus->write = &tg3_mdio_write; | |
1017 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
1018 | tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR); | |
1019 | tp->mdio_bus->irq = &tp->mdio_irq[0]; | |
1020 | ||
1021 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
1022 | tp->mdio_bus->irq[i] = PHY_POLL; | |
1023 | ||
1024 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1025 | * Unfortunately, it does not ensure the PHY is powered up before | |
1026 | * accessing the PHY ID registers. A chip reset is the | |
1027 | * quickest way to bring the device back to an operational state.. | |
1028 | */ | |
1029 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1030 | tg3_bmcr_reset(tp); | |
1031 | ||
1032 | i = mdiobus_register(tp->mdio_bus); | |
1033 | if (i) { | |
1034 | printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n", | |
1035 | tp->dev->name, i); | |
1036 | mdiobus_free(tp->mdio_bus); | |
1037 | return i; | |
1038 | } | |
1039 | ||
1040 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; | |
1041 | ||
1042 | if (!phydev || !phydev->drv) { | |
1043 | printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name); | |
1044 | mdiobus_unregister(tp->mdio_bus); | |
1045 | mdiobus_free(tp->mdio_bus); | |
1046 | return -ENODEV; | |
1047 | } | |
1048 | ||
1049 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
1050 | case TG3_PHY_ID_BCM57780: | |
1051 | phydev->interface = PHY_INTERFACE_MODE_GMII; | |
1052 | break; | |
1053 | case TG3_PHY_ID_BCM50610: | |
1054 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) | |
1055 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; | |
1056 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1057 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; | |
1058 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1059 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; | |
1060 | /* fallthru */ | |
1061 | case TG3_PHY_ID_RTL8211C: | |
1062 | phydev->interface = PHY_INTERFACE_MODE_RGMII; | |
1063 | break; | |
1064 | case TG3_PHY_ID_RTL8201E: | |
1065 | case TG3_PHY_ID_BCMAC131: | |
1066 | phydev->interface = PHY_INTERFACE_MODE_MII; | |
1067 | break; | |
1068 | } | |
1069 | ||
1070 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED; | |
1071 | ||
1072 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1073 | tg3_mdio_config_5785(tp); | |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
1078 | static void tg3_mdio_fini(struct tg3 *tp) | |
1079 | { | |
1080 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
1081 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED; | |
1082 | mdiobus_unregister(tp->mdio_bus); | |
1083 | mdiobus_free(tp->mdio_bus); | |
1084 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED; | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | /* tp->lock is held. */ | |
1089 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1090 | { | |
1091 | u32 val; | |
1092 | ||
1093 | val = tr32(GRC_RX_CPU_EVENT); | |
1094 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1095 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1096 | ||
1097 | tp->last_event_jiffies = jiffies; | |
1098 | } | |
1099 | ||
1100 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1101 | ||
1102 | /* tp->lock is held. */ | |
1103 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1104 | { | |
1105 | int i; | |
1106 | unsigned int delay_cnt; | |
1107 | long time_remain; | |
1108 | ||
1109 | /* If enough time has passed, no wait is necessary. */ | |
1110 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1111 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1112 | (long)jiffies; | |
1113 | if (time_remain < 0) | |
1114 | return; | |
1115 | ||
1116 | /* Check if we can shorten the wait time. */ | |
1117 | delay_cnt = jiffies_to_usecs(time_remain); | |
1118 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1119 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1120 | delay_cnt = (delay_cnt >> 3) + 1; | |
1121 | ||
1122 | for (i = 0; i < delay_cnt; i++) { | |
1123 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) | |
1124 | break; | |
1125 | udelay(8); | |
1126 | } | |
1127 | } | |
1128 | ||
1129 | /* tp->lock is held. */ | |
1130 | static void tg3_ump_link_report(struct tg3 *tp) | |
1131 | { | |
1132 | u32 reg; | |
1133 | u32 val; | |
1134 | ||
1135 | if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
1136 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
1137 | return; | |
1138 | ||
1139 | tg3_wait_for_event_ack(tp); | |
1140 | ||
1141 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1142 | ||
1143 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1144 | ||
1145 | val = 0; | |
1146 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1147 | val = reg << 16; | |
1148 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1149 | val |= (reg & 0xffff); | |
1150 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1151 | ||
1152 | val = 0; | |
1153 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1154 | val = reg << 16; | |
1155 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1156 | val |= (reg & 0xffff); | |
1157 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1158 | ||
1159 | val = 0; | |
1160 | if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) { | |
1161 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) | |
1162 | val = reg << 16; | |
1163 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1164 | val |= (reg & 0xffff); | |
1165 | } | |
1166 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1167 | ||
1168 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1169 | val = reg << 16; | |
1170 | else | |
1171 | val = 0; | |
1172 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1173 | ||
1174 | tg3_generate_fw_event(tp); | |
1175 | } | |
1176 | ||
1177 | static void tg3_link_report(struct tg3 *tp) | |
1178 | { | |
1179 | if (!netif_carrier_ok(tp->dev)) { | |
1180 | if (netif_msg_link(tp)) | |
1181 | printk(KERN_INFO PFX "%s: Link is down.\n", | |
1182 | tp->dev->name); | |
1183 | tg3_ump_link_report(tp); | |
1184 | } else if (netif_msg_link(tp)) { | |
1185 | printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n", | |
1186 | tp->dev->name, | |
1187 | (tp->link_config.active_speed == SPEED_1000 ? | |
1188 | 1000 : | |
1189 | (tp->link_config.active_speed == SPEED_100 ? | |
1190 | 100 : 10)), | |
1191 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1192 | "full" : "half")); | |
1193 | ||
1194 | printk(KERN_INFO PFX | |
1195 | "%s: Flow control is %s for TX and %s for RX.\n", | |
1196 | tp->dev->name, | |
1197 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1198 | "on" : "off", | |
1199 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1200 | "on" : "off"); | |
1201 | tg3_ump_link_report(tp); | |
1202 | } | |
1203 | } | |
1204 | ||
1205 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1206 | { | |
1207 | u16 miireg; | |
1208 | ||
1209 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) | |
1210 | miireg = ADVERTISE_PAUSE_CAP; | |
1211 | else if (flow_ctrl & FLOW_CTRL_TX) | |
1212 | miireg = ADVERTISE_PAUSE_ASYM; | |
1213 | else if (flow_ctrl & FLOW_CTRL_RX) | |
1214 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
1215 | else | |
1216 | miireg = 0; | |
1217 | ||
1218 | return miireg; | |
1219 | } | |
1220 | ||
1221 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1222 | { | |
1223 | u16 miireg; | |
1224 | ||
1225 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) | |
1226 | miireg = ADVERTISE_1000XPAUSE; | |
1227 | else if (flow_ctrl & FLOW_CTRL_TX) | |
1228 | miireg = ADVERTISE_1000XPSE_ASYM; | |
1229 | else if (flow_ctrl & FLOW_CTRL_RX) | |
1230 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; | |
1231 | else | |
1232 | miireg = 0; | |
1233 | ||
1234 | return miireg; | |
1235 | } | |
1236 | ||
1237 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) | |
1238 | { | |
1239 | u8 cap = 0; | |
1240 | ||
1241 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1242 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1243 | if (rmtadv & LPA_1000XPAUSE) | |
1244 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1245 | else if (rmtadv & LPA_1000XPAUSE_ASYM) | |
1246 | cap = FLOW_CTRL_RX; | |
1247 | } else { | |
1248 | if (rmtadv & LPA_1000XPAUSE) | |
1249 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1250 | } | |
1251 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1252 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
1253 | cap = FLOW_CTRL_TX; | |
1254 | } | |
1255 | ||
1256 | return cap; | |
1257 | } | |
1258 | ||
1259 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) | |
1260 | { | |
1261 | u8 autoneg; | |
1262 | u8 flowctrl = 0; | |
1263 | u32 old_rx_mode = tp->rx_mode; | |
1264 | u32 old_tx_mode = tp->tx_mode; | |
1265 | ||
1266 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) | |
1267 | autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg; | |
1268 | else | |
1269 | autoneg = tp->link_config.autoneg; | |
1270 | ||
1271 | if (autoneg == AUTONEG_ENABLE && | |
1272 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { | |
1273 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) | |
1274 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); | |
1275 | else | |
1276 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); | |
1277 | } else | |
1278 | flowctrl = tp->link_config.flowctrl; | |
1279 | ||
1280 | tp->link_config.active_flowctrl = flowctrl; | |
1281 | ||
1282 | if (flowctrl & FLOW_CTRL_RX) | |
1283 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; | |
1284 | else | |
1285 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1286 | ||
1287 | if (old_rx_mode != tp->rx_mode) | |
1288 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
1289 | ||
1290 | if (flowctrl & FLOW_CTRL_TX) | |
1291 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; | |
1292 | else | |
1293 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1294 | ||
1295 | if (old_tx_mode != tp->tx_mode) | |
1296 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
1297 | } | |
1298 | ||
1299 | static void tg3_adjust_link(struct net_device *dev) | |
1300 | { | |
1301 | u8 oldflowctrl, linkmesg = 0; | |
1302 | u32 mac_mode, lcl_adv, rmt_adv; | |
1303 | struct tg3 *tp = netdev_priv(dev); | |
1304 | struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR]; | |
1305 | ||
1306 | spin_lock(&tp->lock); | |
1307 | ||
1308 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1309 | MAC_MODE_HALF_DUPLEX); | |
1310 | ||
1311 | oldflowctrl = tp->link_config.active_flowctrl; | |
1312 | ||
1313 | if (phydev->link) { | |
1314 | lcl_adv = 0; | |
1315 | rmt_adv = 0; | |
1316 | ||
1317 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1318 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
1319 | else | |
1320 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1321 | ||
1322 | if (phydev->duplex == DUPLEX_HALF) | |
1323 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1324 | else { | |
1325 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1326 | tp->link_config.flowctrl); | |
1327 | ||
1328 | if (phydev->pause) | |
1329 | rmt_adv = LPA_PAUSE_CAP; | |
1330 | if (phydev->asym_pause) | |
1331 | rmt_adv |= LPA_PAUSE_ASYM; | |
1332 | } | |
1333 | ||
1334 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1335 | } else | |
1336 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1337 | ||
1338 | if (mac_mode != tp->mac_mode) { | |
1339 | tp->mac_mode = mac_mode; | |
1340 | tw32_f(MAC_MODE, tp->mac_mode); | |
1341 | udelay(40); | |
1342 | } | |
1343 | ||
1344 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
1345 | if (phydev->speed == SPEED_10) | |
1346 | tw32(MAC_MI_STAT, | |
1347 | MAC_MI_STAT_10MBPS_MODE | | |
1348 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1349 | else | |
1350 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1351 | } | |
1352 | ||
1353 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) | |
1354 | tw32(MAC_TX_LENGTHS, | |
1355 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1356 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1357 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1358 | else | |
1359 | tw32(MAC_TX_LENGTHS, | |
1360 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1361 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1362 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1363 | ||
1364 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1365 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1366 | phydev->speed != tp->link_config.active_speed || | |
1367 | phydev->duplex != tp->link_config.active_duplex || | |
1368 | oldflowctrl != tp->link_config.active_flowctrl) | |
1369 | linkmesg = 1; | |
1370 | ||
1371 | tp->link_config.active_speed = phydev->speed; | |
1372 | tp->link_config.active_duplex = phydev->duplex; | |
1373 | ||
1374 | spin_unlock(&tp->lock); | |
1375 | ||
1376 | if (linkmesg) | |
1377 | tg3_link_report(tp); | |
1378 | } | |
1379 | ||
1380 | static int tg3_phy_init(struct tg3 *tp) | |
1381 | { | |
1382 | struct phy_device *phydev; | |
1383 | ||
1384 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) | |
1385 | return 0; | |
1386 | ||
1387 | /* Bring the PHY back to a known state. */ | |
1388 | tg3_bmcr_reset(tp); | |
1389 | ||
1390 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; | |
1391 | ||
1392 | /* Attach the MAC to the PHY. */ | |
1393 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, | |
1394 | phydev->dev_flags, phydev->interface); | |
1395 | if (IS_ERR(phydev)) { | |
1396 | printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name); | |
1397 | return PTR_ERR(phydev); | |
1398 | } | |
1399 | ||
1400 | /* Mask with MAC supported features. */ | |
1401 | switch (phydev->interface) { | |
1402 | case PHY_INTERFACE_MODE_GMII: | |
1403 | case PHY_INTERFACE_MODE_RGMII: | |
1404 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
1405 | phydev->supported &= (PHY_GBIT_FEATURES | | |
1406 | SUPPORTED_Pause | | |
1407 | SUPPORTED_Asym_Pause); | |
1408 | break; | |
1409 | } | |
1410 | /* fallthru */ | |
1411 | case PHY_INTERFACE_MODE_MII: | |
1412 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1413 | SUPPORTED_Pause | | |
1414 | SUPPORTED_Asym_Pause); | |
1415 | break; | |
1416 | default: | |
1417 | phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]); | |
1418 | return -EINVAL; | |
1419 | } | |
1420 | ||
1421 | tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED; | |
1422 | ||
1423 | phydev->advertising = phydev->supported; | |
1424 | ||
1425 | return 0; | |
1426 | } | |
1427 | ||
1428 | static void tg3_phy_start(struct tg3 *tp) | |
1429 | { | |
1430 | struct phy_device *phydev; | |
1431 | ||
1432 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
1433 | return; | |
1434 | ||
1435 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; | |
1436 | ||
1437 | if (tp->link_config.phy_is_low_power) { | |
1438 | tp->link_config.phy_is_low_power = 0; | |
1439 | phydev->speed = tp->link_config.orig_speed; | |
1440 | phydev->duplex = tp->link_config.orig_duplex; | |
1441 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1442 | phydev->advertising = tp->link_config.orig_advertising; | |
1443 | } | |
1444 | ||
1445 | phy_start(phydev); | |
1446 | ||
1447 | phy_start_aneg(phydev); | |
1448 | } | |
1449 | ||
1450 | static void tg3_phy_stop(struct tg3 *tp) | |
1451 | { | |
1452 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
1453 | return; | |
1454 | ||
1455 | phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]); | |
1456 | } | |
1457 | ||
1458 | static void tg3_phy_fini(struct tg3 *tp) | |
1459 | { | |
1460 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
1461 | phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]); | |
1462 | tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED; | |
1463 | } | |
1464 | } | |
1465 | ||
1466 | static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
1467 | { | |
1468 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1469 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1470 | } | |
1471 | ||
1472 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) | |
1473 | { | |
1474 | u32 reg; | |
1475 | ||
1476 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
1477 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
1478 | return; | |
1479 | ||
1480 | reg = MII_TG3_MISC_SHDW_WREN | | |
1481 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1482 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1483 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1484 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1485 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1486 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1487 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1488 | ||
1489 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1490 | ||
1491 | ||
1492 | reg = MII_TG3_MISC_SHDW_WREN | | |
1493 | MII_TG3_MISC_SHDW_APD_SEL | | |
1494 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1495 | if (enable) | |
1496 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1497 | ||
1498 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1499 | } | |
1500 | ||
1501 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) | |
1502 | { | |
1503 | u32 phy; | |
1504 | ||
1505 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
1506 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
1507 | return; | |
1508 | ||
1509 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
1510 | u32 ephy; | |
1511 | ||
1512 | if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) { | |
1513 | tg3_writephy(tp, MII_TG3_EPHY_TEST, | |
1514 | ephy | MII_TG3_EPHY_SHADOW_EN); | |
1515 | if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) { | |
1516 | if (enable) | |
1517 | phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX; | |
1518 | else | |
1519 | phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX; | |
1520 | tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy); | |
1521 | } | |
1522 | tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy); | |
1523 | } | |
1524 | } else { | |
1525 | phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | | |
1526 | MII_TG3_AUXCTL_SHDWSEL_MISC; | |
1527 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) && | |
1528 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) { | |
1529 | if (enable) | |
1530 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1531 | else | |
1532 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1533 | phy |= MII_TG3_AUXCTL_MISC_WREN; | |
1534 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1535 | } | |
1536 | } | |
1537 | } | |
1538 | ||
1539 | static void tg3_phy_set_wirespeed(struct tg3 *tp) | |
1540 | { | |
1541 | u32 val; | |
1542 | ||
1543 | if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) | |
1544 | return; | |
1545 | ||
1546 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) && | |
1547 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) | |
1548 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1549 | (val | (1 << 15) | (1 << 4))); | |
1550 | } | |
1551 | ||
1552 | static void tg3_phy_apply_otp(struct tg3 *tp) | |
1553 | { | |
1554 | u32 otp, phy; | |
1555 | ||
1556 | if (!tp->phy_otp) | |
1557 | return; | |
1558 | ||
1559 | otp = tp->phy_otp; | |
1560 | ||
1561 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
1562 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1563 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
1564 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1565 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1566 | ||
1567 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1568 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1569 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1570 | ||
1571 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1572 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1573 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1574 | ||
1575 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1576 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1577 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1578 | ||
1579 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1580 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1581 | ||
1582 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1583 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1584 | ||
1585 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1586 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1587 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1588 | ||
1589 | /* Turn off SM_DSP clock. */ | |
1590 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1591 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1592 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1593 | } | |
1594 | ||
1595 | static int tg3_wait_macro_done(struct tg3 *tp) | |
1596 | { | |
1597 | int limit = 100; | |
1598 | ||
1599 | while (limit--) { | |
1600 | u32 tmp32; | |
1601 | ||
1602 | if (!tg3_readphy(tp, 0x16, &tmp32)) { | |
1603 | if ((tmp32 & 0x1000) == 0) | |
1604 | break; | |
1605 | } | |
1606 | } | |
1607 | if (limit < 0) | |
1608 | return -EBUSY; | |
1609 | ||
1610 | return 0; | |
1611 | } | |
1612 | ||
1613 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1614 | { | |
1615 | static const u32 test_pat[4][6] = { | |
1616 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1617 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1618 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1619 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1620 | }; | |
1621 | int chan; | |
1622 | ||
1623 | for (chan = 0; chan < 4; chan++) { | |
1624 | int i; | |
1625 | ||
1626 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1627 | (chan * 0x2000) | 0x0200); | |
1628 | tg3_writephy(tp, 0x16, 0x0002); | |
1629 | ||
1630 | for (i = 0; i < 6; i++) | |
1631 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1632 | test_pat[chan][i]); | |
1633 | ||
1634 | tg3_writephy(tp, 0x16, 0x0202); | |
1635 | if (tg3_wait_macro_done(tp)) { | |
1636 | *resetp = 1; | |
1637 | return -EBUSY; | |
1638 | } | |
1639 | ||
1640 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1641 | (chan * 0x2000) | 0x0200); | |
1642 | tg3_writephy(tp, 0x16, 0x0082); | |
1643 | if (tg3_wait_macro_done(tp)) { | |
1644 | *resetp = 1; | |
1645 | return -EBUSY; | |
1646 | } | |
1647 | ||
1648 | tg3_writephy(tp, 0x16, 0x0802); | |
1649 | if (tg3_wait_macro_done(tp)) { | |
1650 | *resetp = 1; | |
1651 | return -EBUSY; | |
1652 | } | |
1653 | ||
1654 | for (i = 0; i < 6; i += 2) { | |
1655 | u32 low, high; | |
1656 | ||
1657 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1658 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1659 | tg3_wait_macro_done(tp)) { | |
1660 | *resetp = 1; | |
1661 | return -EBUSY; | |
1662 | } | |
1663 | low &= 0x7fff; | |
1664 | high &= 0x000f; | |
1665 | if (low != test_pat[chan][i] || | |
1666 | high != test_pat[chan][i+1]) { | |
1667 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1668 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1669 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1670 | ||
1671 | return -EBUSY; | |
1672 | } | |
1673 | } | |
1674 | } | |
1675 | ||
1676 | return 0; | |
1677 | } | |
1678 | ||
1679 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1680 | { | |
1681 | int chan; | |
1682 | ||
1683 | for (chan = 0; chan < 4; chan++) { | |
1684 | int i; | |
1685 | ||
1686 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1687 | (chan * 0x2000) | 0x0200); | |
1688 | tg3_writephy(tp, 0x16, 0x0002); | |
1689 | for (i = 0; i < 6; i++) | |
1690 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
1691 | tg3_writephy(tp, 0x16, 0x0202); | |
1692 | if (tg3_wait_macro_done(tp)) | |
1693 | return -EBUSY; | |
1694 | } | |
1695 | ||
1696 | return 0; | |
1697 | } | |
1698 | ||
1699 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1700 | { | |
1701 | u32 reg32, phy9_orig; | |
1702 | int retries, do_phy_reset, err; | |
1703 | ||
1704 | retries = 10; | |
1705 | do_phy_reset = 1; | |
1706 | do { | |
1707 | if (do_phy_reset) { | |
1708 | err = tg3_bmcr_reset(tp); | |
1709 | if (err) | |
1710 | return err; | |
1711 | do_phy_reset = 0; | |
1712 | } | |
1713 | ||
1714 | /* Disable transmitter and interrupt. */ | |
1715 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
1716 | continue; | |
1717 | ||
1718 | reg32 |= 0x3000; | |
1719 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1720 | ||
1721 | /* Set full-duplex, 1000 mbps. */ | |
1722 | tg3_writephy(tp, MII_BMCR, | |
1723 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | |
1724 | ||
1725 | /* Set to master mode. */ | |
1726 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | |
1727 | continue; | |
1728 | ||
1729 | tg3_writephy(tp, MII_TG3_CTRL, | |
1730 | (MII_TG3_CTRL_AS_MASTER | | |
1731 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | |
1732 | ||
1733 | /* Enable SM_DSP_CLOCK and 6dB. */ | |
1734 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1735 | ||
1736 | /* Block the PHY control access. */ | |
1737 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); | |
1738 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800); | |
1739 | ||
1740 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
1741 | if (!err) | |
1742 | break; | |
1743 | } while (--retries); | |
1744 | ||
1745 | err = tg3_phy_reset_chanpat(tp); | |
1746 | if (err) | |
1747 | return err; | |
1748 | ||
1749 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); | |
1750 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000); | |
1751 | ||
1752 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
1753 | tg3_writephy(tp, 0x16, 0x0000); | |
1754 | ||
1755 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
1756 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
1757 | /* Set Extended packet length bit for jumbo frames */ | |
1758 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400); | |
1759 | } | |
1760 | else { | |
1761 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1762 | } | |
1763 | ||
1764 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | |
1765 | ||
1766 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
1767 | reg32 &= ~0x3000; | |
1768 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1769 | } else if (!err) | |
1770 | err = -EBUSY; | |
1771 | ||
1772 | return err; | |
1773 | } | |
1774 | ||
1775 | /* This will reset the tigon3 PHY if there is no valid | |
1776 | * link unless the FORCE argument is non-zero. | |
1777 | */ | |
1778 | static int tg3_phy_reset(struct tg3 *tp) | |
1779 | { | |
1780 | u32 cpmuctrl; | |
1781 | u32 phy_status; | |
1782 | int err; | |
1783 | ||
1784 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
1785 | u32 val; | |
1786 | ||
1787 | val = tr32(GRC_MISC_CFG); | |
1788 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
1789 | udelay(40); | |
1790 | } | |
1791 | err = tg3_readphy(tp, MII_BMSR, &phy_status); | |
1792 | err |= tg3_readphy(tp, MII_BMSR, &phy_status); | |
1793 | if (err != 0) | |
1794 | return -EBUSY; | |
1795 | ||
1796 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { | |
1797 | netif_carrier_off(tp->dev); | |
1798 | tg3_link_report(tp); | |
1799 | } | |
1800 | ||
1801 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
1802 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
1803 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
1804 | err = tg3_phy_reset_5703_4_5(tp); | |
1805 | if (err) | |
1806 | return err; | |
1807 | goto out; | |
1808 | } | |
1809 | ||
1810 | cpmuctrl = 0; | |
1811 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
1812 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
1813 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
1814 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
1815 | tw32(TG3_CPMU_CTRL, | |
1816 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
1817 | } | |
1818 | ||
1819 | err = tg3_bmcr_reset(tp); | |
1820 | if (err) | |
1821 | return err; | |
1822 | ||
1823 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { | |
1824 | u32 phy; | |
1825 | ||
1826 | phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; | |
1827 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy); | |
1828 | ||
1829 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
1830 | } | |
1831 | ||
1832 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || | |
1833 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
1834 | u32 val; | |
1835 | ||
1836 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | |
1837 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
1838 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
1839 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
1840 | udelay(40); | |
1841 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
1842 | } | |
1843 | } | |
1844 | ||
1845 | tg3_phy_apply_otp(tp); | |
1846 | ||
1847 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
1848 | tg3_phy_toggle_apd(tp, true); | |
1849 | else | |
1850 | tg3_phy_toggle_apd(tp, false); | |
1851 | ||
1852 | out: | |
1853 | if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) { | |
1854 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1855 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
1856 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa); | |
1857 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1858 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323); | |
1859 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1860 | } | |
1861 | if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) { | |
1862 | tg3_writephy(tp, 0x1c, 0x8d68); | |
1863 | tg3_writephy(tp, 0x1c, 0x8d68); | |
1864 | } | |
1865 | if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) { | |
1866 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1867 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1868 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b); | |
1869 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
1870 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506); | |
1871 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f); | |
1872 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2); | |
1873 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1874 | } | |
1875 | else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) { | |
1876 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1877 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1878 | if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) { | |
1879 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
1880 | tg3_writephy(tp, MII_TG3_TEST1, | |
1881 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
1882 | } else | |
1883 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
1884 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1885 | } | |
1886 | /* Set Extended packet length bit (bit 14) on all chips that */ | |
1887 | /* support jumbo frames */ | |
1888 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
1889 | /* Cannot do read-modify-write on 5401 */ | |
1890 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
1891 | } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) { | |
1892 | u32 phy_reg; | |
1893 | ||
1894 | /* Set bit 14 with read-modify-write to preserve other bits */ | |
1895 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) && | |
1896 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg)) | |
1897 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000); | |
1898 | } | |
1899 | ||
1900 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
1901 | * jumbo frames transmission. | |
1902 | */ | |
1903 | if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) { | |
1904 | u32 phy_reg; | |
1905 | ||
1906 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) | |
1907 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
1908 | phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC); | |
1909 | } | |
1910 | ||
1911 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
1912 | /* adjust output voltage */ | |
1913 | tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12); | |
1914 | } | |
1915 | ||
1916 | tg3_phy_toggle_automdix(tp, 1); | |
1917 | tg3_phy_set_wirespeed(tp); | |
1918 | return 0; | |
1919 | } | |
1920 | ||
1921 | static void tg3_frob_aux_power(struct tg3 *tp) | |
1922 | { | |
1923 | struct tg3 *tp_peer = tp; | |
1924 | ||
1925 | if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0) | |
1926 | return; | |
1927 | ||
1928 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || | |
1929 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { | |
1930 | struct net_device *dev_peer; | |
1931 | ||
1932 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
1933 | /* remove_one() may have been run on the peer. */ | |
1934 | if (!dev_peer) | |
1935 | tp_peer = tp; | |
1936 | else | |
1937 | tp_peer = netdev_priv(dev_peer); | |
1938 | } | |
1939 | ||
1940 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || | |
1941 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 || | |
1942 | (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || | |
1943 | (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { | |
1944 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
1945 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
1946 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
1947 | (GRC_LCLCTRL_GPIO_OE0 | | |
1948 | GRC_LCLCTRL_GPIO_OE1 | | |
1949 | GRC_LCLCTRL_GPIO_OE2 | | |
1950 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
1951 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
1952 | 100); | |
1953 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) { | |
1954 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
1955 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
1956 | GRC_LCLCTRL_GPIO_OE1 | | |
1957 | GRC_LCLCTRL_GPIO_OE2 | | |
1958 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
1959 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
1960 | tp->grc_local_ctrl; | |
1961 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
1962 | ||
1963 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
1964 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
1965 | ||
1966 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
1967 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
1968 | } else { | |
1969 | u32 no_gpio2; | |
1970 | u32 grc_local_ctrl = 0; | |
1971 | ||
1972 | if (tp_peer != tp && | |
1973 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
1974 | return; | |
1975 | ||
1976 | /* Workaround to prevent overdrawing Amps. */ | |
1977 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
1978 | ASIC_REV_5714) { | |
1979 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
1980 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
1981 | grc_local_ctrl, 100); | |
1982 | } | |
1983 | ||
1984 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
1985 | no_gpio2 = tp->nic_sram_data_cfg & | |
1986 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
1987 | ||
1988 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
1989 | GRC_LCLCTRL_GPIO_OE1 | | |
1990 | GRC_LCLCTRL_GPIO_OE2 | | |
1991 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
1992 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
1993 | if (no_gpio2) { | |
1994 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
1995 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
1996 | } | |
1997 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
1998 | grc_local_ctrl, 100); | |
1999 | ||
2000 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2001 | ||
2002 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2003 | grc_local_ctrl, 100); | |
2004 | ||
2005 | if (!no_gpio2) { | |
2006 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2007 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2008 | grc_local_ctrl, 100); | |
2009 | } | |
2010 | } | |
2011 | } else { | |
2012 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
2013 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
2014 | if (tp_peer != tp && | |
2015 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2016 | return; | |
2017 | ||
2018 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2019 | (GRC_LCLCTRL_GPIO_OE1 | | |
2020 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
2021 | ||
2022 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2023 | GRC_LCLCTRL_GPIO_OE1, 100); | |
2024 | ||
2025 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2026 | (GRC_LCLCTRL_GPIO_OE1 | | |
2027 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
2028 | } | |
2029 | } | |
2030 | } | |
2031 | ||
2032 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) | |
2033 | { | |
2034 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2035 | return 1; | |
2036 | else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) { | |
2037 | if (speed != SPEED_10) | |
2038 | return 1; | |
2039 | } else if (speed == SPEED_10) | |
2040 | return 1; | |
2041 | ||
2042 | return 0; | |
2043 | } | |
2044 | ||
2045 | static int tg3_setup_phy(struct tg3 *, int); | |
2046 | ||
2047 | #define RESET_KIND_SHUTDOWN 0 | |
2048 | #define RESET_KIND_INIT 1 | |
2049 | #define RESET_KIND_SUSPEND 2 | |
2050 | ||
2051 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2052 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2053 | static int tg3_nvram_lock(struct tg3 *); | |
2054 | static void tg3_nvram_unlock(struct tg3 *); | |
2055 | ||
2056 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) | |
2057 | { | |
2058 | u32 val; | |
2059 | ||
2060 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
2061 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2062 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2063 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2064 | ||
2065 | sg_dig_ctrl |= | |
2066 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2067 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2068 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2069 | } | |
2070 | return; | |
2071 | } | |
2072 | ||
2073 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2074 | tg3_bmcr_reset(tp); | |
2075 | val = tr32(GRC_MISC_CFG); | |
2076 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2077 | udelay(40); | |
2078 | return; | |
2079 | } else if (do_low_power) { | |
2080 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
2081 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
2082 | ||
2083 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
2084 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL | | |
2085 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2086 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2087 | MII_TG3_AUXCTL_PCTL_VREG_11V); | |
2088 | } | |
2089 | ||
2090 | /* The PHY should not be powered down on some chips because | |
2091 | * of bugs. | |
2092 | */ | |
2093 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2094 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2095 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
2096 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) | |
2097 | return; | |
2098 | ||
2099 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || | |
2100 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
2101 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | |
2102 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2103 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2104 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2105 | } | |
2106 | ||
2107 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
2108 | } | |
2109 | ||
2110 | /* tp->lock is held. */ | |
2111 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2112 | { | |
2113 | u32 addr_high, addr_low; | |
2114 | int i; | |
2115 | ||
2116 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2117 | tp->dev->dev_addr[1]); | |
2118 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2119 | (tp->dev->dev_addr[3] << 16) | | |
2120 | (tp->dev->dev_addr[4] << 8) | | |
2121 | (tp->dev->dev_addr[5] << 0)); | |
2122 | for (i = 0; i < 4; i++) { | |
2123 | if (i == 1 && skip_mac_1) | |
2124 | continue; | |
2125 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2126 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2127 | } | |
2128 | ||
2129 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2130 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2131 | for (i = 0; i < 12; i++) { | |
2132 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2133 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2134 | } | |
2135 | } | |
2136 | ||
2137 | addr_high = (tp->dev->dev_addr[0] + | |
2138 | tp->dev->dev_addr[1] + | |
2139 | tp->dev->dev_addr[2] + | |
2140 | tp->dev->dev_addr[3] + | |
2141 | tp->dev->dev_addr[4] + | |
2142 | tp->dev->dev_addr[5]) & | |
2143 | TX_BACKOFF_SEED_MASK; | |
2144 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2145 | } | |
2146 | ||
2147 | static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) | |
2148 | { | |
2149 | u32 misc_host_ctrl; | |
2150 | bool device_should_wake, do_low_power; | |
2151 | ||
2152 | /* Make sure register accesses (indirect or otherwise) | |
2153 | * will function correctly. | |
2154 | */ | |
2155 | pci_write_config_dword(tp->pdev, | |
2156 | TG3PCI_MISC_HOST_CTRL, | |
2157 | tp->misc_host_ctrl); | |
2158 | ||
2159 | switch (state) { | |
2160 | case PCI_D0: | |
2161 | pci_enable_wake(tp->pdev, state, false); | |
2162 | pci_set_power_state(tp->pdev, PCI_D0); | |
2163 | ||
2164 | /* Switch out of Vaux if it is a NIC */ | |
2165 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
2166 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); | |
2167 | ||
2168 | return 0; | |
2169 | ||
2170 | case PCI_D1: | |
2171 | case PCI_D2: | |
2172 | case PCI_D3hot: | |
2173 | break; | |
2174 | ||
2175 | default: | |
2176 | printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n", | |
2177 | tp->dev->name, state); | |
2178 | return -EINVAL; | |
2179 | } | |
2180 | ||
2181 | /* Restore the CLKREQ setting. */ | |
2182 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
2183 | u16 lnkctl; | |
2184 | ||
2185 | pci_read_config_word(tp->pdev, | |
2186 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2187 | &lnkctl); | |
2188 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2189 | pci_write_config_word(tp->pdev, | |
2190 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2191 | lnkctl); | |
2192 | } | |
2193 | ||
2194 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); | |
2195 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2196 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2197 | ||
2198 | device_should_wake = pci_pme_capable(tp->pdev, state) && | |
2199 | device_may_wakeup(&tp->pdev->dev) && | |
2200 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
2201 | ||
2202 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
2203 | do_low_power = false; | |
2204 | if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) && | |
2205 | !tp->link_config.phy_is_low_power) { | |
2206 | struct phy_device *phydev; | |
2207 | u32 phyid, advertising; | |
2208 | ||
2209 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; | |
2210 | ||
2211 | tp->link_config.phy_is_low_power = 1; | |
2212 | ||
2213 | tp->link_config.orig_speed = phydev->speed; | |
2214 | tp->link_config.orig_duplex = phydev->duplex; | |
2215 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2216 | tp->link_config.orig_advertising = phydev->advertising; | |
2217 | ||
2218 | advertising = ADVERTISED_TP | | |
2219 | ADVERTISED_Pause | | |
2220 | ADVERTISED_Autoneg | | |
2221 | ADVERTISED_10baseT_Half; | |
2222 | ||
2223 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2224 | device_should_wake) { | |
2225 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2226 | advertising |= | |
2227 | ADVERTISED_100baseT_Half | | |
2228 | ADVERTISED_100baseT_Full | | |
2229 | ADVERTISED_10baseT_Full; | |
2230 | else | |
2231 | advertising |= ADVERTISED_10baseT_Full; | |
2232 | } | |
2233 | ||
2234 | phydev->advertising = advertising; | |
2235 | ||
2236 | phy_start_aneg(phydev); | |
2237 | ||
2238 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
2239 | if (phyid != TG3_PHY_ID_BCMAC131) { | |
2240 | phyid &= TG3_PHY_OUI_MASK; | |
2241 | if (phyid == TG3_PHY_OUI_1 || | |
2242 | phyid == TG3_PHY_OUI_2 || | |
2243 | phyid == TG3_PHY_OUI_3) | |
2244 | do_low_power = true; | |
2245 | } | |
2246 | } | |
2247 | } else { | |
2248 | do_low_power = true; | |
2249 | ||
2250 | if (tp->link_config.phy_is_low_power == 0) { | |
2251 | tp->link_config.phy_is_low_power = 1; | |
2252 | tp->link_config.orig_speed = tp->link_config.speed; | |
2253 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2254 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2255 | } | |
2256 | ||
2257 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { | |
2258 | tp->link_config.speed = SPEED_10; | |
2259 | tp->link_config.duplex = DUPLEX_HALF; | |
2260 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2261 | tg3_setup_phy(tp, 0); | |
2262 | } | |
2263 | } | |
2264 | ||
2265 | __tg3_set_mac_addr(tp, 0); | |
2266 | ||
2267 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2268 | u32 val; | |
2269 | ||
2270 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2271 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
2272 | } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
2273 | int i; | |
2274 | u32 val; | |
2275 | ||
2276 | for (i = 0; i < 200; i++) { | |
2277 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2278 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2279 | break; | |
2280 | msleep(1); | |
2281 | } | |
2282 | } | |
2283 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) | |
2284 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | | |
2285 | WOL_DRV_STATE_SHUTDOWN | | |
2286 | WOL_DRV_WOL | | |
2287 | WOL_SET_MAGIC_PKT); | |
2288 | ||
2289 | if (device_should_wake) { | |
2290 | u32 mac_mode; | |
2291 | ||
2292 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
2293 | if (do_low_power) { | |
2294 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); | |
2295 | udelay(40); | |
2296 | } | |
2297 | ||
2298 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) | |
2299 | mac_mode = MAC_MODE_PORT_MODE_GMII; | |
2300 | else | |
2301 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
2302 | ||
2303 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; | |
2304 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2305 | ASIC_REV_5700) { | |
2306 | u32 speed = (tp->tg3_flags & | |
2307 | TG3_FLAG_WOL_SPEED_100MB) ? | |
2308 | SPEED_100 : SPEED_10; | |
2309 | if (tg3_5700_link_polarity(tp, speed)) | |
2310 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2311 | else | |
2312 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2313 | } | |
2314 | } else { | |
2315 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2316 | } | |
2317 | ||
2318 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
2319 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
2320 | ||
2321 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; | |
2322 | if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
2323 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) && | |
2324 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2325 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))) | |
2326 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; | |
2327 | ||
2328 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { | |
2329 | mac_mode |= tp->mac_mode & | |
2330 | (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); | |
2331 | if (mac_mode & MAC_MODE_APE_TX_EN) | |
2332 | mac_mode |= MAC_MODE_TDE_ENABLE; | |
2333 | } | |
2334 | ||
2335 | tw32_f(MAC_MODE, mac_mode); | |
2336 | udelay(100); | |
2337 | ||
2338 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2339 | udelay(10); | |
2340 | } | |
2341 | ||
2342 | if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) && | |
2343 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2344 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2345 | u32 base_val; | |
2346 | ||
2347 | base_val = tp->pci_clock_ctrl; | |
2348 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2349 | CLOCK_CTRL_TXCLK_DISABLE); | |
2350 | ||
2351 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | | |
2352 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
2353 | } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
2354 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || | |
2355 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { | |
2356 | /* do nothing */ | |
2357 | } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
2358 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { | |
2359 | u32 newbits1, newbits2; | |
2360 | ||
2361 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2362 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2363 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2364 | CLOCK_CTRL_TXCLK_DISABLE | | |
2365 | CLOCK_CTRL_ALTCLK); | |
2366 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2367 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
2368 | newbits1 = CLOCK_CTRL_625_CORE; | |
2369 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2370 | } else { | |
2371 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2372 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2373 | } | |
2374 | ||
2375 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, | |
2376 | 40); | |
2377 | ||
2378 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, | |
2379 | 40); | |
2380 | ||
2381 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
2382 | u32 newbits3; | |
2383 | ||
2384 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2385 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2386 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2387 | CLOCK_CTRL_TXCLK_DISABLE | | |
2388 | CLOCK_CTRL_44MHZ_CORE); | |
2389 | } else { | |
2390 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2391 | } | |
2392 | ||
2393 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
2394 | tp->pci_clock_ctrl | newbits3, 40); | |
2395 | } | |
2396 | } | |
2397 | ||
2398 | if (!(device_should_wake) && | |
2399 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
2400 | tg3_power_down_phy(tp, do_low_power); | |
2401 | ||
2402 | tg3_frob_aux_power(tp); | |
2403 | ||
2404 | /* Workaround for unstable PLL clock */ | |
2405 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2406 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2407 | u32 val = tr32(0x7d00); | |
2408 | ||
2409 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2410 | tw32(0x7d00, val); | |
2411 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
2412 | int err; | |
2413 | ||
2414 | err = tg3_nvram_lock(tp); | |
2415 | tg3_halt_cpu(tp, RX_CPU_BASE); | |
2416 | if (!err) | |
2417 | tg3_nvram_unlock(tp); | |
2418 | } | |
2419 | } | |
2420 | ||
2421 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); | |
2422 | ||
2423 | if (device_should_wake) | |
2424 | pci_enable_wake(tp->pdev, state, true); | |
2425 | ||
2426 | /* Finally, set the new power state. */ | |
2427 | pci_set_power_state(tp->pdev, state); | |
2428 | ||
2429 | return 0; | |
2430 | } | |
2431 | ||
2432 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) | |
2433 | { | |
2434 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2435 | case MII_TG3_AUX_STAT_10HALF: | |
2436 | *speed = SPEED_10; | |
2437 | *duplex = DUPLEX_HALF; | |
2438 | break; | |
2439 | ||
2440 | case MII_TG3_AUX_STAT_10FULL: | |
2441 | *speed = SPEED_10; | |
2442 | *duplex = DUPLEX_FULL; | |
2443 | break; | |
2444 | ||
2445 | case MII_TG3_AUX_STAT_100HALF: | |
2446 | *speed = SPEED_100; | |
2447 | *duplex = DUPLEX_HALF; | |
2448 | break; | |
2449 | ||
2450 | case MII_TG3_AUX_STAT_100FULL: | |
2451 | *speed = SPEED_100; | |
2452 | *duplex = DUPLEX_FULL; | |
2453 | break; | |
2454 | ||
2455 | case MII_TG3_AUX_STAT_1000HALF: | |
2456 | *speed = SPEED_1000; | |
2457 | *duplex = DUPLEX_HALF; | |
2458 | break; | |
2459 | ||
2460 | case MII_TG3_AUX_STAT_1000FULL: | |
2461 | *speed = SPEED_1000; | |
2462 | *duplex = DUPLEX_FULL; | |
2463 | break; | |
2464 | ||
2465 | default: | |
2466 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2467 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : | |
2468 | SPEED_10; | |
2469 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
2470 | DUPLEX_HALF; | |
2471 | break; | |
2472 | } | |
2473 | *speed = SPEED_INVALID; | |
2474 | *duplex = DUPLEX_INVALID; | |
2475 | break; | |
2476 | } | |
2477 | } | |
2478 | ||
2479 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
2480 | { | |
2481 | u32 new_adv; | |
2482 | int i; | |
2483 | ||
2484 | if (tp->link_config.phy_is_low_power) { | |
2485 | /* Entering low power mode. Disable gigabit and | |
2486 | * 100baseT advertisements. | |
2487 | */ | |
2488 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2489 | ||
2490 | new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2491 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
2492 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2493 | new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL); | |
2494 | ||
2495 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2496 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
2497 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) | |
2498 | tp->link_config.advertising &= | |
2499 | ~(ADVERTISED_1000baseT_Half | | |
2500 | ADVERTISED_1000baseT_Full); | |
2501 | ||
2502 | new_adv = ADVERTISE_CSMA; | |
2503 | if (tp->link_config.advertising & ADVERTISED_10baseT_Half) | |
2504 | new_adv |= ADVERTISE_10HALF; | |
2505 | if (tp->link_config.advertising & ADVERTISED_10baseT_Full) | |
2506 | new_adv |= ADVERTISE_10FULL; | |
2507 | if (tp->link_config.advertising & ADVERTISED_100baseT_Half) | |
2508 | new_adv |= ADVERTISE_100HALF; | |
2509 | if (tp->link_config.advertising & ADVERTISED_100baseT_Full) | |
2510 | new_adv |= ADVERTISE_100FULL; | |
2511 | ||
2512 | new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2513 | ||
2514 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2515 | ||
2516 | if (tp->link_config.advertising & | |
2517 | (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { | |
2518 | new_adv = 0; | |
2519 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
2520 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | |
2521 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
2522 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | |
2523 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) && | |
2524 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2525 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) | |
2526 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2527 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2528 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2529 | } else { | |
2530 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2531 | } | |
2532 | } else { | |
2533 | new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2534 | new_adv |= ADVERTISE_CSMA; | |
2535 | ||
2536 | /* Asking for a specific link mode. */ | |
2537 | if (tp->link_config.speed == SPEED_1000) { | |
2538 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2539 | ||
2540 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2541 | new_adv = MII_TG3_CTRL_ADV_1000_FULL; | |
2542 | else | |
2543 | new_adv = MII_TG3_CTRL_ADV_1000_HALF; | |
2544 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2545 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
2546 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2547 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2548 | } else { | |
2549 | if (tp->link_config.speed == SPEED_100) { | |
2550 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2551 | new_adv |= ADVERTISE_100FULL; | |
2552 | else | |
2553 | new_adv |= ADVERTISE_100HALF; | |
2554 | } else { | |
2555 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2556 | new_adv |= ADVERTISE_10FULL; | |
2557 | else | |
2558 | new_adv |= ADVERTISE_10HALF; | |
2559 | } | |
2560 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2561 | ||
2562 | new_adv = 0; | |
2563 | } | |
2564 | ||
2565 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2566 | } | |
2567 | ||
2568 | if (tp->link_config.autoneg == AUTONEG_DISABLE && | |
2569 | tp->link_config.speed != SPEED_INVALID) { | |
2570 | u32 bmcr, orig_bmcr; | |
2571 | ||
2572 | tp->link_config.active_speed = tp->link_config.speed; | |
2573 | tp->link_config.active_duplex = tp->link_config.duplex; | |
2574 | ||
2575 | bmcr = 0; | |
2576 | switch (tp->link_config.speed) { | |
2577 | default: | |
2578 | case SPEED_10: | |
2579 | break; | |
2580 | ||
2581 | case SPEED_100: | |
2582 | bmcr |= BMCR_SPEED100; | |
2583 | break; | |
2584 | ||
2585 | case SPEED_1000: | |
2586 | bmcr |= TG3_BMCR_SPEED1000; | |
2587 | break; | |
2588 | } | |
2589 | ||
2590 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2591 | bmcr |= BMCR_FULLDPLX; | |
2592 | ||
2593 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
2594 | (bmcr != orig_bmcr)) { | |
2595 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
2596 | for (i = 0; i < 1500; i++) { | |
2597 | u32 tmp; | |
2598 | ||
2599 | udelay(10); | |
2600 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
2601 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
2602 | continue; | |
2603 | if (!(tmp & BMSR_LSTATUS)) { | |
2604 | udelay(40); | |
2605 | break; | |
2606 | } | |
2607 | } | |
2608 | tg3_writephy(tp, MII_BMCR, bmcr); | |
2609 | udelay(40); | |
2610 | } | |
2611 | } else { | |
2612 | tg3_writephy(tp, MII_BMCR, | |
2613 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2614 | } | |
2615 | } | |
2616 | ||
2617 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
2618 | { | |
2619 | int err; | |
2620 | ||
2621 | /* Turn off tap power management. */ | |
2622 | /* Set Extended packet length bit */ | |
2623 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
2624 | ||
2625 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012); | |
2626 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804); | |
2627 | ||
2628 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013); | |
2629 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204); | |
2630 | ||
2631 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006); | |
2632 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132); | |
2633 | ||
2634 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006); | |
2635 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232); | |
2636 | ||
2637 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
2638 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20); | |
2639 | ||
2640 | udelay(40); | |
2641 | ||
2642 | return err; | |
2643 | } | |
2644 | ||
2645 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) | |
2646 | { | |
2647 | u32 adv_reg, all_mask = 0; | |
2648 | ||
2649 | if (mask & ADVERTISED_10baseT_Half) | |
2650 | all_mask |= ADVERTISE_10HALF; | |
2651 | if (mask & ADVERTISED_10baseT_Full) | |
2652 | all_mask |= ADVERTISE_10FULL; | |
2653 | if (mask & ADVERTISED_100baseT_Half) | |
2654 | all_mask |= ADVERTISE_100HALF; | |
2655 | if (mask & ADVERTISED_100baseT_Full) | |
2656 | all_mask |= ADVERTISE_100FULL; | |
2657 | ||
2658 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
2659 | return 0; | |
2660 | ||
2661 | if ((adv_reg & all_mask) != all_mask) | |
2662 | return 0; | |
2663 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
2664 | u32 tg3_ctrl; | |
2665 | ||
2666 | all_mask = 0; | |
2667 | if (mask & ADVERTISED_1000baseT_Half) | |
2668 | all_mask |= ADVERTISE_1000HALF; | |
2669 | if (mask & ADVERTISED_1000baseT_Full) | |
2670 | all_mask |= ADVERTISE_1000FULL; | |
2671 | ||
2672 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) | |
2673 | return 0; | |
2674 | ||
2675 | if ((tg3_ctrl & all_mask) != all_mask) | |
2676 | return 0; | |
2677 | } | |
2678 | return 1; | |
2679 | } | |
2680 | ||
2681 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) | |
2682 | { | |
2683 | u32 curadv, reqadv; | |
2684 | ||
2685 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
2686 | return 1; | |
2687 | ||
2688 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
2689 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2690 | ||
2691 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
2692 | if (curadv != reqadv) | |
2693 | return 0; | |
2694 | ||
2695 | if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) | |
2696 | tg3_readphy(tp, MII_LPA, rmtadv); | |
2697 | } else { | |
2698 | /* Reprogram the advertisement register, even if it | |
2699 | * does not affect the current link. If the link | |
2700 | * gets renegotiated in the future, we can save an | |
2701 | * additional renegotiation cycle by advertising | |
2702 | * it correctly in the first place. | |
2703 | */ | |
2704 | if (curadv != reqadv) { | |
2705 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
2706 | ADVERTISE_PAUSE_ASYM); | |
2707 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
2708 | } | |
2709 | } | |
2710 | ||
2711 | return 1; | |
2712 | } | |
2713 | ||
2714 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |
2715 | { | |
2716 | int current_link_up; | |
2717 | u32 bmsr, dummy; | |
2718 | u32 lcl_adv, rmt_adv; | |
2719 | u16 current_speed; | |
2720 | u8 current_duplex; | |
2721 | int i, err; | |
2722 | ||
2723 | tw32(MAC_EVENT, 0); | |
2724 | ||
2725 | tw32_f(MAC_STATUS, | |
2726 | (MAC_STATUS_SYNC_CHANGED | | |
2727 | MAC_STATUS_CFG_CHANGED | | |
2728 | MAC_STATUS_MI_COMPLETION | | |
2729 | MAC_STATUS_LNKSTATE_CHANGED)); | |
2730 | udelay(40); | |
2731 | ||
2732 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
2733 | tw32_f(MAC_MI_MODE, | |
2734 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
2735 | udelay(80); | |
2736 | } | |
2737 | ||
2738 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); | |
2739 | ||
2740 | /* Some third-party PHYs need to be reset on link going | |
2741 | * down. | |
2742 | */ | |
2743 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2744 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2745 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
2746 | netif_carrier_ok(tp->dev)) { | |
2747 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
2748 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
2749 | !(bmsr & BMSR_LSTATUS)) | |
2750 | force_reset = 1; | |
2751 | } | |
2752 | if (force_reset) | |
2753 | tg3_phy_reset(tp); | |
2754 | ||
2755 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
2756 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
2757 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
2758 | !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) | |
2759 | bmsr = 0; | |
2760 | ||
2761 | if (!(bmsr & BMSR_LSTATUS)) { | |
2762 | err = tg3_init_5401phy_dsp(tp); | |
2763 | if (err) | |
2764 | return err; | |
2765 | ||
2766 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
2767 | for (i = 0; i < 1000; i++) { | |
2768 | udelay(10); | |
2769 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
2770 | (bmsr & BMSR_LSTATUS)) { | |
2771 | udelay(40); | |
2772 | break; | |
2773 | } | |
2774 | } | |
2775 | ||
2776 | if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 && | |
2777 | !(bmsr & BMSR_LSTATUS) && | |
2778 | tp->link_config.active_speed == SPEED_1000) { | |
2779 | err = tg3_phy_reset(tp); | |
2780 | if (!err) | |
2781 | err = tg3_init_5401phy_dsp(tp); | |
2782 | if (err) | |
2783 | return err; | |
2784 | } | |
2785 | } | |
2786 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2787 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
2788 | /* 5701 {A0,B0} CRC bug workaround */ | |
2789 | tg3_writephy(tp, 0x15, 0x0a75); | |
2790 | tg3_writephy(tp, 0x1c, 0x8c68); | |
2791 | tg3_writephy(tp, 0x1c, 0x8d68); | |
2792 | tg3_writephy(tp, 0x1c, 0x8c68); | |
2793 | } | |
2794 | ||
2795 | /* Clear pending interrupts... */ | |
2796 | tg3_readphy(tp, MII_TG3_ISTAT, &dummy); | |
2797 | tg3_readphy(tp, MII_TG3_ISTAT, &dummy); | |
2798 | ||
2799 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) | |
2800 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); | |
2801 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) | |
2802 | tg3_writephy(tp, MII_TG3_IMASK, ~0); | |
2803 | ||
2804 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2805 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2806 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
2807 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
2808 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
2809 | else | |
2810 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
2811 | } | |
2812 | ||
2813 | current_link_up = 0; | |
2814 | current_speed = SPEED_INVALID; | |
2815 | current_duplex = DUPLEX_INVALID; | |
2816 | ||
2817 | if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) { | |
2818 | u32 val; | |
2819 | ||
2820 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007); | |
2821 | tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); | |
2822 | if (!(val & (1 << 10))) { | |
2823 | val |= (1 << 10); | |
2824 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
2825 | goto relink; | |
2826 | } | |
2827 | } | |
2828 | ||
2829 | bmsr = 0; | |
2830 | for (i = 0; i < 100; i++) { | |
2831 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
2832 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
2833 | (bmsr & BMSR_LSTATUS)) | |
2834 | break; | |
2835 | udelay(40); | |
2836 | } | |
2837 | ||
2838 | if (bmsr & BMSR_LSTATUS) { | |
2839 | u32 aux_stat, bmcr; | |
2840 | ||
2841 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
2842 | for (i = 0; i < 2000; i++) { | |
2843 | udelay(10); | |
2844 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
2845 | aux_stat) | |
2846 | break; | |
2847 | } | |
2848 | ||
2849 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
2850 | ¤t_speed, | |
2851 | ¤t_duplex); | |
2852 | ||
2853 | bmcr = 0; | |
2854 | for (i = 0; i < 200; i++) { | |
2855 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
2856 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
2857 | continue; | |
2858 | if (bmcr && bmcr != 0x7fff) | |
2859 | break; | |
2860 | udelay(10); | |
2861 | } | |
2862 | ||
2863 | lcl_adv = 0; | |
2864 | rmt_adv = 0; | |
2865 | ||
2866 | tp->link_config.active_speed = current_speed; | |
2867 | tp->link_config.active_duplex = current_duplex; | |
2868 | ||
2869 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
2870 | if ((bmcr & BMCR_ANENABLE) && | |
2871 | tg3_copper_is_advertising_all(tp, | |
2872 | tp->link_config.advertising)) { | |
2873 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
2874 | &rmt_adv)) | |
2875 | current_link_up = 1; | |
2876 | } | |
2877 | } else { | |
2878 | if (!(bmcr & BMCR_ANENABLE) && | |
2879 | tp->link_config.speed == current_speed && | |
2880 | tp->link_config.duplex == current_duplex && | |
2881 | tp->link_config.flowctrl == | |
2882 | tp->link_config.active_flowctrl) { | |
2883 | current_link_up = 1; | |
2884 | } | |
2885 | } | |
2886 | ||
2887 | if (current_link_up == 1 && | |
2888 | tp->link_config.active_duplex == DUPLEX_FULL) | |
2889 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
2890 | } | |
2891 | ||
2892 | relink: | |
2893 | if (current_link_up == 0 || tp->link_config.phy_is_low_power) { | |
2894 | u32 tmp; | |
2895 | ||
2896 | tg3_phy_copper_begin(tp); | |
2897 | ||
2898 | tg3_readphy(tp, MII_BMSR, &tmp); | |
2899 | if (!tg3_readphy(tp, MII_BMSR, &tmp) && | |
2900 | (tmp & BMSR_LSTATUS)) | |
2901 | current_link_up = 1; | |
2902 | } | |
2903 | ||
2904 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
2905 | if (current_link_up == 1) { | |
2906 | if (tp->link_config.active_speed == SPEED_100 || | |
2907 | tp->link_config.active_speed == SPEED_10) | |
2908 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
2909 | else | |
2910 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
2911 | } else | |
2912 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
2913 | ||
2914 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
2915 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
2916 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
2917 | ||
2918 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
2919 | if (current_link_up == 1 && | |
2920 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
2921 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
2922 | else | |
2923 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2924 | } | |
2925 | ||
2926 | /* ??? Without this setting Netgear GA302T PHY does not | |
2927 | * ??? send/receive packets... | |
2928 | */ | |
2929 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 && | |
2930 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { | |
2931 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
2932 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
2933 | udelay(80); | |
2934 | } | |
2935 | ||
2936 | tw32_f(MAC_MODE, tp->mac_mode); | |
2937 | udelay(40); | |
2938 | ||
2939 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { | |
2940 | /* Polled via timer. */ | |
2941 | tw32_f(MAC_EVENT, 0); | |
2942 | } else { | |
2943 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
2944 | } | |
2945 | udelay(40); | |
2946 | ||
2947 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
2948 | current_link_up == 1 && | |
2949 | tp->link_config.active_speed == SPEED_1000 && | |
2950 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || | |
2951 | (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { | |
2952 | udelay(120); | |
2953 | tw32_f(MAC_STATUS, | |
2954 | (MAC_STATUS_SYNC_CHANGED | | |
2955 | MAC_STATUS_CFG_CHANGED)); | |
2956 | udelay(40); | |
2957 | tg3_write_mem(tp, | |
2958 | NIC_SRAM_FIRMWARE_MBOX, | |
2959 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
2960 | } | |
2961 | ||
2962 | /* Prevent send BD corruption. */ | |
2963 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
2964 | u16 oldlnkctl, newlnkctl; | |
2965 | ||
2966 | pci_read_config_word(tp->pdev, | |
2967 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2968 | &oldlnkctl); | |
2969 | if (tp->link_config.active_speed == SPEED_100 || | |
2970 | tp->link_config.active_speed == SPEED_10) | |
2971 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
2972 | else | |
2973 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
2974 | if (newlnkctl != oldlnkctl) | |
2975 | pci_write_config_word(tp->pdev, | |
2976 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2977 | newlnkctl); | |
2978 | } | |
2979 | ||
2980 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
2981 | if (current_link_up) | |
2982 | netif_carrier_on(tp->dev); | |
2983 | else | |
2984 | netif_carrier_off(tp->dev); | |
2985 | tg3_link_report(tp); | |
2986 | } | |
2987 | ||
2988 | return 0; | |
2989 | } | |
2990 | ||
2991 | struct tg3_fiber_aneginfo { | |
2992 | int state; | |
2993 | #define ANEG_STATE_UNKNOWN 0 | |
2994 | #define ANEG_STATE_AN_ENABLE 1 | |
2995 | #define ANEG_STATE_RESTART_INIT 2 | |
2996 | #define ANEG_STATE_RESTART 3 | |
2997 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
2998 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
2999 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3000 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3001 | #define ANEG_STATE_ACK_DETECT 8 | |
3002 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3003 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3004 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3005 | #define ANEG_STATE_IDLE_DETECT 12 | |
3006 | #define ANEG_STATE_LINK_OK 13 | |
3007 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3008 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3009 | ||
3010 | u32 flags; | |
3011 | #define MR_AN_ENABLE 0x00000001 | |
3012 | #define MR_RESTART_AN 0x00000002 | |
3013 | #define MR_AN_COMPLETE 0x00000004 | |
3014 | #define MR_PAGE_RX 0x00000008 | |
3015 | #define MR_NP_LOADED 0x00000010 | |
3016 | #define MR_TOGGLE_TX 0x00000020 | |
3017 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3018 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3019 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3020 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3021 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3022 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3023 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3024 | #define MR_TOGGLE_RX 0x00002000 | |
3025 | #define MR_NP_RX 0x00004000 | |
3026 | ||
3027 | #define MR_LINK_OK 0x80000000 | |
3028 | ||
3029 | unsigned long link_time, cur_time; | |
3030 | ||
3031 | u32 ability_match_cfg; | |
3032 | int ability_match_count; | |
3033 | ||
3034 | char ability_match, idle_match, ack_match; | |
3035 | ||
3036 | u32 txconfig, rxconfig; | |
3037 | #define ANEG_CFG_NP 0x00000080 | |
3038 | #define ANEG_CFG_ACK 0x00000040 | |
3039 | #define ANEG_CFG_RF2 0x00000020 | |
3040 | #define ANEG_CFG_RF1 0x00000010 | |
3041 | #define ANEG_CFG_PS2 0x00000001 | |
3042 | #define ANEG_CFG_PS1 0x00008000 | |
3043 | #define ANEG_CFG_HD 0x00004000 | |
3044 | #define ANEG_CFG_FD 0x00002000 | |
3045 | #define ANEG_CFG_INVAL 0x00001f06 | |
3046 | ||
3047 | }; | |
3048 | #define ANEG_OK 0 | |
3049 | #define ANEG_DONE 1 | |
3050 | #define ANEG_TIMER_ENAB 2 | |
3051 | #define ANEG_FAILED -1 | |
3052 | ||
3053 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3054 | ||
3055 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3056 | struct tg3_fiber_aneginfo *ap) | |
3057 | { | |
3058 | u16 flowctrl; | |
3059 | unsigned long delta; | |
3060 | u32 rx_cfg_reg; | |
3061 | int ret; | |
3062 | ||
3063 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3064 | ap->rxconfig = 0; | |
3065 | ap->link_time = 0; | |
3066 | ap->cur_time = 0; | |
3067 | ap->ability_match_cfg = 0; | |
3068 | ap->ability_match_count = 0; | |
3069 | ap->ability_match = 0; | |
3070 | ap->idle_match = 0; | |
3071 | ap->ack_match = 0; | |
3072 | } | |
3073 | ap->cur_time++; | |
3074 | ||
3075 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3076 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3077 | ||
3078 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3079 | ap->ability_match_cfg = rx_cfg_reg; | |
3080 | ap->ability_match = 0; | |
3081 | ap->ability_match_count = 0; | |
3082 | } else { | |
3083 | if (++ap->ability_match_count > 1) { | |
3084 | ap->ability_match = 1; | |
3085 | ap->ability_match_cfg = rx_cfg_reg; | |
3086 | } | |
3087 | } | |
3088 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3089 | ap->ack_match = 1; | |
3090 | else | |
3091 | ap->ack_match = 0; | |
3092 | ||
3093 | ap->idle_match = 0; | |
3094 | } else { | |
3095 | ap->idle_match = 1; | |
3096 | ap->ability_match_cfg = 0; | |
3097 | ap->ability_match_count = 0; | |
3098 | ap->ability_match = 0; | |
3099 | ap->ack_match = 0; | |
3100 | ||
3101 | rx_cfg_reg = 0; | |
3102 | } | |
3103 | ||
3104 | ap->rxconfig = rx_cfg_reg; | |
3105 | ret = ANEG_OK; | |
3106 | ||
3107 | switch(ap->state) { | |
3108 | case ANEG_STATE_UNKNOWN: | |
3109 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3110 | ap->state = ANEG_STATE_AN_ENABLE; | |
3111 | ||
3112 | /* fallthru */ | |
3113 | case ANEG_STATE_AN_ENABLE: | |
3114 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3115 | if (ap->flags & MR_AN_ENABLE) { | |
3116 | ap->link_time = 0; | |
3117 | ap->cur_time = 0; | |
3118 | ap->ability_match_cfg = 0; | |
3119 | ap->ability_match_count = 0; | |
3120 | ap->ability_match = 0; | |
3121 | ap->idle_match = 0; | |
3122 | ap->ack_match = 0; | |
3123 | ||
3124 | ap->state = ANEG_STATE_RESTART_INIT; | |
3125 | } else { | |
3126 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3127 | } | |
3128 | break; | |
3129 | ||
3130 | case ANEG_STATE_RESTART_INIT: | |
3131 | ap->link_time = ap->cur_time; | |
3132 | ap->flags &= ~(MR_NP_LOADED); | |
3133 | ap->txconfig = 0; | |
3134 | tw32(MAC_TX_AUTO_NEG, 0); | |
3135 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3136 | tw32_f(MAC_MODE, tp->mac_mode); | |
3137 | udelay(40); | |
3138 | ||
3139 | ret = ANEG_TIMER_ENAB; | |
3140 | ap->state = ANEG_STATE_RESTART; | |
3141 | ||
3142 | /* fallthru */ | |
3143 | case ANEG_STATE_RESTART: | |
3144 | delta = ap->cur_time - ap->link_time; | |
3145 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3146 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; | |
3147 | } else { | |
3148 | ret = ANEG_TIMER_ENAB; | |
3149 | } | |
3150 | break; | |
3151 | ||
3152 | case ANEG_STATE_DISABLE_LINK_OK: | |
3153 | ret = ANEG_DONE; | |
3154 | break; | |
3155 | ||
3156 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3157 | ap->flags &= ~(MR_TOGGLE_TX); | |
3158 | ap->txconfig = ANEG_CFG_FD; | |
3159 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3160 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3161 | ap->txconfig |= ANEG_CFG_PS1; | |
3162 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3163 | ap->txconfig |= ANEG_CFG_PS2; | |
3164 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3165 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3166 | tw32_f(MAC_MODE, tp->mac_mode); | |
3167 | udelay(40); | |
3168 | ||
3169 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3170 | break; | |
3171 | ||
3172 | case ANEG_STATE_ABILITY_DETECT: | |
3173 | if (ap->ability_match != 0 && ap->rxconfig != 0) { | |
3174 | ap->state = ANEG_STATE_ACK_DETECT_INIT; | |
3175 | } | |
3176 | break; | |
3177 | ||
3178 | case ANEG_STATE_ACK_DETECT_INIT: | |
3179 | ap->txconfig |= ANEG_CFG_ACK; | |
3180 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3181 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3182 | tw32_f(MAC_MODE, tp->mac_mode); | |
3183 | udelay(40); | |
3184 | ||
3185 | ap->state = ANEG_STATE_ACK_DETECT; | |
3186 | ||
3187 | /* fallthru */ | |
3188 | case ANEG_STATE_ACK_DETECT: | |
3189 | if (ap->ack_match != 0) { | |
3190 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3191 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3192 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3193 | } else { | |
3194 | ap->state = ANEG_STATE_AN_ENABLE; | |
3195 | } | |
3196 | } else if (ap->ability_match != 0 && | |
3197 | ap->rxconfig == 0) { | |
3198 | ap->state = ANEG_STATE_AN_ENABLE; | |
3199 | } | |
3200 | break; | |
3201 | ||
3202 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3203 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3204 | ret = ANEG_FAILED; | |
3205 | break; | |
3206 | } | |
3207 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3208 | MR_LP_ADV_HALF_DUPLEX | | |
3209 | MR_LP_ADV_SYM_PAUSE | | |
3210 | MR_LP_ADV_ASYM_PAUSE | | |
3211 | MR_LP_ADV_REMOTE_FAULT1 | | |
3212 | MR_LP_ADV_REMOTE_FAULT2 | | |
3213 | MR_LP_ADV_NEXT_PAGE | | |
3214 | MR_TOGGLE_RX | | |
3215 | MR_NP_RX); | |
3216 | if (ap->rxconfig & ANEG_CFG_FD) | |
3217 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3218 | if (ap->rxconfig & ANEG_CFG_HD) | |
3219 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3220 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3221 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3222 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3223 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3224 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3225 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3226 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3227 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3228 | if (ap->rxconfig & ANEG_CFG_NP) | |
3229 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3230 | ||
3231 | ap->link_time = ap->cur_time; | |
3232 | ||
3233 | ap->flags ^= (MR_TOGGLE_TX); | |
3234 | if (ap->rxconfig & 0x0008) | |
3235 | ap->flags |= MR_TOGGLE_RX; | |
3236 | if (ap->rxconfig & ANEG_CFG_NP) | |
3237 | ap->flags |= MR_NP_RX; | |
3238 | ap->flags |= MR_PAGE_RX; | |
3239 | ||
3240 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3241 | ret = ANEG_TIMER_ENAB; | |
3242 | break; | |
3243 | ||
3244 | case ANEG_STATE_COMPLETE_ACK: | |
3245 | if (ap->ability_match != 0 && | |
3246 | ap->rxconfig == 0) { | |
3247 | ap->state = ANEG_STATE_AN_ENABLE; | |
3248 | break; | |
3249 | } | |
3250 | delta = ap->cur_time - ap->link_time; | |
3251 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3252 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3253 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3254 | } else { | |
3255 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3256 | !(ap->flags & MR_NP_RX)) { | |
3257 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3258 | } else { | |
3259 | ret = ANEG_FAILED; | |
3260 | } | |
3261 | } | |
3262 | } | |
3263 | break; | |
3264 | ||
3265 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3266 | ap->link_time = ap->cur_time; | |
3267 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3268 | tw32_f(MAC_MODE, tp->mac_mode); | |
3269 | udelay(40); | |
3270 | ||
3271 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3272 | ret = ANEG_TIMER_ENAB; | |
3273 | break; | |
3274 | ||
3275 | case ANEG_STATE_IDLE_DETECT: | |
3276 | if (ap->ability_match != 0 && | |
3277 | ap->rxconfig == 0) { | |
3278 | ap->state = ANEG_STATE_AN_ENABLE; | |
3279 | break; | |
3280 | } | |
3281 | delta = ap->cur_time - ap->link_time; | |
3282 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3283 | /* XXX another gem from the Broadcom driver :( */ | |
3284 | ap->state = ANEG_STATE_LINK_OK; | |
3285 | } | |
3286 | break; | |
3287 | ||
3288 | case ANEG_STATE_LINK_OK: | |
3289 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3290 | ret = ANEG_DONE; | |
3291 | break; | |
3292 | ||
3293 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3294 | /* ??? unimplemented */ | |
3295 | break; | |
3296 | ||
3297 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3298 | /* ??? unimplemented */ | |
3299 | break; | |
3300 | ||
3301 | default: | |
3302 | ret = ANEG_FAILED; | |
3303 | break; | |
3304 | } | |
3305 | ||
3306 | return ret; | |
3307 | } | |
3308 | ||
3309 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) | |
3310 | { | |
3311 | int res = 0; | |
3312 | struct tg3_fiber_aneginfo aninfo; | |
3313 | int status = ANEG_FAILED; | |
3314 | unsigned int tick; | |
3315 | u32 tmp; | |
3316 | ||
3317 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3318 | ||
3319 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3320 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3321 | udelay(40); | |
3322 | ||
3323 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3324 | udelay(40); | |
3325 | ||
3326 | memset(&aninfo, 0, sizeof(aninfo)); | |
3327 | aninfo.flags |= MR_AN_ENABLE; | |
3328 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3329 | aninfo.cur_time = 0; | |
3330 | tick = 0; | |
3331 | while (++tick < 195000) { | |
3332 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3333 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3334 | break; | |
3335 | ||
3336 | udelay(1); | |
3337 | } | |
3338 | ||
3339 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3340 | tw32_f(MAC_MODE, tp->mac_mode); | |
3341 | udelay(40); | |
3342 | ||
3343 | *txflags = aninfo.txconfig; | |
3344 | *rxflags = aninfo.flags; | |
3345 | ||
3346 | if (status == ANEG_DONE && | |
3347 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3348 | MR_LP_ADV_FULL_DUPLEX))) | |
3349 | res = 1; | |
3350 | ||
3351 | return res; | |
3352 | } | |
3353 | ||
3354 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3355 | { | |
3356 | u32 mac_status = tr32(MAC_STATUS); | |
3357 | int i; | |
3358 | ||
3359 | /* Reset when initting first time or we have a link. */ | |
3360 | if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) && | |
3361 | !(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3362 | return; | |
3363 | ||
3364 | /* Set PLL lock range. */ | |
3365 | tg3_writephy(tp, 0x16, 0x8007); | |
3366 | ||
3367 | /* SW reset */ | |
3368 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3369 | ||
3370 | /* Wait for reset to complete. */ | |
3371 | /* XXX schedule_timeout() ... */ | |
3372 | for (i = 0; i < 500; i++) | |
3373 | udelay(10); | |
3374 | ||
3375 | /* Config mode; select PMA/Ch 1 regs. */ | |
3376 | tg3_writephy(tp, 0x10, 0x8411); | |
3377 | ||
3378 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3379 | tg3_writephy(tp, 0x11, 0x0a10); | |
3380 | ||
3381 | tg3_writephy(tp, 0x18, 0x00a0); | |
3382 | tg3_writephy(tp, 0x16, 0x41ff); | |
3383 | ||
3384 | /* Assert and deassert POR. */ | |
3385 | tg3_writephy(tp, 0x13, 0x0400); | |
3386 | udelay(40); | |
3387 | tg3_writephy(tp, 0x13, 0x0000); | |
3388 | ||
3389 | tg3_writephy(tp, 0x11, 0x0a50); | |
3390 | udelay(40); | |
3391 | tg3_writephy(tp, 0x11, 0x0a10); | |
3392 | ||
3393 | /* Wait for signal to stabilize */ | |
3394 | /* XXX schedule_timeout() ... */ | |
3395 | for (i = 0; i < 15000; i++) | |
3396 | udelay(10); | |
3397 | ||
3398 | /* Deselect the channel register so we can read the PHYID | |
3399 | * later. | |
3400 | */ | |
3401 | tg3_writephy(tp, 0x10, 0x8011); | |
3402 | } | |
3403 | ||
3404 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3405 | { | |
3406 | u16 flowctrl; | |
3407 | u32 sg_dig_ctrl, sg_dig_status; | |
3408 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3409 | int workaround, port_a; | |
3410 | int current_link_up; | |
3411 | ||
3412 | serdes_cfg = 0; | |
3413 | expected_sg_dig_ctrl = 0; | |
3414 | workaround = 0; | |
3415 | port_a = 1; | |
3416 | current_link_up = 0; | |
3417 | ||
3418 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3419 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3420 | workaround = 1; | |
3421 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3422 | port_a = 0; | |
3423 | ||
3424 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3425 | /* preserve bits 20-23 for voltage regulator */ | |
3426 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3427 | } | |
3428 | ||
3429 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3430 | ||
3431 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
3432 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { | |
3433 | if (workaround) { | |
3434 | u32 val = serdes_cfg; | |
3435 | ||
3436 | if (port_a) | |
3437 | val |= 0xc010000; | |
3438 | else | |
3439 | val |= 0x4010000; | |
3440 | tw32_f(MAC_SERDES_CFG, val); | |
3441 | } | |
3442 | ||
3443 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
3444 | } | |
3445 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
3446 | tg3_setup_flow_control(tp, 0, 0); | |
3447 | current_link_up = 1; | |
3448 | } | |
3449 | goto out; | |
3450 | } | |
3451 | ||
3452 | /* Want auto-negotiation. */ | |
3453 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; | |
3454 | ||
3455 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3456 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3457 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
3458 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3459 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
3460 | ||
3461 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
3462 | if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) && | |
3463 | tp->serdes_counter && | |
3464 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
3465 | MAC_STATUS_RCVD_CFG)) == | |
3466 | MAC_STATUS_PCS_SYNCED)) { | |
3467 | tp->serdes_counter--; | |
3468 | current_link_up = 1; | |
3469 | goto out; | |
3470 | } | |
3471 | restart_autoneg: | |
3472 | if (workaround) | |
3473 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
3474 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); | |
3475 | udelay(5); | |
3476 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
3477 | ||
3478 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
3479 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
3480 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | | |
3481 | MAC_STATUS_SIGNAL_DET)) { | |
3482 | sg_dig_status = tr32(SG_DIG_STATUS); | |
3483 | mac_status = tr32(MAC_STATUS); | |
3484 | ||
3485 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && | |
3486 | (mac_status & MAC_STATUS_PCS_SYNCED)) { | |
3487 | u32 local_adv = 0, remote_adv = 0; | |
3488 | ||
3489 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
3490 | local_adv |= ADVERTISE_1000XPAUSE; | |
3491 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
3492 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
3493 | ||
3494 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) | |
3495 | remote_adv |= LPA_1000XPAUSE; | |
3496 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) | |
3497 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
3498 | ||
3499 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3500 | current_link_up = 1; | |
3501 | tp->serdes_counter = 0; | |
3502 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
3503 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { | |
3504 | if (tp->serdes_counter) | |
3505 | tp->serdes_counter--; | |
3506 | else { | |
3507 | if (workaround) { | |
3508 | u32 val = serdes_cfg; | |
3509 | ||
3510 | if (port_a) | |
3511 | val |= 0xc010000; | |
3512 | else | |
3513 | val |= 0x4010000; | |
3514 | ||
3515 | tw32_f(MAC_SERDES_CFG, val); | |
3516 | } | |
3517 | ||
3518 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
3519 | udelay(40); | |
3520 | ||
3521 | /* Link parallel detection - link is up */ | |
3522 | /* only if we have PCS_SYNC and not */ | |
3523 | /* receiving config code words */ | |
3524 | mac_status = tr32(MAC_STATUS); | |
3525 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
3526 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
3527 | tg3_setup_flow_control(tp, 0, 0); | |
3528 | current_link_up = 1; | |
3529 | tp->tg3_flags2 |= | |
3530 | TG3_FLG2_PARALLEL_DETECT; | |
3531 | tp->serdes_counter = | |
3532 | SERDES_PARALLEL_DET_TIMEOUT; | |
3533 | } else | |
3534 | goto restart_autoneg; | |
3535 | } | |
3536 | } | |
3537 | } else { | |
3538 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
3539 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
3540 | } | |
3541 | ||
3542 | out: | |
3543 | return current_link_up; | |
3544 | } | |
3545 | ||
3546 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
3547 | { | |
3548 | int current_link_up = 0; | |
3549 | ||
3550 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3551 | goto out; | |
3552 | ||
3553 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3554 | u32 txflags, rxflags; | |
3555 | int i; | |
3556 | ||
3557 | if (fiber_autoneg(tp, &txflags, &rxflags)) { | |
3558 | u32 local_adv = 0, remote_adv = 0; | |
3559 | ||
3560 | if (txflags & ANEG_CFG_PS1) | |
3561 | local_adv |= ADVERTISE_1000XPAUSE; | |
3562 | if (txflags & ANEG_CFG_PS2) | |
3563 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
3564 | ||
3565 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
3566 | remote_adv |= LPA_1000XPAUSE; | |
3567 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
3568 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
3569 | ||
3570 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3571 | ||
3572 | current_link_up = 1; | |
3573 | } | |
3574 | for (i = 0; i < 30; i++) { | |
3575 | udelay(20); | |
3576 | tw32_f(MAC_STATUS, | |
3577 | (MAC_STATUS_SYNC_CHANGED | | |
3578 | MAC_STATUS_CFG_CHANGED)); | |
3579 | udelay(40); | |
3580 | if ((tr32(MAC_STATUS) & | |
3581 | (MAC_STATUS_SYNC_CHANGED | | |
3582 | MAC_STATUS_CFG_CHANGED)) == 0) | |
3583 | break; | |
3584 | } | |
3585 | ||
3586 | mac_status = tr32(MAC_STATUS); | |
3587 | if (current_link_up == 0 && | |
3588 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
3589 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
3590 | current_link_up = 1; | |
3591 | } else { | |
3592 | tg3_setup_flow_control(tp, 0, 0); | |
3593 | ||
3594 | /* Forcing 1000FD link up. */ | |
3595 | current_link_up = 1; | |
3596 | ||
3597 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
3598 | udelay(40); | |
3599 | ||
3600 | tw32_f(MAC_MODE, tp->mac_mode); | |
3601 | udelay(40); | |
3602 | } | |
3603 | ||
3604 | out: | |
3605 | return current_link_up; | |
3606 | } | |
3607 | ||
3608 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
3609 | { | |
3610 | u32 orig_pause_cfg; | |
3611 | u16 orig_active_speed; | |
3612 | u8 orig_active_duplex; | |
3613 | u32 mac_status; | |
3614 | int current_link_up; | |
3615 | int i; | |
3616 | ||
3617 | orig_pause_cfg = tp->link_config.active_flowctrl; | |
3618 | orig_active_speed = tp->link_config.active_speed; | |
3619 | orig_active_duplex = tp->link_config.active_duplex; | |
3620 | ||
3621 | if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) && | |
3622 | netif_carrier_ok(tp->dev) && | |
3623 | (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) { | |
3624 | mac_status = tr32(MAC_STATUS); | |
3625 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
3626 | MAC_STATUS_SIGNAL_DET | | |
3627 | MAC_STATUS_CFG_CHANGED | | |
3628 | MAC_STATUS_RCVD_CFG); | |
3629 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
3630 | MAC_STATUS_SIGNAL_DET)) { | |
3631 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
3632 | MAC_STATUS_CFG_CHANGED)); | |
3633 | return 0; | |
3634 | } | |
3635 | } | |
3636 | ||
3637 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3638 | ||
3639 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
3640 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
3641 | tw32_f(MAC_MODE, tp->mac_mode); | |
3642 | udelay(40); | |
3643 | ||
3644 | if (tp->phy_id == PHY_ID_BCM8002) | |
3645 | tg3_init_bcm8002(tp); | |
3646 | ||
3647 | /* Enable link change event even when serdes polling. */ | |
3648 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3649 | udelay(40); | |
3650 | ||
3651 | current_link_up = 0; | |
3652 | mac_status = tr32(MAC_STATUS); | |
3653 | ||
3654 | if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) | |
3655 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); | |
3656 | else | |
3657 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
3658 | ||
3659 | tp->hw_status->status = | |
3660 | (SD_STATUS_UPDATED | | |
3661 | (tp->hw_status->status & ~SD_STATUS_LINK_CHG)); | |
3662 | ||
3663 | for (i = 0; i < 100; i++) { | |
3664 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
3665 | MAC_STATUS_CFG_CHANGED)); | |
3666 | udelay(5); | |
3667 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3668 | MAC_STATUS_CFG_CHANGED | | |
3669 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
3670 | break; | |
3671 | } | |
3672 | ||
3673 | mac_status = tr32(MAC_STATUS); | |
3674 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
3675 | current_link_up = 0; | |
3676 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
3677 | tp->serdes_counter == 0) { | |
3678 | tw32_f(MAC_MODE, (tp->mac_mode | | |
3679 | MAC_MODE_SEND_CONFIGS)); | |
3680 | udelay(1); | |
3681 | tw32_f(MAC_MODE, tp->mac_mode); | |
3682 | } | |
3683 | } | |
3684 | ||
3685 | if (current_link_up == 1) { | |
3686 | tp->link_config.active_speed = SPEED_1000; | |
3687 | tp->link_config.active_duplex = DUPLEX_FULL; | |
3688 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
3689 | LED_CTRL_LNKLED_OVERRIDE | | |
3690 | LED_CTRL_1000MBPS_ON)); | |
3691 | } else { | |
3692 | tp->link_config.active_speed = SPEED_INVALID; | |
3693 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
3694 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
3695 | LED_CTRL_LNKLED_OVERRIDE | | |
3696 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
3697 | } | |
3698 | ||
3699 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
3700 | if (current_link_up) | |
3701 | netif_carrier_on(tp->dev); | |
3702 | else | |
3703 | netif_carrier_off(tp->dev); | |
3704 | tg3_link_report(tp); | |
3705 | } else { | |
3706 | u32 now_pause_cfg = tp->link_config.active_flowctrl; | |
3707 | if (orig_pause_cfg != now_pause_cfg || | |
3708 | orig_active_speed != tp->link_config.active_speed || | |
3709 | orig_active_duplex != tp->link_config.active_duplex) | |
3710 | tg3_link_report(tp); | |
3711 | } | |
3712 | ||
3713 | return 0; | |
3714 | } | |
3715 | ||
3716 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) | |
3717 | { | |
3718 | int current_link_up, err = 0; | |
3719 | u32 bmsr, bmcr; | |
3720 | u16 current_speed; | |
3721 | u8 current_duplex; | |
3722 | u32 local_adv, remote_adv; | |
3723 | ||
3724 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
3725 | tw32_f(MAC_MODE, tp->mac_mode); | |
3726 | udelay(40); | |
3727 | ||
3728 | tw32(MAC_EVENT, 0); | |
3729 | ||
3730 | tw32_f(MAC_STATUS, | |
3731 | (MAC_STATUS_SYNC_CHANGED | | |
3732 | MAC_STATUS_CFG_CHANGED | | |
3733 | MAC_STATUS_MI_COMPLETION | | |
3734 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3735 | udelay(40); | |
3736 | ||
3737 | if (force_reset) | |
3738 | tg3_phy_reset(tp); | |
3739 | ||
3740 | current_link_up = 0; | |
3741 | current_speed = SPEED_INVALID; | |
3742 | current_duplex = DUPLEX_INVALID; | |
3743 | ||
3744 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
3745 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
3746 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
3747 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
3748 | bmsr |= BMSR_LSTATUS; | |
3749 | else | |
3750 | bmsr &= ~BMSR_LSTATUS; | |
3751 | } | |
3752 | ||
3753 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
3754 | ||
3755 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
3756 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) { | |
3757 | /* do nothing, just check for link up at the end */ | |
3758 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3759 | u32 adv, new_adv; | |
3760 | ||
3761 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
3762 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
3763 | ADVERTISE_1000XPAUSE | | |
3764 | ADVERTISE_1000XPSE_ASYM | | |
3765 | ADVERTISE_SLCT); | |
3766 | ||
3767 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3768 | ||
3769 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
3770 | new_adv |= ADVERTISE_1000XHALF; | |
3771 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
3772 | new_adv |= ADVERTISE_1000XFULL; | |
3773 | ||
3774 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
3775 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
3776 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
3777 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3778 | ||
3779 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3780 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; | |
3781 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
3782 | ||
3783 | return err; | |
3784 | } | |
3785 | } else { | |
3786 | u32 new_bmcr; | |
3787 | ||
3788 | bmcr &= ~BMCR_SPEED1000; | |
3789 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
3790 | ||
3791 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3792 | new_bmcr |= BMCR_FULLDPLX; | |
3793 | ||
3794 | if (new_bmcr != bmcr) { | |
3795 | /* BMCR_SPEED1000 is a reserved bit that needs | |
3796 | * to be set on write. | |
3797 | */ | |
3798 | new_bmcr |= BMCR_SPEED1000; | |
3799 | ||
3800 | /* Force a linkdown */ | |
3801 | if (netif_carrier_ok(tp->dev)) { | |
3802 | u32 adv; | |
3803 | ||
3804 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
3805 | adv &= ~(ADVERTISE_1000XFULL | | |
3806 | ADVERTISE_1000XHALF | | |
3807 | ADVERTISE_SLCT); | |
3808 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
3809 | tg3_writephy(tp, MII_BMCR, bmcr | | |
3810 | BMCR_ANRESTART | | |
3811 | BMCR_ANENABLE); | |
3812 | udelay(10); | |
3813 | netif_carrier_off(tp->dev); | |
3814 | } | |
3815 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
3816 | bmcr = new_bmcr; | |
3817 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
3818 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
3819 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
3820 | ASIC_REV_5714) { | |
3821 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
3822 | bmsr |= BMSR_LSTATUS; | |
3823 | else | |
3824 | bmsr &= ~BMSR_LSTATUS; | |
3825 | } | |
3826 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
3827 | } | |
3828 | } | |
3829 | ||
3830 | if (bmsr & BMSR_LSTATUS) { | |
3831 | current_speed = SPEED_1000; | |
3832 | current_link_up = 1; | |
3833 | if (bmcr & BMCR_FULLDPLX) | |
3834 | current_duplex = DUPLEX_FULL; | |
3835 | else | |
3836 | current_duplex = DUPLEX_HALF; | |
3837 | ||
3838 | local_adv = 0; | |
3839 | remote_adv = 0; | |
3840 | ||
3841 | if (bmcr & BMCR_ANENABLE) { | |
3842 | u32 common; | |
3843 | ||
3844 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
3845 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
3846 | common = local_adv & remote_adv; | |
3847 | if (common & (ADVERTISE_1000XHALF | | |
3848 | ADVERTISE_1000XFULL)) { | |
3849 | if (common & ADVERTISE_1000XFULL) | |
3850 | current_duplex = DUPLEX_FULL; | |
3851 | else | |
3852 | current_duplex = DUPLEX_HALF; | |
3853 | } | |
3854 | else | |
3855 | current_link_up = 0; | |
3856 | } | |
3857 | } | |
3858 | ||
3859 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) | |
3860 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3861 | ||
3862 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3863 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3864 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3865 | ||
3866 | tw32_f(MAC_MODE, tp->mac_mode); | |
3867 | udelay(40); | |
3868 | ||
3869 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3870 | ||
3871 | tp->link_config.active_speed = current_speed; | |
3872 | tp->link_config.active_duplex = current_duplex; | |
3873 | ||
3874 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
3875 | if (current_link_up) | |
3876 | netif_carrier_on(tp->dev); | |
3877 | else { | |
3878 | netif_carrier_off(tp->dev); | |
3879 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
3880 | } | |
3881 | tg3_link_report(tp); | |
3882 | } | |
3883 | return err; | |
3884 | } | |
3885 | ||
3886 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
3887 | { | |
3888 | if (tp->serdes_counter) { | |
3889 | /* Give autoneg time to complete. */ | |
3890 | tp->serdes_counter--; | |
3891 | return; | |
3892 | } | |
3893 | if (!netif_carrier_ok(tp->dev) && | |
3894 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
3895 | u32 bmcr; | |
3896 | ||
3897 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3898 | if (bmcr & BMCR_ANENABLE) { | |
3899 | u32 phy1, phy2; | |
3900 | ||
3901 | /* Select shadow register 0x1f */ | |
3902 | tg3_writephy(tp, 0x1c, 0x7c00); | |
3903 | tg3_readphy(tp, 0x1c, &phy1); | |
3904 | ||
3905 | /* Select expansion interrupt status register */ | |
3906 | tg3_writephy(tp, 0x17, 0x0f01); | |
3907 | tg3_readphy(tp, 0x15, &phy2); | |
3908 | tg3_readphy(tp, 0x15, &phy2); | |
3909 | ||
3910 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
3911 | /* We have signal detect and not receiving | |
3912 | * config code words, link is up by parallel | |
3913 | * detection. | |
3914 | */ | |
3915 | ||
3916 | bmcr &= ~BMCR_ANENABLE; | |
3917 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
3918 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3919 | tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT; | |
3920 | } | |
3921 | } | |
3922 | } | |
3923 | else if (netif_carrier_ok(tp->dev) && | |
3924 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
3925 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) { | |
3926 | u32 phy2; | |
3927 | ||
3928 | /* Select expansion interrupt status register */ | |
3929 | tg3_writephy(tp, 0x17, 0x0f01); | |
3930 | tg3_readphy(tp, 0x15, &phy2); | |
3931 | if (phy2 & 0x20) { | |
3932 | u32 bmcr; | |
3933 | ||
3934 | /* Config code words received, turn on autoneg. */ | |
3935 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3936 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
3937 | ||
3938 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
3939 | ||
3940 | } | |
3941 | } | |
3942 | } | |
3943 | ||
3944 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) | |
3945 | { | |
3946 | int err; | |
3947 | ||
3948 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
3949 | err = tg3_setup_fiber_phy(tp, force_reset); | |
3950 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
3951 | err = tg3_setup_fiber_mii_phy(tp, force_reset); | |
3952 | } else { | |
3953 | err = tg3_setup_copper_phy(tp, force_reset); | |
3954 | } | |
3955 | ||
3956 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { | |
3957 | u32 val, scale; | |
3958 | ||
3959 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
3960 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
3961 | scale = 65; | |
3962 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
3963 | scale = 6; | |
3964 | else | |
3965 | scale = 12; | |
3966 | ||
3967 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
3968 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
3969 | tw32(GRC_MISC_CFG, val); | |
3970 | } | |
3971 | ||
3972 | if (tp->link_config.active_speed == SPEED_1000 && | |
3973 | tp->link_config.active_duplex == DUPLEX_HALF) | |
3974 | tw32(MAC_TX_LENGTHS, | |
3975 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
3976 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
3977 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
3978 | else | |
3979 | tw32(MAC_TX_LENGTHS, | |
3980 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
3981 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
3982 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
3983 | ||
3984 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
3985 | if (netif_carrier_ok(tp->dev)) { | |
3986 | tw32(HOSTCC_STAT_COAL_TICKS, | |
3987 | tp->coal.stats_block_coalesce_usecs); | |
3988 | } else { | |
3989 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
3990 | } | |
3991 | } | |
3992 | ||
3993 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { | |
3994 | u32 val = tr32(PCIE_PWR_MGMT_THRESH); | |
3995 | if (!netif_carrier_ok(tp->dev)) | |
3996 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
3997 | tp->pwrmgmt_thresh; | |
3998 | else | |
3999 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4000 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4001 | } | |
4002 | ||
4003 | return err; | |
4004 | } | |
4005 | ||
4006 | /* This is called whenever we suspect that the system chipset is re- | |
4007 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4008 | * is bogus tx completions. We try to recover by setting the | |
4009 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4010 | * in the workqueue. | |
4011 | */ | |
4012 | static void tg3_tx_recover(struct tg3 *tp) | |
4013 | { | |
4014 | BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || | |
4015 | tp->write32_tx_mbox == tg3_write_indirect_mbox); | |
4016 | ||
4017 | printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-" | |
4018 | "mapped I/O cycles to the network device, attempting to " | |
4019 | "recover. Please report the problem to the driver maintainer " | |
4020 | "and include system chipset information.\n", tp->dev->name); | |
4021 | ||
4022 | spin_lock(&tp->lock); | |
4023 | tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; | |
4024 | spin_unlock(&tp->lock); | |
4025 | } | |
4026 | ||
4027 | static inline u32 tg3_tx_avail(struct tg3 *tp) | |
4028 | { | |
4029 | smp_mb(); | |
4030 | return (tp->tx_pending - | |
4031 | ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1))); | |
4032 | } | |
4033 | ||
4034 | /* Tigon3 never reports partial packet sends. So we do not | |
4035 | * need special logic to handle SKBs that have not had all | |
4036 | * of their frags sent yet, like SunGEM does. | |
4037 | */ | |
4038 | static void tg3_tx(struct tg3 *tp) | |
4039 | { | |
4040 | u32 hw_idx = tp->hw_status->idx[0].tx_consumer; | |
4041 | u32 sw_idx = tp->tx_cons; | |
4042 | ||
4043 | while (sw_idx != hw_idx) { | |
4044 | struct tx_ring_info *ri = &tp->tx_buffers[sw_idx]; | |
4045 | struct sk_buff *skb = ri->skb; | |
4046 | int i, tx_bug = 0; | |
4047 | ||
4048 | if (unlikely(skb == NULL)) { | |
4049 | tg3_tx_recover(tp); | |
4050 | return; | |
4051 | } | |
4052 | ||
4053 | skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE); | |
4054 | ||
4055 | ri->skb = NULL; | |
4056 | ||
4057 | sw_idx = NEXT_TX(sw_idx); | |
4058 | ||
4059 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
4060 | ri = &tp->tx_buffers[sw_idx]; | |
4061 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) | |
4062 | tx_bug = 1; | |
4063 | sw_idx = NEXT_TX(sw_idx); | |
4064 | } | |
4065 | ||
4066 | dev_kfree_skb(skb); | |
4067 | ||
4068 | if (unlikely(tx_bug)) { | |
4069 | tg3_tx_recover(tp); | |
4070 | return; | |
4071 | } | |
4072 | } | |
4073 | ||
4074 | tp->tx_cons = sw_idx; | |
4075 | ||
4076 | /* Need to make the tx_cons update visible to tg3_start_xmit() | |
4077 | * before checking for netif_queue_stopped(). Without the | |
4078 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4079 | * will miss it and cause the queue to be stopped forever. | |
4080 | */ | |
4081 | smp_mb(); | |
4082 | ||
4083 | if (unlikely(netif_queue_stopped(tp->dev) && | |
4084 | (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) { | |
4085 | netif_tx_lock(tp->dev); | |
4086 | if (netif_queue_stopped(tp->dev) && | |
4087 | (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))) | |
4088 | netif_wake_queue(tp->dev); | |
4089 | netif_tx_unlock(tp->dev); | |
4090 | } | |
4091 | } | |
4092 | ||
4093 | /* Returns size of skb allocated or < 0 on error. | |
4094 | * | |
4095 | * We only need to fill in the address because the other members | |
4096 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4097 | * | |
4098 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4099 | * posting buffers we only dirty the first cache line of the RX | |
4100 | * descriptor (containing the address). Whereas for the RX status | |
4101 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4102 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4103 | */ | |
4104 | static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key, | |
4105 | int src_idx, u32 dest_idx_unmasked) | |
4106 | { | |
4107 | struct tg3_rx_buffer_desc *desc; | |
4108 | struct ring_info *map, *src_map; | |
4109 | struct sk_buff *skb; | |
4110 | dma_addr_t mapping; | |
4111 | int skb_size, dest_idx; | |
4112 | ||
4113 | src_map = NULL; | |
4114 | switch (opaque_key) { | |
4115 | case RXD_OPAQUE_RING_STD: | |
4116 | dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE; | |
4117 | desc = &tp->rx_std[dest_idx]; | |
4118 | map = &tp->rx_std_buffers[dest_idx]; | |
4119 | if (src_idx >= 0) | |
4120 | src_map = &tp->rx_std_buffers[src_idx]; | |
4121 | skb_size = tp->rx_pkt_buf_sz; | |
4122 | break; | |
4123 | ||
4124 | case RXD_OPAQUE_RING_JUMBO: | |
4125 | dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE; | |
4126 | desc = &tp->rx_jumbo[dest_idx]; | |
4127 | map = &tp->rx_jumbo_buffers[dest_idx]; | |
4128 | if (src_idx >= 0) | |
4129 | src_map = &tp->rx_jumbo_buffers[src_idx]; | |
4130 | skb_size = RX_JUMBO_PKT_BUF_SZ; | |
4131 | break; | |
4132 | ||
4133 | default: | |
4134 | return -EINVAL; | |
4135 | } | |
4136 | ||
4137 | /* Do not overwrite any of the map or rp information | |
4138 | * until we are sure we can commit to a new buffer. | |
4139 | * | |
4140 | * Callers depend upon this behavior and assume that | |
4141 | * we leave everything unchanged if we fail. | |
4142 | */ | |
4143 | skb = netdev_alloc_skb(tp->dev, skb_size); | |
4144 | if (skb == NULL) | |
4145 | return -ENOMEM; | |
4146 | ||
4147 | skb_reserve(skb, tp->rx_offset); | |
4148 | ||
4149 | mapping = pci_map_single(tp->pdev, skb->data, | |
4150 | skb_size - tp->rx_offset, | |
4151 | PCI_DMA_FROMDEVICE); | |
4152 | ||
4153 | map->skb = skb; | |
4154 | pci_unmap_addr_set(map, mapping, mapping); | |
4155 | ||
4156 | if (src_map != NULL) | |
4157 | src_map->skb = NULL; | |
4158 | ||
4159 | desc->addr_hi = ((u64)mapping >> 32); | |
4160 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4161 | ||
4162 | return skb_size; | |
4163 | } | |
4164 | ||
4165 | /* We only need to move over in the address because the other | |
4166 | * members of the RX descriptor are invariant. See notes above | |
4167 | * tg3_alloc_rx_skb for full details. | |
4168 | */ | |
4169 | static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key, | |
4170 | int src_idx, u32 dest_idx_unmasked) | |
4171 | { | |
4172 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; | |
4173 | struct ring_info *src_map, *dest_map; | |
4174 | int dest_idx; | |
4175 | ||
4176 | switch (opaque_key) { | |
4177 | case RXD_OPAQUE_RING_STD: | |
4178 | dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE; | |
4179 | dest_desc = &tp->rx_std[dest_idx]; | |
4180 | dest_map = &tp->rx_std_buffers[dest_idx]; | |
4181 | src_desc = &tp->rx_std[src_idx]; | |
4182 | src_map = &tp->rx_std_buffers[src_idx]; | |
4183 | break; | |
4184 | ||
4185 | case RXD_OPAQUE_RING_JUMBO: | |
4186 | dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE; | |
4187 | dest_desc = &tp->rx_jumbo[dest_idx]; | |
4188 | dest_map = &tp->rx_jumbo_buffers[dest_idx]; | |
4189 | src_desc = &tp->rx_jumbo[src_idx]; | |
4190 | src_map = &tp->rx_jumbo_buffers[src_idx]; | |
4191 | break; | |
4192 | ||
4193 | default: | |
4194 | return; | |
4195 | } | |
4196 | ||
4197 | dest_map->skb = src_map->skb; | |
4198 | pci_unmap_addr_set(dest_map, mapping, | |
4199 | pci_unmap_addr(src_map, mapping)); | |
4200 | dest_desc->addr_hi = src_desc->addr_hi; | |
4201 | dest_desc->addr_lo = src_desc->addr_lo; | |
4202 | ||
4203 | src_map->skb = NULL; | |
4204 | } | |
4205 | ||
4206 | #if TG3_VLAN_TAG_USED | |
4207 | static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag) | |
4208 | { | |
4209 | return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag); | |
4210 | } | |
4211 | #endif | |
4212 | ||
4213 | /* The RX ring scheme is composed of multiple rings which post fresh | |
4214 | * buffers to the chip, and one special ring the chip uses to report | |
4215 | * status back to the host. | |
4216 | * | |
4217 | * The special ring reports the status of received packets to the | |
4218 | * host. The chip does not write into the original descriptor the | |
4219 | * RX buffer was obtained from. The chip simply takes the original | |
4220 | * descriptor as provided by the host, updates the status and length | |
4221 | * field, then writes this into the next status ring entry. | |
4222 | * | |
4223 | * Each ring the host uses to post buffers to the chip is described | |
4224 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4225 | * it is first placed into the on-chip ram. When the packet's length | |
4226 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4227 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4228 | * which is within the range of the new packet's length is chosen. | |
4229 | * | |
4230 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4231 | * sense from a cache coherency perspective. If only the host writes | |
4232 | * to the buffer post rings, and only the chip writes to the rx status | |
4233 | * rings, then cache lines never move beyond shared-modified state. | |
4234 | * If both the host and chip were to write into the same ring, cache line | |
4235 | * eviction could occur since both entities want it in an exclusive state. | |
4236 | */ | |
4237 | static int tg3_rx(struct tg3 *tp, int budget) | |
4238 | { | |
4239 | u32 work_mask, rx_std_posted = 0; | |
4240 | u32 sw_idx = tp->rx_rcb_ptr; | |
4241 | u16 hw_idx; | |
4242 | int received; | |
4243 | ||
4244 | hw_idx = tp->hw_status->idx[0].rx_producer; | |
4245 | /* | |
4246 | * We need to order the read of hw_idx and the read of | |
4247 | * the opaque cookie. | |
4248 | */ | |
4249 | rmb(); | |
4250 | work_mask = 0; | |
4251 | received = 0; | |
4252 | while (sw_idx != hw_idx && budget > 0) { | |
4253 | struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx]; | |
4254 | unsigned int len; | |
4255 | struct sk_buff *skb; | |
4256 | dma_addr_t dma_addr; | |
4257 | u32 opaque_key, desc_idx, *post_ptr; | |
4258 | ||
4259 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4260 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4261 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
4262 | dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], | |
4263 | mapping); | |
4264 | skb = tp->rx_std_buffers[desc_idx].skb; | |
4265 | post_ptr = &tp->rx_std_ptr; | |
4266 | rx_std_posted++; | |
4267 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
4268 | dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx], | |
4269 | mapping); | |
4270 | skb = tp->rx_jumbo_buffers[desc_idx].skb; | |
4271 | post_ptr = &tp->rx_jumbo_ptr; | |
4272 | } | |
4273 | else { | |
4274 | goto next_pkt_nopost; | |
4275 | } | |
4276 | ||
4277 | work_mask |= opaque_key; | |
4278 | ||
4279 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
4280 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
4281 | drop_it: | |
4282 | tg3_recycle_rx(tp, opaque_key, | |
4283 | desc_idx, *post_ptr); | |
4284 | drop_it_no_recycle: | |
4285 | /* Other statistics kept track of by card. */ | |
4286 | tp->net_stats.rx_dropped++; | |
4287 | goto next_pkt; | |
4288 | } | |
4289 | ||
4290 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - | |
4291 | ETH_FCS_LEN; | |
4292 | ||
4293 | if (len > RX_COPY_THRESHOLD | |
4294 | && tp->rx_offset == NET_IP_ALIGN | |
4295 | /* rx_offset will likely not equal NET_IP_ALIGN | |
4296 | * if this is a 5701 card running in PCI-X mode | |
4297 | * [see tg3_get_invariants()] | |
4298 | */ | |
4299 | ) { | |
4300 | int skb_size; | |
4301 | ||
4302 | skb_size = tg3_alloc_rx_skb(tp, opaque_key, | |
4303 | desc_idx, *post_ptr); | |
4304 | if (skb_size < 0) | |
4305 | goto drop_it; | |
4306 | ||
4307 | pci_unmap_single(tp->pdev, dma_addr, | |
4308 | skb_size - tp->rx_offset, | |
4309 | PCI_DMA_FROMDEVICE); | |
4310 | ||
4311 | skb_put(skb, len); | |
4312 | } else { | |
4313 | struct sk_buff *copy_skb; | |
4314 | ||
4315 | tg3_recycle_rx(tp, opaque_key, | |
4316 | desc_idx, *post_ptr); | |
4317 | ||
4318 | copy_skb = netdev_alloc_skb(tp->dev, | |
4319 | len + TG3_RAW_IP_ALIGN); | |
4320 | if (copy_skb == NULL) | |
4321 | goto drop_it_no_recycle; | |
4322 | ||
4323 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); | |
4324 | skb_put(copy_skb, len); | |
4325 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
4326 | skb_copy_from_linear_data(skb, copy_skb->data, len); | |
4327 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
4328 | ||
4329 | /* We'll reuse the original ring buffer. */ | |
4330 | skb = copy_skb; | |
4331 | } | |
4332 | ||
4333 | if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) && | |
4334 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
4335 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
4336 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
4337 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4338 | else | |
4339 | skb->ip_summed = CHECKSUM_NONE; | |
4340 | ||
4341 | skb->protocol = eth_type_trans(skb, tp->dev); | |
4342 | ||
4343 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
4344 | skb->protocol != htons(ETH_P_8021Q)) { | |
4345 | dev_kfree_skb(skb); | |
4346 | goto next_pkt; | |
4347 | } | |
4348 | ||
4349 | #if TG3_VLAN_TAG_USED | |
4350 | if (tp->vlgrp != NULL && | |
4351 | desc->type_flags & RXD_FLAG_VLAN) { | |
4352 | tg3_vlan_rx(tp, skb, | |
4353 | desc->err_vlan & RXD_VLAN_MASK); | |
4354 | } else | |
4355 | #endif | |
4356 | netif_receive_skb(skb); | |
4357 | ||
4358 | received++; | |
4359 | budget--; | |
4360 | ||
4361 | next_pkt: | |
4362 | (*post_ptr)++; | |
4363 | ||
4364 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
4365 | u32 idx = *post_ptr % TG3_RX_RING_SIZE; | |
4366 | ||
4367 | tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + | |
4368 | TG3_64BIT_REG_LOW, idx); | |
4369 | work_mask &= ~RXD_OPAQUE_RING_STD; | |
4370 | rx_std_posted = 0; | |
4371 | } | |
4372 | next_pkt_nopost: | |
4373 | sw_idx++; | |
4374 | sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1); | |
4375 | ||
4376 | /* Refresh hw_idx to see if there is new work */ | |
4377 | if (sw_idx == hw_idx) { | |
4378 | hw_idx = tp->hw_status->idx[0].rx_producer; | |
4379 | rmb(); | |
4380 | } | |
4381 | } | |
4382 | ||
4383 | /* ACK the status ring. */ | |
4384 | tp->rx_rcb_ptr = sw_idx; | |
4385 | tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx); | |
4386 | ||
4387 | /* Refill RX ring(s). */ | |
4388 | if (work_mask & RXD_OPAQUE_RING_STD) { | |
4389 | sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE; | |
4390 | tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, | |
4391 | sw_idx); | |
4392 | } | |
4393 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
4394 | sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE; | |
4395 | tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, | |
4396 | sw_idx); | |
4397 | } | |
4398 | mmiowb(); | |
4399 | ||
4400 | return received; | |
4401 | } | |
4402 | ||
4403 | static int tg3_poll_work(struct tg3 *tp, int work_done, int budget) | |
4404 | { | |
4405 | struct tg3_hw_status *sblk = tp->hw_status; | |
4406 | ||
4407 | /* handle link change and other phy events */ | |
4408 | if (!(tp->tg3_flags & | |
4409 | (TG3_FLAG_USE_LINKCHG_REG | | |
4410 | TG3_FLAG_POLL_SERDES))) { | |
4411 | if (sblk->status & SD_STATUS_LINK_CHG) { | |
4412 | sblk->status = SD_STATUS_UPDATED | | |
4413 | (sblk->status & ~SD_STATUS_LINK_CHG); | |
4414 | spin_lock(&tp->lock); | |
4415 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
4416 | tw32_f(MAC_STATUS, | |
4417 | (MAC_STATUS_SYNC_CHANGED | | |
4418 | MAC_STATUS_CFG_CHANGED | | |
4419 | MAC_STATUS_MI_COMPLETION | | |
4420 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4421 | udelay(40); | |
4422 | } else | |
4423 | tg3_setup_phy(tp, 0); | |
4424 | spin_unlock(&tp->lock); | |
4425 | } | |
4426 | } | |
4427 | ||
4428 | /* run TX completion thread */ | |
4429 | if (sblk->idx[0].tx_consumer != tp->tx_cons) { | |
4430 | tg3_tx(tp); | |
4431 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
4432 | return work_done; | |
4433 | } | |
4434 | ||
4435 | /* run RX thread, within the bounds set by NAPI. | |
4436 | * All RX "locking" is done by ensuring outside | |
4437 | * code synchronizes with tg3->napi.poll() | |
4438 | */ | |
4439 | if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) | |
4440 | work_done += tg3_rx(tp, budget - work_done); | |
4441 | ||
4442 | return work_done; | |
4443 | } | |
4444 | ||
4445 | static int tg3_poll(struct napi_struct *napi, int budget) | |
4446 | { | |
4447 | struct tg3 *tp = container_of(napi, struct tg3, napi); | |
4448 | int work_done = 0; | |
4449 | struct tg3_hw_status *sblk = tp->hw_status; | |
4450 | ||
4451 | while (1) { | |
4452 | work_done = tg3_poll_work(tp, work_done, budget); | |
4453 | ||
4454 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
4455 | goto tx_recovery; | |
4456 | ||
4457 | if (unlikely(work_done >= budget)) | |
4458 | break; | |
4459 | ||
4460 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
4461 | /* tp->last_tag is used in tg3_restart_ints() below | |
4462 | * to tell the hw how much work has been processed, | |
4463 | * so we must read it before checking for more work. | |
4464 | */ | |
4465 | tp->last_tag = sblk->status_tag; | |
4466 | rmb(); | |
4467 | } else | |
4468 | sblk->status &= ~SD_STATUS_UPDATED; | |
4469 | ||
4470 | if (likely(!tg3_has_work(tp))) { | |
4471 | napi_complete(napi); | |
4472 | tg3_restart_ints(tp); | |
4473 | break; | |
4474 | } | |
4475 | } | |
4476 | ||
4477 | return work_done; | |
4478 | ||
4479 | tx_recovery: | |
4480 | /* work_done is guaranteed to be less than budget. */ | |
4481 | napi_complete(napi); | |
4482 | schedule_work(&tp->reset_task); | |
4483 | return work_done; | |
4484 | } | |
4485 | ||
4486 | static void tg3_irq_quiesce(struct tg3 *tp) | |
4487 | { | |
4488 | BUG_ON(tp->irq_sync); | |
4489 | ||
4490 | tp->irq_sync = 1; | |
4491 | smp_mb(); | |
4492 | ||
4493 | synchronize_irq(tp->pdev->irq); | |
4494 | } | |
4495 | ||
4496 | static inline int tg3_irq_sync(struct tg3 *tp) | |
4497 | { | |
4498 | return tp->irq_sync; | |
4499 | } | |
4500 | ||
4501 | /* Fully shutdown all tg3 driver activity elsewhere in the system. | |
4502 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
4503 | * with as well. Most of the time, this is not necessary except when | |
4504 | * shutting down the device. | |
4505 | */ | |
4506 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
4507 | { | |
4508 | spin_lock_bh(&tp->lock); | |
4509 | if (irq_sync) | |
4510 | tg3_irq_quiesce(tp); | |
4511 | } | |
4512 | ||
4513 | static inline void tg3_full_unlock(struct tg3 *tp) | |
4514 | { | |
4515 | spin_unlock_bh(&tp->lock); | |
4516 | } | |
4517 | ||
4518 | /* One-shot MSI handler - Chip automatically disables interrupt | |
4519 | * after sending MSI so driver doesn't have to do it. | |
4520 | */ | |
4521 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) | |
4522 | { | |
4523 | struct net_device *dev = dev_id; | |
4524 | struct tg3 *tp = netdev_priv(dev); | |
4525 | ||
4526 | prefetch(tp->hw_status); | |
4527 | prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]); | |
4528 | ||
4529 | if (likely(!tg3_irq_sync(tp))) | |
4530 | napi_schedule(&tp->napi); | |
4531 | ||
4532 | return IRQ_HANDLED; | |
4533 | } | |
4534 | ||
4535 | /* MSI ISR - No need to check for interrupt sharing and no need to | |
4536 | * flush status block and interrupt mailbox. PCI ordering rules | |
4537 | * guarantee that MSI will arrive after the status block. | |
4538 | */ | |
4539 | static irqreturn_t tg3_msi(int irq, void *dev_id) | |
4540 | { | |
4541 | struct net_device *dev = dev_id; | |
4542 | struct tg3 *tp = netdev_priv(dev); | |
4543 | ||
4544 | prefetch(tp->hw_status); | |
4545 | prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]); | |
4546 | /* | |
4547 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
4548 | * chip-internal interrupt pending events. | |
4549 | * Writing non-zero to intr-mbox-0 additional tells the | |
4550 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
4551 | * event coalescing. | |
4552 | */ | |
4553 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
4554 | if (likely(!tg3_irq_sync(tp))) | |
4555 | napi_schedule(&tp->napi); | |
4556 | ||
4557 | return IRQ_RETVAL(1); | |
4558 | } | |
4559 | ||
4560 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) | |
4561 | { | |
4562 | struct net_device *dev = dev_id; | |
4563 | struct tg3 *tp = netdev_priv(dev); | |
4564 | struct tg3_hw_status *sblk = tp->hw_status; | |
4565 | unsigned int handled = 1; | |
4566 | ||
4567 | /* In INTx mode, it is possible for the interrupt to arrive at | |
4568 | * the CPU before the status block posted prior to the interrupt. | |
4569 | * Reading the PCI State register will confirm whether the | |
4570 | * interrupt is ours and will flush the status block. | |
4571 | */ | |
4572 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { | |
4573 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
4574 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
4575 | handled = 0; | |
4576 | goto out; | |
4577 | } | |
4578 | } | |
4579 | ||
4580 | /* | |
4581 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
4582 | * chip-internal interrupt pending events. | |
4583 | * Writing non-zero to intr-mbox-0 additional tells the | |
4584 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
4585 | * event coalescing. | |
4586 | * | |
4587 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
4588 | * spurious interrupts. The flush impacts performance but | |
4589 | * excessive spurious interrupts can be worse in some cases. | |
4590 | */ | |
4591 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
4592 | if (tg3_irq_sync(tp)) | |
4593 | goto out; | |
4594 | sblk->status &= ~SD_STATUS_UPDATED; | |
4595 | if (likely(tg3_has_work(tp))) { | |
4596 | prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]); | |
4597 | napi_schedule(&tp->napi); | |
4598 | } else { | |
4599 | /* No work, shared interrupt perhaps? re-enable | |
4600 | * interrupts, and flush that PCI write | |
4601 | */ | |
4602 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
4603 | 0x00000000); | |
4604 | } | |
4605 | out: | |
4606 | return IRQ_RETVAL(handled); | |
4607 | } | |
4608 | ||
4609 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) | |
4610 | { | |
4611 | struct net_device *dev = dev_id; | |
4612 | struct tg3 *tp = netdev_priv(dev); | |
4613 | struct tg3_hw_status *sblk = tp->hw_status; | |
4614 | unsigned int handled = 1; | |
4615 | ||
4616 | /* In INTx mode, it is possible for the interrupt to arrive at | |
4617 | * the CPU before the status block posted prior to the interrupt. | |
4618 | * Reading the PCI State register will confirm whether the | |
4619 | * interrupt is ours and will flush the status block. | |
4620 | */ | |
4621 | if (unlikely(sblk->status_tag == tp->last_tag)) { | |
4622 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
4623 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
4624 | handled = 0; | |
4625 | goto out; | |
4626 | } | |
4627 | } | |
4628 | ||
4629 | /* | |
4630 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
4631 | * chip-internal interrupt pending events. | |
4632 | * writing non-zero to intr-mbox-0 additional tells the | |
4633 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
4634 | * event coalescing. | |
4635 | * | |
4636 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
4637 | * spurious interrupts. The flush impacts performance but | |
4638 | * excessive spurious interrupts can be worse in some cases. | |
4639 | */ | |
4640 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
4641 | if (tg3_irq_sync(tp)) | |
4642 | goto out; | |
4643 | if (napi_schedule_prep(&tp->napi)) { | |
4644 | prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]); | |
4645 | /* Update last_tag to mark that this status has been | |
4646 | * seen. Because interrupt may be shared, we may be | |
4647 | * racing with tg3_poll(), so only update last_tag | |
4648 | * if tg3_poll() is not scheduled. | |
4649 | */ | |
4650 | tp->last_tag = sblk->status_tag; | |
4651 | __napi_schedule(&tp->napi); | |
4652 | } | |
4653 | out: | |
4654 | return IRQ_RETVAL(handled); | |
4655 | } | |
4656 | ||
4657 | /* ISR for interrupt test */ | |
4658 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) | |
4659 | { | |
4660 | struct net_device *dev = dev_id; | |
4661 | struct tg3 *tp = netdev_priv(dev); | |
4662 | struct tg3_hw_status *sblk = tp->hw_status; | |
4663 | ||
4664 | if ((sblk->status & SD_STATUS_UPDATED) || | |
4665 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
4666 | tg3_disable_ints(tp); | |
4667 | return IRQ_RETVAL(1); | |
4668 | } | |
4669 | return IRQ_RETVAL(0); | |
4670 | } | |
4671 | ||
4672 | static int tg3_init_hw(struct tg3 *, int); | |
4673 | static int tg3_halt(struct tg3 *, int, int); | |
4674 | ||
4675 | /* Restart hardware after configuration changes, self-test, etc. | |
4676 | * Invoked with tp->lock held. | |
4677 | */ | |
4678 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
4679 | __releases(tp->lock) | |
4680 | __acquires(tp->lock) | |
4681 | { | |
4682 | int err; | |
4683 | ||
4684 | err = tg3_init_hw(tp, reset_phy); | |
4685 | if (err) { | |
4686 | printk(KERN_ERR PFX "%s: Failed to re-initialize device, " | |
4687 | "aborting.\n", tp->dev->name); | |
4688 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
4689 | tg3_full_unlock(tp); | |
4690 | del_timer_sync(&tp->timer); | |
4691 | tp->irq_sync = 0; | |
4692 | napi_enable(&tp->napi); | |
4693 | dev_close(tp->dev); | |
4694 | tg3_full_lock(tp, 0); | |
4695 | } | |
4696 | return err; | |
4697 | } | |
4698 | ||
4699 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4700 | static void tg3_poll_controller(struct net_device *dev) | |
4701 | { | |
4702 | struct tg3 *tp = netdev_priv(dev); | |
4703 | ||
4704 | tg3_interrupt(tp->pdev->irq, dev); | |
4705 | } | |
4706 | #endif | |
4707 | ||
4708 | static void tg3_reset_task(struct work_struct *work) | |
4709 | { | |
4710 | struct tg3 *tp = container_of(work, struct tg3, reset_task); | |
4711 | int err; | |
4712 | unsigned int restart_timer; | |
4713 | ||
4714 | tg3_full_lock(tp, 0); | |
4715 | ||
4716 | if (!netif_running(tp->dev)) { | |
4717 | tg3_full_unlock(tp); | |
4718 | return; | |
4719 | } | |
4720 | ||
4721 | tg3_full_unlock(tp); | |
4722 | ||
4723 | tg3_phy_stop(tp); | |
4724 | ||
4725 | tg3_netif_stop(tp); | |
4726 | ||
4727 | tg3_full_lock(tp, 1); | |
4728 | ||
4729 | restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; | |
4730 | tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; | |
4731 | ||
4732 | if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) { | |
4733 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
4734 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
4735 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
4736 | tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; | |
4737 | } | |
4738 | ||
4739 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
4740 | err = tg3_init_hw(tp, 1); | |
4741 | if (err) | |
4742 | goto out; | |
4743 | ||
4744 | tg3_netif_start(tp); | |
4745 | ||
4746 | if (restart_timer) | |
4747 | mod_timer(&tp->timer, jiffies + 1); | |
4748 | ||
4749 | out: | |
4750 | tg3_full_unlock(tp); | |
4751 | ||
4752 | if (!err) | |
4753 | tg3_phy_start(tp); | |
4754 | } | |
4755 | ||
4756 | static void tg3_dump_short_state(struct tg3 *tp) | |
4757 | { | |
4758 | printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n", | |
4759 | tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS)); | |
4760 | printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n", | |
4761 | tr32(RDMAC_STATUS), tr32(WDMAC_STATUS)); | |
4762 | } | |
4763 | ||
4764 | static void tg3_tx_timeout(struct net_device *dev) | |
4765 | { | |
4766 | struct tg3 *tp = netdev_priv(dev); | |
4767 | ||
4768 | if (netif_msg_tx_err(tp)) { | |
4769 | printk(KERN_ERR PFX "%s: transmit timed out, resetting\n", | |
4770 | dev->name); | |
4771 | tg3_dump_short_state(tp); | |
4772 | } | |
4773 | ||
4774 | schedule_work(&tp->reset_task); | |
4775 | } | |
4776 | ||
4777 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ | |
4778 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
4779 | { | |
4780 | u32 base = (u32) mapping & 0xffffffff; | |
4781 | ||
4782 | return ((base > 0xffffdcc0) && | |
4783 | (base + len + 8 < base)); | |
4784 | } | |
4785 | ||
4786 | /* Test for DMA addresses > 40-bit */ | |
4787 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
4788 | int len) | |
4789 | { | |
4790 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
4791 | if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) | |
4792 | return (((u64) mapping + len) > DMA_40BIT_MASK); | |
4793 | return 0; | |
4794 | #else | |
4795 | return 0; | |
4796 | #endif | |
4797 | } | |
4798 | ||
4799 | static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32); | |
4800 | ||
4801 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ | |
4802 | static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb, | |
4803 | u32 last_plus_one, u32 *start, | |
4804 | u32 base_flags, u32 mss) | |
4805 | { | |
4806 | struct sk_buff *new_skb; | |
4807 | dma_addr_t new_addr = 0; | |
4808 | u32 entry = *start; | |
4809 | int i, ret = 0; | |
4810 | ||
4811 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
4812 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
4813 | else { | |
4814 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
4815 | ||
4816 | new_skb = skb_copy_expand(skb, | |
4817 | skb_headroom(skb) + more_headroom, | |
4818 | skb_tailroom(skb), GFP_ATOMIC); | |
4819 | } | |
4820 | ||
4821 | if (!new_skb) { | |
4822 | ret = -1; | |
4823 | } else { | |
4824 | /* New SKB is guaranteed to be linear. */ | |
4825 | entry = *start; | |
4826 | ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE); | |
4827 | new_addr = skb_shinfo(new_skb)->dma_maps[0]; | |
4828 | ||
4829 | /* Make sure new skb does not cross any 4G boundaries. | |
4830 | * Drop the packet if it does. | |
4831 | */ | |
4832 | if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) { | |
4833 | if (!ret) | |
4834 | skb_dma_unmap(&tp->pdev->dev, new_skb, | |
4835 | DMA_TO_DEVICE); | |
4836 | ret = -1; | |
4837 | dev_kfree_skb(new_skb); | |
4838 | new_skb = NULL; | |
4839 | } else { | |
4840 | tg3_set_txd(tp, entry, new_addr, new_skb->len, | |
4841 | base_flags, 1 | (mss << 1)); | |
4842 | *start = NEXT_TX(entry); | |
4843 | } | |
4844 | } | |
4845 | ||
4846 | /* Now clean up the sw ring entries. */ | |
4847 | i = 0; | |
4848 | while (entry != last_plus_one) { | |
4849 | if (i == 0) { | |
4850 | tp->tx_buffers[entry].skb = new_skb; | |
4851 | } else { | |
4852 | tp->tx_buffers[entry].skb = NULL; | |
4853 | } | |
4854 | entry = NEXT_TX(entry); | |
4855 | i++; | |
4856 | } | |
4857 | ||
4858 | skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE); | |
4859 | dev_kfree_skb(skb); | |
4860 | ||
4861 | return ret; | |
4862 | } | |
4863 | ||
4864 | static void tg3_set_txd(struct tg3 *tp, int entry, | |
4865 | dma_addr_t mapping, int len, u32 flags, | |
4866 | u32 mss_and_is_end) | |
4867 | { | |
4868 | struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry]; | |
4869 | int is_end = (mss_and_is_end & 0x1); | |
4870 | u32 mss = (mss_and_is_end >> 1); | |
4871 | u32 vlan_tag = 0; | |
4872 | ||
4873 | if (is_end) | |
4874 | flags |= TXD_FLAG_END; | |
4875 | if (flags & TXD_FLAG_VLAN) { | |
4876 | vlan_tag = flags >> 16; | |
4877 | flags &= 0xffff; | |
4878 | } | |
4879 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
4880 | ||
4881 | txd->addr_hi = ((u64) mapping >> 32); | |
4882 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
4883 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
4884 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
4885 | } | |
4886 | ||
4887 | /* hard_start_xmit for devices that don't have any bugs and | |
4888 | * support TG3_FLG2_HW_TSO_2 only. | |
4889 | */ | |
4890 | static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
4891 | { | |
4892 | struct tg3 *tp = netdev_priv(dev); | |
4893 | u32 len, entry, base_flags, mss; | |
4894 | struct skb_shared_info *sp; | |
4895 | dma_addr_t mapping; | |
4896 | ||
4897 | len = skb_headlen(skb); | |
4898 | ||
4899 | /* We are running in BH disabled context with netif_tx_lock | |
4900 | * and TX reclaim runs via tp->napi.poll inside of a software | |
4901 | * interrupt. Furthermore, IRQ processing runs lockless so we have | |
4902 | * no IRQ context deadlocks to worry about either. Rejoice! | |
4903 | */ | |
4904 | if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) { | |
4905 | if (!netif_queue_stopped(dev)) { | |
4906 | netif_stop_queue(dev); | |
4907 | ||
4908 | /* This is a hard error, log it. */ | |
4909 | printk(KERN_ERR PFX "%s: BUG! Tx Ring full when " | |
4910 | "queue awake!\n", dev->name); | |
4911 | } | |
4912 | return NETDEV_TX_BUSY; | |
4913 | } | |
4914 | ||
4915 | entry = tp->tx_prod; | |
4916 | base_flags = 0; | |
4917 | mss = 0; | |
4918 | if ((mss = skb_shinfo(skb)->gso_size) != 0) { | |
4919 | int tcp_opt_len, ip_tcp_len; | |
4920 | ||
4921 | if (skb_header_cloned(skb) && | |
4922 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
4923 | dev_kfree_skb(skb); | |
4924 | goto out_unlock; | |
4925 | } | |
4926 | ||
4927 | if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) | |
4928 | mss |= (skb_headlen(skb) - ETH_HLEN) << 9; | |
4929 | else { | |
4930 | struct iphdr *iph = ip_hdr(skb); | |
4931 | ||
4932 | tcp_opt_len = tcp_optlen(skb); | |
4933 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
4934 | ||
4935 | iph->check = 0; | |
4936 | iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); | |
4937 | mss |= (ip_tcp_len + tcp_opt_len) << 9; | |
4938 | } | |
4939 | ||
4940 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | | |
4941 | TXD_FLAG_CPU_POST_DMA); | |
4942 | ||
4943 | tcp_hdr(skb)->check = 0; | |
4944 | ||
4945 | } | |
4946 | else if (skb->ip_summed == CHECKSUM_PARTIAL) | |
4947 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
4948 | #if TG3_VLAN_TAG_USED | |
4949 | if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) | |
4950 | base_flags |= (TXD_FLAG_VLAN | | |
4951 | (vlan_tx_tag_get(skb) << 16)); | |
4952 | #endif | |
4953 | ||
4954 | if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) { | |
4955 | dev_kfree_skb(skb); | |
4956 | goto out_unlock; | |
4957 | } | |
4958 | ||
4959 | sp = skb_shinfo(skb); | |
4960 | ||
4961 | mapping = sp->dma_maps[0]; | |
4962 | ||
4963 | tp->tx_buffers[entry].skb = skb; | |
4964 | ||
4965 | tg3_set_txd(tp, entry, mapping, len, base_flags, | |
4966 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); | |
4967 | ||
4968 | entry = NEXT_TX(entry); | |
4969 | ||
4970 | /* Now loop through additional data fragments, and queue them. */ | |
4971 | if (skb_shinfo(skb)->nr_frags > 0) { | |
4972 | unsigned int i, last; | |
4973 | ||
4974 | last = skb_shinfo(skb)->nr_frags - 1; | |
4975 | for (i = 0; i <= last; i++) { | |
4976 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
4977 | ||
4978 | len = frag->size; | |
4979 | mapping = sp->dma_maps[i + 1]; | |
4980 | tp->tx_buffers[entry].skb = NULL; | |
4981 | ||
4982 | tg3_set_txd(tp, entry, mapping, len, | |
4983 | base_flags, (i == last) | (mss << 1)); | |
4984 | ||
4985 | entry = NEXT_TX(entry); | |
4986 | } | |
4987 | } | |
4988 | ||
4989 | /* Packets are ready, update Tx producer idx local and on card. */ | |
4990 | tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry); | |
4991 | ||
4992 | tp->tx_prod = entry; | |
4993 | if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) { | |
4994 | netif_stop_queue(dev); | |
4995 | if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)) | |
4996 | netif_wake_queue(tp->dev); | |
4997 | } | |
4998 | ||
4999 | out_unlock: | |
5000 | mmiowb(); | |
5001 | ||
5002 | dev->trans_start = jiffies; | |
5003 | ||
5004 | return NETDEV_TX_OK; | |
5005 | } | |
5006 | ||
5007 | static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *); | |
5008 | ||
5009 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5010 | * TSO header is greater than 80 bytes. | |
5011 | */ | |
5012 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5013 | { | |
5014 | struct sk_buff *segs, *nskb; | |
5015 | ||
5016 | /* Estimate the number of fragments in the worst case */ | |
5017 | if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) { | |
5018 | netif_stop_queue(tp->dev); | |
5019 | if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3)) | |
5020 | return NETDEV_TX_BUSY; | |
5021 | ||
5022 | netif_wake_queue(tp->dev); | |
5023 | } | |
5024 | ||
5025 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
5026 | if (IS_ERR(segs)) | |
5027 | goto tg3_tso_bug_end; | |
5028 | ||
5029 | do { | |
5030 | nskb = segs; | |
5031 | segs = segs->next; | |
5032 | nskb->next = NULL; | |
5033 | tg3_start_xmit_dma_bug(nskb, tp->dev); | |
5034 | } while (segs); | |
5035 | ||
5036 | tg3_tso_bug_end: | |
5037 | dev_kfree_skb(skb); | |
5038 | ||
5039 | return NETDEV_TX_OK; | |
5040 | } | |
5041 | ||
5042 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and | |
5043 | * support TG3_FLG2_HW_TSO_1 or firmware TSO only. | |
5044 | */ | |
5045 | static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev) | |
5046 | { | |
5047 | struct tg3 *tp = netdev_priv(dev); | |
5048 | u32 len, entry, base_flags, mss; | |
5049 | struct skb_shared_info *sp; | |
5050 | int would_hit_hwbug; | |
5051 | dma_addr_t mapping; | |
5052 | ||
5053 | len = skb_headlen(skb); | |
5054 | ||
5055 | /* We are running in BH disabled context with netif_tx_lock | |
5056 | * and TX reclaim runs via tp->napi.poll inside of a software | |
5057 | * interrupt. Furthermore, IRQ processing runs lockless so we have | |
5058 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5059 | */ | |
5060 | if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) { | |
5061 | if (!netif_queue_stopped(dev)) { | |
5062 | netif_stop_queue(dev); | |
5063 | ||
5064 | /* This is a hard error, log it. */ | |
5065 | printk(KERN_ERR PFX "%s: BUG! Tx Ring full when " | |
5066 | "queue awake!\n", dev->name); | |
5067 | } | |
5068 | return NETDEV_TX_BUSY; | |
5069 | } | |
5070 | ||
5071 | entry = tp->tx_prod; | |
5072 | base_flags = 0; | |
5073 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
5074 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
5075 | mss = 0; | |
5076 | if ((mss = skb_shinfo(skb)->gso_size) != 0) { | |
5077 | struct iphdr *iph; | |
5078 | int tcp_opt_len, ip_tcp_len, hdr_len; | |
5079 | ||
5080 | if (skb_header_cloned(skb) && | |
5081 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5082 | dev_kfree_skb(skb); | |
5083 | goto out_unlock; | |
5084 | } | |
5085 | ||
5086 | tcp_opt_len = tcp_optlen(skb); | |
5087 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
5088 | ||
5089 | hdr_len = ip_tcp_len + tcp_opt_len; | |
5090 | if (unlikely((ETH_HLEN + hdr_len) > 80) && | |
5091 | (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) | |
5092 | return (tg3_tso_bug(tp, skb)); | |
5093 | ||
5094 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | | |
5095 | TXD_FLAG_CPU_POST_DMA); | |
5096 | ||
5097 | iph = ip_hdr(skb); | |
5098 | iph->check = 0; | |
5099 | iph->tot_len = htons(mss + hdr_len); | |
5100 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { | |
5101 | tcp_hdr(skb)->check = 0; | |
5102 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; | |
5103 | } else | |
5104 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5105 | iph->daddr, 0, | |
5106 | IPPROTO_TCP, | |
5107 | 0); | |
5108 | ||
5109 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) || | |
5110 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) { | |
5111 | if (tcp_opt_len || iph->ihl > 5) { | |
5112 | int tsflags; | |
5113 | ||
5114 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); | |
5115 | mss |= (tsflags << 11); | |
5116 | } | |
5117 | } else { | |
5118 | if (tcp_opt_len || iph->ihl > 5) { | |
5119 | int tsflags; | |
5120 | ||
5121 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); | |
5122 | base_flags |= tsflags << 12; | |
5123 | } | |
5124 | } | |
5125 | } | |
5126 | #if TG3_VLAN_TAG_USED | |
5127 | if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) | |
5128 | base_flags |= (TXD_FLAG_VLAN | | |
5129 | (vlan_tx_tag_get(skb) << 16)); | |
5130 | #endif | |
5131 | ||
5132 | if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) { | |
5133 | dev_kfree_skb(skb); | |
5134 | goto out_unlock; | |
5135 | } | |
5136 | ||
5137 | sp = skb_shinfo(skb); | |
5138 | ||
5139 | mapping = sp->dma_maps[0]; | |
5140 | ||
5141 | tp->tx_buffers[entry].skb = skb; | |
5142 | ||
5143 | would_hit_hwbug = 0; | |
5144 | ||
5145 | if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG) | |
5146 | would_hit_hwbug = 1; | |
5147 | else if (tg3_4g_overflow_test(mapping, len)) | |
5148 | would_hit_hwbug = 1; | |
5149 | ||
5150 | tg3_set_txd(tp, entry, mapping, len, base_flags, | |
5151 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); | |
5152 | ||
5153 | entry = NEXT_TX(entry); | |
5154 | ||
5155 | /* Now loop through additional data fragments, and queue them. */ | |
5156 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5157 | unsigned int i, last; | |
5158 | ||
5159 | last = skb_shinfo(skb)->nr_frags - 1; | |
5160 | for (i = 0; i <= last; i++) { | |
5161 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5162 | ||
5163 | len = frag->size; | |
5164 | mapping = sp->dma_maps[i + 1]; | |
5165 | ||
5166 | tp->tx_buffers[entry].skb = NULL; | |
5167 | ||
5168 | if (tg3_4g_overflow_test(mapping, len)) | |
5169 | would_hit_hwbug = 1; | |
5170 | ||
5171 | if (tg3_40bit_overflow_test(tp, mapping, len)) | |
5172 | would_hit_hwbug = 1; | |
5173 | ||
5174 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
5175 | tg3_set_txd(tp, entry, mapping, len, | |
5176 | base_flags, (i == last)|(mss << 1)); | |
5177 | else | |
5178 | tg3_set_txd(tp, entry, mapping, len, | |
5179 | base_flags, (i == last)); | |
5180 | ||
5181 | entry = NEXT_TX(entry); | |
5182 | } | |
5183 | } | |
5184 | ||
5185 | if (would_hit_hwbug) { | |
5186 | u32 last_plus_one = entry; | |
5187 | u32 start; | |
5188 | ||
5189 | start = entry - 1 - skb_shinfo(skb)->nr_frags; | |
5190 | start &= (TG3_TX_RING_SIZE - 1); | |
5191 | ||
5192 | /* If the workaround fails due to memory/mapping | |
5193 | * failure, silently drop this packet. | |
5194 | */ | |
5195 | if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one, | |
5196 | &start, base_flags, mss)) | |
5197 | goto out_unlock; | |
5198 | ||
5199 | entry = start; | |
5200 | } | |
5201 | ||
5202 | /* Packets are ready, update Tx producer idx local and on card. */ | |
5203 | tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry); | |
5204 | ||
5205 | tp->tx_prod = entry; | |
5206 | if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) { | |
5207 | netif_stop_queue(dev); | |
5208 | if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)) | |
5209 | netif_wake_queue(tp->dev); | |
5210 | } | |
5211 | ||
5212 | out_unlock: | |
5213 | mmiowb(); | |
5214 | ||
5215 | dev->trans_start = jiffies; | |
5216 | ||
5217 | return NETDEV_TX_OK; | |
5218 | } | |
5219 | ||
5220 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, | |
5221 | int new_mtu) | |
5222 | { | |
5223 | dev->mtu = new_mtu; | |
5224 | ||
5225 | if (new_mtu > ETH_DATA_LEN) { | |
5226 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
5227 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; | |
5228 | ethtool_op_set_tso(dev, 0); | |
5229 | } | |
5230 | else | |
5231 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; | |
5232 | } else { | |
5233 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
5234 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; | |
5235 | tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE; | |
5236 | } | |
5237 | } | |
5238 | ||
5239 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
5240 | { | |
5241 | struct tg3 *tp = netdev_priv(dev); | |
5242 | int err; | |
5243 | ||
5244 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
5245 | return -EINVAL; | |
5246 | ||
5247 | if (!netif_running(dev)) { | |
5248 | /* We'll just catch it later when the | |
5249 | * device is up'd. | |
5250 | */ | |
5251 | tg3_set_mtu(dev, tp, new_mtu); | |
5252 | return 0; | |
5253 | } | |
5254 | ||
5255 | tg3_phy_stop(tp); | |
5256 | ||
5257 | tg3_netif_stop(tp); | |
5258 | ||
5259 | tg3_full_lock(tp, 1); | |
5260 | ||
5261 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
5262 | ||
5263 | tg3_set_mtu(dev, tp, new_mtu); | |
5264 | ||
5265 | err = tg3_restart_hw(tp, 0); | |
5266 | ||
5267 | if (!err) | |
5268 | tg3_netif_start(tp); | |
5269 | ||
5270 | tg3_full_unlock(tp); | |
5271 | ||
5272 | if (!err) | |
5273 | tg3_phy_start(tp); | |
5274 | ||
5275 | return err; | |
5276 | } | |
5277 | ||
5278 | /* Free up pending packets in all rx/tx rings. | |
5279 | * | |
5280 | * The chip has been shut down and the driver detached from | |
5281 | * the networking, so no interrupts or new tx packets will | |
5282 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
5283 | * in an interrupt context and thus may sleep. | |
5284 | */ | |
5285 | static void tg3_free_rings(struct tg3 *tp) | |
5286 | { | |
5287 | struct ring_info *rxp; | |
5288 | int i; | |
5289 | ||
5290 | for (i = 0; i < TG3_RX_RING_SIZE; i++) { | |
5291 | rxp = &tp->rx_std_buffers[i]; | |
5292 | ||
5293 | if (rxp->skb == NULL) | |
5294 | continue; | |
5295 | pci_unmap_single(tp->pdev, | |
5296 | pci_unmap_addr(rxp, mapping), | |
5297 | tp->rx_pkt_buf_sz - tp->rx_offset, | |
5298 | PCI_DMA_FROMDEVICE); | |
5299 | dev_kfree_skb_any(rxp->skb); | |
5300 | rxp->skb = NULL; | |
5301 | } | |
5302 | ||
5303 | for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { | |
5304 | rxp = &tp->rx_jumbo_buffers[i]; | |
5305 | ||
5306 | if (rxp->skb == NULL) | |
5307 | continue; | |
5308 | pci_unmap_single(tp->pdev, | |
5309 | pci_unmap_addr(rxp, mapping), | |
5310 | RX_JUMBO_PKT_BUF_SZ - tp->rx_offset, | |
5311 | PCI_DMA_FROMDEVICE); | |
5312 | dev_kfree_skb_any(rxp->skb); | |
5313 | rxp->skb = NULL; | |
5314 | } | |
5315 | ||
5316 | for (i = 0; i < TG3_TX_RING_SIZE; ) { | |
5317 | struct tx_ring_info *txp; | |
5318 | struct sk_buff *skb; | |
5319 | ||
5320 | txp = &tp->tx_buffers[i]; | |
5321 | skb = txp->skb; | |
5322 | ||
5323 | if (skb == NULL) { | |
5324 | i++; | |
5325 | continue; | |
5326 | } | |
5327 | ||
5328 | skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE); | |
5329 | ||
5330 | txp->skb = NULL; | |
5331 | ||
5332 | i += skb_shinfo(skb)->nr_frags + 1; | |
5333 | ||
5334 | dev_kfree_skb_any(skb); | |
5335 | } | |
5336 | } | |
5337 | ||
5338 | /* Initialize tx/rx rings for packet processing. | |
5339 | * | |
5340 | * The chip has been shut down and the driver detached from | |
5341 | * the networking, so no interrupts or new tx packets will | |
5342 | * end up in the driver. tp->{tx,}lock are held and thus | |
5343 | * we may not sleep. | |
5344 | */ | |
5345 | static int tg3_init_rings(struct tg3 *tp) | |
5346 | { | |
5347 | u32 i; | |
5348 | ||
5349 | /* Free up all the SKBs. */ | |
5350 | tg3_free_rings(tp); | |
5351 | ||
5352 | /* Zero out all descriptors. */ | |
5353 | memset(tp->rx_std, 0, TG3_RX_RING_BYTES); | |
5354 | memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES); | |
5355 | memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
5356 | memset(tp->tx_ring, 0, TG3_TX_RING_BYTES); | |
5357 | ||
5358 | tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ; | |
5359 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && | |
5360 | (tp->dev->mtu > ETH_DATA_LEN)) | |
5361 | tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ; | |
5362 | ||
5363 | /* Initialize invariants of the rings, we only set this | |
5364 | * stuff once. This works because the card does not | |
5365 | * write into the rx buffer posting rings. | |
5366 | */ | |
5367 | for (i = 0; i < TG3_RX_RING_SIZE; i++) { | |
5368 | struct tg3_rx_buffer_desc *rxd; | |
5369 | ||
5370 | rxd = &tp->rx_std[i]; | |
5371 | rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64) | |
5372 | << RXD_LEN_SHIFT; | |
5373 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); | |
5374 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
5375 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
5376 | } | |
5377 | ||
5378 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { | |
5379 | for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { | |
5380 | struct tg3_rx_buffer_desc *rxd; | |
5381 | ||
5382 | rxd = &tp->rx_jumbo[i]; | |
5383 | rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64) | |
5384 | << RXD_LEN_SHIFT; | |
5385 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
5386 | RXD_FLAG_JUMBO; | |
5387 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
5388 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
5389 | } | |
5390 | } | |
5391 | ||
5392 | /* Now allocate fresh SKBs for each rx ring. */ | |
5393 | for (i = 0; i < tp->rx_pending; i++) { | |
5394 | if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) { | |
5395 | printk(KERN_WARNING PFX | |
5396 | "%s: Using a smaller RX standard ring, " | |
5397 | "only %d out of %d buffers were allocated " | |
5398 | "successfully.\n", | |
5399 | tp->dev->name, i, tp->rx_pending); | |
5400 | if (i == 0) | |
5401 | return -ENOMEM; | |
5402 | tp->rx_pending = i; | |
5403 | break; | |
5404 | } | |
5405 | } | |
5406 | ||
5407 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { | |
5408 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
5409 | if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO, | |
5410 | -1, i) < 0) { | |
5411 | printk(KERN_WARNING PFX | |
5412 | "%s: Using a smaller RX jumbo ring, " | |
5413 | "only %d out of %d buffers were " | |
5414 | "allocated successfully.\n", | |
5415 | tp->dev->name, i, tp->rx_jumbo_pending); | |
5416 | if (i == 0) { | |
5417 | tg3_free_rings(tp); | |
5418 | return -ENOMEM; | |
5419 | } | |
5420 | tp->rx_jumbo_pending = i; | |
5421 | break; | |
5422 | } | |
5423 | } | |
5424 | } | |
5425 | return 0; | |
5426 | } | |
5427 | ||
5428 | /* | |
5429 | * Must not be invoked with interrupt sources disabled and | |
5430 | * the hardware shutdown down. | |
5431 | */ | |
5432 | static void tg3_free_consistent(struct tg3 *tp) | |
5433 | { | |
5434 | kfree(tp->rx_std_buffers); | |
5435 | tp->rx_std_buffers = NULL; | |
5436 | if (tp->rx_std) { | |
5437 | pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES, | |
5438 | tp->rx_std, tp->rx_std_mapping); | |
5439 | tp->rx_std = NULL; | |
5440 | } | |
5441 | if (tp->rx_jumbo) { | |
5442 | pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES, | |
5443 | tp->rx_jumbo, tp->rx_jumbo_mapping); | |
5444 | tp->rx_jumbo = NULL; | |
5445 | } | |
5446 | if (tp->rx_rcb) { | |
5447 | pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp), | |
5448 | tp->rx_rcb, tp->rx_rcb_mapping); | |
5449 | tp->rx_rcb = NULL; | |
5450 | } | |
5451 | if (tp->tx_ring) { | |
5452 | pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES, | |
5453 | tp->tx_ring, tp->tx_desc_mapping); | |
5454 | tp->tx_ring = NULL; | |
5455 | } | |
5456 | if (tp->hw_status) { | |
5457 | pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE, | |
5458 | tp->hw_status, tp->status_mapping); | |
5459 | tp->hw_status = NULL; | |
5460 | } | |
5461 | if (tp->hw_stats) { | |
5462 | pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats), | |
5463 | tp->hw_stats, tp->stats_mapping); | |
5464 | tp->hw_stats = NULL; | |
5465 | } | |
5466 | } | |
5467 | ||
5468 | /* | |
5469 | * Must not be invoked with interrupt sources disabled and | |
5470 | * the hardware shutdown down. Can sleep. | |
5471 | */ | |
5472 | static int tg3_alloc_consistent(struct tg3 *tp) | |
5473 | { | |
5474 | tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) * | |
5475 | (TG3_RX_RING_SIZE + | |
5476 | TG3_RX_JUMBO_RING_SIZE)) + | |
5477 | (sizeof(struct tx_ring_info) * | |
5478 | TG3_TX_RING_SIZE), | |
5479 | GFP_KERNEL); | |
5480 | if (!tp->rx_std_buffers) | |
5481 | return -ENOMEM; | |
5482 | ||
5483 | tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE]; | |
5484 | tp->tx_buffers = (struct tx_ring_info *) | |
5485 | &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE]; | |
5486 | ||
5487 | tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES, | |
5488 | &tp->rx_std_mapping); | |
5489 | if (!tp->rx_std) | |
5490 | goto err_out; | |
5491 | ||
5492 | tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES, | |
5493 | &tp->rx_jumbo_mapping); | |
5494 | ||
5495 | if (!tp->rx_jumbo) | |
5496 | goto err_out; | |
5497 | ||
5498 | tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp), | |
5499 | &tp->rx_rcb_mapping); | |
5500 | if (!tp->rx_rcb) | |
5501 | goto err_out; | |
5502 | ||
5503 | tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES, | |
5504 | &tp->tx_desc_mapping); | |
5505 | if (!tp->tx_ring) | |
5506 | goto err_out; | |
5507 | ||
5508 | tp->hw_status = pci_alloc_consistent(tp->pdev, | |
5509 | TG3_HW_STATUS_SIZE, | |
5510 | &tp->status_mapping); | |
5511 | if (!tp->hw_status) | |
5512 | goto err_out; | |
5513 | ||
5514 | tp->hw_stats = pci_alloc_consistent(tp->pdev, | |
5515 | sizeof(struct tg3_hw_stats), | |
5516 | &tp->stats_mapping); | |
5517 | if (!tp->hw_stats) | |
5518 | goto err_out; | |
5519 | ||
5520 | memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE); | |
5521 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
5522 | ||
5523 | return 0; | |
5524 | ||
5525 | err_out: | |
5526 | tg3_free_consistent(tp); | |
5527 | return -ENOMEM; | |
5528 | } | |
5529 | ||
5530 | #define MAX_WAIT_CNT 1000 | |
5531 | ||
5532 | /* To stop a block, clear the enable bit and poll till it | |
5533 | * clears. tp->lock is held. | |
5534 | */ | |
5535 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) | |
5536 | { | |
5537 | unsigned int i; | |
5538 | u32 val; | |
5539 | ||
5540 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
5541 | switch (ofs) { | |
5542 | case RCVLSC_MODE: | |
5543 | case DMAC_MODE: | |
5544 | case MBFREE_MODE: | |
5545 | case BUFMGR_MODE: | |
5546 | case MEMARB_MODE: | |
5547 | /* We can't enable/disable these bits of the | |
5548 | * 5705/5750, just say success. | |
5549 | */ | |
5550 | return 0; | |
5551 | ||
5552 | default: | |
5553 | break; | |
5554 | } | |
5555 | } | |
5556 | ||
5557 | val = tr32(ofs); | |
5558 | val &= ~enable_bit; | |
5559 | tw32_f(ofs, val); | |
5560 | ||
5561 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
5562 | udelay(100); | |
5563 | val = tr32(ofs); | |
5564 | if ((val & enable_bit) == 0) | |
5565 | break; | |
5566 | } | |
5567 | ||
5568 | if (i == MAX_WAIT_CNT && !silent) { | |
5569 | printk(KERN_ERR PFX "tg3_stop_block timed out, " | |
5570 | "ofs=%lx enable_bit=%x\n", | |
5571 | ofs, enable_bit); | |
5572 | return -ENODEV; | |
5573 | } | |
5574 | ||
5575 | return 0; | |
5576 | } | |
5577 | ||
5578 | /* tp->lock is held. */ | |
5579 | static int tg3_abort_hw(struct tg3 *tp, int silent) | |
5580 | { | |
5581 | int i, err; | |
5582 | ||
5583 | tg3_disable_ints(tp); | |
5584 | ||
5585 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
5586 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
5587 | udelay(10); | |
5588 | ||
5589 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); | |
5590 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
5591 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
5592 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
5593 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
5594 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
5595 | ||
5596 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
5597 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
5598 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
5599 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
5600 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
5601 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
5602 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
5603 | ||
5604 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
5605 | tw32_f(MAC_MODE, tp->mac_mode); | |
5606 | udelay(40); | |
5607 | ||
5608 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
5609 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
5610 | ||
5611 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
5612 | udelay(100); | |
5613 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
5614 | break; | |
5615 | } | |
5616 | if (i >= MAX_WAIT_CNT) { | |
5617 | printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, " | |
5618 | "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n", | |
5619 | tp->dev->name, tr32(MAC_TX_MODE)); | |
5620 | err |= -ENODEV; | |
5621 | } | |
5622 | ||
5623 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); | |
5624 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); | |
5625 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
5626 | ||
5627 | tw32(FTQ_RESET, 0xffffffff); | |
5628 | tw32(FTQ_RESET, 0x00000000); | |
5629 | ||
5630 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); | |
5631 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
5632 | ||
5633 | if (tp->hw_status) | |
5634 | memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE); | |
5635 | if (tp->hw_stats) | |
5636 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
5637 | ||
5638 | return err; | |
5639 | } | |
5640 | ||
5641 | /* tp->lock is held. */ | |
5642 | static int tg3_nvram_lock(struct tg3 *tp) | |
5643 | { | |
5644 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
5645 | int i; | |
5646 | ||
5647 | if (tp->nvram_lock_cnt == 0) { | |
5648 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
5649 | for (i = 0; i < 8000; i++) { | |
5650 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
5651 | break; | |
5652 | udelay(20); | |
5653 | } | |
5654 | if (i == 8000) { | |
5655 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
5656 | return -ENODEV; | |
5657 | } | |
5658 | } | |
5659 | tp->nvram_lock_cnt++; | |
5660 | } | |
5661 | return 0; | |
5662 | } | |
5663 | ||
5664 | /* tp->lock is held. */ | |
5665 | static void tg3_nvram_unlock(struct tg3 *tp) | |
5666 | { | |
5667 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
5668 | if (tp->nvram_lock_cnt > 0) | |
5669 | tp->nvram_lock_cnt--; | |
5670 | if (tp->nvram_lock_cnt == 0) | |
5671 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
5672 | } | |
5673 | } | |
5674 | ||
5675 | /* tp->lock is held. */ | |
5676 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
5677 | { | |
5678 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
5679 | !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { | |
5680 | u32 nvaccess = tr32(NVRAM_ACCESS); | |
5681 | ||
5682 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
5683 | } | |
5684 | } | |
5685 | ||
5686 | /* tp->lock is held. */ | |
5687 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
5688 | { | |
5689 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
5690 | !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { | |
5691 | u32 nvaccess = tr32(NVRAM_ACCESS); | |
5692 | ||
5693 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
5694 | } | |
5695 | } | |
5696 | ||
5697 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) | |
5698 | { | |
5699 | int i; | |
5700 | u32 apedata; | |
5701 | ||
5702 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
5703 | if (apedata != APE_SEG_SIG_MAGIC) | |
5704 | return; | |
5705 | ||
5706 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
5707 | if (!(apedata & APE_FW_STATUS_READY)) | |
5708 | return; | |
5709 | ||
5710 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
5711 | for (i = 0; i < 10; i++) { | |
5712 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
5713 | return; | |
5714 | ||
5715 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
5716 | ||
5717 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
5718 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
5719 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
5720 | ||
5721 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
5722 | ||
5723 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
5724 | break; | |
5725 | ||
5726 | udelay(100); | |
5727 | } | |
5728 | ||
5729 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
5730 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
5731 | } | |
5732 | ||
5733 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
5734 | { | |
5735 | u32 event; | |
5736 | u32 apedata; | |
5737 | ||
5738 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
5739 | return; | |
5740 | ||
5741 | switch (kind) { | |
5742 | case RESET_KIND_INIT: | |
5743 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
5744 | APE_HOST_SEG_SIG_MAGIC); | |
5745 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
5746 | APE_HOST_SEG_LEN_MAGIC); | |
5747 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
5748 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
5749 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
5750 | APE_HOST_DRIVER_ID_MAGIC); | |
5751 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
5752 | APE_HOST_BEHAV_NO_PHYLOCK); | |
5753 | ||
5754 | event = APE_EVENT_STATUS_STATE_START; | |
5755 | break; | |
5756 | case RESET_KIND_SHUTDOWN: | |
5757 | /* With the interface we are currently using, | |
5758 | * APE does not track driver state. Wiping | |
5759 | * out the HOST SEGMENT SIGNATURE forces | |
5760 | * the APE to assume OS absent status. | |
5761 | */ | |
5762 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
5763 | ||
5764 | event = APE_EVENT_STATUS_STATE_UNLOAD; | |
5765 | break; | |
5766 | case RESET_KIND_SUSPEND: | |
5767 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
5768 | break; | |
5769 | default: | |
5770 | return; | |
5771 | } | |
5772 | ||
5773 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
5774 | ||
5775 | tg3_ape_send_event(tp, event); | |
5776 | } | |
5777 | ||
5778 | /* tp->lock is held. */ | |
5779 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
5780 | { | |
5781 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, | |
5782 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
5783 | ||
5784 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
5785 | switch (kind) { | |
5786 | case RESET_KIND_INIT: | |
5787 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
5788 | DRV_STATE_START); | |
5789 | break; | |
5790 | ||
5791 | case RESET_KIND_SHUTDOWN: | |
5792 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
5793 | DRV_STATE_UNLOAD); | |
5794 | break; | |
5795 | ||
5796 | case RESET_KIND_SUSPEND: | |
5797 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
5798 | DRV_STATE_SUSPEND); | |
5799 | break; | |
5800 | ||
5801 | default: | |
5802 | break; | |
5803 | } | |
5804 | } | |
5805 | ||
5806 | if (kind == RESET_KIND_INIT || | |
5807 | kind == RESET_KIND_SUSPEND) | |
5808 | tg3_ape_driver_state_change(tp, kind); | |
5809 | } | |
5810 | ||
5811 | /* tp->lock is held. */ | |
5812 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
5813 | { | |
5814 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
5815 | switch (kind) { | |
5816 | case RESET_KIND_INIT: | |
5817 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
5818 | DRV_STATE_START_DONE); | |
5819 | break; | |
5820 | ||
5821 | case RESET_KIND_SHUTDOWN: | |
5822 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
5823 | DRV_STATE_UNLOAD_DONE); | |
5824 | break; | |
5825 | ||
5826 | default: | |
5827 | break; | |
5828 | } | |
5829 | } | |
5830 | ||
5831 | if (kind == RESET_KIND_SHUTDOWN) | |
5832 | tg3_ape_driver_state_change(tp, kind); | |
5833 | } | |
5834 | ||
5835 | /* tp->lock is held. */ | |
5836 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
5837 | { | |
5838 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
5839 | switch (kind) { | |
5840 | case RESET_KIND_INIT: | |
5841 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
5842 | DRV_STATE_START); | |
5843 | break; | |
5844 | ||
5845 | case RESET_KIND_SHUTDOWN: | |
5846 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
5847 | DRV_STATE_UNLOAD); | |
5848 | break; | |
5849 | ||
5850 | case RESET_KIND_SUSPEND: | |
5851 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
5852 | DRV_STATE_SUSPEND); | |
5853 | break; | |
5854 | ||
5855 | default: | |
5856 | break; | |
5857 | } | |
5858 | } | |
5859 | } | |
5860 | ||
5861 | static int tg3_poll_fw(struct tg3 *tp) | |
5862 | { | |
5863 | int i; | |
5864 | u32 val; | |
5865 | ||
5866 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
5867 | /* Wait up to 20ms for init done. */ | |
5868 | for (i = 0; i < 200; i++) { | |
5869 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) | |
5870 | return 0; | |
5871 | udelay(100); | |
5872 | } | |
5873 | return -ENODEV; | |
5874 | } | |
5875 | ||
5876 | /* Wait for firmware initialization to complete. */ | |
5877 | for (i = 0; i < 100000; i++) { | |
5878 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
5879 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
5880 | break; | |
5881 | udelay(10); | |
5882 | } | |
5883 | ||
5884 | /* Chip might not be fitted with firmware. Some Sun onboard | |
5885 | * parts are configured like that. So don't signal the timeout | |
5886 | * of the above loop as an error, but do report the lack of | |
5887 | * running firmware once. | |
5888 | */ | |
5889 | if (i >= 100000 && | |
5890 | !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) { | |
5891 | tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED; | |
5892 | ||
5893 | printk(KERN_INFO PFX "%s: No firmware running.\n", | |
5894 | tp->dev->name); | |
5895 | } | |
5896 | ||
5897 | return 0; | |
5898 | } | |
5899 | ||
5900 | /* Save PCI command register before chip reset */ | |
5901 | static void tg3_save_pci_state(struct tg3 *tp) | |
5902 | { | |
5903 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); | |
5904 | } | |
5905 | ||
5906 | /* Restore PCI state after chip reset */ | |
5907 | static void tg3_restore_pci_state(struct tg3 *tp) | |
5908 | { | |
5909 | u32 val; | |
5910 | ||
5911 | /* Re-enable indirect register accesses. */ | |
5912 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
5913 | tp->misc_host_ctrl); | |
5914 | ||
5915 | /* Set MAX PCI retry to zero. */ | |
5916 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
5917 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
5918 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) | |
5919 | val |= PCISTATE_RETRY_SAME_DMA; | |
5920 | /* Allow reads and writes to the APE register and memory space. */ | |
5921 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
5922 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
5923 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
5924 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); | |
5925 | ||
5926 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); | |
5927 | ||
5928 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { | |
5929 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
5930 | pcie_set_readrq(tp->pdev, 4096); | |
5931 | else { | |
5932 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
5933 | tp->pci_cacheline_sz); | |
5934 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
5935 | tp->pci_lat_timer); | |
5936 | } | |
5937 | } | |
5938 | ||
5939 | /* Make sure PCI-X relaxed ordering bit is clear. */ | |
5940 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
5941 | u16 pcix_cmd; | |
5942 | ||
5943 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
5944 | &pcix_cmd); | |
5945 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
5946 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
5947 | pcix_cmd); | |
5948 | } | |
5949 | ||
5950 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
5951 | ||
5952 | /* Chip reset on 5780 will reset MSI enable bit, | |
5953 | * so need to restore it. | |
5954 | */ | |
5955 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
5956 | u16 ctrl; | |
5957 | ||
5958 | pci_read_config_word(tp->pdev, | |
5959 | tp->msi_cap + PCI_MSI_FLAGS, | |
5960 | &ctrl); | |
5961 | pci_write_config_word(tp->pdev, | |
5962 | tp->msi_cap + PCI_MSI_FLAGS, | |
5963 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
5964 | val = tr32(MSGINT_MODE); | |
5965 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
5966 | } | |
5967 | } | |
5968 | } | |
5969 | ||
5970 | static void tg3_stop_fw(struct tg3 *); | |
5971 | ||
5972 | /* tp->lock is held. */ | |
5973 | static int tg3_chip_reset(struct tg3 *tp) | |
5974 | { | |
5975 | u32 val; | |
5976 | void (*write_op)(struct tg3 *, u32, u32); | |
5977 | int err; | |
5978 | ||
5979 | tg3_nvram_lock(tp); | |
5980 | ||
5981 | tg3_mdio_stop(tp); | |
5982 | ||
5983 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); | |
5984 | ||
5985 | /* No matching tg3_nvram_unlock() after this because | |
5986 | * chip reset below will undo the nvram lock. | |
5987 | */ | |
5988 | tp->nvram_lock_cnt = 0; | |
5989 | ||
5990 | /* GRC_MISC_CFG core clock reset will clear the memory | |
5991 | * enable bit in PCI register 4 and the MSI enable bit | |
5992 | * on some chips, so we save relevant registers here. | |
5993 | */ | |
5994 | tg3_save_pci_state(tp); | |
5995 | ||
5996 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
5997 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) | |
5998 | tw32(GRC_FASTBOOT_PC, 0); | |
5999 | ||
6000 | /* | |
6001 | * We must avoid the readl() that normally takes place. | |
6002 | * It locks machines, causes machine checks, and other | |
6003 | * fun things. So, temporarily disable the 5701 | |
6004 | * hardware workaround, while we do the reset. | |
6005 | */ | |
6006 | write_op = tp->write32; | |
6007 | if (write_op == tg3_write_flush_reg32) | |
6008 | tp->write32 = tg3_write32; | |
6009 | ||
6010 | /* Prevent the irq handler from reading or writing PCI registers | |
6011 | * during chip reset when the memory enable bit in the PCI command | |
6012 | * register may be cleared. The chip does not generate interrupt | |
6013 | * at this time, but the irq handler may still be called due to irq | |
6014 | * sharing or irqpoll. | |
6015 | */ | |
6016 | tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; | |
6017 | if (tp->hw_status) { | |
6018 | tp->hw_status->status = 0; | |
6019 | tp->hw_status->status_tag = 0; | |
6020 | } | |
6021 | tp->last_tag = 0; | |
6022 | smp_mb(); | |
6023 | synchronize_irq(tp->pdev->irq); | |
6024 | ||
6025 | /* do the reset */ | |
6026 | val = GRC_MISC_CFG_CORECLK_RESET; | |
6027 | ||
6028 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
6029 | if (tr32(0x7e2c) == 0x60) { | |
6030 | tw32(0x7e2c, 0x20); | |
6031 | } | |
6032 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { | |
6033 | tw32(GRC_MISC_CFG, (1 << 29)); | |
6034 | val |= (1 << 29); | |
6035 | } | |
6036 | } | |
6037 | ||
6038 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
6039 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
6040 | tw32(GRC_VCPU_EXT_CTRL, | |
6041 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
6042 | } | |
6043 | ||
6044 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
6045 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; | |
6046 | tw32(GRC_MISC_CFG, val); | |
6047 | ||
6048 | /* restore 5701 hardware bug workaround write method */ | |
6049 | tp->write32 = write_op; | |
6050 | ||
6051 | /* Unfortunately, we have to delay before the PCI read back. | |
6052 | * Some 575X chips even will not respond to a PCI cfg access | |
6053 | * when the reset command is given to the chip. | |
6054 | * | |
6055 | * How do these hardware designers expect things to work | |
6056 | * properly if the PCI write is posted for a long period | |
6057 | * of time? It is always necessary to have some method by | |
6058 | * which a register read back can occur to push the write | |
6059 | * out which does the reset. | |
6060 | * | |
6061 | * For most tg3 variants the trick below was working. | |
6062 | * Ho hum... | |
6063 | */ | |
6064 | udelay(120); | |
6065 | ||
6066 | /* Flush PCI posted writes. The normal MMIO registers | |
6067 | * are inaccessible at this time so this is the only | |
6068 | * way to make this reliably (actually, this is no longer | |
6069 | * the case, see above). I tried to use indirect | |
6070 | * register read/write but this upset some 5701 variants. | |
6071 | */ | |
6072 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
6073 | ||
6074 | udelay(120); | |
6075 | ||
6076 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { | |
6077 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { | |
6078 | int i; | |
6079 | u32 cfg_val; | |
6080 | ||
6081 | /* Wait for link training to complete. */ | |
6082 | for (i = 0; i < 5000; i++) | |
6083 | udelay(100); | |
6084 | ||
6085 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
6086 | pci_write_config_dword(tp->pdev, 0xc4, | |
6087 | cfg_val | (1 << 15)); | |
6088 | } | |
6089 | ||
6090 | /* Set PCIE max payload size to 128 bytes and | |
6091 | * clear the "no snoop" and "relaxed ordering" bits. | |
6092 | */ | |
6093 | pci_write_config_word(tp->pdev, | |
6094 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
6095 | 0); | |
6096 | ||
6097 | pcie_set_readrq(tp->pdev, 4096); | |
6098 | ||
6099 | /* Clear error status */ | |
6100 | pci_write_config_word(tp->pdev, | |
6101 | tp->pcie_cap + PCI_EXP_DEVSTA, | |
6102 | PCI_EXP_DEVSTA_CED | | |
6103 | PCI_EXP_DEVSTA_NFED | | |
6104 | PCI_EXP_DEVSTA_FED | | |
6105 | PCI_EXP_DEVSTA_URD); | |
6106 | } | |
6107 | ||
6108 | tg3_restore_pci_state(tp); | |
6109 | ||
6110 | tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING; | |
6111 | ||
6112 | val = 0; | |
6113 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
6114 | val = tr32(MEMARB_MODE); | |
6115 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
6116 | ||
6117 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
6118 | tg3_stop_fw(tp); | |
6119 | tw32(0x5000, 0x400); | |
6120 | } | |
6121 | ||
6122 | tw32(GRC_MODE, tp->grc_mode); | |
6123 | ||
6124 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
6125 | val = tr32(0xc4); | |
6126 | ||
6127 | tw32(0xc4, val | (1 << 15)); | |
6128 | } | |
6129 | ||
6130 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
6131 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
6132 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
6133 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
6134 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
6135 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
6136 | } | |
6137 | ||
6138 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
6139 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; | |
6140 | tw32_f(MAC_MODE, tp->mac_mode); | |
6141 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
6142 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; | |
6143 | tw32_f(MAC_MODE, tp->mac_mode); | |
6144 | } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { | |
6145 | tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); | |
6146 | if (tp->mac_mode & MAC_MODE_APE_TX_EN) | |
6147 | tp->mac_mode |= MAC_MODE_TDE_ENABLE; | |
6148 | tw32_f(MAC_MODE, tp->mac_mode); | |
6149 | } else | |
6150 | tw32_f(MAC_MODE, 0); | |
6151 | udelay(40); | |
6152 | ||
6153 | tg3_mdio_start(tp); | |
6154 | ||
6155 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); | |
6156 | ||
6157 | err = tg3_poll_fw(tp); | |
6158 | if (err) | |
6159 | return err; | |
6160 | ||
6161 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
6162 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { | |
6163 | val = tr32(0x7c00); | |
6164 | ||
6165 | tw32(0x7c00, val | (1 << 25)); | |
6166 | } | |
6167 | ||
6168 | /* Reprobe ASF enable state. */ | |
6169 | tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF; | |
6170 | tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE; | |
6171 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
6172 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
6173 | u32 nic_cfg; | |
6174 | ||
6175 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
6176 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
6177 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
6178 | tp->last_event_jiffies = jiffies; | |
6179 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) | |
6180 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; | |
6181 | } | |
6182 | } | |
6183 | ||
6184 | return 0; | |
6185 | } | |
6186 | ||
6187 | /* tp->lock is held. */ | |
6188 | static void tg3_stop_fw(struct tg3 *tp) | |
6189 | { | |
6190 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && | |
6191 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
6192 | /* Wait for RX cpu to ACK the previous event. */ | |
6193 | tg3_wait_for_event_ack(tp); | |
6194 | ||
6195 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
6196 | ||
6197 | tg3_generate_fw_event(tp); | |
6198 | ||
6199 | /* Wait for RX cpu to ACK this event. */ | |
6200 | tg3_wait_for_event_ack(tp); | |
6201 | } | |
6202 | } | |
6203 | ||
6204 | /* tp->lock is held. */ | |
6205 | static int tg3_halt(struct tg3 *tp, int kind, int silent) | |
6206 | { | |
6207 | int err; | |
6208 | ||
6209 | tg3_stop_fw(tp); | |
6210 | ||
6211 | tg3_write_sig_pre_reset(tp, kind); | |
6212 | ||
6213 | tg3_abort_hw(tp, silent); | |
6214 | err = tg3_chip_reset(tp); | |
6215 | ||
6216 | tg3_write_sig_legacy(tp, kind); | |
6217 | tg3_write_sig_post_reset(tp, kind); | |
6218 | ||
6219 | if (err) | |
6220 | return err; | |
6221 | ||
6222 | return 0; | |
6223 | } | |
6224 | ||
6225 | #define RX_CPU_SCRATCH_BASE 0x30000 | |
6226 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
6227 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
6228 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
6229 | ||
6230 | /* tp->lock is held. */ | |
6231 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
6232 | { | |
6233 | int i; | |
6234 | ||
6235 | BUG_ON(offset == TX_CPU_BASE && | |
6236 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)); | |
6237 | ||
6238 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
6239 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
6240 | ||
6241 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
6242 | return 0; | |
6243 | } | |
6244 | if (offset == RX_CPU_BASE) { | |
6245 | for (i = 0; i < 10000; i++) { | |
6246 | tw32(offset + CPU_STATE, 0xffffffff); | |
6247 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
6248 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
6249 | break; | |
6250 | } | |
6251 | ||
6252 | tw32(offset + CPU_STATE, 0xffffffff); | |
6253 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
6254 | udelay(10); | |
6255 | } else { | |
6256 | for (i = 0; i < 10000; i++) { | |
6257 | tw32(offset + CPU_STATE, 0xffffffff); | |
6258 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
6259 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
6260 | break; | |
6261 | } | |
6262 | } | |
6263 | ||
6264 | if (i >= 10000) { | |
6265 | printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, " | |
6266 | "and %s CPU\n", | |
6267 | tp->dev->name, | |
6268 | (offset == RX_CPU_BASE ? "RX" : "TX")); | |
6269 | return -ENODEV; | |
6270 | } | |
6271 | ||
6272 | /* Clear firmware's nvram arbitration. */ | |
6273 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
6274 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
6275 | return 0; | |
6276 | } | |
6277 | ||
6278 | struct fw_info { | |
6279 | unsigned int fw_base; | |
6280 | unsigned int fw_len; | |
6281 | const __be32 *fw_data; | |
6282 | }; | |
6283 | ||
6284 | /* tp->lock is held. */ | |
6285 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
6286 | int cpu_scratch_size, struct fw_info *info) | |
6287 | { | |
6288 | int err, lock_err, i; | |
6289 | void (*write_op)(struct tg3 *, u32, u32); | |
6290 | ||
6291 | if (cpu_base == TX_CPU_BASE && | |
6292 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
6293 | printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load " | |
6294 | "TX cpu firmware on %s which is 5705.\n", | |
6295 | tp->dev->name); | |
6296 | return -EINVAL; | |
6297 | } | |
6298 | ||
6299 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
6300 | write_op = tg3_write_mem; | |
6301 | else | |
6302 | write_op = tg3_write_indirect_reg32; | |
6303 | ||
6304 | /* It is possible that bootcode is still loading at this point. | |
6305 | * Get the nvram lock first before halting the cpu. | |
6306 | */ | |
6307 | lock_err = tg3_nvram_lock(tp); | |
6308 | err = tg3_halt_cpu(tp, cpu_base); | |
6309 | if (!lock_err) | |
6310 | tg3_nvram_unlock(tp); | |
6311 | if (err) | |
6312 | goto out; | |
6313 | ||
6314 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
6315 | write_op(tp, cpu_scratch_base + i, 0); | |
6316 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
6317 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
6318 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) | |
6319 | write_op(tp, (cpu_scratch_base + | |
6320 | (info->fw_base & 0xffff) + | |
6321 | (i * sizeof(u32))), | |
6322 | be32_to_cpu(info->fw_data[i])); | |
6323 | ||
6324 | err = 0; | |
6325 | ||
6326 | out: | |
6327 | return err; | |
6328 | } | |
6329 | ||
6330 | /* tp->lock is held. */ | |
6331 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
6332 | { | |
6333 | struct fw_info info; | |
6334 | const __be32 *fw_data; | |
6335 | int err, i; | |
6336 | ||
6337 | fw_data = (void *)tp->fw->data; | |
6338 | ||
6339 | /* Firmware blob starts with version numbers, followed by | |
6340 | start address and length. We are setting complete length. | |
6341 | length = end_address_of_bss - start_address_of_text. | |
6342 | Remainder is the blob to be loaded contiguously | |
6343 | from start address. */ | |
6344 | ||
6345 | info.fw_base = be32_to_cpu(fw_data[1]); | |
6346 | info.fw_len = tp->fw->size - 12; | |
6347 | info.fw_data = &fw_data[3]; | |
6348 | ||
6349 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
6350 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
6351 | &info); | |
6352 | if (err) | |
6353 | return err; | |
6354 | ||
6355 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
6356 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
6357 | &info); | |
6358 | if (err) | |
6359 | return err; | |
6360 | ||
6361 | /* Now startup only the RX cpu. */ | |
6362 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
6363 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
6364 | ||
6365 | for (i = 0; i < 5; i++) { | |
6366 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) | |
6367 | break; | |
6368 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
6369 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
6370 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
6371 | udelay(1000); | |
6372 | } | |
6373 | if (i >= 5) { | |
6374 | printk(KERN_ERR PFX "tg3_load_firmware fails for %s " | |
6375 | "to set RX CPU PC, is %08x should be %08x\n", | |
6376 | tp->dev->name, tr32(RX_CPU_BASE + CPU_PC), | |
6377 | info.fw_base); | |
6378 | return -ENODEV; | |
6379 | } | |
6380 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
6381 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
6382 | ||
6383 | return 0; | |
6384 | } | |
6385 | ||
6386 | /* 5705 needs a special version of the TSO firmware. */ | |
6387 | ||
6388 | /* tp->lock is held. */ | |
6389 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
6390 | { | |
6391 | struct fw_info info; | |
6392 | const __be32 *fw_data; | |
6393 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; | |
6394 | int err, i; | |
6395 | ||
6396 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
6397 | return 0; | |
6398 | ||
6399 | fw_data = (void *)tp->fw->data; | |
6400 | ||
6401 | /* Firmware blob starts with version numbers, followed by | |
6402 | start address and length. We are setting complete length. | |
6403 | length = end_address_of_bss - start_address_of_text. | |
6404 | Remainder is the blob to be loaded contiguously | |
6405 | from start address. */ | |
6406 | ||
6407 | info.fw_base = be32_to_cpu(fw_data[1]); | |
6408 | cpu_scratch_size = tp->fw_len; | |
6409 | info.fw_len = tp->fw->size - 12; | |
6410 | info.fw_data = &fw_data[3]; | |
6411 | ||
6412 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
6413 | cpu_base = RX_CPU_BASE; | |
6414 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
6415 | } else { | |
6416 | cpu_base = TX_CPU_BASE; | |
6417 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
6418 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
6419 | } | |
6420 | ||
6421 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
6422 | cpu_scratch_base, cpu_scratch_size, | |
6423 | &info); | |
6424 | if (err) | |
6425 | return err; | |
6426 | ||
6427 | /* Now startup the cpu. */ | |
6428 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
6429 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
6430 | ||
6431 | for (i = 0; i < 5; i++) { | |
6432 | if (tr32(cpu_base + CPU_PC) == info.fw_base) | |
6433 | break; | |
6434 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
6435 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
6436 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
6437 | udelay(1000); | |
6438 | } | |
6439 | if (i >= 5) { | |
6440 | printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s " | |
6441 | "to set CPU PC, is %08x should be %08x\n", | |
6442 | tp->dev->name, tr32(cpu_base + CPU_PC), | |
6443 | info.fw_base); | |
6444 | return -ENODEV; | |
6445 | } | |
6446 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
6447 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
6448 | return 0; | |
6449 | } | |
6450 | ||
6451 | ||
6452 | static int tg3_set_mac_addr(struct net_device *dev, void *p) | |
6453 | { | |
6454 | struct tg3 *tp = netdev_priv(dev); | |
6455 | struct sockaddr *addr = p; | |
6456 | int err = 0, skip_mac_1 = 0; | |
6457 | ||
6458 | if (!is_valid_ether_addr(addr->sa_data)) | |
6459 | return -EINVAL; | |
6460 | ||
6461 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
6462 | ||
6463 | if (!netif_running(dev)) | |
6464 | return 0; | |
6465 | ||
6466 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
6467 | u32 addr0_high, addr0_low, addr1_high, addr1_low; | |
6468 | ||
6469 | addr0_high = tr32(MAC_ADDR_0_HIGH); | |
6470 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
6471 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
6472 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
6473 | ||
6474 | /* Skip MAC addr 1 if ASF is using it. */ | |
6475 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
6476 | !(addr1_high == 0 && addr1_low == 0)) | |
6477 | skip_mac_1 = 1; | |
6478 | } | |
6479 | spin_lock_bh(&tp->lock); | |
6480 | __tg3_set_mac_addr(tp, skip_mac_1); | |
6481 | spin_unlock_bh(&tp->lock); | |
6482 | ||
6483 | return err; | |
6484 | } | |
6485 | ||
6486 | /* tp->lock is held. */ | |
6487 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
6488 | dma_addr_t mapping, u32 maxlen_flags, | |
6489 | u32 nic_addr) | |
6490 | { | |
6491 | tg3_write_mem(tp, | |
6492 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
6493 | ((u64) mapping >> 32)); | |
6494 | tg3_write_mem(tp, | |
6495 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
6496 | ((u64) mapping & 0xffffffff)); | |
6497 | tg3_write_mem(tp, | |
6498 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
6499 | maxlen_flags); | |
6500 | ||
6501 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
6502 | tg3_write_mem(tp, | |
6503 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
6504 | nic_addr); | |
6505 | } | |
6506 | ||
6507 | static void __tg3_set_rx_mode(struct net_device *); | |
6508 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) | |
6509 | { | |
6510 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); | |
6511 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); | |
6512 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
6513 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
6514 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
6515 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); | |
6516 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
6517 | } | |
6518 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
6519 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
6520 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
6521 | u32 val = ec->stats_block_coalesce_usecs; | |
6522 | ||
6523 | if (!netif_carrier_ok(tp->dev)) | |
6524 | val = 0; | |
6525 | ||
6526 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
6527 | } | |
6528 | } | |
6529 | ||
6530 | /* tp->lock is held. */ | |
6531 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |
6532 | { | |
6533 | u32 val, rdmac_mode; | |
6534 | int i, err, limit; | |
6535 | ||
6536 | tg3_disable_ints(tp); | |
6537 | ||
6538 | tg3_stop_fw(tp); | |
6539 | ||
6540 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
6541 | ||
6542 | if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) { | |
6543 | tg3_abort_hw(tp, 1); | |
6544 | } | |
6545 | ||
6546 | if (reset_phy && | |
6547 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) | |
6548 | tg3_phy_reset(tp); | |
6549 | ||
6550 | err = tg3_chip_reset(tp); | |
6551 | if (err) | |
6552 | return err; | |
6553 | ||
6554 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
6555 | ||
6556 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { | |
6557 | val = tr32(TG3_CPMU_CTRL); | |
6558 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
6559 | tw32(TG3_CPMU_CTRL, val); | |
6560 | ||
6561 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
6562 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
6563 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
6564 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
6565 | ||
6566 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
6567 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
6568 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
6569 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
6570 | ||
6571 | val = tr32(TG3_CPMU_HST_ACC); | |
6572 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
6573 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
6574 | tw32(TG3_CPMU_HST_ACC, val); | |
6575 | } | |
6576 | ||
6577 | /* This works around an issue with Athlon chipsets on | |
6578 | * B3 tigon3 silicon. This bit has no effect on any | |
6579 | * other revision. But do not set this on PCI Express | |
6580 | * chips and don't even touch the clocks if the CPMU is present. | |
6581 | */ | |
6582 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) { | |
6583 | if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
6584 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; | |
6585 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
6586 | } | |
6587 | ||
6588 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
6589 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
6590 | val = tr32(TG3PCI_PCISTATE); | |
6591 | val |= PCISTATE_RETRY_SAME_DMA; | |
6592 | tw32(TG3PCI_PCISTATE, val); | |
6593 | } | |
6594 | ||
6595 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { | |
6596 | /* Allow reads and writes to the | |
6597 | * APE register and memory space. | |
6598 | */ | |
6599 | val = tr32(TG3PCI_PCISTATE); | |
6600 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
6601 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
6602 | tw32(TG3PCI_PCISTATE, val); | |
6603 | } | |
6604 | ||
6605 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { | |
6606 | /* Enable some hw fixes. */ | |
6607 | val = tr32(TG3PCI_MSI_DATA); | |
6608 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
6609 | tw32(TG3PCI_MSI_DATA, val); | |
6610 | } | |
6611 | ||
6612 | /* Descriptor ring init may make accesses to the | |
6613 | * NIC SRAM area to setup the TX descriptors, so we | |
6614 | * can only do this after the hardware has been | |
6615 | * successfully reset. | |
6616 | */ | |
6617 | err = tg3_init_rings(tp); | |
6618 | if (err) | |
6619 | return err; | |
6620 | ||
6621 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
6622 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
6623 | /* This value is determined during the probe time DMA | |
6624 | * engine test, tg3_test_dma. | |
6625 | */ | |
6626 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
6627 | } | |
6628 | ||
6629 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
6630 | GRC_MODE_4X_NIC_SEND_RINGS | | |
6631 | GRC_MODE_NO_TX_PHDR_CSUM | | |
6632 | GRC_MODE_NO_RX_PHDR_CSUM); | |
6633 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
6634 | ||
6635 | /* Pseudo-header checksum is done by hardware logic and not | |
6636 | * the offload processers, so make the chip do the pseudo- | |
6637 | * header checksums on receive. For transmit it is more | |
6638 | * convenient to do the pseudo-header checksum in software | |
6639 | * as Linux does that on transmit for us in all cases. | |
6640 | */ | |
6641 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
6642 | ||
6643 | tw32(GRC_MODE, | |
6644 | tp->grc_mode | | |
6645 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
6646 | ||
6647 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
6648 | val = tr32(GRC_MISC_CFG); | |
6649 | val &= ~0xff; | |
6650 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
6651 | tw32(GRC_MISC_CFG, val); | |
6652 | ||
6653 | /* Initialize MBUF/DESC pool. */ | |
6654 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
6655 | /* Do nothing. */ | |
6656 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
6657 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
6658 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
6659 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
6660 | else | |
6661 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
6662 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
6663 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
6664 | } | |
6665 | else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { | |
6666 | int fw_len; | |
6667 | ||
6668 | fw_len = tp->fw_len; | |
6669 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); | |
6670 | tw32(BUFMGR_MB_POOL_ADDR, | |
6671 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
6672 | tw32(BUFMGR_MB_POOL_SIZE, | |
6673 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
6674 | } | |
6675 | ||
6676 | if (tp->dev->mtu <= ETH_DATA_LEN) { | |
6677 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
6678 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
6679 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
6680 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
6681 | tw32(BUFMGR_MB_HIGH_WATER, | |
6682 | tp->bufmgr_config.mbuf_high_water); | |
6683 | } else { | |
6684 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
6685 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
6686 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
6687 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
6688 | tw32(BUFMGR_MB_HIGH_WATER, | |
6689 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
6690 | } | |
6691 | tw32(BUFMGR_DMA_LOW_WATER, | |
6692 | tp->bufmgr_config.dma_low_water); | |
6693 | tw32(BUFMGR_DMA_HIGH_WATER, | |
6694 | tp->bufmgr_config.dma_high_water); | |
6695 | ||
6696 | tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); | |
6697 | for (i = 0; i < 2000; i++) { | |
6698 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
6699 | break; | |
6700 | udelay(10); | |
6701 | } | |
6702 | if (i >= 2000) { | |
6703 | printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n", | |
6704 | tp->dev->name); | |
6705 | return -ENODEV; | |
6706 | } | |
6707 | ||
6708 | /* Setup replenish threshold. */ | |
6709 | val = tp->rx_pending / 8; | |
6710 | if (val == 0) | |
6711 | val = 1; | |
6712 | else if (val > tp->rx_std_max_post) | |
6713 | val = tp->rx_std_max_post; | |
6714 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
6715 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) | |
6716 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
6717 | ||
6718 | if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2)) | |
6719 | val = TG3_RX_INTERNAL_RING_SZ_5906 / 2; | |
6720 | } | |
6721 | ||
6722 | tw32(RCVBDI_STD_THRESH, val); | |
6723 | ||
6724 | /* Initialize TG3_BDINFO's at: | |
6725 | * RCVDBDI_STD_BD: standard eth size rx ring | |
6726 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
6727 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
6728 | * | |
6729 | * like so: | |
6730 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
6731 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
6732 | * ring attribute flags | |
6733 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
6734 | * | |
6735 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
6736 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
6737 | * | |
6738 | * The size of each ring is fixed in the firmware, but the location is | |
6739 | * configurable. | |
6740 | */ | |
6741 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
6742 | ((u64) tp->rx_std_mapping >> 32)); | |
6743 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, | |
6744 | ((u64) tp->rx_std_mapping & 0xffffffff)); | |
6745 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, | |
6746 | NIC_SRAM_RX_BUFFER_DESC); | |
6747 | ||
6748 | /* Don't even try to program the JUMBO/MINI buffer descriptor | |
6749 | * configs on 5705. | |
6750 | */ | |
6751 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
6752 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
6753 | RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT); | |
6754 | } else { | |
6755 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
6756 | RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT); | |
6757 | ||
6758 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
6759 | BDINFO_FLAGS_DISABLED); | |
6760 | ||
6761 | /* Setup replenish threshold. */ | |
6762 | tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); | |
6763 | ||
6764 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { | |
6765 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
6766 | ((u64) tp->rx_jumbo_mapping >> 32)); | |
6767 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, | |
6768 | ((u64) tp->rx_jumbo_mapping & 0xffffffff)); | |
6769 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
6770 | RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT); | |
6771 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, | |
6772 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
6773 | } else { | |
6774 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
6775 | BDINFO_FLAGS_DISABLED); | |
6776 | } | |
6777 | ||
6778 | } | |
6779 | ||
6780 | /* There is only one send ring on 5705/5750, no need to explicitly | |
6781 | * disable the others. | |
6782 | */ | |
6783 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
6784 | /* Clear out send RCB ring in SRAM. */ | |
6785 | for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE) | |
6786 | tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS, | |
6787 | BDINFO_FLAGS_DISABLED); | |
6788 | } | |
6789 | ||
6790 | tp->tx_prod = 0; | |
6791 | tp->tx_cons = 0; | |
6792 | tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0); | |
6793 | tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0); | |
6794 | ||
6795 | tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB, | |
6796 | tp->tx_desc_mapping, | |
6797 | (TG3_TX_RING_SIZE << | |
6798 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
6799 | NIC_SRAM_TX_BUFFER_DESC); | |
6800 | ||
6801 | /* There is only one receive return ring on 5705/5750, no need | |
6802 | * to explicitly disable the others. | |
6803 | */ | |
6804 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
6805 | for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; | |
6806 | i += TG3_BDINFO_SIZE) { | |
6807 | tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS, | |
6808 | BDINFO_FLAGS_DISABLED); | |
6809 | } | |
6810 | } | |
6811 | ||
6812 | tp->rx_rcb_ptr = 0; | |
6813 | tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0); | |
6814 | ||
6815 | tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB, | |
6816 | tp->rx_rcb_mapping, | |
6817 | (TG3_RX_RCB_RING_SIZE(tp) << | |
6818 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
6819 | 0); | |
6820 | ||
6821 | tp->rx_std_ptr = tp->rx_pending; | |
6822 | tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, | |
6823 | tp->rx_std_ptr); | |
6824 | ||
6825 | tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? | |
6826 | tp->rx_jumbo_pending : 0; | |
6827 | tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, | |
6828 | tp->rx_jumbo_ptr); | |
6829 | ||
6830 | /* Initialize MAC address and backoff seed. */ | |
6831 | __tg3_set_mac_addr(tp, 0); | |
6832 | ||
6833 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
6834 | tw32(MAC_RX_MTU_SIZE, | |
6835 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
6836 | ||
6837 | /* The slot time is changed by tg3_setup_phy if we | |
6838 | * run at gigabit with half duplex. | |
6839 | */ | |
6840 | tw32(MAC_TX_LENGTHS, | |
6841 | (2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
6842 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
6843 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
6844 | ||
6845 | /* Receive rules. */ | |
6846 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
6847 | tw32(RCVLPC_CONFIG, 0x0181); | |
6848 | ||
6849 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
6850 | * the RCVLPC_STATE_ENABLE mask. | |
6851 | */ | |
6852 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
6853 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
6854 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
6855 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
6856 | RDMAC_MODE_LNGREAD_ENAB); | |
6857 | ||
6858 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
6859 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
6860 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
6861 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | | |
6862 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
6863 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
6864 | ||
6865 | /* If statement applies to 5705 and 5750 PCI devices only */ | |
6866 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
6867 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
6868 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) { | |
6869 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && | |
6870 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
6871 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; | |
6872 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
6873 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { | |
6874 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
6875 | } | |
6876 | } | |
6877 | ||
6878 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
6879 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
6880 | ||
6881 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
6882 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; | |
6883 | ||
6884 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
6885 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
6886 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
6887 | ||
6888 | /* Receive/send statistics. */ | |
6889 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
6890 | val = tr32(RCVLPC_STATS_ENABLE); | |
6891 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
6892 | tw32(RCVLPC_STATS_ENABLE, val); | |
6893 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
6894 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
6895 | val = tr32(RCVLPC_STATS_ENABLE); | |
6896 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
6897 | tw32(RCVLPC_STATS_ENABLE, val); | |
6898 | } else { | |
6899 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
6900 | } | |
6901 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
6902 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
6903 | tw32(SNDDATAI_STATSCTRL, | |
6904 | (SNDDATAI_SCTRL_ENABLE | | |
6905 | SNDDATAI_SCTRL_FASTUPD)); | |
6906 | ||
6907 | /* Setup host coalescing engine. */ | |
6908 | tw32(HOSTCC_MODE, 0); | |
6909 | for (i = 0; i < 2000; i++) { | |
6910 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
6911 | break; | |
6912 | udelay(10); | |
6913 | } | |
6914 | ||
6915 | __tg3_set_coalesce(tp, &tp->coal); | |
6916 | ||
6917 | /* set status block DMA address */ | |
6918 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
6919 | ((u64) tp->status_mapping >> 32)); | |
6920 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
6921 | ((u64) tp->status_mapping & 0xffffffff)); | |
6922 | ||
6923 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
6924 | /* Status/statistics block address. See tg3_timer, | |
6925 | * the tg3_periodic_fetch_stats call there, and | |
6926 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
6927 | */ | |
6928 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
6929 | ((u64) tp->stats_mapping >> 32)); | |
6930 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
6931 | ((u64) tp->stats_mapping & 0xffffffff)); | |
6932 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
6933 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); | |
6934 | } | |
6935 | ||
6936 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
6937 | ||
6938 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
6939 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
6940 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
6941 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); | |
6942 | ||
6943 | /* Clear statistics/status block in chip, and status block in ram. */ | |
6944 | for (i = NIC_SRAM_STATS_BLK; | |
6945 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
6946 | i += sizeof(u32)) { | |
6947 | tg3_write_mem(tp, i, 0); | |
6948 | udelay(40); | |
6949 | } | |
6950 | memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6951 | ||
6952 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
6953 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
6954 | /* reset to prevent losing 1st rx packet intermittently */ | |
6955 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
6956 | udelay(10); | |
6957 | } | |
6958 | ||
6959 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
6960 | tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
6961 | else | |
6962 | tp->mac_mode = 0; | |
6963 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
6964 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; | |
6965 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
6966 | !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
6967 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | |
6968 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
6969 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); | |
6970 | udelay(40); | |
6971 | ||
6972 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). | |
6973 | * If TG3_FLG2_IS_NIC is zero, we should read the | |
6974 | * register to preserve the GPIO settings for LOMs. The GPIOs, | |
6975 | * whether used as inputs or outputs, are set by boot code after | |
6976 | * reset. | |
6977 | */ | |
6978 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) { | |
6979 | u32 gpio_mask; | |
6980 | ||
6981 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | | |
6982 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
6983 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
6984 | ||
6985 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
6986 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
6987 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
6988 | ||
6989 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
6990 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
6991 | ||
6992 | tp->grc_local_ctrl &= ~gpio_mask; | |
6993 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; | |
6994 | ||
6995 | /* GPIO1 must be driven high for eeprom write protect */ | |
6996 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) | |
6997 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
6998 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
6999 | } | |
7000 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
7001 | udelay(100); | |
7002 | ||
7003 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0); | |
7004 | tp->last_tag = 0; | |
7005 | ||
7006 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7007 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | |
7008 | udelay(40); | |
7009 | } | |
7010 | ||
7011 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
7012 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
7013 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
7014 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
7015 | WDMAC_MODE_LNGREAD_ENAB); | |
7016 | ||
7017 | /* If statement applies to 5705 and 5750 PCI devices only */ | |
7018 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
7019 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
7020 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { | |
7021 | if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) && | |
7022 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || | |
7023 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
7024 | /* nothing */ | |
7025 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
7026 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
7027 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
7028 | val |= WDMAC_MODE_RX_ACCEL; | |
7029 | } | |
7030 | } | |
7031 | ||
7032 | /* Enable host coalescing bug fix */ | |
7033 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
7034 | val |= WDMAC_MODE_STATUS_TAG_FIX; | |
7035 | ||
7036 | tw32_f(WDMAC_MODE, val); | |
7037 | udelay(40); | |
7038 | ||
7039 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
7040 | u16 pcix_cmd; | |
7041 | ||
7042 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7043 | &pcix_cmd); | |
7044 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { | |
7045 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; | |
7046 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
7047 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
7048 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); | |
7049 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
7050 | } | |
7051 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7052 | pcix_cmd); | |
7053 | } | |
7054 | ||
7055 | tw32_f(RDMAC_MODE, rdmac_mode); | |
7056 | udelay(40); | |
7057 | ||
7058 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
7059 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7060 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | |
7061 | ||
7062 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
7063 | tw32(SNDDATAC_MODE, | |
7064 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
7065 | else | |
7066 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
7067 | ||
7068 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); | |
7069 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7070 | tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ); | |
7071 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); | |
7072 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
7073 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); | |
7074 | tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE); | |
7075 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); | |
7076 | ||
7077 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
7078 | err = tg3_load_5701_a0_firmware_fix(tp); | |
7079 | if (err) | |
7080 | return err; | |
7081 | } | |
7082 | ||
7083 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { | |
7084 | err = tg3_load_tso_firmware(tp); | |
7085 | if (err) | |
7086 | return err; | |
7087 | } | |
7088 | ||
7089 | tp->tx_mode = TX_MODE_ENABLE; | |
7090 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
7091 | udelay(100); | |
7092 | ||
7093 | tp->rx_mode = RX_MODE_ENABLE; | |
7094 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
7095 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; | |
7096 | ||
7097 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7098 | udelay(10); | |
7099 | ||
7100 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
7101 | ||
7102 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
7103 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
7104 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
7105 | udelay(10); | |
7106 | } | |
7107 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7108 | udelay(10); | |
7109 | ||
7110 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
7111 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && | |
7112 | !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) { | |
7113 | /* Set drive transmission level to 1.2V */ | |
7114 | /* only if the signal pre-emphasis bit is not set */ | |
7115 | val = tr32(MAC_SERDES_CFG); | |
7116 | val &= 0xfffff000; | |
7117 | val |= 0x880; | |
7118 | tw32(MAC_SERDES_CFG, val); | |
7119 | } | |
7120 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
7121 | tw32(MAC_SERDES_CFG, 0x616000); | |
7122 | } | |
7123 | ||
7124 | /* Prevent chip from dropping frames when flow control | |
7125 | * is enabled. | |
7126 | */ | |
7127 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2); | |
7128 | ||
7129 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
7130 | (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
7131 | /* Use hardware link auto-negotiation */ | |
7132 | tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG; | |
7133 | } | |
7134 | ||
7135 | if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && | |
7136 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { | |
7137 | u32 tmp; | |
7138 | ||
7139 | tmp = tr32(SERDES_RX_CTRL); | |
7140 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
7141 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
7142 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
7143 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
7144 | } | |
7145 | ||
7146 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { | |
7147 | if (tp->link_config.phy_is_low_power) { | |
7148 | tp->link_config.phy_is_low_power = 0; | |
7149 | tp->link_config.speed = tp->link_config.orig_speed; | |
7150 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
7151 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
7152 | } | |
7153 | ||
7154 | err = tg3_setup_phy(tp, 0); | |
7155 | if (err) | |
7156 | return err; | |
7157 | ||
7158 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
7159 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) { | |
7160 | u32 tmp; | |
7161 | ||
7162 | /* Clear CRC stats. */ | |
7163 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
7164 | tg3_writephy(tp, MII_TG3_TEST1, | |
7165 | tmp | MII_TG3_TEST1_CRC_EN); | |
7166 | tg3_readphy(tp, 0x14, &tmp); | |
7167 | } | |
7168 | } | |
7169 | } | |
7170 | ||
7171 | __tg3_set_rx_mode(tp->dev); | |
7172 | ||
7173 | /* Initialize receive rules. */ | |
7174 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
7175 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
7176 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
7177 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
7178 | ||
7179 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
7180 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
7181 | limit = 8; | |
7182 | else | |
7183 | limit = 16; | |
7184 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
7185 | limit -= 4; | |
7186 | switch (limit) { | |
7187 | case 16: | |
7188 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
7189 | case 15: | |
7190 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
7191 | case 14: | |
7192 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
7193 | case 13: | |
7194 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
7195 | case 12: | |
7196 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
7197 | case 11: | |
7198 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
7199 | case 10: | |
7200 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
7201 | case 9: | |
7202 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
7203 | case 8: | |
7204 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
7205 | case 7: | |
7206 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
7207 | case 6: | |
7208 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
7209 | case 5: | |
7210 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
7211 | case 4: | |
7212 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
7213 | case 3: | |
7214 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
7215 | case 2: | |
7216 | case 1: | |
7217 | ||
7218 | default: | |
7219 | break; | |
7220 | } | |
7221 | ||
7222 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
7223 | /* Write our heartbeat update interval to APE. */ | |
7224 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
7225 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
7226 | ||
7227 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); | |
7228 | ||
7229 | return 0; | |
7230 | } | |
7231 | ||
7232 | /* Called at device open time to get the chip ready for | |
7233 | * packet processing. Invoked with tp->lock held. | |
7234 | */ | |
7235 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) | |
7236 | { | |
7237 | tg3_switch_clocks(tp); | |
7238 | ||
7239 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
7240 | ||
7241 | return tg3_reset_hw(tp, reset_phy); | |
7242 | } | |
7243 | ||
7244 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
7245 | do { u32 __val = tr32(REG); \ | |
7246 | (PSTAT)->low += __val; \ | |
7247 | if ((PSTAT)->low < __val) \ | |
7248 | (PSTAT)->high += 1; \ | |
7249 | } while (0) | |
7250 | ||
7251 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
7252 | { | |
7253 | struct tg3_hw_stats *sp = tp->hw_stats; | |
7254 | ||
7255 | if (!netif_carrier_ok(tp->dev)) | |
7256 | return; | |
7257 | ||
7258 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
7259 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
7260 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
7261 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
7262 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
7263 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
7264 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
7265 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
7266 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
7267 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
7268 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
7269 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
7270 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
7271 | ||
7272 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
7273 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
7274 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
7275 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
7276 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
7277 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
7278 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
7279 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
7280 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
7281 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
7282 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
7283 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
7284 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
7285 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
7286 | ||
7287 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
7288 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | |
7289 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); | |
7290 | } | |
7291 | ||
7292 | static void tg3_timer(unsigned long __opaque) | |
7293 | { | |
7294 | struct tg3 *tp = (struct tg3 *) __opaque; | |
7295 | ||
7296 | if (tp->irq_sync) | |
7297 | goto restart_timer; | |
7298 | ||
7299 | spin_lock(&tp->lock); | |
7300 | ||
7301 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
7302 | /* All of this garbage is because when using non-tagged | |
7303 | * IRQ status the mailbox/status_block protocol the chip | |
7304 | * uses with the cpu is race prone. | |
7305 | */ | |
7306 | if (tp->hw_status->status & SD_STATUS_UPDATED) { | |
7307 | tw32(GRC_LOCAL_CTRL, | |
7308 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
7309 | } else { | |
7310 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
7311 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); | |
7312 | } | |
7313 | ||
7314 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
7315 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; | |
7316 | spin_unlock(&tp->lock); | |
7317 | schedule_work(&tp->reset_task); | |
7318 | return; | |
7319 | } | |
7320 | } | |
7321 | ||
7322 | /* This part only runs once per second. */ | |
7323 | if (!--tp->timer_counter) { | |
7324 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
7325 | tg3_periodic_fetch_stats(tp); | |
7326 | ||
7327 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { | |
7328 | u32 mac_stat; | |
7329 | int phy_event; | |
7330 | ||
7331 | mac_stat = tr32(MAC_STATUS); | |
7332 | ||
7333 | phy_event = 0; | |
7334 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) { | |
7335 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) | |
7336 | phy_event = 1; | |
7337 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
7338 | phy_event = 1; | |
7339 | ||
7340 | if (phy_event) | |
7341 | tg3_setup_phy(tp, 0); | |
7342 | } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) { | |
7343 | u32 mac_stat = tr32(MAC_STATUS); | |
7344 | int need_setup = 0; | |
7345 | ||
7346 | if (netif_carrier_ok(tp->dev) && | |
7347 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
7348 | need_setup = 1; | |
7349 | } | |
7350 | if (! netif_carrier_ok(tp->dev) && | |
7351 | (mac_stat & (MAC_STATUS_PCS_SYNCED | | |
7352 | MAC_STATUS_SIGNAL_DET))) { | |
7353 | need_setup = 1; | |
7354 | } | |
7355 | if (need_setup) { | |
7356 | if (!tp->serdes_counter) { | |
7357 | tw32_f(MAC_MODE, | |
7358 | (tp->mac_mode & | |
7359 | ~MAC_MODE_PORT_MODE_MASK)); | |
7360 | udelay(40); | |
7361 | tw32_f(MAC_MODE, tp->mac_mode); | |
7362 | udelay(40); | |
7363 | } | |
7364 | tg3_setup_phy(tp, 0); | |
7365 | } | |
7366 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) | |
7367 | tg3_serdes_parallel_detect(tp); | |
7368 | ||
7369 | tp->timer_counter = tp->timer_multiplier; | |
7370 | } | |
7371 | ||
7372 | /* Heartbeat is only sent once every 2 seconds. | |
7373 | * | |
7374 | * The heartbeat is to tell the ASF firmware that the host | |
7375 | * driver is still alive. In the event that the OS crashes, | |
7376 | * ASF needs to reset the hardware to free up the FIFO space | |
7377 | * that may be filled with rx packets destined for the host. | |
7378 | * If the FIFO is full, ASF will no longer function properly. | |
7379 | * | |
7380 | * Unintended resets have been reported on real time kernels | |
7381 | * where the timer doesn't run on time. Netpoll will also have | |
7382 | * same problem. | |
7383 | * | |
7384 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
7385 | * to check the ring condition when the heartbeat is expiring | |
7386 | * before doing the reset. This will prevent most unintended | |
7387 | * resets. | |
7388 | */ | |
7389 | if (!--tp->asf_counter) { | |
7390 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && | |
7391 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7392 | tg3_wait_for_event_ack(tp); | |
7393 | ||
7394 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, | |
7395 | FWCMD_NICDRV_ALIVE3); | |
7396 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); | |
7397 | /* 5 seconds timeout */ | |
7398 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5); | |
7399 | ||
7400 | tg3_generate_fw_event(tp); | |
7401 | } | |
7402 | tp->asf_counter = tp->asf_multiplier; | |
7403 | } | |
7404 | ||
7405 | spin_unlock(&tp->lock); | |
7406 | ||
7407 | restart_timer: | |
7408 | tp->timer.expires = jiffies + tp->timer_offset; | |
7409 | add_timer(&tp->timer); | |
7410 | } | |
7411 | ||
7412 | static int tg3_request_irq(struct tg3 *tp) | |
7413 | { | |
7414 | irq_handler_t fn; | |
7415 | unsigned long flags; | |
7416 | struct net_device *dev = tp->dev; | |
7417 | ||
7418 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7419 | fn = tg3_msi; | |
7420 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
7421 | fn = tg3_msi_1shot; | |
7422 | flags = IRQF_SAMPLE_RANDOM; | |
7423 | } else { | |
7424 | fn = tg3_interrupt; | |
7425 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
7426 | fn = tg3_interrupt_tagged; | |
7427 | flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM; | |
7428 | } | |
7429 | return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev)); | |
7430 | } | |
7431 | ||
7432 | static int tg3_test_interrupt(struct tg3 *tp) | |
7433 | { | |
7434 | struct net_device *dev = tp->dev; | |
7435 | int err, i, intr_ok = 0; | |
7436 | ||
7437 | if (!netif_running(dev)) | |
7438 | return -ENODEV; | |
7439 | ||
7440 | tg3_disable_ints(tp); | |
7441 | ||
7442 | free_irq(tp->pdev->irq, dev); | |
7443 | ||
7444 | err = request_irq(tp->pdev->irq, tg3_test_isr, | |
7445 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); | |
7446 | if (err) | |
7447 | return err; | |
7448 | ||
7449 | tp->hw_status->status &= ~SD_STATUS_UPDATED; | |
7450 | tg3_enable_ints(tp); | |
7451 | ||
7452 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
7453 | HOSTCC_MODE_NOW); | |
7454 | ||
7455 | for (i = 0; i < 5; i++) { | |
7456 | u32 int_mbox, misc_host_ctrl; | |
7457 | ||
7458 | int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 + | |
7459 | TG3_64BIT_REG_LOW); | |
7460 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); | |
7461 | ||
7462 | if ((int_mbox != 0) || | |
7463 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
7464 | intr_ok = 1; | |
7465 | break; | |
7466 | } | |
7467 | ||
7468 | msleep(10); | |
7469 | } | |
7470 | ||
7471 | tg3_disable_ints(tp); | |
7472 | ||
7473 | free_irq(tp->pdev->irq, dev); | |
7474 | ||
7475 | err = tg3_request_irq(tp); | |
7476 | ||
7477 | if (err) | |
7478 | return err; | |
7479 | ||
7480 | if (intr_ok) | |
7481 | return 0; | |
7482 | ||
7483 | return -EIO; | |
7484 | } | |
7485 | ||
7486 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
7487 | * successfully restored | |
7488 | */ | |
7489 | static int tg3_test_msi(struct tg3 *tp) | |
7490 | { | |
7491 | struct net_device *dev = tp->dev; | |
7492 | int err; | |
7493 | u16 pci_cmd; | |
7494 | ||
7495 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) | |
7496 | return 0; | |
7497 | ||
7498 | /* Turn off SERR reporting in case MSI terminates with Master | |
7499 | * Abort. | |
7500 | */ | |
7501 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
7502 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
7503 | pci_cmd & ~PCI_COMMAND_SERR); | |
7504 | ||
7505 | err = tg3_test_interrupt(tp); | |
7506 | ||
7507 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
7508 | ||
7509 | if (!err) | |
7510 | return 0; | |
7511 | ||
7512 | /* other failures */ | |
7513 | if (err != -EIO) | |
7514 | return err; | |
7515 | ||
7516 | /* MSI test failed, go back to INTx mode */ | |
7517 | printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " | |
7518 | "switching to INTx mode. Please report this failure to " | |
7519 | "the PCI maintainer and include system chipset information.\n", | |
7520 | tp->dev->name); | |
7521 | ||
7522 | free_irq(tp->pdev->irq, dev); | |
7523 | pci_disable_msi(tp->pdev); | |
7524 | ||
7525 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
7526 | ||
7527 | err = tg3_request_irq(tp); | |
7528 | if (err) | |
7529 | return err; | |
7530 | ||
7531 | /* Need to reset the chip because the MSI cycle may have terminated | |
7532 | * with Master Abort. | |
7533 | */ | |
7534 | tg3_full_lock(tp, 1); | |
7535 | ||
7536 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
7537 | err = tg3_init_hw(tp, 1); | |
7538 | ||
7539 | tg3_full_unlock(tp); | |
7540 | ||
7541 | if (err) | |
7542 | free_irq(tp->pdev->irq, dev); | |
7543 | ||
7544 | return err; | |
7545 | } | |
7546 | ||
7547 | static int tg3_request_firmware(struct tg3 *tp) | |
7548 | { | |
7549 | const __be32 *fw_data; | |
7550 | ||
7551 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
7552 | printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n", | |
7553 | tp->dev->name, tp->fw_needed); | |
7554 | return -ENOENT; | |
7555 | } | |
7556 | ||
7557 | fw_data = (void *)tp->fw->data; | |
7558 | ||
7559 | /* Firmware blob starts with version numbers, followed by | |
7560 | * start address and _full_ length including BSS sections | |
7561 | * (which must be longer than the actual data, of course | |
7562 | */ | |
7563 | ||
7564 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
7565 | if (tp->fw_len < (tp->fw->size - 12)) { | |
7566 | printk(KERN_ERR "%s: bogus length %d in \"%s\"\n", | |
7567 | tp->dev->name, tp->fw_len, tp->fw_needed); | |
7568 | release_firmware(tp->fw); | |
7569 | tp->fw = NULL; | |
7570 | return -EINVAL; | |
7571 | } | |
7572 | ||
7573 | /* We no longer need firmware; we have it. */ | |
7574 | tp->fw_needed = NULL; | |
7575 | return 0; | |
7576 | } | |
7577 | ||
7578 | static int tg3_open(struct net_device *dev) | |
7579 | { | |
7580 | struct tg3 *tp = netdev_priv(dev); | |
7581 | int err; | |
7582 | ||
7583 | if (tp->fw_needed) { | |
7584 | err = tg3_request_firmware(tp); | |
7585 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
7586 | if (err) | |
7587 | return err; | |
7588 | } else if (err) { | |
7589 | printk(KERN_WARNING "%s: TSO capability disabled.\n", | |
7590 | tp->dev->name); | |
7591 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; | |
7592 | } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
7593 | printk(KERN_NOTICE "%s: TSO capability restored.\n", | |
7594 | tp->dev->name); | |
7595 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; | |
7596 | } | |
7597 | } | |
7598 | ||
7599 | netif_carrier_off(tp->dev); | |
7600 | ||
7601 | err = tg3_set_power_state(tp, PCI_D0); | |
7602 | if (err) | |
7603 | return err; | |
7604 | ||
7605 | tg3_full_lock(tp, 0); | |
7606 | ||
7607 | tg3_disable_ints(tp); | |
7608 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
7609 | ||
7610 | tg3_full_unlock(tp); | |
7611 | ||
7612 | /* The placement of this call is tied | |
7613 | * to the setup and use of Host TX descriptors. | |
7614 | */ | |
7615 | err = tg3_alloc_consistent(tp); | |
7616 | if (err) | |
7617 | return err; | |
7618 | ||
7619 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) { | |
7620 | /* All MSI supporting chips should support tagged | |
7621 | * status. Assert that this is the case. | |
7622 | */ | |
7623 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
7624 | printk(KERN_WARNING PFX "%s: MSI without TAGGED? " | |
7625 | "Not using MSI.\n", tp->dev->name); | |
7626 | } else if (pci_enable_msi(tp->pdev) == 0) { | |
7627 | u32 msi_mode; | |
7628 | ||
7629 | msi_mode = tr32(MSGINT_MODE); | |
7630 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); | |
7631 | tp->tg3_flags2 |= TG3_FLG2_USING_MSI; | |
7632 | } | |
7633 | } | |
7634 | err = tg3_request_irq(tp); | |
7635 | ||
7636 | if (err) { | |
7637 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7638 | pci_disable_msi(tp->pdev); | |
7639 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
7640 | } | |
7641 | tg3_free_consistent(tp); | |
7642 | return err; | |
7643 | } | |
7644 | ||
7645 | napi_enable(&tp->napi); | |
7646 | ||
7647 | tg3_full_lock(tp, 0); | |
7648 | ||
7649 | err = tg3_init_hw(tp, 1); | |
7650 | if (err) { | |
7651 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
7652 | tg3_free_rings(tp); | |
7653 | } else { | |
7654 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
7655 | tp->timer_offset = HZ; | |
7656 | else | |
7657 | tp->timer_offset = HZ / 10; | |
7658 | ||
7659 | BUG_ON(tp->timer_offset > HZ); | |
7660 | tp->timer_counter = tp->timer_multiplier = | |
7661 | (HZ / tp->timer_offset); | |
7662 | tp->asf_counter = tp->asf_multiplier = | |
7663 | ((HZ / tp->timer_offset) * 2); | |
7664 | ||
7665 | init_timer(&tp->timer); | |
7666 | tp->timer.expires = jiffies + tp->timer_offset; | |
7667 | tp->timer.data = (unsigned long) tp; | |
7668 | tp->timer.function = tg3_timer; | |
7669 | } | |
7670 | ||
7671 | tg3_full_unlock(tp); | |
7672 | ||
7673 | if (err) { | |
7674 | napi_disable(&tp->napi); | |
7675 | free_irq(tp->pdev->irq, dev); | |
7676 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7677 | pci_disable_msi(tp->pdev); | |
7678 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
7679 | } | |
7680 | tg3_free_consistent(tp); | |
7681 | return err; | |
7682 | } | |
7683 | ||
7684 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7685 | err = tg3_test_msi(tp); | |
7686 | ||
7687 | if (err) { | |
7688 | tg3_full_lock(tp, 0); | |
7689 | ||
7690 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7691 | pci_disable_msi(tp->pdev); | |
7692 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
7693 | } | |
7694 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
7695 | tg3_free_rings(tp); | |
7696 | tg3_free_consistent(tp); | |
7697 | ||
7698 | tg3_full_unlock(tp); | |
7699 | ||
7700 | napi_disable(&tp->napi); | |
7701 | ||
7702 | return err; | |
7703 | } | |
7704 | ||
7705 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7706 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) { | |
7707 | u32 val = tr32(PCIE_TRANSACTION_CFG); | |
7708 | ||
7709 | tw32(PCIE_TRANSACTION_CFG, | |
7710 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
7711 | } | |
7712 | } | |
7713 | } | |
7714 | ||
7715 | tg3_phy_start(tp); | |
7716 | ||
7717 | tg3_full_lock(tp, 0); | |
7718 | ||
7719 | add_timer(&tp->timer); | |
7720 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
7721 | tg3_enable_ints(tp); | |
7722 | ||
7723 | tg3_full_unlock(tp); | |
7724 | ||
7725 | netif_start_queue(dev); | |
7726 | ||
7727 | return 0; | |
7728 | } | |
7729 | ||
7730 | #if 0 | |
7731 | /*static*/ void tg3_dump_state(struct tg3 *tp) | |
7732 | { | |
7733 | u32 val32, val32_2, val32_3, val32_4, val32_5; | |
7734 | u16 val16; | |
7735 | int i; | |
7736 | ||
7737 | pci_read_config_word(tp->pdev, PCI_STATUS, &val16); | |
7738 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32); | |
7739 | printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n", | |
7740 | val16, val32); | |
7741 | ||
7742 | /* MAC block */ | |
7743 | printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n", | |
7744 | tr32(MAC_MODE), tr32(MAC_STATUS)); | |
7745 | printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n", | |
7746 | tr32(MAC_EVENT), tr32(MAC_LED_CTRL)); | |
7747 | printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n", | |
7748 | tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS)); | |
7749 | printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n", | |
7750 | tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS)); | |
7751 | ||
7752 | /* Send data initiator control block */ | |
7753 | printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n", | |
7754 | tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS)); | |
7755 | printk(" SNDDATAI_STATSCTRL[%08x]\n", | |
7756 | tr32(SNDDATAI_STATSCTRL)); | |
7757 | ||
7758 | /* Send data completion control block */ | |
7759 | printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE)); | |
7760 | ||
7761 | /* Send BD ring selector block */ | |
7762 | printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n", | |
7763 | tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS)); | |
7764 | ||
7765 | /* Send BD initiator control block */ | |
7766 | printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n", | |
7767 | tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS)); | |
7768 | ||
7769 | /* Send BD completion control block */ | |
7770 | printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE)); | |
7771 | ||
7772 | /* Receive list placement control block */ | |
7773 | printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n", | |
7774 | tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS)); | |
7775 | printk(" RCVLPC_STATSCTRL[%08x]\n", | |
7776 | tr32(RCVLPC_STATSCTRL)); | |
7777 | ||
7778 | /* Receive data and receive BD initiator control block */ | |
7779 | printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n", | |
7780 | tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS)); | |
7781 | ||
7782 | /* Receive data completion control block */ | |
7783 | printk("DEBUG: RCVDCC_MODE[%08x]\n", | |
7784 | tr32(RCVDCC_MODE)); | |
7785 | ||
7786 | /* Receive BD initiator control block */ | |
7787 | printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n", | |
7788 | tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS)); | |
7789 | ||
7790 | /* Receive BD completion control block */ | |
7791 | printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n", | |
7792 | tr32(RCVCC_MODE), tr32(RCVCC_STATUS)); | |
7793 | ||
7794 | /* Receive list selector control block */ | |
7795 | printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n", | |
7796 | tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS)); | |
7797 | ||
7798 | /* Mbuf cluster free block */ | |
7799 | printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n", | |
7800 | tr32(MBFREE_MODE), tr32(MBFREE_STATUS)); | |
7801 | ||
7802 | /* Host coalescing control block */ | |
7803 | printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n", | |
7804 | tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS)); | |
7805 | printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n", | |
7806 | tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7807 | tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW)); | |
7808 | printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n", | |
7809 | tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7810 | tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW)); | |
7811 | printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n", | |
7812 | tr32(HOSTCC_STATS_BLK_NIC_ADDR)); | |
7813 | printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n", | |
7814 | tr32(HOSTCC_STATUS_BLK_NIC_ADDR)); | |
7815 | ||
7816 | /* Memory arbiter control block */ | |
7817 | printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n", | |
7818 | tr32(MEMARB_MODE), tr32(MEMARB_STATUS)); | |
7819 | ||
7820 | /* Buffer manager control block */ | |
7821 | printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n", | |
7822 | tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS)); | |
7823 | printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n", | |
7824 | tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE)); | |
7825 | printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] " | |
7826 | "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n", | |
7827 | tr32(BUFMGR_DMA_DESC_POOL_ADDR), | |
7828 | tr32(BUFMGR_DMA_DESC_POOL_SIZE)); | |
7829 | ||
7830 | /* Read DMA control block */ | |
7831 | printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n", | |
7832 | tr32(RDMAC_MODE), tr32(RDMAC_STATUS)); | |
7833 | ||
7834 | /* Write DMA control block */ | |
7835 | printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n", | |
7836 | tr32(WDMAC_MODE), tr32(WDMAC_STATUS)); | |
7837 | ||
7838 | /* DMA completion block */ | |
7839 | printk("DEBUG: DMAC_MODE[%08x]\n", | |
7840 | tr32(DMAC_MODE)); | |
7841 | ||
7842 | /* GRC block */ | |
7843 | printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n", | |
7844 | tr32(GRC_MODE), tr32(GRC_MISC_CFG)); | |
7845 | printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n", | |
7846 | tr32(GRC_LOCAL_CTRL)); | |
7847 | ||
7848 | /* TG3_BDINFOs */ | |
7849 | printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n", | |
7850 | tr32(RCVDBDI_JUMBO_BD + 0x0), | |
7851 | tr32(RCVDBDI_JUMBO_BD + 0x4), | |
7852 | tr32(RCVDBDI_JUMBO_BD + 0x8), | |
7853 | tr32(RCVDBDI_JUMBO_BD + 0xc)); | |
7854 | printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n", | |
7855 | tr32(RCVDBDI_STD_BD + 0x0), | |
7856 | tr32(RCVDBDI_STD_BD + 0x4), | |
7857 | tr32(RCVDBDI_STD_BD + 0x8), | |
7858 | tr32(RCVDBDI_STD_BD + 0xc)); | |
7859 | printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n", | |
7860 | tr32(RCVDBDI_MINI_BD + 0x0), | |
7861 | tr32(RCVDBDI_MINI_BD + 0x4), | |
7862 | tr32(RCVDBDI_MINI_BD + 0x8), | |
7863 | tr32(RCVDBDI_MINI_BD + 0xc)); | |
7864 | ||
7865 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32); | |
7866 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2); | |
7867 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3); | |
7868 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4); | |
7869 | printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n", | |
7870 | val32, val32_2, val32_3, val32_4); | |
7871 | ||
7872 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32); | |
7873 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2); | |
7874 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3); | |
7875 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4); | |
7876 | printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n", | |
7877 | val32, val32_2, val32_3, val32_4); | |
7878 | ||
7879 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32); | |
7880 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2); | |
7881 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3); | |
7882 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4); | |
7883 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5); | |
7884 | printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n", | |
7885 | val32, val32_2, val32_3, val32_4, val32_5); | |
7886 | ||
7887 | /* SW status block */ | |
7888 | printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
7889 | tp->hw_status->status, | |
7890 | tp->hw_status->status_tag, | |
7891 | tp->hw_status->rx_jumbo_consumer, | |
7892 | tp->hw_status->rx_consumer, | |
7893 | tp->hw_status->rx_mini_consumer, | |
7894 | tp->hw_status->idx[0].rx_producer, | |
7895 | tp->hw_status->idx[0].tx_consumer); | |
7896 | ||
7897 | /* SW statistics block */ | |
7898 | printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n", | |
7899 | ((u32 *)tp->hw_stats)[0], | |
7900 | ((u32 *)tp->hw_stats)[1], | |
7901 | ((u32 *)tp->hw_stats)[2], | |
7902 | ((u32 *)tp->hw_stats)[3]); | |
7903 | ||
7904 | /* Mailboxes */ | |
7905 | printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n", | |
7906 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0), | |
7907 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4), | |
7908 | tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0), | |
7909 | tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4)); | |
7910 | ||
7911 | /* NIC side send descriptors. */ | |
7912 | for (i = 0; i < 6; i++) { | |
7913 | unsigned long txd; | |
7914 | ||
7915 | txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC | |
7916 | + (i * sizeof(struct tg3_tx_buffer_desc)); | |
7917 | printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n", | |
7918 | i, | |
7919 | readl(txd + 0x0), readl(txd + 0x4), | |
7920 | readl(txd + 0x8), readl(txd + 0xc)); | |
7921 | } | |
7922 | ||
7923 | /* NIC side RX descriptors. */ | |
7924 | for (i = 0; i < 6; i++) { | |
7925 | unsigned long rxd; | |
7926 | ||
7927 | rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC | |
7928 | + (i * sizeof(struct tg3_rx_buffer_desc)); | |
7929 | printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n", | |
7930 | i, | |
7931 | readl(rxd + 0x0), readl(rxd + 0x4), | |
7932 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
7933 | rxd += (4 * sizeof(u32)); | |
7934 | printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n", | |
7935 | i, | |
7936 | readl(rxd + 0x0), readl(rxd + 0x4), | |
7937 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
7938 | } | |
7939 | ||
7940 | for (i = 0; i < 6; i++) { | |
7941 | unsigned long rxd; | |
7942 | ||
7943 | rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC | |
7944 | + (i * sizeof(struct tg3_rx_buffer_desc)); | |
7945 | printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n", | |
7946 | i, | |
7947 | readl(rxd + 0x0), readl(rxd + 0x4), | |
7948 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
7949 | rxd += (4 * sizeof(u32)); | |
7950 | printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n", | |
7951 | i, | |
7952 | readl(rxd + 0x0), readl(rxd + 0x4), | |
7953 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
7954 | } | |
7955 | } | |
7956 | #endif | |
7957 | ||
7958 | static struct net_device_stats *tg3_get_stats(struct net_device *); | |
7959 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); | |
7960 | ||
7961 | static int tg3_close(struct net_device *dev) | |
7962 | { | |
7963 | struct tg3 *tp = netdev_priv(dev); | |
7964 | ||
7965 | napi_disable(&tp->napi); | |
7966 | cancel_work_sync(&tp->reset_task); | |
7967 | ||
7968 | netif_stop_queue(dev); | |
7969 | ||
7970 | del_timer_sync(&tp->timer); | |
7971 | ||
7972 | tg3_full_lock(tp, 1); | |
7973 | #if 0 | |
7974 | tg3_dump_state(tp); | |
7975 | #endif | |
7976 | ||
7977 | tg3_disable_ints(tp); | |
7978 | ||
7979 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
7980 | tg3_free_rings(tp); | |
7981 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
7982 | ||
7983 | tg3_full_unlock(tp); | |
7984 | ||
7985 | free_irq(tp->pdev->irq, dev); | |
7986 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7987 | pci_disable_msi(tp->pdev); | |
7988 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
7989 | } | |
7990 | ||
7991 | memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev), | |
7992 | sizeof(tp->net_stats_prev)); | |
7993 | memcpy(&tp->estats_prev, tg3_get_estats(tp), | |
7994 | sizeof(tp->estats_prev)); | |
7995 | ||
7996 | tg3_free_consistent(tp); | |
7997 | ||
7998 | tg3_set_power_state(tp, PCI_D3hot); | |
7999 | ||
8000 | netif_carrier_off(tp->dev); | |
8001 | ||
8002 | return 0; | |
8003 | } | |
8004 | ||
8005 | static inline unsigned long get_stat64(tg3_stat64_t *val) | |
8006 | { | |
8007 | unsigned long ret; | |
8008 | ||
8009 | #if (BITS_PER_LONG == 32) | |
8010 | ret = val->low; | |
8011 | #else | |
8012 | ret = ((u64)val->high << 32) | ((u64)val->low); | |
8013 | #endif | |
8014 | return ret; | |
8015 | } | |
8016 | ||
8017 | static inline u64 get_estat64(tg3_stat64_t *val) | |
8018 | { | |
8019 | return ((u64)val->high << 32) | ((u64)val->low); | |
8020 | } | |
8021 | ||
8022 | static unsigned long calc_crc_errors(struct tg3 *tp) | |
8023 | { | |
8024 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
8025 | ||
8026 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
8027 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
8028 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
8029 | u32 val; | |
8030 | ||
8031 | spin_lock_bh(&tp->lock); | |
8032 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { | |
8033 | tg3_writephy(tp, MII_TG3_TEST1, | |
8034 | val | MII_TG3_TEST1_CRC_EN); | |
8035 | tg3_readphy(tp, 0x14, &val); | |
8036 | } else | |
8037 | val = 0; | |
8038 | spin_unlock_bh(&tp->lock); | |
8039 | ||
8040 | tp->phy_crc_errors += val; | |
8041 | ||
8042 | return tp->phy_crc_errors; | |
8043 | } | |
8044 | ||
8045 | return get_stat64(&hw_stats->rx_fcs_errors); | |
8046 | } | |
8047 | ||
8048 | #define ESTAT_ADD(member) \ | |
8049 | estats->member = old_estats->member + \ | |
8050 | get_estat64(&hw_stats->member) | |
8051 | ||
8052 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
8053 | { | |
8054 | struct tg3_ethtool_stats *estats = &tp->estats; | |
8055 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
8056 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
8057 | ||
8058 | if (!hw_stats) | |
8059 | return old_estats; | |
8060 | ||
8061 | ESTAT_ADD(rx_octets); | |
8062 | ESTAT_ADD(rx_fragments); | |
8063 | ESTAT_ADD(rx_ucast_packets); | |
8064 | ESTAT_ADD(rx_mcast_packets); | |
8065 | ESTAT_ADD(rx_bcast_packets); | |
8066 | ESTAT_ADD(rx_fcs_errors); | |
8067 | ESTAT_ADD(rx_align_errors); | |
8068 | ESTAT_ADD(rx_xon_pause_rcvd); | |
8069 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
8070 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
8071 | ESTAT_ADD(rx_xoff_entered); | |
8072 | ESTAT_ADD(rx_frame_too_long_errors); | |
8073 | ESTAT_ADD(rx_jabbers); | |
8074 | ESTAT_ADD(rx_undersize_packets); | |
8075 | ESTAT_ADD(rx_in_length_errors); | |
8076 | ESTAT_ADD(rx_out_length_errors); | |
8077 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
8078 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
8079 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
8080 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
8081 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
8082 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
8083 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
8084 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
8085 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
8086 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
8087 | ||
8088 | ESTAT_ADD(tx_octets); | |
8089 | ESTAT_ADD(tx_collisions); | |
8090 | ESTAT_ADD(tx_xon_sent); | |
8091 | ESTAT_ADD(tx_xoff_sent); | |
8092 | ESTAT_ADD(tx_flow_control); | |
8093 | ESTAT_ADD(tx_mac_errors); | |
8094 | ESTAT_ADD(tx_single_collisions); | |
8095 | ESTAT_ADD(tx_mult_collisions); | |
8096 | ESTAT_ADD(tx_deferred); | |
8097 | ESTAT_ADD(tx_excessive_collisions); | |
8098 | ESTAT_ADD(tx_late_collisions); | |
8099 | ESTAT_ADD(tx_collide_2times); | |
8100 | ESTAT_ADD(tx_collide_3times); | |
8101 | ESTAT_ADD(tx_collide_4times); | |
8102 | ESTAT_ADD(tx_collide_5times); | |
8103 | ESTAT_ADD(tx_collide_6times); | |
8104 | ESTAT_ADD(tx_collide_7times); | |
8105 | ESTAT_ADD(tx_collide_8times); | |
8106 | ESTAT_ADD(tx_collide_9times); | |
8107 | ESTAT_ADD(tx_collide_10times); | |
8108 | ESTAT_ADD(tx_collide_11times); | |
8109 | ESTAT_ADD(tx_collide_12times); | |
8110 | ESTAT_ADD(tx_collide_13times); | |
8111 | ESTAT_ADD(tx_collide_14times); | |
8112 | ESTAT_ADD(tx_collide_15times); | |
8113 | ESTAT_ADD(tx_ucast_packets); | |
8114 | ESTAT_ADD(tx_mcast_packets); | |
8115 | ESTAT_ADD(tx_bcast_packets); | |
8116 | ESTAT_ADD(tx_carrier_sense_errors); | |
8117 | ESTAT_ADD(tx_discards); | |
8118 | ESTAT_ADD(tx_errors); | |
8119 | ||
8120 | ESTAT_ADD(dma_writeq_full); | |
8121 | ESTAT_ADD(dma_write_prioq_full); | |
8122 | ESTAT_ADD(rxbds_empty); | |
8123 | ESTAT_ADD(rx_discards); | |
8124 | ESTAT_ADD(rx_errors); | |
8125 | ESTAT_ADD(rx_threshold_hit); | |
8126 | ||
8127 | ESTAT_ADD(dma_readq_full); | |
8128 | ESTAT_ADD(dma_read_prioq_full); | |
8129 | ESTAT_ADD(tx_comp_queue_full); | |
8130 | ||
8131 | ESTAT_ADD(ring_set_send_prod_index); | |
8132 | ESTAT_ADD(ring_status_update); | |
8133 | ESTAT_ADD(nic_irqs); | |
8134 | ESTAT_ADD(nic_avoided_irqs); | |
8135 | ESTAT_ADD(nic_tx_threshold_hit); | |
8136 | ||
8137 | return estats; | |
8138 | } | |
8139 | ||
8140 | static struct net_device_stats *tg3_get_stats(struct net_device *dev) | |
8141 | { | |
8142 | struct tg3 *tp = netdev_priv(dev); | |
8143 | struct net_device_stats *stats = &tp->net_stats; | |
8144 | struct net_device_stats *old_stats = &tp->net_stats_prev; | |
8145 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
8146 | ||
8147 | if (!hw_stats) | |
8148 | return old_stats; | |
8149 | ||
8150 | stats->rx_packets = old_stats->rx_packets + | |
8151 | get_stat64(&hw_stats->rx_ucast_packets) + | |
8152 | get_stat64(&hw_stats->rx_mcast_packets) + | |
8153 | get_stat64(&hw_stats->rx_bcast_packets); | |
8154 | ||
8155 | stats->tx_packets = old_stats->tx_packets + | |
8156 | get_stat64(&hw_stats->tx_ucast_packets) + | |
8157 | get_stat64(&hw_stats->tx_mcast_packets) + | |
8158 | get_stat64(&hw_stats->tx_bcast_packets); | |
8159 | ||
8160 | stats->rx_bytes = old_stats->rx_bytes + | |
8161 | get_stat64(&hw_stats->rx_octets); | |
8162 | stats->tx_bytes = old_stats->tx_bytes + | |
8163 | get_stat64(&hw_stats->tx_octets); | |
8164 | ||
8165 | stats->rx_errors = old_stats->rx_errors + | |
8166 | get_stat64(&hw_stats->rx_errors); | |
8167 | stats->tx_errors = old_stats->tx_errors + | |
8168 | get_stat64(&hw_stats->tx_errors) + | |
8169 | get_stat64(&hw_stats->tx_mac_errors) + | |
8170 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
8171 | get_stat64(&hw_stats->tx_discards); | |
8172 | ||
8173 | stats->multicast = old_stats->multicast + | |
8174 | get_stat64(&hw_stats->rx_mcast_packets); | |
8175 | stats->collisions = old_stats->collisions + | |
8176 | get_stat64(&hw_stats->tx_collisions); | |
8177 | ||
8178 | stats->rx_length_errors = old_stats->rx_length_errors + | |
8179 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
8180 | get_stat64(&hw_stats->rx_undersize_packets); | |
8181 | ||
8182 | stats->rx_over_errors = old_stats->rx_over_errors + | |
8183 | get_stat64(&hw_stats->rxbds_empty); | |
8184 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
8185 | get_stat64(&hw_stats->rx_align_errors); | |
8186 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
8187 | get_stat64(&hw_stats->tx_discards); | |
8188 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
8189 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
8190 | ||
8191 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
8192 | calc_crc_errors(tp); | |
8193 | ||
8194 | stats->rx_missed_errors = old_stats->rx_missed_errors + | |
8195 | get_stat64(&hw_stats->rx_discards); | |
8196 | ||
8197 | return stats; | |
8198 | } | |
8199 | ||
8200 | static inline u32 calc_crc(unsigned char *buf, int len) | |
8201 | { | |
8202 | u32 reg; | |
8203 | u32 tmp; | |
8204 | int j, k; | |
8205 | ||
8206 | reg = 0xffffffff; | |
8207 | ||
8208 | for (j = 0; j < len; j++) { | |
8209 | reg ^= buf[j]; | |
8210 | ||
8211 | for (k = 0; k < 8; k++) { | |
8212 | tmp = reg & 0x01; | |
8213 | ||
8214 | reg >>= 1; | |
8215 | ||
8216 | if (tmp) { | |
8217 | reg ^= 0xedb88320; | |
8218 | } | |
8219 | } | |
8220 | } | |
8221 | ||
8222 | return ~reg; | |
8223 | } | |
8224 | ||
8225 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
8226 | { | |
8227 | /* accept or reject all multicast frames */ | |
8228 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
8229 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
8230 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
8231 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
8232 | } | |
8233 | ||
8234 | static void __tg3_set_rx_mode(struct net_device *dev) | |
8235 | { | |
8236 | struct tg3 *tp = netdev_priv(dev); | |
8237 | u32 rx_mode; | |
8238 | ||
8239 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
8240 | RX_MODE_KEEP_VLAN_TAG); | |
8241 | ||
8242 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG | |
8243 | * flag clear. | |
8244 | */ | |
8245 | #if TG3_VLAN_TAG_USED | |
8246 | if (!tp->vlgrp && | |
8247 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
8248 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
8249 | #else | |
8250 | /* By definition, VLAN is disabled always in this | |
8251 | * case. | |
8252 | */ | |
8253 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
8254 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
8255 | #endif | |
8256 | ||
8257 | if (dev->flags & IFF_PROMISC) { | |
8258 | /* Promiscuous mode. */ | |
8259 | rx_mode |= RX_MODE_PROMISC; | |
8260 | } else if (dev->flags & IFF_ALLMULTI) { | |
8261 | /* Accept all multicast. */ | |
8262 | tg3_set_multi (tp, 1); | |
8263 | } else if (dev->mc_count < 1) { | |
8264 | /* Reject all multicast. */ | |
8265 | tg3_set_multi (tp, 0); | |
8266 | } else { | |
8267 | /* Accept one or more multicast(s). */ | |
8268 | struct dev_mc_list *mclist; | |
8269 | unsigned int i; | |
8270 | u32 mc_filter[4] = { 0, }; | |
8271 | u32 regidx; | |
8272 | u32 bit; | |
8273 | u32 crc; | |
8274 | ||
8275 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
8276 | i++, mclist = mclist->next) { | |
8277 | ||
8278 | crc = calc_crc (mclist->dmi_addr, ETH_ALEN); | |
8279 | bit = ~crc & 0x7f; | |
8280 | regidx = (bit & 0x60) >> 5; | |
8281 | bit &= 0x1f; | |
8282 | mc_filter[regidx] |= (1 << bit); | |
8283 | } | |
8284 | ||
8285 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
8286 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
8287 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
8288 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
8289 | } | |
8290 | ||
8291 | if (rx_mode != tp->rx_mode) { | |
8292 | tp->rx_mode = rx_mode; | |
8293 | tw32_f(MAC_RX_MODE, rx_mode); | |
8294 | udelay(10); | |
8295 | } | |
8296 | } | |
8297 | ||
8298 | static void tg3_set_rx_mode(struct net_device *dev) | |
8299 | { | |
8300 | struct tg3 *tp = netdev_priv(dev); | |
8301 | ||
8302 | if (!netif_running(dev)) | |
8303 | return; | |
8304 | ||
8305 | tg3_full_lock(tp, 0); | |
8306 | __tg3_set_rx_mode(dev); | |
8307 | tg3_full_unlock(tp); | |
8308 | } | |
8309 | ||
8310 | #define TG3_REGDUMP_LEN (32 * 1024) | |
8311 | ||
8312 | static int tg3_get_regs_len(struct net_device *dev) | |
8313 | { | |
8314 | return TG3_REGDUMP_LEN; | |
8315 | } | |
8316 | ||
8317 | static void tg3_get_regs(struct net_device *dev, | |
8318 | struct ethtool_regs *regs, void *_p) | |
8319 | { | |
8320 | u32 *p = _p; | |
8321 | struct tg3 *tp = netdev_priv(dev); | |
8322 | u8 *orig_p = _p; | |
8323 | int i; | |
8324 | ||
8325 | regs->version = 0; | |
8326 | ||
8327 | memset(p, 0, TG3_REGDUMP_LEN); | |
8328 | ||
8329 | if (tp->link_config.phy_is_low_power) | |
8330 | return; | |
8331 | ||
8332 | tg3_full_lock(tp, 0); | |
8333 | ||
8334 | #define __GET_REG32(reg) (*(p)++ = tr32(reg)) | |
8335 | #define GET_REG32_LOOP(base,len) \ | |
8336 | do { p = (u32 *)(orig_p + (base)); \ | |
8337 | for (i = 0; i < len; i += 4) \ | |
8338 | __GET_REG32((base) + i); \ | |
8339 | } while (0) | |
8340 | #define GET_REG32_1(reg) \ | |
8341 | do { p = (u32 *)(orig_p + (reg)); \ | |
8342 | __GET_REG32((reg)); \ | |
8343 | } while (0) | |
8344 | ||
8345 | GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0); | |
8346 | GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200); | |
8347 | GET_REG32_LOOP(MAC_MODE, 0x4f0); | |
8348 | GET_REG32_LOOP(SNDDATAI_MODE, 0xe0); | |
8349 | GET_REG32_1(SNDDATAC_MODE); | |
8350 | GET_REG32_LOOP(SNDBDS_MODE, 0x80); | |
8351 | GET_REG32_LOOP(SNDBDI_MODE, 0x48); | |
8352 | GET_REG32_1(SNDBDC_MODE); | |
8353 | GET_REG32_LOOP(RCVLPC_MODE, 0x20); | |
8354 | GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c); | |
8355 | GET_REG32_LOOP(RCVDBDI_MODE, 0x0c); | |
8356 | GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c); | |
8357 | GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44); | |
8358 | GET_REG32_1(RCVDCC_MODE); | |
8359 | GET_REG32_LOOP(RCVBDI_MODE, 0x20); | |
8360 | GET_REG32_LOOP(RCVCC_MODE, 0x14); | |
8361 | GET_REG32_LOOP(RCVLSC_MODE, 0x08); | |
8362 | GET_REG32_1(MBFREE_MODE); | |
8363 | GET_REG32_LOOP(HOSTCC_MODE, 0x100); | |
8364 | GET_REG32_LOOP(MEMARB_MODE, 0x10); | |
8365 | GET_REG32_LOOP(BUFMGR_MODE, 0x58); | |
8366 | GET_REG32_LOOP(RDMAC_MODE, 0x08); | |
8367 | GET_REG32_LOOP(WDMAC_MODE, 0x08); | |
8368 | GET_REG32_1(RX_CPU_MODE); | |
8369 | GET_REG32_1(RX_CPU_STATE); | |
8370 | GET_REG32_1(RX_CPU_PGMCTR); | |
8371 | GET_REG32_1(RX_CPU_HWBKPT); | |
8372 | GET_REG32_1(TX_CPU_MODE); | |
8373 | GET_REG32_1(TX_CPU_STATE); | |
8374 | GET_REG32_1(TX_CPU_PGMCTR); | |
8375 | GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110); | |
8376 | GET_REG32_LOOP(FTQ_RESET, 0x120); | |
8377 | GET_REG32_LOOP(MSGINT_MODE, 0x0c); | |
8378 | GET_REG32_1(DMAC_MODE); | |
8379 | GET_REG32_LOOP(GRC_MODE, 0x4c); | |
8380 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
8381 | GET_REG32_LOOP(NVRAM_CMD, 0x24); | |
8382 | ||
8383 | #undef __GET_REG32 | |
8384 | #undef GET_REG32_LOOP | |
8385 | #undef GET_REG32_1 | |
8386 | ||
8387 | tg3_full_unlock(tp); | |
8388 | } | |
8389 | ||
8390 | static int tg3_get_eeprom_len(struct net_device *dev) | |
8391 | { | |
8392 | struct tg3 *tp = netdev_priv(dev); | |
8393 | ||
8394 | return tp->nvram_size; | |
8395 | } | |
8396 | ||
8397 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val); | |
8398 | static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val); | |
8399 | static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val); | |
8400 | ||
8401 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
8402 | { | |
8403 | struct tg3 *tp = netdev_priv(dev); | |
8404 | int ret; | |
8405 | u8 *pd; | |
8406 | u32 i, offset, len, b_offset, b_count; | |
8407 | __le32 val; | |
8408 | ||
8409 | if (tp->link_config.phy_is_low_power) | |
8410 | return -EAGAIN; | |
8411 | ||
8412 | offset = eeprom->offset; | |
8413 | len = eeprom->len; | |
8414 | eeprom->len = 0; | |
8415 | ||
8416 | eeprom->magic = TG3_EEPROM_MAGIC; | |
8417 | ||
8418 | if (offset & 3) { | |
8419 | /* adjustments to start on required 4 byte boundary */ | |
8420 | b_offset = offset & 3; | |
8421 | b_count = 4 - b_offset; | |
8422 | if (b_count > len) { | |
8423 | /* i.e. offset=1 len=2 */ | |
8424 | b_count = len; | |
8425 | } | |
8426 | ret = tg3_nvram_read_le(tp, offset-b_offset, &val); | |
8427 | if (ret) | |
8428 | return ret; | |
8429 | memcpy(data, ((char*)&val) + b_offset, b_count); | |
8430 | len -= b_count; | |
8431 | offset += b_count; | |
8432 | eeprom->len += b_count; | |
8433 | } | |
8434 | ||
8435 | /* read bytes upto the last 4 byte boundary */ | |
8436 | pd = &data[eeprom->len]; | |
8437 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
8438 | ret = tg3_nvram_read_le(tp, offset + i, &val); | |
8439 | if (ret) { | |
8440 | eeprom->len += i; | |
8441 | return ret; | |
8442 | } | |
8443 | memcpy(pd + i, &val, 4); | |
8444 | } | |
8445 | eeprom->len += i; | |
8446 | ||
8447 | if (len & 3) { | |
8448 | /* read last bytes not ending on 4 byte boundary */ | |
8449 | pd = &data[eeprom->len]; | |
8450 | b_count = len & 3; | |
8451 | b_offset = offset + len - b_count; | |
8452 | ret = tg3_nvram_read_le(tp, b_offset, &val); | |
8453 | if (ret) | |
8454 | return ret; | |
8455 | memcpy(pd, &val, b_count); | |
8456 | eeprom->len += b_count; | |
8457 | } | |
8458 | return 0; | |
8459 | } | |
8460 | ||
8461 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); | |
8462 | ||
8463 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
8464 | { | |
8465 | struct tg3 *tp = netdev_priv(dev); | |
8466 | int ret; | |
8467 | u32 offset, len, b_offset, odd_len; | |
8468 | u8 *buf; | |
8469 | __le32 start, end; | |
8470 | ||
8471 | if (tp->link_config.phy_is_low_power) | |
8472 | return -EAGAIN; | |
8473 | ||
8474 | if (eeprom->magic != TG3_EEPROM_MAGIC) | |
8475 | return -EINVAL; | |
8476 | ||
8477 | offset = eeprom->offset; | |
8478 | len = eeprom->len; | |
8479 | ||
8480 | if ((b_offset = (offset & 3))) { | |
8481 | /* adjustments to start on required 4 byte boundary */ | |
8482 | ret = tg3_nvram_read_le(tp, offset-b_offset, &start); | |
8483 | if (ret) | |
8484 | return ret; | |
8485 | len += b_offset; | |
8486 | offset &= ~3; | |
8487 | if (len < 4) | |
8488 | len = 4; | |
8489 | } | |
8490 | ||
8491 | odd_len = 0; | |
8492 | if (len & 3) { | |
8493 | /* adjustments to end on required 4 byte boundary */ | |
8494 | odd_len = 1; | |
8495 | len = (len + 3) & ~3; | |
8496 | ret = tg3_nvram_read_le(tp, offset+len-4, &end); | |
8497 | if (ret) | |
8498 | return ret; | |
8499 | } | |
8500 | ||
8501 | buf = data; | |
8502 | if (b_offset || odd_len) { | |
8503 | buf = kmalloc(len, GFP_KERNEL); | |
8504 | if (!buf) | |
8505 | return -ENOMEM; | |
8506 | if (b_offset) | |
8507 | memcpy(buf, &start, 4); | |
8508 | if (odd_len) | |
8509 | memcpy(buf+len-4, &end, 4); | |
8510 | memcpy(buf + b_offset, data, eeprom->len); | |
8511 | } | |
8512 | ||
8513 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
8514 | ||
8515 | if (buf != data) | |
8516 | kfree(buf); | |
8517 | ||
8518 | return ret; | |
8519 | } | |
8520 | ||
8521 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
8522 | { | |
8523 | struct tg3 *tp = netdev_priv(dev); | |
8524 | ||
8525 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
8526 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
8527 | return -EAGAIN; | |
8528 | return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd); | |
8529 | } | |
8530 | ||
8531 | cmd->supported = (SUPPORTED_Autoneg); | |
8532 | ||
8533 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
8534 | cmd->supported |= (SUPPORTED_1000baseT_Half | | |
8535 | SUPPORTED_1000baseT_Full); | |
8536 | ||
8537 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { | |
8538 | cmd->supported |= (SUPPORTED_100baseT_Half | | |
8539 | SUPPORTED_100baseT_Full | | |
8540 | SUPPORTED_10baseT_Half | | |
8541 | SUPPORTED_10baseT_Full | | |
8542 | SUPPORTED_TP); | |
8543 | cmd->port = PORT_TP; | |
8544 | } else { | |
8545 | cmd->supported |= SUPPORTED_FIBRE; | |
8546 | cmd->port = PORT_FIBRE; | |
8547 | } | |
8548 | ||
8549 | cmd->advertising = tp->link_config.advertising; | |
8550 | if (netif_running(dev)) { | |
8551 | cmd->speed = tp->link_config.active_speed; | |
8552 | cmd->duplex = tp->link_config.active_duplex; | |
8553 | } | |
8554 | cmd->phy_address = PHY_ADDR; | |
8555 | cmd->transceiver = XCVR_INTERNAL; | |
8556 | cmd->autoneg = tp->link_config.autoneg; | |
8557 | cmd->maxtxpkt = 0; | |
8558 | cmd->maxrxpkt = 0; | |
8559 | return 0; | |
8560 | } | |
8561 | ||
8562 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
8563 | { | |
8564 | struct tg3 *tp = netdev_priv(dev); | |
8565 | ||
8566 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
8567 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
8568 | return -EAGAIN; | |
8569 | return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd); | |
8570 | } | |
8571 | ||
8572 | if (cmd->autoneg != AUTONEG_ENABLE && | |
8573 | cmd->autoneg != AUTONEG_DISABLE) | |
8574 | return -EINVAL; | |
8575 | ||
8576 | if (cmd->autoneg == AUTONEG_DISABLE && | |
8577 | cmd->duplex != DUPLEX_FULL && | |
8578 | cmd->duplex != DUPLEX_HALF) | |
8579 | return -EINVAL; | |
8580 | ||
8581 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
8582 | u32 mask = ADVERTISED_Autoneg | | |
8583 | ADVERTISED_Pause | | |
8584 | ADVERTISED_Asym_Pause; | |
8585 | ||
8586 | if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY)) | |
8587 | mask |= ADVERTISED_1000baseT_Half | | |
8588 | ADVERTISED_1000baseT_Full; | |
8589 | ||
8590 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
8591 | mask |= ADVERTISED_100baseT_Half | | |
8592 | ADVERTISED_100baseT_Full | | |
8593 | ADVERTISED_10baseT_Half | | |
8594 | ADVERTISED_10baseT_Full | | |
8595 | ADVERTISED_TP; | |
8596 | else | |
8597 | mask |= ADVERTISED_FIBRE; | |
8598 | ||
8599 | if (cmd->advertising & ~mask) | |
8600 | return -EINVAL; | |
8601 | ||
8602 | mask &= (ADVERTISED_1000baseT_Half | | |
8603 | ADVERTISED_1000baseT_Full | | |
8604 | ADVERTISED_100baseT_Half | | |
8605 | ADVERTISED_100baseT_Full | | |
8606 | ADVERTISED_10baseT_Half | | |
8607 | ADVERTISED_10baseT_Full); | |
8608 | ||
8609 | cmd->advertising &= mask; | |
8610 | } else { | |
8611 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { | |
8612 | if (cmd->speed != SPEED_1000) | |
8613 | return -EINVAL; | |
8614 | ||
8615 | if (cmd->duplex != DUPLEX_FULL) | |
8616 | return -EINVAL; | |
8617 | } else { | |
8618 | if (cmd->speed != SPEED_100 && | |
8619 | cmd->speed != SPEED_10) | |
8620 | return -EINVAL; | |
8621 | } | |
8622 | } | |
8623 | ||
8624 | tg3_full_lock(tp, 0); | |
8625 | ||
8626 | tp->link_config.autoneg = cmd->autoneg; | |
8627 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
8628 | tp->link_config.advertising = (cmd->advertising | | |
8629 | ADVERTISED_Autoneg); | |
8630 | tp->link_config.speed = SPEED_INVALID; | |
8631 | tp->link_config.duplex = DUPLEX_INVALID; | |
8632 | } else { | |
8633 | tp->link_config.advertising = 0; | |
8634 | tp->link_config.speed = cmd->speed; | |
8635 | tp->link_config.duplex = cmd->duplex; | |
8636 | } | |
8637 | ||
8638 | tp->link_config.orig_speed = tp->link_config.speed; | |
8639 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
8640 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
8641 | ||
8642 | if (netif_running(dev)) | |
8643 | tg3_setup_phy(tp, 1); | |
8644 | ||
8645 | tg3_full_unlock(tp); | |
8646 | ||
8647 | return 0; | |
8648 | } | |
8649 | ||
8650 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
8651 | { | |
8652 | struct tg3 *tp = netdev_priv(dev); | |
8653 | ||
8654 | strcpy(info->driver, DRV_MODULE_NAME); | |
8655 | strcpy(info->version, DRV_MODULE_VERSION); | |
8656 | strcpy(info->fw_version, tp->fw_ver); | |
8657 | strcpy(info->bus_info, pci_name(tp->pdev)); | |
8658 | } | |
8659 | ||
8660 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
8661 | { | |
8662 | struct tg3 *tp = netdev_priv(dev); | |
8663 | ||
8664 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && | |
8665 | device_can_wakeup(&tp->pdev->dev)) | |
8666 | wol->supported = WAKE_MAGIC; | |
8667 | else | |
8668 | wol->supported = 0; | |
8669 | wol->wolopts = 0; | |
8670 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && | |
8671 | device_can_wakeup(&tp->pdev->dev)) | |
8672 | wol->wolopts = WAKE_MAGIC; | |
8673 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
8674 | } | |
8675 | ||
8676 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
8677 | { | |
8678 | struct tg3 *tp = netdev_priv(dev); | |
8679 | struct device *dp = &tp->pdev->dev; | |
8680 | ||
8681 | if (wol->wolopts & ~WAKE_MAGIC) | |
8682 | return -EINVAL; | |
8683 | if ((wol->wolopts & WAKE_MAGIC) && | |
8684 | !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp))) | |
8685 | return -EINVAL; | |
8686 | ||
8687 | spin_lock_bh(&tp->lock); | |
8688 | if (wol->wolopts & WAKE_MAGIC) { | |
8689 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; | |
8690 | device_set_wakeup_enable(dp, true); | |
8691 | } else { | |
8692 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; | |
8693 | device_set_wakeup_enable(dp, false); | |
8694 | } | |
8695 | spin_unlock_bh(&tp->lock); | |
8696 | ||
8697 | return 0; | |
8698 | } | |
8699 | ||
8700 | static u32 tg3_get_msglevel(struct net_device *dev) | |
8701 | { | |
8702 | struct tg3 *tp = netdev_priv(dev); | |
8703 | return tp->msg_enable; | |
8704 | } | |
8705 | ||
8706 | static void tg3_set_msglevel(struct net_device *dev, u32 value) | |
8707 | { | |
8708 | struct tg3 *tp = netdev_priv(dev); | |
8709 | tp->msg_enable = value; | |
8710 | } | |
8711 | ||
8712 | static int tg3_set_tso(struct net_device *dev, u32 value) | |
8713 | { | |
8714 | struct tg3 *tp = netdev_priv(dev); | |
8715 | ||
8716 | if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
8717 | if (value) | |
8718 | return -EINVAL; | |
8719 | return 0; | |
8720 | } | |
8721 | if ((dev->features & NETIF_F_IPV6_CSUM) && | |
8722 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) { | |
8723 | if (value) { | |
8724 | dev->features |= NETIF_F_TSO6; | |
8725 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
8726 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
8727 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
8728 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8729 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
8730 | dev->features |= NETIF_F_TSO_ECN; | |
8731 | } else | |
8732 | dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN); | |
8733 | } | |
8734 | return ethtool_op_set_tso(dev, value); | |
8735 | } | |
8736 | ||
8737 | static int tg3_nway_reset(struct net_device *dev) | |
8738 | { | |
8739 | struct tg3 *tp = netdev_priv(dev); | |
8740 | int r; | |
8741 | ||
8742 | if (!netif_running(dev)) | |
8743 | return -EAGAIN; | |
8744 | ||
8745 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
8746 | return -EINVAL; | |
8747 | ||
8748 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
8749 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
8750 | return -EAGAIN; | |
8751 | r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]); | |
8752 | } else { | |
8753 | u32 bmcr; | |
8754 | ||
8755 | spin_lock_bh(&tp->lock); | |
8756 | r = -EINVAL; | |
8757 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
8758 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
8759 | ((bmcr & BMCR_ANENABLE) || | |
8760 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) { | |
8761 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | | |
8762 | BMCR_ANENABLE); | |
8763 | r = 0; | |
8764 | } | |
8765 | spin_unlock_bh(&tp->lock); | |
8766 | } | |
8767 | ||
8768 | return r; | |
8769 | } | |
8770 | ||
8771 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
8772 | { | |
8773 | struct tg3 *tp = netdev_priv(dev); | |
8774 | ||
8775 | ering->rx_max_pending = TG3_RX_RING_SIZE - 1; | |
8776 | ering->rx_mini_max_pending = 0; | |
8777 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) | |
8778 | ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1; | |
8779 | else | |
8780 | ering->rx_jumbo_max_pending = 0; | |
8781 | ||
8782 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
8783 | ||
8784 | ering->rx_pending = tp->rx_pending; | |
8785 | ering->rx_mini_pending = 0; | |
8786 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) | |
8787 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; | |
8788 | else | |
8789 | ering->rx_jumbo_pending = 0; | |
8790 | ||
8791 | ering->tx_pending = tp->tx_pending; | |
8792 | } | |
8793 | ||
8794 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
8795 | { | |
8796 | struct tg3 *tp = netdev_priv(dev); | |
8797 | int irq_sync = 0, err = 0; | |
8798 | ||
8799 | if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) || | |
8800 | (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || | |
8801 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || | |
8802 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
8803 | ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) && | |
8804 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) | |
8805 | return -EINVAL; | |
8806 | ||
8807 | if (netif_running(dev)) { | |
8808 | tg3_phy_stop(tp); | |
8809 | tg3_netif_stop(tp); | |
8810 | irq_sync = 1; | |
8811 | } | |
8812 | ||
8813 | tg3_full_lock(tp, irq_sync); | |
8814 | ||
8815 | tp->rx_pending = ering->rx_pending; | |
8816 | ||
8817 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && | |
8818 | tp->rx_pending > 63) | |
8819 | tp->rx_pending = 63; | |
8820 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
8821 | tp->tx_pending = ering->tx_pending; | |
8822 | ||
8823 | if (netif_running(dev)) { | |
8824 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
8825 | err = tg3_restart_hw(tp, 1); | |
8826 | if (!err) | |
8827 | tg3_netif_start(tp); | |
8828 | } | |
8829 | ||
8830 | tg3_full_unlock(tp); | |
8831 | ||
8832 | if (irq_sync && !err) | |
8833 | tg3_phy_start(tp); | |
8834 | ||
8835 | return err; | |
8836 | } | |
8837 | ||
8838 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
8839 | { | |
8840 | struct tg3 *tp = netdev_priv(dev); | |
8841 | ||
8842 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; | |
8843 | ||
8844 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) | |
8845 | epause->rx_pause = 1; | |
8846 | else | |
8847 | epause->rx_pause = 0; | |
8848 | ||
8849 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) | |
8850 | epause->tx_pause = 1; | |
8851 | else | |
8852 | epause->tx_pause = 0; | |
8853 | } | |
8854 | ||
8855 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
8856 | { | |
8857 | struct tg3 *tp = netdev_priv(dev); | |
8858 | int err = 0; | |
8859 | ||
8860 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
8861 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
8862 | return -EAGAIN; | |
8863 | ||
8864 | if (epause->autoneg) { | |
8865 | u32 newadv; | |
8866 | struct phy_device *phydev; | |
8867 | ||
8868 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; | |
8869 | ||
8870 | if (epause->rx_pause) { | |
8871 | if (epause->tx_pause) | |
8872 | newadv = ADVERTISED_Pause; | |
8873 | else | |
8874 | newadv = ADVERTISED_Pause | | |
8875 | ADVERTISED_Asym_Pause; | |
8876 | } else if (epause->tx_pause) { | |
8877 | newadv = ADVERTISED_Asym_Pause; | |
8878 | } else | |
8879 | newadv = 0; | |
8880 | ||
8881 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
8882 | u32 oldadv = phydev->advertising & | |
8883 | (ADVERTISED_Pause | | |
8884 | ADVERTISED_Asym_Pause); | |
8885 | if (oldadv != newadv) { | |
8886 | phydev->advertising &= | |
8887 | ~(ADVERTISED_Pause | | |
8888 | ADVERTISED_Asym_Pause); | |
8889 | phydev->advertising |= newadv; | |
8890 | err = phy_start_aneg(phydev); | |
8891 | } | |
8892 | } else { | |
8893 | tp->link_config.advertising &= | |
8894 | ~(ADVERTISED_Pause | | |
8895 | ADVERTISED_Asym_Pause); | |
8896 | tp->link_config.advertising |= newadv; | |
8897 | } | |
8898 | } else { | |
8899 | if (epause->rx_pause) | |
8900 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
8901 | else | |
8902 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; | |
8903 | ||
8904 | if (epause->tx_pause) | |
8905 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
8906 | else | |
8907 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; | |
8908 | ||
8909 | if (netif_running(dev)) | |
8910 | tg3_setup_flow_control(tp, 0, 0); | |
8911 | } | |
8912 | } else { | |
8913 | int irq_sync = 0; | |
8914 | ||
8915 | if (netif_running(dev)) { | |
8916 | tg3_netif_stop(tp); | |
8917 | irq_sync = 1; | |
8918 | } | |
8919 | ||
8920 | tg3_full_lock(tp, irq_sync); | |
8921 | ||
8922 | if (epause->autoneg) | |
8923 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
8924 | else | |
8925 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
8926 | if (epause->rx_pause) | |
8927 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
8928 | else | |
8929 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; | |
8930 | if (epause->tx_pause) | |
8931 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
8932 | else | |
8933 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; | |
8934 | ||
8935 | if (netif_running(dev)) { | |
8936 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
8937 | err = tg3_restart_hw(tp, 1); | |
8938 | if (!err) | |
8939 | tg3_netif_start(tp); | |
8940 | } | |
8941 | ||
8942 | tg3_full_unlock(tp); | |
8943 | } | |
8944 | ||
8945 | return err; | |
8946 | } | |
8947 | ||
8948 | static u32 tg3_get_rx_csum(struct net_device *dev) | |
8949 | { | |
8950 | struct tg3 *tp = netdev_priv(dev); | |
8951 | return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0; | |
8952 | } | |
8953 | ||
8954 | static int tg3_set_rx_csum(struct net_device *dev, u32 data) | |
8955 | { | |
8956 | struct tg3 *tp = netdev_priv(dev); | |
8957 | ||
8958 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { | |
8959 | if (data != 0) | |
8960 | return -EINVAL; | |
8961 | return 0; | |
8962 | } | |
8963 | ||
8964 | spin_lock_bh(&tp->lock); | |
8965 | if (data) | |
8966 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
8967 | else | |
8968 | tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; | |
8969 | spin_unlock_bh(&tp->lock); | |
8970 | ||
8971 | return 0; | |
8972 | } | |
8973 | ||
8974 | static int tg3_set_tx_csum(struct net_device *dev, u32 data) | |
8975 | { | |
8976 | struct tg3 *tp = netdev_priv(dev); | |
8977 | ||
8978 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { | |
8979 | if (data != 0) | |
8980 | return -EINVAL; | |
8981 | return 0; | |
8982 | } | |
8983 | ||
8984 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
8985 | ethtool_op_set_tx_ipv6_csum(dev, data); | |
8986 | else | |
8987 | ethtool_op_set_tx_csum(dev, data); | |
8988 | ||
8989 | return 0; | |
8990 | } | |
8991 | ||
8992 | static int tg3_get_sset_count (struct net_device *dev, int sset) | |
8993 | { | |
8994 | switch (sset) { | |
8995 | case ETH_SS_TEST: | |
8996 | return TG3_NUM_TEST; | |
8997 | case ETH_SS_STATS: | |
8998 | return TG3_NUM_STATS; | |
8999 | default: | |
9000 | return -EOPNOTSUPP; | |
9001 | } | |
9002 | } | |
9003 | ||
9004 | static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf) | |
9005 | { | |
9006 | switch (stringset) { | |
9007 | case ETH_SS_STATS: | |
9008 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
9009 | break; | |
9010 | case ETH_SS_TEST: | |
9011 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
9012 | break; | |
9013 | default: | |
9014 | WARN_ON(1); /* we need a WARN() */ | |
9015 | break; | |
9016 | } | |
9017 | } | |
9018 | ||
9019 | static int tg3_phys_id(struct net_device *dev, u32 data) | |
9020 | { | |
9021 | struct tg3 *tp = netdev_priv(dev); | |
9022 | int i; | |
9023 | ||
9024 | if (!netif_running(tp->dev)) | |
9025 | return -EAGAIN; | |
9026 | ||
9027 | if (data == 0) | |
9028 | data = UINT_MAX / 2; | |
9029 | ||
9030 | for (i = 0; i < (data * 2); i++) { | |
9031 | if ((i % 2) == 0) | |
9032 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
9033 | LED_CTRL_1000MBPS_ON | | |
9034 | LED_CTRL_100MBPS_ON | | |
9035 | LED_CTRL_10MBPS_ON | | |
9036 | LED_CTRL_TRAFFIC_OVERRIDE | | |
9037 | LED_CTRL_TRAFFIC_BLINK | | |
9038 | LED_CTRL_TRAFFIC_LED); | |
9039 | ||
9040 | else | |
9041 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
9042 | LED_CTRL_TRAFFIC_OVERRIDE); | |
9043 | ||
9044 | if (msleep_interruptible(500)) | |
9045 | break; | |
9046 | } | |
9047 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
9048 | return 0; | |
9049 | } | |
9050 | ||
9051 | static void tg3_get_ethtool_stats (struct net_device *dev, | |
9052 | struct ethtool_stats *estats, u64 *tmp_stats) | |
9053 | { | |
9054 | struct tg3 *tp = netdev_priv(dev); | |
9055 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
9056 | } | |
9057 | ||
9058 | #define NVRAM_TEST_SIZE 0x100 | |
9059 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 | |
9060 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
9061 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
9062 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 | |
9063 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
9064 | ||
9065 | static int tg3_test_nvram(struct tg3 *tp) | |
9066 | { | |
9067 | u32 csum, magic; | |
9068 | __le32 *buf; | |
9069 | int i, j, k, err = 0, size; | |
9070 | ||
9071 | if (tg3_nvram_read_swab(tp, 0, &magic) != 0) | |
9072 | return -EIO; | |
9073 | ||
9074 | if (magic == TG3_EEPROM_MAGIC) | |
9075 | size = NVRAM_TEST_SIZE; | |
9076 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { | |
9077 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == | |
9078 | TG3_EEPROM_SB_FORMAT_1) { | |
9079 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
9080 | case TG3_EEPROM_SB_REVISION_0: | |
9081 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
9082 | break; | |
9083 | case TG3_EEPROM_SB_REVISION_2: | |
9084 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
9085 | break; | |
9086 | case TG3_EEPROM_SB_REVISION_3: | |
9087 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
9088 | break; | |
9089 | default: | |
9090 | return 0; | |
9091 | } | |
9092 | } else | |
9093 | return 0; | |
9094 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) | |
9095 | size = NVRAM_SELFBOOT_HW_SIZE; | |
9096 | else | |
9097 | return -EIO; | |
9098 | ||
9099 | buf = kmalloc(size, GFP_KERNEL); | |
9100 | if (buf == NULL) | |
9101 | return -ENOMEM; | |
9102 | ||
9103 | err = -EIO; | |
9104 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
9105 | if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0) | |
9106 | break; | |
9107 | } | |
9108 | if (i < size) | |
9109 | goto out; | |
9110 | ||
9111 | /* Selfboot format */ | |
9112 | magic = swab32(le32_to_cpu(buf[0])); | |
9113 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == | |
9114 | TG3_EEPROM_MAGIC_FW) { | |
9115 | u8 *buf8 = (u8 *) buf, csum8 = 0; | |
9116 | ||
9117 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == | |
9118 | TG3_EEPROM_SB_REVISION_2) { | |
9119 | /* For rev 2, the csum doesn't include the MBA. */ | |
9120 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
9121 | csum8 += buf8[i]; | |
9122 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
9123 | csum8 += buf8[i]; | |
9124 | } else { | |
9125 | for (i = 0; i < size; i++) | |
9126 | csum8 += buf8[i]; | |
9127 | } | |
9128 | ||
9129 | if (csum8 == 0) { | |
9130 | err = 0; | |
9131 | goto out; | |
9132 | } | |
9133 | ||
9134 | err = -EIO; | |
9135 | goto out; | |
9136 | } | |
9137 | ||
9138 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == | |
9139 | TG3_EEPROM_MAGIC_HW) { | |
9140 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
9141 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; | |
9142 | u8 *buf8 = (u8 *) buf; | |
9143 | ||
9144 | /* Separate the parity bits and the data bytes. */ | |
9145 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
9146 | if ((i == 0) || (i == 8)) { | |
9147 | int l; | |
9148 | u8 msk; | |
9149 | ||
9150 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
9151 | parity[k++] = buf8[i] & msk; | |
9152 | i++; | |
9153 | } | |
9154 | else if (i == 16) { | |
9155 | int l; | |
9156 | u8 msk; | |
9157 | ||
9158 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
9159 | parity[k++] = buf8[i] & msk; | |
9160 | i++; | |
9161 | ||
9162 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
9163 | parity[k++] = buf8[i] & msk; | |
9164 | i++; | |
9165 | } | |
9166 | data[j++] = buf8[i]; | |
9167 | } | |
9168 | ||
9169 | err = -EIO; | |
9170 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
9171 | u8 hw8 = hweight8(data[i]); | |
9172 | ||
9173 | if ((hw8 & 0x1) && parity[i]) | |
9174 | goto out; | |
9175 | else if (!(hw8 & 0x1) && !parity[i]) | |
9176 | goto out; | |
9177 | } | |
9178 | err = 0; | |
9179 | goto out; | |
9180 | } | |
9181 | ||
9182 | /* Bootstrap checksum at offset 0x10 */ | |
9183 | csum = calc_crc((unsigned char *) buf, 0x10); | |
9184 | if(csum != le32_to_cpu(buf[0x10/4])) | |
9185 | goto out; | |
9186 | ||
9187 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
9188 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
9189 | if (csum != le32_to_cpu(buf[0xfc/4])) | |
9190 | goto out; | |
9191 | ||
9192 | err = 0; | |
9193 | ||
9194 | out: | |
9195 | kfree(buf); | |
9196 | return err; | |
9197 | } | |
9198 | ||
9199 | #define TG3_SERDES_TIMEOUT_SEC 2 | |
9200 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
9201 | ||
9202 | static int tg3_test_link(struct tg3 *tp) | |
9203 | { | |
9204 | int i, max; | |
9205 | ||
9206 | if (!netif_running(tp->dev)) | |
9207 | return -ENODEV; | |
9208 | ||
9209 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) | |
9210 | max = TG3_SERDES_TIMEOUT_SEC; | |
9211 | else | |
9212 | max = TG3_COPPER_TIMEOUT_SEC; | |
9213 | ||
9214 | for (i = 0; i < max; i++) { | |
9215 | if (netif_carrier_ok(tp->dev)) | |
9216 | return 0; | |
9217 | ||
9218 | if (msleep_interruptible(1000)) | |
9219 | break; | |
9220 | } | |
9221 | ||
9222 | return -EIO; | |
9223 | } | |
9224 | ||
9225 | /* Only test the commonly used registers */ | |
9226 | static int tg3_test_registers(struct tg3 *tp) | |
9227 | { | |
9228 | int i, is_5705, is_5750; | |
9229 | u32 offset, read_mask, write_mask, val, save_val, read_val; | |
9230 | static struct { | |
9231 | u16 offset; | |
9232 | u16 flags; | |
9233 | #define TG3_FL_5705 0x1 | |
9234 | #define TG3_FL_NOT_5705 0x2 | |
9235 | #define TG3_FL_NOT_5788 0x4 | |
9236 | #define TG3_FL_NOT_5750 0x8 | |
9237 | u32 read_mask; | |
9238 | u32 write_mask; | |
9239 | } reg_tbl[] = { | |
9240 | /* MAC Control Registers */ | |
9241 | { MAC_MODE, TG3_FL_NOT_5705, | |
9242 | 0x00000000, 0x00ef6f8c }, | |
9243 | { MAC_MODE, TG3_FL_5705, | |
9244 | 0x00000000, 0x01ef6b8c }, | |
9245 | { MAC_STATUS, TG3_FL_NOT_5705, | |
9246 | 0x03800107, 0x00000000 }, | |
9247 | { MAC_STATUS, TG3_FL_5705, | |
9248 | 0x03800100, 0x00000000 }, | |
9249 | { MAC_ADDR_0_HIGH, 0x0000, | |
9250 | 0x00000000, 0x0000ffff }, | |
9251 | { MAC_ADDR_0_LOW, 0x0000, | |
9252 | 0x00000000, 0xffffffff }, | |
9253 | { MAC_RX_MTU_SIZE, 0x0000, | |
9254 | 0x00000000, 0x0000ffff }, | |
9255 | { MAC_TX_MODE, 0x0000, | |
9256 | 0x00000000, 0x00000070 }, | |
9257 | { MAC_TX_LENGTHS, 0x0000, | |
9258 | 0x00000000, 0x00003fff }, | |
9259 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
9260 | 0x00000000, 0x000007fc }, | |
9261 | { MAC_RX_MODE, TG3_FL_5705, | |
9262 | 0x00000000, 0x000007dc }, | |
9263 | { MAC_HASH_REG_0, 0x0000, | |
9264 | 0x00000000, 0xffffffff }, | |
9265 | { MAC_HASH_REG_1, 0x0000, | |
9266 | 0x00000000, 0xffffffff }, | |
9267 | { MAC_HASH_REG_2, 0x0000, | |
9268 | 0x00000000, 0xffffffff }, | |
9269 | { MAC_HASH_REG_3, 0x0000, | |
9270 | 0x00000000, 0xffffffff }, | |
9271 | ||
9272 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
9273 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
9274 | 0x00000000, 0xffffffff }, | |
9275 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
9276 | 0x00000000, 0xffffffff }, | |
9277 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
9278 | 0x00000000, 0x00000003 }, | |
9279 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
9280 | 0x00000000, 0xffffffff }, | |
9281 | { RCVDBDI_STD_BD+0, 0x0000, | |
9282 | 0x00000000, 0xffffffff }, | |
9283 | { RCVDBDI_STD_BD+4, 0x0000, | |
9284 | 0x00000000, 0xffffffff }, | |
9285 | { RCVDBDI_STD_BD+8, 0x0000, | |
9286 | 0x00000000, 0xffff0002 }, | |
9287 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
9288 | 0x00000000, 0xffffffff }, | |
9289 | ||
9290 | /* Receive BD Initiator Control Registers. */ | |
9291 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
9292 | 0x00000000, 0xffffffff }, | |
9293 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
9294 | 0x00000000, 0x000003ff }, | |
9295 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
9296 | 0x00000000, 0xffffffff }, | |
9297 | ||
9298 | /* Host Coalescing Control Registers. */ | |
9299 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
9300 | 0x00000000, 0x00000004 }, | |
9301 | { HOSTCC_MODE, TG3_FL_5705, | |
9302 | 0x00000000, 0x000000f6 }, | |
9303 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
9304 | 0x00000000, 0xffffffff }, | |
9305 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
9306 | 0x00000000, 0x000003ff }, | |
9307 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
9308 | 0x00000000, 0xffffffff }, | |
9309 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
9310 | 0x00000000, 0x000003ff }, | |
9311 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
9312 | 0x00000000, 0xffffffff }, | |
9313 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
9314 | 0x00000000, 0x000000ff }, | |
9315 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
9316 | 0x00000000, 0xffffffff }, | |
9317 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
9318 | 0x00000000, 0x000000ff }, | |
9319 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
9320 | 0x00000000, 0xffffffff }, | |
9321 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
9322 | 0x00000000, 0xffffffff }, | |
9323 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
9324 | 0x00000000, 0xffffffff }, | |
9325 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
9326 | 0x00000000, 0x000000ff }, | |
9327 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
9328 | 0x00000000, 0xffffffff }, | |
9329 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
9330 | 0x00000000, 0x000000ff }, | |
9331 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
9332 | 0x00000000, 0xffffffff }, | |
9333 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
9334 | 0x00000000, 0xffffffff }, | |
9335 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
9336 | 0x00000000, 0xffffffff }, | |
9337 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
9338 | 0x00000000, 0xffffffff }, | |
9339 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
9340 | 0x00000000, 0xffffffff }, | |
9341 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
9342 | 0xffffffff, 0x00000000 }, | |
9343 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
9344 | 0xffffffff, 0x00000000 }, | |
9345 | ||
9346 | /* Buffer Manager Control Registers. */ | |
9347 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, | |
9348 | 0x00000000, 0x007fff80 }, | |
9349 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, | |
9350 | 0x00000000, 0x007fffff }, | |
9351 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
9352 | 0x00000000, 0x0000003f }, | |
9353 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
9354 | 0x00000000, 0x000001ff }, | |
9355 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
9356 | 0x00000000, 0x000001ff }, | |
9357 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
9358 | 0xffffffff, 0x00000000 }, | |
9359 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
9360 | 0xffffffff, 0x00000000 }, | |
9361 | ||
9362 | /* Mailbox Registers */ | |
9363 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
9364 | 0x00000000, 0x000001ff }, | |
9365 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
9366 | 0x00000000, 0x000001ff }, | |
9367 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
9368 | 0x00000000, 0x000007ff }, | |
9369 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
9370 | 0x00000000, 0x000001ff }, | |
9371 | ||
9372 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
9373 | }; | |
9374 | ||
9375 | is_5705 = is_5750 = 0; | |
9376 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
9377 | is_5705 = 1; | |
9378 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) | |
9379 | is_5750 = 1; | |
9380 | } | |
9381 | ||
9382 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
9383 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
9384 | continue; | |
9385 | ||
9386 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
9387 | continue; | |
9388 | ||
9389 | if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
9390 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) | |
9391 | continue; | |
9392 | ||
9393 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) | |
9394 | continue; | |
9395 | ||
9396 | offset = (u32) reg_tbl[i].offset; | |
9397 | read_mask = reg_tbl[i].read_mask; | |
9398 | write_mask = reg_tbl[i].write_mask; | |
9399 | ||
9400 | /* Save the original register content */ | |
9401 | save_val = tr32(offset); | |
9402 | ||
9403 | /* Determine the read-only value. */ | |
9404 | read_val = save_val & read_mask; | |
9405 | ||
9406 | /* Write zero to the register, then make sure the read-only bits | |
9407 | * are not changed and the read/write bits are all zeros. | |
9408 | */ | |
9409 | tw32(offset, 0); | |
9410 | ||
9411 | val = tr32(offset); | |
9412 | ||
9413 | /* Test the read-only and read/write bits. */ | |
9414 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
9415 | goto out; | |
9416 | ||
9417 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
9418 | * make sure the read-only bits are not changed and the | |
9419 | * read/write bits are all ones. | |
9420 | */ | |
9421 | tw32(offset, read_mask | write_mask); | |
9422 | ||
9423 | val = tr32(offset); | |
9424 | ||
9425 | /* Test the read-only bits. */ | |
9426 | if ((val & read_mask) != read_val) | |
9427 | goto out; | |
9428 | ||
9429 | /* Test the read/write bits. */ | |
9430 | if ((val & write_mask) != write_mask) | |
9431 | goto out; | |
9432 | ||
9433 | tw32(offset, save_val); | |
9434 | } | |
9435 | ||
9436 | return 0; | |
9437 | ||
9438 | out: | |
9439 | if (netif_msg_hw(tp)) | |
9440 | printk(KERN_ERR PFX "Register test failed at offset %x\n", | |
9441 | offset); | |
9442 | tw32(offset, save_val); | |
9443 | return -EIO; | |
9444 | } | |
9445 | ||
9446 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) | |
9447 | { | |
9448 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; | |
9449 | int i; | |
9450 | u32 j; | |
9451 | ||
9452 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { | |
9453 | for (j = 0; j < len; j += 4) { | |
9454 | u32 val; | |
9455 | ||
9456 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
9457 | tg3_read_mem(tp, offset + j, &val); | |
9458 | if (val != test_pattern[i]) | |
9459 | return -EIO; | |
9460 | } | |
9461 | } | |
9462 | return 0; | |
9463 | } | |
9464 | ||
9465 | static int tg3_test_memory(struct tg3 *tp) | |
9466 | { | |
9467 | static struct mem_entry { | |
9468 | u32 offset; | |
9469 | u32 len; | |
9470 | } mem_tbl_570x[] = { | |
9471 | { 0x00000000, 0x00b50}, | |
9472 | { 0x00002000, 0x1c000}, | |
9473 | { 0xffffffff, 0x00000} | |
9474 | }, mem_tbl_5705[] = { | |
9475 | { 0x00000100, 0x0000c}, | |
9476 | { 0x00000200, 0x00008}, | |
9477 | { 0x00004000, 0x00800}, | |
9478 | { 0x00006000, 0x01000}, | |
9479 | { 0x00008000, 0x02000}, | |
9480 | { 0x00010000, 0x0e000}, | |
9481 | { 0xffffffff, 0x00000} | |
9482 | }, mem_tbl_5755[] = { | |
9483 | { 0x00000200, 0x00008}, | |
9484 | { 0x00004000, 0x00800}, | |
9485 | { 0x00006000, 0x00800}, | |
9486 | { 0x00008000, 0x02000}, | |
9487 | { 0x00010000, 0x0c000}, | |
9488 | { 0xffffffff, 0x00000} | |
9489 | }, mem_tbl_5906[] = { | |
9490 | { 0x00000200, 0x00008}, | |
9491 | { 0x00004000, 0x00400}, | |
9492 | { 0x00006000, 0x00400}, | |
9493 | { 0x00008000, 0x01000}, | |
9494 | { 0x00010000, 0x01000}, | |
9495 | { 0xffffffff, 0x00000} | |
9496 | }; | |
9497 | struct mem_entry *mem_tbl; | |
9498 | int err = 0; | |
9499 | int i; | |
9500 | ||
9501 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
9502 | mem_tbl = mem_tbl_5755; | |
9503 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
9504 | mem_tbl = mem_tbl_5906; | |
9505 | else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
9506 | mem_tbl = mem_tbl_5705; | |
9507 | else | |
9508 | mem_tbl = mem_tbl_570x; | |
9509 | ||
9510 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
9511 | if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset, | |
9512 | mem_tbl[i].len)) != 0) | |
9513 | break; | |
9514 | } | |
9515 | ||
9516 | return err; | |
9517 | } | |
9518 | ||
9519 | #define TG3_MAC_LOOPBACK 0 | |
9520 | #define TG3_PHY_LOOPBACK 1 | |
9521 | ||
9522 | static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |
9523 | { | |
9524 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; | |
9525 | u32 desc_idx; | |
9526 | struct sk_buff *skb, *rx_skb; | |
9527 | u8 *tx_data; | |
9528 | dma_addr_t map; | |
9529 | int num_pkts, tx_len, rx_len, i, err; | |
9530 | struct tg3_rx_buffer_desc *desc; | |
9531 | ||
9532 | if (loopback_mode == TG3_MAC_LOOPBACK) { | |
9533 | /* HW errata - mac loopback fails in some cases on 5780. | |
9534 | * Normal traffic and PHY loopback are not affected by | |
9535 | * errata. | |
9536 | */ | |
9537 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) | |
9538 | return 0; | |
9539 | ||
9540 | mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) | | |
9541 | MAC_MODE_PORT_INT_LPBACK; | |
9542 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
9543 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
9544 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) | |
9545 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
9546 | else | |
9547 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9548 | tw32(MAC_MODE, mac_mode); | |
9549 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { | |
9550 | u32 val; | |
9551 | ||
9552 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
9553 | u32 phytest; | |
9554 | ||
9555 | if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) { | |
9556 | u32 phy; | |
9557 | ||
9558 | tg3_writephy(tp, MII_TG3_EPHY_TEST, | |
9559 | phytest | MII_TG3_EPHY_SHADOW_EN); | |
9560 | if (!tg3_readphy(tp, 0x1b, &phy)) | |
9561 | tg3_writephy(tp, 0x1b, phy & ~0x20); | |
9562 | tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest); | |
9563 | } | |
9564 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; | |
9565 | } else | |
9566 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
9567 | ||
9568 | tg3_phy_toggle_automdix(tp, 0); | |
9569 | ||
9570 | tg3_writephy(tp, MII_BMCR, val); | |
9571 | udelay(40); | |
9572 | ||
9573 | mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
9574 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
9575 | tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800); | |
9576 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
9577 | } else | |
9578 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9579 | ||
9580 | /* reset to prevent losing 1st rx packet intermittently */ | |
9581 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
9582 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
9583 | udelay(10); | |
9584 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
9585 | } | |
9586 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
9587 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) | |
9588 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
9589 | else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) | |
9590 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
9591 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
9592 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
9593 | } | |
9594 | tw32(MAC_MODE, mac_mode); | |
9595 | } | |
9596 | else | |
9597 | return -EINVAL; | |
9598 | ||
9599 | err = -EIO; | |
9600 | ||
9601 | tx_len = 1514; | |
9602 | skb = netdev_alloc_skb(tp->dev, tx_len); | |
9603 | if (!skb) | |
9604 | return -ENOMEM; | |
9605 | ||
9606 | tx_data = skb_put(skb, tx_len); | |
9607 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
9608 | memset(tx_data + 6, 0x0, 8); | |
9609 | ||
9610 | tw32(MAC_RX_MTU_SIZE, tx_len + 4); | |
9611 | ||
9612 | for (i = 14; i < tx_len; i++) | |
9613 | tx_data[i] = (u8) (i & 0xff); | |
9614 | ||
9615 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); | |
9616 | ||
9617 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
9618 | HOSTCC_MODE_NOW); | |
9619 | ||
9620 | udelay(10); | |
9621 | ||
9622 | rx_start_idx = tp->hw_status->idx[0].rx_producer; | |
9623 | ||
9624 | num_pkts = 0; | |
9625 | ||
9626 | tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1); | |
9627 | ||
9628 | tp->tx_prod++; | |
9629 | num_pkts++; | |
9630 | ||
9631 | tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, | |
9632 | tp->tx_prod); | |
9633 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW); | |
9634 | ||
9635 | udelay(10); | |
9636 | ||
9637 | /* 250 usec to allow enough time on some 10/100 Mbps devices. */ | |
9638 | for (i = 0; i < 25; i++) { | |
9639 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
9640 | HOSTCC_MODE_NOW); | |
9641 | ||
9642 | udelay(10); | |
9643 | ||
9644 | tx_idx = tp->hw_status->idx[0].tx_consumer; | |
9645 | rx_idx = tp->hw_status->idx[0].rx_producer; | |
9646 | if ((tx_idx == tp->tx_prod) && | |
9647 | (rx_idx == (rx_start_idx + num_pkts))) | |
9648 | break; | |
9649 | } | |
9650 | ||
9651 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); | |
9652 | dev_kfree_skb(skb); | |
9653 | ||
9654 | if (tx_idx != tp->tx_prod) | |
9655 | goto out; | |
9656 | ||
9657 | if (rx_idx != rx_start_idx + num_pkts) | |
9658 | goto out; | |
9659 | ||
9660 | desc = &tp->rx_rcb[rx_start_idx]; | |
9661 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
9662 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
9663 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
9664 | goto out; | |
9665 | ||
9666 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
9667 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
9668 | goto out; | |
9669 | ||
9670 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; | |
9671 | if (rx_len != tx_len) | |
9672 | goto out; | |
9673 | ||
9674 | rx_skb = tp->rx_std_buffers[desc_idx].skb; | |
9675 | ||
9676 | map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping); | |
9677 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE); | |
9678 | ||
9679 | for (i = 14; i < tx_len; i++) { | |
9680 | if (*(rx_skb->data + i) != (u8) (i & 0xff)) | |
9681 | goto out; | |
9682 | } | |
9683 | err = 0; | |
9684 | ||
9685 | /* tg3_free_rings will unmap and free the rx_skb */ | |
9686 | out: | |
9687 | return err; | |
9688 | } | |
9689 | ||
9690 | #define TG3_MAC_LOOPBACK_FAILED 1 | |
9691 | #define TG3_PHY_LOOPBACK_FAILED 2 | |
9692 | #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \ | |
9693 | TG3_PHY_LOOPBACK_FAILED) | |
9694 | ||
9695 | static int tg3_test_loopback(struct tg3 *tp) | |
9696 | { | |
9697 | int err = 0; | |
9698 | u32 cpmuctrl = 0; | |
9699 | ||
9700 | if (!netif_running(tp->dev)) | |
9701 | return TG3_LOOPBACK_FAILED; | |
9702 | ||
9703 | err = tg3_reset_hw(tp, 1); | |
9704 | if (err) | |
9705 | return TG3_LOOPBACK_FAILED; | |
9706 | ||
9707 | /* Turn off gphy autopowerdown. */ | |
9708 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
9709 | tg3_phy_toggle_apd(tp, false); | |
9710 | ||
9711 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { | |
9712 | int i; | |
9713 | u32 status; | |
9714 | ||
9715 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
9716 | ||
9717 | /* Wait for up to 40 microseconds to acquire lock. */ | |
9718 | for (i = 0; i < 4; i++) { | |
9719 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
9720 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
9721 | break; | |
9722 | udelay(10); | |
9723 | } | |
9724 | ||
9725 | if (status != CPMU_MUTEX_GNT_DRIVER) | |
9726 | return TG3_LOOPBACK_FAILED; | |
9727 | ||
9728 | /* Turn off link-based power management. */ | |
9729 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
9730 | tw32(TG3_CPMU_CTRL, | |
9731 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
9732 | CPMU_CTRL_LINK_AWARE_MODE)); | |
9733 | } | |
9734 | ||
9735 | if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) | |
9736 | err |= TG3_MAC_LOOPBACK_FAILED; | |
9737 | ||
9738 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { | |
9739 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
9740 | ||
9741 | /* Release the mutex */ | |
9742 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
9743 | } | |
9744 | ||
9745 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
9746 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { | |
9747 | if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) | |
9748 | err |= TG3_PHY_LOOPBACK_FAILED; | |
9749 | } | |
9750 | ||
9751 | /* Re-enable gphy autopowerdown. */ | |
9752 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
9753 | tg3_phy_toggle_apd(tp, true); | |
9754 | ||
9755 | return err; | |
9756 | } | |
9757 | ||
9758 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, | |
9759 | u64 *data) | |
9760 | { | |
9761 | struct tg3 *tp = netdev_priv(dev); | |
9762 | ||
9763 | if (tp->link_config.phy_is_low_power) | |
9764 | tg3_set_power_state(tp, PCI_D0); | |
9765 | ||
9766 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); | |
9767 | ||
9768 | if (tg3_test_nvram(tp) != 0) { | |
9769 | etest->flags |= ETH_TEST_FL_FAILED; | |
9770 | data[0] = 1; | |
9771 | } | |
9772 | if (tg3_test_link(tp) != 0) { | |
9773 | etest->flags |= ETH_TEST_FL_FAILED; | |
9774 | data[1] = 1; | |
9775 | } | |
9776 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | |
9777 | int err, err2 = 0, irq_sync = 0; | |
9778 | ||
9779 | if (netif_running(dev)) { | |
9780 | tg3_phy_stop(tp); | |
9781 | tg3_netif_stop(tp); | |
9782 | irq_sync = 1; | |
9783 | } | |
9784 | ||
9785 | tg3_full_lock(tp, irq_sync); | |
9786 | ||
9787 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
9788 | err = tg3_nvram_lock(tp); | |
9789 | tg3_halt_cpu(tp, RX_CPU_BASE); | |
9790 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
9791 | tg3_halt_cpu(tp, TX_CPU_BASE); | |
9792 | if (!err) | |
9793 | tg3_nvram_unlock(tp); | |
9794 | ||
9795 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) | |
9796 | tg3_phy_reset(tp); | |
9797 | ||
9798 | if (tg3_test_registers(tp) != 0) { | |
9799 | etest->flags |= ETH_TEST_FL_FAILED; | |
9800 | data[2] = 1; | |
9801 | } | |
9802 | if (tg3_test_memory(tp) != 0) { | |
9803 | etest->flags |= ETH_TEST_FL_FAILED; | |
9804 | data[3] = 1; | |
9805 | } | |
9806 | if ((data[4] = tg3_test_loopback(tp)) != 0) | |
9807 | etest->flags |= ETH_TEST_FL_FAILED; | |
9808 | ||
9809 | tg3_full_unlock(tp); | |
9810 | ||
9811 | if (tg3_test_interrupt(tp) != 0) { | |
9812 | etest->flags |= ETH_TEST_FL_FAILED; | |
9813 | data[5] = 1; | |
9814 | } | |
9815 | ||
9816 | tg3_full_lock(tp, 0); | |
9817 | ||
9818 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9819 | if (netif_running(dev)) { | |
9820 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
9821 | err2 = tg3_restart_hw(tp, 1); | |
9822 | if (!err2) | |
9823 | tg3_netif_start(tp); | |
9824 | } | |
9825 | ||
9826 | tg3_full_unlock(tp); | |
9827 | ||
9828 | if (irq_sync && !err2) | |
9829 | tg3_phy_start(tp); | |
9830 | } | |
9831 | if (tp->link_config.phy_is_low_power) | |
9832 | tg3_set_power_state(tp, PCI_D3hot); | |
9833 | ||
9834 | } | |
9835 | ||
9836 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
9837 | { | |
9838 | struct mii_ioctl_data *data = if_mii(ifr); | |
9839 | struct tg3 *tp = netdev_priv(dev); | |
9840 | int err; | |
9841 | ||
9842 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
9843 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
9844 | return -EAGAIN; | |
9845 | return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd); | |
9846 | } | |
9847 | ||
9848 | switch(cmd) { | |
9849 | case SIOCGMIIPHY: | |
9850 | data->phy_id = PHY_ADDR; | |
9851 | ||
9852 | /* fallthru */ | |
9853 | case SIOCGMIIREG: { | |
9854 | u32 mii_regval; | |
9855 | ||
9856 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
9857 | break; /* We have no PHY */ | |
9858 | ||
9859 | if (tp->link_config.phy_is_low_power) | |
9860 | return -EAGAIN; | |
9861 | ||
9862 | spin_lock_bh(&tp->lock); | |
9863 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); | |
9864 | spin_unlock_bh(&tp->lock); | |
9865 | ||
9866 | data->val_out = mii_regval; | |
9867 | ||
9868 | return err; | |
9869 | } | |
9870 | ||
9871 | case SIOCSMIIREG: | |
9872 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
9873 | break; /* We have no PHY */ | |
9874 | ||
9875 | if (!capable(CAP_NET_ADMIN)) | |
9876 | return -EPERM; | |
9877 | ||
9878 | if (tp->link_config.phy_is_low_power) | |
9879 | return -EAGAIN; | |
9880 | ||
9881 | spin_lock_bh(&tp->lock); | |
9882 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); | |
9883 | spin_unlock_bh(&tp->lock); | |
9884 | ||
9885 | return err; | |
9886 | ||
9887 | default: | |
9888 | /* do nothing */ | |
9889 | break; | |
9890 | } | |
9891 | return -EOPNOTSUPP; | |
9892 | } | |
9893 | ||
9894 | #if TG3_VLAN_TAG_USED | |
9895 | static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
9896 | { | |
9897 | struct tg3 *tp = netdev_priv(dev); | |
9898 | ||
9899 | if (netif_running(dev)) | |
9900 | tg3_netif_stop(tp); | |
9901 | ||
9902 | tg3_full_lock(tp, 0); | |
9903 | ||
9904 | tp->vlgrp = grp; | |
9905 | ||
9906 | /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */ | |
9907 | __tg3_set_rx_mode(dev); | |
9908 | ||
9909 | if (netif_running(dev)) | |
9910 | tg3_netif_start(tp); | |
9911 | ||
9912 | tg3_full_unlock(tp); | |
9913 | } | |
9914 | #endif | |
9915 | ||
9916 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
9917 | { | |
9918 | struct tg3 *tp = netdev_priv(dev); | |
9919 | ||
9920 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
9921 | return 0; | |
9922 | } | |
9923 | ||
9924 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
9925 | { | |
9926 | struct tg3 *tp = netdev_priv(dev); | |
9927 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
9928 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
9929 | ||
9930 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
9931 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; | |
9932 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
9933 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
9934 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
9935 | } | |
9936 | ||
9937 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
9938 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
9939 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
9940 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
9941 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
9942 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
9943 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
9944 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
9945 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
9946 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
9947 | return -EINVAL; | |
9948 | ||
9949 | /* No rx interrupts will be generated if both are zero */ | |
9950 | if ((ec->rx_coalesce_usecs == 0) && | |
9951 | (ec->rx_max_coalesced_frames == 0)) | |
9952 | return -EINVAL; | |
9953 | ||
9954 | /* No tx interrupts will be generated if both are zero */ | |
9955 | if ((ec->tx_coalesce_usecs == 0) && | |
9956 | (ec->tx_max_coalesced_frames == 0)) | |
9957 | return -EINVAL; | |
9958 | ||
9959 | /* Only copy relevant parameters, ignore all others. */ | |
9960 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
9961 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
9962 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
9963 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
9964 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
9965 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
9966 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
9967 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
9968 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
9969 | ||
9970 | if (netif_running(dev)) { | |
9971 | tg3_full_lock(tp, 0); | |
9972 | __tg3_set_coalesce(tp, &tp->coal); | |
9973 | tg3_full_unlock(tp); | |
9974 | } | |
9975 | return 0; | |
9976 | } | |
9977 | ||
9978 | static const struct ethtool_ops tg3_ethtool_ops = { | |
9979 | .get_settings = tg3_get_settings, | |
9980 | .set_settings = tg3_set_settings, | |
9981 | .get_drvinfo = tg3_get_drvinfo, | |
9982 | .get_regs_len = tg3_get_regs_len, | |
9983 | .get_regs = tg3_get_regs, | |
9984 | .get_wol = tg3_get_wol, | |
9985 | .set_wol = tg3_set_wol, | |
9986 | .get_msglevel = tg3_get_msglevel, | |
9987 | .set_msglevel = tg3_set_msglevel, | |
9988 | .nway_reset = tg3_nway_reset, | |
9989 | .get_link = ethtool_op_get_link, | |
9990 | .get_eeprom_len = tg3_get_eeprom_len, | |
9991 | .get_eeprom = tg3_get_eeprom, | |
9992 | .set_eeprom = tg3_set_eeprom, | |
9993 | .get_ringparam = tg3_get_ringparam, | |
9994 | .set_ringparam = tg3_set_ringparam, | |
9995 | .get_pauseparam = tg3_get_pauseparam, | |
9996 | .set_pauseparam = tg3_set_pauseparam, | |
9997 | .get_rx_csum = tg3_get_rx_csum, | |
9998 | .set_rx_csum = tg3_set_rx_csum, | |
9999 | .set_tx_csum = tg3_set_tx_csum, | |
10000 | .set_sg = ethtool_op_set_sg, | |
10001 | .set_tso = tg3_set_tso, | |
10002 | .self_test = tg3_self_test, | |
10003 | .get_strings = tg3_get_strings, | |
10004 | .phys_id = tg3_phys_id, | |
10005 | .get_ethtool_stats = tg3_get_ethtool_stats, | |
10006 | .get_coalesce = tg3_get_coalesce, | |
10007 | .set_coalesce = tg3_set_coalesce, | |
10008 | .get_sset_count = tg3_get_sset_count, | |
10009 | }; | |
10010 | ||
10011 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
10012 | { | |
10013 | u32 cursize, val, magic; | |
10014 | ||
10015 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
10016 | ||
10017 | if (tg3_nvram_read_swab(tp, 0, &magic) != 0) | |
10018 | return; | |
10019 | ||
10020 | if ((magic != TG3_EEPROM_MAGIC) && | |
10021 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
10022 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
10023 | return; | |
10024 | ||
10025 | /* | |
10026 | * Size the chip by reading offsets at increasing powers of two. | |
10027 | * When we encounter our validation signature, we know the addressing | |
10028 | * has wrapped around, and thus have our chip size. | |
10029 | */ | |
10030 | cursize = 0x10; | |
10031 | ||
10032 | while (cursize < tp->nvram_size) { | |
10033 | if (tg3_nvram_read_swab(tp, cursize, &val) != 0) | |
10034 | return; | |
10035 | ||
10036 | if (val == magic) | |
10037 | break; | |
10038 | ||
10039 | cursize <<= 1; | |
10040 | } | |
10041 | ||
10042 | tp->nvram_size = cursize; | |
10043 | } | |
10044 | ||
10045 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) | |
10046 | { | |
10047 | u32 val; | |
10048 | ||
10049 | if (tg3_nvram_read_swab(tp, 0, &val) != 0) | |
10050 | return; | |
10051 | ||
10052 | /* Selfboot format */ | |
10053 | if (val != TG3_EEPROM_MAGIC) { | |
10054 | tg3_get_eeprom_size(tp); | |
10055 | return; | |
10056 | } | |
10057 | ||
10058 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { | |
10059 | if (val != 0) { | |
10060 | tp->nvram_size = (val >> 16) * 1024; | |
10061 | return; | |
10062 | } | |
10063 | } | |
10064 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
10065 | } | |
10066 | ||
10067 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
10068 | { | |
10069 | u32 nvcfg1; | |
10070 | ||
10071 | nvcfg1 = tr32(NVRAM_CFG1); | |
10072 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
10073 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10074 | } | |
10075 | else { | |
10076 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
10077 | tw32(NVRAM_CFG1, nvcfg1); | |
10078 | } | |
10079 | ||
10080 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || | |
10081 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
10082 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { | |
10083 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: | |
10084 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10085 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
10086 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10087 | break; | |
10088 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
10089 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10090 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
10091 | break; | |
10092 | case FLASH_VENDOR_ATMEL_EEPROM: | |
10093 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10094 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
10095 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10096 | break; | |
10097 | case FLASH_VENDOR_ST: | |
10098 | tp->nvram_jedecnum = JEDEC_ST; | |
10099 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
10100 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10101 | break; | |
10102 | case FLASH_VENDOR_SAIFUN: | |
10103 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
10104 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
10105 | break; | |
10106 | case FLASH_VENDOR_SST_SMALL: | |
10107 | case FLASH_VENDOR_SST_LARGE: | |
10108 | tp->nvram_jedecnum = JEDEC_SST; | |
10109 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
10110 | break; | |
10111 | } | |
10112 | } | |
10113 | else { | |
10114 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10115 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
10116 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10117 | } | |
10118 | } | |
10119 | ||
10120 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) | |
10121 | { | |
10122 | u32 nvcfg1; | |
10123 | ||
10124 | nvcfg1 = tr32(NVRAM_CFG1); | |
10125 | ||
10126 | /* NVRAM protection for TPM */ | |
10127 | if (nvcfg1 & (1 << 27)) | |
10128 | tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM; | |
10129 | ||
10130 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
10131 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: | |
10132 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
10133 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10134 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10135 | break; | |
10136 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
10137 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10138 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10139 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10140 | break; | |
10141 | case FLASH_5752VENDOR_ST_M45PE10: | |
10142 | case FLASH_5752VENDOR_ST_M45PE20: | |
10143 | case FLASH_5752VENDOR_ST_M45PE40: | |
10144 | tp->nvram_jedecnum = JEDEC_ST; | |
10145 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10146 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10147 | break; | |
10148 | } | |
10149 | ||
10150 | if (tp->tg3_flags2 & TG3_FLG2_FLASH) { | |
10151 | switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
10152 | case FLASH_5752PAGE_SIZE_256: | |
10153 | tp->nvram_pagesize = 256; | |
10154 | break; | |
10155 | case FLASH_5752PAGE_SIZE_512: | |
10156 | tp->nvram_pagesize = 512; | |
10157 | break; | |
10158 | case FLASH_5752PAGE_SIZE_1K: | |
10159 | tp->nvram_pagesize = 1024; | |
10160 | break; | |
10161 | case FLASH_5752PAGE_SIZE_2K: | |
10162 | tp->nvram_pagesize = 2048; | |
10163 | break; | |
10164 | case FLASH_5752PAGE_SIZE_4K: | |
10165 | tp->nvram_pagesize = 4096; | |
10166 | break; | |
10167 | case FLASH_5752PAGE_SIZE_264: | |
10168 | tp->nvram_pagesize = 264; | |
10169 | break; | |
10170 | } | |
10171 | } | |
10172 | else { | |
10173 | /* For eeprom, set pagesize to maximum eeprom size */ | |
10174 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
10175 | ||
10176 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
10177 | tw32(NVRAM_CFG1, nvcfg1); | |
10178 | } | |
10179 | } | |
10180 | ||
10181 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) | |
10182 | { | |
10183 | u32 nvcfg1, protect = 0; | |
10184 | ||
10185 | nvcfg1 = tr32(NVRAM_CFG1); | |
10186 | ||
10187 | /* NVRAM protection for TPM */ | |
10188 | if (nvcfg1 & (1 << 27)) { | |
10189 | tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM; | |
10190 | protect = 1; | |
10191 | } | |
10192 | ||
10193 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
10194 | switch (nvcfg1) { | |
10195 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
10196 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
10197 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
10198 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
10199 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10200 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10201 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10202 | tp->nvram_pagesize = 264; | |
10203 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
10204 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
10205 | tp->nvram_size = (protect ? 0x3e200 : | |
10206 | TG3_NVRAM_SIZE_512KB); | |
10207 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
10208 | tp->nvram_size = (protect ? 0x1f200 : | |
10209 | TG3_NVRAM_SIZE_256KB); | |
10210 | else | |
10211 | tp->nvram_size = (protect ? 0x1f200 : | |
10212 | TG3_NVRAM_SIZE_128KB); | |
10213 | break; | |
10214 | case FLASH_5752VENDOR_ST_M45PE10: | |
10215 | case FLASH_5752VENDOR_ST_M45PE20: | |
10216 | case FLASH_5752VENDOR_ST_M45PE40: | |
10217 | tp->nvram_jedecnum = JEDEC_ST; | |
10218 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10219 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10220 | tp->nvram_pagesize = 256; | |
10221 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
10222 | tp->nvram_size = (protect ? | |
10223 | TG3_NVRAM_SIZE_64KB : | |
10224 | TG3_NVRAM_SIZE_128KB); | |
10225 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
10226 | tp->nvram_size = (protect ? | |
10227 | TG3_NVRAM_SIZE_64KB : | |
10228 | TG3_NVRAM_SIZE_256KB); | |
10229 | else | |
10230 | tp->nvram_size = (protect ? | |
10231 | TG3_NVRAM_SIZE_128KB : | |
10232 | TG3_NVRAM_SIZE_512KB); | |
10233 | break; | |
10234 | } | |
10235 | } | |
10236 | ||
10237 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) | |
10238 | { | |
10239 | u32 nvcfg1; | |
10240 | ||
10241 | nvcfg1 = tr32(NVRAM_CFG1); | |
10242 | ||
10243 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
10244 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: | |
10245 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
10246 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
10247 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
10248 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10249 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10250 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
10251 | ||
10252 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
10253 | tw32(NVRAM_CFG1, nvcfg1); | |
10254 | break; | |
10255 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
10256 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
10257 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
10258 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
10259 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10260 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10261 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10262 | tp->nvram_pagesize = 264; | |
10263 | break; | |
10264 | case FLASH_5752VENDOR_ST_M45PE10: | |
10265 | case FLASH_5752VENDOR_ST_M45PE20: | |
10266 | case FLASH_5752VENDOR_ST_M45PE40: | |
10267 | tp->nvram_jedecnum = JEDEC_ST; | |
10268 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10269 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10270 | tp->nvram_pagesize = 256; | |
10271 | break; | |
10272 | } | |
10273 | } | |
10274 | ||
10275 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) | |
10276 | { | |
10277 | u32 nvcfg1, protect = 0; | |
10278 | ||
10279 | nvcfg1 = tr32(NVRAM_CFG1); | |
10280 | ||
10281 | /* NVRAM protection for TPM */ | |
10282 | if (nvcfg1 & (1 << 27)) { | |
10283 | tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM; | |
10284 | protect = 1; | |
10285 | } | |
10286 | ||
10287 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
10288 | switch (nvcfg1) { | |
10289 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
10290 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
10291 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
10292 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
10293 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
10294 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
10295 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
10296 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
10297 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10298 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10299 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10300 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10301 | tp->nvram_pagesize = 256; | |
10302 | break; | |
10303 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
10304 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
10305 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
10306 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
10307 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
10308 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
10309 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
10310 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
10311 | tp->nvram_jedecnum = JEDEC_ST; | |
10312 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10313 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10314 | tp->nvram_pagesize = 256; | |
10315 | break; | |
10316 | } | |
10317 | ||
10318 | if (protect) { | |
10319 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
10320 | } else { | |
10321 | switch (nvcfg1) { | |
10322 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
10323 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
10324 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
10325 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
10326 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
10327 | break; | |
10328 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
10329 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
10330 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
10331 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
10332 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
10333 | break; | |
10334 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
10335 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
10336 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
10337 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
10338 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
10339 | break; | |
10340 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
10341 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
10342 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
10343 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
10344 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
10345 | break; | |
10346 | } | |
10347 | } | |
10348 | } | |
10349 | ||
10350 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) | |
10351 | { | |
10352 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10353 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10354 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
10355 | } | |
10356 | ||
10357 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) | |
10358 | { | |
10359 | u32 nvcfg1; | |
10360 | ||
10361 | nvcfg1 = tr32(NVRAM_CFG1); | |
10362 | ||
10363 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
10364 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
10365 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
10366 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10367 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10368 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
10369 | ||
10370 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
10371 | tw32(NVRAM_CFG1, nvcfg1); | |
10372 | return; | |
10373 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
10374 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
10375 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
10376 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
10377 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
10378 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
10379 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
10380 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10381 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10382 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10383 | ||
10384 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
10385 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
10386 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
10387 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
10388 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
10389 | break; | |
10390 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
10391 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
10392 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
10393 | break; | |
10394 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
10395 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
10396 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
10397 | break; | |
10398 | } | |
10399 | break; | |
10400 | case FLASH_5752VENDOR_ST_M45PE10: | |
10401 | case FLASH_5752VENDOR_ST_M45PE20: | |
10402 | case FLASH_5752VENDOR_ST_M45PE40: | |
10403 | tp->nvram_jedecnum = JEDEC_ST; | |
10404 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10405 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10406 | ||
10407 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
10408 | case FLASH_5752VENDOR_ST_M45PE10: | |
10409 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
10410 | break; | |
10411 | case FLASH_5752VENDOR_ST_M45PE20: | |
10412 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
10413 | break; | |
10414 | case FLASH_5752VENDOR_ST_M45PE40: | |
10415 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
10416 | break; | |
10417 | } | |
10418 | break; | |
10419 | default: | |
10420 | return; | |
10421 | } | |
10422 | ||
10423 | switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
10424 | case FLASH_5752PAGE_SIZE_256: | |
10425 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10426 | tp->nvram_pagesize = 256; | |
10427 | break; | |
10428 | case FLASH_5752PAGE_SIZE_512: | |
10429 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10430 | tp->nvram_pagesize = 512; | |
10431 | break; | |
10432 | case FLASH_5752PAGE_SIZE_1K: | |
10433 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10434 | tp->nvram_pagesize = 1024; | |
10435 | break; | |
10436 | case FLASH_5752PAGE_SIZE_2K: | |
10437 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10438 | tp->nvram_pagesize = 2048; | |
10439 | break; | |
10440 | case FLASH_5752PAGE_SIZE_4K: | |
10441 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10442 | tp->nvram_pagesize = 4096; | |
10443 | break; | |
10444 | case FLASH_5752PAGE_SIZE_264: | |
10445 | tp->nvram_pagesize = 264; | |
10446 | break; | |
10447 | case FLASH_5752PAGE_SIZE_528: | |
10448 | tp->nvram_pagesize = 528; | |
10449 | break; | |
10450 | } | |
10451 | } | |
10452 | ||
10453 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ | |
10454 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
10455 | { | |
10456 | tw32_f(GRC_EEPROM_ADDR, | |
10457 | (EEPROM_ADDR_FSM_RESET | | |
10458 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
10459 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
10460 | ||
10461 | msleep(1); | |
10462 | ||
10463 | /* Enable seeprom accesses. */ | |
10464 | tw32_f(GRC_LOCAL_CTRL, | |
10465 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
10466 | udelay(100); | |
10467 | ||
10468 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
10469 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
10470 | tp->tg3_flags |= TG3_FLAG_NVRAM; | |
10471 | ||
10472 | if (tg3_nvram_lock(tp)) { | |
10473 | printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, " | |
10474 | "tg3_nvram_init failed.\n", tp->dev->name); | |
10475 | return; | |
10476 | } | |
10477 | tg3_enable_nvram_access(tp); | |
10478 | ||
10479 | tp->nvram_size = 0; | |
10480 | ||
10481 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
10482 | tg3_get_5752_nvram_info(tp); | |
10483 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
10484 | tg3_get_5755_nvram_info(tp); | |
10485 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
10486 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
10487 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
10488 | tg3_get_5787_nvram_info(tp); | |
10489 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
10490 | tg3_get_5761_nvram_info(tp); | |
10491 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
10492 | tg3_get_5906_nvram_info(tp); | |
10493 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
10494 | tg3_get_57780_nvram_info(tp); | |
10495 | else | |
10496 | tg3_get_nvram_info(tp); | |
10497 | ||
10498 | if (tp->nvram_size == 0) | |
10499 | tg3_get_nvram_size(tp); | |
10500 | ||
10501 | tg3_disable_nvram_access(tp); | |
10502 | tg3_nvram_unlock(tp); | |
10503 | ||
10504 | } else { | |
10505 | tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); | |
10506 | ||
10507 | tg3_get_eeprom_size(tp); | |
10508 | } | |
10509 | } | |
10510 | ||
10511 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
10512 | u32 offset, u32 *val) | |
10513 | { | |
10514 | u32 tmp; | |
10515 | int i; | |
10516 | ||
10517 | if (offset > EEPROM_ADDR_ADDR_MASK || | |
10518 | (offset % 4) != 0) | |
10519 | return -EINVAL; | |
10520 | ||
10521 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
10522 | EEPROM_ADDR_DEVID_MASK | | |
10523 | EEPROM_ADDR_READ); | |
10524 | tw32(GRC_EEPROM_ADDR, | |
10525 | tmp | | |
10526 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
10527 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
10528 | EEPROM_ADDR_ADDR_MASK) | | |
10529 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
10530 | ||
10531 | for (i = 0; i < 1000; i++) { | |
10532 | tmp = tr32(GRC_EEPROM_ADDR); | |
10533 | ||
10534 | if (tmp & EEPROM_ADDR_COMPLETE) | |
10535 | break; | |
10536 | msleep(1); | |
10537 | } | |
10538 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
10539 | return -EBUSY; | |
10540 | ||
10541 | *val = tr32(GRC_EEPROM_DATA); | |
10542 | return 0; | |
10543 | } | |
10544 | ||
10545 | #define NVRAM_CMD_TIMEOUT 10000 | |
10546 | ||
10547 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
10548 | { | |
10549 | int i; | |
10550 | ||
10551 | tw32(NVRAM_CMD, nvram_cmd); | |
10552 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
10553 | udelay(10); | |
10554 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
10555 | udelay(10); | |
10556 | break; | |
10557 | } | |
10558 | } | |
10559 | if (i == NVRAM_CMD_TIMEOUT) { | |
10560 | return -EBUSY; | |
10561 | } | |
10562 | return 0; | |
10563 | } | |
10564 | ||
10565 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
10566 | { | |
10567 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
10568 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
10569 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
10570 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
10571 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
10572 | ||
10573 | addr = ((addr / tp->nvram_pagesize) << | |
10574 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
10575 | (addr % tp->nvram_pagesize); | |
10576 | ||
10577 | return addr; | |
10578 | } | |
10579 | ||
10580 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
10581 | { | |
10582 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
10583 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
10584 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
10585 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
10586 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
10587 | ||
10588 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
10589 | tp->nvram_pagesize) + | |
10590 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
10591 | ||
10592 | return addr; | |
10593 | } | |
10594 | ||
10595 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) | |
10596 | { | |
10597 | int ret; | |
10598 | ||
10599 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | |
10600 | return tg3_nvram_read_using_eeprom(tp, offset, val); | |
10601 | ||
10602 | offset = tg3_nvram_phys_addr(tp, offset); | |
10603 | ||
10604 | if (offset > NVRAM_ADDR_MSK) | |
10605 | return -EINVAL; | |
10606 | ||
10607 | ret = tg3_nvram_lock(tp); | |
10608 | if (ret) | |
10609 | return ret; | |
10610 | ||
10611 | tg3_enable_nvram_access(tp); | |
10612 | ||
10613 | tw32(NVRAM_ADDR, offset); | |
10614 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
10615 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
10616 | ||
10617 | if (ret == 0) | |
10618 | *val = swab32(tr32(NVRAM_RDDATA)); | |
10619 | ||
10620 | tg3_disable_nvram_access(tp); | |
10621 | ||
10622 | tg3_nvram_unlock(tp); | |
10623 | ||
10624 | return ret; | |
10625 | } | |
10626 | ||
10627 | static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val) | |
10628 | { | |
10629 | u32 v; | |
10630 | int res = tg3_nvram_read(tp, offset, &v); | |
10631 | if (!res) | |
10632 | *val = cpu_to_le32(v); | |
10633 | return res; | |
10634 | } | |
10635 | ||
10636 | static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val) | |
10637 | { | |
10638 | int err; | |
10639 | u32 tmp; | |
10640 | ||
10641 | err = tg3_nvram_read(tp, offset, &tmp); | |
10642 | *val = swab32(tmp); | |
10643 | return err; | |
10644 | } | |
10645 | ||
10646 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, | |
10647 | u32 offset, u32 len, u8 *buf) | |
10648 | { | |
10649 | int i, j, rc = 0; | |
10650 | u32 val; | |
10651 | ||
10652 | for (i = 0; i < len; i += 4) { | |
10653 | u32 addr; | |
10654 | __le32 data; | |
10655 | ||
10656 | addr = offset + i; | |
10657 | ||
10658 | memcpy(&data, buf + i, 4); | |
10659 | ||
10660 | tw32(GRC_EEPROM_DATA, le32_to_cpu(data)); | |
10661 | ||
10662 | val = tr32(GRC_EEPROM_ADDR); | |
10663 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
10664 | ||
10665 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
10666 | EEPROM_ADDR_READ); | |
10667 | tw32(GRC_EEPROM_ADDR, val | | |
10668 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
10669 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
10670 | EEPROM_ADDR_START | | |
10671 | EEPROM_ADDR_WRITE); | |
10672 | ||
10673 | for (j = 0; j < 1000; j++) { | |
10674 | val = tr32(GRC_EEPROM_ADDR); | |
10675 | ||
10676 | if (val & EEPROM_ADDR_COMPLETE) | |
10677 | break; | |
10678 | msleep(1); | |
10679 | } | |
10680 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
10681 | rc = -EBUSY; | |
10682 | break; | |
10683 | } | |
10684 | } | |
10685 | ||
10686 | return rc; | |
10687 | } | |
10688 | ||
10689 | /* offset and length are dword aligned */ | |
10690 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
10691 | u8 *buf) | |
10692 | { | |
10693 | int ret = 0; | |
10694 | u32 pagesize = tp->nvram_pagesize; | |
10695 | u32 pagemask = pagesize - 1; | |
10696 | u32 nvram_cmd; | |
10697 | u8 *tmp; | |
10698 | ||
10699 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
10700 | if (tmp == NULL) | |
10701 | return -ENOMEM; | |
10702 | ||
10703 | while (len) { | |
10704 | int j; | |
10705 | u32 phy_addr, page_off, size; | |
10706 | ||
10707 | phy_addr = offset & ~pagemask; | |
10708 | ||
10709 | for (j = 0; j < pagesize; j += 4) { | |
10710 | if ((ret = tg3_nvram_read_le(tp, phy_addr + j, | |
10711 | (__le32 *) (tmp + j)))) | |
10712 | break; | |
10713 | } | |
10714 | if (ret) | |
10715 | break; | |
10716 | ||
10717 | page_off = offset & pagemask; | |
10718 | size = pagesize; | |
10719 | if (len < size) | |
10720 | size = len; | |
10721 | ||
10722 | len -= size; | |
10723 | ||
10724 | memcpy(tmp + page_off, buf, size); | |
10725 | ||
10726 | offset = offset + (pagesize - page_off); | |
10727 | ||
10728 | tg3_enable_nvram_access(tp); | |
10729 | ||
10730 | /* | |
10731 | * Before we can erase the flash page, we need | |
10732 | * to issue a special "write enable" command. | |
10733 | */ | |
10734 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
10735 | ||
10736 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
10737 | break; | |
10738 | ||
10739 | /* Erase the target page */ | |
10740 | tw32(NVRAM_ADDR, phy_addr); | |
10741 | ||
10742 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
10743 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
10744 | ||
10745 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
10746 | break; | |
10747 | ||
10748 | /* Issue another write enable to start the write. */ | |
10749 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
10750 | ||
10751 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
10752 | break; | |
10753 | ||
10754 | for (j = 0; j < pagesize; j += 4) { | |
10755 | __be32 data; | |
10756 | ||
10757 | data = *((__be32 *) (tmp + j)); | |
10758 | /* swab32(le32_to_cpu(data)), actually */ | |
10759 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
10760 | ||
10761 | tw32(NVRAM_ADDR, phy_addr + j); | |
10762 | ||
10763 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
10764 | NVRAM_CMD_WR; | |
10765 | ||
10766 | if (j == 0) | |
10767 | nvram_cmd |= NVRAM_CMD_FIRST; | |
10768 | else if (j == (pagesize - 4)) | |
10769 | nvram_cmd |= NVRAM_CMD_LAST; | |
10770 | ||
10771 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
10772 | break; | |
10773 | } | |
10774 | if (ret) | |
10775 | break; | |
10776 | } | |
10777 | ||
10778 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
10779 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
10780 | ||
10781 | kfree(tmp); | |
10782 | ||
10783 | return ret; | |
10784 | } | |
10785 | ||
10786 | /* offset and length are dword aligned */ | |
10787 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
10788 | u8 *buf) | |
10789 | { | |
10790 | int i, ret = 0; | |
10791 | ||
10792 | for (i = 0; i < len; i += 4, offset += 4) { | |
10793 | u32 page_off, phy_addr, nvram_cmd; | |
10794 | __be32 data; | |
10795 | ||
10796 | memcpy(&data, buf + i, 4); | |
10797 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
10798 | ||
10799 | page_off = offset % tp->nvram_pagesize; | |
10800 | ||
10801 | phy_addr = tg3_nvram_phys_addr(tp, offset); | |
10802 | ||
10803 | tw32(NVRAM_ADDR, phy_addr); | |
10804 | ||
10805 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
10806 | ||
10807 | if ((page_off == 0) || (i == 0)) | |
10808 | nvram_cmd |= NVRAM_CMD_FIRST; | |
10809 | if (page_off == (tp->nvram_pagesize - 4)) | |
10810 | nvram_cmd |= NVRAM_CMD_LAST; | |
10811 | ||
10812 | if (i == (len - 4)) | |
10813 | nvram_cmd |= NVRAM_CMD_LAST; | |
10814 | ||
10815 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && | |
10816 | !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && | |
10817 | (tp->nvram_jedecnum == JEDEC_ST) && | |
10818 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
10819 | ||
10820 | if ((ret = tg3_nvram_exec_cmd(tp, | |
10821 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
10822 | NVRAM_CMD_DONE))) | |
10823 | ||
10824 | break; | |
10825 | } | |
10826 | if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
10827 | /* We always do complete word writes to eeprom. */ | |
10828 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
10829 | } | |
10830 | ||
10831 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
10832 | break; | |
10833 | } | |
10834 | return ret; | |
10835 | } | |
10836 | ||
10837 | /* offset and length are dword aligned */ | |
10838 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
10839 | { | |
10840 | int ret; | |
10841 | ||
10842 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
10843 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & | |
10844 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
10845 | udelay(40); | |
10846 | } | |
10847 | ||
10848 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { | |
10849 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
10850 | } | |
10851 | else { | |
10852 | u32 grc_mode; | |
10853 | ||
10854 | ret = tg3_nvram_lock(tp); | |
10855 | if (ret) | |
10856 | return ret; | |
10857 | ||
10858 | tg3_enable_nvram_access(tp); | |
10859 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
10860 | !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) | |
10861 | tw32(NVRAM_WRITE1, 0x406); | |
10862 | ||
10863 | grc_mode = tr32(GRC_MODE); | |
10864 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
10865 | ||
10866 | if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) || | |
10867 | !(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
10868 | ||
10869 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
10870 | buf); | |
10871 | } | |
10872 | else { | |
10873 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, | |
10874 | buf); | |
10875 | } | |
10876 | ||
10877 | grc_mode = tr32(GRC_MODE); | |
10878 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
10879 | ||
10880 | tg3_disable_nvram_access(tp); | |
10881 | tg3_nvram_unlock(tp); | |
10882 | } | |
10883 | ||
10884 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
10885 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
10886 | udelay(40); | |
10887 | } | |
10888 | ||
10889 | return ret; | |
10890 | } | |
10891 | ||
10892 | struct subsys_tbl_ent { | |
10893 | u16 subsys_vendor, subsys_devid; | |
10894 | u32 phy_id; | |
10895 | }; | |
10896 | ||
10897 | static struct subsys_tbl_ent subsys_id_to_phy_id[] = { | |
10898 | /* Broadcom boards. */ | |
10899 | { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */ | |
10900 | { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */ | |
10901 | { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */ | |
10902 | { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */ | |
10903 | { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */ | |
10904 | { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */ | |
10905 | { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */ | |
10906 | { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */ | |
10907 | { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */ | |
10908 | { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */ | |
10909 | { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */ | |
10910 | ||
10911 | /* 3com boards. */ | |
10912 | { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */ | |
10913 | { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */ | |
10914 | { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */ | |
10915 | { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */ | |
10916 | { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */ | |
10917 | ||
10918 | /* DELL boards. */ | |
10919 | { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */ | |
10920 | { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */ | |
10921 | { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */ | |
10922 | { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */ | |
10923 | ||
10924 | /* Compaq boards. */ | |
10925 | { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */ | |
10926 | { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */ | |
10927 | { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */ | |
10928 | { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */ | |
10929 | { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */ | |
10930 | ||
10931 | /* IBM boards. */ | |
10932 | { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */ | |
10933 | }; | |
10934 | ||
10935 | static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp) | |
10936 | { | |
10937 | int i; | |
10938 | ||
10939 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
10940 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
10941 | tp->pdev->subsystem_vendor) && | |
10942 | (subsys_id_to_phy_id[i].subsys_devid == | |
10943 | tp->pdev->subsystem_device)) | |
10944 | return &subsys_id_to_phy_id[i]; | |
10945 | } | |
10946 | return NULL; | |
10947 | } | |
10948 | ||
10949 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) | |
10950 | { | |
10951 | u32 val; | |
10952 | u16 pmcsr; | |
10953 | ||
10954 | /* On some early chips the SRAM cannot be accessed in D3hot state, | |
10955 | * so need make sure we're in D0. | |
10956 | */ | |
10957 | pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
10958 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
10959 | pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); | |
10960 | msleep(1); | |
10961 | ||
10962 | /* Make sure register accesses (indirect or otherwise) | |
10963 | * will function correctly. | |
10964 | */ | |
10965 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
10966 | tp->misc_host_ctrl); | |
10967 | ||
10968 | /* The memory arbiter has to be enabled in order for SRAM accesses | |
10969 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
10970 | * sure it is enabled, but other entities such as system netboot | |
10971 | * code might disable it. | |
10972 | */ | |
10973 | val = tr32(MEMARB_MODE); | |
10974 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
10975 | ||
10976 | tp->phy_id = PHY_ID_INVALID; | |
10977 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
10978 | ||
10979 | /* Assume an onboard device and WOL capable by default. */ | |
10980 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; | |
10981 | ||
10982 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
10983 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { | |
10984 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
10985 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; | |
10986 | } | |
10987 | val = tr32(VCPU_CFGSHDW); | |
10988 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
10989 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
10990 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && | |
10991 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) | |
10992 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; | |
10993 | goto done; | |
10994 | } | |
10995 | ||
10996 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
10997 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
10998 | u32 nic_cfg, led_cfg; | |
10999 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; | |
11000 | int eeprom_phy_serdes = 0; | |
11001 | ||
11002 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
11003 | tp->nic_sram_data_cfg = nic_cfg; | |
11004 | ||
11005 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
11006 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
11007 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && | |
11008 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && | |
11009 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) && | |
11010 | (ver > 0) && (ver < 0x100)) | |
11011 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
11012 | ||
11013 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
11014 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
11015 | ||
11016 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == | |
11017 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
11018 | eeprom_phy_serdes = 1; | |
11019 | ||
11020 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
11021 | if (nic_phy_id != 0) { | |
11022 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
11023 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
11024 | ||
11025 | eeprom_phy_id = (id1 >> 16) << 10; | |
11026 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
11027 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
11028 | } else | |
11029 | eeprom_phy_id = 0; | |
11030 | ||
11031 | tp->phy_id = eeprom_phy_id; | |
11032 | if (eeprom_phy_serdes) { | |
11033 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
11034 | tp->tg3_flags2 |= TG3_FLG2_MII_SERDES; | |
11035 | else | |
11036 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
11037 | } | |
11038 | ||
11039 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) | |
11040 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | | |
11041 | SHASTA_EXT_LED_MODE_MASK); | |
11042 | else | |
11043 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; | |
11044 | ||
11045 | switch (led_cfg) { | |
11046 | default: | |
11047 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
11048 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
11049 | break; | |
11050 | ||
11051 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
11052 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
11053 | break; | |
11054 | ||
11055 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
11056 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
11057 | ||
11058 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
11059 | * read on some older 5700/5701 bootcode. | |
11060 | */ | |
11061 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
11062 | ASIC_REV_5700 || | |
11063 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
11064 | ASIC_REV_5701) | |
11065 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
11066 | ||
11067 | break; | |
11068 | ||
11069 | case SHASTA_EXT_LED_SHARED: | |
11070 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
11071 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
11072 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
11073 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
11074 | LED_CTRL_MODE_PHY_2); | |
11075 | break; | |
11076 | ||
11077 | case SHASTA_EXT_LED_MAC: | |
11078 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
11079 | break; | |
11080 | ||
11081 | case SHASTA_EXT_LED_COMBO: | |
11082 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
11083 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
11084 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
11085 | LED_CTRL_MODE_PHY_2); | |
11086 | break; | |
11087 | ||
11088 | } | |
11089 | ||
11090 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
11091 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
11092 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
11093 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
11094 | ||
11095 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) | |
11096 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
11097 | ||
11098 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { | |
11099 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; | |
11100 | if ((tp->pdev->subsystem_vendor == | |
11101 | PCI_VENDOR_ID_ARIMA) && | |
11102 | (tp->pdev->subsystem_device == 0x205a || | |
11103 | tp->pdev->subsystem_device == 0x2063)) | |
11104 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
11105 | } else { | |
11106 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
11107 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; | |
11108 | } | |
11109 | ||
11110 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
11111 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
11112 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) | |
11113 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; | |
11114 | } | |
11115 | ||
11116 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
11117 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
11118 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; | |
11119 | ||
11120 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES && | |
11121 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) | |
11122 | tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; | |
11123 | ||
11124 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && | |
11125 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) | |
11126 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; | |
11127 | ||
11128 | if (cfg2 & (1 << 17)) | |
11129 | tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING; | |
11130 | ||
11131 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
11132 | /* bootcode if bit 18 is set */ | |
11133 | if (cfg2 & (1 << 18)) | |
11134 | tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS; | |
11135 | ||
11136 | if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
11137 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
11138 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) | |
11139 | tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD; | |
11140 | ||
11141 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
11142 | u32 cfg3; | |
11143 | ||
11144 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
11145 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
11146 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
11147 | } | |
11148 | ||
11149 | if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE) | |
11150 | tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE; | |
11151 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) | |
11152 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN; | |
11153 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) | |
11154 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; | |
11155 | } | |
11156 | done: | |
11157 | device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP); | |
11158 | device_set_wakeup_enable(&tp->pdev->dev, | |
11159 | tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
11160 | } | |
11161 | ||
11162 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) | |
11163 | { | |
11164 | int i; | |
11165 | u32 val; | |
11166 | ||
11167 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
11168 | tw32(OTP_CTRL, cmd); | |
11169 | ||
11170 | /* Wait for up to 1 ms for command to execute. */ | |
11171 | for (i = 0; i < 100; i++) { | |
11172 | val = tr32(OTP_STATUS); | |
11173 | if (val & OTP_STATUS_CMD_DONE) | |
11174 | break; | |
11175 | udelay(10); | |
11176 | } | |
11177 | ||
11178 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
11179 | } | |
11180 | ||
11181 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
11182 | * configuration is a 32-bit value that straddles the alignment boundary. | |
11183 | * We do two 32-bit reads and then shift and merge the results. | |
11184 | */ | |
11185 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
11186 | { | |
11187 | u32 bhalf_otp, thalf_otp; | |
11188 | ||
11189 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
11190 | ||
11191 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
11192 | return 0; | |
11193 | ||
11194 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
11195 | ||
11196 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
11197 | return 0; | |
11198 | ||
11199 | thalf_otp = tr32(OTP_READ_DATA); | |
11200 | ||
11201 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
11202 | ||
11203 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
11204 | return 0; | |
11205 | ||
11206 | bhalf_otp = tr32(OTP_READ_DATA); | |
11207 | ||
11208 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
11209 | } | |
11210 | ||
11211 | static int __devinit tg3_phy_probe(struct tg3 *tp) | |
11212 | { | |
11213 | u32 hw_phy_id_1, hw_phy_id_2; | |
11214 | u32 hw_phy_id, hw_phy_id_masked; | |
11215 | int err; | |
11216 | ||
11217 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) | |
11218 | return tg3_phy_init(tp); | |
11219 | ||
11220 | /* Reading the PHY ID register can conflict with ASF | |
11221 | * firwmare access to the PHY hardware. | |
11222 | */ | |
11223 | err = 0; | |
11224 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
11225 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
11226 | hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID; | |
11227 | } else { | |
11228 | /* Now read the physical PHY_ID from the chip and verify | |
11229 | * that it is sane. If it doesn't look good, we fall back | |
11230 | * to either the hard-coded table based PHY_ID and failing | |
11231 | * that the value found in the eeprom area. | |
11232 | */ | |
11233 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
11234 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
11235 | ||
11236 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
11237 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
11238 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
11239 | ||
11240 | hw_phy_id_masked = hw_phy_id & PHY_ID_MASK; | |
11241 | } | |
11242 | ||
11243 | if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) { | |
11244 | tp->phy_id = hw_phy_id; | |
11245 | if (hw_phy_id_masked == PHY_ID_BCM8002) | |
11246 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
11247 | else | |
11248 | tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES; | |
11249 | } else { | |
11250 | if (tp->phy_id != PHY_ID_INVALID) { | |
11251 | /* Do nothing, phy ID already set up in | |
11252 | * tg3_get_eeprom_hw_cfg(). | |
11253 | */ | |
11254 | } else { | |
11255 | struct subsys_tbl_ent *p; | |
11256 | ||
11257 | /* No eeprom signature? Try the hardcoded | |
11258 | * subsys device table. | |
11259 | */ | |
11260 | p = lookup_by_subsys(tp); | |
11261 | if (!p) | |
11262 | return -ENODEV; | |
11263 | ||
11264 | tp->phy_id = p->phy_id; | |
11265 | if (!tp->phy_id || | |
11266 | tp->phy_id == PHY_ID_BCM8002) | |
11267 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
11268 | } | |
11269 | } | |
11270 | ||
11271 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) && | |
11272 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) && | |
11273 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
11274 | u32 bmsr, adv_reg, tg3_ctrl, mask; | |
11275 | ||
11276 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
11277 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
11278 | (bmsr & BMSR_LSTATUS)) | |
11279 | goto skip_phy_reset; | |
11280 | ||
11281 | err = tg3_phy_reset(tp); | |
11282 | if (err) | |
11283 | return err; | |
11284 | ||
11285 | adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
11286 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
11287 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
11288 | tg3_ctrl = 0; | |
11289 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
11290 | tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF | | |
11291 | MII_TG3_CTRL_ADV_1000_FULL); | |
11292 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
11293 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
11294 | tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER | | |
11295 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
11296 | } | |
11297 | ||
11298 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
11299 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
11300 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
11301 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
11302 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
11303 | ||
11304 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
11305 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); | |
11306 | ||
11307 | tg3_writephy(tp, MII_BMCR, | |
11308 | BMCR_ANENABLE | BMCR_ANRESTART); | |
11309 | } | |
11310 | tg3_phy_set_wirespeed(tp); | |
11311 | ||
11312 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
11313 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
11314 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); | |
11315 | } | |
11316 | ||
11317 | skip_phy_reset: | |
11318 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
11319 | err = tg3_init_5401phy_dsp(tp); | |
11320 | if (err) | |
11321 | return err; | |
11322 | } | |
11323 | ||
11324 | if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) { | |
11325 | err = tg3_init_5401phy_dsp(tp); | |
11326 | } | |
11327 | ||
11328 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) | |
11329 | tp->link_config.advertising = | |
11330 | (ADVERTISED_1000baseT_Half | | |
11331 | ADVERTISED_1000baseT_Full | | |
11332 | ADVERTISED_Autoneg | | |
11333 | ADVERTISED_FIBRE); | |
11334 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) | |
11335 | tp->link_config.advertising &= | |
11336 | ~(ADVERTISED_1000baseT_Half | | |
11337 | ADVERTISED_1000baseT_Full); | |
11338 | ||
11339 | return err; | |
11340 | } | |
11341 | ||
11342 | static void __devinit tg3_read_partno(struct tg3 *tp) | |
11343 | { | |
11344 | unsigned char vpd_data[256]; | |
11345 | unsigned int i; | |
11346 | u32 magic; | |
11347 | ||
11348 | if (tg3_nvram_read_swab(tp, 0x0, &magic)) | |
11349 | goto out_not_found; | |
11350 | ||
11351 | if (magic == TG3_EEPROM_MAGIC) { | |
11352 | for (i = 0; i < 256; i += 4) { | |
11353 | u32 tmp; | |
11354 | ||
11355 | if (tg3_nvram_read(tp, 0x100 + i, &tmp)) | |
11356 | goto out_not_found; | |
11357 | ||
11358 | vpd_data[i + 0] = ((tmp >> 0) & 0xff); | |
11359 | vpd_data[i + 1] = ((tmp >> 8) & 0xff); | |
11360 | vpd_data[i + 2] = ((tmp >> 16) & 0xff); | |
11361 | vpd_data[i + 3] = ((tmp >> 24) & 0xff); | |
11362 | } | |
11363 | } else { | |
11364 | int vpd_cap; | |
11365 | ||
11366 | vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD); | |
11367 | for (i = 0; i < 256; i += 4) { | |
11368 | u32 tmp, j = 0; | |
11369 | __le32 v; | |
11370 | u16 tmp16; | |
11371 | ||
11372 | pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR, | |
11373 | i); | |
11374 | while (j++ < 100) { | |
11375 | pci_read_config_word(tp->pdev, vpd_cap + | |
11376 | PCI_VPD_ADDR, &tmp16); | |
11377 | if (tmp16 & 0x8000) | |
11378 | break; | |
11379 | msleep(1); | |
11380 | } | |
11381 | if (!(tmp16 & 0x8000)) | |
11382 | goto out_not_found; | |
11383 | ||
11384 | pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA, | |
11385 | &tmp); | |
11386 | v = cpu_to_le32(tmp); | |
11387 | memcpy(&vpd_data[i], &v, 4); | |
11388 | } | |
11389 | } | |
11390 | ||
11391 | /* Now parse and find the part number. */ | |
11392 | for (i = 0; i < 254; ) { | |
11393 | unsigned char val = vpd_data[i]; | |
11394 | unsigned int block_end; | |
11395 | ||
11396 | if (val == 0x82 || val == 0x91) { | |
11397 | i = (i + 3 + | |
11398 | (vpd_data[i + 1] + | |
11399 | (vpd_data[i + 2] << 8))); | |
11400 | continue; | |
11401 | } | |
11402 | ||
11403 | if (val != 0x90) | |
11404 | goto out_not_found; | |
11405 | ||
11406 | block_end = (i + 3 + | |
11407 | (vpd_data[i + 1] + | |
11408 | (vpd_data[i + 2] << 8))); | |
11409 | i += 3; | |
11410 | ||
11411 | if (block_end > 256) | |
11412 | goto out_not_found; | |
11413 | ||
11414 | while (i < (block_end - 2)) { | |
11415 | if (vpd_data[i + 0] == 'P' && | |
11416 | vpd_data[i + 1] == 'N') { | |
11417 | int partno_len = vpd_data[i + 2]; | |
11418 | ||
11419 | i += 3; | |
11420 | if (partno_len > 24 || (partno_len + i) > 256) | |
11421 | goto out_not_found; | |
11422 | ||
11423 | memcpy(tp->board_part_number, | |
11424 | &vpd_data[i], partno_len); | |
11425 | ||
11426 | /* Success. */ | |
11427 | return; | |
11428 | } | |
11429 | i += 3 + vpd_data[i + 2]; | |
11430 | } | |
11431 | ||
11432 | /* Part number not found. */ | |
11433 | goto out_not_found; | |
11434 | } | |
11435 | ||
11436 | out_not_found: | |
11437 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11438 | strcpy(tp->board_part_number, "BCM95906"); | |
11439 | else | |
11440 | strcpy(tp->board_part_number, "none"); | |
11441 | } | |
11442 | ||
11443 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) | |
11444 | { | |
11445 | u32 val; | |
11446 | ||
11447 | if (tg3_nvram_read_swab(tp, offset, &val) || | |
11448 | (val & 0xfc000000) != 0x0c000000 || | |
11449 | tg3_nvram_read_swab(tp, offset + 4, &val) || | |
11450 | val != 0) | |
11451 | return 0; | |
11452 | ||
11453 | return 1; | |
11454 | } | |
11455 | ||
11456 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) | |
11457 | { | |
11458 | u32 offset, major, minor, build; | |
11459 | ||
11460 | tp->fw_ver[0] = 's'; | |
11461 | tp->fw_ver[1] = 'b'; | |
11462 | tp->fw_ver[2] = '\0'; | |
11463 | ||
11464 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
11465 | return; | |
11466 | ||
11467 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
11468 | case TG3_EEPROM_SB_REVISION_0: | |
11469 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
11470 | break; | |
11471 | case TG3_EEPROM_SB_REVISION_2: | |
11472 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
11473 | break; | |
11474 | case TG3_EEPROM_SB_REVISION_3: | |
11475 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
11476 | break; | |
11477 | default: | |
11478 | return; | |
11479 | } | |
11480 | ||
11481 | if (tg3_nvram_read_swab(tp, offset, &val)) | |
11482 | return; | |
11483 | ||
11484 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
11485 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
11486 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
11487 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
11488 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
11489 | ||
11490 | if (minor > 99 || build > 26) | |
11491 | return; | |
11492 | ||
11493 | snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor); | |
11494 | ||
11495 | if (build > 0) { | |
11496 | tp->fw_ver[8] = 'a' + build - 1; | |
11497 | tp->fw_ver[9] = '\0'; | |
11498 | } | |
11499 | } | |
11500 | ||
11501 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) | |
11502 | { | |
11503 | u32 val, offset, start; | |
11504 | u32 ver_offset; | |
11505 | int i, bcnt; | |
11506 | ||
11507 | if (tg3_nvram_read_swab(tp, 0, &val)) | |
11508 | return; | |
11509 | ||
11510 | if (val != TG3_EEPROM_MAGIC) { | |
11511 | if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
11512 | tg3_read_sb_ver(tp, val); | |
11513 | ||
11514 | return; | |
11515 | } | |
11516 | ||
11517 | if (tg3_nvram_read_swab(tp, 0xc, &offset) || | |
11518 | tg3_nvram_read_swab(tp, 0x4, &start)) | |
11519 | return; | |
11520 | ||
11521 | offset = tg3_nvram_logical_addr(tp, offset); | |
11522 | ||
11523 | if (!tg3_fw_img_is_valid(tp, offset) || | |
11524 | tg3_nvram_read_swab(tp, offset + 8, &ver_offset)) | |
11525 | return; | |
11526 | ||
11527 | offset = offset + ver_offset - start; | |
11528 | for (i = 0; i < 16; i += 4) { | |
11529 | __le32 v; | |
11530 | if (tg3_nvram_read_le(tp, offset + i, &v)) | |
11531 | return; | |
11532 | ||
11533 | memcpy(tp->fw_ver + i, &v, 4); | |
11534 | } | |
11535 | ||
11536 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
11537 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
11538 | return; | |
11539 | ||
11540 | for (offset = TG3_NVM_DIR_START; | |
11541 | offset < TG3_NVM_DIR_END; | |
11542 | offset += TG3_NVM_DIRENT_SIZE) { | |
11543 | if (tg3_nvram_read_swab(tp, offset, &val)) | |
11544 | return; | |
11545 | ||
11546 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) | |
11547 | break; | |
11548 | } | |
11549 | ||
11550 | if (offset == TG3_NVM_DIR_END) | |
11551 | return; | |
11552 | ||
11553 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
11554 | start = 0x08000000; | |
11555 | else if (tg3_nvram_read_swab(tp, offset - 4, &start)) | |
11556 | return; | |
11557 | ||
11558 | if (tg3_nvram_read_swab(tp, offset + 4, &offset) || | |
11559 | !tg3_fw_img_is_valid(tp, offset) || | |
11560 | tg3_nvram_read_swab(tp, offset + 8, &val)) | |
11561 | return; | |
11562 | ||
11563 | offset += val - start; | |
11564 | ||
11565 | bcnt = strlen(tp->fw_ver); | |
11566 | ||
11567 | tp->fw_ver[bcnt++] = ','; | |
11568 | tp->fw_ver[bcnt++] = ' '; | |
11569 | ||
11570 | for (i = 0; i < 4; i++) { | |
11571 | __le32 v; | |
11572 | if (tg3_nvram_read_le(tp, offset, &v)) | |
11573 | return; | |
11574 | ||
11575 | offset += sizeof(v); | |
11576 | ||
11577 | if (bcnt > TG3_VER_SIZE - sizeof(v)) { | |
11578 | memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt); | |
11579 | break; | |
11580 | } | |
11581 | ||
11582 | memcpy(&tp->fw_ver[bcnt], &v, sizeof(v)); | |
11583 | bcnt += sizeof(v); | |
11584 | } | |
11585 | ||
11586 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; | |
11587 | } | |
11588 | ||
11589 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); | |
11590 | ||
11591 | static int __devinit tg3_get_invariants(struct tg3 *tp) | |
11592 | { | |
11593 | static struct pci_device_id write_reorder_chipsets[] = { | |
11594 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, | |
11595 | PCI_DEVICE_ID_AMD_FE_GATE_700C) }, | |
11596 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, | |
11597 | PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
11598 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, | |
11599 | PCI_DEVICE_ID_VIA_8385_0) }, | |
11600 | { }, | |
11601 | }; | |
11602 | u32 misc_ctrl_reg; | |
11603 | u32 pci_state_reg, grc_misc_cfg; | |
11604 | u32 val; | |
11605 | u16 pci_cmd; | |
11606 | int err; | |
11607 | ||
11608 | /* Force memory write invalidate off. If we leave it on, | |
11609 | * then on 5700_BX chips we have to enable a workaround. | |
11610 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
11611 | * to match the cacheline size. The Broadcom driver have this | |
11612 | * workaround but turns MWI off all the times so never uses | |
11613 | * it. This seems to suggest that the workaround is insufficient. | |
11614 | */ | |
11615 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
11616 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
11617 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
11618 | ||
11619 | /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL | |
11620 | * has the register indirect write enable bit set before | |
11621 | * we try to access any of the MMIO registers. It is also | |
11622 | * critical that the PCI-X hw workaround situation is decided | |
11623 | * before that as well. | |
11624 | */ | |
11625 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
11626 | &misc_ctrl_reg); | |
11627 | ||
11628 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
11629 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
11630 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { | |
11631 | u32 prod_id_asic_rev; | |
11632 | ||
11633 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
11634 | &prod_id_asic_rev); | |
11635 | tp->pci_chip_rev_id = prod_id_asic_rev; | |
11636 | } | |
11637 | ||
11638 | /* Wrong chip ID in 5752 A0. This code can be removed later | |
11639 | * as A0 is not in production. | |
11640 | */ | |
11641 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
11642 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
11643 | ||
11644 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, | |
11645 | * we need to disable memory and use config. cycles | |
11646 | * only to access all registers. The 5702/03 chips | |
11647 | * can mistakenly decode the special cycles from the | |
11648 | * ICH chipsets as memory write cycles, causing corruption | |
11649 | * of register and memory space. Only certain ICH bridges | |
11650 | * will drive special cycles with non-zero data during the | |
11651 | * address phase which can fall within the 5703's address | |
11652 | * range. This is not an ICH bug as the PCI spec allows | |
11653 | * non-zero address during special cycles. However, only | |
11654 | * these ICH bridges are known to drive non-zero addresses | |
11655 | * during special cycles. | |
11656 | * | |
11657 | * Since special cycles do not cross PCI bridges, we only | |
11658 | * enable this workaround if the 5703 is on the secondary | |
11659 | * bus of these ICH bridges. | |
11660 | */ | |
11661 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
11662 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
11663 | static struct tg3_dev_id { | |
11664 | u32 vendor; | |
11665 | u32 device; | |
11666 | u32 rev; | |
11667 | } ich_chipsets[] = { | |
11668 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
11669 | PCI_ANY_ID }, | |
11670 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
11671 | PCI_ANY_ID }, | |
11672 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
11673 | 0xa }, | |
11674 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
11675 | PCI_ANY_ID }, | |
11676 | { }, | |
11677 | }; | |
11678 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
11679 | struct pci_dev *bridge = NULL; | |
11680 | ||
11681 | while (pci_id->vendor != 0) { | |
11682 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
11683 | bridge); | |
11684 | if (!bridge) { | |
11685 | pci_id++; | |
11686 | continue; | |
11687 | } | |
11688 | if (pci_id->rev != PCI_ANY_ID) { | |
11689 | if (bridge->revision > pci_id->rev) | |
11690 | continue; | |
11691 | } | |
11692 | if (bridge->subordinate && | |
11693 | (bridge->subordinate->number == | |
11694 | tp->pdev->bus->number)) { | |
11695 | ||
11696 | tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND; | |
11697 | pci_dev_put(bridge); | |
11698 | break; | |
11699 | } | |
11700 | } | |
11701 | } | |
11702 | ||
11703 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
11704 | static struct tg3_dev_id { | |
11705 | u32 vendor; | |
11706 | u32 device; | |
11707 | } bridge_chipsets[] = { | |
11708 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
11709 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
11710 | { }, | |
11711 | }; | |
11712 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
11713 | struct pci_dev *bridge = NULL; | |
11714 | ||
11715 | while (pci_id->vendor != 0) { | |
11716 | bridge = pci_get_device(pci_id->vendor, | |
11717 | pci_id->device, | |
11718 | bridge); | |
11719 | if (!bridge) { | |
11720 | pci_id++; | |
11721 | continue; | |
11722 | } | |
11723 | if (bridge->subordinate && | |
11724 | (bridge->subordinate->number <= | |
11725 | tp->pdev->bus->number) && | |
11726 | (bridge->subordinate->subordinate >= | |
11727 | tp->pdev->bus->number)) { | |
11728 | tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG; | |
11729 | pci_dev_put(bridge); | |
11730 | break; | |
11731 | } | |
11732 | } | |
11733 | } | |
11734 | ||
11735 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support | |
11736 | * DMA addresses > 40-bit. This bridge may have other additional | |
11737 | * 57xx devices behind it in some 4-port NIC designs for example. | |
11738 | * Any tg3 device found behind the bridge will also need the 40-bit | |
11739 | * DMA workaround. | |
11740 | */ | |
11741 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || | |
11742 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
11743 | tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; | |
11744 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
11745 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); | |
11746 | } | |
11747 | else { | |
11748 | struct pci_dev *bridge = NULL; | |
11749 | ||
11750 | do { | |
11751 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
11752 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
11753 | bridge); | |
11754 | if (bridge && bridge->subordinate && | |
11755 | (bridge->subordinate->number <= | |
11756 | tp->pdev->bus->number) && | |
11757 | (bridge->subordinate->subordinate >= | |
11758 | tp->pdev->bus->number)) { | |
11759 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
11760 | pci_dev_put(bridge); | |
11761 | break; | |
11762 | } | |
11763 | } while (bridge); | |
11764 | } | |
11765 | ||
11766 | /* Initialize misc host control in PCI block. */ | |
11767 | tp->misc_host_ctrl |= (misc_ctrl_reg & | |
11768 | MISC_HOST_CTRL_CHIPREV); | |
11769 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
11770 | tp->misc_host_ctrl); | |
11771 | ||
11772 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || | |
11773 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) | |
11774 | tp->pdev_peer = tg3_find_peer(tp); | |
11775 | ||
11776 | /* Intentionally exclude ASIC_REV_5906 */ | |
11777 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
11778 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
11779 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
11780 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
11781 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
11782 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
11783 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; | |
11784 | ||
11785 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
11786 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
11787 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || | |
11788 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
11789 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
11790 | tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; | |
11791 | ||
11792 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || | |
11793 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
11794 | tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; | |
11795 | ||
11796 | /* 5700 B0 chips do not support checksumming correctly due | |
11797 | * to hardware bugs. | |
11798 | */ | |
11799 | if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0) | |
11800 | tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS; | |
11801 | else { | |
11802 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
11803 | tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; | |
11804 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
11805 | tp->dev->features |= NETIF_F_IPV6_CSUM; | |
11806 | } | |
11807 | ||
11808 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
11809 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; | |
11810 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | |
11811 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
11812 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
11813 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
11814 | tp->pdev_peer == tp->pdev)) | |
11815 | tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; | |
11816 | ||
11817 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
11818 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
11819 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; | |
11820 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; | |
11821 | } else { | |
11822 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG; | |
11823 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
11824 | ASIC_REV_5750 && | |
11825 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
11826 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG; | |
11827 | } | |
11828 | } | |
11829 | ||
11830 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
11831 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
11832 | tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE; | |
11833 | ||
11834 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
11835 | &pci_state_reg); | |
11836 | ||
11837 | tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); | |
11838 | if (tp->pcie_cap != 0) { | |
11839 | u16 lnkctl; | |
11840 | ||
11841 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; | |
11842 | ||
11843 | pcie_set_readrq(tp->pdev, 4096); | |
11844 | ||
11845 | pci_read_config_word(tp->pdev, | |
11846 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
11847 | &lnkctl); | |
11848 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
11849 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11850 | tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; | |
11851 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
11852 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
11853 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
11854 | tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; | |
11855 | } | |
11856 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
11857 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; | |
11858 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
11859 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
11860 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); | |
11861 | if (!tp->pcix_cap) { | |
11862 | printk(KERN_ERR PFX "Cannot find PCI-X " | |
11863 | "capability, aborting.\n"); | |
11864 | return -EIO; | |
11865 | } | |
11866 | ||
11867 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
11868 | tp->tg3_flags |= TG3_FLAG_PCIX_MODE; | |
11869 | } | |
11870 | ||
11871 | /* If we have an AMD 762 or VIA K8T800 chipset, write | |
11872 | * reordering to the mailbox registers done by the host | |
11873 | * controller can cause major troubles. We read back from | |
11874 | * every mailbox register write to force the writes to be | |
11875 | * posted to the chip in order. | |
11876 | */ | |
11877 | if (pci_dev_present(write_reorder_chipsets) && | |
11878 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
11879 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
11880 | ||
11881 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
11882 | &tp->pci_cacheline_sz); | |
11883 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
11884 | &tp->pci_lat_timer); | |
11885 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
11886 | tp->pci_lat_timer < 64) { | |
11887 | tp->pci_lat_timer = 64; | |
11888 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
11889 | tp->pci_lat_timer); | |
11890 | } | |
11891 | ||
11892 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { | |
11893 | /* 5700 BX chips need to have their TX producer index | |
11894 | * mailboxes written twice to workaround a bug. | |
11895 | */ | |
11896 | tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; | |
11897 | ||
11898 | /* If we are in PCI-X mode, enable register write workaround. | |
11899 | * | |
11900 | * The workaround is to use indirect register accesses | |
11901 | * for all chip writes not to mailbox registers. | |
11902 | */ | |
11903 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
11904 | u32 pm_reg; | |
11905 | ||
11906 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
11907 | ||
11908 | /* The chip can have it's power management PCI config | |
11909 | * space registers clobbered due to this bug. | |
11910 | * So explicitly force the chip into D0 here. | |
11911 | */ | |
11912 | pci_read_config_dword(tp->pdev, | |
11913 | tp->pm_cap + PCI_PM_CTRL, | |
11914 | &pm_reg); | |
11915 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
11916 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
11917 | pci_write_config_dword(tp->pdev, | |
11918 | tp->pm_cap + PCI_PM_CTRL, | |
11919 | pm_reg); | |
11920 | ||
11921 | /* Also, force SERR#/PERR# in PCI command. */ | |
11922 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
11923 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
11924 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
11925 | } | |
11926 | } | |
11927 | ||
11928 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) | |
11929 | tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; | |
11930 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) | |
11931 | tp->tg3_flags |= TG3_FLAG_PCI_32BIT; | |
11932 | ||
11933 | /* Chip-specific fixup from Broadcom driver */ | |
11934 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
11935 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
11936 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
11937 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
11938 | } | |
11939 | ||
11940 | /* Default fast path register access methods */ | |
11941 | tp->read32 = tg3_read32; | |
11942 | tp->write32 = tg3_write32; | |
11943 | tp->read32_mbox = tg3_read32; | |
11944 | tp->write32_mbox = tg3_write32; | |
11945 | tp->write32_tx_mbox = tg3_write32; | |
11946 | tp->write32_rx_mbox = tg3_write32; | |
11947 | ||
11948 | /* Various workaround register access methods */ | |
11949 | if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) | |
11950 | tp->write32 = tg3_write_indirect_reg32; | |
11951 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || | |
11952 | ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
11953 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | |
11954 | /* | |
11955 | * Back to back register writes can cause problems on these | |
11956 | * chips, the workaround is to read back all reg writes | |
11957 | * except those to mailbox regs. | |
11958 | * | |
11959 | * See tg3_write_indirect_reg32(). | |
11960 | */ | |
11961 | tp->write32 = tg3_write_flush_reg32; | |
11962 | } | |
11963 | ||
11964 | ||
11965 | if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || | |
11966 | (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { | |
11967 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
11968 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
11969 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
11970 | } | |
11971 | ||
11972 | if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) { | |
11973 | tp->read32 = tg3_read_indirect_reg32; | |
11974 | tp->write32 = tg3_write_indirect_reg32; | |
11975 | tp->read32_mbox = tg3_read_indirect_mbox; | |
11976 | tp->write32_mbox = tg3_write_indirect_mbox; | |
11977 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
11978 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
11979 | ||
11980 | iounmap(tp->regs); | |
11981 | tp->regs = NULL; | |
11982 | ||
11983 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
11984 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
11985 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
11986 | } | |
11987 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
11988 | tp->read32_mbox = tg3_read32_mbox_5906; | |
11989 | tp->write32_mbox = tg3_write32_mbox_5906; | |
11990 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
11991 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
11992 | } | |
11993 | ||
11994 | if (tp->write32 == tg3_write_indirect_reg32 || | |
11995 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
11996 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
11997 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) | |
11998 | tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; | |
11999 | ||
12000 | /* Get eeprom hw config before calling tg3_set_power_state(). | |
12001 | * In particular, the TG3_FLG2_IS_NIC flag must be | |
12002 | * determined before calling tg3_set_power_state() so that | |
12003 | * we know whether or not to switch out of Vaux power. | |
12004 | * When the flag is set, it means that GPIO1 is used for eeprom | |
12005 | * write protect and also implies that it is a LOM where GPIOs | |
12006 | * are not used to switch power. | |
12007 | */ | |
12008 | tg3_get_eeprom_hw_cfg(tp); | |
12009 | ||
12010 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { | |
12011 | /* Allow reads and writes to the | |
12012 | * APE register and memory space. | |
12013 | */ | |
12014 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
12015 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
12016 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
12017 | pci_state_reg); | |
12018 | } | |
12019 | ||
12020 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
12021 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
12022 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
12023 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
12024 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; | |
12025 | ||
12026 | /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). | |
12027 | * GPIO1 driven high will bring 5700's external PHY out of reset. | |
12028 | * It is also used as eeprom write protect on LOMs. | |
12029 | */ | |
12030 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
12031 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
12032 | (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) | |
12033 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
12034 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
12035 | /* Unused GPIO3 must be driven as output on 5752 because there | |
12036 | * are no pull-up resistors on unused GPIO pins. | |
12037 | */ | |
12038 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
12039 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
12040 | ||
12041 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
12042 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
12043 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
12044 | ||
12045 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) { | |
12046 | /* Turn off the debug UART. */ | |
12047 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
12048 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
12049 | /* Keep VMain power. */ | |
12050 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
12051 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
12052 | } | |
12053 | ||
12054 | /* Force the chip into D0. */ | |
12055 | err = tg3_set_power_state(tp, PCI_D0); | |
12056 | if (err) { | |
12057 | printk(KERN_ERR PFX "(%s) transition to D0 failed\n", | |
12058 | pci_name(tp->pdev)); | |
12059 | return err; | |
12060 | } | |
12061 | ||
12062 | /* Derive initial jumbo mode from MTU assigned in | |
12063 | * ether_setup() via the alloc_etherdev() call | |
12064 | */ | |
12065 | if (tp->dev->mtu > ETH_DATA_LEN && | |
12066 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
12067 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; | |
12068 | ||
12069 | /* Determine WakeOnLan speed to use. */ | |
12070 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12071 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
12072 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
12073 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
12074 | tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB); | |
12075 | } else { | |
12076 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; | |
12077 | } | |
12078 | ||
12079 | /* A few boards don't want Ethernet@WireSpeed phy feature */ | |
12080 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
12081 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
12082 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | |
12083 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || | |
12084 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) || | |
12085 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
12086 | tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; | |
12087 | ||
12088 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
12089 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
12090 | tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG; | |
12091 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) | |
12092 | tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; | |
12093 | ||
12094 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
12095 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 && | |
12096 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
12097 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) { | |
12098 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
12099 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
12100 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
12101 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
12102 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && | |
12103 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
12104 | tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG; | |
12105 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) | |
12106 | tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM; | |
12107 | } else | |
12108 | tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; | |
12109 | } | |
12110 | ||
12111 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
12112 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
12113 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
12114 | if (tp->phy_otp == 0) | |
12115 | tp->phy_otp = TG3_OTP_DEFAULT; | |
12116 | } | |
12117 | ||
12118 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) | |
12119 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; | |
12120 | else | |
12121 | tp->mi_mode = MAC_MI_MODE_BASE; | |
12122 | ||
12123 | tp->coalesce_mode = 0; | |
12124 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && | |
12125 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
12126 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
12127 | ||
12128 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
12129 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
12130 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; | |
12131 | ||
12132 | err = tg3_mdio_init(tp); | |
12133 | if (err) | |
12134 | return err; | |
12135 | ||
12136 | /* Initialize data/descriptor byte/word swapping. */ | |
12137 | val = tr32(GRC_MODE); | |
12138 | val &= GRC_MODE_HOST_STACKUP; | |
12139 | tw32(GRC_MODE, val | tp->grc_mode); | |
12140 | ||
12141 | tg3_switch_clocks(tp); | |
12142 | ||
12143 | /* Clear this out for sanity. */ | |
12144 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
12145 | ||
12146 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
12147 | &pci_state_reg); | |
12148 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
12149 | (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) { | |
12150 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); | |
12151 | ||
12152 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
12153 | chiprevid == CHIPREV_ID_5701_B0 || | |
12154 | chiprevid == CHIPREV_ID_5701_B2 || | |
12155 | chiprevid == CHIPREV_ID_5701_B5) { | |
12156 | void __iomem *sram_base; | |
12157 | ||
12158 | /* Write some dummy words into the SRAM status block | |
12159 | * area, see if it reads back correctly. If the return | |
12160 | * value is bad, force enable the PCIX workaround. | |
12161 | */ | |
12162 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
12163 | ||
12164 | writel(0x00000000, sram_base); | |
12165 | writel(0x00000000, sram_base + 4); | |
12166 | writel(0xffffffff, sram_base + 4); | |
12167 | if (readl(sram_base) != 0x00000000) | |
12168 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
12169 | } | |
12170 | } | |
12171 | ||
12172 | udelay(50); | |
12173 | tg3_nvram_init(tp); | |
12174 | ||
12175 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
12176 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
12177 | ||
12178 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
12179 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
12180 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
12181 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; | |
12182 | ||
12183 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
12184 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) | |
12185 | tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; | |
12186 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
12187 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | |
12188 | HOSTCC_MODE_CLRTICK_TXBD); | |
12189 | ||
12190 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
12191 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12192 | tp->misc_host_ctrl); | |
12193 | } | |
12194 | ||
12195 | /* Preserve the APE MAC_MODE bits */ | |
12196 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
12197 | tp->mac_mode = tr32(MAC_MODE) | | |
12198 | MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
12199 | else | |
12200 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
12201 | ||
12202 | /* these are limited to 10/100 only */ | |
12203 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
12204 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
12205 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
12206 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
12207 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
12208 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
12209 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
12210 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
12211 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
12212 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || | |
12213 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
12214 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || | |
12215 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
12216 | tp->tg3_flags |= TG3_FLAG_10_100_ONLY; | |
12217 | ||
12218 | err = tg3_phy_probe(tp); | |
12219 | if (err) { | |
12220 | printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n", | |
12221 | pci_name(tp->pdev), err); | |
12222 | /* ... but do not return immediately ... */ | |
12223 | tg3_mdio_fini(tp); | |
12224 | } | |
12225 | ||
12226 | tg3_read_partno(tp); | |
12227 | tg3_read_fw_ver(tp); | |
12228 | ||
12229 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
12230 | tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT; | |
12231 | } else { | |
12232 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
12233 | tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT; | |
12234 | else | |
12235 | tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT; | |
12236 | } | |
12237 | ||
12238 | /* 5700 {AX,BX} chips have a broken status block link | |
12239 | * change bit implementation, so we must use the | |
12240 | * status register in those cases. | |
12241 | */ | |
12242 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
12243 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
12244 | else | |
12245 | tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG; | |
12246 | ||
12247 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
12248 | * have to force the link status polling mechanism based | |
12249 | * upon subsystem IDs. | |
12250 | */ | |
12251 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
12252 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && | |
12253 | !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
12254 | tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT | | |
12255 | TG3_FLAG_USE_LINKCHG_REG); | |
12256 | } | |
12257 | ||
12258 | /* For all SERDES we poll the MAC status register. */ | |
12259 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
12260 | tp->tg3_flags |= TG3_FLAG_POLL_SERDES; | |
12261 | else | |
12262 | tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; | |
12263 | ||
12264 | tp->rx_offset = NET_IP_ALIGN; | |
12265 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && | |
12266 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) | |
12267 | tp->rx_offset = 0; | |
12268 | ||
12269 | tp->rx_std_max_post = TG3_RX_RING_SIZE; | |
12270 | ||
12271 | /* Increment the rx prod index on the rx std ring by at most | |
12272 | * 8 for these chips to workaround hw errata. | |
12273 | */ | |
12274 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
12275 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
12276 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
12277 | tp->rx_std_max_post = 8; | |
12278 | ||
12279 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) | |
12280 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & | |
12281 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
12282 | ||
12283 | return err; | |
12284 | } | |
12285 | ||
12286 | #ifdef CONFIG_SPARC | |
12287 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) | |
12288 | { | |
12289 | struct net_device *dev = tp->dev; | |
12290 | struct pci_dev *pdev = tp->pdev; | |
12291 | struct device_node *dp = pci_device_to_OF_node(pdev); | |
12292 | const unsigned char *addr; | |
12293 | int len; | |
12294 | ||
12295 | addr = of_get_property(dp, "local-mac-address", &len); | |
12296 | if (addr && len == 6) { | |
12297 | memcpy(dev->dev_addr, addr, 6); | |
12298 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
12299 | return 0; | |
12300 | } | |
12301 | return -ENODEV; | |
12302 | } | |
12303 | ||
12304 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
12305 | { | |
12306 | struct net_device *dev = tp->dev; | |
12307 | ||
12308 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
12309 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); | |
12310 | return 0; | |
12311 | } | |
12312 | #endif | |
12313 | ||
12314 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
12315 | { | |
12316 | struct net_device *dev = tp->dev; | |
12317 | u32 hi, lo, mac_offset; | |
12318 | int addr_ok = 0; | |
12319 | ||
12320 | #ifdef CONFIG_SPARC | |
12321 | if (!tg3_get_macaddr_sparc(tp)) | |
12322 | return 0; | |
12323 | #endif | |
12324 | ||
12325 | mac_offset = 0x7c; | |
12326 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || | |
12327 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
12328 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
12329 | mac_offset = 0xcc; | |
12330 | if (tg3_nvram_lock(tp)) | |
12331 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
12332 | else | |
12333 | tg3_nvram_unlock(tp); | |
12334 | } | |
12335 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
12336 | mac_offset = 0x10; | |
12337 | ||
12338 | /* First try to get it from MAC address mailbox. */ | |
12339 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
12340 | if ((hi >> 16) == 0x484b) { | |
12341 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
12342 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
12343 | ||
12344 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
12345 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
12346 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
12347 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
12348 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
12349 | ||
12350 | /* Some old bootcode may report a 0 MAC address in SRAM */ | |
12351 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
12352 | } | |
12353 | if (!addr_ok) { | |
12354 | /* Next, try NVRAM. */ | |
12355 | if (!tg3_nvram_read(tp, mac_offset + 0, &hi) && | |
12356 | !tg3_nvram_read(tp, mac_offset + 4, &lo)) { | |
12357 | dev->dev_addr[0] = ((hi >> 16) & 0xff); | |
12358 | dev->dev_addr[1] = ((hi >> 24) & 0xff); | |
12359 | dev->dev_addr[2] = ((lo >> 0) & 0xff); | |
12360 | dev->dev_addr[3] = ((lo >> 8) & 0xff); | |
12361 | dev->dev_addr[4] = ((lo >> 16) & 0xff); | |
12362 | dev->dev_addr[5] = ((lo >> 24) & 0xff); | |
12363 | } | |
12364 | /* Finally just fetch it out of the MAC control regs. */ | |
12365 | else { | |
12366 | hi = tr32(MAC_ADDR_0_HIGH); | |
12367 | lo = tr32(MAC_ADDR_0_LOW); | |
12368 | ||
12369 | dev->dev_addr[5] = lo & 0xff; | |
12370 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
12371 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
12372 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
12373 | dev->dev_addr[1] = hi & 0xff; | |
12374 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
12375 | } | |
12376 | } | |
12377 | ||
12378 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
12379 | #ifdef CONFIG_SPARC | |
12380 | if (!tg3_get_default_macaddr_sparc(tp)) | |
12381 | return 0; | |
12382 | #endif | |
12383 | return -EINVAL; | |
12384 | } | |
12385 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
12386 | return 0; | |
12387 | } | |
12388 | ||
12389 | #define BOUNDARY_SINGLE_CACHELINE 1 | |
12390 | #define BOUNDARY_MULTI_CACHELINE 2 | |
12391 | ||
12392 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
12393 | { | |
12394 | int cacheline_size; | |
12395 | u8 byte; | |
12396 | int goal; | |
12397 | ||
12398 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
12399 | if (byte == 0) | |
12400 | cacheline_size = 1024; | |
12401 | else | |
12402 | cacheline_size = (int) byte * 4; | |
12403 | ||
12404 | /* On 5703 and later chips, the boundary bits have no | |
12405 | * effect. | |
12406 | */ | |
12407 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12408 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
12409 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
12410 | goto out; | |
12411 | ||
12412 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
12413 | goal = BOUNDARY_MULTI_CACHELINE; | |
12414 | #else | |
12415 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
12416 | goal = BOUNDARY_SINGLE_CACHELINE; | |
12417 | #else | |
12418 | goal = 0; | |
12419 | #endif | |
12420 | #endif | |
12421 | ||
12422 | if (!goal) | |
12423 | goto out; | |
12424 | ||
12425 | /* PCI controllers on most RISC systems tend to disconnect | |
12426 | * when a device tries to burst across a cache-line boundary. | |
12427 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
12428 | * | |
12429 | * Unfortunately, for PCI-E there are only limited | |
12430 | * write-side controls for this, and thus for reads | |
12431 | * we will still get the disconnects. We'll also waste | |
12432 | * these PCI cycles for both read and write for chips | |
12433 | * other than 5700 and 5701 which do not implement the | |
12434 | * boundary bits. | |
12435 | */ | |
12436 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
12437 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
12438 | switch (cacheline_size) { | |
12439 | case 16: | |
12440 | case 32: | |
12441 | case 64: | |
12442 | case 128: | |
12443 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12444 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
12445 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
12446 | } else { | |
12447 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
12448 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
12449 | } | |
12450 | break; | |
12451 | ||
12452 | case 256: | |
12453 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
12454 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
12455 | break; | |
12456 | ||
12457 | default: | |
12458 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
12459 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
12460 | break; | |
12461 | } | |
12462 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
12463 | switch (cacheline_size) { | |
12464 | case 16: | |
12465 | case 32: | |
12466 | case 64: | |
12467 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12468 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
12469 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
12470 | break; | |
12471 | } | |
12472 | /* fallthrough */ | |
12473 | case 128: | |
12474 | default: | |
12475 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
12476 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
12477 | break; | |
12478 | } | |
12479 | } else { | |
12480 | switch (cacheline_size) { | |
12481 | case 16: | |
12482 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12483 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
12484 | DMA_RWCTRL_WRITE_BNDRY_16); | |
12485 | break; | |
12486 | } | |
12487 | /* fallthrough */ | |
12488 | case 32: | |
12489 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12490 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
12491 | DMA_RWCTRL_WRITE_BNDRY_32); | |
12492 | break; | |
12493 | } | |
12494 | /* fallthrough */ | |
12495 | case 64: | |
12496 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12497 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
12498 | DMA_RWCTRL_WRITE_BNDRY_64); | |
12499 | break; | |
12500 | } | |
12501 | /* fallthrough */ | |
12502 | case 128: | |
12503 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12504 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
12505 | DMA_RWCTRL_WRITE_BNDRY_128); | |
12506 | break; | |
12507 | } | |
12508 | /* fallthrough */ | |
12509 | case 256: | |
12510 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
12511 | DMA_RWCTRL_WRITE_BNDRY_256); | |
12512 | break; | |
12513 | case 512: | |
12514 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
12515 | DMA_RWCTRL_WRITE_BNDRY_512); | |
12516 | break; | |
12517 | case 1024: | |
12518 | default: | |
12519 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
12520 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
12521 | break; | |
12522 | } | |
12523 | } | |
12524 | ||
12525 | out: | |
12526 | return val; | |
12527 | } | |
12528 | ||
12529 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) | |
12530 | { | |
12531 | struct tg3_internal_buffer_desc test_desc; | |
12532 | u32 sram_dma_descs; | |
12533 | int i, ret; | |
12534 | ||
12535 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
12536 | ||
12537 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
12538 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
12539 | tw32(RDMAC_STATUS, 0); | |
12540 | tw32(WDMAC_STATUS, 0); | |
12541 | ||
12542 | tw32(BUFMGR_MODE, 0); | |
12543 | tw32(FTQ_RESET, 0); | |
12544 | ||
12545 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
12546 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
12547 | test_desc.nic_mbuf = 0x00002100; | |
12548 | test_desc.len = size; | |
12549 | ||
12550 | /* | |
12551 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
12552 | * the *second* time the tg3 driver was getting loaded after an | |
12553 | * initial scan. | |
12554 | * | |
12555 | * Broadcom tells me: | |
12556 | * ...the DMA engine is connected to the GRC block and a DMA | |
12557 | * reset may affect the GRC block in some unpredictable way... | |
12558 | * The behavior of resets to individual blocks has not been tested. | |
12559 | * | |
12560 | * Broadcom noted the GRC reset will also reset all sub-components. | |
12561 | */ | |
12562 | if (to_device) { | |
12563 | test_desc.cqid_sqid = (13 << 8) | 2; | |
12564 | ||
12565 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
12566 | udelay(40); | |
12567 | } else { | |
12568 | test_desc.cqid_sqid = (16 << 8) | 7; | |
12569 | ||
12570 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
12571 | udelay(40); | |
12572 | } | |
12573 | test_desc.flags = 0x00000005; | |
12574 | ||
12575 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
12576 | u32 val; | |
12577 | ||
12578 | val = *(((u32 *)&test_desc) + i); | |
12579 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
12580 | sram_dma_descs + (i * sizeof(u32))); | |
12581 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
12582 | } | |
12583 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
12584 | ||
12585 | if (to_device) { | |
12586 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); | |
12587 | } else { | |
12588 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); | |
12589 | } | |
12590 | ||
12591 | ret = -ENODEV; | |
12592 | for (i = 0; i < 40; i++) { | |
12593 | u32 val; | |
12594 | ||
12595 | if (to_device) | |
12596 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
12597 | else | |
12598 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
12599 | if ((val & 0xffff) == sram_dma_descs) { | |
12600 | ret = 0; | |
12601 | break; | |
12602 | } | |
12603 | ||
12604 | udelay(100); | |
12605 | } | |
12606 | ||
12607 | return ret; | |
12608 | } | |
12609 | ||
12610 | #define TEST_BUFFER_SIZE 0x2000 | |
12611 | ||
12612 | static int __devinit tg3_test_dma(struct tg3 *tp) | |
12613 | { | |
12614 | dma_addr_t buf_dma; | |
12615 | u32 *buf, saved_dma_rwctrl; | |
12616 | int ret; | |
12617 | ||
12618 | buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma); | |
12619 | if (!buf) { | |
12620 | ret = -ENOMEM; | |
12621 | goto out_nofree; | |
12622 | } | |
12623 | ||
12624 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
12625 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
12626 | ||
12627 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); | |
12628 | ||
12629 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
12630 | /* DMA read watermark not used on PCIE */ | |
12631 | tp->dma_rwctrl |= 0x00180000; | |
12632 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
12633 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || | |
12634 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
12635 | tp->dma_rwctrl |= 0x003f0000; | |
12636 | else | |
12637 | tp->dma_rwctrl |= 0x003f000f; | |
12638 | } else { | |
12639 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
12640 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
12641 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
12642 | u32 read_water = 0x7; | |
12643 | ||
12644 | /* If the 5704 is behind the EPB bridge, we can | |
12645 | * do the less restrictive ONE_DMA workaround for | |
12646 | * better performance. | |
12647 | */ | |
12648 | if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) && | |
12649 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
12650 | tp->dma_rwctrl |= 0x8000; | |
12651 | else if (ccval == 0x6 || ccval == 0x7) | |
12652 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; | |
12653 | ||
12654 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) | |
12655 | read_water = 4; | |
12656 | /* Set bit 23 to enable PCIX hw bug fix */ | |
12657 | tp->dma_rwctrl |= | |
12658 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
12659 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
12660 | (1 << 23); | |
12661 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { | |
12662 | /* 5780 always in PCIX mode */ | |
12663 | tp->dma_rwctrl |= 0x00144000; | |
12664 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
12665 | /* 5714 always in PCIX mode */ | |
12666 | tp->dma_rwctrl |= 0x00148000; | |
12667 | } else { | |
12668 | tp->dma_rwctrl |= 0x001b000f; | |
12669 | } | |
12670 | } | |
12671 | ||
12672 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
12673 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
12674 | tp->dma_rwctrl &= 0xfffffff0; | |
12675 | ||
12676 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12677 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
12678 | /* Remove this if it causes problems for some boards. */ | |
12679 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
12680 | ||
12681 | /* On 5700/5701 chips, we need to set this bit. | |
12682 | * Otherwise the chip will issue cacheline transactions | |
12683 | * to streamable DMA memory with not all the byte | |
12684 | * enables turned on. This is an error on several | |
12685 | * RISC PCI controllers, in particular sparc64. | |
12686 | * | |
12687 | * On 5703/5704 chips, this bit has been reassigned | |
12688 | * a different meaning. In particular, it is used | |
12689 | * on those chips to enable a PCI-X workaround. | |
12690 | */ | |
12691 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
12692 | } | |
12693 | ||
12694 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
12695 | ||
12696 | #if 0 | |
12697 | /* Unneeded, already done by tg3_get_invariants. */ | |
12698 | tg3_switch_clocks(tp); | |
12699 | #endif | |
12700 | ||
12701 | ret = 0; | |
12702 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12703 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
12704 | goto out; | |
12705 | ||
12706 | /* It is best to perform DMA test with maximum write burst size | |
12707 | * to expose the 5700/5701 write DMA bug. | |
12708 | */ | |
12709 | saved_dma_rwctrl = tp->dma_rwctrl; | |
12710 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
12711 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
12712 | ||
12713 | while (1) { | |
12714 | u32 *p = buf, i; | |
12715 | ||
12716 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
12717 | p[i] = i; | |
12718 | ||
12719 | /* Send the buffer to the chip. */ | |
12720 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
12721 | if (ret) { | |
12722 | printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret); | |
12723 | break; | |
12724 | } | |
12725 | ||
12726 | #if 0 | |
12727 | /* validate data reached card RAM correctly. */ | |
12728 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
12729 | u32 val; | |
12730 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
12731 | if (le32_to_cpu(val) != p[i]) { | |
12732 | printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i); | |
12733 | /* ret = -ENODEV here? */ | |
12734 | } | |
12735 | p[i] = 0; | |
12736 | } | |
12737 | #endif | |
12738 | /* Now read it back. */ | |
12739 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
12740 | if (ret) { | |
12741 | printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret); | |
12742 | ||
12743 | break; | |
12744 | } | |
12745 | ||
12746 | /* Verify it. */ | |
12747 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
12748 | if (p[i] == i) | |
12749 | continue; | |
12750 | ||
12751 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != | |
12752 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
12753 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
12754 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
12755 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
12756 | break; | |
12757 | } else { | |
12758 | printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i); | |
12759 | ret = -ENODEV; | |
12760 | goto out; | |
12761 | } | |
12762 | } | |
12763 | ||
12764 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
12765 | /* Success. */ | |
12766 | ret = 0; | |
12767 | break; | |
12768 | } | |
12769 | } | |
12770 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != | |
12771 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
12772 | static struct pci_device_id dma_wait_state_chipsets[] = { | |
12773 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, | |
12774 | PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, | |
12775 | { }, | |
12776 | }; | |
12777 | ||
12778 | /* DMA test passed without adjusting DMA boundary, | |
12779 | * now look for chipsets that are known to expose the | |
12780 | * DMA bug without failing the test. | |
12781 | */ | |
12782 | if (pci_dev_present(dma_wait_state_chipsets)) { | |
12783 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
12784 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
12785 | } | |
12786 | else | |
12787 | /* Safe to use the calculated DMA boundary. */ | |
12788 | tp->dma_rwctrl = saved_dma_rwctrl; | |
12789 | ||
12790 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
12791 | } | |
12792 | ||
12793 | out: | |
12794 | pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma); | |
12795 | out_nofree: | |
12796 | return ret; | |
12797 | } | |
12798 | ||
12799 | static void __devinit tg3_init_link_config(struct tg3 *tp) | |
12800 | { | |
12801 | tp->link_config.advertising = | |
12802 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
12803 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
12804 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | | |
12805 | ADVERTISED_Autoneg | ADVERTISED_MII); | |
12806 | tp->link_config.speed = SPEED_INVALID; | |
12807 | tp->link_config.duplex = DUPLEX_INVALID; | |
12808 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
12809 | tp->link_config.active_speed = SPEED_INVALID; | |
12810 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
12811 | tp->link_config.phy_is_low_power = 0; | |
12812 | tp->link_config.orig_speed = SPEED_INVALID; | |
12813 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
12814 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
12815 | } | |
12816 | ||
12817 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) | |
12818 | { | |
12819 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
12820 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
12821 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
12822 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
12823 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
12824 | tp->bufmgr_config.mbuf_high_water = | |
12825 | DEFAULT_MB_HIGH_WATER_5705; | |
12826 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
12827 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
12828 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
12829 | tp->bufmgr_config.mbuf_high_water = | |
12830 | DEFAULT_MB_HIGH_WATER_5906; | |
12831 | } | |
12832 | ||
12833 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
12834 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
12835 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
12836 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
12837 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
12838 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
12839 | } else { | |
12840 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
12841 | DEFAULT_MB_RDMA_LOW_WATER; | |
12842 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
12843 | DEFAULT_MB_MACRX_LOW_WATER; | |
12844 | tp->bufmgr_config.mbuf_high_water = | |
12845 | DEFAULT_MB_HIGH_WATER; | |
12846 | ||
12847 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
12848 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
12849 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
12850 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
12851 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
12852 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
12853 | } | |
12854 | ||
12855 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
12856 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
12857 | } | |
12858 | ||
12859 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
12860 | { | |
12861 | switch (tp->phy_id & PHY_ID_MASK) { | |
12862 | case PHY_ID_BCM5400: return "5400"; | |
12863 | case PHY_ID_BCM5401: return "5401"; | |
12864 | case PHY_ID_BCM5411: return "5411"; | |
12865 | case PHY_ID_BCM5701: return "5701"; | |
12866 | case PHY_ID_BCM5703: return "5703"; | |
12867 | case PHY_ID_BCM5704: return "5704"; | |
12868 | case PHY_ID_BCM5705: return "5705"; | |
12869 | case PHY_ID_BCM5750: return "5750"; | |
12870 | case PHY_ID_BCM5752: return "5752"; | |
12871 | case PHY_ID_BCM5714: return "5714"; | |
12872 | case PHY_ID_BCM5780: return "5780"; | |
12873 | case PHY_ID_BCM5755: return "5755"; | |
12874 | case PHY_ID_BCM5787: return "5787"; | |
12875 | case PHY_ID_BCM5784: return "5784"; | |
12876 | case PHY_ID_BCM5756: return "5722/5756"; | |
12877 | case PHY_ID_BCM5906: return "5906"; | |
12878 | case PHY_ID_BCM5761: return "5761"; | |
12879 | case PHY_ID_BCM8002: return "8002/serdes"; | |
12880 | case 0: return "serdes"; | |
12881 | default: return "unknown"; | |
12882 | } | |
12883 | } | |
12884 | ||
12885 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) | |
12886 | { | |
12887 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
12888 | strcpy(str, "PCI Express"); | |
12889 | return str; | |
12890 | } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
12891 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; | |
12892 | ||
12893 | strcpy(str, "PCIX:"); | |
12894 | ||
12895 | if ((clock_ctrl == 7) || | |
12896 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
12897 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
12898 | strcat(str, "133MHz"); | |
12899 | else if (clock_ctrl == 0) | |
12900 | strcat(str, "33MHz"); | |
12901 | else if (clock_ctrl == 2) | |
12902 | strcat(str, "50MHz"); | |
12903 | else if (clock_ctrl == 4) | |
12904 | strcat(str, "66MHz"); | |
12905 | else if (clock_ctrl == 6) | |
12906 | strcat(str, "100MHz"); | |
12907 | } else { | |
12908 | strcpy(str, "PCI:"); | |
12909 | if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) | |
12910 | strcat(str, "66MHz"); | |
12911 | else | |
12912 | strcat(str, "33MHz"); | |
12913 | } | |
12914 | if (tp->tg3_flags & TG3_FLAG_PCI_32BIT) | |
12915 | strcat(str, ":32-bit"); | |
12916 | else | |
12917 | strcat(str, ":64-bit"); | |
12918 | return str; | |
12919 | } | |
12920 | ||
12921 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) | |
12922 | { | |
12923 | struct pci_dev *peer; | |
12924 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
12925 | ||
12926 | for (func = 0; func < 8; func++) { | |
12927 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
12928 | if (peer && peer != tp->pdev) | |
12929 | break; | |
12930 | pci_dev_put(peer); | |
12931 | } | |
12932 | /* 5704 can be configured in single-port mode, set peer to | |
12933 | * tp->pdev in that case. | |
12934 | */ | |
12935 | if (!peer) { | |
12936 | peer = tp->pdev; | |
12937 | return peer; | |
12938 | } | |
12939 | ||
12940 | /* | |
12941 | * We don't need to keep the refcount elevated; there's no way | |
12942 | * to remove one half of this device without removing the other | |
12943 | */ | |
12944 | pci_dev_put(peer); | |
12945 | ||
12946 | return peer; | |
12947 | } | |
12948 | ||
12949 | static void __devinit tg3_init_coal(struct tg3 *tp) | |
12950 | { | |
12951 | struct ethtool_coalesce *ec = &tp->coal; | |
12952 | ||
12953 | memset(ec, 0, sizeof(*ec)); | |
12954 | ec->cmd = ETHTOOL_GCOALESCE; | |
12955 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
12956 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
12957 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
12958 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
12959 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
12960 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
12961 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
12962 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
12963 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
12964 | ||
12965 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
12966 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
12967 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
12968 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
12969 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
12970 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
12971 | } | |
12972 | ||
12973 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
12974 | ec->rx_coalesce_usecs_irq = 0; | |
12975 | ec->tx_coalesce_usecs_irq = 0; | |
12976 | ec->stats_block_coalesce_usecs = 0; | |
12977 | } | |
12978 | } | |
12979 | ||
12980 | static const struct net_device_ops tg3_netdev_ops = { | |
12981 | .ndo_open = tg3_open, | |
12982 | .ndo_stop = tg3_close, | |
12983 | .ndo_start_xmit = tg3_start_xmit, | |
12984 | .ndo_get_stats = tg3_get_stats, | |
12985 | .ndo_validate_addr = eth_validate_addr, | |
12986 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
12987 | .ndo_set_mac_address = tg3_set_mac_addr, | |
12988 | .ndo_do_ioctl = tg3_ioctl, | |
12989 | .ndo_tx_timeout = tg3_tx_timeout, | |
12990 | .ndo_change_mtu = tg3_change_mtu, | |
12991 | #if TG3_VLAN_TAG_USED | |
12992 | .ndo_vlan_rx_register = tg3_vlan_rx_register, | |
12993 | #endif | |
12994 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
12995 | .ndo_poll_controller = tg3_poll_controller, | |
12996 | #endif | |
12997 | }; | |
12998 | ||
12999 | static const struct net_device_ops tg3_netdev_ops_dma_bug = { | |
13000 | .ndo_open = tg3_open, | |
13001 | .ndo_stop = tg3_close, | |
13002 | .ndo_start_xmit = tg3_start_xmit_dma_bug, | |
13003 | .ndo_get_stats = tg3_get_stats, | |
13004 | .ndo_validate_addr = eth_validate_addr, | |
13005 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
13006 | .ndo_set_mac_address = tg3_set_mac_addr, | |
13007 | .ndo_do_ioctl = tg3_ioctl, | |
13008 | .ndo_tx_timeout = tg3_tx_timeout, | |
13009 | .ndo_change_mtu = tg3_change_mtu, | |
13010 | #if TG3_VLAN_TAG_USED | |
13011 | .ndo_vlan_rx_register = tg3_vlan_rx_register, | |
13012 | #endif | |
13013 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
13014 | .ndo_poll_controller = tg3_poll_controller, | |
13015 | #endif | |
13016 | }; | |
13017 | ||
13018 | static int __devinit tg3_init_one(struct pci_dev *pdev, | |
13019 | const struct pci_device_id *ent) | |
13020 | { | |
13021 | static int tg3_version_printed = 0; | |
13022 | struct net_device *dev; | |
13023 | struct tg3 *tp; | |
13024 | int err, pm_cap; | |
13025 | char str[40]; | |
13026 | u64 dma_mask, persist_dma_mask; | |
13027 | ||
13028 | if (tg3_version_printed++ == 0) | |
13029 | printk(KERN_INFO "%s", version); | |
13030 | ||
13031 | err = pci_enable_device(pdev); | |
13032 | if (err) { | |
13033 | printk(KERN_ERR PFX "Cannot enable PCI device, " | |
13034 | "aborting.\n"); | |
13035 | return err; | |
13036 | } | |
13037 | ||
13038 | err = pci_request_regions(pdev, DRV_MODULE_NAME); | |
13039 | if (err) { | |
13040 | printk(KERN_ERR PFX "Cannot obtain PCI resources, " | |
13041 | "aborting.\n"); | |
13042 | goto err_out_disable_pdev; | |
13043 | } | |
13044 | ||
13045 | pci_set_master(pdev); | |
13046 | ||
13047 | /* Find power-management capability. */ | |
13048 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
13049 | if (pm_cap == 0) { | |
13050 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
13051 | "aborting.\n"); | |
13052 | err = -EIO; | |
13053 | goto err_out_free_res; | |
13054 | } | |
13055 | ||
13056 | dev = alloc_etherdev(sizeof(*tp)); | |
13057 | if (!dev) { | |
13058 | printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n"); | |
13059 | err = -ENOMEM; | |
13060 | goto err_out_free_res; | |
13061 | } | |
13062 | ||
13063 | SET_NETDEV_DEV(dev, &pdev->dev); | |
13064 | ||
13065 | #if TG3_VLAN_TAG_USED | |
13066 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
13067 | #endif | |
13068 | ||
13069 | tp = netdev_priv(dev); | |
13070 | tp->pdev = pdev; | |
13071 | tp->dev = dev; | |
13072 | tp->pm_cap = pm_cap; | |
13073 | tp->rx_mode = TG3_DEF_RX_MODE; | |
13074 | tp->tx_mode = TG3_DEF_TX_MODE; | |
13075 | ||
13076 | if (tg3_debug > 0) | |
13077 | tp->msg_enable = tg3_debug; | |
13078 | else | |
13079 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
13080 | ||
13081 | /* The word/byte swap controls here control register access byte | |
13082 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
13083 | * setting below. | |
13084 | */ | |
13085 | tp->misc_host_ctrl = | |
13086 | MISC_HOST_CTRL_MASK_PCI_INT | | |
13087 | MISC_HOST_CTRL_WORD_SWAP | | |
13088 | MISC_HOST_CTRL_INDIR_ACCESS | | |
13089 | MISC_HOST_CTRL_PCISTATE_RW; | |
13090 | ||
13091 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
13092 | * on descriptor entries, anything which isn't packet data. | |
13093 | * | |
13094 | * The StrongARM chips on the board (one for tx, one for rx) | |
13095 | * are running in big-endian mode. | |
13096 | */ | |
13097 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
13098 | GRC_MODE_WSWAP_NONFRM_DATA); | |
13099 | #ifdef __BIG_ENDIAN | |
13100 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
13101 | #endif | |
13102 | spin_lock_init(&tp->lock); | |
13103 | spin_lock_init(&tp->indirect_lock); | |
13104 | INIT_WORK(&tp->reset_task, tg3_reset_task); | |
13105 | ||
13106 | tp->regs = pci_ioremap_bar(pdev, BAR_0); | |
13107 | if (!tp->regs) { | |
13108 | printk(KERN_ERR PFX "Cannot map device registers, " | |
13109 | "aborting.\n"); | |
13110 | err = -ENOMEM; | |
13111 | goto err_out_free_dev; | |
13112 | } | |
13113 | ||
13114 | tg3_init_link_config(tp); | |
13115 | ||
13116 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; | |
13117 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
13118 | tp->tx_pending = TG3_DEF_TX_RING_PENDING; | |
13119 | ||
13120 | netif_napi_add(dev, &tp->napi, tg3_poll, 64); | |
13121 | dev->ethtool_ops = &tg3_ethtool_ops; | |
13122 | dev->watchdog_timeo = TG3_TX_TIMEOUT; | |
13123 | dev->irq = pdev->irq; | |
13124 | ||
13125 | err = tg3_get_invariants(tp); | |
13126 | if (err) { | |
13127 | printk(KERN_ERR PFX "Problem fetching invariants of chip, " | |
13128 | "aborting.\n"); | |
13129 | goto err_out_iounmap; | |
13130 | } | |
13131 | ||
13132 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
13133 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
13134 | dev->netdev_ops = &tg3_netdev_ops; | |
13135 | else | |
13136 | dev->netdev_ops = &tg3_netdev_ops_dma_bug; | |
13137 | ||
13138 | ||
13139 | /* The EPB bridge inside 5714, 5715, and 5780 and any | |
13140 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
13141 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. | |
13142 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
13143 | * do DMA address check in tg3_start_xmit(). | |
13144 | */ | |
13145 | if (tp->tg3_flags2 & TG3_FLG2_IS_5788) | |
13146 | persist_dma_mask = dma_mask = DMA_32BIT_MASK; | |
13147 | else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { | |
13148 | persist_dma_mask = dma_mask = DMA_40BIT_MASK; | |
13149 | #ifdef CONFIG_HIGHMEM | |
13150 | dma_mask = DMA_64BIT_MASK; | |
13151 | #endif | |
13152 | } else | |
13153 | persist_dma_mask = dma_mask = DMA_64BIT_MASK; | |
13154 | ||
13155 | /* Configure DMA attributes. */ | |
13156 | if (dma_mask > DMA_32BIT_MASK) { | |
13157 | err = pci_set_dma_mask(pdev, dma_mask); | |
13158 | if (!err) { | |
13159 | dev->features |= NETIF_F_HIGHDMA; | |
13160 | err = pci_set_consistent_dma_mask(pdev, | |
13161 | persist_dma_mask); | |
13162 | if (err < 0) { | |
13163 | printk(KERN_ERR PFX "Unable to obtain 64 bit " | |
13164 | "DMA for consistent allocations\n"); | |
13165 | goto err_out_iounmap; | |
13166 | } | |
13167 | } | |
13168 | } | |
13169 | if (err || dma_mask == DMA_32BIT_MASK) { | |
13170 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
13171 | if (err) { | |
13172 | printk(KERN_ERR PFX "No usable DMA configuration, " | |
13173 | "aborting.\n"); | |
13174 | goto err_out_iounmap; | |
13175 | } | |
13176 | } | |
13177 | ||
13178 | tg3_init_bufmgr_config(tp); | |
13179 | ||
13180 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
13181 | tp->fw_needed = FIRMWARE_TG3; | |
13182 | ||
13183 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { | |
13184 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; | |
13185 | } | |
13186 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13187 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || | |
13188 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 || | |
13189 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || | |
13190 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { | |
13191 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; | |
13192 | } else { | |
13193 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG; | |
13194 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) | |
13195 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13196 | else | |
13197 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13198 | } | |
13199 | ||
13200 | /* TSO is on by default on chips that support hardware TSO. | |
13201 | * Firmware TSO on older chips gives lower performance, so it | |
13202 | * is off by default, but can be enabled using ethtool. | |
13203 | */ | |
13204 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { | |
13205 | if (dev->features & NETIF_F_IP_CSUM) | |
13206 | dev->features |= NETIF_F_TSO; | |
13207 | if ((dev->features & NETIF_F_IPV6_CSUM) && | |
13208 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) | |
13209 | dev->features |= NETIF_F_TSO6; | |
13210 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
13211 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
13212 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
13213 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
13214 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
13215 | dev->features |= NETIF_F_TSO_ECN; | |
13216 | } | |
13217 | ||
13218 | ||
13219 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && | |
13220 | !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && | |
13221 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | |
13222 | tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64; | |
13223 | tp->rx_pending = 63; | |
13224 | } | |
13225 | ||
13226 | err = tg3_get_device_address(tp); | |
13227 | if (err) { | |
13228 | printk(KERN_ERR PFX "Could not obtain valid ethernet address, " | |
13229 | "aborting.\n"); | |
13230 | goto err_out_fw; | |
13231 | } | |
13232 | ||
13233 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { | |
13234 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
13235 | if (!tp->aperegs) { | |
13236 | printk(KERN_ERR PFX "Cannot map APE registers, " | |
13237 | "aborting.\n"); | |
13238 | err = -ENOMEM; | |
13239 | goto err_out_fw; | |
13240 | } | |
13241 | ||
13242 | tg3_ape_lock_init(tp); | |
13243 | } | |
13244 | ||
13245 | /* | |
13246 | * Reset chip in case UNDI or EFI driver did not shutdown | |
13247 | * DMA self test will enable WDMAC and we'll see (spurious) | |
13248 | * pending DMA on the PCI bus at that point. | |
13249 | */ | |
13250 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
13251 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
13252 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); | |
13253 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
13254 | } | |
13255 | ||
13256 | err = tg3_test_dma(tp); | |
13257 | if (err) { | |
13258 | printk(KERN_ERR PFX "DMA engine test failed, aborting.\n"); | |
13259 | goto err_out_apeunmap; | |
13260 | } | |
13261 | ||
13262 | /* flow control autonegotiation is default behavior */ | |
13263 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
13264 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
13265 | ||
13266 | tg3_init_coal(tp); | |
13267 | ||
13268 | pci_set_drvdata(pdev, dev); | |
13269 | ||
13270 | err = register_netdev(dev); | |
13271 | if (err) { | |
13272 | printk(KERN_ERR PFX "Cannot register net device, " | |
13273 | "aborting.\n"); | |
13274 | goto err_out_apeunmap; | |
13275 | } | |
13276 | ||
13277 | printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", | |
13278 | dev->name, | |
13279 | tp->board_part_number, | |
13280 | tp->pci_chip_rev_id, | |
13281 | tg3_bus_string(tp, str), | |
13282 | dev->dev_addr); | |
13283 | ||
13284 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) | |
13285 | printk(KERN_INFO | |
13286 | "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
13287 | tp->dev->name, | |
13288 | tp->mdio_bus->phy_map[PHY_ADDR]->drv->name, | |
13289 | dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev)); | |
13290 | else | |
13291 | printk(KERN_INFO | |
13292 | "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n", | |
13293 | tp->dev->name, tg3_phy_string(tp), | |
13294 | ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" : | |
13295 | ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" : | |
13296 | "10/100/1000Base-T")), | |
13297 | (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0); | |
13298 | ||
13299 | printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
13300 | dev->name, | |
13301 | (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0, | |
13302 | (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, | |
13303 | (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0, | |
13304 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, | |
13305 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); | |
13306 | printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n", | |
13307 | dev->name, tp->dma_rwctrl, | |
13308 | (pdev->dma_mask == DMA_32BIT_MASK) ? 32 : | |
13309 | (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64)); | |
13310 | ||
13311 | return 0; | |
13312 | ||
13313 | err_out_apeunmap: | |
13314 | if (tp->aperegs) { | |
13315 | iounmap(tp->aperegs); | |
13316 | tp->aperegs = NULL; | |
13317 | } | |
13318 | ||
13319 | err_out_fw: | |
13320 | if (tp->fw) | |
13321 | release_firmware(tp->fw); | |
13322 | ||
13323 | err_out_iounmap: | |
13324 | if (tp->regs) { | |
13325 | iounmap(tp->regs); | |
13326 | tp->regs = NULL; | |
13327 | } | |
13328 | ||
13329 | err_out_free_dev: | |
13330 | free_netdev(dev); | |
13331 | ||
13332 | err_out_free_res: | |
13333 | pci_release_regions(pdev); | |
13334 | ||
13335 | err_out_disable_pdev: | |
13336 | pci_disable_device(pdev); | |
13337 | pci_set_drvdata(pdev, NULL); | |
13338 | return err; | |
13339 | } | |
13340 | ||
13341 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
13342 | { | |
13343 | struct net_device *dev = pci_get_drvdata(pdev); | |
13344 | ||
13345 | if (dev) { | |
13346 | struct tg3 *tp = netdev_priv(dev); | |
13347 | ||
13348 | if (tp->fw) | |
13349 | release_firmware(tp->fw); | |
13350 | ||
13351 | flush_scheduled_work(); | |
13352 | ||
13353 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
13354 | tg3_phy_fini(tp); | |
13355 | tg3_mdio_fini(tp); | |
13356 | } | |
13357 | ||
13358 | unregister_netdev(dev); | |
13359 | if (tp->aperegs) { | |
13360 | iounmap(tp->aperegs); | |
13361 | tp->aperegs = NULL; | |
13362 | } | |
13363 | if (tp->regs) { | |
13364 | iounmap(tp->regs); | |
13365 | tp->regs = NULL; | |
13366 | } | |
13367 | free_netdev(dev); | |
13368 | pci_release_regions(pdev); | |
13369 | pci_disable_device(pdev); | |
13370 | pci_set_drvdata(pdev, NULL); | |
13371 | } | |
13372 | } | |
13373 | ||
13374 | static int tg3_suspend(struct pci_dev *pdev, pm_message_t state) | |
13375 | { | |
13376 | struct net_device *dev = pci_get_drvdata(pdev); | |
13377 | struct tg3 *tp = netdev_priv(dev); | |
13378 | pci_power_t target_state; | |
13379 | int err; | |
13380 | ||
13381 | /* PCI register 4 needs to be saved whether netif_running() or not. | |
13382 | * MSI address and data need to be saved if using MSI and | |
13383 | * netif_running(). | |
13384 | */ | |
13385 | pci_save_state(pdev); | |
13386 | ||
13387 | if (!netif_running(dev)) | |
13388 | return 0; | |
13389 | ||
13390 | flush_scheduled_work(); | |
13391 | tg3_phy_stop(tp); | |
13392 | tg3_netif_stop(tp); | |
13393 | ||
13394 | del_timer_sync(&tp->timer); | |
13395 | ||
13396 | tg3_full_lock(tp, 1); | |
13397 | tg3_disable_ints(tp); | |
13398 | tg3_full_unlock(tp); | |
13399 | ||
13400 | netif_device_detach(dev); | |
13401 | ||
13402 | tg3_full_lock(tp, 0); | |
13403 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
13404 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
13405 | tg3_full_unlock(tp); | |
13406 | ||
13407 | target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot; | |
13408 | ||
13409 | err = tg3_set_power_state(tp, target_state); | |
13410 | if (err) { | |
13411 | int err2; | |
13412 | ||
13413 | tg3_full_lock(tp, 0); | |
13414 | ||
13415 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
13416 | err2 = tg3_restart_hw(tp, 1); | |
13417 | if (err2) | |
13418 | goto out; | |
13419 | ||
13420 | tp->timer.expires = jiffies + tp->timer_offset; | |
13421 | add_timer(&tp->timer); | |
13422 | ||
13423 | netif_device_attach(dev); | |
13424 | tg3_netif_start(tp); | |
13425 | ||
13426 | out: | |
13427 | tg3_full_unlock(tp); | |
13428 | ||
13429 | if (!err2) | |
13430 | tg3_phy_start(tp); | |
13431 | } | |
13432 | ||
13433 | return err; | |
13434 | } | |
13435 | ||
13436 | static int tg3_resume(struct pci_dev *pdev) | |
13437 | { | |
13438 | struct net_device *dev = pci_get_drvdata(pdev); | |
13439 | struct tg3 *tp = netdev_priv(dev); | |
13440 | int err; | |
13441 | ||
13442 | pci_restore_state(tp->pdev); | |
13443 | ||
13444 | if (!netif_running(dev)) | |
13445 | return 0; | |
13446 | ||
13447 | err = tg3_set_power_state(tp, PCI_D0); | |
13448 | if (err) | |
13449 | return err; | |
13450 | ||
13451 | netif_device_attach(dev); | |
13452 | ||
13453 | tg3_full_lock(tp, 0); | |
13454 | ||
13455 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
13456 | err = tg3_restart_hw(tp, 1); | |
13457 | if (err) | |
13458 | goto out; | |
13459 | ||
13460 | tp->timer.expires = jiffies + tp->timer_offset; | |
13461 | add_timer(&tp->timer); | |
13462 | ||
13463 | tg3_netif_start(tp); | |
13464 | ||
13465 | out: | |
13466 | tg3_full_unlock(tp); | |
13467 | ||
13468 | if (!err) | |
13469 | tg3_phy_start(tp); | |
13470 | ||
13471 | return err; | |
13472 | } | |
13473 | ||
13474 | static struct pci_driver tg3_driver = { | |
13475 | .name = DRV_MODULE_NAME, | |
13476 | .id_table = tg3_pci_tbl, | |
13477 | .probe = tg3_init_one, | |
13478 | .remove = __devexit_p(tg3_remove_one), | |
13479 | .suspend = tg3_suspend, | |
13480 | .resume = tg3_resume | |
13481 | }; | |
13482 | ||
13483 | static int __init tg3_init(void) | |
13484 | { | |
13485 | return pci_register_driver(&tg3_driver); | |
13486 | } | |
13487 | ||
13488 | static void __exit tg3_cleanup(void) | |
13489 | { | |
13490 | pci_unregister_driver(&tg3_driver); | |
13491 | } | |
13492 | ||
13493 | module_init(tg3_init); | |
13494 | module_exit(tg3_cleanup); |