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tg3: Disable TSS also during tg3_close()
[net-next-2.6.git] / drivers / net / tg3.c
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CommitLineData
1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/stringify.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/in.h>
28#include <linux/init.h>
29#include <linux/ioport.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ethtool.h>
35#include <linux/mii.h>
36#include <linux/phy.h>
37#include <linux/brcmphy.h>
38#include <linux/if_vlan.h>
39#include <linux/ip.h>
40#include <linux/tcp.h>
41#include <linux/workqueue.h>
42#include <linux/prefetch.h>
43#include <linux/dma-mapping.h>
44#include <linux/firmware.h>
45
46#include <net/checksum.h>
47#include <net/ip.h>
48
49#include <asm/system.h>
50#include <asm/io.h>
51#include <asm/byteorder.h>
52#include <asm/uaccess.h>
53
54#ifdef CONFIG_SPARC
55#include <asm/idprom.h>
56#include <asm/prom.h>
57#endif
58
59#define BAR_0 0
60#define BAR_2 2
61
62#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63#define TG3_VLAN_TAG_USED 1
64#else
65#define TG3_VLAN_TAG_USED 0
66#endif
67
68#include "tg3.h"
69
70#define DRV_MODULE_NAME "tg3"
71#define TG3_MAJ_NUM 3
72#define TG3_MIN_NUM 112
73#define DRV_MODULE_VERSION \
74 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75#define DRV_MODULE_RELDATE "July 11, 2010"
76
77#define TG3_DEF_MAC_MODE 0
78#define TG3_DEF_RX_MODE 0
79#define TG3_DEF_TX_MODE 0
80#define TG3_DEF_MSG_ENABLE \
81 (NETIF_MSG_DRV | \
82 NETIF_MSG_PROBE | \
83 NETIF_MSG_LINK | \
84 NETIF_MSG_TIMER | \
85 NETIF_MSG_IFDOWN | \
86 NETIF_MSG_IFUP | \
87 NETIF_MSG_RX_ERR | \
88 NETIF_MSG_TX_ERR)
89
90/* length of time before we decide the hardware is borked,
91 * and dev->tx_timeout() should be called to fix the problem
92 */
93#define TG3_TX_TIMEOUT (5 * HZ)
94
95/* hardware minimum and maximum for a single frame's data payload */
96#define TG3_MIN_MTU 60
97#define TG3_MAX_MTU(tp) \
98 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
99
100/* These numbers seem to be hard coded in the NIC firmware somehow.
101 * You can't change the ring sizes, but you can change where you place
102 * them in the NIC onboard memory.
103 */
104#define TG3_RX_RING_SIZE 512
105#define TG3_DEF_RX_RING_PENDING 200
106#define TG3_RX_JUMBO_RING_SIZE 256
107#define TG3_DEF_RX_JUMBO_RING_PENDING 100
108#define TG3_RSS_INDIR_TBL_SIZE 128
109
110/* Do not place this n-ring entries value into the tp struct itself,
111 * we really want to expose these constants to GCC so that modulo et
112 * al. operations are done with shifts and masks instead of with
113 * hw multiply/modulo instructions. Another solution would be to
114 * replace things like '% foo' with '& (foo - 1)'.
115 */
116#define TG3_RX_RCB_RING_SIZE(tp) \
117 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
118 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
119
120#define TG3_TX_RING_SIZE 512
121#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
122
123#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RING_SIZE)
125#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
126 TG3_RX_JUMBO_RING_SIZE)
127#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
128 TG3_RX_RCB_RING_SIZE(tp))
129#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
130 TG3_TX_RING_SIZE)
131#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
132
133#define TG3_RX_DMA_ALIGN 16
134#define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
135
136#define TG3_DMA_BYTE_ENAB 64
137
138#define TG3_RX_STD_DMA_SZ 1536
139#define TG3_RX_JMB_DMA_SZ 9046
140
141#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
142
143#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
144#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
145
146#define TG3_RX_STD_BUFF_RING_SIZE \
147 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
148
149#define TG3_RX_JMB_BUFF_RING_SIZE \
150 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
151
152/* Due to a hardware bug, the 5701 can only DMA to memory addresses
153 * that are at least dword aligned when used in PCIX mode. The driver
154 * works around this bug by double copying the packet. This workaround
155 * is built into the normal double copy length check for efficiency.
156 *
157 * However, the double copy is only necessary on those architectures
158 * where unaligned memory accesses are inefficient. For those architectures
159 * where unaligned memory accesses incur little penalty, we can reintegrate
160 * the 5701 in the normal rx path. Doing so saves a device structure
161 * dereference by hardcoding the double copy threshold in place.
162 */
163#define TG3_RX_COPY_THRESHOLD 256
164#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
165 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
166#else
167 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
168#endif
169
170/* minimum number of free TX descriptors required to wake up TX process */
171#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
172
173#define TG3_RAW_IP_ALIGN 2
174
175/* number of ETHTOOL_GSTATS u64's */
176#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
177
178#define TG3_NUM_TEST 6
179
180#define TG3_FW_UPDATE_TIMEOUT_SEC 5
181
182#define FIRMWARE_TG3 "tigon/tg3.bin"
183#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
184#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
185
186static char version[] __devinitdata =
187 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
188
189MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
190MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
191MODULE_LICENSE("GPL");
192MODULE_VERSION(DRV_MODULE_VERSION);
193MODULE_FIRMWARE(FIRMWARE_TG3);
194MODULE_FIRMWARE(FIRMWARE_TG3TSO);
195MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
196
197static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
198module_param(tg3_debug, int, 0);
199MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
200
201static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
278 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
279 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
281 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
282 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
283 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
284 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
285 {}
286};
287
288MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
289
290static const struct {
291 const char string[ETH_GSTRING_LEN];
292} ethtool_stats_keys[TG3_NUM_STATS] = {
293 { "rx_octets" },
294 { "rx_fragments" },
295 { "rx_ucast_packets" },
296 { "rx_mcast_packets" },
297 { "rx_bcast_packets" },
298 { "rx_fcs_errors" },
299 { "rx_align_errors" },
300 { "rx_xon_pause_rcvd" },
301 { "rx_xoff_pause_rcvd" },
302 { "rx_mac_ctrl_rcvd" },
303 { "rx_xoff_entered" },
304 { "rx_frame_too_long_errors" },
305 { "rx_jabbers" },
306 { "rx_undersize_packets" },
307 { "rx_in_length_errors" },
308 { "rx_out_length_errors" },
309 { "rx_64_or_less_octet_packets" },
310 { "rx_65_to_127_octet_packets" },
311 { "rx_128_to_255_octet_packets" },
312 { "rx_256_to_511_octet_packets" },
313 { "rx_512_to_1023_octet_packets" },
314 { "rx_1024_to_1522_octet_packets" },
315 { "rx_1523_to_2047_octet_packets" },
316 { "rx_2048_to_4095_octet_packets" },
317 { "rx_4096_to_8191_octet_packets" },
318 { "rx_8192_to_9022_octet_packets" },
319
320 { "tx_octets" },
321 { "tx_collisions" },
322
323 { "tx_xon_sent" },
324 { "tx_xoff_sent" },
325 { "tx_flow_control" },
326 { "tx_mac_errors" },
327 { "tx_single_collisions" },
328 { "tx_mult_collisions" },
329 { "tx_deferred" },
330 { "tx_excessive_collisions" },
331 { "tx_late_collisions" },
332 { "tx_collide_2times" },
333 { "tx_collide_3times" },
334 { "tx_collide_4times" },
335 { "tx_collide_5times" },
336 { "tx_collide_6times" },
337 { "tx_collide_7times" },
338 { "tx_collide_8times" },
339 { "tx_collide_9times" },
340 { "tx_collide_10times" },
341 { "tx_collide_11times" },
342 { "tx_collide_12times" },
343 { "tx_collide_13times" },
344 { "tx_collide_14times" },
345 { "tx_collide_15times" },
346 { "tx_ucast_packets" },
347 { "tx_mcast_packets" },
348 { "tx_bcast_packets" },
349 { "tx_carrier_sense_errors" },
350 { "tx_discards" },
351 { "tx_errors" },
352
353 { "dma_writeq_full" },
354 { "dma_write_prioq_full" },
355 { "rxbds_empty" },
356 { "rx_discards" },
357 { "rx_errors" },
358 { "rx_threshold_hit" },
359
360 { "dma_readq_full" },
361 { "dma_read_prioq_full" },
362 { "tx_comp_queue_full" },
363
364 { "ring_set_send_prod_index" },
365 { "ring_status_update" },
366 { "nic_irqs" },
367 { "nic_avoided_irqs" },
368 { "nic_tx_threshold_hit" }
369};
370
371static const struct {
372 const char string[ETH_GSTRING_LEN];
373} ethtool_test_keys[TG3_NUM_TEST] = {
374 { "nvram test (online) " },
375 { "link test (online) " },
376 { "register test (offline)" },
377 { "memory test (offline)" },
378 { "loopback test (offline)" },
379 { "interrupt test (offline)" },
380};
381
382static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
383{
384 writel(val, tp->regs + off);
385}
386
387static u32 tg3_read32(struct tg3 *tp, u32 off)
388{
389 return readl(tp->regs + off);
390}
391
392static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
393{
394 writel(val, tp->aperegs + off);
395}
396
397static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
398{
399 return readl(tp->aperegs + off);
400}
401
402static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
403{
404 unsigned long flags;
405
406 spin_lock_irqsave(&tp->indirect_lock, flags);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
408 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
409 spin_unlock_irqrestore(&tp->indirect_lock, flags);
410}
411
412static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
413{
414 writel(val, tp->regs + off);
415 readl(tp->regs + off);
416}
417
418static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
419{
420 unsigned long flags;
421 u32 val;
422
423 spin_lock_irqsave(&tp->indirect_lock, flags);
424 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
425 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
426 spin_unlock_irqrestore(&tp->indirect_lock, flags);
427 return val;
428}
429
430static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
431{
432 unsigned long flags;
433
434 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
435 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
436 TG3_64BIT_REG_LOW, val);
437 return;
438 }
439 if (off == TG3_RX_STD_PROD_IDX_REG) {
440 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
441 TG3_64BIT_REG_LOW, val);
442 return;
443 }
444
445 spin_lock_irqsave(&tp->indirect_lock, flags);
446 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
447 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
448 spin_unlock_irqrestore(&tp->indirect_lock, flags);
449
450 /* In indirect mode when disabling interrupts, we also need
451 * to clear the interrupt bit in the GRC local ctrl register.
452 */
453 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
454 (val == 0x1)) {
455 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
456 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
457 }
458}
459
460static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
461{
462 unsigned long flags;
463 u32 val;
464
465 spin_lock_irqsave(&tp->indirect_lock, flags);
466 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
467 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
468 spin_unlock_irqrestore(&tp->indirect_lock, flags);
469 return val;
470}
471
472/* usec_wait specifies the wait time in usec when writing to certain registers
473 * where it is unsafe to read back the register without some delay.
474 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
475 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
476 */
477static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
478{
479 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
480 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
481 /* Non-posted methods */
482 tp->write32(tp, off, val);
483 else {
484 /* Posted method */
485 tg3_write32(tp, off, val);
486 if (usec_wait)
487 udelay(usec_wait);
488 tp->read32(tp, off);
489 }
490 /* Wait again after the read for the posted method to guarantee that
491 * the wait time is met.
492 */
493 if (usec_wait)
494 udelay(usec_wait);
495}
496
497static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
498{
499 tp->write32_mbox(tp, off, val);
500 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
501 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
502 tp->read32_mbox(tp, off);
503}
504
505static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
506{
507 void __iomem *mbox = tp->regs + off;
508 writel(val, mbox);
509 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
510 writel(val, mbox);
511 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
512 readl(mbox);
513}
514
515static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
516{
517 return readl(tp->regs + off + GRCMBOX_BASE);
518}
519
520static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
521{
522 writel(val, tp->regs + off + GRCMBOX_BASE);
523}
524
525#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
526#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
527#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
528#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
529#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
530
531#define tw32(reg, val) tp->write32(tp, reg, val)
532#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
533#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
534#define tr32(reg) tp->read32(tp, reg)
535
536static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
537{
538 unsigned long flags;
539
540 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
541 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
542 return;
543
544 spin_lock_irqsave(&tp->indirect_lock, flags);
545 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
547 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
548
549 /* Always leave this as zero. */
550 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
551 } else {
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
553 tw32_f(TG3PCI_MEM_WIN_DATA, val);
554
555 /* Always leave this as zero. */
556 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
557 }
558 spin_unlock_irqrestore(&tp->indirect_lock, flags);
559}
560
561static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
562{
563 unsigned long flags;
564
565 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
566 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
567 *val = 0;
568 return;
569 }
570
571 spin_lock_irqsave(&tp->indirect_lock, flags);
572 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
573 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
574 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
575
576 /* Always leave this as zero. */
577 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
578 } else {
579 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
580 *val = tr32(TG3PCI_MEM_WIN_DATA);
581
582 /* Always leave this as zero. */
583 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
584 }
585 spin_unlock_irqrestore(&tp->indirect_lock, flags);
586}
587
588static void tg3_ape_lock_init(struct tg3 *tp)
589{
590 int i;
591 u32 regbase;
592
593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
594 regbase = TG3_APE_LOCK_GRANT;
595 else
596 regbase = TG3_APE_PER_LOCK_GRANT;
597
598 /* Make sure the driver hasn't any stale locks. */
599 for (i = 0; i < 8; i++)
600 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
601}
602
603static int tg3_ape_lock(struct tg3 *tp, int locknum)
604{
605 int i, off;
606 int ret = 0;
607 u32 status, req, gnt;
608
609 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
610 return 0;
611
612 switch (locknum) {
613 case TG3_APE_LOCK_GRC:
614 case TG3_APE_LOCK_MEM:
615 break;
616 default:
617 return -EINVAL;
618 }
619
620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
621 req = TG3_APE_LOCK_REQ;
622 gnt = TG3_APE_LOCK_GRANT;
623 } else {
624 req = TG3_APE_PER_LOCK_REQ;
625 gnt = TG3_APE_PER_LOCK_GRANT;
626 }
627
628 off = 4 * locknum;
629
630 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
631
632 /* Wait for up to 1 millisecond to acquire lock. */
633 for (i = 0; i < 100; i++) {
634 status = tg3_ape_read32(tp, gnt + off);
635 if (status == APE_LOCK_GRANT_DRIVER)
636 break;
637 udelay(10);
638 }
639
640 if (status != APE_LOCK_GRANT_DRIVER) {
641 /* Revoke the lock request. */
642 tg3_ape_write32(tp, gnt + off,
643 APE_LOCK_GRANT_DRIVER);
644
645 ret = -EBUSY;
646 }
647
648 return ret;
649}
650
651static void tg3_ape_unlock(struct tg3 *tp, int locknum)
652{
653 u32 gnt;
654
655 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
656 return;
657
658 switch (locknum) {
659 case TG3_APE_LOCK_GRC:
660 case TG3_APE_LOCK_MEM:
661 break;
662 default:
663 return;
664 }
665
666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
667 gnt = TG3_APE_LOCK_GRANT;
668 else
669 gnt = TG3_APE_PER_LOCK_GRANT;
670
671 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
672}
673
674static void tg3_disable_ints(struct tg3 *tp)
675{
676 int i;
677
678 tw32(TG3PCI_MISC_HOST_CTRL,
679 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
680 for (i = 0; i < tp->irq_max; i++)
681 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
682}
683
684static void tg3_enable_ints(struct tg3 *tp)
685{
686 int i;
687
688 tp->irq_sync = 0;
689 wmb();
690
691 tw32(TG3PCI_MISC_HOST_CTRL,
692 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
693
694 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
695 for (i = 0; i < tp->irq_cnt; i++) {
696 struct tg3_napi *tnapi = &tp->napi[i];
697
698 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
699 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
700 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
701
702 tp->coal_now |= tnapi->coal_now;
703 }
704
705 /* Force an initial interrupt */
706 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
707 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
708 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
709 else
710 tw32(HOSTCC_MODE, tp->coal_now);
711
712 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
713}
714
715static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
716{
717 struct tg3 *tp = tnapi->tp;
718 struct tg3_hw_status *sblk = tnapi->hw_status;
719 unsigned int work_exists = 0;
720
721 /* check for phy events */
722 if (!(tp->tg3_flags &
723 (TG3_FLAG_USE_LINKCHG_REG |
724 TG3_FLAG_POLL_SERDES))) {
725 if (sblk->status & SD_STATUS_LINK_CHG)
726 work_exists = 1;
727 }
728 /* check for RX/TX work to do */
729 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
730 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
731 work_exists = 1;
732
733 return work_exists;
734}
735
736/* tg3_int_reenable
737 * similar to tg3_enable_ints, but it accurately determines whether there
738 * is new work pending and can return without flushing the PIO write
739 * which reenables interrupts
740 */
741static void tg3_int_reenable(struct tg3_napi *tnapi)
742{
743 struct tg3 *tp = tnapi->tp;
744
745 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
746 mmiowb();
747
748 /* When doing tagged status, this work check is unnecessary.
749 * The last_tag we write above tells the chip which piece of
750 * work we've completed.
751 */
752 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
753 tg3_has_work(tnapi))
754 tw32(HOSTCC_MODE, tp->coalesce_mode |
755 HOSTCC_MODE_ENABLE | tnapi->coal_now);
756}
757
758static void tg3_napi_disable(struct tg3 *tp)
759{
760 int i;
761
762 for (i = tp->irq_cnt - 1; i >= 0; i--)
763 napi_disable(&tp->napi[i].napi);
764}
765
766static void tg3_napi_enable(struct tg3 *tp)
767{
768 int i;
769
770 for (i = 0; i < tp->irq_cnt; i++)
771 napi_enable(&tp->napi[i].napi);
772}
773
774static inline void tg3_netif_stop(struct tg3 *tp)
775{
776 tp->dev->trans_start = jiffies; /* prevent tx timeout */
777 tg3_napi_disable(tp);
778 netif_tx_disable(tp->dev);
779}
780
781static inline void tg3_netif_start(struct tg3 *tp)
782{
783 /* NOTE: unconditional netif_tx_wake_all_queues is only
784 * appropriate so long as all callers are assured to
785 * have free tx slots (such as after tg3_init_hw)
786 */
787 netif_tx_wake_all_queues(tp->dev);
788
789 tg3_napi_enable(tp);
790 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
791 tg3_enable_ints(tp);
792}
793
794static void tg3_switch_clocks(struct tg3 *tp)
795{
796 u32 clock_ctrl;
797 u32 orig_clock_ctrl;
798
799 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
800 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
801 return;
802
803 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
804
805 orig_clock_ctrl = clock_ctrl;
806 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
807 CLOCK_CTRL_CLKRUN_OENABLE |
808 0x1f);
809 tp->pci_clock_ctrl = clock_ctrl;
810
811 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
812 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
813 tw32_wait_f(TG3PCI_CLOCK_CTRL,
814 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
815 }
816 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
817 tw32_wait_f(TG3PCI_CLOCK_CTRL,
818 clock_ctrl |
819 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
820 40);
821 tw32_wait_f(TG3PCI_CLOCK_CTRL,
822 clock_ctrl | (CLOCK_CTRL_ALTCLK),
823 40);
824 }
825 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
826}
827
828#define PHY_BUSY_LOOPS 5000
829
830static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
831{
832 u32 frame_val;
833 unsigned int loops;
834 int ret;
835
836 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
837 tw32_f(MAC_MI_MODE,
838 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
839 udelay(80);
840 }
841
842 *val = 0x0;
843
844 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
845 MI_COM_PHY_ADDR_MASK);
846 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
847 MI_COM_REG_ADDR_MASK);
848 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
849
850 tw32_f(MAC_MI_COM, frame_val);
851
852 loops = PHY_BUSY_LOOPS;
853 while (loops != 0) {
854 udelay(10);
855 frame_val = tr32(MAC_MI_COM);
856
857 if ((frame_val & MI_COM_BUSY) == 0) {
858 udelay(5);
859 frame_val = tr32(MAC_MI_COM);
860 break;
861 }
862 loops -= 1;
863 }
864
865 ret = -EBUSY;
866 if (loops != 0) {
867 *val = frame_val & MI_COM_DATA_MASK;
868 ret = 0;
869 }
870
871 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
872 tw32_f(MAC_MI_MODE, tp->mi_mode);
873 udelay(80);
874 }
875
876 return ret;
877}
878
879static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
880{
881 u32 frame_val;
882 unsigned int loops;
883 int ret;
884
885 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
886 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
887 return 0;
888
889 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
890 tw32_f(MAC_MI_MODE,
891 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
892 udelay(80);
893 }
894
895 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
896 MI_COM_PHY_ADDR_MASK);
897 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
898 MI_COM_REG_ADDR_MASK);
899 frame_val |= (val & MI_COM_DATA_MASK);
900 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
901
902 tw32_f(MAC_MI_COM, frame_val);
903
904 loops = PHY_BUSY_LOOPS;
905 while (loops != 0) {
906 udelay(10);
907 frame_val = tr32(MAC_MI_COM);
908 if ((frame_val & MI_COM_BUSY) == 0) {
909 udelay(5);
910 frame_val = tr32(MAC_MI_COM);
911 break;
912 }
913 loops -= 1;
914 }
915
916 ret = -EBUSY;
917 if (loops != 0)
918 ret = 0;
919
920 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
921 tw32_f(MAC_MI_MODE, tp->mi_mode);
922 udelay(80);
923 }
924
925 return ret;
926}
927
928static int tg3_bmcr_reset(struct tg3 *tp)
929{
930 u32 phy_control;
931 int limit, err;
932
933 /* OK, reset it, and poll the BMCR_RESET bit until it
934 * clears or we time out.
935 */
936 phy_control = BMCR_RESET;
937 err = tg3_writephy(tp, MII_BMCR, phy_control);
938 if (err != 0)
939 return -EBUSY;
940
941 limit = 5000;
942 while (limit--) {
943 err = tg3_readphy(tp, MII_BMCR, &phy_control);
944 if (err != 0)
945 return -EBUSY;
946
947 if ((phy_control & BMCR_RESET) == 0) {
948 udelay(40);
949 break;
950 }
951 udelay(10);
952 }
953 if (limit < 0)
954 return -EBUSY;
955
956 return 0;
957}
958
959static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
960{
961 struct tg3 *tp = bp->priv;
962 u32 val;
963
964 spin_lock_bh(&tp->lock);
965
966 if (tg3_readphy(tp, reg, &val))
967 val = -EIO;
968
969 spin_unlock_bh(&tp->lock);
970
971 return val;
972}
973
974static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
975{
976 struct tg3 *tp = bp->priv;
977 u32 ret = 0;
978
979 spin_lock_bh(&tp->lock);
980
981 if (tg3_writephy(tp, reg, val))
982 ret = -EIO;
983
984 spin_unlock_bh(&tp->lock);
985
986 return ret;
987}
988
989static int tg3_mdio_reset(struct mii_bus *bp)
990{
991 return 0;
992}
993
994static void tg3_mdio_config_5785(struct tg3 *tp)
995{
996 u32 val;
997 struct phy_device *phydev;
998
999 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1000 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1001 case PHY_ID_BCM50610:
1002 case PHY_ID_BCM50610M:
1003 val = MAC_PHYCFG2_50610_LED_MODES;
1004 break;
1005 case PHY_ID_BCMAC131:
1006 val = MAC_PHYCFG2_AC131_LED_MODES;
1007 break;
1008 case PHY_ID_RTL8211C:
1009 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1010 break;
1011 case PHY_ID_RTL8201E:
1012 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1013 break;
1014 default:
1015 return;
1016 }
1017
1018 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1019 tw32(MAC_PHYCFG2, val);
1020
1021 val = tr32(MAC_PHYCFG1);
1022 val &= ~(MAC_PHYCFG1_RGMII_INT |
1023 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1024 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1025 tw32(MAC_PHYCFG1, val);
1026
1027 return;
1028 }
1029
1030 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1031 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1032 MAC_PHYCFG2_FMODE_MASK_MASK |
1033 MAC_PHYCFG2_GMODE_MASK_MASK |
1034 MAC_PHYCFG2_ACT_MASK_MASK |
1035 MAC_PHYCFG2_QUAL_MASK_MASK |
1036 MAC_PHYCFG2_INBAND_ENABLE;
1037
1038 tw32(MAC_PHYCFG2, val);
1039
1040 val = tr32(MAC_PHYCFG1);
1041 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1042 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1043 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1044 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1045 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1046 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1047 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1048 }
1049 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1050 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1051 tw32(MAC_PHYCFG1, val);
1052
1053 val = tr32(MAC_EXT_RGMII_MODE);
1054 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1055 MAC_RGMII_MODE_RX_QUALITY |
1056 MAC_RGMII_MODE_RX_ACTIVITY |
1057 MAC_RGMII_MODE_RX_ENG_DET |
1058 MAC_RGMII_MODE_TX_ENABLE |
1059 MAC_RGMII_MODE_TX_LOWPWR |
1060 MAC_RGMII_MODE_TX_RESET);
1061 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1062 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1063 val |= MAC_RGMII_MODE_RX_INT_B |
1064 MAC_RGMII_MODE_RX_QUALITY |
1065 MAC_RGMII_MODE_RX_ACTIVITY |
1066 MAC_RGMII_MODE_RX_ENG_DET;
1067 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1068 val |= MAC_RGMII_MODE_TX_ENABLE |
1069 MAC_RGMII_MODE_TX_LOWPWR |
1070 MAC_RGMII_MODE_TX_RESET;
1071 }
1072 tw32(MAC_EXT_RGMII_MODE, val);
1073}
1074
1075static void tg3_mdio_start(struct tg3 *tp)
1076{
1077 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1078 tw32_f(MAC_MI_MODE, tp->mi_mode);
1079 udelay(80);
1080
1081 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1082 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1083 tg3_mdio_config_5785(tp);
1084}
1085
1086static int tg3_mdio_init(struct tg3 *tp)
1087{
1088 int i;
1089 u32 reg;
1090 struct phy_device *phydev;
1091
1092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1094 u32 is_serdes;
1095
1096 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1097
1098 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1099 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1100 else
1101 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1102 TG3_CPMU_PHY_STRAP_IS_SERDES;
1103 if (is_serdes)
1104 tp->phy_addr += 7;
1105 } else
1106 tp->phy_addr = TG3_PHY_MII_ADDR;
1107
1108 tg3_mdio_start(tp);
1109
1110 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1111 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1112 return 0;
1113
1114 tp->mdio_bus = mdiobus_alloc();
1115 if (tp->mdio_bus == NULL)
1116 return -ENOMEM;
1117
1118 tp->mdio_bus->name = "tg3 mdio bus";
1119 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1120 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1121 tp->mdio_bus->priv = tp;
1122 tp->mdio_bus->parent = &tp->pdev->dev;
1123 tp->mdio_bus->read = &tg3_mdio_read;
1124 tp->mdio_bus->write = &tg3_mdio_write;
1125 tp->mdio_bus->reset = &tg3_mdio_reset;
1126 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1127 tp->mdio_bus->irq = &tp->mdio_irq[0];
1128
1129 for (i = 0; i < PHY_MAX_ADDR; i++)
1130 tp->mdio_bus->irq[i] = PHY_POLL;
1131
1132 /* The bus registration will look for all the PHYs on the mdio bus.
1133 * Unfortunately, it does not ensure the PHY is powered up before
1134 * accessing the PHY ID registers. A chip reset is the
1135 * quickest way to bring the device back to an operational state..
1136 */
1137 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1138 tg3_bmcr_reset(tp);
1139
1140 i = mdiobus_register(tp->mdio_bus);
1141 if (i) {
1142 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1143 mdiobus_free(tp->mdio_bus);
1144 return i;
1145 }
1146
1147 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1148
1149 if (!phydev || !phydev->drv) {
1150 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1151 mdiobus_unregister(tp->mdio_bus);
1152 mdiobus_free(tp->mdio_bus);
1153 return -ENODEV;
1154 }
1155
1156 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1157 case PHY_ID_BCM57780:
1158 phydev->interface = PHY_INTERFACE_MODE_GMII;
1159 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1160 break;
1161 case PHY_ID_BCM50610:
1162 case PHY_ID_BCM50610M:
1163 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1164 PHY_BRCM_RX_REFCLK_UNUSED |
1165 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1166 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1167 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1168 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1169 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1170 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1171 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1172 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1173 /* fallthru */
1174 case PHY_ID_RTL8211C:
1175 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1176 break;
1177 case PHY_ID_RTL8201E:
1178 case PHY_ID_BCMAC131:
1179 phydev->interface = PHY_INTERFACE_MODE_MII;
1180 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1181 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1182 break;
1183 }
1184
1185 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1186
1187 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1188 tg3_mdio_config_5785(tp);
1189
1190 return 0;
1191}
1192
1193static void tg3_mdio_fini(struct tg3 *tp)
1194{
1195 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1196 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1197 mdiobus_unregister(tp->mdio_bus);
1198 mdiobus_free(tp->mdio_bus);
1199 }
1200}
1201
1202/* tp->lock is held. */
1203static inline void tg3_generate_fw_event(struct tg3 *tp)
1204{
1205 u32 val;
1206
1207 val = tr32(GRC_RX_CPU_EVENT);
1208 val |= GRC_RX_CPU_DRIVER_EVENT;
1209 tw32_f(GRC_RX_CPU_EVENT, val);
1210
1211 tp->last_event_jiffies = jiffies;
1212}
1213
1214#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1215
1216/* tp->lock is held. */
1217static void tg3_wait_for_event_ack(struct tg3 *tp)
1218{
1219 int i;
1220 unsigned int delay_cnt;
1221 long time_remain;
1222
1223 /* If enough time has passed, no wait is necessary. */
1224 time_remain = (long)(tp->last_event_jiffies + 1 +
1225 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1226 (long)jiffies;
1227 if (time_remain < 0)
1228 return;
1229
1230 /* Check if we can shorten the wait time. */
1231 delay_cnt = jiffies_to_usecs(time_remain);
1232 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1233 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1234 delay_cnt = (delay_cnt >> 3) + 1;
1235
1236 for (i = 0; i < delay_cnt; i++) {
1237 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1238 break;
1239 udelay(8);
1240 }
1241}
1242
1243/* tp->lock is held. */
1244static void tg3_ump_link_report(struct tg3 *tp)
1245{
1246 u32 reg;
1247 u32 val;
1248
1249 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1250 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1251 return;
1252
1253 tg3_wait_for_event_ack(tp);
1254
1255 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1256
1257 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1258
1259 val = 0;
1260 if (!tg3_readphy(tp, MII_BMCR, &reg))
1261 val = reg << 16;
1262 if (!tg3_readphy(tp, MII_BMSR, &reg))
1263 val |= (reg & 0xffff);
1264 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1265
1266 val = 0;
1267 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1268 val = reg << 16;
1269 if (!tg3_readphy(tp, MII_LPA, &reg))
1270 val |= (reg & 0xffff);
1271 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1272
1273 val = 0;
1274 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1275 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1276 val = reg << 16;
1277 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1278 val |= (reg & 0xffff);
1279 }
1280 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1281
1282 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1283 val = reg << 16;
1284 else
1285 val = 0;
1286 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1287
1288 tg3_generate_fw_event(tp);
1289}
1290
1291static void tg3_link_report(struct tg3 *tp)
1292{
1293 if (!netif_carrier_ok(tp->dev)) {
1294 netif_info(tp, link, tp->dev, "Link is down\n");
1295 tg3_ump_link_report(tp);
1296 } else if (netif_msg_link(tp)) {
1297 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1298 (tp->link_config.active_speed == SPEED_1000 ?
1299 1000 :
1300 (tp->link_config.active_speed == SPEED_100 ?
1301 100 : 10)),
1302 (tp->link_config.active_duplex == DUPLEX_FULL ?
1303 "full" : "half"));
1304
1305 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1306 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1307 "on" : "off",
1308 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1309 "on" : "off");
1310 tg3_ump_link_report(tp);
1311 }
1312}
1313
1314static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1315{
1316 u16 miireg;
1317
1318 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1319 miireg = ADVERTISE_PAUSE_CAP;
1320 else if (flow_ctrl & FLOW_CTRL_TX)
1321 miireg = ADVERTISE_PAUSE_ASYM;
1322 else if (flow_ctrl & FLOW_CTRL_RX)
1323 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1324 else
1325 miireg = 0;
1326
1327 return miireg;
1328}
1329
1330static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1331{
1332 u16 miireg;
1333
1334 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1335 miireg = ADVERTISE_1000XPAUSE;
1336 else if (flow_ctrl & FLOW_CTRL_TX)
1337 miireg = ADVERTISE_1000XPSE_ASYM;
1338 else if (flow_ctrl & FLOW_CTRL_RX)
1339 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1340 else
1341 miireg = 0;
1342
1343 return miireg;
1344}
1345
1346static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1347{
1348 u8 cap = 0;
1349
1350 if (lcladv & ADVERTISE_1000XPAUSE) {
1351 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1352 if (rmtadv & LPA_1000XPAUSE)
1353 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1354 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1355 cap = FLOW_CTRL_RX;
1356 } else {
1357 if (rmtadv & LPA_1000XPAUSE)
1358 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1359 }
1360 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1362 cap = FLOW_CTRL_TX;
1363 }
1364
1365 return cap;
1366}
1367
1368static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1369{
1370 u8 autoneg;
1371 u8 flowctrl = 0;
1372 u32 old_rx_mode = tp->rx_mode;
1373 u32 old_tx_mode = tp->tx_mode;
1374
1375 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1376 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1377 else
1378 autoneg = tp->link_config.autoneg;
1379
1380 if (autoneg == AUTONEG_ENABLE &&
1381 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1382 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1383 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1384 else
1385 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1386 } else
1387 flowctrl = tp->link_config.flowctrl;
1388
1389 tp->link_config.active_flowctrl = flowctrl;
1390
1391 if (flowctrl & FLOW_CTRL_RX)
1392 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1393 else
1394 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1395
1396 if (old_rx_mode != tp->rx_mode)
1397 tw32_f(MAC_RX_MODE, tp->rx_mode);
1398
1399 if (flowctrl & FLOW_CTRL_TX)
1400 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1401 else
1402 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1403
1404 if (old_tx_mode != tp->tx_mode)
1405 tw32_f(MAC_TX_MODE, tp->tx_mode);
1406}
1407
1408static void tg3_adjust_link(struct net_device *dev)
1409{
1410 u8 oldflowctrl, linkmesg = 0;
1411 u32 mac_mode, lcl_adv, rmt_adv;
1412 struct tg3 *tp = netdev_priv(dev);
1413 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1414
1415 spin_lock_bh(&tp->lock);
1416
1417 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1418 MAC_MODE_HALF_DUPLEX);
1419
1420 oldflowctrl = tp->link_config.active_flowctrl;
1421
1422 if (phydev->link) {
1423 lcl_adv = 0;
1424 rmt_adv = 0;
1425
1426 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1427 mac_mode |= MAC_MODE_PORT_MODE_MII;
1428 else if (phydev->speed == SPEED_1000 ||
1429 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1430 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1431 else
1432 mac_mode |= MAC_MODE_PORT_MODE_MII;
1433
1434 if (phydev->duplex == DUPLEX_HALF)
1435 mac_mode |= MAC_MODE_HALF_DUPLEX;
1436 else {
1437 lcl_adv = tg3_advert_flowctrl_1000T(
1438 tp->link_config.flowctrl);
1439
1440 if (phydev->pause)
1441 rmt_adv = LPA_PAUSE_CAP;
1442 if (phydev->asym_pause)
1443 rmt_adv |= LPA_PAUSE_ASYM;
1444 }
1445
1446 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1447 } else
1448 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1449
1450 if (mac_mode != tp->mac_mode) {
1451 tp->mac_mode = mac_mode;
1452 tw32_f(MAC_MODE, tp->mac_mode);
1453 udelay(40);
1454 }
1455
1456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1457 if (phydev->speed == SPEED_10)
1458 tw32(MAC_MI_STAT,
1459 MAC_MI_STAT_10MBPS_MODE |
1460 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1461 else
1462 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1463 }
1464
1465 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1466 tw32(MAC_TX_LENGTHS,
1467 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1468 (6 << TX_LENGTHS_IPG_SHIFT) |
1469 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1470 else
1471 tw32(MAC_TX_LENGTHS,
1472 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1473 (6 << TX_LENGTHS_IPG_SHIFT) |
1474 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1475
1476 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1477 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1478 phydev->speed != tp->link_config.active_speed ||
1479 phydev->duplex != tp->link_config.active_duplex ||
1480 oldflowctrl != tp->link_config.active_flowctrl)
1481 linkmesg = 1;
1482
1483 tp->link_config.active_speed = phydev->speed;
1484 tp->link_config.active_duplex = phydev->duplex;
1485
1486 spin_unlock_bh(&tp->lock);
1487
1488 if (linkmesg)
1489 tg3_link_report(tp);
1490}
1491
1492static int tg3_phy_init(struct tg3 *tp)
1493{
1494 struct phy_device *phydev;
1495
1496 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1497 return 0;
1498
1499 /* Bring the PHY back to a known state. */
1500 tg3_bmcr_reset(tp);
1501
1502 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503
1504 /* Attach the MAC to the PHY. */
1505 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1506 phydev->dev_flags, phydev->interface);
1507 if (IS_ERR(phydev)) {
1508 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1509 return PTR_ERR(phydev);
1510 }
1511
1512 /* Mask with MAC supported features. */
1513 switch (phydev->interface) {
1514 case PHY_INTERFACE_MODE_GMII:
1515 case PHY_INTERFACE_MODE_RGMII:
1516 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1517 phydev->supported &= (PHY_GBIT_FEATURES |
1518 SUPPORTED_Pause |
1519 SUPPORTED_Asym_Pause);
1520 break;
1521 }
1522 /* fallthru */
1523 case PHY_INTERFACE_MODE_MII:
1524 phydev->supported &= (PHY_BASIC_FEATURES |
1525 SUPPORTED_Pause |
1526 SUPPORTED_Asym_Pause);
1527 break;
1528 default:
1529 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1530 return -EINVAL;
1531 }
1532
1533 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1534
1535 phydev->advertising = phydev->supported;
1536
1537 return 0;
1538}
1539
1540static void tg3_phy_start(struct tg3 *tp)
1541{
1542 struct phy_device *phydev;
1543
1544 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1545 return;
1546
1547 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1548
1549 if (tp->link_config.phy_is_low_power) {
1550 tp->link_config.phy_is_low_power = 0;
1551 phydev->speed = tp->link_config.orig_speed;
1552 phydev->duplex = tp->link_config.orig_duplex;
1553 phydev->autoneg = tp->link_config.orig_autoneg;
1554 phydev->advertising = tp->link_config.orig_advertising;
1555 }
1556
1557 phy_start(phydev);
1558
1559 phy_start_aneg(phydev);
1560}
1561
1562static void tg3_phy_stop(struct tg3 *tp)
1563{
1564 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1565 return;
1566
1567 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1568}
1569
1570static void tg3_phy_fini(struct tg3 *tp)
1571{
1572 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1573 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1574 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1575 }
1576}
1577
1578static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1579{
1580 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1581 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1582}
1583
1584static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1585{
1586 u32 phytest;
1587
1588 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1589 u32 phy;
1590
1591 tg3_writephy(tp, MII_TG3_FET_TEST,
1592 phytest | MII_TG3_FET_SHADOW_EN);
1593 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1594 if (enable)
1595 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1596 else
1597 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1598 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1599 }
1600 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1601 }
1602}
1603
1604static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1605{
1606 u32 reg;
1607
1608 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1609 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1610 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1611 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1612 return;
1613
1614 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1615 tg3_phy_fet_toggle_apd(tp, enable);
1616 return;
1617 }
1618
1619 reg = MII_TG3_MISC_SHDW_WREN |
1620 MII_TG3_MISC_SHDW_SCR5_SEL |
1621 MII_TG3_MISC_SHDW_SCR5_LPED |
1622 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1623 MII_TG3_MISC_SHDW_SCR5_SDTL |
1624 MII_TG3_MISC_SHDW_SCR5_C125OE;
1625 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1626 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1627
1628 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1629
1630
1631 reg = MII_TG3_MISC_SHDW_WREN |
1632 MII_TG3_MISC_SHDW_APD_SEL |
1633 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1634 if (enable)
1635 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1636
1637 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1638}
1639
1640static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1641{
1642 u32 phy;
1643
1644 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1645 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1646 return;
1647
1648 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1649 u32 ephy;
1650
1651 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1652 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1653
1654 tg3_writephy(tp, MII_TG3_FET_TEST,
1655 ephy | MII_TG3_FET_SHADOW_EN);
1656 if (!tg3_readphy(tp, reg, &phy)) {
1657 if (enable)
1658 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1659 else
1660 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1661 tg3_writephy(tp, reg, phy);
1662 }
1663 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1664 }
1665 } else {
1666 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1667 MII_TG3_AUXCTL_SHDWSEL_MISC;
1668 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1669 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1670 if (enable)
1671 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1672 else
1673 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1674 phy |= MII_TG3_AUXCTL_MISC_WREN;
1675 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1676 }
1677 }
1678}
1679
1680static void tg3_phy_set_wirespeed(struct tg3 *tp)
1681{
1682 u32 val;
1683
1684 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1685 return;
1686
1687 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1688 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1689 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1690 (val | (1 << 15) | (1 << 4)));
1691}
1692
1693static void tg3_phy_apply_otp(struct tg3 *tp)
1694{
1695 u32 otp, phy;
1696
1697 if (!tp->phy_otp)
1698 return;
1699
1700 otp = tp->phy_otp;
1701
1702 /* Enable SM_DSP clock and tx 6dB coding. */
1703 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1704 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1705 MII_TG3_AUXCTL_ACTL_TX_6DB;
1706 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1707
1708 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1709 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1710 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1711
1712 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1713 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1714 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1715
1716 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1717 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1718 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1719
1720 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1721 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1722
1723 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1724 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1725
1726 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1727 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1728 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1729
1730 /* Turn off SM_DSP clock. */
1731 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1732 MII_TG3_AUXCTL_ACTL_TX_6DB;
1733 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1734}
1735
1736static int tg3_wait_macro_done(struct tg3 *tp)
1737{
1738 int limit = 100;
1739
1740 while (limit--) {
1741 u32 tmp32;
1742
1743 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1744 if ((tmp32 & 0x1000) == 0)
1745 break;
1746 }
1747 }
1748 if (limit < 0)
1749 return -EBUSY;
1750
1751 return 0;
1752}
1753
1754static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1755{
1756 static const u32 test_pat[4][6] = {
1757 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1758 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1759 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1760 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1761 };
1762 int chan;
1763
1764 for (chan = 0; chan < 4; chan++) {
1765 int i;
1766
1767 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1768 (chan * 0x2000) | 0x0200);
1769 tg3_writephy(tp, 0x16, 0x0002);
1770
1771 for (i = 0; i < 6; i++)
1772 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1773 test_pat[chan][i]);
1774
1775 tg3_writephy(tp, 0x16, 0x0202);
1776 if (tg3_wait_macro_done(tp)) {
1777 *resetp = 1;
1778 return -EBUSY;
1779 }
1780
1781 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1782 (chan * 0x2000) | 0x0200);
1783 tg3_writephy(tp, 0x16, 0x0082);
1784 if (tg3_wait_macro_done(tp)) {
1785 *resetp = 1;
1786 return -EBUSY;
1787 }
1788
1789 tg3_writephy(tp, 0x16, 0x0802);
1790 if (tg3_wait_macro_done(tp)) {
1791 *resetp = 1;
1792 return -EBUSY;
1793 }
1794
1795 for (i = 0; i < 6; i += 2) {
1796 u32 low, high;
1797
1798 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1799 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1800 tg3_wait_macro_done(tp)) {
1801 *resetp = 1;
1802 return -EBUSY;
1803 }
1804 low &= 0x7fff;
1805 high &= 0x000f;
1806 if (low != test_pat[chan][i] ||
1807 high != test_pat[chan][i+1]) {
1808 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1809 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1810 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1811
1812 return -EBUSY;
1813 }
1814 }
1815 }
1816
1817 return 0;
1818}
1819
1820static int tg3_phy_reset_chanpat(struct tg3 *tp)
1821{
1822 int chan;
1823
1824 for (chan = 0; chan < 4; chan++) {
1825 int i;
1826
1827 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1828 (chan * 0x2000) | 0x0200);
1829 tg3_writephy(tp, 0x16, 0x0002);
1830 for (i = 0; i < 6; i++)
1831 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1832 tg3_writephy(tp, 0x16, 0x0202);
1833 if (tg3_wait_macro_done(tp))
1834 return -EBUSY;
1835 }
1836
1837 return 0;
1838}
1839
1840static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1841{
1842 u32 reg32, phy9_orig;
1843 int retries, do_phy_reset, err;
1844
1845 retries = 10;
1846 do_phy_reset = 1;
1847 do {
1848 if (do_phy_reset) {
1849 err = tg3_bmcr_reset(tp);
1850 if (err)
1851 return err;
1852 do_phy_reset = 0;
1853 }
1854
1855 /* Disable transmitter and interrupt. */
1856 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1857 continue;
1858
1859 reg32 |= 0x3000;
1860 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1861
1862 /* Set full-duplex, 1000 mbps. */
1863 tg3_writephy(tp, MII_BMCR,
1864 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1865
1866 /* Set to master mode. */
1867 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1868 continue;
1869
1870 tg3_writephy(tp, MII_TG3_CTRL,
1871 (MII_TG3_CTRL_AS_MASTER |
1872 MII_TG3_CTRL_ENABLE_AS_MASTER));
1873
1874 /* Enable SM_DSP_CLOCK and 6dB. */
1875 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1876
1877 /* Block the PHY control access. */
1878 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1880
1881 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1882 if (!err)
1883 break;
1884 } while (--retries);
1885
1886 err = tg3_phy_reset_chanpat(tp);
1887 if (err)
1888 return err;
1889
1890 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1891 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1892
1893 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1894 tg3_writephy(tp, 0x16, 0x0000);
1895
1896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1898 /* Set Extended packet length bit for jumbo frames */
1899 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1900 } else {
1901 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902 }
1903
1904 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1905
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1907 reg32 &= ~0x3000;
1908 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1909 } else if (!err)
1910 err = -EBUSY;
1911
1912 return err;
1913}
1914
1915/* This will reset the tigon3 PHY if there is no valid
1916 * link unless the FORCE argument is non-zero.
1917 */
1918static int tg3_phy_reset(struct tg3 *tp)
1919{
1920 u32 cpmuctrl;
1921 u32 phy_status;
1922 int err;
1923
1924 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1925 u32 val;
1926
1927 val = tr32(GRC_MISC_CFG);
1928 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1929 udelay(40);
1930 }
1931 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1932 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1933 if (err != 0)
1934 return -EBUSY;
1935
1936 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1937 netif_carrier_off(tp->dev);
1938 tg3_link_report(tp);
1939 }
1940
1941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1944 err = tg3_phy_reset_5703_4_5(tp);
1945 if (err)
1946 return err;
1947 goto out;
1948 }
1949
1950 cpmuctrl = 0;
1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1952 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1953 cpmuctrl = tr32(TG3_CPMU_CTRL);
1954 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1955 tw32(TG3_CPMU_CTRL,
1956 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1957 }
1958
1959 err = tg3_bmcr_reset(tp);
1960 if (err)
1961 return err;
1962
1963 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1964 u32 phy;
1965
1966 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1967 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1968
1969 tw32(TG3_CPMU_CTRL, cpmuctrl);
1970 }
1971
1972 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1973 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1974 u32 val;
1975
1976 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1977 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1978 CPMU_LSPD_1000MB_MACCLK_12_5) {
1979 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1980 udelay(40);
1981 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1982 }
1983 }
1984
1985 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1987 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1988 return 0;
1989
1990 tg3_phy_apply_otp(tp);
1991
1992 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1993 tg3_phy_toggle_apd(tp, true);
1994 else
1995 tg3_phy_toggle_apd(tp, false);
1996
1997out:
1998 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1999 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2000 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2001 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
2002 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2003 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
2004 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2005 }
2006 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
2007 tg3_writephy(tp, 0x1c, 0x8d68);
2008 tg3_writephy(tp, 0x1c, 0x8d68);
2009 }
2010 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2011 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2012 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2013 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
2014 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2015 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
2016 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
2017 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
2018 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2019 } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2020 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2021 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2022 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2023 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2024 tg3_writephy(tp, MII_TG3_TEST1,
2025 MII_TG3_TEST1_TRIM_EN | 0x4);
2026 } else
2027 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2028 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2029 }
2030 /* Set Extended packet length bit (bit 14) on all chips that */
2031 /* support jumbo frames */
2032 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2033 /* Cannot do read-modify-write on 5401 */
2034 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2035 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2036 u32 phy_reg;
2037
2038 /* Set bit 14 with read-modify-write to preserve other bits */
2039 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2040 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2041 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2042 }
2043
2044 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2045 * jumbo frames transmission.
2046 */
2047 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2048 u32 phy_reg;
2049
2050 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2051 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2052 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2053 }
2054
2055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2056 /* adjust output voltage */
2057 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2058 }
2059
2060 tg3_phy_toggle_automdix(tp, 1);
2061 tg3_phy_set_wirespeed(tp);
2062 return 0;
2063}
2064
2065static void tg3_frob_aux_power(struct tg3 *tp)
2066{
2067 struct tg3 *tp_peer = tp;
2068
2069 /* The GPIOs do something completely different on 57765. */
2070 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2071 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2072 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2073 return;
2074
2075 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2076 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2077 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2078 struct net_device *dev_peer;
2079
2080 dev_peer = pci_get_drvdata(tp->pdev_peer);
2081 /* remove_one() may have been run on the peer. */
2082 if (!dev_peer)
2083 tp_peer = tp;
2084 else
2085 tp_peer = netdev_priv(dev_peer);
2086 }
2087
2088 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2089 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2090 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2091 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095 (GRC_LCLCTRL_GPIO_OE0 |
2096 GRC_LCLCTRL_GPIO_OE1 |
2097 GRC_LCLCTRL_GPIO_OE2 |
2098 GRC_LCLCTRL_GPIO_OUTPUT0 |
2099 GRC_LCLCTRL_GPIO_OUTPUT1),
2100 100);
2101 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2102 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2103 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2104 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2105 GRC_LCLCTRL_GPIO_OE1 |
2106 GRC_LCLCTRL_GPIO_OE2 |
2107 GRC_LCLCTRL_GPIO_OUTPUT0 |
2108 GRC_LCLCTRL_GPIO_OUTPUT1 |
2109 tp->grc_local_ctrl;
2110 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2111
2112 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2113 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2114
2115 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2116 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2117 } else {
2118 u32 no_gpio2;
2119 u32 grc_local_ctrl = 0;
2120
2121 if (tp_peer != tp &&
2122 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2123 return;
2124
2125 /* Workaround to prevent overdrawing Amps. */
2126 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2127 ASIC_REV_5714) {
2128 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2129 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2130 grc_local_ctrl, 100);
2131 }
2132
2133 /* On 5753 and variants, GPIO2 cannot be used. */
2134 no_gpio2 = tp->nic_sram_data_cfg &
2135 NIC_SRAM_DATA_CFG_NO_GPIO2;
2136
2137 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2138 GRC_LCLCTRL_GPIO_OE1 |
2139 GRC_LCLCTRL_GPIO_OE2 |
2140 GRC_LCLCTRL_GPIO_OUTPUT1 |
2141 GRC_LCLCTRL_GPIO_OUTPUT2;
2142 if (no_gpio2) {
2143 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2144 GRC_LCLCTRL_GPIO_OUTPUT2);
2145 }
2146 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2147 grc_local_ctrl, 100);
2148
2149 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2150
2151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152 grc_local_ctrl, 100);
2153
2154 if (!no_gpio2) {
2155 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2156 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2157 grc_local_ctrl, 100);
2158 }
2159 }
2160 } else {
2161 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2162 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2163 if (tp_peer != tp &&
2164 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2165 return;
2166
2167 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2168 (GRC_LCLCTRL_GPIO_OE1 |
2169 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2170
2171 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2172 GRC_LCLCTRL_GPIO_OE1, 100);
2173
2174 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2175 (GRC_LCLCTRL_GPIO_OE1 |
2176 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2177 }
2178 }
2179}
2180
2181static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2182{
2183 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2184 return 1;
2185 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2186 if (speed != SPEED_10)
2187 return 1;
2188 } else if (speed == SPEED_10)
2189 return 1;
2190
2191 return 0;
2192}
2193
2194static int tg3_setup_phy(struct tg3 *, int);
2195
2196#define RESET_KIND_SHUTDOWN 0
2197#define RESET_KIND_INIT 1
2198#define RESET_KIND_SUSPEND 2
2199
2200static void tg3_write_sig_post_reset(struct tg3 *, int);
2201static int tg3_halt_cpu(struct tg3 *, u32);
2202
2203static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2204{
2205 u32 val;
2206
2207 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2209 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2210 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2211
2212 sg_dig_ctrl |=
2213 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2214 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2215 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2216 }
2217 return;
2218 }
2219
2220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2221 tg3_bmcr_reset(tp);
2222 val = tr32(GRC_MISC_CFG);
2223 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2224 udelay(40);
2225 return;
2226 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2227 u32 phytest;
2228 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2229 u32 phy;
2230
2231 tg3_writephy(tp, MII_ADVERTISE, 0);
2232 tg3_writephy(tp, MII_BMCR,
2233 BMCR_ANENABLE | BMCR_ANRESTART);
2234
2235 tg3_writephy(tp, MII_TG3_FET_TEST,
2236 phytest | MII_TG3_FET_SHADOW_EN);
2237 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2238 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2239 tg3_writephy(tp,
2240 MII_TG3_FET_SHDW_AUXMODE4,
2241 phy);
2242 }
2243 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2244 }
2245 return;
2246 } else if (do_low_power) {
2247 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2248 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2249
2250 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2251 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2252 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2253 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2254 MII_TG3_AUXCTL_PCTL_VREG_11V);
2255 }
2256
2257 /* The PHY should not be powered down on some chips because
2258 * of bugs.
2259 */
2260 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2261 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2262 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2263 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2264 return;
2265
2266 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2267 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2268 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2269 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2270 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2271 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2272 }
2273
2274 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2275}
2276
2277/* tp->lock is held. */
2278static int tg3_nvram_lock(struct tg3 *tp)
2279{
2280 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2281 int i;
2282
2283 if (tp->nvram_lock_cnt == 0) {
2284 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2285 for (i = 0; i < 8000; i++) {
2286 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2287 break;
2288 udelay(20);
2289 }
2290 if (i == 8000) {
2291 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2292 return -ENODEV;
2293 }
2294 }
2295 tp->nvram_lock_cnt++;
2296 }
2297 return 0;
2298}
2299
2300/* tp->lock is held. */
2301static void tg3_nvram_unlock(struct tg3 *tp)
2302{
2303 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2304 if (tp->nvram_lock_cnt > 0)
2305 tp->nvram_lock_cnt--;
2306 if (tp->nvram_lock_cnt == 0)
2307 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2308 }
2309}
2310
2311/* tp->lock is held. */
2312static void tg3_enable_nvram_access(struct tg3 *tp)
2313{
2314 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2315 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2316 u32 nvaccess = tr32(NVRAM_ACCESS);
2317
2318 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2319 }
2320}
2321
2322/* tp->lock is held. */
2323static void tg3_disable_nvram_access(struct tg3 *tp)
2324{
2325 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2326 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2327 u32 nvaccess = tr32(NVRAM_ACCESS);
2328
2329 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2330 }
2331}
2332
2333static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2334 u32 offset, u32 *val)
2335{
2336 u32 tmp;
2337 int i;
2338
2339 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2340 return -EINVAL;
2341
2342 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2343 EEPROM_ADDR_DEVID_MASK |
2344 EEPROM_ADDR_READ);
2345 tw32(GRC_EEPROM_ADDR,
2346 tmp |
2347 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2348 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2349 EEPROM_ADDR_ADDR_MASK) |
2350 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2351
2352 for (i = 0; i < 1000; i++) {
2353 tmp = tr32(GRC_EEPROM_ADDR);
2354
2355 if (tmp & EEPROM_ADDR_COMPLETE)
2356 break;
2357 msleep(1);
2358 }
2359 if (!(tmp & EEPROM_ADDR_COMPLETE))
2360 return -EBUSY;
2361
2362 tmp = tr32(GRC_EEPROM_DATA);
2363
2364 /*
2365 * The data will always be opposite the native endian
2366 * format. Perform a blind byteswap to compensate.
2367 */
2368 *val = swab32(tmp);
2369
2370 return 0;
2371}
2372
2373#define NVRAM_CMD_TIMEOUT 10000
2374
2375static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2376{
2377 int i;
2378
2379 tw32(NVRAM_CMD, nvram_cmd);
2380 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2381 udelay(10);
2382 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2383 udelay(10);
2384 break;
2385 }
2386 }
2387
2388 if (i == NVRAM_CMD_TIMEOUT)
2389 return -EBUSY;
2390
2391 return 0;
2392}
2393
2394static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2395{
2396 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2397 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2398 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2399 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2400 (tp->nvram_jedecnum == JEDEC_ATMEL))
2401
2402 addr = ((addr / tp->nvram_pagesize) <<
2403 ATMEL_AT45DB0X1B_PAGE_POS) +
2404 (addr % tp->nvram_pagesize);
2405
2406 return addr;
2407}
2408
2409static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2410{
2411 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2412 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2413 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2414 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2415 (tp->nvram_jedecnum == JEDEC_ATMEL))
2416
2417 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2418 tp->nvram_pagesize) +
2419 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2420
2421 return addr;
2422}
2423
2424/* NOTE: Data read in from NVRAM is byteswapped according to
2425 * the byteswapping settings for all other register accesses.
2426 * tg3 devices are BE devices, so on a BE machine, the data
2427 * returned will be exactly as it is seen in NVRAM. On a LE
2428 * machine, the 32-bit value will be byteswapped.
2429 */
2430static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2431{
2432 int ret;
2433
2434 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2435 return tg3_nvram_read_using_eeprom(tp, offset, val);
2436
2437 offset = tg3_nvram_phys_addr(tp, offset);
2438
2439 if (offset > NVRAM_ADDR_MSK)
2440 return -EINVAL;
2441
2442 ret = tg3_nvram_lock(tp);
2443 if (ret)
2444 return ret;
2445
2446 tg3_enable_nvram_access(tp);
2447
2448 tw32(NVRAM_ADDR, offset);
2449 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2450 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2451
2452 if (ret == 0)
2453 *val = tr32(NVRAM_RDDATA);
2454
2455 tg3_disable_nvram_access(tp);
2456
2457 tg3_nvram_unlock(tp);
2458
2459 return ret;
2460}
2461
2462/* Ensures NVRAM data is in bytestream format. */
2463static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2464{
2465 u32 v;
2466 int res = tg3_nvram_read(tp, offset, &v);
2467 if (!res)
2468 *val = cpu_to_be32(v);
2469 return res;
2470}
2471
2472/* tp->lock is held. */
2473static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2474{
2475 u32 addr_high, addr_low;
2476 int i;
2477
2478 addr_high = ((tp->dev->dev_addr[0] << 8) |
2479 tp->dev->dev_addr[1]);
2480 addr_low = ((tp->dev->dev_addr[2] << 24) |
2481 (tp->dev->dev_addr[3] << 16) |
2482 (tp->dev->dev_addr[4] << 8) |
2483 (tp->dev->dev_addr[5] << 0));
2484 for (i = 0; i < 4; i++) {
2485 if (i == 1 && skip_mac_1)
2486 continue;
2487 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2488 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2489 }
2490
2491 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2492 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2493 for (i = 0; i < 12; i++) {
2494 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2495 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2496 }
2497 }
2498
2499 addr_high = (tp->dev->dev_addr[0] +
2500 tp->dev->dev_addr[1] +
2501 tp->dev->dev_addr[2] +
2502 tp->dev->dev_addr[3] +
2503 tp->dev->dev_addr[4] +
2504 tp->dev->dev_addr[5]) &
2505 TX_BACKOFF_SEED_MASK;
2506 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2507}
2508
2509static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2510{
2511 u32 misc_host_ctrl;
2512 bool device_should_wake, do_low_power;
2513
2514 /* Make sure register accesses (indirect or otherwise)
2515 * will function correctly.
2516 */
2517 pci_write_config_dword(tp->pdev,
2518 TG3PCI_MISC_HOST_CTRL,
2519 tp->misc_host_ctrl);
2520
2521 switch (state) {
2522 case PCI_D0:
2523 pci_enable_wake(tp->pdev, state, false);
2524 pci_set_power_state(tp->pdev, PCI_D0);
2525
2526 /* Switch out of Vaux if it is a NIC */
2527 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2528 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2529
2530 return 0;
2531
2532 case PCI_D1:
2533 case PCI_D2:
2534 case PCI_D3hot:
2535 break;
2536
2537 default:
2538 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2539 state);
2540 return -EINVAL;
2541 }
2542
2543 /* Restore the CLKREQ setting. */
2544 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2545 u16 lnkctl;
2546
2547 pci_read_config_word(tp->pdev,
2548 tp->pcie_cap + PCI_EXP_LNKCTL,
2549 &lnkctl);
2550 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2551 pci_write_config_word(tp->pdev,
2552 tp->pcie_cap + PCI_EXP_LNKCTL,
2553 lnkctl);
2554 }
2555
2556 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2557 tw32(TG3PCI_MISC_HOST_CTRL,
2558 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2559
2560 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2561 device_may_wakeup(&tp->pdev->dev) &&
2562 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2563
2564 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2565 do_low_power = false;
2566 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2567 !tp->link_config.phy_is_low_power) {
2568 struct phy_device *phydev;
2569 u32 phyid, advertising;
2570
2571 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2572
2573 tp->link_config.phy_is_low_power = 1;
2574
2575 tp->link_config.orig_speed = phydev->speed;
2576 tp->link_config.orig_duplex = phydev->duplex;
2577 tp->link_config.orig_autoneg = phydev->autoneg;
2578 tp->link_config.orig_advertising = phydev->advertising;
2579
2580 advertising = ADVERTISED_TP |
2581 ADVERTISED_Pause |
2582 ADVERTISED_Autoneg |
2583 ADVERTISED_10baseT_Half;
2584
2585 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2586 device_should_wake) {
2587 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2588 advertising |=
2589 ADVERTISED_100baseT_Half |
2590 ADVERTISED_100baseT_Full |
2591 ADVERTISED_10baseT_Full;
2592 else
2593 advertising |= ADVERTISED_10baseT_Full;
2594 }
2595
2596 phydev->advertising = advertising;
2597
2598 phy_start_aneg(phydev);
2599
2600 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2601 if (phyid != PHY_ID_BCMAC131) {
2602 phyid &= PHY_BCM_OUI_MASK;
2603 if (phyid == PHY_BCM_OUI_1 ||
2604 phyid == PHY_BCM_OUI_2 ||
2605 phyid == PHY_BCM_OUI_3)
2606 do_low_power = true;
2607 }
2608 }
2609 } else {
2610 do_low_power = true;
2611
2612 if (tp->link_config.phy_is_low_power == 0) {
2613 tp->link_config.phy_is_low_power = 1;
2614 tp->link_config.orig_speed = tp->link_config.speed;
2615 tp->link_config.orig_duplex = tp->link_config.duplex;
2616 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2617 }
2618
2619 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2620 tp->link_config.speed = SPEED_10;
2621 tp->link_config.duplex = DUPLEX_HALF;
2622 tp->link_config.autoneg = AUTONEG_ENABLE;
2623 tg3_setup_phy(tp, 0);
2624 }
2625 }
2626
2627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2628 u32 val;
2629
2630 val = tr32(GRC_VCPU_EXT_CTRL);
2631 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2632 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2633 int i;
2634 u32 val;
2635
2636 for (i = 0; i < 200; i++) {
2637 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2638 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2639 break;
2640 msleep(1);
2641 }
2642 }
2643 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2644 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2645 WOL_DRV_STATE_SHUTDOWN |
2646 WOL_DRV_WOL |
2647 WOL_SET_MAGIC_PKT);
2648
2649 if (device_should_wake) {
2650 u32 mac_mode;
2651
2652 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2653 if (do_low_power) {
2654 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2655 udelay(40);
2656 }
2657
2658 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2659 mac_mode = MAC_MODE_PORT_MODE_GMII;
2660 else
2661 mac_mode = MAC_MODE_PORT_MODE_MII;
2662
2663 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2664 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2665 ASIC_REV_5700) {
2666 u32 speed = (tp->tg3_flags &
2667 TG3_FLAG_WOL_SPEED_100MB) ?
2668 SPEED_100 : SPEED_10;
2669 if (tg3_5700_link_polarity(tp, speed))
2670 mac_mode |= MAC_MODE_LINK_POLARITY;
2671 else
2672 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2673 }
2674 } else {
2675 mac_mode = MAC_MODE_PORT_MODE_TBI;
2676 }
2677
2678 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2679 tw32(MAC_LED_CTRL, tp->led_ctrl);
2680
2681 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2682 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2683 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2684 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2685 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2686 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2687
2688 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2689 mac_mode |= tp->mac_mode &
2690 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2691 if (mac_mode & MAC_MODE_APE_TX_EN)
2692 mac_mode |= MAC_MODE_TDE_ENABLE;
2693 }
2694
2695 tw32_f(MAC_MODE, mac_mode);
2696 udelay(100);
2697
2698 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2699 udelay(10);
2700 }
2701
2702 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2703 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2705 u32 base_val;
2706
2707 base_val = tp->pci_clock_ctrl;
2708 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2709 CLOCK_CTRL_TXCLK_DISABLE);
2710
2711 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2712 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2713 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2714 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2715 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2716 /* do nothing */
2717 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2718 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2719 u32 newbits1, newbits2;
2720
2721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2723 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2724 CLOCK_CTRL_TXCLK_DISABLE |
2725 CLOCK_CTRL_ALTCLK);
2726 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2727 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2728 newbits1 = CLOCK_CTRL_625_CORE;
2729 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2730 } else {
2731 newbits1 = CLOCK_CTRL_ALTCLK;
2732 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2733 }
2734
2735 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2736 40);
2737
2738 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2739 40);
2740
2741 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2742 u32 newbits3;
2743
2744 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2745 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2746 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2747 CLOCK_CTRL_TXCLK_DISABLE |
2748 CLOCK_CTRL_44MHZ_CORE);
2749 } else {
2750 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2751 }
2752
2753 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2754 tp->pci_clock_ctrl | newbits3, 40);
2755 }
2756 }
2757
2758 if (!(device_should_wake) &&
2759 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2760 tg3_power_down_phy(tp, do_low_power);
2761
2762 tg3_frob_aux_power(tp);
2763
2764 /* Workaround for unstable PLL clock */
2765 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2766 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2767 u32 val = tr32(0x7d00);
2768
2769 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2770 tw32(0x7d00, val);
2771 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2772 int err;
2773
2774 err = tg3_nvram_lock(tp);
2775 tg3_halt_cpu(tp, RX_CPU_BASE);
2776 if (!err)
2777 tg3_nvram_unlock(tp);
2778 }
2779 }
2780
2781 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2782
2783 if (device_should_wake)
2784 pci_enable_wake(tp->pdev, state, true);
2785
2786 /* Finally, set the new power state. */
2787 pci_set_power_state(tp->pdev, state);
2788
2789 return 0;
2790}
2791
2792static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2793{
2794 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2795 case MII_TG3_AUX_STAT_10HALF:
2796 *speed = SPEED_10;
2797 *duplex = DUPLEX_HALF;
2798 break;
2799
2800 case MII_TG3_AUX_STAT_10FULL:
2801 *speed = SPEED_10;
2802 *duplex = DUPLEX_FULL;
2803 break;
2804
2805 case MII_TG3_AUX_STAT_100HALF:
2806 *speed = SPEED_100;
2807 *duplex = DUPLEX_HALF;
2808 break;
2809
2810 case MII_TG3_AUX_STAT_100FULL:
2811 *speed = SPEED_100;
2812 *duplex = DUPLEX_FULL;
2813 break;
2814
2815 case MII_TG3_AUX_STAT_1000HALF:
2816 *speed = SPEED_1000;
2817 *duplex = DUPLEX_HALF;
2818 break;
2819
2820 case MII_TG3_AUX_STAT_1000FULL:
2821 *speed = SPEED_1000;
2822 *duplex = DUPLEX_FULL;
2823 break;
2824
2825 default:
2826 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2827 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2828 SPEED_10;
2829 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2830 DUPLEX_HALF;
2831 break;
2832 }
2833 *speed = SPEED_INVALID;
2834 *duplex = DUPLEX_INVALID;
2835 break;
2836 }
2837}
2838
2839static void tg3_phy_copper_begin(struct tg3 *tp)
2840{
2841 u32 new_adv;
2842 int i;
2843
2844 if (tp->link_config.phy_is_low_power) {
2845 /* Entering low power mode. Disable gigabit and
2846 * 100baseT advertisements.
2847 */
2848 tg3_writephy(tp, MII_TG3_CTRL, 0);
2849
2850 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2851 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2852 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2853 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2854
2855 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2856 } else if (tp->link_config.speed == SPEED_INVALID) {
2857 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2858 tp->link_config.advertising &=
2859 ~(ADVERTISED_1000baseT_Half |
2860 ADVERTISED_1000baseT_Full);
2861
2862 new_adv = ADVERTISE_CSMA;
2863 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2864 new_adv |= ADVERTISE_10HALF;
2865 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2866 new_adv |= ADVERTISE_10FULL;
2867 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2868 new_adv |= ADVERTISE_100HALF;
2869 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2870 new_adv |= ADVERTISE_100FULL;
2871
2872 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2873
2874 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2875
2876 if (tp->link_config.advertising &
2877 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2878 new_adv = 0;
2879 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2880 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2881 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2882 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2883 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2884 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2885 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2886 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2887 MII_TG3_CTRL_ENABLE_AS_MASTER);
2888 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2889 } else {
2890 tg3_writephy(tp, MII_TG3_CTRL, 0);
2891 }
2892 } else {
2893 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2894 new_adv |= ADVERTISE_CSMA;
2895
2896 /* Asking for a specific link mode. */
2897 if (tp->link_config.speed == SPEED_1000) {
2898 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2899
2900 if (tp->link_config.duplex == DUPLEX_FULL)
2901 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2902 else
2903 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2904 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2905 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2906 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2907 MII_TG3_CTRL_ENABLE_AS_MASTER);
2908 } else {
2909 if (tp->link_config.speed == SPEED_100) {
2910 if (tp->link_config.duplex == DUPLEX_FULL)
2911 new_adv |= ADVERTISE_100FULL;
2912 else
2913 new_adv |= ADVERTISE_100HALF;
2914 } else {
2915 if (tp->link_config.duplex == DUPLEX_FULL)
2916 new_adv |= ADVERTISE_10FULL;
2917 else
2918 new_adv |= ADVERTISE_10HALF;
2919 }
2920 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2921
2922 new_adv = 0;
2923 }
2924
2925 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2926 }
2927
2928 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2929 tp->link_config.speed != SPEED_INVALID) {
2930 u32 bmcr, orig_bmcr;
2931
2932 tp->link_config.active_speed = tp->link_config.speed;
2933 tp->link_config.active_duplex = tp->link_config.duplex;
2934
2935 bmcr = 0;
2936 switch (tp->link_config.speed) {
2937 default:
2938 case SPEED_10:
2939 break;
2940
2941 case SPEED_100:
2942 bmcr |= BMCR_SPEED100;
2943 break;
2944
2945 case SPEED_1000:
2946 bmcr |= TG3_BMCR_SPEED1000;
2947 break;
2948 }
2949
2950 if (tp->link_config.duplex == DUPLEX_FULL)
2951 bmcr |= BMCR_FULLDPLX;
2952
2953 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2954 (bmcr != orig_bmcr)) {
2955 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2956 for (i = 0; i < 1500; i++) {
2957 u32 tmp;
2958
2959 udelay(10);
2960 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2961 tg3_readphy(tp, MII_BMSR, &tmp))
2962 continue;
2963 if (!(tmp & BMSR_LSTATUS)) {
2964 udelay(40);
2965 break;
2966 }
2967 }
2968 tg3_writephy(tp, MII_BMCR, bmcr);
2969 udelay(40);
2970 }
2971 } else {
2972 tg3_writephy(tp, MII_BMCR,
2973 BMCR_ANENABLE | BMCR_ANRESTART);
2974 }
2975}
2976
2977static int tg3_init_5401phy_dsp(struct tg3 *tp)
2978{
2979 int err;
2980
2981 /* Turn off tap power management. */
2982 /* Set Extended packet length bit */
2983 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2984
2985 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2986 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2987
2988 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2989 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2990
2991 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2992 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2993
2994 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2995 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2996
2997 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2998 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2999
3000 udelay(40);
3001
3002 return err;
3003}
3004
3005static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3006{
3007 u32 adv_reg, all_mask = 0;
3008
3009 if (mask & ADVERTISED_10baseT_Half)
3010 all_mask |= ADVERTISE_10HALF;
3011 if (mask & ADVERTISED_10baseT_Full)
3012 all_mask |= ADVERTISE_10FULL;
3013 if (mask & ADVERTISED_100baseT_Half)
3014 all_mask |= ADVERTISE_100HALF;
3015 if (mask & ADVERTISED_100baseT_Full)
3016 all_mask |= ADVERTISE_100FULL;
3017
3018 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3019 return 0;
3020
3021 if ((adv_reg & all_mask) != all_mask)
3022 return 0;
3023 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3024 u32 tg3_ctrl;
3025
3026 all_mask = 0;
3027 if (mask & ADVERTISED_1000baseT_Half)
3028 all_mask |= ADVERTISE_1000HALF;
3029 if (mask & ADVERTISED_1000baseT_Full)
3030 all_mask |= ADVERTISE_1000FULL;
3031
3032 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3033 return 0;
3034
3035 if ((tg3_ctrl & all_mask) != all_mask)
3036 return 0;
3037 }
3038 return 1;
3039}
3040
3041static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3042{
3043 u32 curadv, reqadv;
3044
3045 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3046 return 1;
3047
3048 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3049 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3050
3051 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3052 if (curadv != reqadv)
3053 return 0;
3054
3055 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3056 tg3_readphy(tp, MII_LPA, rmtadv);
3057 } else {
3058 /* Reprogram the advertisement register, even if it
3059 * does not affect the current link. If the link
3060 * gets renegotiated in the future, we can save an
3061 * additional renegotiation cycle by advertising
3062 * it correctly in the first place.
3063 */
3064 if (curadv != reqadv) {
3065 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3066 ADVERTISE_PAUSE_ASYM);
3067 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3068 }
3069 }
3070
3071 return 1;
3072}
3073
3074static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3075{
3076 int current_link_up;
3077 u32 bmsr, dummy;
3078 u32 lcl_adv, rmt_adv;
3079 u16 current_speed;
3080 u8 current_duplex;
3081 int i, err;
3082
3083 tw32(MAC_EVENT, 0);
3084
3085 tw32_f(MAC_STATUS,
3086 (MAC_STATUS_SYNC_CHANGED |
3087 MAC_STATUS_CFG_CHANGED |
3088 MAC_STATUS_MI_COMPLETION |
3089 MAC_STATUS_LNKSTATE_CHANGED));
3090 udelay(40);
3091
3092 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3093 tw32_f(MAC_MI_MODE,
3094 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3095 udelay(80);
3096 }
3097
3098 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3099
3100 /* Some third-party PHYs need to be reset on link going
3101 * down.
3102 */
3103 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3106 netif_carrier_ok(tp->dev)) {
3107 tg3_readphy(tp, MII_BMSR, &bmsr);
3108 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3109 !(bmsr & BMSR_LSTATUS))
3110 force_reset = 1;
3111 }
3112 if (force_reset)
3113 tg3_phy_reset(tp);
3114
3115 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3116 tg3_readphy(tp, MII_BMSR, &bmsr);
3117 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3118 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3119 bmsr = 0;
3120
3121 if (!(bmsr & BMSR_LSTATUS)) {
3122 err = tg3_init_5401phy_dsp(tp);
3123 if (err)
3124 return err;
3125
3126 tg3_readphy(tp, MII_BMSR, &bmsr);
3127 for (i = 0; i < 1000; i++) {
3128 udelay(10);
3129 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130 (bmsr & BMSR_LSTATUS)) {
3131 udelay(40);
3132 break;
3133 }
3134 }
3135
3136 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3137 TG3_PHY_REV_BCM5401_B0 &&
3138 !(bmsr & BMSR_LSTATUS) &&
3139 tp->link_config.active_speed == SPEED_1000) {
3140 err = tg3_phy_reset(tp);
3141 if (!err)
3142 err = tg3_init_5401phy_dsp(tp);
3143 if (err)
3144 return err;
3145 }
3146 }
3147 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3148 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3149 /* 5701 {A0,B0} CRC bug workaround */
3150 tg3_writephy(tp, 0x15, 0x0a75);
3151 tg3_writephy(tp, 0x1c, 0x8c68);
3152 tg3_writephy(tp, 0x1c, 0x8d68);
3153 tg3_writephy(tp, 0x1c, 0x8c68);
3154 }
3155
3156 /* Clear pending interrupts... */
3157 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3158 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3159
3160 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3161 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3162 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3163 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3164
3165 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3167 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3168 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3169 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3170 else
3171 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3172 }
3173
3174 current_link_up = 0;
3175 current_speed = SPEED_INVALID;
3176 current_duplex = DUPLEX_INVALID;
3177
3178 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3179 u32 val;
3180
3181 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3182 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3183 if (!(val & (1 << 10))) {
3184 val |= (1 << 10);
3185 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3186 goto relink;
3187 }
3188 }
3189
3190 bmsr = 0;
3191 for (i = 0; i < 100; i++) {
3192 tg3_readphy(tp, MII_BMSR, &bmsr);
3193 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3194 (bmsr & BMSR_LSTATUS))
3195 break;
3196 udelay(40);
3197 }
3198
3199 if (bmsr & BMSR_LSTATUS) {
3200 u32 aux_stat, bmcr;
3201
3202 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3203 for (i = 0; i < 2000; i++) {
3204 udelay(10);
3205 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3206 aux_stat)
3207 break;
3208 }
3209
3210 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3211 &current_speed,
3212 &current_duplex);
3213
3214 bmcr = 0;
3215 for (i = 0; i < 200; i++) {
3216 tg3_readphy(tp, MII_BMCR, &bmcr);
3217 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3218 continue;
3219 if (bmcr && bmcr != 0x7fff)
3220 break;
3221 udelay(10);
3222 }
3223
3224 lcl_adv = 0;
3225 rmt_adv = 0;
3226
3227 tp->link_config.active_speed = current_speed;
3228 tp->link_config.active_duplex = current_duplex;
3229
3230 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3231 if ((bmcr & BMCR_ANENABLE) &&
3232 tg3_copper_is_advertising_all(tp,
3233 tp->link_config.advertising)) {
3234 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3235 &rmt_adv))
3236 current_link_up = 1;
3237 }
3238 } else {
3239 if (!(bmcr & BMCR_ANENABLE) &&
3240 tp->link_config.speed == current_speed &&
3241 tp->link_config.duplex == current_duplex &&
3242 tp->link_config.flowctrl ==
3243 tp->link_config.active_flowctrl) {
3244 current_link_up = 1;
3245 }
3246 }
3247
3248 if (current_link_up == 1 &&
3249 tp->link_config.active_duplex == DUPLEX_FULL)
3250 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3251 }
3252
3253relink:
3254 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3255 u32 tmp;
3256
3257 tg3_phy_copper_begin(tp);
3258
3259 tg3_readphy(tp, MII_BMSR, &tmp);
3260 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3261 (tmp & BMSR_LSTATUS))
3262 current_link_up = 1;
3263 }
3264
3265 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3266 if (current_link_up == 1) {
3267 if (tp->link_config.active_speed == SPEED_100 ||
3268 tp->link_config.active_speed == SPEED_10)
3269 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3270 else
3271 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3272 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3273 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3274 else
3275 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3276
3277 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3278 if (tp->link_config.active_duplex == DUPLEX_HALF)
3279 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3280
3281 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3282 if (current_link_up == 1 &&
3283 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3284 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3285 else
3286 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3287 }
3288
3289 /* ??? Without this setting Netgear GA302T PHY does not
3290 * ??? send/receive packets...
3291 */
3292 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3293 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3294 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3295 tw32_f(MAC_MI_MODE, tp->mi_mode);
3296 udelay(80);
3297 }
3298
3299 tw32_f(MAC_MODE, tp->mac_mode);
3300 udelay(40);
3301
3302 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3303 /* Polled via timer. */
3304 tw32_f(MAC_EVENT, 0);
3305 } else {
3306 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3307 }
3308 udelay(40);
3309
3310 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3311 current_link_up == 1 &&
3312 tp->link_config.active_speed == SPEED_1000 &&
3313 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3314 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3315 udelay(120);
3316 tw32_f(MAC_STATUS,
3317 (MAC_STATUS_SYNC_CHANGED |
3318 MAC_STATUS_CFG_CHANGED));
3319 udelay(40);
3320 tg3_write_mem(tp,
3321 NIC_SRAM_FIRMWARE_MBOX,
3322 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3323 }
3324
3325 /* Prevent send BD corruption. */
3326 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3327 u16 oldlnkctl, newlnkctl;
3328
3329 pci_read_config_word(tp->pdev,
3330 tp->pcie_cap + PCI_EXP_LNKCTL,
3331 &oldlnkctl);
3332 if (tp->link_config.active_speed == SPEED_100 ||
3333 tp->link_config.active_speed == SPEED_10)
3334 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3335 else
3336 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3337 if (newlnkctl != oldlnkctl)
3338 pci_write_config_word(tp->pdev,
3339 tp->pcie_cap + PCI_EXP_LNKCTL,
3340 newlnkctl);
3341 }
3342
3343 if (current_link_up != netif_carrier_ok(tp->dev)) {
3344 if (current_link_up)
3345 netif_carrier_on(tp->dev);
3346 else
3347 netif_carrier_off(tp->dev);
3348 tg3_link_report(tp);
3349 }
3350
3351 return 0;
3352}
3353
3354struct tg3_fiber_aneginfo {
3355 int state;
3356#define ANEG_STATE_UNKNOWN 0
3357#define ANEG_STATE_AN_ENABLE 1
3358#define ANEG_STATE_RESTART_INIT 2
3359#define ANEG_STATE_RESTART 3
3360#define ANEG_STATE_DISABLE_LINK_OK 4
3361#define ANEG_STATE_ABILITY_DETECT_INIT 5
3362#define ANEG_STATE_ABILITY_DETECT 6
3363#define ANEG_STATE_ACK_DETECT_INIT 7
3364#define ANEG_STATE_ACK_DETECT 8
3365#define ANEG_STATE_COMPLETE_ACK_INIT 9
3366#define ANEG_STATE_COMPLETE_ACK 10
3367#define ANEG_STATE_IDLE_DETECT_INIT 11
3368#define ANEG_STATE_IDLE_DETECT 12
3369#define ANEG_STATE_LINK_OK 13
3370#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3371#define ANEG_STATE_NEXT_PAGE_WAIT 15
3372
3373 u32 flags;
3374#define MR_AN_ENABLE 0x00000001
3375#define MR_RESTART_AN 0x00000002
3376#define MR_AN_COMPLETE 0x00000004
3377#define MR_PAGE_RX 0x00000008
3378#define MR_NP_LOADED 0x00000010
3379#define MR_TOGGLE_TX 0x00000020
3380#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3381#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3382#define MR_LP_ADV_SYM_PAUSE 0x00000100
3383#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3384#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3385#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3386#define MR_LP_ADV_NEXT_PAGE 0x00001000
3387#define MR_TOGGLE_RX 0x00002000
3388#define MR_NP_RX 0x00004000
3389
3390#define MR_LINK_OK 0x80000000
3391
3392 unsigned long link_time, cur_time;
3393
3394 u32 ability_match_cfg;
3395 int ability_match_count;
3396
3397 char ability_match, idle_match, ack_match;
3398
3399 u32 txconfig, rxconfig;
3400#define ANEG_CFG_NP 0x00000080
3401#define ANEG_CFG_ACK 0x00000040
3402#define ANEG_CFG_RF2 0x00000020
3403#define ANEG_CFG_RF1 0x00000010
3404#define ANEG_CFG_PS2 0x00000001
3405#define ANEG_CFG_PS1 0x00008000
3406#define ANEG_CFG_HD 0x00004000
3407#define ANEG_CFG_FD 0x00002000
3408#define ANEG_CFG_INVAL 0x00001f06
3409
3410};
3411#define ANEG_OK 0
3412#define ANEG_DONE 1
3413#define ANEG_TIMER_ENAB 2
3414#define ANEG_FAILED -1
3415
3416#define ANEG_STATE_SETTLE_TIME 10000
3417
3418static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3419 struct tg3_fiber_aneginfo *ap)
3420{
3421 u16 flowctrl;
3422 unsigned long delta;
3423 u32 rx_cfg_reg;
3424 int ret;
3425
3426 if (ap->state == ANEG_STATE_UNKNOWN) {
3427 ap->rxconfig = 0;
3428 ap->link_time = 0;
3429 ap->cur_time = 0;
3430 ap->ability_match_cfg = 0;
3431 ap->ability_match_count = 0;
3432 ap->ability_match = 0;
3433 ap->idle_match = 0;
3434 ap->ack_match = 0;
3435 }
3436 ap->cur_time++;
3437
3438 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3439 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3440
3441 if (rx_cfg_reg != ap->ability_match_cfg) {
3442 ap->ability_match_cfg = rx_cfg_reg;
3443 ap->ability_match = 0;
3444 ap->ability_match_count = 0;
3445 } else {
3446 if (++ap->ability_match_count > 1) {
3447 ap->ability_match = 1;
3448 ap->ability_match_cfg = rx_cfg_reg;
3449 }
3450 }
3451 if (rx_cfg_reg & ANEG_CFG_ACK)
3452 ap->ack_match = 1;
3453 else
3454 ap->ack_match = 0;
3455
3456 ap->idle_match = 0;
3457 } else {
3458 ap->idle_match = 1;
3459 ap->ability_match_cfg = 0;
3460 ap->ability_match_count = 0;
3461 ap->ability_match = 0;
3462 ap->ack_match = 0;
3463
3464 rx_cfg_reg = 0;
3465 }
3466
3467 ap->rxconfig = rx_cfg_reg;
3468 ret = ANEG_OK;
3469
3470 switch (ap->state) {
3471 case ANEG_STATE_UNKNOWN:
3472 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3473 ap->state = ANEG_STATE_AN_ENABLE;
3474
3475 /* fallthru */
3476 case ANEG_STATE_AN_ENABLE:
3477 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3478 if (ap->flags & MR_AN_ENABLE) {
3479 ap->link_time = 0;
3480 ap->cur_time = 0;
3481 ap->ability_match_cfg = 0;
3482 ap->ability_match_count = 0;
3483 ap->ability_match = 0;
3484 ap->idle_match = 0;
3485 ap->ack_match = 0;
3486
3487 ap->state = ANEG_STATE_RESTART_INIT;
3488 } else {
3489 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3490 }
3491 break;
3492
3493 case ANEG_STATE_RESTART_INIT:
3494 ap->link_time = ap->cur_time;
3495 ap->flags &= ~(MR_NP_LOADED);
3496 ap->txconfig = 0;
3497 tw32(MAC_TX_AUTO_NEG, 0);
3498 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3499 tw32_f(MAC_MODE, tp->mac_mode);
3500 udelay(40);
3501
3502 ret = ANEG_TIMER_ENAB;
3503 ap->state = ANEG_STATE_RESTART;
3504
3505 /* fallthru */
3506 case ANEG_STATE_RESTART:
3507 delta = ap->cur_time - ap->link_time;
3508 if (delta > ANEG_STATE_SETTLE_TIME)
3509 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3510 else
3511 ret = ANEG_TIMER_ENAB;
3512 break;
3513
3514 case ANEG_STATE_DISABLE_LINK_OK:
3515 ret = ANEG_DONE;
3516 break;
3517
3518 case ANEG_STATE_ABILITY_DETECT_INIT:
3519 ap->flags &= ~(MR_TOGGLE_TX);
3520 ap->txconfig = ANEG_CFG_FD;
3521 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3522 if (flowctrl & ADVERTISE_1000XPAUSE)
3523 ap->txconfig |= ANEG_CFG_PS1;
3524 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3525 ap->txconfig |= ANEG_CFG_PS2;
3526 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3527 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3528 tw32_f(MAC_MODE, tp->mac_mode);
3529 udelay(40);
3530
3531 ap->state = ANEG_STATE_ABILITY_DETECT;
3532 break;
3533
3534 case ANEG_STATE_ABILITY_DETECT:
3535 if (ap->ability_match != 0 && ap->rxconfig != 0)
3536 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3537 break;
3538
3539 case ANEG_STATE_ACK_DETECT_INIT:
3540 ap->txconfig |= ANEG_CFG_ACK;
3541 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3542 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3543 tw32_f(MAC_MODE, tp->mac_mode);
3544 udelay(40);
3545
3546 ap->state = ANEG_STATE_ACK_DETECT;
3547
3548 /* fallthru */
3549 case ANEG_STATE_ACK_DETECT:
3550 if (ap->ack_match != 0) {
3551 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3552 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3553 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3554 } else {
3555 ap->state = ANEG_STATE_AN_ENABLE;
3556 }
3557 } else if (ap->ability_match != 0 &&
3558 ap->rxconfig == 0) {
3559 ap->state = ANEG_STATE_AN_ENABLE;
3560 }
3561 break;
3562
3563 case ANEG_STATE_COMPLETE_ACK_INIT:
3564 if (ap->rxconfig & ANEG_CFG_INVAL) {
3565 ret = ANEG_FAILED;
3566 break;
3567 }
3568 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3569 MR_LP_ADV_HALF_DUPLEX |
3570 MR_LP_ADV_SYM_PAUSE |
3571 MR_LP_ADV_ASYM_PAUSE |
3572 MR_LP_ADV_REMOTE_FAULT1 |
3573 MR_LP_ADV_REMOTE_FAULT2 |
3574 MR_LP_ADV_NEXT_PAGE |
3575 MR_TOGGLE_RX |
3576 MR_NP_RX);
3577 if (ap->rxconfig & ANEG_CFG_FD)
3578 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3579 if (ap->rxconfig & ANEG_CFG_HD)
3580 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3581 if (ap->rxconfig & ANEG_CFG_PS1)
3582 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3583 if (ap->rxconfig & ANEG_CFG_PS2)
3584 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3585 if (ap->rxconfig & ANEG_CFG_RF1)
3586 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3587 if (ap->rxconfig & ANEG_CFG_RF2)
3588 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3589 if (ap->rxconfig & ANEG_CFG_NP)
3590 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3591
3592 ap->link_time = ap->cur_time;
3593
3594 ap->flags ^= (MR_TOGGLE_TX);
3595 if (ap->rxconfig & 0x0008)
3596 ap->flags |= MR_TOGGLE_RX;
3597 if (ap->rxconfig & ANEG_CFG_NP)
3598 ap->flags |= MR_NP_RX;
3599 ap->flags |= MR_PAGE_RX;
3600
3601 ap->state = ANEG_STATE_COMPLETE_ACK;
3602 ret = ANEG_TIMER_ENAB;
3603 break;
3604
3605 case ANEG_STATE_COMPLETE_ACK:
3606 if (ap->ability_match != 0 &&
3607 ap->rxconfig == 0) {
3608 ap->state = ANEG_STATE_AN_ENABLE;
3609 break;
3610 }
3611 delta = ap->cur_time - ap->link_time;
3612 if (delta > ANEG_STATE_SETTLE_TIME) {
3613 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3614 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3615 } else {
3616 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3617 !(ap->flags & MR_NP_RX)) {
3618 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3619 } else {
3620 ret = ANEG_FAILED;
3621 }
3622 }
3623 }
3624 break;
3625
3626 case ANEG_STATE_IDLE_DETECT_INIT:
3627 ap->link_time = ap->cur_time;
3628 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3629 tw32_f(MAC_MODE, tp->mac_mode);
3630 udelay(40);
3631
3632 ap->state = ANEG_STATE_IDLE_DETECT;
3633 ret = ANEG_TIMER_ENAB;
3634 break;
3635
3636 case ANEG_STATE_IDLE_DETECT:
3637 if (ap->ability_match != 0 &&
3638 ap->rxconfig == 0) {
3639 ap->state = ANEG_STATE_AN_ENABLE;
3640 break;
3641 }
3642 delta = ap->cur_time - ap->link_time;
3643 if (delta > ANEG_STATE_SETTLE_TIME) {
3644 /* XXX another gem from the Broadcom driver :( */
3645 ap->state = ANEG_STATE_LINK_OK;
3646 }
3647 break;
3648
3649 case ANEG_STATE_LINK_OK:
3650 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3651 ret = ANEG_DONE;
3652 break;
3653
3654 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3655 /* ??? unimplemented */
3656 break;
3657
3658 case ANEG_STATE_NEXT_PAGE_WAIT:
3659 /* ??? unimplemented */
3660 break;
3661
3662 default:
3663 ret = ANEG_FAILED;
3664 break;
3665 }
3666
3667 return ret;
3668}
3669
3670static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3671{
3672 int res = 0;
3673 struct tg3_fiber_aneginfo aninfo;
3674 int status = ANEG_FAILED;
3675 unsigned int tick;
3676 u32 tmp;
3677
3678 tw32_f(MAC_TX_AUTO_NEG, 0);
3679
3680 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3681 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3682 udelay(40);
3683
3684 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3685 udelay(40);
3686
3687 memset(&aninfo, 0, sizeof(aninfo));
3688 aninfo.flags |= MR_AN_ENABLE;
3689 aninfo.state = ANEG_STATE_UNKNOWN;
3690 aninfo.cur_time = 0;
3691 tick = 0;
3692 while (++tick < 195000) {
3693 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3694 if (status == ANEG_DONE || status == ANEG_FAILED)
3695 break;
3696
3697 udelay(1);
3698 }
3699
3700 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3701 tw32_f(MAC_MODE, tp->mac_mode);
3702 udelay(40);
3703
3704 *txflags = aninfo.txconfig;
3705 *rxflags = aninfo.flags;
3706
3707 if (status == ANEG_DONE &&
3708 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3709 MR_LP_ADV_FULL_DUPLEX)))
3710 res = 1;
3711
3712 return res;
3713}
3714
3715static void tg3_init_bcm8002(struct tg3 *tp)
3716{
3717 u32 mac_status = tr32(MAC_STATUS);
3718 int i;
3719
3720 /* Reset when initting first time or we have a link. */
3721 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3722 !(mac_status & MAC_STATUS_PCS_SYNCED))
3723 return;
3724
3725 /* Set PLL lock range. */
3726 tg3_writephy(tp, 0x16, 0x8007);
3727
3728 /* SW reset */
3729 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3730
3731 /* Wait for reset to complete. */
3732 /* XXX schedule_timeout() ... */
3733 for (i = 0; i < 500; i++)
3734 udelay(10);
3735
3736 /* Config mode; select PMA/Ch 1 regs. */
3737 tg3_writephy(tp, 0x10, 0x8411);
3738
3739 /* Enable auto-lock and comdet, select txclk for tx. */
3740 tg3_writephy(tp, 0x11, 0x0a10);
3741
3742 tg3_writephy(tp, 0x18, 0x00a0);
3743 tg3_writephy(tp, 0x16, 0x41ff);
3744
3745 /* Assert and deassert POR. */
3746 tg3_writephy(tp, 0x13, 0x0400);
3747 udelay(40);
3748 tg3_writephy(tp, 0x13, 0x0000);
3749
3750 tg3_writephy(tp, 0x11, 0x0a50);
3751 udelay(40);
3752 tg3_writephy(tp, 0x11, 0x0a10);
3753
3754 /* Wait for signal to stabilize */
3755 /* XXX schedule_timeout() ... */
3756 for (i = 0; i < 15000; i++)
3757 udelay(10);
3758
3759 /* Deselect the channel register so we can read the PHYID
3760 * later.
3761 */
3762 tg3_writephy(tp, 0x10, 0x8011);
3763}
3764
3765static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3766{
3767 u16 flowctrl;
3768 u32 sg_dig_ctrl, sg_dig_status;
3769 u32 serdes_cfg, expected_sg_dig_ctrl;
3770 int workaround, port_a;
3771 int current_link_up;
3772
3773 serdes_cfg = 0;
3774 expected_sg_dig_ctrl = 0;
3775 workaround = 0;
3776 port_a = 1;
3777 current_link_up = 0;
3778
3779 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3780 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3781 workaround = 1;
3782 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3783 port_a = 0;
3784
3785 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3786 /* preserve bits 20-23 for voltage regulator */
3787 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3788 }
3789
3790 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3791
3792 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3793 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3794 if (workaround) {
3795 u32 val = serdes_cfg;
3796
3797 if (port_a)
3798 val |= 0xc010000;
3799 else
3800 val |= 0x4010000;
3801 tw32_f(MAC_SERDES_CFG, val);
3802 }
3803
3804 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3805 }
3806 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3807 tg3_setup_flow_control(tp, 0, 0);
3808 current_link_up = 1;
3809 }
3810 goto out;
3811 }
3812
3813 /* Want auto-negotiation. */
3814 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3815
3816 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3817 if (flowctrl & ADVERTISE_1000XPAUSE)
3818 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3819 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3820 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3821
3822 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3823 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3824 tp->serdes_counter &&
3825 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3826 MAC_STATUS_RCVD_CFG)) ==
3827 MAC_STATUS_PCS_SYNCED)) {
3828 tp->serdes_counter--;
3829 current_link_up = 1;
3830 goto out;
3831 }
3832restart_autoneg:
3833 if (workaround)
3834 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3835 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3836 udelay(5);
3837 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3838
3839 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3840 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3841 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3842 MAC_STATUS_SIGNAL_DET)) {
3843 sg_dig_status = tr32(SG_DIG_STATUS);
3844 mac_status = tr32(MAC_STATUS);
3845
3846 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3847 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3848 u32 local_adv = 0, remote_adv = 0;
3849
3850 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3851 local_adv |= ADVERTISE_1000XPAUSE;
3852 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3853 local_adv |= ADVERTISE_1000XPSE_ASYM;
3854
3855 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3856 remote_adv |= LPA_1000XPAUSE;
3857 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3858 remote_adv |= LPA_1000XPAUSE_ASYM;
3859
3860 tg3_setup_flow_control(tp, local_adv, remote_adv);
3861 current_link_up = 1;
3862 tp->serdes_counter = 0;
3863 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3864 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3865 if (tp->serdes_counter)
3866 tp->serdes_counter--;
3867 else {
3868 if (workaround) {
3869 u32 val = serdes_cfg;
3870
3871 if (port_a)
3872 val |= 0xc010000;
3873 else
3874 val |= 0x4010000;
3875
3876 tw32_f(MAC_SERDES_CFG, val);
3877 }
3878
3879 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3880 udelay(40);
3881
3882 /* Link parallel detection - link is up */
3883 /* only if we have PCS_SYNC and not */
3884 /* receiving config code words */
3885 mac_status = tr32(MAC_STATUS);
3886 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3887 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3888 tg3_setup_flow_control(tp, 0, 0);
3889 current_link_up = 1;
3890 tp->tg3_flags2 |=
3891 TG3_FLG2_PARALLEL_DETECT;
3892 tp->serdes_counter =
3893 SERDES_PARALLEL_DET_TIMEOUT;
3894 } else
3895 goto restart_autoneg;
3896 }
3897 }
3898 } else {
3899 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3900 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3901 }
3902
3903out:
3904 return current_link_up;
3905}
3906
3907static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3908{
3909 int current_link_up = 0;
3910
3911 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3912 goto out;
3913
3914 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3915 u32 txflags, rxflags;
3916 int i;
3917
3918 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3919 u32 local_adv = 0, remote_adv = 0;
3920
3921 if (txflags & ANEG_CFG_PS1)
3922 local_adv |= ADVERTISE_1000XPAUSE;
3923 if (txflags & ANEG_CFG_PS2)
3924 local_adv |= ADVERTISE_1000XPSE_ASYM;
3925
3926 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3927 remote_adv |= LPA_1000XPAUSE;
3928 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3929 remote_adv |= LPA_1000XPAUSE_ASYM;
3930
3931 tg3_setup_flow_control(tp, local_adv, remote_adv);
3932
3933 current_link_up = 1;
3934 }
3935 for (i = 0; i < 30; i++) {
3936 udelay(20);
3937 tw32_f(MAC_STATUS,
3938 (MAC_STATUS_SYNC_CHANGED |
3939 MAC_STATUS_CFG_CHANGED));
3940 udelay(40);
3941 if ((tr32(MAC_STATUS) &
3942 (MAC_STATUS_SYNC_CHANGED |
3943 MAC_STATUS_CFG_CHANGED)) == 0)
3944 break;
3945 }
3946
3947 mac_status = tr32(MAC_STATUS);
3948 if (current_link_up == 0 &&
3949 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3950 !(mac_status & MAC_STATUS_RCVD_CFG))
3951 current_link_up = 1;
3952 } else {
3953 tg3_setup_flow_control(tp, 0, 0);
3954
3955 /* Forcing 1000FD link up. */
3956 current_link_up = 1;
3957
3958 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3959 udelay(40);
3960
3961 tw32_f(MAC_MODE, tp->mac_mode);
3962 udelay(40);
3963 }
3964
3965out:
3966 return current_link_up;
3967}
3968
3969static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3970{
3971 u32 orig_pause_cfg;
3972 u16 orig_active_speed;
3973 u8 orig_active_duplex;
3974 u32 mac_status;
3975 int current_link_up;
3976 int i;
3977
3978 orig_pause_cfg = tp->link_config.active_flowctrl;
3979 orig_active_speed = tp->link_config.active_speed;
3980 orig_active_duplex = tp->link_config.active_duplex;
3981
3982 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3983 netif_carrier_ok(tp->dev) &&
3984 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3985 mac_status = tr32(MAC_STATUS);
3986 mac_status &= (MAC_STATUS_PCS_SYNCED |
3987 MAC_STATUS_SIGNAL_DET |
3988 MAC_STATUS_CFG_CHANGED |
3989 MAC_STATUS_RCVD_CFG);
3990 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3991 MAC_STATUS_SIGNAL_DET)) {
3992 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3993 MAC_STATUS_CFG_CHANGED));
3994 return 0;
3995 }
3996 }
3997
3998 tw32_f(MAC_TX_AUTO_NEG, 0);
3999
4000 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4001 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4002 tw32_f(MAC_MODE, tp->mac_mode);
4003 udelay(40);
4004
4005 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4006 tg3_init_bcm8002(tp);
4007
4008 /* Enable link change event even when serdes polling. */
4009 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4010 udelay(40);
4011
4012 current_link_up = 0;
4013 mac_status = tr32(MAC_STATUS);
4014
4015 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4016 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4017 else
4018 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4019
4020 tp->napi[0].hw_status->status =
4021 (SD_STATUS_UPDATED |
4022 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4023
4024 for (i = 0; i < 100; i++) {
4025 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4026 MAC_STATUS_CFG_CHANGED));
4027 udelay(5);
4028 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4029 MAC_STATUS_CFG_CHANGED |
4030 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4031 break;
4032 }
4033
4034 mac_status = tr32(MAC_STATUS);
4035 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4036 current_link_up = 0;
4037 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4038 tp->serdes_counter == 0) {
4039 tw32_f(MAC_MODE, (tp->mac_mode |
4040 MAC_MODE_SEND_CONFIGS));
4041 udelay(1);
4042 tw32_f(MAC_MODE, tp->mac_mode);
4043 }
4044 }
4045
4046 if (current_link_up == 1) {
4047 tp->link_config.active_speed = SPEED_1000;
4048 tp->link_config.active_duplex = DUPLEX_FULL;
4049 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4050 LED_CTRL_LNKLED_OVERRIDE |
4051 LED_CTRL_1000MBPS_ON));
4052 } else {
4053 tp->link_config.active_speed = SPEED_INVALID;
4054 tp->link_config.active_duplex = DUPLEX_INVALID;
4055 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4056 LED_CTRL_LNKLED_OVERRIDE |
4057 LED_CTRL_TRAFFIC_OVERRIDE));
4058 }
4059
4060 if (current_link_up != netif_carrier_ok(tp->dev)) {
4061 if (current_link_up)
4062 netif_carrier_on(tp->dev);
4063 else
4064 netif_carrier_off(tp->dev);
4065 tg3_link_report(tp);
4066 } else {
4067 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4068 if (orig_pause_cfg != now_pause_cfg ||
4069 orig_active_speed != tp->link_config.active_speed ||
4070 orig_active_duplex != tp->link_config.active_duplex)
4071 tg3_link_report(tp);
4072 }
4073
4074 return 0;
4075}
4076
4077static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4078{
4079 int current_link_up, err = 0;
4080 u32 bmsr, bmcr;
4081 u16 current_speed;
4082 u8 current_duplex;
4083 u32 local_adv, remote_adv;
4084
4085 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4086 tw32_f(MAC_MODE, tp->mac_mode);
4087 udelay(40);
4088
4089 tw32(MAC_EVENT, 0);
4090
4091 tw32_f(MAC_STATUS,
4092 (MAC_STATUS_SYNC_CHANGED |
4093 MAC_STATUS_CFG_CHANGED |
4094 MAC_STATUS_MI_COMPLETION |
4095 MAC_STATUS_LNKSTATE_CHANGED));
4096 udelay(40);
4097
4098 if (force_reset)
4099 tg3_phy_reset(tp);
4100
4101 current_link_up = 0;
4102 current_speed = SPEED_INVALID;
4103 current_duplex = DUPLEX_INVALID;
4104
4105 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4106 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4108 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4109 bmsr |= BMSR_LSTATUS;
4110 else
4111 bmsr &= ~BMSR_LSTATUS;
4112 }
4113
4114 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4115
4116 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4117 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4118 /* do nothing, just check for link up at the end */
4119 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4120 u32 adv, new_adv;
4121
4122 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4123 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4124 ADVERTISE_1000XPAUSE |
4125 ADVERTISE_1000XPSE_ASYM |
4126 ADVERTISE_SLCT);
4127
4128 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4129
4130 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4131 new_adv |= ADVERTISE_1000XHALF;
4132 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4133 new_adv |= ADVERTISE_1000XFULL;
4134
4135 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4136 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4137 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4138 tg3_writephy(tp, MII_BMCR, bmcr);
4139
4140 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4141 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4142 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4143
4144 return err;
4145 }
4146 } else {
4147 u32 new_bmcr;
4148
4149 bmcr &= ~BMCR_SPEED1000;
4150 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4151
4152 if (tp->link_config.duplex == DUPLEX_FULL)
4153 new_bmcr |= BMCR_FULLDPLX;
4154
4155 if (new_bmcr != bmcr) {
4156 /* BMCR_SPEED1000 is a reserved bit that needs
4157 * to be set on write.
4158 */
4159 new_bmcr |= BMCR_SPEED1000;
4160
4161 /* Force a linkdown */
4162 if (netif_carrier_ok(tp->dev)) {
4163 u32 adv;
4164
4165 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4166 adv &= ~(ADVERTISE_1000XFULL |
4167 ADVERTISE_1000XHALF |
4168 ADVERTISE_SLCT);
4169 tg3_writephy(tp, MII_ADVERTISE, adv);
4170 tg3_writephy(tp, MII_BMCR, bmcr |
4171 BMCR_ANRESTART |
4172 BMCR_ANENABLE);
4173 udelay(10);
4174 netif_carrier_off(tp->dev);
4175 }
4176 tg3_writephy(tp, MII_BMCR, new_bmcr);
4177 bmcr = new_bmcr;
4178 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4179 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4180 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4181 ASIC_REV_5714) {
4182 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4183 bmsr |= BMSR_LSTATUS;
4184 else
4185 bmsr &= ~BMSR_LSTATUS;
4186 }
4187 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4188 }
4189 }
4190
4191 if (bmsr & BMSR_LSTATUS) {
4192 current_speed = SPEED_1000;
4193 current_link_up = 1;
4194 if (bmcr & BMCR_FULLDPLX)
4195 current_duplex = DUPLEX_FULL;
4196 else
4197 current_duplex = DUPLEX_HALF;
4198
4199 local_adv = 0;
4200 remote_adv = 0;
4201
4202 if (bmcr & BMCR_ANENABLE) {
4203 u32 common;
4204
4205 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4206 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4207 common = local_adv & remote_adv;
4208 if (common & (ADVERTISE_1000XHALF |
4209 ADVERTISE_1000XFULL)) {
4210 if (common & ADVERTISE_1000XFULL)
4211 current_duplex = DUPLEX_FULL;
4212 else
4213 current_duplex = DUPLEX_HALF;
4214 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4215 /* Link is up via parallel detect */
4216 } else {
4217 current_link_up = 0;
4218 }
4219 }
4220 }
4221
4222 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4223 tg3_setup_flow_control(tp, local_adv, remote_adv);
4224
4225 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4226 if (tp->link_config.active_duplex == DUPLEX_HALF)
4227 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4228
4229 tw32_f(MAC_MODE, tp->mac_mode);
4230 udelay(40);
4231
4232 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4233
4234 tp->link_config.active_speed = current_speed;
4235 tp->link_config.active_duplex = current_duplex;
4236
4237 if (current_link_up != netif_carrier_ok(tp->dev)) {
4238 if (current_link_up)
4239 netif_carrier_on(tp->dev);
4240 else {
4241 netif_carrier_off(tp->dev);
4242 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4243 }
4244 tg3_link_report(tp);
4245 }
4246 return err;
4247}
4248
4249static void tg3_serdes_parallel_detect(struct tg3 *tp)
4250{
4251 if (tp->serdes_counter) {
4252 /* Give autoneg time to complete. */
4253 tp->serdes_counter--;
4254 return;
4255 }
4256
4257 if (!netif_carrier_ok(tp->dev) &&
4258 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4259 u32 bmcr;
4260
4261 tg3_readphy(tp, MII_BMCR, &bmcr);
4262 if (bmcr & BMCR_ANENABLE) {
4263 u32 phy1, phy2;
4264
4265 /* Select shadow register 0x1f */
4266 tg3_writephy(tp, 0x1c, 0x7c00);
4267 tg3_readphy(tp, 0x1c, &phy1);
4268
4269 /* Select expansion interrupt status register */
4270 tg3_writephy(tp, 0x17, 0x0f01);
4271 tg3_readphy(tp, 0x15, &phy2);
4272 tg3_readphy(tp, 0x15, &phy2);
4273
4274 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4275 /* We have signal detect and not receiving
4276 * config code words, link is up by parallel
4277 * detection.
4278 */
4279
4280 bmcr &= ~BMCR_ANENABLE;
4281 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4282 tg3_writephy(tp, MII_BMCR, bmcr);
4283 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4284 }
4285 }
4286 } else if (netif_carrier_ok(tp->dev) &&
4287 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4288 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4289 u32 phy2;
4290
4291 /* Select expansion interrupt status register */
4292 tg3_writephy(tp, 0x17, 0x0f01);
4293 tg3_readphy(tp, 0x15, &phy2);
4294 if (phy2 & 0x20) {
4295 u32 bmcr;
4296
4297 /* Config code words received, turn on autoneg. */
4298 tg3_readphy(tp, MII_BMCR, &bmcr);
4299 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4300
4301 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4302
4303 }
4304 }
4305}
4306
4307static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4308{
4309 int err;
4310
4311 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4312 err = tg3_setup_fiber_phy(tp, force_reset);
4313 else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4314 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4315 else
4316 err = tg3_setup_copper_phy(tp, force_reset);
4317
4318 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4319 u32 val, scale;
4320
4321 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4322 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4323 scale = 65;
4324 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4325 scale = 6;
4326 else
4327 scale = 12;
4328
4329 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4330 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4331 tw32(GRC_MISC_CFG, val);
4332 }
4333
4334 if (tp->link_config.active_speed == SPEED_1000 &&
4335 tp->link_config.active_duplex == DUPLEX_HALF)
4336 tw32(MAC_TX_LENGTHS,
4337 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4338 (6 << TX_LENGTHS_IPG_SHIFT) |
4339 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4340 else
4341 tw32(MAC_TX_LENGTHS,
4342 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4343 (6 << TX_LENGTHS_IPG_SHIFT) |
4344 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4345
4346 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4347 if (netif_carrier_ok(tp->dev)) {
4348 tw32(HOSTCC_STAT_COAL_TICKS,
4349 tp->coal.stats_block_coalesce_usecs);
4350 } else {
4351 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4352 }
4353 }
4354
4355 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4356 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4357 if (!netif_carrier_ok(tp->dev))
4358 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4359 tp->pwrmgmt_thresh;
4360 else
4361 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4362 tw32(PCIE_PWR_MGMT_THRESH, val);
4363 }
4364
4365 return err;
4366}
4367
4368/* This is called whenever we suspect that the system chipset is re-
4369 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4370 * is bogus tx completions. We try to recover by setting the
4371 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4372 * in the workqueue.
4373 */
4374static void tg3_tx_recover(struct tg3 *tp)
4375{
4376 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4377 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4378
4379 netdev_warn(tp->dev,
4380 "The system may be re-ordering memory-mapped I/O "
4381 "cycles to the network device, attempting to recover. "
4382 "Please report the problem to the driver maintainer "
4383 "and include system chipset information.\n");
4384
4385 spin_lock(&tp->lock);
4386 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4387 spin_unlock(&tp->lock);
4388}
4389
4390static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4391{
4392 smp_mb();
4393 return tnapi->tx_pending -
4394 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4395}
4396
4397/* Tigon3 never reports partial packet sends. So we do not
4398 * need special logic to handle SKBs that have not had all
4399 * of their frags sent yet, like SunGEM does.
4400 */
4401static void tg3_tx(struct tg3_napi *tnapi)
4402{
4403 struct tg3 *tp = tnapi->tp;
4404 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4405 u32 sw_idx = tnapi->tx_cons;
4406 struct netdev_queue *txq;
4407 int index = tnapi - tp->napi;
4408
4409 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4410 index--;
4411
4412 txq = netdev_get_tx_queue(tp->dev, index);
4413
4414 while (sw_idx != hw_idx) {
4415 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4416 struct sk_buff *skb = ri->skb;
4417 int i, tx_bug = 0;
4418
4419 if (unlikely(skb == NULL)) {
4420 tg3_tx_recover(tp);
4421 return;
4422 }
4423
4424 pci_unmap_single(tp->pdev,
4425 dma_unmap_addr(ri, mapping),
4426 skb_headlen(skb),
4427 PCI_DMA_TODEVICE);
4428
4429 ri->skb = NULL;
4430
4431 sw_idx = NEXT_TX(sw_idx);
4432
4433 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4434 ri = &tnapi->tx_buffers[sw_idx];
4435 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4436 tx_bug = 1;
4437
4438 pci_unmap_page(tp->pdev,
4439 dma_unmap_addr(ri, mapping),
4440 skb_shinfo(skb)->frags[i].size,
4441 PCI_DMA_TODEVICE);
4442 sw_idx = NEXT_TX(sw_idx);
4443 }
4444
4445 dev_kfree_skb(skb);
4446
4447 if (unlikely(tx_bug)) {
4448 tg3_tx_recover(tp);
4449 return;
4450 }
4451 }
4452
4453 tnapi->tx_cons = sw_idx;
4454
4455 /* Need to make the tx_cons update visible to tg3_start_xmit()
4456 * before checking for netif_queue_stopped(). Without the
4457 * memory barrier, there is a small possibility that tg3_start_xmit()
4458 * will miss it and cause the queue to be stopped forever.
4459 */
4460 smp_mb();
4461
4462 if (unlikely(netif_tx_queue_stopped(txq) &&
4463 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4464 __netif_tx_lock(txq, smp_processor_id());
4465 if (netif_tx_queue_stopped(txq) &&
4466 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4467 netif_tx_wake_queue(txq);
4468 __netif_tx_unlock(txq);
4469 }
4470}
4471
4472static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4473{
4474 if (!ri->skb)
4475 return;
4476
4477 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4478 map_sz, PCI_DMA_FROMDEVICE);
4479 dev_kfree_skb_any(ri->skb);
4480 ri->skb = NULL;
4481}
4482
4483/* Returns size of skb allocated or < 0 on error.
4484 *
4485 * We only need to fill in the address because the other members
4486 * of the RX descriptor are invariant, see tg3_init_rings.
4487 *
4488 * Note the purposeful assymetry of cpu vs. chip accesses. For
4489 * posting buffers we only dirty the first cache line of the RX
4490 * descriptor (containing the address). Whereas for the RX status
4491 * buffers the cpu only reads the last cacheline of the RX descriptor
4492 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4493 */
4494static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4495 u32 opaque_key, u32 dest_idx_unmasked)
4496{
4497 struct tg3_rx_buffer_desc *desc;
4498 struct ring_info *map, *src_map;
4499 struct sk_buff *skb;
4500 dma_addr_t mapping;
4501 int skb_size, dest_idx;
4502
4503 src_map = NULL;
4504 switch (opaque_key) {
4505 case RXD_OPAQUE_RING_STD:
4506 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4507 desc = &tpr->rx_std[dest_idx];
4508 map = &tpr->rx_std_buffers[dest_idx];
4509 skb_size = tp->rx_pkt_map_sz;
4510 break;
4511
4512 case RXD_OPAQUE_RING_JUMBO:
4513 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4514 desc = &tpr->rx_jmb[dest_idx].std;
4515 map = &tpr->rx_jmb_buffers[dest_idx];
4516 skb_size = TG3_RX_JMB_MAP_SZ;
4517 break;
4518
4519 default:
4520 return -EINVAL;
4521 }
4522
4523 /* Do not overwrite any of the map or rp information
4524 * until we are sure we can commit to a new buffer.
4525 *
4526 * Callers depend upon this behavior and assume that
4527 * we leave everything unchanged if we fail.
4528 */
4529 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4530 if (skb == NULL)
4531 return -ENOMEM;
4532
4533 skb_reserve(skb, tp->rx_offset);
4534
4535 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4536 PCI_DMA_FROMDEVICE);
4537 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4538 dev_kfree_skb(skb);
4539 return -EIO;
4540 }
4541
4542 map->skb = skb;
4543 dma_unmap_addr_set(map, mapping, mapping);
4544
4545 desc->addr_hi = ((u64)mapping >> 32);
4546 desc->addr_lo = ((u64)mapping & 0xffffffff);
4547
4548 return skb_size;
4549}
4550
4551/* We only need to move over in the address because the other
4552 * members of the RX descriptor are invariant. See notes above
4553 * tg3_alloc_rx_skb for full details.
4554 */
4555static void tg3_recycle_rx(struct tg3_napi *tnapi,
4556 struct tg3_rx_prodring_set *dpr,
4557 u32 opaque_key, int src_idx,
4558 u32 dest_idx_unmasked)
4559{
4560 struct tg3 *tp = tnapi->tp;
4561 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4562 struct ring_info *src_map, *dest_map;
4563 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4564 int dest_idx;
4565
4566 switch (opaque_key) {
4567 case RXD_OPAQUE_RING_STD:
4568 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4569 dest_desc = &dpr->rx_std[dest_idx];
4570 dest_map = &dpr->rx_std_buffers[dest_idx];
4571 src_desc = &spr->rx_std[src_idx];
4572 src_map = &spr->rx_std_buffers[src_idx];
4573 break;
4574
4575 case RXD_OPAQUE_RING_JUMBO:
4576 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4577 dest_desc = &dpr->rx_jmb[dest_idx].std;
4578 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4579 src_desc = &spr->rx_jmb[src_idx].std;
4580 src_map = &spr->rx_jmb_buffers[src_idx];
4581 break;
4582
4583 default:
4584 return;
4585 }
4586
4587 dest_map->skb = src_map->skb;
4588 dma_unmap_addr_set(dest_map, mapping,
4589 dma_unmap_addr(src_map, mapping));
4590 dest_desc->addr_hi = src_desc->addr_hi;
4591 dest_desc->addr_lo = src_desc->addr_lo;
4592
4593 /* Ensure that the update to the skb happens after the physical
4594 * addresses have been transferred to the new BD location.
4595 */
4596 smp_wmb();
4597
4598 src_map->skb = NULL;
4599}
4600
4601/* The RX ring scheme is composed of multiple rings which post fresh
4602 * buffers to the chip, and one special ring the chip uses to report
4603 * status back to the host.
4604 *
4605 * The special ring reports the status of received packets to the
4606 * host. The chip does not write into the original descriptor the
4607 * RX buffer was obtained from. The chip simply takes the original
4608 * descriptor as provided by the host, updates the status and length
4609 * field, then writes this into the next status ring entry.
4610 *
4611 * Each ring the host uses to post buffers to the chip is described
4612 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4613 * it is first placed into the on-chip ram. When the packet's length
4614 * is known, it walks down the TG3_BDINFO entries to select the ring.
4615 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4616 * which is within the range of the new packet's length is chosen.
4617 *
4618 * The "separate ring for rx status" scheme may sound queer, but it makes
4619 * sense from a cache coherency perspective. If only the host writes
4620 * to the buffer post rings, and only the chip writes to the rx status
4621 * rings, then cache lines never move beyond shared-modified state.
4622 * If both the host and chip were to write into the same ring, cache line
4623 * eviction could occur since both entities want it in an exclusive state.
4624 */
4625static int tg3_rx(struct tg3_napi *tnapi, int budget)
4626{
4627 struct tg3 *tp = tnapi->tp;
4628 u32 work_mask, rx_std_posted = 0;
4629 u32 std_prod_idx, jmb_prod_idx;
4630 u32 sw_idx = tnapi->rx_rcb_ptr;
4631 u16 hw_idx;
4632 int received;
4633 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4634
4635 hw_idx = *(tnapi->rx_rcb_prod_idx);
4636 /*
4637 * We need to order the read of hw_idx and the read of
4638 * the opaque cookie.
4639 */
4640 rmb();
4641 work_mask = 0;
4642 received = 0;
4643 std_prod_idx = tpr->rx_std_prod_idx;
4644 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4645 while (sw_idx != hw_idx && budget > 0) {
4646 struct ring_info *ri;
4647 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4648 unsigned int len;
4649 struct sk_buff *skb;
4650 dma_addr_t dma_addr;
4651 u32 opaque_key, desc_idx, *post_ptr;
4652 bool hw_vlan __maybe_unused = false;
4653 u16 vtag __maybe_unused = 0;
4654
4655 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4656 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4657 if (opaque_key == RXD_OPAQUE_RING_STD) {
4658 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4659 dma_addr = dma_unmap_addr(ri, mapping);
4660 skb = ri->skb;
4661 post_ptr = &std_prod_idx;
4662 rx_std_posted++;
4663 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4664 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4665 dma_addr = dma_unmap_addr(ri, mapping);
4666 skb = ri->skb;
4667 post_ptr = &jmb_prod_idx;
4668 } else
4669 goto next_pkt_nopost;
4670
4671 work_mask |= opaque_key;
4672
4673 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4674 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4675 drop_it:
4676 tg3_recycle_rx(tnapi, tpr, opaque_key,
4677 desc_idx, *post_ptr);
4678 drop_it_no_recycle:
4679 /* Other statistics kept track of by card. */
4680 tp->net_stats.rx_dropped++;
4681 goto next_pkt;
4682 }
4683
4684 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4685 ETH_FCS_LEN;
4686
4687 if (len > TG3_RX_COPY_THRESH(tp)) {
4688 int skb_size;
4689
4690 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4691 *post_ptr);
4692 if (skb_size < 0)
4693 goto drop_it;
4694
4695 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4696 PCI_DMA_FROMDEVICE);
4697
4698 /* Ensure that the update to the skb happens
4699 * after the usage of the old DMA mapping.
4700 */
4701 smp_wmb();
4702
4703 ri->skb = NULL;
4704
4705 skb_put(skb, len);
4706 } else {
4707 struct sk_buff *copy_skb;
4708
4709 tg3_recycle_rx(tnapi, tpr, opaque_key,
4710 desc_idx, *post_ptr);
4711
4712 copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4713 TG3_RAW_IP_ALIGN);
4714 if (copy_skb == NULL)
4715 goto drop_it_no_recycle;
4716
4717 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4718 skb_put(copy_skb, len);
4719 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4720 skb_copy_from_linear_data(skb, copy_skb->data, len);
4721 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4722
4723 /* We'll reuse the original ring buffer. */
4724 skb = copy_skb;
4725 }
4726
4727 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4728 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4729 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4730 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4731 skb->ip_summed = CHECKSUM_UNNECESSARY;
4732 else
4733 skb->ip_summed = CHECKSUM_NONE;
4734
4735 skb->protocol = eth_type_trans(skb, tp->dev);
4736
4737 if (len > (tp->dev->mtu + ETH_HLEN) &&
4738 skb->protocol != htons(ETH_P_8021Q)) {
4739 dev_kfree_skb(skb);
4740 goto next_pkt;
4741 }
4742
4743 if (desc->type_flags & RXD_FLAG_VLAN &&
4744 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4745 vtag = desc->err_vlan & RXD_VLAN_MASK;
4746#if TG3_VLAN_TAG_USED
4747 if (tp->vlgrp)
4748 hw_vlan = true;
4749 else
4750#endif
4751 {
4752 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4753 __skb_push(skb, VLAN_HLEN);
4754
4755 memmove(ve, skb->data + VLAN_HLEN,
4756 ETH_ALEN * 2);
4757 ve->h_vlan_proto = htons(ETH_P_8021Q);
4758 ve->h_vlan_TCI = htons(vtag);
4759 }
4760 }
4761
4762#if TG3_VLAN_TAG_USED
4763 if (hw_vlan)
4764 vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4765 else
4766#endif
4767 napi_gro_receive(&tnapi->napi, skb);
4768
4769 received++;
4770 budget--;
4771
4772next_pkt:
4773 (*post_ptr)++;
4774
4775 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4776 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4777 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4778 tpr->rx_std_prod_idx);
4779 work_mask &= ~RXD_OPAQUE_RING_STD;
4780 rx_std_posted = 0;
4781 }
4782next_pkt_nopost:
4783 sw_idx++;
4784 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4785
4786 /* Refresh hw_idx to see if there is new work */
4787 if (sw_idx == hw_idx) {
4788 hw_idx = *(tnapi->rx_rcb_prod_idx);
4789 rmb();
4790 }
4791 }
4792
4793 /* ACK the status ring. */
4794 tnapi->rx_rcb_ptr = sw_idx;
4795 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4796
4797 /* Refill RX ring(s). */
4798 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4799 if (work_mask & RXD_OPAQUE_RING_STD) {
4800 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4801 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4802 tpr->rx_std_prod_idx);
4803 }
4804 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4805 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4806 TG3_RX_JUMBO_RING_SIZE;
4807 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4808 tpr->rx_jmb_prod_idx);
4809 }
4810 mmiowb();
4811 } else if (work_mask) {
4812 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4813 * updated before the producer indices can be updated.
4814 */
4815 smp_wmb();
4816
4817 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4818 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4819
4820 if (tnapi != &tp->napi[1])
4821 napi_schedule(&tp->napi[1].napi);
4822 }
4823
4824 return received;
4825}
4826
4827static void tg3_poll_link(struct tg3 *tp)
4828{
4829 /* handle link change and other phy events */
4830 if (!(tp->tg3_flags &
4831 (TG3_FLAG_USE_LINKCHG_REG |
4832 TG3_FLAG_POLL_SERDES))) {
4833 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4834
4835 if (sblk->status & SD_STATUS_LINK_CHG) {
4836 sblk->status = SD_STATUS_UPDATED |
4837 (sblk->status & ~SD_STATUS_LINK_CHG);
4838 spin_lock(&tp->lock);
4839 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4840 tw32_f(MAC_STATUS,
4841 (MAC_STATUS_SYNC_CHANGED |
4842 MAC_STATUS_CFG_CHANGED |
4843 MAC_STATUS_MI_COMPLETION |
4844 MAC_STATUS_LNKSTATE_CHANGED));
4845 udelay(40);
4846 } else
4847 tg3_setup_phy(tp, 0);
4848 spin_unlock(&tp->lock);
4849 }
4850 }
4851}
4852
4853static int tg3_rx_prodring_xfer(struct tg3 *tp,
4854 struct tg3_rx_prodring_set *dpr,
4855 struct tg3_rx_prodring_set *spr)
4856{
4857 u32 si, di, cpycnt, src_prod_idx;
4858 int i, err = 0;
4859
4860 while (1) {
4861 src_prod_idx = spr->rx_std_prod_idx;
4862
4863 /* Make sure updates to the rx_std_buffers[] entries and the
4864 * standard producer index are seen in the correct order.
4865 */
4866 smp_rmb();
4867
4868 if (spr->rx_std_cons_idx == src_prod_idx)
4869 break;
4870
4871 if (spr->rx_std_cons_idx < src_prod_idx)
4872 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4873 else
4874 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4875
4876 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4877
4878 si = spr->rx_std_cons_idx;
4879 di = dpr->rx_std_prod_idx;
4880
4881 for (i = di; i < di + cpycnt; i++) {
4882 if (dpr->rx_std_buffers[i].skb) {
4883 cpycnt = i - di;
4884 err = -ENOSPC;
4885 break;
4886 }
4887 }
4888
4889 if (!cpycnt)
4890 break;
4891
4892 /* Ensure that updates to the rx_std_buffers ring and the
4893 * shadowed hardware producer ring from tg3_recycle_skb() are
4894 * ordered correctly WRT the skb check above.
4895 */
4896 smp_rmb();
4897
4898 memcpy(&dpr->rx_std_buffers[di],
4899 &spr->rx_std_buffers[si],
4900 cpycnt * sizeof(struct ring_info));
4901
4902 for (i = 0; i < cpycnt; i++, di++, si++) {
4903 struct tg3_rx_buffer_desc *sbd, *dbd;
4904 sbd = &spr->rx_std[si];
4905 dbd = &dpr->rx_std[di];
4906 dbd->addr_hi = sbd->addr_hi;
4907 dbd->addr_lo = sbd->addr_lo;
4908 }
4909
4910 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4911 TG3_RX_RING_SIZE;
4912 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4913 TG3_RX_RING_SIZE;
4914 }
4915
4916 while (1) {
4917 src_prod_idx = spr->rx_jmb_prod_idx;
4918
4919 /* Make sure updates to the rx_jmb_buffers[] entries and
4920 * the jumbo producer index are seen in the correct order.
4921 */
4922 smp_rmb();
4923
4924 if (spr->rx_jmb_cons_idx == src_prod_idx)
4925 break;
4926
4927 if (spr->rx_jmb_cons_idx < src_prod_idx)
4928 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4929 else
4930 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4931
4932 cpycnt = min(cpycnt,
4933 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4934
4935 si = spr->rx_jmb_cons_idx;
4936 di = dpr->rx_jmb_prod_idx;
4937
4938 for (i = di; i < di + cpycnt; i++) {
4939 if (dpr->rx_jmb_buffers[i].skb) {
4940 cpycnt = i - di;
4941 err = -ENOSPC;
4942 break;
4943 }
4944 }
4945
4946 if (!cpycnt)
4947 break;
4948
4949 /* Ensure that updates to the rx_jmb_buffers ring and the
4950 * shadowed hardware producer ring from tg3_recycle_skb() are
4951 * ordered correctly WRT the skb check above.
4952 */
4953 smp_rmb();
4954
4955 memcpy(&dpr->rx_jmb_buffers[di],
4956 &spr->rx_jmb_buffers[si],
4957 cpycnt * sizeof(struct ring_info));
4958
4959 for (i = 0; i < cpycnt; i++, di++, si++) {
4960 struct tg3_rx_buffer_desc *sbd, *dbd;
4961 sbd = &spr->rx_jmb[si].std;
4962 dbd = &dpr->rx_jmb[di].std;
4963 dbd->addr_hi = sbd->addr_hi;
4964 dbd->addr_lo = sbd->addr_lo;
4965 }
4966
4967 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4968 TG3_RX_JUMBO_RING_SIZE;
4969 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4970 TG3_RX_JUMBO_RING_SIZE;
4971 }
4972
4973 return err;
4974}
4975
4976static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4977{
4978 struct tg3 *tp = tnapi->tp;
4979
4980 /* run TX completion thread */
4981 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4982 tg3_tx(tnapi);
4983 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4984 return work_done;
4985 }
4986
4987 /* run RX thread, within the bounds set by NAPI.
4988 * All RX "locking" is done by ensuring outside
4989 * code synchronizes with tg3->napi.poll()
4990 */
4991 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4992 work_done += tg3_rx(tnapi, budget - work_done);
4993
4994 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4995 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4996 int i, err = 0;
4997 u32 std_prod_idx = dpr->rx_std_prod_idx;
4998 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4999
5000 for (i = 1; i < tp->irq_cnt; i++)
5001 err |= tg3_rx_prodring_xfer(tp, dpr,
5002 tp->napi[i].prodring);
5003
5004 wmb();
5005
5006 if (std_prod_idx != dpr->rx_std_prod_idx)
5007 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5008 dpr->rx_std_prod_idx);
5009
5010 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5011 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5012 dpr->rx_jmb_prod_idx);
5013
5014 mmiowb();
5015
5016 if (err)
5017 tw32_f(HOSTCC_MODE, tp->coal_now);
5018 }
5019
5020 return work_done;
5021}
5022
5023static int tg3_poll_msix(struct napi_struct *napi, int budget)
5024{
5025 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5026 struct tg3 *tp = tnapi->tp;
5027 int work_done = 0;
5028 struct tg3_hw_status *sblk = tnapi->hw_status;
5029
5030 while (1) {
5031 work_done = tg3_poll_work(tnapi, work_done, budget);
5032
5033 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5034 goto tx_recovery;
5035
5036 if (unlikely(work_done >= budget))
5037 break;
5038
5039 /* tp->last_tag is used in tg3_int_reenable() below
5040 * to tell the hw how much work has been processed,
5041 * so we must read it before checking for more work.
5042 */
5043 tnapi->last_tag = sblk->status_tag;
5044 tnapi->last_irq_tag = tnapi->last_tag;
5045 rmb();
5046
5047 /* check for RX/TX work to do */
5048 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5049 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5050 napi_complete(napi);
5051 /* Reenable interrupts. */
5052 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5053 mmiowb();
5054 break;
5055 }
5056 }
5057
5058 return work_done;
5059
5060tx_recovery:
5061 /* work_done is guaranteed to be less than budget. */
5062 napi_complete(napi);
5063 schedule_work(&tp->reset_task);
5064 return work_done;
5065}
5066
5067static int tg3_poll(struct napi_struct *napi, int budget)
5068{
5069 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5070 struct tg3 *tp = tnapi->tp;
5071 int work_done = 0;
5072 struct tg3_hw_status *sblk = tnapi->hw_status;
5073
5074 while (1) {
5075 tg3_poll_link(tp);
5076
5077 work_done = tg3_poll_work(tnapi, work_done, budget);
5078
5079 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5080 goto tx_recovery;
5081
5082 if (unlikely(work_done >= budget))
5083 break;
5084
5085 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5086 /* tp->last_tag is used in tg3_int_reenable() below
5087 * to tell the hw how much work has been processed,
5088 * so we must read it before checking for more work.
5089 */
5090 tnapi->last_tag = sblk->status_tag;
5091 tnapi->last_irq_tag = tnapi->last_tag;
5092 rmb();
5093 } else
5094 sblk->status &= ~SD_STATUS_UPDATED;
5095
5096 if (likely(!tg3_has_work(tnapi))) {
5097 napi_complete(napi);
5098 tg3_int_reenable(tnapi);
5099 break;
5100 }
5101 }
5102
5103 return work_done;
5104
5105tx_recovery:
5106 /* work_done is guaranteed to be less than budget. */
5107 napi_complete(napi);
5108 schedule_work(&tp->reset_task);
5109 return work_done;
5110}
5111
5112static void tg3_irq_quiesce(struct tg3 *tp)
5113{
5114 int i;
5115
5116 BUG_ON(tp->irq_sync);
5117
5118 tp->irq_sync = 1;
5119 smp_mb();
5120
5121 for (i = 0; i < tp->irq_cnt; i++)
5122 synchronize_irq(tp->napi[i].irq_vec);
5123}
5124
5125static inline int tg3_irq_sync(struct tg3 *tp)
5126{
5127 return tp->irq_sync;
5128}
5129
5130/* Fully shutdown all tg3 driver activity elsewhere in the system.
5131 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5132 * with as well. Most of the time, this is not necessary except when
5133 * shutting down the device.
5134 */
5135static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5136{
5137 spin_lock_bh(&tp->lock);
5138 if (irq_sync)
5139 tg3_irq_quiesce(tp);
5140}
5141
5142static inline void tg3_full_unlock(struct tg3 *tp)
5143{
5144 spin_unlock_bh(&tp->lock);
5145}
5146
5147/* One-shot MSI handler - Chip automatically disables interrupt
5148 * after sending MSI so driver doesn't have to do it.
5149 */
5150static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5151{
5152 struct tg3_napi *tnapi = dev_id;
5153 struct tg3 *tp = tnapi->tp;
5154
5155 prefetch(tnapi->hw_status);
5156 if (tnapi->rx_rcb)
5157 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5158
5159 if (likely(!tg3_irq_sync(tp)))
5160 napi_schedule(&tnapi->napi);
5161
5162 return IRQ_HANDLED;
5163}
5164
5165/* MSI ISR - No need to check for interrupt sharing and no need to
5166 * flush status block and interrupt mailbox. PCI ordering rules
5167 * guarantee that MSI will arrive after the status block.
5168 */
5169static irqreturn_t tg3_msi(int irq, void *dev_id)
5170{
5171 struct tg3_napi *tnapi = dev_id;
5172 struct tg3 *tp = tnapi->tp;
5173
5174 prefetch(tnapi->hw_status);
5175 if (tnapi->rx_rcb)
5176 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5177 /*
5178 * Writing any value to intr-mbox-0 clears PCI INTA# and
5179 * chip-internal interrupt pending events.
5180 * Writing non-zero to intr-mbox-0 additional tells the
5181 * NIC to stop sending us irqs, engaging "in-intr-handler"
5182 * event coalescing.
5183 */
5184 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5185 if (likely(!tg3_irq_sync(tp)))
5186 napi_schedule(&tnapi->napi);
5187
5188 return IRQ_RETVAL(1);
5189}
5190
5191static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5192{
5193 struct tg3_napi *tnapi = dev_id;
5194 struct tg3 *tp = tnapi->tp;
5195 struct tg3_hw_status *sblk = tnapi->hw_status;
5196 unsigned int handled = 1;
5197
5198 /* In INTx mode, it is possible for the interrupt to arrive at
5199 * the CPU before the status block posted prior to the interrupt.
5200 * Reading the PCI State register will confirm whether the
5201 * interrupt is ours and will flush the status block.
5202 */
5203 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5204 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5205 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5206 handled = 0;
5207 goto out;
5208 }
5209 }
5210
5211 /*
5212 * Writing any value to intr-mbox-0 clears PCI INTA# and
5213 * chip-internal interrupt pending events.
5214 * Writing non-zero to intr-mbox-0 additional tells the
5215 * NIC to stop sending us irqs, engaging "in-intr-handler"
5216 * event coalescing.
5217 *
5218 * Flush the mailbox to de-assert the IRQ immediately to prevent
5219 * spurious interrupts. The flush impacts performance but
5220 * excessive spurious interrupts can be worse in some cases.
5221 */
5222 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5223 if (tg3_irq_sync(tp))
5224 goto out;
5225 sblk->status &= ~SD_STATUS_UPDATED;
5226 if (likely(tg3_has_work(tnapi))) {
5227 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5228 napi_schedule(&tnapi->napi);
5229 } else {
5230 /* No work, shared interrupt perhaps? re-enable
5231 * interrupts, and flush that PCI write
5232 */
5233 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5234 0x00000000);
5235 }
5236out:
5237 return IRQ_RETVAL(handled);
5238}
5239
5240static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5241{
5242 struct tg3_napi *tnapi = dev_id;
5243 struct tg3 *tp = tnapi->tp;
5244 struct tg3_hw_status *sblk = tnapi->hw_status;
5245 unsigned int handled = 1;
5246
5247 /* In INTx mode, it is possible for the interrupt to arrive at
5248 * the CPU before the status block posted prior to the interrupt.
5249 * Reading the PCI State register will confirm whether the
5250 * interrupt is ours and will flush the status block.
5251 */
5252 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5253 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5254 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5255 handled = 0;
5256 goto out;
5257 }
5258 }
5259
5260 /*
5261 * writing any value to intr-mbox-0 clears PCI INTA# and
5262 * chip-internal interrupt pending events.
5263 * writing non-zero to intr-mbox-0 additional tells the
5264 * NIC to stop sending us irqs, engaging "in-intr-handler"
5265 * event coalescing.
5266 *
5267 * Flush the mailbox to de-assert the IRQ immediately to prevent
5268 * spurious interrupts. The flush impacts performance but
5269 * excessive spurious interrupts can be worse in some cases.
5270 */
5271 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5272
5273 /*
5274 * In a shared interrupt configuration, sometimes other devices'
5275 * interrupts will scream. We record the current status tag here
5276 * so that the above check can report that the screaming interrupts
5277 * are unhandled. Eventually they will be silenced.
5278 */
5279 tnapi->last_irq_tag = sblk->status_tag;
5280
5281 if (tg3_irq_sync(tp))
5282 goto out;
5283
5284 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5285
5286 napi_schedule(&tnapi->napi);
5287
5288out:
5289 return IRQ_RETVAL(handled);
5290}
5291
5292/* ISR for interrupt test */
5293static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5294{
5295 struct tg3_napi *tnapi = dev_id;
5296 struct tg3 *tp = tnapi->tp;
5297 struct tg3_hw_status *sblk = tnapi->hw_status;
5298
5299 if ((sblk->status & SD_STATUS_UPDATED) ||
5300 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5301 tg3_disable_ints(tp);
5302 return IRQ_RETVAL(1);
5303 }
5304 return IRQ_RETVAL(0);
5305}
5306
5307static int tg3_init_hw(struct tg3 *, int);
5308static int tg3_halt(struct tg3 *, int, int);
5309
5310/* Restart hardware after configuration changes, self-test, etc.
5311 * Invoked with tp->lock held.
5312 */
5313static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5314 __releases(tp->lock)
5315 __acquires(tp->lock)
5316{
5317 int err;
5318
5319 err = tg3_init_hw(tp, reset_phy);
5320 if (err) {
5321 netdev_err(tp->dev,
5322 "Failed to re-initialize device, aborting\n");
5323 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5324 tg3_full_unlock(tp);
5325 del_timer_sync(&tp->timer);
5326 tp->irq_sync = 0;
5327 tg3_napi_enable(tp);
5328 dev_close(tp->dev);
5329 tg3_full_lock(tp, 0);
5330 }
5331 return err;
5332}
5333
5334#ifdef CONFIG_NET_POLL_CONTROLLER
5335static void tg3_poll_controller(struct net_device *dev)
5336{
5337 int i;
5338 struct tg3 *tp = netdev_priv(dev);
5339
5340 for (i = 0; i < tp->irq_cnt; i++)
5341 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5342}
5343#endif
5344
5345static void tg3_reset_task(struct work_struct *work)
5346{
5347 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5348 int err;
5349 unsigned int restart_timer;
5350
5351 tg3_full_lock(tp, 0);
5352
5353 if (!netif_running(tp->dev)) {
5354 tg3_full_unlock(tp);
5355 return;
5356 }
5357
5358 tg3_full_unlock(tp);
5359
5360 tg3_phy_stop(tp);
5361
5362 tg3_netif_stop(tp);
5363
5364 tg3_full_lock(tp, 1);
5365
5366 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5367 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5368
5369 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5370 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5371 tp->write32_rx_mbox = tg3_write_flush_reg32;
5372 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5373 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5374 }
5375
5376 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5377 err = tg3_init_hw(tp, 1);
5378 if (err)
5379 goto out;
5380
5381 tg3_netif_start(tp);
5382
5383 if (restart_timer)
5384 mod_timer(&tp->timer, jiffies + 1);
5385
5386out:
5387 tg3_full_unlock(tp);
5388
5389 if (!err)
5390 tg3_phy_start(tp);
5391}
5392
5393static void tg3_dump_short_state(struct tg3 *tp)
5394{
5395 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5396 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5397 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5398 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5399}
5400
5401static void tg3_tx_timeout(struct net_device *dev)
5402{
5403 struct tg3 *tp = netdev_priv(dev);
5404
5405 if (netif_msg_tx_err(tp)) {
5406 netdev_err(dev, "transmit timed out, resetting\n");
5407 tg3_dump_short_state(tp);
5408 }
5409
5410 schedule_work(&tp->reset_task);
5411}
5412
5413/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5414static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5415{
5416 u32 base = (u32) mapping & 0xffffffff;
5417
5418 return ((base > 0xffffdcc0) &&
5419 (base + len + 8 < base));
5420}
5421
5422/* Test for DMA addresses > 40-bit */
5423static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5424 int len)
5425{
5426#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5427 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5428 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5429 return 0;
5430#else
5431 return 0;
5432#endif
5433}
5434
5435static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5436
5437/* Workaround 4GB and 40-bit hardware DMA bugs. */
5438static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5439 struct sk_buff *skb, u32 last_plus_one,
5440 u32 *start, u32 base_flags, u32 mss)
5441{
5442 struct tg3 *tp = tnapi->tp;
5443 struct sk_buff *new_skb;
5444 dma_addr_t new_addr = 0;
5445 u32 entry = *start;
5446 int i, ret = 0;
5447
5448 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5449 new_skb = skb_copy(skb, GFP_ATOMIC);
5450 else {
5451 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5452
5453 new_skb = skb_copy_expand(skb,
5454 skb_headroom(skb) + more_headroom,
5455 skb_tailroom(skb), GFP_ATOMIC);
5456 }
5457
5458 if (!new_skb) {
5459 ret = -1;
5460 } else {
5461 /* New SKB is guaranteed to be linear. */
5462 entry = *start;
5463 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5464 PCI_DMA_TODEVICE);
5465 /* Make sure the mapping succeeded */
5466 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5467 ret = -1;
5468 dev_kfree_skb(new_skb);
5469 new_skb = NULL;
5470
5471 /* Make sure new skb does not cross any 4G boundaries.
5472 * Drop the packet if it does.
5473 */
5474 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5475 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5476 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5477 PCI_DMA_TODEVICE);
5478 ret = -1;
5479 dev_kfree_skb(new_skb);
5480 new_skb = NULL;
5481 } else {
5482 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5483 base_flags, 1 | (mss << 1));
5484 *start = NEXT_TX(entry);
5485 }
5486 }
5487
5488 /* Now clean up the sw ring entries. */
5489 i = 0;
5490 while (entry != last_plus_one) {
5491 int len;
5492
5493 if (i == 0)
5494 len = skb_headlen(skb);
5495 else
5496 len = skb_shinfo(skb)->frags[i-1].size;
5497
5498 pci_unmap_single(tp->pdev,
5499 dma_unmap_addr(&tnapi->tx_buffers[entry],
5500 mapping),
5501 len, PCI_DMA_TODEVICE);
5502 if (i == 0) {
5503 tnapi->tx_buffers[entry].skb = new_skb;
5504 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5505 new_addr);
5506 } else {
5507 tnapi->tx_buffers[entry].skb = NULL;
5508 }
5509 entry = NEXT_TX(entry);
5510 i++;
5511 }
5512
5513 dev_kfree_skb(skb);
5514
5515 return ret;
5516}
5517
5518static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5519 dma_addr_t mapping, int len, u32 flags,
5520 u32 mss_and_is_end)
5521{
5522 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5523 int is_end = (mss_and_is_end & 0x1);
5524 u32 mss = (mss_and_is_end >> 1);
5525 u32 vlan_tag = 0;
5526
5527 if (is_end)
5528 flags |= TXD_FLAG_END;
5529 if (flags & TXD_FLAG_VLAN) {
5530 vlan_tag = flags >> 16;
5531 flags &= 0xffff;
5532 }
5533 vlan_tag |= (mss << TXD_MSS_SHIFT);
5534
5535 txd->addr_hi = ((u64) mapping >> 32);
5536 txd->addr_lo = ((u64) mapping & 0xffffffff);
5537 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5538 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5539}
5540
5541/* hard_start_xmit for devices that don't have any bugs and
5542 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5543 */
5544static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5545 struct net_device *dev)
5546{
5547 struct tg3 *tp = netdev_priv(dev);
5548 u32 len, entry, base_flags, mss;
5549 dma_addr_t mapping;
5550 struct tg3_napi *tnapi;
5551 struct netdev_queue *txq;
5552 unsigned int i, last;
5553
5554 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5555 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5556 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5557 tnapi++;
5558
5559 /* We are running in BH disabled context with netif_tx_lock
5560 * and TX reclaim runs via tp->napi.poll inside of a software
5561 * interrupt. Furthermore, IRQ processing runs lockless so we have
5562 * no IRQ context deadlocks to worry about either. Rejoice!
5563 */
5564 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5565 if (!netif_tx_queue_stopped(txq)) {
5566 netif_tx_stop_queue(txq);
5567
5568 /* This is a hard error, log it. */
5569 netdev_err(dev,
5570 "BUG! Tx Ring full when queue awake!\n");
5571 }
5572 return NETDEV_TX_BUSY;
5573 }
5574
5575 entry = tnapi->tx_prod;
5576 base_flags = 0;
5577 mss = skb_shinfo(skb)->gso_size;
5578 if (mss) {
5579 int tcp_opt_len, ip_tcp_len;
5580 u32 hdrlen;
5581
5582 if (skb_header_cloned(skb) &&
5583 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5584 dev_kfree_skb(skb);
5585 goto out_unlock;
5586 }
5587
5588 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5589 hdrlen = skb_headlen(skb) - ETH_HLEN;
5590 else {
5591 struct iphdr *iph = ip_hdr(skb);
5592
5593 tcp_opt_len = tcp_optlen(skb);
5594 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5595
5596 iph->check = 0;
5597 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5598 hdrlen = ip_tcp_len + tcp_opt_len;
5599 }
5600
5601 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5602 mss |= (hdrlen & 0xc) << 12;
5603 if (hdrlen & 0x10)
5604 base_flags |= 0x00000010;
5605 base_flags |= (hdrlen & 0x3e0) << 5;
5606 } else
5607 mss |= hdrlen << 9;
5608
5609 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5610 TXD_FLAG_CPU_POST_DMA);
5611
5612 tcp_hdr(skb)->check = 0;
5613
5614 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5615 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5616 }
5617
5618#if TG3_VLAN_TAG_USED
5619 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5620 base_flags |= (TXD_FLAG_VLAN |
5621 (vlan_tx_tag_get(skb) << 16));
5622#endif
5623
5624 len = skb_headlen(skb);
5625
5626 /* Queue skb data, a.k.a. the main skb fragment. */
5627 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5628 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5629 dev_kfree_skb(skb);
5630 goto out_unlock;
5631 }
5632
5633 tnapi->tx_buffers[entry].skb = skb;
5634 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5635
5636 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5637 !mss && skb->len > ETH_DATA_LEN)
5638 base_flags |= TXD_FLAG_JMB_PKT;
5639
5640 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5641 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5642
5643 entry = NEXT_TX(entry);
5644
5645 /* Now loop through additional data fragments, and queue them. */
5646 if (skb_shinfo(skb)->nr_frags > 0) {
5647 last = skb_shinfo(skb)->nr_frags - 1;
5648 for (i = 0; i <= last; i++) {
5649 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5650
5651 len = frag->size;
5652 mapping = pci_map_page(tp->pdev,
5653 frag->page,
5654 frag->page_offset,
5655 len, PCI_DMA_TODEVICE);
5656 if (pci_dma_mapping_error(tp->pdev, mapping))
5657 goto dma_error;
5658
5659 tnapi->tx_buffers[entry].skb = NULL;
5660 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5661 mapping);
5662
5663 tg3_set_txd(tnapi, entry, mapping, len,
5664 base_flags, (i == last) | (mss << 1));
5665
5666 entry = NEXT_TX(entry);
5667 }
5668 }
5669
5670 /* Packets are ready, update Tx producer idx local and on card. */
5671 tw32_tx_mbox(tnapi->prodmbox, entry);
5672
5673 tnapi->tx_prod = entry;
5674 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5675 netif_tx_stop_queue(txq);
5676 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5677 netif_tx_wake_queue(txq);
5678 }
5679
5680out_unlock:
5681 mmiowb();
5682
5683 return NETDEV_TX_OK;
5684
5685dma_error:
5686 last = i;
5687 entry = tnapi->tx_prod;
5688 tnapi->tx_buffers[entry].skb = NULL;
5689 pci_unmap_single(tp->pdev,
5690 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5691 skb_headlen(skb),
5692 PCI_DMA_TODEVICE);
5693 for (i = 0; i <= last; i++) {
5694 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5695 entry = NEXT_TX(entry);
5696
5697 pci_unmap_page(tp->pdev,
5698 dma_unmap_addr(&tnapi->tx_buffers[entry],
5699 mapping),
5700 frag->size, PCI_DMA_TODEVICE);
5701 }
5702
5703 dev_kfree_skb(skb);
5704 return NETDEV_TX_OK;
5705}
5706
5707static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5708 struct net_device *);
5709
5710/* Use GSO to workaround a rare TSO bug that may be triggered when the
5711 * TSO header is greater than 80 bytes.
5712 */
5713static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5714{
5715 struct sk_buff *segs, *nskb;
5716 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5717
5718 /* Estimate the number of fragments in the worst case */
5719 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5720 netif_stop_queue(tp->dev);
5721 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5722 return NETDEV_TX_BUSY;
5723
5724 netif_wake_queue(tp->dev);
5725 }
5726
5727 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5728 if (IS_ERR(segs))
5729 goto tg3_tso_bug_end;
5730
5731 do {
5732 nskb = segs;
5733 segs = segs->next;
5734 nskb->next = NULL;
5735 tg3_start_xmit_dma_bug(nskb, tp->dev);
5736 } while (segs);
5737
5738tg3_tso_bug_end:
5739 dev_kfree_skb(skb);
5740
5741 return NETDEV_TX_OK;
5742}
5743
5744/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5745 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5746 */
5747static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5748 struct net_device *dev)
5749{
5750 struct tg3 *tp = netdev_priv(dev);
5751 u32 len, entry, base_flags, mss;
5752 int would_hit_hwbug;
5753 dma_addr_t mapping;
5754 struct tg3_napi *tnapi;
5755 struct netdev_queue *txq;
5756 unsigned int i, last;
5757
5758 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5759 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5760 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5761 tnapi++;
5762
5763 /* We are running in BH disabled context with netif_tx_lock
5764 * and TX reclaim runs via tp->napi.poll inside of a software
5765 * interrupt. Furthermore, IRQ processing runs lockless so we have
5766 * no IRQ context deadlocks to worry about either. Rejoice!
5767 */
5768 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5769 if (!netif_tx_queue_stopped(txq)) {
5770 netif_tx_stop_queue(txq);
5771
5772 /* This is a hard error, log it. */
5773 netdev_err(dev,
5774 "BUG! Tx Ring full when queue awake!\n");
5775 }
5776 return NETDEV_TX_BUSY;
5777 }
5778
5779 entry = tnapi->tx_prod;
5780 base_flags = 0;
5781 if (skb->ip_summed == CHECKSUM_PARTIAL)
5782 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5783
5784 mss = skb_shinfo(skb)->gso_size;
5785 if (mss) {
5786 struct iphdr *iph;
5787 u32 tcp_opt_len, hdr_len;
5788
5789 if (skb_header_cloned(skb) &&
5790 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5791 dev_kfree_skb(skb);
5792 goto out_unlock;
5793 }
5794
5795 iph = ip_hdr(skb);
5796 tcp_opt_len = tcp_optlen(skb);
5797
5798 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5799 hdr_len = skb_headlen(skb) - ETH_HLEN;
5800 } else {
5801 u32 ip_tcp_len;
5802
5803 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5804 hdr_len = ip_tcp_len + tcp_opt_len;
5805
5806 iph->check = 0;
5807 iph->tot_len = htons(mss + hdr_len);
5808 }
5809
5810 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5811 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5812 return tg3_tso_bug(tp, skb);
5813
5814 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5815 TXD_FLAG_CPU_POST_DMA);
5816
5817 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5818 tcp_hdr(skb)->check = 0;
5819 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5820 } else
5821 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5822 iph->daddr, 0,
5823 IPPROTO_TCP,
5824 0);
5825
5826 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5827 mss |= (hdr_len & 0xc) << 12;
5828 if (hdr_len & 0x10)
5829 base_flags |= 0x00000010;
5830 base_flags |= (hdr_len & 0x3e0) << 5;
5831 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5832 mss |= hdr_len << 9;
5833 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5835 if (tcp_opt_len || iph->ihl > 5) {
5836 int tsflags;
5837
5838 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5839 mss |= (tsflags << 11);
5840 }
5841 } else {
5842 if (tcp_opt_len || iph->ihl > 5) {
5843 int tsflags;
5844
5845 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5846 base_flags |= tsflags << 12;
5847 }
5848 }
5849 }
5850#if TG3_VLAN_TAG_USED
5851 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5852 base_flags |= (TXD_FLAG_VLAN |
5853 (vlan_tx_tag_get(skb) << 16));
5854#endif
5855
5856 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5857 !mss && skb->len > ETH_DATA_LEN)
5858 base_flags |= TXD_FLAG_JMB_PKT;
5859
5860 len = skb_headlen(skb);
5861
5862 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5863 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5864 dev_kfree_skb(skb);
5865 goto out_unlock;
5866 }
5867
5868 tnapi->tx_buffers[entry].skb = skb;
5869 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5870
5871 would_hit_hwbug = 0;
5872
5873 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5874 would_hit_hwbug = 1;
5875
5876 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5877 tg3_4g_overflow_test(mapping, len))
5878 would_hit_hwbug = 1;
5879
5880 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5881 tg3_40bit_overflow_test(tp, mapping, len))
5882 would_hit_hwbug = 1;
5883
5884 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5885 would_hit_hwbug = 1;
5886
5887 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5888 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5889
5890 entry = NEXT_TX(entry);
5891
5892 /* Now loop through additional data fragments, and queue them. */
5893 if (skb_shinfo(skb)->nr_frags > 0) {
5894 last = skb_shinfo(skb)->nr_frags - 1;
5895 for (i = 0; i <= last; i++) {
5896 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5897
5898 len = frag->size;
5899 mapping = pci_map_page(tp->pdev,
5900 frag->page,
5901 frag->page_offset,
5902 len, PCI_DMA_TODEVICE);
5903
5904 tnapi->tx_buffers[entry].skb = NULL;
5905 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5906 mapping);
5907 if (pci_dma_mapping_error(tp->pdev, mapping))
5908 goto dma_error;
5909
5910 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5911 len <= 8)
5912 would_hit_hwbug = 1;
5913
5914 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5915 tg3_4g_overflow_test(mapping, len))
5916 would_hit_hwbug = 1;
5917
5918 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5919 tg3_40bit_overflow_test(tp, mapping, len))
5920 would_hit_hwbug = 1;
5921
5922 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5923 tg3_set_txd(tnapi, entry, mapping, len,
5924 base_flags, (i == last)|(mss << 1));
5925 else
5926 tg3_set_txd(tnapi, entry, mapping, len,
5927 base_flags, (i == last));
5928
5929 entry = NEXT_TX(entry);
5930 }
5931 }
5932
5933 if (would_hit_hwbug) {
5934 u32 last_plus_one = entry;
5935 u32 start;
5936
5937 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5938 start &= (TG3_TX_RING_SIZE - 1);
5939
5940 /* If the workaround fails due to memory/mapping
5941 * failure, silently drop this packet.
5942 */
5943 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5944 &start, base_flags, mss))
5945 goto out_unlock;
5946
5947 entry = start;
5948 }
5949
5950 /* Packets are ready, update Tx producer idx local and on card. */
5951 tw32_tx_mbox(tnapi->prodmbox, entry);
5952
5953 tnapi->tx_prod = entry;
5954 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5955 netif_tx_stop_queue(txq);
5956 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5957 netif_tx_wake_queue(txq);
5958 }
5959
5960out_unlock:
5961 mmiowb();
5962
5963 return NETDEV_TX_OK;
5964
5965dma_error:
5966 last = i;
5967 entry = tnapi->tx_prod;
5968 tnapi->tx_buffers[entry].skb = NULL;
5969 pci_unmap_single(tp->pdev,
5970 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5971 skb_headlen(skb),
5972 PCI_DMA_TODEVICE);
5973 for (i = 0; i <= last; i++) {
5974 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5975 entry = NEXT_TX(entry);
5976
5977 pci_unmap_page(tp->pdev,
5978 dma_unmap_addr(&tnapi->tx_buffers[entry],
5979 mapping),
5980 frag->size, PCI_DMA_TODEVICE);
5981 }
5982
5983 dev_kfree_skb(skb);
5984 return NETDEV_TX_OK;
5985}
5986
5987static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5988 int new_mtu)
5989{
5990 dev->mtu = new_mtu;
5991
5992 if (new_mtu > ETH_DATA_LEN) {
5993 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5994 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5995 ethtool_op_set_tso(dev, 0);
5996 } else {
5997 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5998 }
5999 } else {
6000 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6001 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6002 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6003 }
6004}
6005
6006static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6007{
6008 struct tg3 *tp = netdev_priv(dev);
6009 int err;
6010
6011 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6012 return -EINVAL;
6013
6014 if (!netif_running(dev)) {
6015 /* We'll just catch it later when the
6016 * device is up'd.
6017 */
6018 tg3_set_mtu(dev, tp, new_mtu);
6019 return 0;
6020 }
6021
6022 tg3_phy_stop(tp);
6023
6024 tg3_netif_stop(tp);
6025
6026 tg3_full_lock(tp, 1);
6027
6028 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6029
6030 tg3_set_mtu(dev, tp, new_mtu);
6031
6032 err = tg3_restart_hw(tp, 0);
6033
6034 if (!err)
6035 tg3_netif_start(tp);
6036
6037 tg3_full_unlock(tp);
6038
6039 if (!err)
6040 tg3_phy_start(tp);
6041
6042 return err;
6043}
6044
6045static void tg3_rx_prodring_free(struct tg3 *tp,
6046 struct tg3_rx_prodring_set *tpr)
6047{
6048 int i;
6049
6050 if (tpr != &tp->prodring[0]) {
6051 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6052 i = (i + 1) % TG3_RX_RING_SIZE)
6053 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6054 tp->rx_pkt_map_sz);
6055
6056 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6057 for (i = tpr->rx_jmb_cons_idx;
6058 i != tpr->rx_jmb_prod_idx;
6059 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6060 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6061 TG3_RX_JMB_MAP_SZ);
6062 }
6063 }
6064
6065 return;
6066 }
6067
6068 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6069 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6070 tp->rx_pkt_map_sz);
6071
6072 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6073 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6074 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6075 TG3_RX_JMB_MAP_SZ);
6076 }
6077}
6078
6079/* Initialize rx rings for packet processing.
6080 *
6081 * The chip has been shut down and the driver detached from
6082 * the networking, so no interrupts or new tx packets will
6083 * end up in the driver. tp->{tx,}lock are held and thus
6084 * we may not sleep.
6085 */
6086static int tg3_rx_prodring_alloc(struct tg3 *tp,
6087 struct tg3_rx_prodring_set *tpr)
6088{
6089 u32 i, rx_pkt_dma_sz;
6090
6091 tpr->rx_std_cons_idx = 0;
6092 tpr->rx_std_prod_idx = 0;
6093 tpr->rx_jmb_cons_idx = 0;
6094 tpr->rx_jmb_prod_idx = 0;
6095
6096 if (tpr != &tp->prodring[0]) {
6097 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6098 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6099 memset(&tpr->rx_jmb_buffers[0], 0,
6100 TG3_RX_JMB_BUFF_RING_SIZE);
6101 goto done;
6102 }
6103
6104 /* Zero out all descriptors. */
6105 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6106
6107 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6108 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6109 tp->dev->mtu > ETH_DATA_LEN)
6110 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6111 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6112
6113 /* Initialize invariants of the rings, we only set this
6114 * stuff once. This works because the card does not
6115 * write into the rx buffer posting rings.
6116 */
6117 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6118 struct tg3_rx_buffer_desc *rxd;
6119
6120 rxd = &tpr->rx_std[i];
6121 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6122 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6123 rxd->opaque = (RXD_OPAQUE_RING_STD |
6124 (i << RXD_OPAQUE_INDEX_SHIFT));
6125 }
6126
6127 /* Now allocate fresh SKBs for each rx ring. */
6128 for (i = 0; i < tp->rx_pending; i++) {
6129 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6130 netdev_warn(tp->dev,
6131 "Using a smaller RX standard ring. Only "
6132 "%d out of %d buffers were allocated "
6133 "successfully\n", i, tp->rx_pending);
6134 if (i == 0)
6135 goto initfail;
6136 tp->rx_pending = i;
6137 break;
6138 }
6139 }
6140
6141 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6142 goto done;
6143
6144 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6145
6146 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6147 goto done;
6148
6149 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6150 struct tg3_rx_buffer_desc *rxd;
6151
6152 rxd = &tpr->rx_jmb[i].std;
6153 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6154 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6155 RXD_FLAG_JUMBO;
6156 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6157 (i << RXD_OPAQUE_INDEX_SHIFT));
6158 }
6159
6160 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6161 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6162 netdev_warn(tp->dev,
6163 "Using a smaller RX jumbo ring. Only %d "
6164 "out of %d buffers were allocated "
6165 "successfully\n", i, tp->rx_jumbo_pending);
6166 if (i == 0)
6167 goto initfail;
6168 tp->rx_jumbo_pending = i;
6169 break;
6170 }
6171 }
6172
6173done:
6174 return 0;
6175
6176initfail:
6177 tg3_rx_prodring_free(tp, tpr);
6178 return -ENOMEM;
6179}
6180
6181static void tg3_rx_prodring_fini(struct tg3 *tp,
6182 struct tg3_rx_prodring_set *tpr)
6183{
6184 kfree(tpr->rx_std_buffers);
6185 tpr->rx_std_buffers = NULL;
6186 kfree(tpr->rx_jmb_buffers);
6187 tpr->rx_jmb_buffers = NULL;
6188 if (tpr->rx_std) {
6189 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6190 tpr->rx_std, tpr->rx_std_mapping);
6191 tpr->rx_std = NULL;
6192 }
6193 if (tpr->rx_jmb) {
6194 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6195 tpr->rx_jmb, tpr->rx_jmb_mapping);
6196 tpr->rx_jmb = NULL;
6197 }
6198}
6199
6200static int tg3_rx_prodring_init(struct tg3 *tp,
6201 struct tg3_rx_prodring_set *tpr)
6202{
6203 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6204 if (!tpr->rx_std_buffers)
6205 return -ENOMEM;
6206
6207 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6208 &tpr->rx_std_mapping);
6209 if (!tpr->rx_std)
6210 goto err_out;
6211
6212 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6213 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6214 GFP_KERNEL);
6215 if (!tpr->rx_jmb_buffers)
6216 goto err_out;
6217
6218 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6219 TG3_RX_JUMBO_RING_BYTES,
6220 &tpr->rx_jmb_mapping);
6221 if (!tpr->rx_jmb)
6222 goto err_out;
6223 }
6224
6225 return 0;
6226
6227err_out:
6228 tg3_rx_prodring_fini(tp, tpr);
6229 return -ENOMEM;
6230}
6231
6232/* Free up pending packets in all rx/tx rings.
6233 *
6234 * The chip has been shut down and the driver detached from
6235 * the networking, so no interrupts or new tx packets will
6236 * end up in the driver. tp->{tx,}lock is not held and we are not
6237 * in an interrupt context and thus may sleep.
6238 */
6239static void tg3_free_rings(struct tg3 *tp)
6240{
6241 int i, j;
6242
6243 for (j = 0; j < tp->irq_cnt; j++) {
6244 struct tg3_napi *tnapi = &tp->napi[j];
6245
6246 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6247
6248 if (!tnapi->tx_buffers)
6249 continue;
6250
6251 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6252 struct ring_info *txp;
6253 struct sk_buff *skb;
6254 unsigned int k;
6255
6256 txp = &tnapi->tx_buffers[i];
6257 skb = txp->skb;
6258
6259 if (skb == NULL) {
6260 i++;
6261 continue;
6262 }
6263
6264 pci_unmap_single(tp->pdev,
6265 dma_unmap_addr(txp, mapping),
6266 skb_headlen(skb),
6267 PCI_DMA_TODEVICE);
6268 txp->skb = NULL;
6269
6270 i++;
6271
6272 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6273 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6274 pci_unmap_page(tp->pdev,
6275 dma_unmap_addr(txp, mapping),
6276 skb_shinfo(skb)->frags[k].size,
6277 PCI_DMA_TODEVICE);
6278 i++;
6279 }
6280
6281 dev_kfree_skb_any(skb);
6282 }
6283 }
6284}
6285
6286/* Initialize tx/rx rings for packet processing.
6287 *
6288 * The chip has been shut down and the driver detached from
6289 * the networking, so no interrupts or new tx packets will
6290 * end up in the driver. tp->{tx,}lock are held and thus
6291 * we may not sleep.
6292 */
6293static int tg3_init_rings(struct tg3 *tp)
6294{
6295 int i;
6296
6297 /* Free up all the SKBs. */
6298 tg3_free_rings(tp);
6299
6300 for (i = 0; i < tp->irq_cnt; i++) {
6301 struct tg3_napi *tnapi = &tp->napi[i];
6302
6303 tnapi->last_tag = 0;
6304 tnapi->last_irq_tag = 0;
6305 tnapi->hw_status->status = 0;
6306 tnapi->hw_status->status_tag = 0;
6307 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6308
6309 tnapi->tx_prod = 0;
6310 tnapi->tx_cons = 0;
6311 if (tnapi->tx_ring)
6312 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6313
6314 tnapi->rx_rcb_ptr = 0;
6315 if (tnapi->rx_rcb)
6316 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6317
6318 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6319 tg3_free_rings(tp);
6320 return -ENOMEM;
6321 }
6322 }
6323
6324 return 0;
6325}
6326
6327/*
6328 * Must not be invoked with interrupt sources disabled and
6329 * the hardware shutdown down.
6330 */
6331static void tg3_free_consistent(struct tg3 *tp)
6332{
6333 int i;
6334
6335 for (i = 0; i < tp->irq_cnt; i++) {
6336 struct tg3_napi *tnapi = &tp->napi[i];
6337
6338 if (tnapi->tx_ring) {
6339 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6340 tnapi->tx_ring, tnapi->tx_desc_mapping);
6341 tnapi->tx_ring = NULL;
6342 }
6343
6344 kfree(tnapi->tx_buffers);
6345 tnapi->tx_buffers = NULL;
6346
6347 if (tnapi->rx_rcb) {
6348 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6349 tnapi->rx_rcb,
6350 tnapi->rx_rcb_mapping);
6351 tnapi->rx_rcb = NULL;
6352 }
6353
6354 if (tnapi->hw_status) {
6355 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6356 tnapi->hw_status,
6357 tnapi->status_mapping);
6358 tnapi->hw_status = NULL;
6359 }
6360 }
6361
6362 if (tp->hw_stats) {
6363 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6364 tp->hw_stats, tp->stats_mapping);
6365 tp->hw_stats = NULL;
6366 }
6367
6368 for (i = 0; i < tp->irq_cnt; i++)
6369 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6370}
6371
6372/*
6373 * Must not be invoked with interrupt sources disabled and
6374 * the hardware shutdown down. Can sleep.
6375 */
6376static int tg3_alloc_consistent(struct tg3 *tp)
6377{
6378 int i;
6379
6380 for (i = 0; i < tp->irq_cnt; i++) {
6381 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6382 goto err_out;
6383 }
6384
6385 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6386 sizeof(struct tg3_hw_stats),
6387 &tp->stats_mapping);
6388 if (!tp->hw_stats)
6389 goto err_out;
6390
6391 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6392
6393 for (i = 0; i < tp->irq_cnt; i++) {
6394 struct tg3_napi *tnapi = &tp->napi[i];
6395 struct tg3_hw_status *sblk;
6396
6397 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6398 TG3_HW_STATUS_SIZE,
6399 &tnapi->status_mapping);
6400 if (!tnapi->hw_status)
6401 goto err_out;
6402
6403 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6404 sblk = tnapi->hw_status;
6405
6406 /* If multivector TSS is enabled, vector 0 does not handle
6407 * tx interrupts. Don't allocate any resources for it.
6408 */
6409 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6410 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6411 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6412 TG3_TX_RING_SIZE,
6413 GFP_KERNEL);
6414 if (!tnapi->tx_buffers)
6415 goto err_out;
6416
6417 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6418 TG3_TX_RING_BYTES,
6419 &tnapi->tx_desc_mapping);
6420 if (!tnapi->tx_ring)
6421 goto err_out;
6422 }
6423
6424 /*
6425 * When RSS is enabled, the status block format changes
6426 * slightly. The "rx_jumbo_consumer", "reserved",
6427 * and "rx_mini_consumer" members get mapped to the
6428 * other three rx return ring producer indexes.
6429 */
6430 switch (i) {
6431 default:
6432 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6433 break;
6434 case 2:
6435 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6436 break;
6437 case 3:
6438 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6439 break;
6440 case 4:
6441 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6442 break;
6443 }
6444
6445 tnapi->prodring = &tp->prodring[i];
6446
6447 /*
6448 * If multivector RSS is enabled, vector 0 does not handle
6449 * rx or tx interrupts. Don't allocate any resources for it.
6450 */
6451 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6452 continue;
6453
6454 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6455 TG3_RX_RCB_RING_BYTES(tp),
6456 &tnapi->rx_rcb_mapping);
6457 if (!tnapi->rx_rcb)
6458 goto err_out;
6459
6460 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6461 }
6462
6463 return 0;
6464
6465err_out:
6466 tg3_free_consistent(tp);
6467 return -ENOMEM;
6468}
6469
6470#define MAX_WAIT_CNT 1000
6471
6472/* To stop a block, clear the enable bit and poll till it
6473 * clears. tp->lock is held.
6474 */
6475static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6476{
6477 unsigned int i;
6478 u32 val;
6479
6480 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6481 switch (ofs) {
6482 case RCVLSC_MODE:
6483 case DMAC_MODE:
6484 case MBFREE_MODE:
6485 case BUFMGR_MODE:
6486 case MEMARB_MODE:
6487 /* We can't enable/disable these bits of the
6488 * 5705/5750, just say success.
6489 */
6490 return 0;
6491
6492 default:
6493 break;
6494 }
6495 }
6496
6497 val = tr32(ofs);
6498 val &= ~enable_bit;
6499 tw32_f(ofs, val);
6500
6501 for (i = 0; i < MAX_WAIT_CNT; i++) {
6502 udelay(100);
6503 val = tr32(ofs);
6504 if ((val & enable_bit) == 0)
6505 break;
6506 }
6507
6508 if (i == MAX_WAIT_CNT && !silent) {
6509 dev_err(&tp->pdev->dev,
6510 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6511 ofs, enable_bit);
6512 return -ENODEV;
6513 }
6514
6515 return 0;
6516}
6517
6518/* tp->lock is held. */
6519static int tg3_abort_hw(struct tg3 *tp, int silent)
6520{
6521 int i, err;
6522
6523 tg3_disable_ints(tp);
6524
6525 tp->rx_mode &= ~RX_MODE_ENABLE;
6526 tw32_f(MAC_RX_MODE, tp->rx_mode);
6527 udelay(10);
6528
6529 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6530 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6531 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6532 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6533 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6534 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6535
6536 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6537 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6538 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6539 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6540 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6541 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6542 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6543
6544 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6545 tw32_f(MAC_MODE, tp->mac_mode);
6546 udelay(40);
6547
6548 tp->tx_mode &= ~TX_MODE_ENABLE;
6549 tw32_f(MAC_TX_MODE, tp->tx_mode);
6550
6551 for (i = 0; i < MAX_WAIT_CNT; i++) {
6552 udelay(100);
6553 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6554 break;
6555 }
6556 if (i >= MAX_WAIT_CNT) {
6557 dev_err(&tp->pdev->dev,
6558 "%s timed out, TX_MODE_ENABLE will not clear "
6559 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6560 err |= -ENODEV;
6561 }
6562
6563 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6564 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6565 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6566
6567 tw32(FTQ_RESET, 0xffffffff);
6568 tw32(FTQ_RESET, 0x00000000);
6569
6570 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6571 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6572
6573 for (i = 0; i < tp->irq_cnt; i++) {
6574 struct tg3_napi *tnapi = &tp->napi[i];
6575 if (tnapi->hw_status)
6576 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6577 }
6578 if (tp->hw_stats)
6579 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6580
6581 return err;
6582}
6583
6584static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6585{
6586 int i;
6587 u32 apedata;
6588
6589 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6590 if (apedata != APE_SEG_SIG_MAGIC)
6591 return;
6592
6593 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6594 if (!(apedata & APE_FW_STATUS_READY))
6595 return;
6596
6597 /* Wait for up to 1 millisecond for APE to service previous event. */
6598 for (i = 0; i < 10; i++) {
6599 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6600 return;
6601
6602 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6603
6604 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6605 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6606 event | APE_EVENT_STATUS_EVENT_PENDING);
6607
6608 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6609
6610 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6611 break;
6612
6613 udelay(100);
6614 }
6615
6616 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6617 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6618}
6619
6620static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6621{
6622 u32 event;
6623 u32 apedata;
6624
6625 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6626 return;
6627
6628 switch (kind) {
6629 case RESET_KIND_INIT:
6630 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6631 APE_HOST_SEG_SIG_MAGIC);
6632 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6633 APE_HOST_SEG_LEN_MAGIC);
6634 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6635 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6636 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6637 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6638 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6639 APE_HOST_BEHAV_NO_PHYLOCK);
6640
6641 event = APE_EVENT_STATUS_STATE_START;
6642 break;
6643 case RESET_KIND_SHUTDOWN:
6644 /* With the interface we are currently using,
6645 * APE does not track driver state. Wiping
6646 * out the HOST SEGMENT SIGNATURE forces
6647 * the APE to assume OS absent status.
6648 */
6649 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6650
6651 event = APE_EVENT_STATUS_STATE_UNLOAD;
6652 break;
6653 case RESET_KIND_SUSPEND:
6654 event = APE_EVENT_STATUS_STATE_SUSPEND;
6655 break;
6656 default:
6657 return;
6658 }
6659
6660 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6661
6662 tg3_ape_send_event(tp, event);
6663}
6664
6665/* tp->lock is held. */
6666static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6667{
6668 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6669 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6670
6671 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6672 switch (kind) {
6673 case RESET_KIND_INIT:
6674 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6675 DRV_STATE_START);
6676 break;
6677
6678 case RESET_KIND_SHUTDOWN:
6679 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6680 DRV_STATE_UNLOAD);
6681 break;
6682
6683 case RESET_KIND_SUSPEND:
6684 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6685 DRV_STATE_SUSPEND);
6686 break;
6687
6688 default:
6689 break;
6690 }
6691 }
6692
6693 if (kind == RESET_KIND_INIT ||
6694 kind == RESET_KIND_SUSPEND)
6695 tg3_ape_driver_state_change(tp, kind);
6696}
6697
6698/* tp->lock is held. */
6699static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6700{
6701 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6702 switch (kind) {
6703 case RESET_KIND_INIT:
6704 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6705 DRV_STATE_START_DONE);
6706 break;
6707
6708 case RESET_KIND_SHUTDOWN:
6709 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6710 DRV_STATE_UNLOAD_DONE);
6711 break;
6712
6713 default:
6714 break;
6715 }
6716 }
6717
6718 if (kind == RESET_KIND_SHUTDOWN)
6719 tg3_ape_driver_state_change(tp, kind);
6720}
6721
6722/* tp->lock is held. */
6723static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6724{
6725 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6726 switch (kind) {
6727 case RESET_KIND_INIT:
6728 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6729 DRV_STATE_START);
6730 break;
6731
6732 case RESET_KIND_SHUTDOWN:
6733 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6734 DRV_STATE_UNLOAD);
6735 break;
6736
6737 case RESET_KIND_SUSPEND:
6738 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6739 DRV_STATE_SUSPEND);
6740 break;
6741
6742 default:
6743 break;
6744 }
6745 }
6746}
6747
6748static int tg3_poll_fw(struct tg3 *tp)
6749{
6750 int i;
6751 u32 val;
6752
6753 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6754 /* Wait up to 20ms for init done. */
6755 for (i = 0; i < 200; i++) {
6756 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6757 return 0;
6758 udelay(100);
6759 }
6760 return -ENODEV;
6761 }
6762
6763 /* Wait for firmware initialization to complete. */
6764 for (i = 0; i < 100000; i++) {
6765 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6766 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6767 break;
6768 udelay(10);
6769 }
6770
6771 /* Chip might not be fitted with firmware. Some Sun onboard
6772 * parts are configured like that. So don't signal the timeout
6773 * of the above loop as an error, but do report the lack of
6774 * running firmware once.
6775 */
6776 if (i >= 100000 &&
6777 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6778 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6779
6780 netdev_info(tp->dev, "No firmware running\n");
6781 }
6782
6783 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6784 /* The 57765 A0 needs a little more
6785 * time to do some important work.
6786 */
6787 mdelay(10);
6788 }
6789
6790 return 0;
6791}
6792
6793/* Save PCI command register before chip reset */
6794static void tg3_save_pci_state(struct tg3 *tp)
6795{
6796 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6797}
6798
6799/* Restore PCI state after chip reset */
6800static void tg3_restore_pci_state(struct tg3 *tp)
6801{
6802 u32 val;
6803
6804 /* Re-enable indirect register accesses. */
6805 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6806 tp->misc_host_ctrl);
6807
6808 /* Set MAX PCI retry to zero. */
6809 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6810 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6811 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6812 val |= PCISTATE_RETRY_SAME_DMA;
6813 /* Allow reads and writes to the APE register and memory space. */
6814 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6815 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6816 PCISTATE_ALLOW_APE_SHMEM_WR |
6817 PCISTATE_ALLOW_APE_PSPACE_WR;
6818 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6819
6820 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6821
6822 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6823 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6824 pcie_set_readrq(tp->pdev, 4096);
6825 else {
6826 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6827 tp->pci_cacheline_sz);
6828 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6829 tp->pci_lat_timer);
6830 }
6831 }
6832
6833 /* Make sure PCI-X relaxed ordering bit is clear. */
6834 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6835 u16 pcix_cmd;
6836
6837 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6838 &pcix_cmd);
6839 pcix_cmd &= ~PCI_X_CMD_ERO;
6840 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6841 pcix_cmd);
6842 }
6843
6844 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6845
6846 /* Chip reset on 5780 will reset MSI enable bit,
6847 * so need to restore it.
6848 */
6849 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6850 u16 ctrl;
6851
6852 pci_read_config_word(tp->pdev,
6853 tp->msi_cap + PCI_MSI_FLAGS,
6854 &ctrl);
6855 pci_write_config_word(tp->pdev,
6856 tp->msi_cap + PCI_MSI_FLAGS,
6857 ctrl | PCI_MSI_FLAGS_ENABLE);
6858 val = tr32(MSGINT_MODE);
6859 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6860 }
6861 }
6862}
6863
6864static void tg3_stop_fw(struct tg3 *);
6865
6866/* tp->lock is held. */
6867static int tg3_chip_reset(struct tg3 *tp)
6868{
6869 u32 val;
6870 void (*write_op)(struct tg3 *, u32, u32);
6871 int i, err;
6872
6873 tg3_nvram_lock(tp);
6874
6875 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6876
6877 /* No matching tg3_nvram_unlock() after this because
6878 * chip reset below will undo the nvram lock.
6879 */
6880 tp->nvram_lock_cnt = 0;
6881
6882 /* GRC_MISC_CFG core clock reset will clear the memory
6883 * enable bit in PCI register 4 and the MSI enable bit
6884 * on some chips, so we save relevant registers here.
6885 */
6886 tg3_save_pci_state(tp);
6887
6888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6889 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6890 tw32(GRC_FASTBOOT_PC, 0);
6891
6892 /*
6893 * We must avoid the readl() that normally takes place.
6894 * It locks machines, causes machine checks, and other
6895 * fun things. So, temporarily disable the 5701
6896 * hardware workaround, while we do the reset.
6897 */
6898 write_op = tp->write32;
6899 if (write_op == tg3_write_flush_reg32)
6900 tp->write32 = tg3_write32;
6901
6902 /* Prevent the irq handler from reading or writing PCI registers
6903 * during chip reset when the memory enable bit in the PCI command
6904 * register may be cleared. The chip does not generate interrupt
6905 * at this time, but the irq handler may still be called due to irq
6906 * sharing or irqpoll.
6907 */
6908 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6909 for (i = 0; i < tp->irq_cnt; i++) {
6910 struct tg3_napi *tnapi = &tp->napi[i];
6911 if (tnapi->hw_status) {
6912 tnapi->hw_status->status = 0;
6913 tnapi->hw_status->status_tag = 0;
6914 }
6915 tnapi->last_tag = 0;
6916 tnapi->last_irq_tag = 0;
6917 }
6918 smp_mb();
6919
6920 for (i = 0; i < tp->irq_cnt; i++)
6921 synchronize_irq(tp->napi[i].irq_vec);
6922
6923 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6924 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6925 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6926 }
6927
6928 /* do the reset */
6929 val = GRC_MISC_CFG_CORECLK_RESET;
6930
6931 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6932 if (tr32(0x7e2c) == 0x60) {
6933 tw32(0x7e2c, 0x20);
6934 }
6935 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6936 tw32(GRC_MISC_CFG, (1 << 29));
6937 val |= (1 << 29);
6938 }
6939 }
6940
6941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6942 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6943 tw32(GRC_VCPU_EXT_CTRL,
6944 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6945 }
6946
6947 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6948 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6949 tw32(GRC_MISC_CFG, val);
6950
6951 /* restore 5701 hardware bug workaround write method */
6952 tp->write32 = write_op;
6953
6954 /* Unfortunately, we have to delay before the PCI read back.
6955 * Some 575X chips even will not respond to a PCI cfg access
6956 * when the reset command is given to the chip.
6957 *
6958 * How do these hardware designers expect things to work
6959 * properly if the PCI write is posted for a long period
6960 * of time? It is always necessary to have some method by
6961 * which a register read back can occur to push the write
6962 * out which does the reset.
6963 *
6964 * For most tg3 variants the trick below was working.
6965 * Ho hum...
6966 */
6967 udelay(120);
6968
6969 /* Flush PCI posted writes. The normal MMIO registers
6970 * are inaccessible at this time so this is the only
6971 * way to make this reliably (actually, this is no longer
6972 * the case, see above). I tried to use indirect
6973 * register read/write but this upset some 5701 variants.
6974 */
6975 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6976
6977 udelay(120);
6978
6979 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6980 u16 val16;
6981
6982 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6983 int i;
6984 u32 cfg_val;
6985
6986 /* Wait for link training to complete. */
6987 for (i = 0; i < 5000; i++)
6988 udelay(100);
6989
6990 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6991 pci_write_config_dword(tp->pdev, 0xc4,
6992 cfg_val | (1 << 15));
6993 }
6994
6995 /* Clear the "no snoop" and "relaxed ordering" bits. */
6996 pci_read_config_word(tp->pdev,
6997 tp->pcie_cap + PCI_EXP_DEVCTL,
6998 &val16);
6999 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7000 PCI_EXP_DEVCTL_NOSNOOP_EN);
7001 /*
7002 * Older PCIe devices only support the 128 byte
7003 * MPS setting. Enforce the restriction.
7004 */
7005 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7006 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7007 pci_write_config_word(tp->pdev,
7008 tp->pcie_cap + PCI_EXP_DEVCTL,
7009 val16);
7010
7011 pcie_set_readrq(tp->pdev, 4096);
7012
7013 /* Clear error status */
7014 pci_write_config_word(tp->pdev,
7015 tp->pcie_cap + PCI_EXP_DEVSTA,
7016 PCI_EXP_DEVSTA_CED |
7017 PCI_EXP_DEVSTA_NFED |
7018 PCI_EXP_DEVSTA_FED |
7019 PCI_EXP_DEVSTA_URD);
7020 }
7021
7022 tg3_restore_pci_state(tp);
7023
7024 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7025
7026 val = 0;
7027 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7028 val = tr32(MEMARB_MODE);
7029 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7030
7031 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7032 tg3_stop_fw(tp);
7033 tw32(0x5000, 0x400);
7034 }
7035
7036 tw32(GRC_MODE, tp->grc_mode);
7037
7038 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7039 val = tr32(0xc4);
7040
7041 tw32(0xc4, val | (1 << 15));
7042 }
7043
7044 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7046 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7047 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7048 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7049 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7050 }
7051
7052 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7053 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7054 tw32_f(MAC_MODE, tp->mac_mode);
7055 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7056 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7057 tw32_f(MAC_MODE, tp->mac_mode);
7058 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7059 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7060 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7061 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7062 tw32_f(MAC_MODE, tp->mac_mode);
7063 } else
7064 tw32_f(MAC_MODE, 0);
7065 udelay(40);
7066
7067 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7068
7069 err = tg3_poll_fw(tp);
7070 if (err)
7071 return err;
7072
7073 tg3_mdio_start(tp);
7074
7075 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7076 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7077 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7078 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7079 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
7080 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7081 val = tr32(0x7c00);
7082
7083 tw32(0x7c00, val | (1 << 25));
7084 }
7085
7086 /* Reprobe ASF enable state. */
7087 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7088 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7089 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7090 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7091 u32 nic_cfg;
7092
7093 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7094 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7095 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7096 tp->last_event_jiffies = jiffies;
7097 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7098 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7099 }
7100 }
7101
7102 return 0;
7103}
7104
7105/* tp->lock is held. */
7106static void tg3_stop_fw(struct tg3 *tp)
7107{
7108 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7109 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7110 /* Wait for RX cpu to ACK the previous event. */
7111 tg3_wait_for_event_ack(tp);
7112
7113 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7114
7115 tg3_generate_fw_event(tp);
7116
7117 /* Wait for RX cpu to ACK this event. */
7118 tg3_wait_for_event_ack(tp);
7119 }
7120}
7121
7122/* tp->lock is held. */
7123static int tg3_halt(struct tg3 *tp, int kind, int silent)
7124{
7125 int err;
7126
7127 tg3_stop_fw(tp);
7128
7129 tg3_write_sig_pre_reset(tp, kind);
7130
7131 tg3_abort_hw(tp, silent);
7132 err = tg3_chip_reset(tp);
7133
7134 __tg3_set_mac_addr(tp, 0);
7135
7136 tg3_write_sig_legacy(tp, kind);
7137 tg3_write_sig_post_reset(tp, kind);
7138
7139 if (err)
7140 return err;
7141
7142 return 0;
7143}
7144
7145#define RX_CPU_SCRATCH_BASE 0x30000
7146#define RX_CPU_SCRATCH_SIZE 0x04000
7147#define TX_CPU_SCRATCH_BASE 0x34000
7148#define TX_CPU_SCRATCH_SIZE 0x04000
7149
7150/* tp->lock is held. */
7151static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7152{
7153 int i;
7154
7155 BUG_ON(offset == TX_CPU_BASE &&
7156 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7157
7158 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7159 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7160
7161 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7162 return 0;
7163 }
7164 if (offset == RX_CPU_BASE) {
7165 for (i = 0; i < 10000; i++) {
7166 tw32(offset + CPU_STATE, 0xffffffff);
7167 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7168 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7169 break;
7170 }
7171
7172 tw32(offset + CPU_STATE, 0xffffffff);
7173 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7174 udelay(10);
7175 } else {
7176 for (i = 0; i < 10000; i++) {
7177 tw32(offset + CPU_STATE, 0xffffffff);
7178 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7179 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7180 break;
7181 }
7182 }
7183
7184 if (i >= 10000) {
7185 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7186 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7187 return -ENODEV;
7188 }
7189
7190 /* Clear firmware's nvram arbitration. */
7191 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7192 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7193 return 0;
7194}
7195
7196struct fw_info {
7197 unsigned int fw_base;
7198 unsigned int fw_len;
7199 const __be32 *fw_data;
7200};
7201
7202/* tp->lock is held. */
7203static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7204 int cpu_scratch_size, struct fw_info *info)
7205{
7206 int err, lock_err, i;
7207 void (*write_op)(struct tg3 *, u32, u32);
7208
7209 if (cpu_base == TX_CPU_BASE &&
7210 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7211 netdev_err(tp->dev,
7212 "%s: Trying to load TX cpu firmware which is 5705\n",
7213 __func__);
7214 return -EINVAL;
7215 }
7216
7217 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7218 write_op = tg3_write_mem;
7219 else
7220 write_op = tg3_write_indirect_reg32;
7221
7222 /* It is possible that bootcode is still loading at this point.
7223 * Get the nvram lock first before halting the cpu.
7224 */
7225 lock_err = tg3_nvram_lock(tp);
7226 err = tg3_halt_cpu(tp, cpu_base);
7227 if (!lock_err)
7228 tg3_nvram_unlock(tp);
7229 if (err)
7230 goto out;
7231
7232 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7233 write_op(tp, cpu_scratch_base + i, 0);
7234 tw32(cpu_base + CPU_STATE, 0xffffffff);
7235 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7236 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7237 write_op(tp, (cpu_scratch_base +
7238 (info->fw_base & 0xffff) +
7239 (i * sizeof(u32))),
7240 be32_to_cpu(info->fw_data[i]));
7241
7242 err = 0;
7243
7244out:
7245 return err;
7246}
7247
7248/* tp->lock is held. */
7249static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7250{
7251 struct fw_info info;
7252 const __be32 *fw_data;
7253 int err, i;
7254
7255 fw_data = (void *)tp->fw->data;
7256
7257 /* Firmware blob starts with version numbers, followed by
7258 start address and length. We are setting complete length.
7259 length = end_address_of_bss - start_address_of_text.
7260 Remainder is the blob to be loaded contiguously
7261 from start address. */
7262
7263 info.fw_base = be32_to_cpu(fw_data[1]);
7264 info.fw_len = tp->fw->size - 12;
7265 info.fw_data = &fw_data[3];
7266
7267 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7268 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7269 &info);
7270 if (err)
7271 return err;
7272
7273 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7274 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7275 &info);
7276 if (err)
7277 return err;
7278
7279 /* Now startup only the RX cpu. */
7280 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7281 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7282
7283 for (i = 0; i < 5; i++) {
7284 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7285 break;
7286 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7287 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7288 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7289 udelay(1000);
7290 }
7291 if (i >= 5) {
7292 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7293 "should be %08x\n", __func__,
7294 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7295 return -ENODEV;
7296 }
7297 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7298 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7299
7300 return 0;
7301}
7302
7303/* 5705 needs a special version of the TSO firmware. */
7304
7305/* tp->lock is held. */
7306static int tg3_load_tso_firmware(struct tg3 *tp)
7307{
7308 struct fw_info info;
7309 const __be32 *fw_data;
7310 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7311 int err, i;
7312
7313 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7314 return 0;
7315
7316 fw_data = (void *)tp->fw->data;
7317
7318 /* Firmware blob starts with version numbers, followed by
7319 start address and length. We are setting complete length.
7320 length = end_address_of_bss - start_address_of_text.
7321 Remainder is the blob to be loaded contiguously
7322 from start address. */
7323
7324 info.fw_base = be32_to_cpu(fw_data[1]);
7325 cpu_scratch_size = tp->fw_len;
7326 info.fw_len = tp->fw->size - 12;
7327 info.fw_data = &fw_data[3];
7328
7329 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7330 cpu_base = RX_CPU_BASE;
7331 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7332 } else {
7333 cpu_base = TX_CPU_BASE;
7334 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7335 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7336 }
7337
7338 err = tg3_load_firmware_cpu(tp, cpu_base,
7339 cpu_scratch_base, cpu_scratch_size,
7340 &info);
7341 if (err)
7342 return err;
7343
7344 /* Now startup the cpu. */
7345 tw32(cpu_base + CPU_STATE, 0xffffffff);
7346 tw32_f(cpu_base + CPU_PC, info.fw_base);
7347
7348 for (i = 0; i < 5; i++) {
7349 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7350 break;
7351 tw32(cpu_base + CPU_STATE, 0xffffffff);
7352 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7353 tw32_f(cpu_base + CPU_PC, info.fw_base);
7354 udelay(1000);
7355 }
7356 if (i >= 5) {
7357 netdev_err(tp->dev,
7358 "%s fails to set CPU PC, is %08x should be %08x\n",
7359 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7360 return -ENODEV;
7361 }
7362 tw32(cpu_base + CPU_STATE, 0xffffffff);
7363 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7364 return 0;
7365}
7366
7367
7368static int tg3_set_mac_addr(struct net_device *dev, void *p)
7369{
7370 struct tg3 *tp = netdev_priv(dev);
7371 struct sockaddr *addr = p;
7372 int err = 0, skip_mac_1 = 0;
7373
7374 if (!is_valid_ether_addr(addr->sa_data))
7375 return -EINVAL;
7376
7377 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7378
7379 if (!netif_running(dev))
7380 return 0;
7381
7382 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7383 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7384
7385 addr0_high = tr32(MAC_ADDR_0_HIGH);
7386 addr0_low = tr32(MAC_ADDR_0_LOW);
7387 addr1_high = tr32(MAC_ADDR_1_HIGH);
7388 addr1_low = tr32(MAC_ADDR_1_LOW);
7389
7390 /* Skip MAC addr 1 if ASF is using it. */
7391 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7392 !(addr1_high == 0 && addr1_low == 0))
7393 skip_mac_1 = 1;
7394 }
7395 spin_lock_bh(&tp->lock);
7396 __tg3_set_mac_addr(tp, skip_mac_1);
7397 spin_unlock_bh(&tp->lock);
7398
7399 return err;
7400}
7401
7402/* tp->lock is held. */
7403static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7404 dma_addr_t mapping, u32 maxlen_flags,
7405 u32 nic_addr)
7406{
7407 tg3_write_mem(tp,
7408 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7409 ((u64) mapping >> 32));
7410 tg3_write_mem(tp,
7411 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7412 ((u64) mapping & 0xffffffff));
7413 tg3_write_mem(tp,
7414 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7415 maxlen_flags);
7416
7417 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7418 tg3_write_mem(tp,
7419 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7420 nic_addr);
7421}
7422
7423static void __tg3_set_rx_mode(struct net_device *);
7424static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7425{
7426 int i;
7427
7428 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7429 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7430 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7431 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7432 } else {
7433 tw32(HOSTCC_TXCOL_TICKS, 0);
7434 tw32(HOSTCC_TXMAX_FRAMES, 0);
7435 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7436 }
7437
7438 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7439 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7440 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7441 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7442 } else {
7443 tw32(HOSTCC_RXCOL_TICKS, 0);
7444 tw32(HOSTCC_RXMAX_FRAMES, 0);
7445 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7446 }
7447
7448 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7449 u32 val = ec->stats_block_coalesce_usecs;
7450
7451 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7452 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7453
7454 if (!netif_carrier_ok(tp->dev))
7455 val = 0;
7456
7457 tw32(HOSTCC_STAT_COAL_TICKS, val);
7458 }
7459
7460 for (i = 0; i < tp->irq_cnt - 1; i++) {
7461 u32 reg;
7462
7463 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7464 tw32(reg, ec->rx_coalesce_usecs);
7465 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7466 tw32(reg, ec->rx_max_coalesced_frames);
7467 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7468 tw32(reg, ec->rx_max_coalesced_frames_irq);
7469
7470 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7471 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7472 tw32(reg, ec->tx_coalesce_usecs);
7473 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7474 tw32(reg, ec->tx_max_coalesced_frames);
7475 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7476 tw32(reg, ec->tx_max_coalesced_frames_irq);
7477 }
7478 }
7479
7480 for (; i < tp->irq_max - 1; i++) {
7481 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7482 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7483 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7484
7485 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7486 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7487 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7488 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7489 }
7490 }
7491}
7492
7493/* tp->lock is held. */
7494static void tg3_rings_reset(struct tg3 *tp)
7495{
7496 int i;
7497 u32 stblk, txrcb, rxrcb, limit;
7498 struct tg3_napi *tnapi = &tp->napi[0];
7499
7500 /* Disable all transmit rings but the first. */
7501 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7502 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7503 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7504 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7505 else
7506 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7507
7508 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7509 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7510 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7511 BDINFO_FLAGS_DISABLED);
7512
7513
7514 /* Disable all receive return rings but the first. */
7515 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7516 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7517 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7518 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7519 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7520 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7521 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7522 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7523 else
7524 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7525
7526 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7527 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7528 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7529 BDINFO_FLAGS_DISABLED);
7530
7531 /* Disable interrupts */
7532 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7533
7534 /* Zero mailbox registers. */
7535 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7536 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7537 tp->napi[i].tx_prod = 0;
7538 tp->napi[i].tx_cons = 0;
7539 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7540 tw32_mailbox(tp->napi[i].prodmbox, 0);
7541 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7542 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7543 }
7544 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7545 tw32_mailbox(tp->napi[0].prodmbox, 0);
7546 } else {
7547 tp->napi[0].tx_prod = 0;
7548 tp->napi[0].tx_cons = 0;
7549 tw32_mailbox(tp->napi[0].prodmbox, 0);
7550 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7551 }
7552
7553 /* Make sure the NIC-based send BD rings are disabled. */
7554 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7555 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7556 for (i = 0; i < 16; i++)
7557 tw32_tx_mbox(mbox + i * 8, 0);
7558 }
7559
7560 txrcb = NIC_SRAM_SEND_RCB;
7561 rxrcb = NIC_SRAM_RCV_RET_RCB;
7562
7563 /* Clear status block in ram. */
7564 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7565
7566 /* Set status block DMA address */
7567 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7568 ((u64) tnapi->status_mapping >> 32));
7569 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7570 ((u64) tnapi->status_mapping & 0xffffffff));
7571
7572 if (tnapi->tx_ring) {
7573 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7574 (TG3_TX_RING_SIZE <<
7575 BDINFO_FLAGS_MAXLEN_SHIFT),
7576 NIC_SRAM_TX_BUFFER_DESC);
7577 txrcb += TG3_BDINFO_SIZE;
7578 }
7579
7580 if (tnapi->rx_rcb) {
7581 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7582 (TG3_RX_RCB_RING_SIZE(tp) <<
7583 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7584 rxrcb += TG3_BDINFO_SIZE;
7585 }
7586
7587 stblk = HOSTCC_STATBLCK_RING1;
7588
7589 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7590 u64 mapping = (u64)tnapi->status_mapping;
7591 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7592 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7593
7594 /* Clear status block in ram. */
7595 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7596
7597 if (tnapi->tx_ring) {
7598 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7599 (TG3_TX_RING_SIZE <<
7600 BDINFO_FLAGS_MAXLEN_SHIFT),
7601 NIC_SRAM_TX_BUFFER_DESC);
7602 txrcb += TG3_BDINFO_SIZE;
7603 }
7604
7605 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7606 (TG3_RX_RCB_RING_SIZE(tp) <<
7607 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7608
7609 stblk += 8;
7610 rxrcb += TG3_BDINFO_SIZE;
7611 }
7612}
7613
7614/* tp->lock is held. */
7615static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7616{
7617 u32 val, rdmac_mode;
7618 int i, err, limit;
7619 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7620
7621 tg3_disable_ints(tp);
7622
7623 tg3_stop_fw(tp);
7624
7625 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7626
7627 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7628 tg3_abort_hw(tp, 1);
7629
7630 if (reset_phy)
7631 tg3_phy_reset(tp);
7632
7633 err = tg3_chip_reset(tp);
7634 if (err)
7635 return err;
7636
7637 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7638
7639 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7640 val = tr32(TG3_CPMU_CTRL);
7641 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7642 tw32(TG3_CPMU_CTRL, val);
7643
7644 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7645 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7646 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7647 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7648
7649 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7650 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7651 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7652 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7653
7654 val = tr32(TG3_CPMU_HST_ACC);
7655 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7656 val |= CPMU_HST_ACC_MACCLK_6_25;
7657 tw32(TG3_CPMU_HST_ACC, val);
7658 }
7659
7660 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7661 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7662 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7663 PCIE_PWR_MGMT_L1_THRESH_4MS;
7664 tw32(PCIE_PWR_MGMT_THRESH, val);
7665
7666 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7667 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7668
7669 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7670
7671 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7672 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7673 }
7674
7675 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7676 u32 grc_mode = tr32(GRC_MODE);
7677
7678 /* Access the lower 1K of PL PCIE block registers. */
7679 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7680 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7681
7682 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7683 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7684 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7685
7686 tw32(GRC_MODE, grc_mode);
7687 }
7688
7689 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7690 u32 grc_mode = tr32(GRC_MODE);
7691
7692 /* Access the lower 1K of PL PCIE block registers. */
7693 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7694 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7695
7696 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7697 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7698 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7699
7700 tw32(GRC_MODE, grc_mode);
7701
7702 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7703 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7704 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7705 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7706 }
7707
7708 /* This works around an issue with Athlon chipsets on
7709 * B3 tigon3 silicon. This bit has no effect on any
7710 * other revision. But do not set this on PCI Express
7711 * chips and don't even touch the clocks if the CPMU is present.
7712 */
7713 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7714 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7715 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7716 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7717 }
7718
7719 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7720 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7721 val = tr32(TG3PCI_PCISTATE);
7722 val |= PCISTATE_RETRY_SAME_DMA;
7723 tw32(TG3PCI_PCISTATE, val);
7724 }
7725
7726 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7727 /* Allow reads and writes to the
7728 * APE register and memory space.
7729 */
7730 val = tr32(TG3PCI_PCISTATE);
7731 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7732 PCISTATE_ALLOW_APE_SHMEM_WR |
7733 PCISTATE_ALLOW_APE_PSPACE_WR;
7734 tw32(TG3PCI_PCISTATE, val);
7735 }
7736
7737 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7738 /* Enable some hw fixes. */
7739 val = tr32(TG3PCI_MSI_DATA);
7740 val |= (1 << 26) | (1 << 28) | (1 << 29);
7741 tw32(TG3PCI_MSI_DATA, val);
7742 }
7743
7744 /* Descriptor ring init may make accesses to the
7745 * NIC SRAM area to setup the TX descriptors, so we
7746 * can only do this after the hardware has been
7747 * successfully reset.
7748 */
7749 err = tg3_init_rings(tp);
7750 if (err)
7751 return err;
7752
7753 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7754 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7755 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7756 val = tr32(TG3PCI_DMA_RW_CTRL) &
7757 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7758 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7759 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7760 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7761 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7762 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7763 /* This value is determined during the probe time DMA
7764 * engine test, tg3_test_dma.
7765 */
7766 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7767 }
7768
7769 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7770 GRC_MODE_4X_NIC_SEND_RINGS |
7771 GRC_MODE_NO_TX_PHDR_CSUM |
7772 GRC_MODE_NO_RX_PHDR_CSUM);
7773 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7774
7775 /* Pseudo-header checksum is done by hardware logic and not
7776 * the offload processers, so make the chip do the pseudo-
7777 * header checksums on receive. For transmit it is more
7778 * convenient to do the pseudo-header checksum in software
7779 * as Linux does that on transmit for us in all cases.
7780 */
7781 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7782
7783 tw32(GRC_MODE,
7784 tp->grc_mode |
7785 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7786
7787 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7788 val = tr32(GRC_MISC_CFG);
7789 val &= ~0xff;
7790 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7791 tw32(GRC_MISC_CFG, val);
7792
7793 /* Initialize MBUF/DESC pool. */
7794 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7795 /* Do nothing. */
7796 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7797 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7798 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7799 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7800 else
7801 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7802 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7803 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7804 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7805 int fw_len;
7806
7807 fw_len = tp->fw_len;
7808 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7809 tw32(BUFMGR_MB_POOL_ADDR,
7810 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7811 tw32(BUFMGR_MB_POOL_SIZE,
7812 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7813 }
7814
7815 if (tp->dev->mtu <= ETH_DATA_LEN) {
7816 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7817 tp->bufmgr_config.mbuf_read_dma_low_water);
7818 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7819 tp->bufmgr_config.mbuf_mac_rx_low_water);
7820 tw32(BUFMGR_MB_HIGH_WATER,
7821 tp->bufmgr_config.mbuf_high_water);
7822 } else {
7823 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7824 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7825 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7826 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7827 tw32(BUFMGR_MB_HIGH_WATER,
7828 tp->bufmgr_config.mbuf_high_water_jumbo);
7829 }
7830 tw32(BUFMGR_DMA_LOW_WATER,
7831 tp->bufmgr_config.dma_low_water);
7832 tw32(BUFMGR_DMA_HIGH_WATER,
7833 tp->bufmgr_config.dma_high_water);
7834
7835 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7836 for (i = 0; i < 2000; i++) {
7837 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7838 break;
7839 udelay(10);
7840 }
7841 if (i >= 2000) {
7842 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7843 return -ENODEV;
7844 }
7845
7846 /* Setup replenish threshold. */
7847 val = tp->rx_pending / 8;
7848 if (val == 0)
7849 val = 1;
7850 else if (val > tp->rx_std_max_post)
7851 val = tp->rx_std_max_post;
7852 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7853 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7854 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7855
7856 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7857 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7858 }
7859
7860 tw32(RCVBDI_STD_THRESH, val);
7861
7862 /* Initialize TG3_BDINFO's at:
7863 * RCVDBDI_STD_BD: standard eth size rx ring
7864 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7865 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7866 *
7867 * like so:
7868 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7869 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7870 * ring attribute flags
7871 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7872 *
7873 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7874 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7875 *
7876 * The size of each ring is fixed in the firmware, but the location is
7877 * configurable.
7878 */
7879 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7880 ((u64) tpr->rx_std_mapping >> 32));
7881 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7882 ((u64) tpr->rx_std_mapping & 0xffffffff));
7883 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7884 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7885 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7886 NIC_SRAM_RX_BUFFER_DESC);
7887
7888 /* Disable the mini ring */
7889 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7890 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7891 BDINFO_FLAGS_DISABLED);
7892
7893 /* Program the jumbo buffer descriptor ring control
7894 * blocks on those devices that have them.
7895 */
7896 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7897 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7898 /* Setup replenish threshold. */
7899 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7900
7901 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7902 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7903 ((u64) tpr->rx_jmb_mapping >> 32));
7904 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7905 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7906 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7907 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7908 BDINFO_FLAGS_USE_EXT_RECV);
7909 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7911 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7912 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7913 } else {
7914 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7915 BDINFO_FLAGS_DISABLED);
7916 }
7917
7918 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7919 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7920 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7921 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7922 (TG3_RX_STD_DMA_SZ << 2);
7923 else
7924 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7925 } else
7926 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7927
7928 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7929
7930 tpr->rx_std_prod_idx = tp->rx_pending;
7931 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7932
7933 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7934 tp->rx_jumbo_pending : 0;
7935 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7936
7937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7940 tw32(STD_REPLENISH_LWM, 32);
7941 tw32(JMB_REPLENISH_LWM, 16);
7942 }
7943
7944 tg3_rings_reset(tp);
7945
7946 /* Initialize MAC address and backoff seed. */
7947 __tg3_set_mac_addr(tp, 0);
7948
7949 /* MTU + ethernet header + FCS + optional VLAN tag */
7950 tw32(MAC_RX_MTU_SIZE,
7951 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7952
7953 /* The slot time is changed by tg3_setup_phy if we
7954 * run at gigabit with half duplex.
7955 */
7956 tw32(MAC_TX_LENGTHS,
7957 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7958 (6 << TX_LENGTHS_IPG_SHIFT) |
7959 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7960
7961 /* Receive rules. */
7962 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7963 tw32(RCVLPC_CONFIG, 0x0181);
7964
7965 /* Calculate RDMAC_MODE setting early, we need it to determine
7966 * the RCVLPC_STATE_ENABLE mask.
7967 */
7968 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7969 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7970 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7971 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7972 RDMAC_MODE_LNGREAD_ENAB);
7973
7974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7975 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7976 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7977
7978 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7980 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7981 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7982 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7983 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7984
7985 /* If statement applies to 5705 and 5750 PCI devices only */
7986 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7987 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7988 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7989 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7991 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7992 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7993 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7994 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7995 }
7996 }
7997
7998 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7999 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8000
8001 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8002 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8003
8004 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8005 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8006 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8007 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8008
8009 /* Receive/send statistics. */
8010 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8011 val = tr32(RCVLPC_STATS_ENABLE);
8012 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8013 tw32(RCVLPC_STATS_ENABLE, val);
8014 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8015 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8016 val = tr32(RCVLPC_STATS_ENABLE);
8017 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8018 tw32(RCVLPC_STATS_ENABLE, val);
8019 } else {
8020 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8021 }
8022 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8023 tw32(SNDDATAI_STATSENAB, 0xffffff);
8024 tw32(SNDDATAI_STATSCTRL,
8025 (SNDDATAI_SCTRL_ENABLE |
8026 SNDDATAI_SCTRL_FASTUPD));
8027
8028 /* Setup host coalescing engine. */
8029 tw32(HOSTCC_MODE, 0);
8030 for (i = 0; i < 2000; i++) {
8031 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8032 break;
8033 udelay(10);
8034 }
8035
8036 __tg3_set_coalesce(tp, &tp->coal);
8037
8038 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8039 /* Status/statistics block address. See tg3_timer,
8040 * the tg3_periodic_fetch_stats call there, and
8041 * tg3_get_stats to see how this works for 5705/5750 chips.
8042 */
8043 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8044 ((u64) tp->stats_mapping >> 32));
8045 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8046 ((u64) tp->stats_mapping & 0xffffffff));
8047 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8048
8049 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8050
8051 /* Clear statistics and status block memory areas */
8052 for (i = NIC_SRAM_STATS_BLK;
8053 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8054 i += sizeof(u32)) {
8055 tg3_write_mem(tp, i, 0);
8056 udelay(40);
8057 }
8058 }
8059
8060 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8061
8062 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8063 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8064 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8065 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8066
8067 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8068 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8069 /* reset to prevent losing 1st rx packet intermittently */
8070 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8071 udelay(10);
8072 }
8073
8074 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8075 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8076 else
8077 tp->mac_mode = 0;
8078 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8079 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8080 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8081 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8082 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8083 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8084 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8085 udelay(40);
8086
8087 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8088 * If TG3_FLG2_IS_NIC is zero, we should read the
8089 * register to preserve the GPIO settings for LOMs. The GPIOs,
8090 * whether used as inputs or outputs, are set by boot code after
8091 * reset.
8092 */
8093 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8094 u32 gpio_mask;
8095
8096 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8097 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8098 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8099
8100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8101 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8102 GRC_LCLCTRL_GPIO_OUTPUT3;
8103
8104 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8105 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8106
8107 tp->grc_local_ctrl &= ~gpio_mask;
8108 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8109
8110 /* GPIO1 must be driven high for eeprom write protect */
8111 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8112 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8113 GRC_LCLCTRL_GPIO_OUTPUT1);
8114 }
8115 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8116 udelay(100);
8117
8118 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8119 val = tr32(MSGINT_MODE);
8120 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8121 tw32(MSGINT_MODE, val);
8122 }
8123
8124 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8125 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8126 udelay(40);
8127 }
8128
8129 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8130 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8131 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8132 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8133 WDMAC_MODE_LNGREAD_ENAB);
8134
8135 /* If statement applies to 5705 and 5750 PCI devices only */
8136 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8137 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8139 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8140 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8141 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8142 /* nothing */
8143 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8144 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8145 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8146 val |= WDMAC_MODE_RX_ACCEL;
8147 }
8148 }
8149
8150 /* Enable host coalescing bug fix */
8151 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8152 val |= WDMAC_MODE_STATUS_TAG_FIX;
8153
8154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8155 val |= WDMAC_MODE_BURST_ALL_DATA;
8156
8157 tw32_f(WDMAC_MODE, val);
8158 udelay(40);
8159
8160 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8161 u16 pcix_cmd;
8162
8163 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8164 &pcix_cmd);
8165 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8166 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8167 pcix_cmd |= PCI_X_CMD_READ_2K;
8168 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8169 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8170 pcix_cmd |= PCI_X_CMD_READ_2K;
8171 }
8172 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8173 pcix_cmd);
8174 }
8175
8176 tw32_f(RDMAC_MODE, rdmac_mode);
8177 udelay(40);
8178
8179 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8180 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8181 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8182
8183 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8184 tw32(SNDDATAC_MODE,
8185 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8186 else
8187 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8188
8189 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8190 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8191 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8192 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8193 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8194 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8195 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8196 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8197 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8198 tw32(SNDBDI_MODE, val);
8199 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8200
8201 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8202 err = tg3_load_5701_a0_firmware_fix(tp);
8203 if (err)
8204 return err;
8205 }
8206
8207 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8208 err = tg3_load_tso_firmware(tp);
8209 if (err)
8210 return err;
8211 }
8212
8213 tp->tx_mode = TX_MODE_ENABLE;
8214 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8215 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8216 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8217 tw32_f(MAC_TX_MODE, tp->tx_mode);
8218 udelay(100);
8219
8220 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8221 u32 reg = MAC_RSS_INDIR_TBL_0;
8222 u8 *ent = (u8 *)&val;
8223
8224 /* Setup the indirection table */
8225 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8226 int idx = i % sizeof(val);
8227
8228 ent[idx] = i % (tp->irq_cnt - 1);
8229 if (idx == sizeof(val) - 1) {
8230 tw32(reg, val);
8231 reg += 4;
8232 }
8233 }
8234
8235 /* Setup the "secret" hash key. */
8236 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8237 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8238 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8239 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8240 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8241 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8242 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8243 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8244 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8245 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8246 }
8247
8248 tp->rx_mode = RX_MODE_ENABLE;
8249 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8250 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8251
8252 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8253 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8254 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8255 RX_MODE_RSS_IPV6_HASH_EN |
8256 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8257 RX_MODE_RSS_IPV4_HASH_EN |
8258 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8259
8260 tw32_f(MAC_RX_MODE, tp->rx_mode);
8261 udelay(10);
8262
8263 tw32(MAC_LED_CTRL, tp->led_ctrl);
8264
8265 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8266 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8267 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8268 udelay(10);
8269 }
8270 tw32_f(MAC_RX_MODE, tp->rx_mode);
8271 udelay(10);
8272
8273 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8274 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8275 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8276 /* Set drive transmission level to 1.2V */
8277 /* only if the signal pre-emphasis bit is not set */
8278 val = tr32(MAC_SERDES_CFG);
8279 val &= 0xfffff000;
8280 val |= 0x880;
8281 tw32(MAC_SERDES_CFG, val);
8282 }
8283 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8284 tw32(MAC_SERDES_CFG, 0x616000);
8285 }
8286
8287 /* Prevent chip from dropping frames when flow control
8288 * is enabled.
8289 */
8290 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8291 val = 1;
8292 else
8293 val = 2;
8294 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8295
8296 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8297 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8298 /* Use hardware link auto-negotiation */
8299 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8300 }
8301
8302 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8303 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8304 u32 tmp;
8305
8306 tmp = tr32(SERDES_RX_CTRL);
8307 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8308 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8309 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8310 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8311 }
8312
8313 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8314 if (tp->link_config.phy_is_low_power) {
8315 tp->link_config.phy_is_low_power = 0;
8316 tp->link_config.speed = tp->link_config.orig_speed;
8317 tp->link_config.duplex = tp->link_config.orig_duplex;
8318 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8319 }
8320
8321 err = tg3_setup_phy(tp, 0);
8322 if (err)
8323 return err;
8324
8325 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8326 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8327 u32 tmp;
8328
8329 /* Clear CRC stats. */
8330 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8331 tg3_writephy(tp, MII_TG3_TEST1,
8332 tmp | MII_TG3_TEST1_CRC_EN);
8333 tg3_readphy(tp, 0x14, &tmp);
8334 }
8335 }
8336 }
8337
8338 __tg3_set_rx_mode(tp->dev);
8339
8340 /* Initialize receive rules. */
8341 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8342 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8343 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8344 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8345
8346 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8347 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8348 limit = 8;
8349 else
8350 limit = 16;
8351 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8352 limit -= 4;
8353 switch (limit) {
8354 case 16:
8355 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8356 case 15:
8357 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8358 case 14:
8359 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8360 case 13:
8361 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8362 case 12:
8363 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8364 case 11:
8365 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8366 case 10:
8367 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8368 case 9:
8369 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8370 case 8:
8371 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8372 case 7:
8373 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8374 case 6:
8375 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8376 case 5:
8377 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8378 case 4:
8379 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8380 case 3:
8381 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8382 case 2:
8383 case 1:
8384
8385 default:
8386 break;
8387 }
8388
8389 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8390 /* Write our heartbeat update interval to APE. */
8391 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8392 APE_HOST_HEARTBEAT_INT_DISABLE);
8393
8394 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8395
8396 return 0;
8397}
8398
8399/* Called at device open time to get the chip ready for
8400 * packet processing. Invoked with tp->lock held.
8401 */
8402static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8403{
8404 tg3_switch_clocks(tp);
8405
8406 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8407
8408 return tg3_reset_hw(tp, reset_phy);
8409}
8410
8411#define TG3_STAT_ADD32(PSTAT, REG) \
8412do { u32 __val = tr32(REG); \
8413 (PSTAT)->low += __val; \
8414 if ((PSTAT)->low < __val) \
8415 (PSTAT)->high += 1; \
8416} while (0)
8417
8418static void tg3_periodic_fetch_stats(struct tg3 *tp)
8419{
8420 struct tg3_hw_stats *sp = tp->hw_stats;
8421
8422 if (!netif_carrier_ok(tp->dev))
8423 return;
8424
8425 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8426 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8427 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8428 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8429 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8430 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8431 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8432 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8433 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8434 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8435 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8436 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8437 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8438
8439 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8440 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8441 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8442 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8443 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8444 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8445 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8446 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8447 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8448 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8449 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8450 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8451 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8452 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8453
8454 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8455 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8456 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8457}
8458
8459static void tg3_timer(unsigned long __opaque)
8460{
8461 struct tg3 *tp = (struct tg3 *) __opaque;
8462
8463 if (tp->irq_sync)
8464 goto restart_timer;
8465
8466 spin_lock(&tp->lock);
8467
8468 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8469 /* All of this garbage is because when using non-tagged
8470 * IRQ status the mailbox/status_block protocol the chip
8471 * uses with the cpu is race prone.
8472 */
8473 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8474 tw32(GRC_LOCAL_CTRL,
8475 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8476 } else {
8477 tw32(HOSTCC_MODE, tp->coalesce_mode |
8478 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8479 }
8480
8481 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8482 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8483 spin_unlock(&tp->lock);
8484 schedule_work(&tp->reset_task);
8485 return;
8486 }
8487 }
8488
8489 /* This part only runs once per second. */
8490 if (!--tp->timer_counter) {
8491 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8492 tg3_periodic_fetch_stats(tp);
8493
8494 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8495 u32 mac_stat;
8496 int phy_event;
8497
8498 mac_stat = tr32(MAC_STATUS);
8499
8500 phy_event = 0;
8501 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8502 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8503 phy_event = 1;
8504 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8505 phy_event = 1;
8506
8507 if (phy_event)
8508 tg3_setup_phy(tp, 0);
8509 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8510 u32 mac_stat = tr32(MAC_STATUS);
8511 int need_setup = 0;
8512
8513 if (netif_carrier_ok(tp->dev) &&
8514 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8515 need_setup = 1;
8516 }
8517 if (!netif_carrier_ok(tp->dev) &&
8518 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8519 MAC_STATUS_SIGNAL_DET))) {
8520 need_setup = 1;
8521 }
8522 if (need_setup) {
8523 if (!tp->serdes_counter) {
8524 tw32_f(MAC_MODE,
8525 (tp->mac_mode &
8526 ~MAC_MODE_PORT_MODE_MASK));
8527 udelay(40);
8528 tw32_f(MAC_MODE, tp->mac_mode);
8529 udelay(40);
8530 }
8531 tg3_setup_phy(tp, 0);
8532 }
8533 } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8534 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8535 tg3_serdes_parallel_detect(tp);
8536 }
8537
8538 tp->timer_counter = tp->timer_multiplier;
8539 }
8540
8541 /* Heartbeat is only sent once every 2 seconds.
8542 *
8543 * The heartbeat is to tell the ASF firmware that the host
8544 * driver is still alive. In the event that the OS crashes,
8545 * ASF needs to reset the hardware to free up the FIFO space
8546 * that may be filled with rx packets destined for the host.
8547 * If the FIFO is full, ASF will no longer function properly.
8548 *
8549 * Unintended resets have been reported on real time kernels
8550 * where the timer doesn't run on time. Netpoll will also have
8551 * same problem.
8552 *
8553 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8554 * to check the ring condition when the heartbeat is expiring
8555 * before doing the reset. This will prevent most unintended
8556 * resets.
8557 */
8558 if (!--tp->asf_counter) {
8559 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8560 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8561 tg3_wait_for_event_ack(tp);
8562
8563 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8564 FWCMD_NICDRV_ALIVE3);
8565 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8566 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8567 TG3_FW_UPDATE_TIMEOUT_SEC);
8568
8569 tg3_generate_fw_event(tp);
8570 }
8571 tp->asf_counter = tp->asf_multiplier;
8572 }
8573
8574 spin_unlock(&tp->lock);
8575
8576restart_timer:
8577 tp->timer.expires = jiffies + tp->timer_offset;
8578 add_timer(&tp->timer);
8579}
8580
8581static int tg3_request_irq(struct tg3 *tp, int irq_num)
8582{
8583 irq_handler_t fn;
8584 unsigned long flags;
8585 char *name;
8586 struct tg3_napi *tnapi = &tp->napi[irq_num];
8587
8588 if (tp->irq_cnt == 1)
8589 name = tp->dev->name;
8590 else {
8591 name = &tnapi->irq_lbl[0];
8592 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8593 name[IFNAMSIZ-1] = 0;
8594 }
8595
8596 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8597 fn = tg3_msi;
8598 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8599 fn = tg3_msi_1shot;
8600 flags = IRQF_SAMPLE_RANDOM;
8601 } else {
8602 fn = tg3_interrupt;
8603 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8604 fn = tg3_interrupt_tagged;
8605 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8606 }
8607
8608 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8609}
8610
8611static int tg3_test_interrupt(struct tg3 *tp)
8612{
8613 struct tg3_napi *tnapi = &tp->napi[0];
8614 struct net_device *dev = tp->dev;
8615 int err, i, intr_ok = 0;
8616 u32 val;
8617
8618 if (!netif_running(dev))
8619 return -ENODEV;
8620
8621 tg3_disable_ints(tp);
8622
8623 free_irq(tnapi->irq_vec, tnapi);
8624
8625 /*
8626 * Turn off MSI one shot mode. Otherwise this test has no
8627 * observable way to know whether the interrupt was delivered.
8628 */
8629 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8632 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8633 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8634 tw32(MSGINT_MODE, val);
8635 }
8636
8637 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8638 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8639 if (err)
8640 return err;
8641
8642 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8643 tg3_enable_ints(tp);
8644
8645 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8646 tnapi->coal_now);
8647
8648 for (i = 0; i < 5; i++) {
8649 u32 int_mbox, misc_host_ctrl;
8650
8651 int_mbox = tr32_mailbox(tnapi->int_mbox);
8652 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8653
8654 if ((int_mbox != 0) ||
8655 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8656 intr_ok = 1;
8657 break;
8658 }
8659
8660 msleep(10);
8661 }
8662
8663 tg3_disable_ints(tp);
8664
8665 free_irq(tnapi->irq_vec, tnapi);
8666
8667 err = tg3_request_irq(tp, 0);
8668
8669 if (err)
8670 return err;
8671
8672 if (intr_ok) {
8673 /* Reenable MSI one shot mode. */
8674 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8675 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8676 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8677 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8678 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8679 tw32(MSGINT_MODE, val);
8680 }
8681 return 0;
8682 }
8683
8684 return -EIO;
8685}
8686
8687/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8688 * successfully restored
8689 */
8690static int tg3_test_msi(struct tg3 *tp)
8691{
8692 int err;
8693 u16 pci_cmd;
8694
8695 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8696 return 0;
8697
8698 /* Turn off SERR reporting in case MSI terminates with Master
8699 * Abort.
8700 */
8701 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8702 pci_write_config_word(tp->pdev, PCI_COMMAND,
8703 pci_cmd & ~PCI_COMMAND_SERR);
8704
8705 err = tg3_test_interrupt(tp);
8706
8707 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8708
8709 if (!err)
8710 return 0;
8711
8712 /* other failures */
8713 if (err != -EIO)
8714 return err;
8715
8716 /* MSI test failed, go back to INTx mode */
8717 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8718 "to INTx mode. Please report this failure to the PCI "
8719 "maintainer and include system chipset information\n");
8720
8721 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8722
8723 pci_disable_msi(tp->pdev);
8724
8725 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8726 tp->napi[0].irq_vec = tp->pdev->irq;
8727
8728 err = tg3_request_irq(tp, 0);
8729 if (err)
8730 return err;
8731
8732 /* Need to reset the chip because the MSI cycle may have terminated
8733 * with Master Abort.
8734 */
8735 tg3_full_lock(tp, 1);
8736
8737 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8738 err = tg3_init_hw(tp, 1);
8739
8740 tg3_full_unlock(tp);
8741
8742 if (err)
8743 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8744
8745 return err;
8746}
8747
8748static int tg3_request_firmware(struct tg3 *tp)
8749{
8750 const __be32 *fw_data;
8751
8752 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8753 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8754 tp->fw_needed);
8755 return -ENOENT;
8756 }
8757
8758 fw_data = (void *)tp->fw->data;
8759
8760 /* Firmware blob starts with version numbers, followed by
8761 * start address and _full_ length including BSS sections
8762 * (which must be longer than the actual data, of course
8763 */
8764
8765 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8766 if (tp->fw_len < (tp->fw->size - 12)) {
8767 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8768 tp->fw_len, tp->fw_needed);
8769 release_firmware(tp->fw);
8770 tp->fw = NULL;
8771 return -EINVAL;
8772 }
8773
8774 /* We no longer need firmware; we have it. */
8775 tp->fw_needed = NULL;
8776 return 0;
8777}
8778
8779static bool tg3_enable_msix(struct tg3 *tp)
8780{
8781 int i, rc, cpus = num_online_cpus();
8782 struct msix_entry msix_ent[tp->irq_max];
8783
8784 if (cpus == 1)
8785 /* Just fallback to the simpler MSI mode. */
8786 return false;
8787
8788 /*
8789 * We want as many rx rings enabled as there are cpus.
8790 * The first MSIX vector only deals with link interrupts, etc,
8791 * so we add one to the number of vectors we are requesting.
8792 */
8793 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8794
8795 for (i = 0; i < tp->irq_max; i++) {
8796 msix_ent[i].entry = i;
8797 msix_ent[i].vector = 0;
8798 }
8799
8800 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8801 if (rc < 0) {
8802 return false;
8803 } else if (rc != 0) {
8804 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8805 return false;
8806 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8807 tp->irq_cnt, rc);
8808 tp->irq_cnt = rc;
8809 }
8810
8811 for (i = 0; i < tp->irq_max; i++)
8812 tp->napi[i].irq_vec = msix_ent[i].vector;
8813
8814 tp->dev->real_num_tx_queues = 1;
8815 if (tp->irq_cnt > 1) {
8816 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8817
8818 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8819 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8820 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8821 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8822 }
8823 }
8824
8825 return true;
8826}
8827
8828static void tg3_ints_init(struct tg3 *tp)
8829{
8830 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8831 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8832 /* All MSI supporting chips should support tagged
8833 * status. Assert that this is the case.
8834 */
8835 netdev_warn(tp->dev,
8836 "MSI without TAGGED_STATUS? Not using MSI\n");
8837 goto defcfg;
8838 }
8839
8840 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8841 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8842 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8843 pci_enable_msi(tp->pdev) == 0)
8844 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8845
8846 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8847 u32 msi_mode = tr32(MSGINT_MODE);
8848 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8849 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8850 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8851 }
8852defcfg:
8853 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8854 tp->irq_cnt = 1;
8855 tp->napi[0].irq_vec = tp->pdev->irq;
8856 tp->dev->real_num_tx_queues = 1;
8857 }
8858}
8859
8860static void tg3_ints_fini(struct tg3 *tp)
8861{
8862 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8863 pci_disable_msix(tp->pdev);
8864 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8865 pci_disable_msi(tp->pdev);
8866 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8867 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8868}
8869
8870static int tg3_open(struct net_device *dev)
8871{
8872 struct tg3 *tp = netdev_priv(dev);
8873 int i, err;
8874
8875 if (tp->fw_needed) {
8876 err = tg3_request_firmware(tp);
8877 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8878 if (err)
8879 return err;
8880 } else if (err) {
8881 netdev_warn(tp->dev, "TSO capability disabled\n");
8882 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8883 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8884 netdev_notice(tp->dev, "TSO capability restored\n");
8885 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8886 }
8887 }
8888
8889 netif_carrier_off(tp->dev);
8890
8891 err = tg3_set_power_state(tp, PCI_D0);
8892 if (err)
8893 return err;
8894
8895 tg3_full_lock(tp, 0);
8896
8897 tg3_disable_ints(tp);
8898 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8899
8900 tg3_full_unlock(tp);
8901
8902 /*
8903 * Setup interrupts first so we know how
8904 * many NAPI resources to allocate
8905 */
8906 tg3_ints_init(tp);
8907
8908 /* The placement of this call is tied
8909 * to the setup and use of Host TX descriptors.
8910 */
8911 err = tg3_alloc_consistent(tp);
8912 if (err)
8913 goto err_out1;
8914
8915 tg3_napi_enable(tp);
8916
8917 for (i = 0; i < tp->irq_cnt; i++) {
8918 struct tg3_napi *tnapi = &tp->napi[i];
8919 err = tg3_request_irq(tp, i);
8920 if (err) {
8921 for (i--; i >= 0; i--)
8922 free_irq(tnapi->irq_vec, tnapi);
8923 break;
8924 }
8925 }
8926
8927 if (err)
8928 goto err_out2;
8929
8930 tg3_full_lock(tp, 0);
8931
8932 err = tg3_init_hw(tp, 1);
8933 if (err) {
8934 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8935 tg3_free_rings(tp);
8936 } else {
8937 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8938 tp->timer_offset = HZ;
8939 else
8940 tp->timer_offset = HZ / 10;
8941
8942 BUG_ON(tp->timer_offset > HZ);
8943 tp->timer_counter = tp->timer_multiplier =
8944 (HZ / tp->timer_offset);
8945 tp->asf_counter = tp->asf_multiplier =
8946 ((HZ / tp->timer_offset) * 2);
8947
8948 init_timer(&tp->timer);
8949 tp->timer.expires = jiffies + tp->timer_offset;
8950 tp->timer.data = (unsigned long) tp;
8951 tp->timer.function = tg3_timer;
8952 }
8953
8954 tg3_full_unlock(tp);
8955
8956 if (err)
8957 goto err_out3;
8958
8959 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8960 err = tg3_test_msi(tp);
8961
8962 if (err) {
8963 tg3_full_lock(tp, 0);
8964 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8965 tg3_free_rings(tp);
8966 tg3_full_unlock(tp);
8967
8968 goto err_out2;
8969 }
8970
8971 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8972 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
8973 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8974 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8975 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8976 u32 val = tr32(PCIE_TRANSACTION_CFG);
8977
8978 tw32(PCIE_TRANSACTION_CFG,
8979 val | PCIE_TRANS_CFG_1SHOT_MSI);
8980 }
8981 }
8982
8983 tg3_phy_start(tp);
8984
8985 tg3_full_lock(tp, 0);
8986
8987 add_timer(&tp->timer);
8988 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8989 tg3_enable_ints(tp);
8990
8991 tg3_full_unlock(tp);
8992
8993 netif_tx_start_all_queues(dev);
8994
8995 return 0;
8996
8997err_out3:
8998 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8999 struct tg3_napi *tnapi = &tp->napi[i];
9000 free_irq(tnapi->irq_vec, tnapi);
9001 }
9002
9003err_out2:
9004 tg3_napi_disable(tp);
9005 tg3_free_consistent(tp);
9006
9007err_out1:
9008 tg3_ints_fini(tp);
9009 return err;
9010}
9011
9012static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9013 struct rtnl_link_stats64 *);
9014static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9015
9016static int tg3_close(struct net_device *dev)
9017{
9018 int i;
9019 struct tg3 *tp = netdev_priv(dev);
9020
9021 tg3_napi_disable(tp);
9022 cancel_work_sync(&tp->reset_task);
9023
9024 netif_tx_stop_all_queues(dev);
9025
9026 del_timer_sync(&tp->timer);
9027
9028 tg3_phy_stop(tp);
9029
9030 tg3_full_lock(tp, 1);
9031
9032 tg3_disable_ints(tp);
9033
9034 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9035 tg3_free_rings(tp);
9036 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9037
9038 tg3_full_unlock(tp);
9039
9040 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9041 struct tg3_napi *tnapi = &tp->napi[i];
9042 free_irq(tnapi->irq_vec, tnapi);
9043 }
9044
9045 tg3_ints_fini(tp);
9046
9047 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9048
9049 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9050 sizeof(tp->estats_prev));
9051
9052 tg3_free_consistent(tp);
9053
9054 tg3_set_power_state(tp, PCI_D3hot);
9055
9056 netif_carrier_off(tp->dev);
9057
9058 return 0;
9059}
9060
9061static inline u64 get_stat64(tg3_stat64_t *val)
9062{
9063 return ((u64)val->high << 32) | ((u64)val->low);
9064}
9065
9066static u64 calc_crc_errors(struct tg3 *tp)
9067{
9068 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9069
9070 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9071 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9072 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9073 u32 val;
9074
9075 spin_lock_bh(&tp->lock);
9076 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9077 tg3_writephy(tp, MII_TG3_TEST1,
9078 val | MII_TG3_TEST1_CRC_EN);
9079 tg3_readphy(tp, 0x14, &val);
9080 } else
9081 val = 0;
9082 spin_unlock_bh(&tp->lock);
9083
9084 tp->phy_crc_errors += val;
9085
9086 return tp->phy_crc_errors;
9087 }
9088
9089 return get_stat64(&hw_stats->rx_fcs_errors);
9090}
9091
9092#define ESTAT_ADD(member) \
9093 estats->member = old_estats->member + \
9094 get_stat64(&hw_stats->member)
9095
9096static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9097{
9098 struct tg3_ethtool_stats *estats = &tp->estats;
9099 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9100 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9101
9102 if (!hw_stats)
9103 return old_estats;
9104
9105 ESTAT_ADD(rx_octets);
9106 ESTAT_ADD(rx_fragments);
9107 ESTAT_ADD(rx_ucast_packets);
9108 ESTAT_ADD(rx_mcast_packets);
9109 ESTAT_ADD(rx_bcast_packets);
9110 ESTAT_ADD(rx_fcs_errors);
9111 ESTAT_ADD(rx_align_errors);
9112 ESTAT_ADD(rx_xon_pause_rcvd);
9113 ESTAT_ADD(rx_xoff_pause_rcvd);
9114 ESTAT_ADD(rx_mac_ctrl_rcvd);
9115 ESTAT_ADD(rx_xoff_entered);
9116 ESTAT_ADD(rx_frame_too_long_errors);
9117 ESTAT_ADD(rx_jabbers);
9118 ESTAT_ADD(rx_undersize_packets);
9119 ESTAT_ADD(rx_in_length_errors);
9120 ESTAT_ADD(rx_out_length_errors);
9121 ESTAT_ADD(rx_64_or_less_octet_packets);
9122 ESTAT_ADD(rx_65_to_127_octet_packets);
9123 ESTAT_ADD(rx_128_to_255_octet_packets);
9124 ESTAT_ADD(rx_256_to_511_octet_packets);
9125 ESTAT_ADD(rx_512_to_1023_octet_packets);
9126 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9127 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9128 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9129 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9130 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9131
9132 ESTAT_ADD(tx_octets);
9133 ESTAT_ADD(tx_collisions);
9134 ESTAT_ADD(tx_xon_sent);
9135 ESTAT_ADD(tx_xoff_sent);
9136 ESTAT_ADD(tx_flow_control);
9137 ESTAT_ADD(tx_mac_errors);
9138 ESTAT_ADD(tx_single_collisions);
9139 ESTAT_ADD(tx_mult_collisions);
9140 ESTAT_ADD(tx_deferred);
9141 ESTAT_ADD(tx_excessive_collisions);
9142 ESTAT_ADD(tx_late_collisions);
9143 ESTAT_ADD(tx_collide_2times);
9144 ESTAT_ADD(tx_collide_3times);
9145 ESTAT_ADD(tx_collide_4times);
9146 ESTAT_ADD(tx_collide_5times);
9147 ESTAT_ADD(tx_collide_6times);
9148 ESTAT_ADD(tx_collide_7times);
9149 ESTAT_ADD(tx_collide_8times);
9150 ESTAT_ADD(tx_collide_9times);
9151 ESTAT_ADD(tx_collide_10times);
9152 ESTAT_ADD(tx_collide_11times);
9153 ESTAT_ADD(tx_collide_12times);
9154 ESTAT_ADD(tx_collide_13times);
9155 ESTAT_ADD(tx_collide_14times);
9156 ESTAT_ADD(tx_collide_15times);
9157 ESTAT_ADD(tx_ucast_packets);
9158 ESTAT_ADD(tx_mcast_packets);
9159 ESTAT_ADD(tx_bcast_packets);
9160 ESTAT_ADD(tx_carrier_sense_errors);
9161 ESTAT_ADD(tx_discards);
9162 ESTAT_ADD(tx_errors);
9163
9164 ESTAT_ADD(dma_writeq_full);
9165 ESTAT_ADD(dma_write_prioq_full);
9166 ESTAT_ADD(rxbds_empty);
9167 ESTAT_ADD(rx_discards);
9168 ESTAT_ADD(rx_errors);
9169 ESTAT_ADD(rx_threshold_hit);
9170
9171 ESTAT_ADD(dma_readq_full);
9172 ESTAT_ADD(dma_read_prioq_full);
9173 ESTAT_ADD(tx_comp_queue_full);
9174
9175 ESTAT_ADD(ring_set_send_prod_index);
9176 ESTAT_ADD(ring_status_update);
9177 ESTAT_ADD(nic_irqs);
9178 ESTAT_ADD(nic_avoided_irqs);
9179 ESTAT_ADD(nic_tx_threshold_hit);
9180
9181 return estats;
9182}
9183
9184static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9185 struct rtnl_link_stats64 *stats)
9186{
9187 struct tg3 *tp = netdev_priv(dev);
9188 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9189 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9190
9191 if (!hw_stats)
9192 return old_stats;
9193
9194 stats->rx_packets = old_stats->rx_packets +
9195 get_stat64(&hw_stats->rx_ucast_packets) +
9196 get_stat64(&hw_stats->rx_mcast_packets) +
9197 get_stat64(&hw_stats->rx_bcast_packets);
9198
9199 stats->tx_packets = old_stats->tx_packets +
9200 get_stat64(&hw_stats->tx_ucast_packets) +
9201 get_stat64(&hw_stats->tx_mcast_packets) +
9202 get_stat64(&hw_stats->tx_bcast_packets);
9203
9204 stats->rx_bytes = old_stats->rx_bytes +
9205 get_stat64(&hw_stats->rx_octets);
9206 stats->tx_bytes = old_stats->tx_bytes +
9207 get_stat64(&hw_stats->tx_octets);
9208
9209 stats->rx_errors = old_stats->rx_errors +
9210 get_stat64(&hw_stats->rx_errors);
9211 stats->tx_errors = old_stats->tx_errors +
9212 get_stat64(&hw_stats->tx_errors) +
9213 get_stat64(&hw_stats->tx_mac_errors) +
9214 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9215 get_stat64(&hw_stats->tx_discards);
9216
9217 stats->multicast = old_stats->multicast +
9218 get_stat64(&hw_stats->rx_mcast_packets);
9219 stats->collisions = old_stats->collisions +
9220 get_stat64(&hw_stats->tx_collisions);
9221
9222 stats->rx_length_errors = old_stats->rx_length_errors +
9223 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9224 get_stat64(&hw_stats->rx_undersize_packets);
9225
9226 stats->rx_over_errors = old_stats->rx_over_errors +
9227 get_stat64(&hw_stats->rxbds_empty);
9228 stats->rx_frame_errors = old_stats->rx_frame_errors +
9229 get_stat64(&hw_stats->rx_align_errors);
9230 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9231 get_stat64(&hw_stats->tx_discards);
9232 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9233 get_stat64(&hw_stats->tx_carrier_sense_errors);
9234
9235 stats->rx_crc_errors = old_stats->rx_crc_errors +
9236 calc_crc_errors(tp);
9237
9238 stats->rx_missed_errors = old_stats->rx_missed_errors +
9239 get_stat64(&hw_stats->rx_discards);
9240
9241 return stats;
9242}
9243
9244static inline u32 calc_crc(unsigned char *buf, int len)
9245{
9246 u32 reg;
9247 u32 tmp;
9248 int j, k;
9249
9250 reg = 0xffffffff;
9251
9252 for (j = 0; j < len; j++) {
9253 reg ^= buf[j];
9254
9255 for (k = 0; k < 8; k++) {
9256 tmp = reg & 0x01;
9257
9258 reg >>= 1;
9259
9260 if (tmp)
9261 reg ^= 0xedb88320;
9262 }
9263 }
9264
9265 return ~reg;
9266}
9267
9268static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9269{
9270 /* accept or reject all multicast frames */
9271 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9272 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9273 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9274 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9275}
9276
9277static void __tg3_set_rx_mode(struct net_device *dev)
9278{
9279 struct tg3 *tp = netdev_priv(dev);
9280 u32 rx_mode;
9281
9282 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9283 RX_MODE_KEEP_VLAN_TAG);
9284
9285 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9286 * flag clear.
9287 */
9288#if TG3_VLAN_TAG_USED
9289 if (!tp->vlgrp &&
9290 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9291 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9292#else
9293 /* By definition, VLAN is disabled always in this
9294 * case.
9295 */
9296 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9297 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9298#endif
9299
9300 if (dev->flags & IFF_PROMISC) {
9301 /* Promiscuous mode. */
9302 rx_mode |= RX_MODE_PROMISC;
9303 } else if (dev->flags & IFF_ALLMULTI) {
9304 /* Accept all multicast. */
9305 tg3_set_multi(tp, 1);
9306 } else if (netdev_mc_empty(dev)) {
9307 /* Reject all multicast. */
9308 tg3_set_multi(tp, 0);
9309 } else {
9310 /* Accept one or more multicast(s). */
9311 struct netdev_hw_addr *ha;
9312 u32 mc_filter[4] = { 0, };
9313 u32 regidx;
9314 u32 bit;
9315 u32 crc;
9316
9317 netdev_for_each_mc_addr(ha, dev) {
9318 crc = calc_crc(ha->addr, ETH_ALEN);
9319 bit = ~crc & 0x7f;
9320 regidx = (bit & 0x60) >> 5;
9321 bit &= 0x1f;
9322 mc_filter[regidx] |= (1 << bit);
9323 }
9324
9325 tw32(MAC_HASH_REG_0, mc_filter[0]);
9326 tw32(MAC_HASH_REG_1, mc_filter[1]);
9327 tw32(MAC_HASH_REG_2, mc_filter[2]);
9328 tw32(MAC_HASH_REG_3, mc_filter[3]);
9329 }
9330
9331 if (rx_mode != tp->rx_mode) {
9332 tp->rx_mode = rx_mode;
9333 tw32_f(MAC_RX_MODE, rx_mode);
9334 udelay(10);
9335 }
9336}
9337
9338static void tg3_set_rx_mode(struct net_device *dev)
9339{
9340 struct tg3 *tp = netdev_priv(dev);
9341
9342 if (!netif_running(dev))
9343 return;
9344
9345 tg3_full_lock(tp, 0);
9346 __tg3_set_rx_mode(dev);
9347 tg3_full_unlock(tp);
9348}
9349
9350#define TG3_REGDUMP_LEN (32 * 1024)
9351
9352static int tg3_get_regs_len(struct net_device *dev)
9353{
9354 return TG3_REGDUMP_LEN;
9355}
9356
9357static void tg3_get_regs(struct net_device *dev,
9358 struct ethtool_regs *regs, void *_p)
9359{
9360 u32 *p = _p;
9361 struct tg3 *tp = netdev_priv(dev);
9362 u8 *orig_p = _p;
9363 int i;
9364
9365 regs->version = 0;
9366
9367 memset(p, 0, TG3_REGDUMP_LEN);
9368
9369 if (tp->link_config.phy_is_low_power)
9370 return;
9371
9372 tg3_full_lock(tp, 0);
9373
9374#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9375#define GET_REG32_LOOP(base, len) \
9376do { p = (u32 *)(orig_p + (base)); \
9377 for (i = 0; i < len; i += 4) \
9378 __GET_REG32((base) + i); \
9379} while (0)
9380#define GET_REG32_1(reg) \
9381do { p = (u32 *)(orig_p + (reg)); \
9382 __GET_REG32((reg)); \
9383} while (0)
9384
9385 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9386 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9387 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9388 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9389 GET_REG32_1(SNDDATAC_MODE);
9390 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9391 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9392 GET_REG32_1(SNDBDC_MODE);
9393 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9394 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9395 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9396 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9397 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9398 GET_REG32_1(RCVDCC_MODE);
9399 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9400 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9401 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9402 GET_REG32_1(MBFREE_MODE);
9403 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9404 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9405 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9406 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9407 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9408 GET_REG32_1(RX_CPU_MODE);
9409 GET_REG32_1(RX_CPU_STATE);
9410 GET_REG32_1(RX_CPU_PGMCTR);
9411 GET_REG32_1(RX_CPU_HWBKPT);
9412 GET_REG32_1(TX_CPU_MODE);
9413 GET_REG32_1(TX_CPU_STATE);
9414 GET_REG32_1(TX_CPU_PGMCTR);
9415 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9416 GET_REG32_LOOP(FTQ_RESET, 0x120);
9417 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9418 GET_REG32_1(DMAC_MODE);
9419 GET_REG32_LOOP(GRC_MODE, 0x4c);
9420 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9421 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9422
9423#undef __GET_REG32
9424#undef GET_REG32_LOOP
9425#undef GET_REG32_1
9426
9427 tg3_full_unlock(tp);
9428}
9429
9430static int tg3_get_eeprom_len(struct net_device *dev)
9431{
9432 struct tg3 *tp = netdev_priv(dev);
9433
9434 return tp->nvram_size;
9435}
9436
9437static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9438{
9439 struct tg3 *tp = netdev_priv(dev);
9440 int ret;
9441 u8 *pd;
9442 u32 i, offset, len, b_offset, b_count;
9443 __be32 val;
9444
9445 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9446 return -EINVAL;
9447
9448 if (tp->link_config.phy_is_low_power)
9449 return -EAGAIN;
9450
9451 offset = eeprom->offset;
9452 len = eeprom->len;
9453 eeprom->len = 0;
9454
9455 eeprom->magic = TG3_EEPROM_MAGIC;
9456
9457 if (offset & 3) {
9458 /* adjustments to start on required 4 byte boundary */
9459 b_offset = offset & 3;
9460 b_count = 4 - b_offset;
9461 if (b_count > len) {
9462 /* i.e. offset=1 len=2 */
9463 b_count = len;
9464 }
9465 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9466 if (ret)
9467 return ret;
9468 memcpy(data, ((char *)&val) + b_offset, b_count);
9469 len -= b_count;
9470 offset += b_count;
9471 eeprom->len += b_count;
9472 }
9473
9474 /* read bytes upto the last 4 byte boundary */
9475 pd = &data[eeprom->len];
9476 for (i = 0; i < (len - (len & 3)); i += 4) {
9477 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9478 if (ret) {
9479 eeprom->len += i;
9480 return ret;
9481 }
9482 memcpy(pd + i, &val, 4);
9483 }
9484 eeprom->len += i;
9485
9486 if (len & 3) {
9487 /* read last bytes not ending on 4 byte boundary */
9488 pd = &data[eeprom->len];
9489 b_count = len & 3;
9490 b_offset = offset + len - b_count;
9491 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9492 if (ret)
9493 return ret;
9494 memcpy(pd, &val, b_count);
9495 eeprom->len += b_count;
9496 }
9497 return 0;
9498}
9499
9500static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9501
9502static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9503{
9504 struct tg3 *tp = netdev_priv(dev);
9505 int ret;
9506 u32 offset, len, b_offset, odd_len;
9507 u8 *buf;
9508 __be32 start, end;
9509
9510 if (tp->link_config.phy_is_low_power)
9511 return -EAGAIN;
9512
9513 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9514 eeprom->magic != TG3_EEPROM_MAGIC)
9515 return -EINVAL;
9516
9517 offset = eeprom->offset;
9518 len = eeprom->len;
9519
9520 if ((b_offset = (offset & 3))) {
9521 /* adjustments to start on required 4 byte boundary */
9522 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9523 if (ret)
9524 return ret;
9525 len += b_offset;
9526 offset &= ~3;
9527 if (len < 4)
9528 len = 4;
9529 }
9530
9531 odd_len = 0;
9532 if (len & 3) {
9533 /* adjustments to end on required 4 byte boundary */
9534 odd_len = 1;
9535 len = (len + 3) & ~3;
9536 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9537 if (ret)
9538 return ret;
9539 }
9540
9541 buf = data;
9542 if (b_offset || odd_len) {
9543 buf = kmalloc(len, GFP_KERNEL);
9544 if (!buf)
9545 return -ENOMEM;
9546 if (b_offset)
9547 memcpy(buf, &start, 4);
9548 if (odd_len)
9549 memcpy(buf+len-4, &end, 4);
9550 memcpy(buf + b_offset, data, eeprom->len);
9551 }
9552
9553 ret = tg3_nvram_write_block(tp, offset, len, buf);
9554
9555 if (buf != data)
9556 kfree(buf);
9557
9558 return ret;
9559}
9560
9561static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9562{
9563 struct tg3 *tp = netdev_priv(dev);
9564
9565 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9566 struct phy_device *phydev;
9567 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9568 return -EAGAIN;
9569 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9570 return phy_ethtool_gset(phydev, cmd);
9571 }
9572
9573 cmd->supported = (SUPPORTED_Autoneg);
9574
9575 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9576 cmd->supported |= (SUPPORTED_1000baseT_Half |
9577 SUPPORTED_1000baseT_Full);
9578
9579 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9580 cmd->supported |= (SUPPORTED_100baseT_Half |
9581 SUPPORTED_100baseT_Full |
9582 SUPPORTED_10baseT_Half |
9583 SUPPORTED_10baseT_Full |
9584 SUPPORTED_TP);
9585 cmd->port = PORT_TP;
9586 } else {
9587 cmd->supported |= SUPPORTED_FIBRE;
9588 cmd->port = PORT_FIBRE;
9589 }
9590
9591 cmd->advertising = tp->link_config.advertising;
9592 if (netif_running(dev)) {
9593 cmd->speed = tp->link_config.active_speed;
9594 cmd->duplex = tp->link_config.active_duplex;
9595 }
9596 cmd->phy_address = tp->phy_addr;
9597 cmd->transceiver = XCVR_INTERNAL;
9598 cmd->autoneg = tp->link_config.autoneg;
9599 cmd->maxtxpkt = 0;
9600 cmd->maxrxpkt = 0;
9601 return 0;
9602}
9603
9604static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9605{
9606 struct tg3 *tp = netdev_priv(dev);
9607
9608 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9609 struct phy_device *phydev;
9610 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9611 return -EAGAIN;
9612 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9613 return phy_ethtool_sset(phydev, cmd);
9614 }
9615
9616 if (cmd->autoneg != AUTONEG_ENABLE &&
9617 cmd->autoneg != AUTONEG_DISABLE)
9618 return -EINVAL;
9619
9620 if (cmd->autoneg == AUTONEG_DISABLE &&
9621 cmd->duplex != DUPLEX_FULL &&
9622 cmd->duplex != DUPLEX_HALF)
9623 return -EINVAL;
9624
9625 if (cmd->autoneg == AUTONEG_ENABLE) {
9626 u32 mask = ADVERTISED_Autoneg |
9627 ADVERTISED_Pause |
9628 ADVERTISED_Asym_Pause;
9629
9630 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9631 mask |= ADVERTISED_1000baseT_Half |
9632 ADVERTISED_1000baseT_Full;
9633
9634 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9635 mask |= ADVERTISED_100baseT_Half |
9636 ADVERTISED_100baseT_Full |
9637 ADVERTISED_10baseT_Half |
9638 ADVERTISED_10baseT_Full |
9639 ADVERTISED_TP;
9640 else
9641 mask |= ADVERTISED_FIBRE;
9642
9643 if (cmd->advertising & ~mask)
9644 return -EINVAL;
9645
9646 mask &= (ADVERTISED_1000baseT_Half |
9647 ADVERTISED_1000baseT_Full |
9648 ADVERTISED_100baseT_Half |
9649 ADVERTISED_100baseT_Full |
9650 ADVERTISED_10baseT_Half |
9651 ADVERTISED_10baseT_Full);
9652
9653 cmd->advertising &= mask;
9654 } else {
9655 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9656 if (cmd->speed != SPEED_1000)
9657 return -EINVAL;
9658
9659 if (cmd->duplex != DUPLEX_FULL)
9660 return -EINVAL;
9661 } else {
9662 if (cmd->speed != SPEED_100 &&
9663 cmd->speed != SPEED_10)
9664 return -EINVAL;
9665 }
9666 }
9667
9668 tg3_full_lock(tp, 0);
9669
9670 tp->link_config.autoneg = cmd->autoneg;
9671 if (cmd->autoneg == AUTONEG_ENABLE) {
9672 tp->link_config.advertising = (cmd->advertising |
9673 ADVERTISED_Autoneg);
9674 tp->link_config.speed = SPEED_INVALID;
9675 tp->link_config.duplex = DUPLEX_INVALID;
9676 } else {
9677 tp->link_config.advertising = 0;
9678 tp->link_config.speed = cmd->speed;
9679 tp->link_config.duplex = cmd->duplex;
9680 }
9681
9682 tp->link_config.orig_speed = tp->link_config.speed;
9683 tp->link_config.orig_duplex = tp->link_config.duplex;
9684 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9685
9686 if (netif_running(dev))
9687 tg3_setup_phy(tp, 1);
9688
9689 tg3_full_unlock(tp);
9690
9691 return 0;
9692}
9693
9694static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9695{
9696 struct tg3 *tp = netdev_priv(dev);
9697
9698 strcpy(info->driver, DRV_MODULE_NAME);
9699 strcpy(info->version, DRV_MODULE_VERSION);
9700 strcpy(info->fw_version, tp->fw_ver);
9701 strcpy(info->bus_info, pci_name(tp->pdev));
9702}
9703
9704static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9705{
9706 struct tg3 *tp = netdev_priv(dev);
9707
9708 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9709 device_can_wakeup(&tp->pdev->dev))
9710 wol->supported = WAKE_MAGIC;
9711 else
9712 wol->supported = 0;
9713 wol->wolopts = 0;
9714 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9715 device_can_wakeup(&tp->pdev->dev))
9716 wol->wolopts = WAKE_MAGIC;
9717 memset(&wol->sopass, 0, sizeof(wol->sopass));
9718}
9719
9720static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9721{
9722 struct tg3 *tp = netdev_priv(dev);
9723 struct device *dp = &tp->pdev->dev;
9724
9725 if (wol->wolopts & ~WAKE_MAGIC)
9726 return -EINVAL;
9727 if ((wol->wolopts & WAKE_MAGIC) &&
9728 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9729 return -EINVAL;
9730
9731 spin_lock_bh(&tp->lock);
9732 if (wol->wolopts & WAKE_MAGIC) {
9733 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9734 device_set_wakeup_enable(dp, true);
9735 } else {
9736 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9737 device_set_wakeup_enable(dp, false);
9738 }
9739 spin_unlock_bh(&tp->lock);
9740
9741 return 0;
9742}
9743
9744static u32 tg3_get_msglevel(struct net_device *dev)
9745{
9746 struct tg3 *tp = netdev_priv(dev);
9747 return tp->msg_enable;
9748}
9749
9750static void tg3_set_msglevel(struct net_device *dev, u32 value)
9751{
9752 struct tg3 *tp = netdev_priv(dev);
9753 tp->msg_enable = value;
9754}
9755
9756static int tg3_set_tso(struct net_device *dev, u32 value)
9757{
9758 struct tg3 *tp = netdev_priv(dev);
9759
9760 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9761 if (value)
9762 return -EINVAL;
9763 return 0;
9764 }
9765 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9766 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9767 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9768 if (value) {
9769 dev->features |= NETIF_F_TSO6;
9770 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9771 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9772 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9773 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9774 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9775 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9776 dev->features |= NETIF_F_TSO_ECN;
9777 } else
9778 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9779 }
9780 return ethtool_op_set_tso(dev, value);
9781}
9782
9783static int tg3_nway_reset(struct net_device *dev)
9784{
9785 struct tg3 *tp = netdev_priv(dev);
9786 int r;
9787
9788 if (!netif_running(dev))
9789 return -EAGAIN;
9790
9791 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9792 return -EINVAL;
9793
9794 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9795 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9796 return -EAGAIN;
9797 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9798 } else {
9799 u32 bmcr;
9800
9801 spin_lock_bh(&tp->lock);
9802 r = -EINVAL;
9803 tg3_readphy(tp, MII_BMCR, &bmcr);
9804 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9805 ((bmcr & BMCR_ANENABLE) ||
9806 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9807 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9808 BMCR_ANENABLE);
9809 r = 0;
9810 }
9811 spin_unlock_bh(&tp->lock);
9812 }
9813
9814 return r;
9815}
9816
9817static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9818{
9819 struct tg3 *tp = netdev_priv(dev);
9820
9821 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9822 ering->rx_mini_max_pending = 0;
9823 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9824 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9825 else
9826 ering->rx_jumbo_max_pending = 0;
9827
9828 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9829
9830 ering->rx_pending = tp->rx_pending;
9831 ering->rx_mini_pending = 0;
9832 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9833 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9834 else
9835 ering->rx_jumbo_pending = 0;
9836
9837 ering->tx_pending = tp->napi[0].tx_pending;
9838}
9839
9840static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9841{
9842 struct tg3 *tp = netdev_priv(dev);
9843 int i, irq_sync = 0, err = 0;
9844
9845 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9846 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9847 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9848 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9849 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9850 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9851 return -EINVAL;
9852
9853 if (netif_running(dev)) {
9854 tg3_phy_stop(tp);
9855 tg3_netif_stop(tp);
9856 irq_sync = 1;
9857 }
9858
9859 tg3_full_lock(tp, irq_sync);
9860
9861 tp->rx_pending = ering->rx_pending;
9862
9863 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9864 tp->rx_pending > 63)
9865 tp->rx_pending = 63;
9866 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9867
9868 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9869 tp->napi[i].tx_pending = ering->tx_pending;
9870
9871 if (netif_running(dev)) {
9872 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9873 err = tg3_restart_hw(tp, 1);
9874 if (!err)
9875 tg3_netif_start(tp);
9876 }
9877
9878 tg3_full_unlock(tp);
9879
9880 if (irq_sync && !err)
9881 tg3_phy_start(tp);
9882
9883 return err;
9884}
9885
9886static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9887{
9888 struct tg3 *tp = netdev_priv(dev);
9889
9890 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9891
9892 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9893 epause->rx_pause = 1;
9894 else
9895 epause->rx_pause = 0;
9896
9897 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9898 epause->tx_pause = 1;
9899 else
9900 epause->tx_pause = 0;
9901}
9902
9903static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9904{
9905 struct tg3 *tp = netdev_priv(dev);
9906 int err = 0;
9907
9908 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9909 u32 newadv;
9910 struct phy_device *phydev;
9911
9912 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9913
9914 if (!(phydev->supported & SUPPORTED_Pause) ||
9915 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9916 ((epause->rx_pause && !epause->tx_pause) ||
9917 (!epause->rx_pause && epause->tx_pause))))
9918 return -EINVAL;
9919
9920 tp->link_config.flowctrl = 0;
9921 if (epause->rx_pause) {
9922 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9923
9924 if (epause->tx_pause) {
9925 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9926 newadv = ADVERTISED_Pause;
9927 } else
9928 newadv = ADVERTISED_Pause |
9929 ADVERTISED_Asym_Pause;
9930 } else if (epause->tx_pause) {
9931 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9932 newadv = ADVERTISED_Asym_Pause;
9933 } else
9934 newadv = 0;
9935
9936 if (epause->autoneg)
9937 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9938 else
9939 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9940
9941 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9942 u32 oldadv = phydev->advertising &
9943 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9944 if (oldadv != newadv) {
9945 phydev->advertising &=
9946 ~(ADVERTISED_Pause |
9947 ADVERTISED_Asym_Pause);
9948 phydev->advertising |= newadv;
9949 if (phydev->autoneg) {
9950 /*
9951 * Always renegotiate the link to
9952 * inform our link partner of our
9953 * flow control settings, even if the
9954 * flow control is forced. Let
9955 * tg3_adjust_link() do the final
9956 * flow control setup.
9957 */
9958 return phy_start_aneg(phydev);
9959 }
9960 }
9961
9962 if (!epause->autoneg)
9963 tg3_setup_flow_control(tp, 0, 0);
9964 } else {
9965 tp->link_config.orig_advertising &=
9966 ~(ADVERTISED_Pause |
9967 ADVERTISED_Asym_Pause);
9968 tp->link_config.orig_advertising |= newadv;
9969 }
9970 } else {
9971 int irq_sync = 0;
9972
9973 if (netif_running(dev)) {
9974 tg3_netif_stop(tp);
9975 irq_sync = 1;
9976 }
9977
9978 tg3_full_lock(tp, irq_sync);
9979
9980 if (epause->autoneg)
9981 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9982 else
9983 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9984 if (epause->rx_pause)
9985 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9986 else
9987 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9988 if (epause->tx_pause)
9989 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9990 else
9991 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9992
9993 if (netif_running(dev)) {
9994 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9995 err = tg3_restart_hw(tp, 1);
9996 if (!err)
9997 tg3_netif_start(tp);
9998 }
9999
10000 tg3_full_unlock(tp);
10001 }
10002
10003 return err;
10004}
10005
10006static u32 tg3_get_rx_csum(struct net_device *dev)
10007{
10008 struct tg3 *tp = netdev_priv(dev);
10009 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10010}
10011
10012static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10013{
10014 struct tg3 *tp = netdev_priv(dev);
10015
10016 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10017 if (data != 0)
10018 return -EINVAL;
10019 return 0;
10020 }
10021
10022 spin_lock_bh(&tp->lock);
10023 if (data)
10024 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10025 else
10026 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10027 spin_unlock_bh(&tp->lock);
10028
10029 return 0;
10030}
10031
10032static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10033{
10034 struct tg3 *tp = netdev_priv(dev);
10035
10036 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10037 if (data != 0)
10038 return -EINVAL;
10039 return 0;
10040 }
10041
10042 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10043 ethtool_op_set_tx_ipv6_csum(dev, data);
10044 else
10045 ethtool_op_set_tx_csum(dev, data);
10046
10047 return 0;
10048}
10049
10050static int tg3_get_sset_count(struct net_device *dev, int sset)
10051{
10052 switch (sset) {
10053 case ETH_SS_TEST:
10054 return TG3_NUM_TEST;
10055 case ETH_SS_STATS:
10056 return TG3_NUM_STATS;
10057 default:
10058 return -EOPNOTSUPP;
10059 }
10060}
10061
10062static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10063{
10064 switch (stringset) {
10065 case ETH_SS_STATS:
10066 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10067 break;
10068 case ETH_SS_TEST:
10069 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10070 break;
10071 default:
10072 WARN_ON(1); /* we need a WARN() */
10073 break;
10074 }
10075}
10076
10077static int tg3_phys_id(struct net_device *dev, u32 data)
10078{
10079 struct tg3 *tp = netdev_priv(dev);
10080 int i;
10081
10082 if (!netif_running(tp->dev))
10083 return -EAGAIN;
10084
10085 if (data == 0)
10086 data = UINT_MAX / 2;
10087
10088 for (i = 0; i < (data * 2); i++) {
10089 if ((i % 2) == 0)
10090 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10091 LED_CTRL_1000MBPS_ON |
10092 LED_CTRL_100MBPS_ON |
10093 LED_CTRL_10MBPS_ON |
10094 LED_CTRL_TRAFFIC_OVERRIDE |
10095 LED_CTRL_TRAFFIC_BLINK |
10096 LED_CTRL_TRAFFIC_LED);
10097
10098 else
10099 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10100 LED_CTRL_TRAFFIC_OVERRIDE);
10101
10102 if (msleep_interruptible(500))
10103 break;
10104 }
10105 tw32(MAC_LED_CTRL, tp->led_ctrl);
10106 return 0;
10107}
10108
10109static void tg3_get_ethtool_stats(struct net_device *dev,
10110 struct ethtool_stats *estats, u64 *tmp_stats)
10111{
10112 struct tg3 *tp = netdev_priv(dev);
10113 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10114}
10115
10116#define NVRAM_TEST_SIZE 0x100
10117#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10118#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10119#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10120#define NVRAM_SELFBOOT_HW_SIZE 0x20
10121#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10122
10123static int tg3_test_nvram(struct tg3 *tp)
10124{
10125 u32 csum, magic;
10126 __be32 *buf;
10127 int i, j, k, err = 0, size;
10128
10129 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10130 return 0;
10131
10132 if (tg3_nvram_read(tp, 0, &magic) != 0)
10133 return -EIO;
10134
10135 if (magic == TG3_EEPROM_MAGIC)
10136 size = NVRAM_TEST_SIZE;
10137 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10138 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10139 TG3_EEPROM_SB_FORMAT_1) {
10140 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10141 case TG3_EEPROM_SB_REVISION_0:
10142 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10143 break;
10144 case TG3_EEPROM_SB_REVISION_2:
10145 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10146 break;
10147 case TG3_EEPROM_SB_REVISION_3:
10148 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10149 break;
10150 default:
10151 return 0;
10152 }
10153 } else
10154 return 0;
10155 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10156 size = NVRAM_SELFBOOT_HW_SIZE;
10157 else
10158 return -EIO;
10159
10160 buf = kmalloc(size, GFP_KERNEL);
10161 if (buf == NULL)
10162 return -ENOMEM;
10163
10164 err = -EIO;
10165 for (i = 0, j = 0; i < size; i += 4, j++) {
10166 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10167 if (err)
10168 break;
10169 }
10170 if (i < size)
10171 goto out;
10172
10173 /* Selfboot format */
10174 magic = be32_to_cpu(buf[0]);
10175 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10176 TG3_EEPROM_MAGIC_FW) {
10177 u8 *buf8 = (u8 *) buf, csum8 = 0;
10178
10179 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10180 TG3_EEPROM_SB_REVISION_2) {
10181 /* For rev 2, the csum doesn't include the MBA. */
10182 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10183 csum8 += buf8[i];
10184 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10185 csum8 += buf8[i];
10186 } else {
10187 for (i = 0; i < size; i++)
10188 csum8 += buf8[i];
10189 }
10190
10191 if (csum8 == 0) {
10192 err = 0;
10193 goto out;
10194 }
10195
10196 err = -EIO;
10197 goto out;
10198 }
10199
10200 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10201 TG3_EEPROM_MAGIC_HW) {
10202 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10203 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10204 u8 *buf8 = (u8 *) buf;
10205
10206 /* Separate the parity bits and the data bytes. */
10207 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10208 if ((i == 0) || (i == 8)) {
10209 int l;
10210 u8 msk;
10211
10212 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10213 parity[k++] = buf8[i] & msk;
10214 i++;
10215 } else if (i == 16) {
10216 int l;
10217 u8 msk;
10218
10219 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10220 parity[k++] = buf8[i] & msk;
10221 i++;
10222
10223 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10224 parity[k++] = buf8[i] & msk;
10225 i++;
10226 }
10227 data[j++] = buf8[i];
10228 }
10229
10230 err = -EIO;
10231 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10232 u8 hw8 = hweight8(data[i]);
10233
10234 if ((hw8 & 0x1) && parity[i])
10235 goto out;
10236 else if (!(hw8 & 0x1) && !parity[i])
10237 goto out;
10238 }
10239 err = 0;
10240 goto out;
10241 }
10242
10243 /* Bootstrap checksum at offset 0x10 */
10244 csum = calc_crc((unsigned char *) buf, 0x10);
10245 if (csum != be32_to_cpu(buf[0x10/4]))
10246 goto out;
10247
10248 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10249 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10250 if (csum != be32_to_cpu(buf[0xfc/4]))
10251 goto out;
10252
10253 err = 0;
10254
10255out:
10256 kfree(buf);
10257 return err;
10258}
10259
10260#define TG3_SERDES_TIMEOUT_SEC 2
10261#define TG3_COPPER_TIMEOUT_SEC 6
10262
10263static int tg3_test_link(struct tg3 *tp)
10264{
10265 int i, max;
10266
10267 if (!netif_running(tp->dev))
10268 return -ENODEV;
10269
10270 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10271 max = TG3_SERDES_TIMEOUT_SEC;
10272 else
10273 max = TG3_COPPER_TIMEOUT_SEC;
10274
10275 for (i = 0; i < max; i++) {
10276 if (netif_carrier_ok(tp->dev))
10277 return 0;
10278
10279 if (msleep_interruptible(1000))
10280 break;
10281 }
10282
10283 return -EIO;
10284}
10285
10286/* Only test the commonly used registers */
10287static int tg3_test_registers(struct tg3 *tp)
10288{
10289 int i, is_5705, is_5750;
10290 u32 offset, read_mask, write_mask, val, save_val, read_val;
10291 static struct {
10292 u16 offset;
10293 u16 flags;
10294#define TG3_FL_5705 0x1
10295#define TG3_FL_NOT_5705 0x2
10296#define TG3_FL_NOT_5788 0x4
10297#define TG3_FL_NOT_5750 0x8
10298 u32 read_mask;
10299 u32 write_mask;
10300 } reg_tbl[] = {
10301 /* MAC Control Registers */
10302 { MAC_MODE, TG3_FL_NOT_5705,
10303 0x00000000, 0x00ef6f8c },
10304 { MAC_MODE, TG3_FL_5705,
10305 0x00000000, 0x01ef6b8c },
10306 { MAC_STATUS, TG3_FL_NOT_5705,
10307 0x03800107, 0x00000000 },
10308 { MAC_STATUS, TG3_FL_5705,
10309 0x03800100, 0x00000000 },
10310 { MAC_ADDR_0_HIGH, 0x0000,
10311 0x00000000, 0x0000ffff },
10312 { MAC_ADDR_0_LOW, 0x0000,
10313 0x00000000, 0xffffffff },
10314 { MAC_RX_MTU_SIZE, 0x0000,
10315 0x00000000, 0x0000ffff },
10316 { MAC_TX_MODE, 0x0000,
10317 0x00000000, 0x00000070 },
10318 { MAC_TX_LENGTHS, 0x0000,
10319 0x00000000, 0x00003fff },
10320 { MAC_RX_MODE, TG3_FL_NOT_5705,
10321 0x00000000, 0x000007fc },
10322 { MAC_RX_MODE, TG3_FL_5705,
10323 0x00000000, 0x000007dc },
10324 { MAC_HASH_REG_0, 0x0000,
10325 0x00000000, 0xffffffff },
10326 { MAC_HASH_REG_1, 0x0000,
10327 0x00000000, 0xffffffff },
10328 { MAC_HASH_REG_2, 0x0000,
10329 0x00000000, 0xffffffff },
10330 { MAC_HASH_REG_3, 0x0000,
10331 0x00000000, 0xffffffff },
10332
10333 /* Receive Data and Receive BD Initiator Control Registers. */
10334 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10335 0x00000000, 0xffffffff },
10336 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10337 0x00000000, 0xffffffff },
10338 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10339 0x00000000, 0x00000003 },
10340 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10341 0x00000000, 0xffffffff },
10342 { RCVDBDI_STD_BD+0, 0x0000,
10343 0x00000000, 0xffffffff },
10344 { RCVDBDI_STD_BD+4, 0x0000,
10345 0x00000000, 0xffffffff },
10346 { RCVDBDI_STD_BD+8, 0x0000,
10347 0x00000000, 0xffff0002 },
10348 { RCVDBDI_STD_BD+0xc, 0x0000,
10349 0x00000000, 0xffffffff },
10350
10351 /* Receive BD Initiator Control Registers. */
10352 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10353 0x00000000, 0xffffffff },
10354 { RCVBDI_STD_THRESH, TG3_FL_5705,
10355 0x00000000, 0x000003ff },
10356 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10357 0x00000000, 0xffffffff },
10358
10359 /* Host Coalescing Control Registers. */
10360 { HOSTCC_MODE, TG3_FL_NOT_5705,
10361 0x00000000, 0x00000004 },
10362 { HOSTCC_MODE, TG3_FL_5705,
10363 0x00000000, 0x000000f6 },
10364 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10365 0x00000000, 0xffffffff },
10366 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10367 0x00000000, 0x000003ff },
10368 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10369 0x00000000, 0xffffffff },
10370 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10371 0x00000000, 0x000003ff },
10372 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10373 0x00000000, 0xffffffff },
10374 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10375 0x00000000, 0x000000ff },
10376 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10377 0x00000000, 0xffffffff },
10378 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10379 0x00000000, 0x000000ff },
10380 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10381 0x00000000, 0xffffffff },
10382 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10383 0x00000000, 0xffffffff },
10384 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10385 0x00000000, 0xffffffff },
10386 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10387 0x00000000, 0x000000ff },
10388 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10389 0x00000000, 0xffffffff },
10390 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10391 0x00000000, 0x000000ff },
10392 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10393 0x00000000, 0xffffffff },
10394 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10395 0x00000000, 0xffffffff },
10396 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10397 0x00000000, 0xffffffff },
10398 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10399 0x00000000, 0xffffffff },
10400 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10401 0x00000000, 0xffffffff },
10402 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10403 0xffffffff, 0x00000000 },
10404 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10405 0xffffffff, 0x00000000 },
10406
10407 /* Buffer Manager Control Registers. */
10408 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10409 0x00000000, 0x007fff80 },
10410 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10411 0x00000000, 0x007fffff },
10412 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10413 0x00000000, 0x0000003f },
10414 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10415 0x00000000, 0x000001ff },
10416 { BUFMGR_MB_HIGH_WATER, 0x0000,
10417 0x00000000, 0x000001ff },
10418 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10419 0xffffffff, 0x00000000 },
10420 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10421 0xffffffff, 0x00000000 },
10422
10423 /* Mailbox Registers */
10424 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10425 0x00000000, 0x000001ff },
10426 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10427 0x00000000, 0x000001ff },
10428 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10429 0x00000000, 0x000007ff },
10430 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10431 0x00000000, 0x000001ff },
10432
10433 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10434 };
10435
10436 is_5705 = is_5750 = 0;
10437 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10438 is_5705 = 1;
10439 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10440 is_5750 = 1;
10441 }
10442
10443 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10444 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10445 continue;
10446
10447 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10448 continue;
10449
10450 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10451 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10452 continue;
10453
10454 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10455 continue;
10456
10457 offset = (u32) reg_tbl[i].offset;
10458 read_mask = reg_tbl[i].read_mask;
10459 write_mask = reg_tbl[i].write_mask;
10460
10461 /* Save the original register content */
10462 save_val = tr32(offset);
10463
10464 /* Determine the read-only value. */
10465 read_val = save_val & read_mask;
10466
10467 /* Write zero to the register, then make sure the read-only bits
10468 * are not changed and the read/write bits are all zeros.
10469 */
10470 tw32(offset, 0);
10471
10472 val = tr32(offset);
10473
10474 /* Test the read-only and read/write bits. */
10475 if (((val & read_mask) != read_val) || (val & write_mask))
10476 goto out;
10477
10478 /* Write ones to all the bits defined by RdMask and WrMask, then
10479 * make sure the read-only bits are not changed and the
10480 * read/write bits are all ones.
10481 */
10482 tw32(offset, read_mask | write_mask);
10483
10484 val = tr32(offset);
10485
10486 /* Test the read-only bits. */
10487 if ((val & read_mask) != read_val)
10488 goto out;
10489
10490 /* Test the read/write bits. */
10491 if ((val & write_mask) != write_mask)
10492 goto out;
10493
10494 tw32(offset, save_val);
10495 }
10496
10497 return 0;
10498
10499out:
10500 if (netif_msg_hw(tp))
10501 netdev_err(tp->dev,
10502 "Register test failed at offset %x\n", offset);
10503 tw32(offset, save_val);
10504 return -EIO;
10505}
10506
10507static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10508{
10509 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10510 int i;
10511 u32 j;
10512
10513 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10514 for (j = 0; j < len; j += 4) {
10515 u32 val;
10516
10517 tg3_write_mem(tp, offset + j, test_pattern[i]);
10518 tg3_read_mem(tp, offset + j, &val);
10519 if (val != test_pattern[i])
10520 return -EIO;
10521 }
10522 }
10523 return 0;
10524}
10525
10526static int tg3_test_memory(struct tg3 *tp)
10527{
10528 static struct mem_entry {
10529 u32 offset;
10530 u32 len;
10531 } mem_tbl_570x[] = {
10532 { 0x00000000, 0x00b50},
10533 { 0x00002000, 0x1c000},
10534 { 0xffffffff, 0x00000}
10535 }, mem_tbl_5705[] = {
10536 { 0x00000100, 0x0000c},
10537 { 0x00000200, 0x00008},
10538 { 0x00004000, 0x00800},
10539 { 0x00006000, 0x01000},
10540 { 0x00008000, 0x02000},
10541 { 0x00010000, 0x0e000},
10542 { 0xffffffff, 0x00000}
10543 }, mem_tbl_5755[] = {
10544 { 0x00000200, 0x00008},
10545 { 0x00004000, 0x00800},
10546 { 0x00006000, 0x00800},
10547 { 0x00008000, 0x02000},
10548 { 0x00010000, 0x0c000},
10549 { 0xffffffff, 0x00000}
10550 }, mem_tbl_5906[] = {
10551 { 0x00000200, 0x00008},
10552 { 0x00004000, 0x00400},
10553 { 0x00006000, 0x00400},
10554 { 0x00008000, 0x01000},
10555 { 0x00010000, 0x01000},
10556 { 0xffffffff, 0x00000}
10557 }, mem_tbl_5717[] = {
10558 { 0x00000200, 0x00008},
10559 { 0x00010000, 0x0a000},
10560 { 0x00020000, 0x13c00},
10561 { 0xffffffff, 0x00000}
10562 }, mem_tbl_57765[] = {
10563 { 0x00000200, 0x00008},
10564 { 0x00004000, 0x00800},
10565 { 0x00006000, 0x09800},
10566 { 0x00010000, 0x0a000},
10567 { 0xffffffff, 0x00000}
10568 };
10569 struct mem_entry *mem_tbl;
10570 int err = 0;
10571 int i;
10572
10573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10574 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10575 mem_tbl = mem_tbl_5717;
10576 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10577 mem_tbl = mem_tbl_57765;
10578 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10579 mem_tbl = mem_tbl_5755;
10580 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10581 mem_tbl = mem_tbl_5906;
10582 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10583 mem_tbl = mem_tbl_5705;
10584 else
10585 mem_tbl = mem_tbl_570x;
10586
10587 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10588 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10589 if (err)
10590 break;
10591 }
10592
10593 return err;
10594}
10595
10596#define TG3_MAC_LOOPBACK 0
10597#define TG3_PHY_LOOPBACK 1
10598
10599static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10600{
10601 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10602 u32 desc_idx, coal_now;
10603 struct sk_buff *skb, *rx_skb;
10604 u8 *tx_data;
10605 dma_addr_t map;
10606 int num_pkts, tx_len, rx_len, i, err;
10607 struct tg3_rx_buffer_desc *desc;
10608 struct tg3_napi *tnapi, *rnapi;
10609 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10610
10611 tnapi = &tp->napi[0];
10612 rnapi = &tp->napi[0];
10613 if (tp->irq_cnt > 1) {
10614 rnapi = &tp->napi[1];
10615 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10616 tnapi = &tp->napi[1];
10617 }
10618 coal_now = tnapi->coal_now | rnapi->coal_now;
10619
10620 if (loopback_mode == TG3_MAC_LOOPBACK) {
10621 /* HW errata - mac loopback fails in some cases on 5780.
10622 * Normal traffic and PHY loopback are not affected by
10623 * errata.
10624 */
10625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10626 return 0;
10627
10628 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10629 MAC_MODE_PORT_INT_LPBACK;
10630 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10631 mac_mode |= MAC_MODE_LINK_POLARITY;
10632 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10633 mac_mode |= MAC_MODE_PORT_MODE_MII;
10634 else
10635 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10636 tw32(MAC_MODE, mac_mode);
10637 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10638 u32 val;
10639
10640 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10641 tg3_phy_fet_toggle_apd(tp, false);
10642 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10643 } else
10644 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10645
10646 tg3_phy_toggle_automdix(tp, 0);
10647
10648 tg3_writephy(tp, MII_BMCR, val);
10649 udelay(40);
10650
10651 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10652 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10653 tg3_writephy(tp, MII_TG3_FET_PTEST,
10654 MII_TG3_FET_PTEST_FRC_TX_LINK |
10655 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10656 /* The write needs to be flushed for the AC131 */
10657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10658 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10659 mac_mode |= MAC_MODE_PORT_MODE_MII;
10660 } else
10661 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10662
10663 /* reset to prevent losing 1st rx packet intermittently */
10664 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10665 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10666 udelay(10);
10667 tw32_f(MAC_RX_MODE, tp->rx_mode);
10668 }
10669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10670 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10671 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10672 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10673 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10674 mac_mode |= MAC_MODE_LINK_POLARITY;
10675 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10676 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10677 }
10678 tw32(MAC_MODE, mac_mode);
10679 } else {
10680 return -EINVAL;
10681 }
10682
10683 err = -EIO;
10684
10685 tx_len = 1514;
10686 skb = netdev_alloc_skb(tp->dev, tx_len);
10687 if (!skb)
10688 return -ENOMEM;
10689
10690 tx_data = skb_put(skb, tx_len);
10691 memcpy(tx_data, tp->dev->dev_addr, 6);
10692 memset(tx_data + 6, 0x0, 8);
10693
10694 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10695
10696 for (i = 14; i < tx_len; i++)
10697 tx_data[i] = (u8) (i & 0xff);
10698
10699 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10700 if (pci_dma_mapping_error(tp->pdev, map)) {
10701 dev_kfree_skb(skb);
10702 return -EIO;
10703 }
10704
10705 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10706 rnapi->coal_now);
10707
10708 udelay(10);
10709
10710 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10711
10712 num_pkts = 0;
10713
10714 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10715
10716 tnapi->tx_prod++;
10717 num_pkts++;
10718
10719 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10720 tr32_mailbox(tnapi->prodmbox);
10721
10722 udelay(10);
10723
10724 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10725 for (i = 0; i < 35; i++) {
10726 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10727 coal_now);
10728
10729 udelay(10);
10730
10731 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10732 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10733 if ((tx_idx == tnapi->tx_prod) &&
10734 (rx_idx == (rx_start_idx + num_pkts)))
10735 break;
10736 }
10737
10738 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10739 dev_kfree_skb(skb);
10740
10741 if (tx_idx != tnapi->tx_prod)
10742 goto out;
10743
10744 if (rx_idx != rx_start_idx + num_pkts)
10745 goto out;
10746
10747 desc = &rnapi->rx_rcb[rx_start_idx];
10748 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10749 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10750 if (opaque_key != RXD_OPAQUE_RING_STD)
10751 goto out;
10752
10753 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10754 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10755 goto out;
10756
10757 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10758 if (rx_len != tx_len)
10759 goto out;
10760
10761 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10762
10763 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10764 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10765
10766 for (i = 14; i < tx_len; i++) {
10767 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10768 goto out;
10769 }
10770 err = 0;
10771
10772 /* tg3_free_rings will unmap and free the rx_skb */
10773out:
10774 return err;
10775}
10776
10777#define TG3_MAC_LOOPBACK_FAILED 1
10778#define TG3_PHY_LOOPBACK_FAILED 2
10779#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10780 TG3_PHY_LOOPBACK_FAILED)
10781
10782static int tg3_test_loopback(struct tg3 *tp)
10783{
10784 int err = 0;
10785 u32 cpmuctrl = 0;
10786
10787 if (!netif_running(tp->dev))
10788 return TG3_LOOPBACK_FAILED;
10789
10790 err = tg3_reset_hw(tp, 1);
10791 if (err)
10792 return TG3_LOOPBACK_FAILED;
10793
10794 /* Turn off gphy autopowerdown. */
10795 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10796 tg3_phy_toggle_apd(tp, false);
10797
10798 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10799 int i;
10800 u32 status;
10801
10802 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10803
10804 /* Wait for up to 40 microseconds to acquire lock. */
10805 for (i = 0; i < 4; i++) {
10806 status = tr32(TG3_CPMU_MUTEX_GNT);
10807 if (status == CPMU_MUTEX_GNT_DRIVER)
10808 break;
10809 udelay(10);
10810 }
10811
10812 if (status != CPMU_MUTEX_GNT_DRIVER)
10813 return TG3_LOOPBACK_FAILED;
10814
10815 /* Turn off link-based power management. */
10816 cpmuctrl = tr32(TG3_CPMU_CTRL);
10817 tw32(TG3_CPMU_CTRL,
10818 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10819 CPMU_CTRL_LINK_AWARE_MODE));
10820 }
10821
10822 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10823 err |= TG3_MAC_LOOPBACK_FAILED;
10824
10825 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10826 tw32(TG3_CPMU_CTRL, cpmuctrl);
10827
10828 /* Release the mutex */
10829 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10830 }
10831
10832 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10833 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10834 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10835 err |= TG3_PHY_LOOPBACK_FAILED;
10836 }
10837
10838 /* Re-enable gphy autopowerdown. */
10839 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10840 tg3_phy_toggle_apd(tp, true);
10841
10842 return err;
10843}
10844
10845static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10846 u64 *data)
10847{
10848 struct tg3 *tp = netdev_priv(dev);
10849
10850 if (tp->link_config.phy_is_low_power)
10851 tg3_set_power_state(tp, PCI_D0);
10852
10853 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10854
10855 if (tg3_test_nvram(tp) != 0) {
10856 etest->flags |= ETH_TEST_FL_FAILED;
10857 data[0] = 1;
10858 }
10859 if (tg3_test_link(tp) != 0) {
10860 etest->flags |= ETH_TEST_FL_FAILED;
10861 data[1] = 1;
10862 }
10863 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10864 int err, err2 = 0, irq_sync = 0;
10865
10866 if (netif_running(dev)) {
10867 tg3_phy_stop(tp);
10868 tg3_netif_stop(tp);
10869 irq_sync = 1;
10870 }
10871
10872 tg3_full_lock(tp, irq_sync);
10873
10874 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10875 err = tg3_nvram_lock(tp);
10876 tg3_halt_cpu(tp, RX_CPU_BASE);
10877 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10878 tg3_halt_cpu(tp, TX_CPU_BASE);
10879 if (!err)
10880 tg3_nvram_unlock(tp);
10881
10882 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10883 tg3_phy_reset(tp);
10884
10885 if (tg3_test_registers(tp) != 0) {
10886 etest->flags |= ETH_TEST_FL_FAILED;
10887 data[2] = 1;
10888 }
10889 if (tg3_test_memory(tp) != 0) {
10890 etest->flags |= ETH_TEST_FL_FAILED;
10891 data[3] = 1;
10892 }
10893 if ((data[4] = tg3_test_loopback(tp)) != 0)
10894 etest->flags |= ETH_TEST_FL_FAILED;
10895
10896 tg3_full_unlock(tp);
10897
10898 if (tg3_test_interrupt(tp) != 0) {
10899 etest->flags |= ETH_TEST_FL_FAILED;
10900 data[5] = 1;
10901 }
10902
10903 tg3_full_lock(tp, 0);
10904
10905 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10906 if (netif_running(dev)) {
10907 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10908 err2 = tg3_restart_hw(tp, 1);
10909 if (!err2)
10910 tg3_netif_start(tp);
10911 }
10912
10913 tg3_full_unlock(tp);
10914
10915 if (irq_sync && !err2)
10916 tg3_phy_start(tp);
10917 }
10918 if (tp->link_config.phy_is_low_power)
10919 tg3_set_power_state(tp, PCI_D3hot);
10920
10921}
10922
10923static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10924{
10925 struct mii_ioctl_data *data = if_mii(ifr);
10926 struct tg3 *tp = netdev_priv(dev);
10927 int err;
10928
10929 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10930 struct phy_device *phydev;
10931 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10932 return -EAGAIN;
10933 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10934 return phy_mii_ioctl(phydev, ifr, cmd);
10935 }
10936
10937 switch (cmd) {
10938 case SIOCGMIIPHY:
10939 data->phy_id = tp->phy_addr;
10940
10941 /* fallthru */
10942 case SIOCGMIIREG: {
10943 u32 mii_regval;
10944
10945 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10946 break; /* We have no PHY */
10947
10948 if (tp->link_config.phy_is_low_power)
10949 return -EAGAIN;
10950
10951 spin_lock_bh(&tp->lock);
10952 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10953 spin_unlock_bh(&tp->lock);
10954
10955 data->val_out = mii_regval;
10956
10957 return err;
10958 }
10959
10960 case SIOCSMIIREG:
10961 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10962 break; /* We have no PHY */
10963
10964 if (tp->link_config.phy_is_low_power)
10965 return -EAGAIN;
10966
10967 spin_lock_bh(&tp->lock);
10968 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10969 spin_unlock_bh(&tp->lock);
10970
10971 return err;
10972
10973 default:
10974 /* do nothing */
10975 break;
10976 }
10977 return -EOPNOTSUPP;
10978}
10979
10980#if TG3_VLAN_TAG_USED
10981static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10982{
10983 struct tg3 *tp = netdev_priv(dev);
10984
10985 if (!netif_running(dev)) {
10986 tp->vlgrp = grp;
10987 return;
10988 }
10989
10990 tg3_netif_stop(tp);
10991
10992 tg3_full_lock(tp, 0);
10993
10994 tp->vlgrp = grp;
10995
10996 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10997 __tg3_set_rx_mode(dev);
10998
10999 tg3_netif_start(tp);
11000
11001 tg3_full_unlock(tp);
11002}
11003#endif
11004
11005static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11006{
11007 struct tg3 *tp = netdev_priv(dev);
11008
11009 memcpy(ec, &tp->coal, sizeof(*ec));
11010 return 0;
11011}
11012
11013static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11014{
11015 struct tg3 *tp = netdev_priv(dev);
11016 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11017 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11018
11019 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11020 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11021 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11022 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11023 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11024 }
11025
11026 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11027 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11028 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11029 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11030 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11031 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11032 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11033 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11034 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11035 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11036 return -EINVAL;
11037
11038 /* No rx interrupts will be generated if both are zero */
11039 if ((ec->rx_coalesce_usecs == 0) &&
11040 (ec->rx_max_coalesced_frames == 0))
11041 return -EINVAL;
11042
11043 /* No tx interrupts will be generated if both are zero */
11044 if ((ec->tx_coalesce_usecs == 0) &&
11045 (ec->tx_max_coalesced_frames == 0))
11046 return -EINVAL;
11047
11048 /* Only copy relevant parameters, ignore all others. */
11049 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11050 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11051 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11052 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11053 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11054 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11055 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11056 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11057 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11058
11059 if (netif_running(dev)) {
11060 tg3_full_lock(tp, 0);
11061 __tg3_set_coalesce(tp, &tp->coal);
11062 tg3_full_unlock(tp);
11063 }
11064 return 0;
11065}
11066
11067static const struct ethtool_ops tg3_ethtool_ops = {
11068 .get_settings = tg3_get_settings,
11069 .set_settings = tg3_set_settings,
11070 .get_drvinfo = tg3_get_drvinfo,
11071 .get_regs_len = tg3_get_regs_len,
11072 .get_regs = tg3_get_regs,
11073 .get_wol = tg3_get_wol,
11074 .set_wol = tg3_set_wol,
11075 .get_msglevel = tg3_get_msglevel,
11076 .set_msglevel = tg3_set_msglevel,
11077 .nway_reset = tg3_nway_reset,
11078 .get_link = ethtool_op_get_link,
11079 .get_eeprom_len = tg3_get_eeprom_len,
11080 .get_eeprom = tg3_get_eeprom,
11081 .set_eeprom = tg3_set_eeprom,
11082 .get_ringparam = tg3_get_ringparam,
11083 .set_ringparam = tg3_set_ringparam,
11084 .get_pauseparam = tg3_get_pauseparam,
11085 .set_pauseparam = tg3_set_pauseparam,
11086 .get_rx_csum = tg3_get_rx_csum,
11087 .set_rx_csum = tg3_set_rx_csum,
11088 .set_tx_csum = tg3_set_tx_csum,
11089 .set_sg = ethtool_op_set_sg,
11090 .set_tso = tg3_set_tso,
11091 .self_test = tg3_self_test,
11092 .get_strings = tg3_get_strings,
11093 .phys_id = tg3_phys_id,
11094 .get_ethtool_stats = tg3_get_ethtool_stats,
11095 .get_coalesce = tg3_get_coalesce,
11096 .set_coalesce = tg3_set_coalesce,
11097 .get_sset_count = tg3_get_sset_count,
11098};
11099
11100static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11101{
11102 u32 cursize, val, magic;
11103
11104 tp->nvram_size = EEPROM_CHIP_SIZE;
11105
11106 if (tg3_nvram_read(tp, 0, &magic) != 0)
11107 return;
11108
11109 if ((magic != TG3_EEPROM_MAGIC) &&
11110 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11111 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11112 return;
11113
11114 /*
11115 * Size the chip by reading offsets at increasing powers of two.
11116 * When we encounter our validation signature, we know the addressing
11117 * has wrapped around, and thus have our chip size.
11118 */
11119 cursize = 0x10;
11120
11121 while (cursize < tp->nvram_size) {
11122 if (tg3_nvram_read(tp, cursize, &val) != 0)
11123 return;
11124
11125 if (val == magic)
11126 break;
11127
11128 cursize <<= 1;
11129 }
11130
11131 tp->nvram_size = cursize;
11132}
11133
11134static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11135{
11136 u32 val;
11137
11138 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11139 tg3_nvram_read(tp, 0, &val) != 0)
11140 return;
11141
11142 /* Selfboot format */
11143 if (val != TG3_EEPROM_MAGIC) {
11144 tg3_get_eeprom_size(tp);
11145 return;
11146 }
11147
11148 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11149 if (val != 0) {
11150 /* This is confusing. We want to operate on the
11151 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11152 * call will read from NVRAM and byteswap the data
11153 * according to the byteswapping settings for all
11154 * other register accesses. This ensures the data we
11155 * want will always reside in the lower 16-bits.
11156 * However, the data in NVRAM is in LE format, which
11157 * means the data from the NVRAM read will always be
11158 * opposite the endianness of the CPU. The 16-bit
11159 * byteswap then brings the data to CPU endianness.
11160 */
11161 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11162 return;
11163 }
11164 }
11165 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11166}
11167
11168static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11169{
11170 u32 nvcfg1;
11171
11172 nvcfg1 = tr32(NVRAM_CFG1);
11173 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11174 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11175 } else {
11176 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11177 tw32(NVRAM_CFG1, nvcfg1);
11178 }
11179
11180 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11181 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11182 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11183 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11184 tp->nvram_jedecnum = JEDEC_ATMEL;
11185 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11186 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11187 break;
11188 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11189 tp->nvram_jedecnum = JEDEC_ATMEL;
11190 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11191 break;
11192 case FLASH_VENDOR_ATMEL_EEPROM:
11193 tp->nvram_jedecnum = JEDEC_ATMEL;
11194 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11195 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11196 break;
11197 case FLASH_VENDOR_ST:
11198 tp->nvram_jedecnum = JEDEC_ST;
11199 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11200 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11201 break;
11202 case FLASH_VENDOR_SAIFUN:
11203 tp->nvram_jedecnum = JEDEC_SAIFUN;
11204 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11205 break;
11206 case FLASH_VENDOR_SST_SMALL:
11207 case FLASH_VENDOR_SST_LARGE:
11208 tp->nvram_jedecnum = JEDEC_SST;
11209 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11210 break;
11211 }
11212 } else {
11213 tp->nvram_jedecnum = JEDEC_ATMEL;
11214 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11215 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11216 }
11217}
11218
11219static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11220{
11221 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11222 case FLASH_5752PAGE_SIZE_256:
11223 tp->nvram_pagesize = 256;
11224 break;
11225 case FLASH_5752PAGE_SIZE_512:
11226 tp->nvram_pagesize = 512;
11227 break;
11228 case FLASH_5752PAGE_SIZE_1K:
11229 tp->nvram_pagesize = 1024;
11230 break;
11231 case FLASH_5752PAGE_SIZE_2K:
11232 tp->nvram_pagesize = 2048;
11233 break;
11234 case FLASH_5752PAGE_SIZE_4K:
11235 tp->nvram_pagesize = 4096;
11236 break;
11237 case FLASH_5752PAGE_SIZE_264:
11238 tp->nvram_pagesize = 264;
11239 break;
11240 case FLASH_5752PAGE_SIZE_528:
11241 tp->nvram_pagesize = 528;
11242 break;
11243 }
11244}
11245
11246static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11247{
11248 u32 nvcfg1;
11249
11250 nvcfg1 = tr32(NVRAM_CFG1);
11251
11252 /* NVRAM protection for TPM */
11253 if (nvcfg1 & (1 << 27))
11254 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11255
11256 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11257 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11258 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11259 tp->nvram_jedecnum = JEDEC_ATMEL;
11260 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11261 break;
11262 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11263 tp->nvram_jedecnum = JEDEC_ATMEL;
11264 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11265 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11266 break;
11267 case FLASH_5752VENDOR_ST_M45PE10:
11268 case FLASH_5752VENDOR_ST_M45PE20:
11269 case FLASH_5752VENDOR_ST_M45PE40:
11270 tp->nvram_jedecnum = JEDEC_ST;
11271 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11272 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11273 break;
11274 }
11275
11276 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11277 tg3_nvram_get_pagesize(tp, nvcfg1);
11278 } else {
11279 /* For eeprom, set pagesize to maximum eeprom size */
11280 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11281
11282 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11283 tw32(NVRAM_CFG1, nvcfg1);
11284 }
11285}
11286
11287static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11288{
11289 u32 nvcfg1, protect = 0;
11290
11291 nvcfg1 = tr32(NVRAM_CFG1);
11292
11293 /* NVRAM protection for TPM */
11294 if (nvcfg1 & (1 << 27)) {
11295 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11296 protect = 1;
11297 }
11298
11299 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11300 switch (nvcfg1) {
11301 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11302 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11303 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11304 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11305 tp->nvram_jedecnum = JEDEC_ATMEL;
11306 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11307 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11308 tp->nvram_pagesize = 264;
11309 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11310 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11311 tp->nvram_size = (protect ? 0x3e200 :
11312 TG3_NVRAM_SIZE_512KB);
11313 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11314 tp->nvram_size = (protect ? 0x1f200 :
11315 TG3_NVRAM_SIZE_256KB);
11316 else
11317 tp->nvram_size = (protect ? 0x1f200 :
11318 TG3_NVRAM_SIZE_128KB);
11319 break;
11320 case FLASH_5752VENDOR_ST_M45PE10:
11321 case FLASH_5752VENDOR_ST_M45PE20:
11322 case FLASH_5752VENDOR_ST_M45PE40:
11323 tp->nvram_jedecnum = JEDEC_ST;
11324 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11325 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11326 tp->nvram_pagesize = 256;
11327 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11328 tp->nvram_size = (protect ?
11329 TG3_NVRAM_SIZE_64KB :
11330 TG3_NVRAM_SIZE_128KB);
11331 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11332 tp->nvram_size = (protect ?
11333 TG3_NVRAM_SIZE_64KB :
11334 TG3_NVRAM_SIZE_256KB);
11335 else
11336 tp->nvram_size = (protect ?
11337 TG3_NVRAM_SIZE_128KB :
11338 TG3_NVRAM_SIZE_512KB);
11339 break;
11340 }
11341}
11342
11343static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11344{
11345 u32 nvcfg1;
11346
11347 nvcfg1 = tr32(NVRAM_CFG1);
11348
11349 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11350 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11351 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11352 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11353 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11354 tp->nvram_jedecnum = JEDEC_ATMEL;
11355 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11356 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11357
11358 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11359 tw32(NVRAM_CFG1, nvcfg1);
11360 break;
11361 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11362 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11363 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11364 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11365 tp->nvram_jedecnum = JEDEC_ATMEL;
11366 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11367 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11368 tp->nvram_pagesize = 264;
11369 break;
11370 case FLASH_5752VENDOR_ST_M45PE10:
11371 case FLASH_5752VENDOR_ST_M45PE20:
11372 case FLASH_5752VENDOR_ST_M45PE40:
11373 tp->nvram_jedecnum = JEDEC_ST;
11374 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11375 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11376 tp->nvram_pagesize = 256;
11377 break;
11378 }
11379}
11380
11381static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11382{
11383 u32 nvcfg1, protect = 0;
11384
11385 nvcfg1 = tr32(NVRAM_CFG1);
11386
11387 /* NVRAM protection for TPM */
11388 if (nvcfg1 & (1 << 27)) {
11389 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11390 protect = 1;
11391 }
11392
11393 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11394 switch (nvcfg1) {
11395 case FLASH_5761VENDOR_ATMEL_ADB021D:
11396 case FLASH_5761VENDOR_ATMEL_ADB041D:
11397 case FLASH_5761VENDOR_ATMEL_ADB081D:
11398 case FLASH_5761VENDOR_ATMEL_ADB161D:
11399 case FLASH_5761VENDOR_ATMEL_MDB021D:
11400 case FLASH_5761VENDOR_ATMEL_MDB041D:
11401 case FLASH_5761VENDOR_ATMEL_MDB081D:
11402 case FLASH_5761VENDOR_ATMEL_MDB161D:
11403 tp->nvram_jedecnum = JEDEC_ATMEL;
11404 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11405 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11406 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11407 tp->nvram_pagesize = 256;
11408 break;
11409 case FLASH_5761VENDOR_ST_A_M45PE20:
11410 case FLASH_5761VENDOR_ST_A_M45PE40:
11411 case FLASH_5761VENDOR_ST_A_M45PE80:
11412 case FLASH_5761VENDOR_ST_A_M45PE16:
11413 case FLASH_5761VENDOR_ST_M_M45PE20:
11414 case FLASH_5761VENDOR_ST_M_M45PE40:
11415 case FLASH_5761VENDOR_ST_M_M45PE80:
11416 case FLASH_5761VENDOR_ST_M_M45PE16:
11417 tp->nvram_jedecnum = JEDEC_ST;
11418 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11419 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11420 tp->nvram_pagesize = 256;
11421 break;
11422 }
11423
11424 if (protect) {
11425 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11426 } else {
11427 switch (nvcfg1) {
11428 case FLASH_5761VENDOR_ATMEL_ADB161D:
11429 case FLASH_5761VENDOR_ATMEL_MDB161D:
11430 case FLASH_5761VENDOR_ST_A_M45PE16:
11431 case FLASH_5761VENDOR_ST_M_M45PE16:
11432 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11433 break;
11434 case FLASH_5761VENDOR_ATMEL_ADB081D:
11435 case FLASH_5761VENDOR_ATMEL_MDB081D:
11436 case FLASH_5761VENDOR_ST_A_M45PE80:
11437 case FLASH_5761VENDOR_ST_M_M45PE80:
11438 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11439 break;
11440 case FLASH_5761VENDOR_ATMEL_ADB041D:
11441 case FLASH_5761VENDOR_ATMEL_MDB041D:
11442 case FLASH_5761VENDOR_ST_A_M45PE40:
11443 case FLASH_5761VENDOR_ST_M_M45PE40:
11444 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11445 break;
11446 case FLASH_5761VENDOR_ATMEL_ADB021D:
11447 case FLASH_5761VENDOR_ATMEL_MDB021D:
11448 case FLASH_5761VENDOR_ST_A_M45PE20:
11449 case FLASH_5761VENDOR_ST_M_M45PE20:
11450 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11451 break;
11452 }
11453 }
11454}
11455
11456static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11457{
11458 tp->nvram_jedecnum = JEDEC_ATMEL;
11459 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11460 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11461}
11462
11463static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11464{
11465 u32 nvcfg1;
11466
11467 nvcfg1 = tr32(NVRAM_CFG1);
11468
11469 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11470 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11471 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11472 tp->nvram_jedecnum = JEDEC_ATMEL;
11473 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11474 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11475
11476 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11477 tw32(NVRAM_CFG1, nvcfg1);
11478 return;
11479 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11480 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11481 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11482 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11483 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11484 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11485 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11486 tp->nvram_jedecnum = JEDEC_ATMEL;
11487 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11488 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11489
11490 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11491 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11492 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11493 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11494 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11495 break;
11496 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11497 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11498 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11499 break;
11500 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11501 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11502 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11503 break;
11504 }
11505 break;
11506 case FLASH_5752VENDOR_ST_M45PE10:
11507 case FLASH_5752VENDOR_ST_M45PE20:
11508 case FLASH_5752VENDOR_ST_M45PE40:
11509 tp->nvram_jedecnum = JEDEC_ST;
11510 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11511 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11512
11513 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11514 case FLASH_5752VENDOR_ST_M45PE10:
11515 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11516 break;
11517 case FLASH_5752VENDOR_ST_M45PE20:
11518 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11519 break;
11520 case FLASH_5752VENDOR_ST_M45PE40:
11521 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11522 break;
11523 }
11524 break;
11525 default:
11526 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11527 return;
11528 }
11529
11530 tg3_nvram_get_pagesize(tp, nvcfg1);
11531 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11532 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11533}
11534
11535
11536static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11537{
11538 u32 nvcfg1;
11539
11540 nvcfg1 = tr32(NVRAM_CFG1);
11541
11542 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11543 case FLASH_5717VENDOR_ATMEL_EEPROM:
11544 case FLASH_5717VENDOR_MICRO_EEPROM:
11545 tp->nvram_jedecnum = JEDEC_ATMEL;
11546 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11547 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11548
11549 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11550 tw32(NVRAM_CFG1, nvcfg1);
11551 return;
11552 case FLASH_5717VENDOR_ATMEL_MDB011D:
11553 case FLASH_5717VENDOR_ATMEL_ADB011B:
11554 case FLASH_5717VENDOR_ATMEL_ADB011D:
11555 case FLASH_5717VENDOR_ATMEL_MDB021D:
11556 case FLASH_5717VENDOR_ATMEL_ADB021B:
11557 case FLASH_5717VENDOR_ATMEL_ADB021D:
11558 case FLASH_5717VENDOR_ATMEL_45USPT:
11559 tp->nvram_jedecnum = JEDEC_ATMEL;
11560 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11561 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11562
11563 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11564 case FLASH_5717VENDOR_ATMEL_MDB021D:
11565 case FLASH_5717VENDOR_ATMEL_ADB021B:
11566 case FLASH_5717VENDOR_ATMEL_ADB021D:
11567 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11568 break;
11569 default:
11570 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11571 break;
11572 }
11573 break;
11574 case FLASH_5717VENDOR_ST_M_M25PE10:
11575 case FLASH_5717VENDOR_ST_A_M25PE10:
11576 case FLASH_5717VENDOR_ST_M_M45PE10:
11577 case FLASH_5717VENDOR_ST_A_M45PE10:
11578 case FLASH_5717VENDOR_ST_M_M25PE20:
11579 case FLASH_5717VENDOR_ST_A_M25PE20:
11580 case FLASH_5717VENDOR_ST_M_M45PE20:
11581 case FLASH_5717VENDOR_ST_A_M45PE20:
11582 case FLASH_5717VENDOR_ST_25USPT:
11583 case FLASH_5717VENDOR_ST_45USPT:
11584 tp->nvram_jedecnum = JEDEC_ST;
11585 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11586 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11587
11588 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11589 case FLASH_5717VENDOR_ST_M_M25PE20:
11590 case FLASH_5717VENDOR_ST_A_M25PE20:
11591 case FLASH_5717VENDOR_ST_M_M45PE20:
11592 case FLASH_5717VENDOR_ST_A_M45PE20:
11593 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11594 break;
11595 default:
11596 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11597 break;
11598 }
11599 break;
11600 default:
11601 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11602 return;
11603 }
11604
11605 tg3_nvram_get_pagesize(tp, nvcfg1);
11606 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11607 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11608}
11609
11610/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11611static void __devinit tg3_nvram_init(struct tg3 *tp)
11612{
11613 tw32_f(GRC_EEPROM_ADDR,
11614 (EEPROM_ADDR_FSM_RESET |
11615 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11616 EEPROM_ADDR_CLKPERD_SHIFT)));
11617
11618 msleep(1);
11619
11620 /* Enable seeprom accesses. */
11621 tw32_f(GRC_LOCAL_CTRL,
11622 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11623 udelay(100);
11624
11625 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11626 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11627 tp->tg3_flags |= TG3_FLAG_NVRAM;
11628
11629 if (tg3_nvram_lock(tp)) {
11630 netdev_warn(tp->dev,
11631 "Cannot get nvram lock, %s failed\n",
11632 __func__);
11633 return;
11634 }
11635 tg3_enable_nvram_access(tp);
11636
11637 tp->nvram_size = 0;
11638
11639 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11640 tg3_get_5752_nvram_info(tp);
11641 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11642 tg3_get_5755_nvram_info(tp);
11643 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11644 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11645 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11646 tg3_get_5787_nvram_info(tp);
11647 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11648 tg3_get_5761_nvram_info(tp);
11649 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11650 tg3_get_5906_nvram_info(tp);
11651 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11652 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11653 tg3_get_57780_nvram_info(tp);
11654 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11655 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11656 tg3_get_5717_nvram_info(tp);
11657 else
11658 tg3_get_nvram_info(tp);
11659
11660 if (tp->nvram_size == 0)
11661 tg3_get_nvram_size(tp);
11662
11663 tg3_disable_nvram_access(tp);
11664 tg3_nvram_unlock(tp);
11665
11666 } else {
11667 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11668
11669 tg3_get_eeprom_size(tp);
11670 }
11671}
11672
11673static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11674 u32 offset, u32 len, u8 *buf)
11675{
11676 int i, j, rc = 0;
11677 u32 val;
11678
11679 for (i = 0; i < len; i += 4) {
11680 u32 addr;
11681 __be32 data;
11682
11683 addr = offset + i;
11684
11685 memcpy(&data, buf + i, 4);
11686
11687 /*
11688 * The SEEPROM interface expects the data to always be opposite
11689 * the native endian format. We accomplish this by reversing
11690 * all the operations that would have been performed on the
11691 * data from a call to tg3_nvram_read_be32().
11692 */
11693 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11694
11695 val = tr32(GRC_EEPROM_ADDR);
11696 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11697
11698 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11699 EEPROM_ADDR_READ);
11700 tw32(GRC_EEPROM_ADDR, val |
11701 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11702 (addr & EEPROM_ADDR_ADDR_MASK) |
11703 EEPROM_ADDR_START |
11704 EEPROM_ADDR_WRITE);
11705
11706 for (j = 0; j < 1000; j++) {
11707 val = tr32(GRC_EEPROM_ADDR);
11708
11709 if (val & EEPROM_ADDR_COMPLETE)
11710 break;
11711 msleep(1);
11712 }
11713 if (!(val & EEPROM_ADDR_COMPLETE)) {
11714 rc = -EBUSY;
11715 break;
11716 }
11717 }
11718
11719 return rc;
11720}
11721
11722/* offset and length are dword aligned */
11723static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11724 u8 *buf)
11725{
11726 int ret = 0;
11727 u32 pagesize = tp->nvram_pagesize;
11728 u32 pagemask = pagesize - 1;
11729 u32 nvram_cmd;
11730 u8 *tmp;
11731
11732 tmp = kmalloc(pagesize, GFP_KERNEL);
11733 if (tmp == NULL)
11734 return -ENOMEM;
11735
11736 while (len) {
11737 int j;
11738 u32 phy_addr, page_off, size;
11739
11740 phy_addr = offset & ~pagemask;
11741
11742 for (j = 0; j < pagesize; j += 4) {
11743 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11744 (__be32 *) (tmp + j));
11745 if (ret)
11746 break;
11747 }
11748 if (ret)
11749 break;
11750
11751 page_off = offset & pagemask;
11752 size = pagesize;
11753 if (len < size)
11754 size = len;
11755
11756 len -= size;
11757
11758 memcpy(tmp + page_off, buf, size);
11759
11760 offset = offset + (pagesize - page_off);
11761
11762 tg3_enable_nvram_access(tp);
11763
11764 /*
11765 * Before we can erase the flash page, we need
11766 * to issue a special "write enable" command.
11767 */
11768 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11769
11770 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11771 break;
11772
11773 /* Erase the target page */
11774 tw32(NVRAM_ADDR, phy_addr);
11775
11776 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11777 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11778
11779 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11780 break;
11781
11782 /* Issue another write enable to start the write. */
11783 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11784
11785 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11786 break;
11787
11788 for (j = 0; j < pagesize; j += 4) {
11789 __be32 data;
11790
11791 data = *((__be32 *) (tmp + j));
11792
11793 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11794
11795 tw32(NVRAM_ADDR, phy_addr + j);
11796
11797 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11798 NVRAM_CMD_WR;
11799
11800 if (j == 0)
11801 nvram_cmd |= NVRAM_CMD_FIRST;
11802 else if (j == (pagesize - 4))
11803 nvram_cmd |= NVRAM_CMD_LAST;
11804
11805 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11806 break;
11807 }
11808 if (ret)
11809 break;
11810 }
11811
11812 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11813 tg3_nvram_exec_cmd(tp, nvram_cmd);
11814
11815 kfree(tmp);
11816
11817 return ret;
11818}
11819
11820/* offset and length are dword aligned */
11821static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11822 u8 *buf)
11823{
11824 int i, ret = 0;
11825
11826 for (i = 0; i < len; i += 4, offset += 4) {
11827 u32 page_off, phy_addr, nvram_cmd;
11828 __be32 data;
11829
11830 memcpy(&data, buf + i, 4);
11831 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11832
11833 page_off = offset % tp->nvram_pagesize;
11834
11835 phy_addr = tg3_nvram_phys_addr(tp, offset);
11836
11837 tw32(NVRAM_ADDR, phy_addr);
11838
11839 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11840
11841 if (page_off == 0 || i == 0)
11842 nvram_cmd |= NVRAM_CMD_FIRST;
11843 if (page_off == (tp->nvram_pagesize - 4))
11844 nvram_cmd |= NVRAM_CMD_LAST;
11845
11846 if (i == (len - 4))
11847 nvram_cmd |= NVRAM_CMD_LAST;
11848
11849 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11850 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11851 (tp->nvram_jedecnum == JEDEC_ST) &&
11852 (nvram_cmd & NVRAM_CMD_FIRST)) {
11853
11854 if ((ret = tg3_nvram_exec_cmd(tp,
11855 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11856 NVRAM_CMD_DONE)))
11857
11858 break;
11859 }
11860 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11861 /* We always do complete word writes to eeprom. */
11862 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11863 }
11864
11865 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11866 break;
11867 }
11868 return ret;
11869}
11870
11871/* offset and length are dword aligned */
11872static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11873{
11874 int ret;
11875
11876 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11877 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11878 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11879 udelay(40);
11880 }
11881
11882 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11883 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11884 } else {
11885 u32 grc_mode;
11886
11887 ret = tg3_nvram_lock(tp);
11888 if (ret)
11889 return ret;
11890
11891 tg3_enable_nvram_access(tp);
11892 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11893 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11894 tw32(NVRAM_WRITE1, 0x406);
11895
11896 grc_mode = tr32(GRC_MODE);
11897 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11898
11899 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11900 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11901
11902 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11903 buf);
11904 } else {
11905 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11906 buf);
11907 }
11908
11909 grc_mode = tr32(GRC_MODE);
11910 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11911
11912 tg3_disable_nvram_access(tp);
11913 tg3_nvram_unlock(tp);
11914 }
11915
11916 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11917 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11918 udelay(40);
11919 }
11920
11921 return ret;
11922}
11923
11924struct subsys_tbl_ent {
11925 u16 subsys_vendor, subsys_devid;
11926 u32 phy_id;
11927};
11928
11929static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11930 /* Broadcom boards. */
11931 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11932 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11933 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11934 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11935 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11936 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11937 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11938 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11939 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11940 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11941 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11942 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11943 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11944 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11945 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11946 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11947 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11948 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11949 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11950 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11951 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11952 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11953
11954 /* 3com boards. */
11955 { TG3PCI_SUBVENDOR_ID_3COM,
11956 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11957 { TG3PCI_SUBVENDOR_ID_3COM,
11958 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11959 { TG3PCI_SUBVENDOR_ID_3COM,
11960 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11961 { TG3PCI_SUBVENDOR_ID_3COM,
11962 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11963 { TG3PCI_SUBVENDOR_ID_3COM,
11964 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11965
11966 /* DELL boards. */
11967 { TG3PCI_SUBVENDOR_ID_DELL,
11968 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11969 { TG3PCI_SUBVENDOR_ID_DELL,
11970 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11971 { TG3PCI_SUBVENDOR_ID_DELL,
11972 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11973 { TG3PCI_SUBVENDOR_ID_DELL,
11974 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11975
11976 /* Compaq boards. */
11977 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11978 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11979 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11980 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11981 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11982 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11983 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11984 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11985 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11986 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11987
11988 /* IBM boards. */
11989 { TG3PCI_SUBVENDOR_ID_IBM,
11990 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
11991};
11992
11993static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
11994{
11995 int i;
11996
11997 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11998 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11999 tp->pdev->subsystem_vendor) &&
12000 (subsys_id_to_phy_id[i].subsys_devid ==
12001 tp->pdev->subsystem_device))
12002 return &subsys_id_to_phy_id[i];
12003 }
12004 return NULL;
12005}
12006
12007static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12008{
12009 u32 val;
12010 u16 pmcsr;
12011
12012 /* On some early chips the SRAM cannot be accessed in D3hot state,
12013 * so need make sure we're in D0.
12014 */
12015 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12016 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12017 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12018 msleep(1);
12019
12020 /* Make sure register accesses (indirect or otherwise)
12021 * will function correctly.
12022 */
12023 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12024 tp->misc_host_ctrl);
12025
12026 /* The memory arbiter has to be enabled in order for SRAM accesses
12027 * to succeed. Normally on powerup the tg3 chip firmware will make
12028 * sure it is enabled, but other entities such as system netboot
12029 * code might disable it.
12030 */
12031 val = tr32(MEMARB_MODE);
12032 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12033
12034 tp->phy_id = TG3_PHY_ID_INVALID;
12035 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12036
12037 /* Assume an onboard device and WOL capable by default. */
12038 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12039
12040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12041 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12042 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12043 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12044 }
12045 val = tr32(VCPU_CFGSHDW);
12046 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12047 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12048 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12049 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12050 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12051 goto done;
12052 }
12053
12054 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12055 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12056 u32 nic_cfg, led_cfg;
12057 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12058 int eeprom_phy_serdes = 0;
12059
12060 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12061 tp->nic_sram_data_cfg = nic_cfg;
12062
12063 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12064 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12065 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12066 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12067 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12068 (ver > 0) && (ver < 0x100))
12069 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12070
12071 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12072 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12073
12074 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12075 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12076 eeprom_phy_serdes = 1;
12077
12078 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12079 if (nic_phy_id != 0) {
12080 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12081 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12082
12083 eeprom_phy_id = (id1 >> 16) << 10;
12084 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12085 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12086 } else
12087 eeprom_phy_id = 0;
12088
12089 tp->phy_id = eeprom_phy_id;
12090 if (eeprom_phy_serdes) {
12091 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12092 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12093 else
12094 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12095 }
12096
12097 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12098 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12099 SHASTA_EXT_LED_MODE_MASK);
12100 else
12101 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12102
12103 switch (led_cfg) {
12104 default:
12105 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12106 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12107 break;
12108
12109 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12110 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12111 break;
12112
12113 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12114 tp->led_ctrl = LED_CTRL_MODE_MAC;
12115
12116 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12117 * read on some older 5700/5701 bootcode.
12118 */
12119 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12120 ASIC_REV_5700 ||
12121 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12122 ASIC_REV_5701)
12123 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12124
12125 break;
12126
12127 case SHASTA_EXT_LED_SHARED:
12128 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12129 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12130 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12131 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12132 LED_CTRL_MODE_PHY_2);
12133 break;
12134
12135 case SHASTA_EXT_LED_MAC:
12136 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12137 break;
12138
12139 case SHASTA_EXT_LED_COMBO:
12140 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12141 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12142 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12143 LED_CTRL_MODE_PHY_2);
12144 break;
12145
12146 }
12147
12148 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12149 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12150 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12151 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12152
12153 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12154 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12155
12156 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12157 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12158 if ((tp->pdev->subsystem_vendor ==
12159 PCI_VENDOR_ID_ARIMA) &&
12160 (tp->pdev->subsystem_device == 0x205a ||
12161 tp->pdev->subsystem_device == 0x2063))
12162 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12163 } else {
12164 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12165 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12166 }
12167
12168 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12169 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12170 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12171 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12172 }
12173
12174 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12175 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12176 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12177
12178 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12179 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12180 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12181
12182 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12183 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12184 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12185
12186 if (cfg2 & (1 << 17))
12187 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12188
12189 /* serdes signal pre-emphasis in register 0x590 set by */
12190 /* bootcode if bit 18 is set */
12191 if (cfg2 & (1 << 18))
12192 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12193
12194 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12195 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12196 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12197 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12198
12199 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12200 u32 cfg3;
12201
12202 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12203 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12204 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12205 }
12206
12207 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12208 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12209 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12210 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12211 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12212 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12213 }
12214done:
12215 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12216 device_set_wakeup_enable(&tp->pdev->dev,
12217 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12218}
12219
12220static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12221{
12222 int i;
12223 u32 val;
12224
12225 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12226 tw32(OTP_CTRL, cmd);
12227
12228 /* Wait for up to 1 ms for command to execute. */
12229 for (i = 0; i < 100; i++) {
12230 val = tr32(OTP_STATUS);
12231 if (val & OTP_STATUS_CMD_DONE)
12232 break;
12233 udelay(10);
12234 }
12235
12236 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12237}
12238
12239/* Read the gphy configuration from the OTP region of the chip. The gphy
12240 * configuration is a 32-bit value that straddles the alignment boundary.
12241 * We do two 32-bit reads and then shift and merge the results.
12242 */
12243static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12244{
12245 u32 bhalf_otp, thalf_otp;
12246
12247 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12248
12249 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12250 return 0;
12251
12252 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12253
12254 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12255 return 0;
12256
12257 thalf_otp = tr32(OTP_READ_DATA);
12258
12259 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12260
12261 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12262 return 0;
12263
12264 bhalf_otp = tr32(OTP_READ_DATA);
12265
12266 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12267}
12268
12269static int __devinit tg3_phy_probe(struct tg3 *tp)
12270{
12271 u32 hw_phy_id_1, hw_phy_id_2;
12272 u32 hw_phy_id, hw_phy_id_masked;
12273 int err;
12274
12275 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12276 return tg3_phy_init(tp);
12277
12278 /* Reading the PHY ID register can conflict with ASF
12279 * firmware access to the PHY hardware.
12280 */
12281 err = 0;
12282 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12283 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12284 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12285 } else {
12286 /* Now read the physical PHY_ID from the chip and verify
12287 * that it is sane. If it doesn't look good, we fall back
12288 * to either the hard-coded table based PHY_ID and failing
12289 * that the value found in the eeprom area.
12290 */
12291 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12292 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12293
12294 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12295 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12296 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12297
12298 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12299 }
12300
12301 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12302 tp->phy_id = hw_phy_id;
12303 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12304 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12305 else
12306 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12307 } else {
12308 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12309 /* Do nothing, phy ID already set up in
12310 * tg3_get_eeprom_hw_cfg().
12311 */
12312 } else {
12313 struct subsys_tbl_ent *p;
12314
12315 /* No eeprom signature? Try the hardcoded
12316 * subsys device table.
12317 */
12318 p = tg3_lookup_by_subsys(tp);
12319 if (!p)
12320 return -ENODEV;
12321
12322 tp->phy_id = p->phy_id;
12323 if (!tp->phy_id ||
12324 tp->phy_id == TG3_PHY_ID_BCM8002)
12325 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12326 }
12327 }
12328
12329 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12330 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12331 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12332 u32 bmsr, adv_reg, tg3_ctrl, mask;
12333
12334 tg3_readphy(tp, MII_BMSR, &bmsr);
12335 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12336 (bmsr & BMSR_LSTATUS))
12337 goto skip_phy_reset;
12338
12339 err = tg3_phy_reset(tp);
12340 if (err)
12341 return err;
12342
12343 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12344 ADVERTISE_100HALF | ADVERTISE_100FULL |
12345 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12346 tg3_ctrl = 0;
12347 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12348 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12349 MII_TG3_CTRL_ADV_1000_FULL);
12350 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12351 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12352 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12353 MII_TG3_CTRL_ENABLE_AS_MASTER);
12354 }
12355
12356 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12357 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12358 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12359 if (!tg3_copper_is_advertising_all(tp, mask)) {
12360 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12361
12362 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12363 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12364
12365 tg3_writephy(tp, MII_BMCR,
12366 BMCR_ANENABLE | BMCR_ANRESTART);
12367 }
12368 tg3_phy_set_wirespeed(tp);
12369
12370 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12371 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12372 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12373 }
12374
12375skip_phy_reset:
12376 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12377 err = tg3_init_5401phy_dsp(tp);
12378 if (err)
12379 return err;
12380
12381 err = tg3_init_5401phy_dsp(tp);
12382 }
12383
12384 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12385 tp->link_config.advertising =
12386 (ADVERTISED_1000baseT_Half |
12387 ADVERTISED_1000baseT_Full |
12388 ADVERTISED_Autoneg |
12389 ADVERTISED_FIBRE);
12390 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12391 tp->link_config.advertising &=
12392 ~(ADVERTISED_1000baseT_Half |
12393 ADVERTISED_1000baseT_Full);
12394
12395 return err;
12396}
12397
12398static void __devinit tg3_read_vpd(struct tg3 *tp)
12399{
12400 u8 vpd_data[TG3_NVM_VPD_LEN];
12401 unsigned int block_end, rosize, len;
12402 int j, i = 0;
12403 u32 magic;
12404
12405 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12406 tg3_nvram_read(tp, 0x0, &magic))
12407 goto out_not_found;
12408
12409 if (magic == TG3_EEPROM_MAGIC) {
12410 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12411 u32 tmp;
12412
12413 /* The data is in little-endian format in NVRAM.
12414 * Use the big-endian read routines to preserve
12415 * the byte order as it exists in NVRAM.
12416 */
12417 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12418 goto out_not_found;
12419
12420 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12421 }
12422 } else {
12423 ssize_t cnt;
12424 unsigned int pos = 0;
12425
12426 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12427 cnt = pci_read_vpd(tp->pdev, pos,
12428 TG3_NVM_VPD_LEN - pos,
12429 &vpd_data[pos]);
12430 if (cnt == -ETIMEDOUT || -EINTR)
12431 cnt = 0;
12432 else if (cnt < 0)
12433 goto out_not_found;
12434 }
12435 if (pos != TG3_NVM_VPD_LEN)
12436 goto out_not_found;
12437 }
12438
12439 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12440 PCI_VPD_LRDT_RO_DATA);
12441 if (i < 0)
12442 goto out_not_found;
12443
12444 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12445 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12446 i += PCI_VPD_LRDT_TAG_SIZE;
12447
12448 if (block_end > TG3_NVM_VPD_LEN)
12449 goto out_not_found;
12450
12451 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12452 PCI_VPD_RO_KEYWORD_MFR_ID);
12453 if (j > 0) {
12454 len = pci_vpd_info_field_size(&vpd_data[j]);
12455
12456 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12457 if (j + len > block_end || len != 4 ||
12458 memcmp(&vpd_data[j], "1028", 4))
12459 goto partno;
12460
12461 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12462 PCI_VPD_RO_KEYWORD_VENDOR0);
12463 if (j < 0)
12464 goto partno;
12465
12466 len = pci_vpd_info_field_size(&vpd_data[j]);
12467
12468 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12469 if (j + len > block_end)
12470 goto partno;
12471
12472 memcpy(tp->fw_ver, &vpd_data[j], len);
12473 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12474 }
12475
12476partno:
12477 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12478 PCI_VPD_RO_KEYWORD_PARTNO);
12479 if (i < 0)
12480 goto out_not_found;
12481
12482 len = pci_vpd_info_field_size(&vpd_data[i]);
12483
12484 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12485 if (len > TG3_BPN_SIZE ||
12486 (len + i) > TG3_NVM_VPD_LEN)
12487 goto out_not_found;
12488
12489 memcpy(tp->board_part_number, &vpd_data[i], len);
12490
12491 return;
12492
12493out_not_found:
12494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12495 strcpy(tp->board_part_number, "BCM95906");
12496 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12497 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12498 strcpy(tp->board_part_number, "BCM57780");
12499 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12500 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12501 strcpy(tp->board_part_number, "BCM57760");
12502 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12503 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12504 strcpy(tp->board_part_number, "BCM57790");
12505 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12506 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12507 strcpy(tp->board_part_number, "BCM57788");
12508 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12509 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12510 strcpy(tp->board_part_number, "BCM57761");
12511 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12512 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12513 strcpy(tp->board_part_number, "BCM57765");
12514 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12515 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12516 strcpy(tp->board_part_number, "BCM57781");
12517 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12518 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12519 strcpy(tp->board_part_number, "BCM57785");
12520 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12521 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12522 strcpy(tp->board_part_number, "BCM57791");
12523 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12524 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12525 strcpy(tp->board_part_number, "BCM57795");
12526 else
12527 strcpy(tp->board_part_number, "none");
12528}
12529
12530static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12531{
12532 u32 val;
12533
12534 if (tg3_nvram_read(tp, offset, &val) ||
12535 (val & 0xfc000000) != 0x0c000000 ||
12536 tg3_nvram_read(tp, offset + 4, &val) ||
12537 val != 0)
12538 return 0;
12539
12540 return 1;
12541}
12542
12543static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12544{
12545 u32 val, offset, start, ver_offset;
12546 int i, dst_off;
12547 bool newver = false;
12548
12549 if (tg3_nvram_read(tp, 0xc, &offset) ||
12550 tg3_nvram_read(tp, 0x4, &start))
12551 return;
12552
12553 offset = tg3_nvram_logical_addr(tp, offset);
12554
12555 if (tg3_nvram_read(tp, offset, &val))
12556 return;
12557
12558 if ((val & 0xfc000000) == 0x0c000000) {
12559 if (tg3_nvram_read(tp, offset + 4, &val))
12560 return;
12561
12562 if (val == 0)
12563 newver = true;
12564 }
12565
12566 dst_off = strlen(tp->fw_ver);
12567
12568 if (newver) {
12569 if (TG3_VER_SIZE - dst_off < 16 ||
12570 tg3_nvram_read(tp, offset + 8, &ver_offset))
12571 return;
12572
12573 offset = offset + ver_offset - start;
12574 for (i = 0; i < 16; i += 4) {
12575 __be32 v;
12576 if (tg3_nvram_read_be32(tp, offset + i, &v))
12577 return;
12578
12579 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12580 }
12581 } else {
12582 u32 major, minor;
12583
12584 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12585 return;
12586
12587 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12588 TG3_NVM_BCVER_MAJSFT;
12589 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12590 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12591 "v%d.%02d", major, minor);
12592 }
12593}
12594
12595static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12596{
12597 u32 val, major, minor;
12598
12599 /* Use native endian representation */
12600 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12601 return;
12602
12603 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12604 TG3_NVM_HWSB_CFG1_MAJSFT;
12605 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12606 TG3_NVM_HWSB_CFG1_MINSFT;
12607
12608 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12609}
12610
12611static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12612{
12613 u32 offset, major, minor, build;
12614
12615 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12616
12617 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12618 return;
12619
12620 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12621 case TG3_EEPROM_SB_REVISION_0:
12622 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12623 break;
12624 case TG3_EEPROM_SB_REVISION_2:
12625 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12626 break;
12627 case TG3_EEPROM_SB_REVISION_3:
12628 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12629 break;
12630 case TG3_EEPROM_SB_REVISION_4:
12631 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12632 break;
12633 case TG3_EEPROM_SB_REVISION_5:
12634 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12635 break;
12636 default:
12637 return;
12638 }
12639
12640 if (tg3_nvram_read(tp, offset, &val))
12641 return;
12642
12643 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12644 TG3_EEPROM_SB_EDH_BLD_SHFT;
12645 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12646 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12647 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12648
12649 if (minor > 99 || build > 26)
12650 return;
12651
12652 offset = strlen(tp->fw_ver);
12653 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12654 " v%d.%02d", major, minor);
12655
12656 if (build > 0) {
12657 offset = strlen(tp->fw_ver);
12658 if (offset < TG3_VER_SIZE - 1)
12659 tp->fw_ver[offset] = 'a' + build - 1;
12660 }
12661}
12662
12663static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12664{
12665 u32 val, offset, start;
12666 int i, vlen;
12667
12668 for (offset = TG3_NVM_DIR_START;
12669 offset < TG3_NVM_DIR_END;
12670 offset += TG3_NVM_DIRENT_SIZE) {
12671 if (tg3_nvram_read(tp, offset, &val))
12672 return;
12673
12674 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12675 break;
12676 }
12677
12678 if (offset == TG3_NVM_DIR_END)
12679 return;
12680
12681 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12682 start = 0x08000000;
12683 else if (tg3_nvram_read(tp, offset - 4, &start))
12684 return;
12685
12686 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12687 !tg3_fw_img_is_valid(tp, offset) ||
12688 tg3_nvram_read(tp, offset + 8, &val))
12689 return;
12690
12691 offset += val - start;
12692
12693 vlen = strlen(tp->fw_ver);
12694
12695 tp->fw_ver[vlen++] = ',';
12696 tp->fw_ver[vlen++] = ' ';
12697
12698 for (i = 0; i < 4; i++) {
12699 __be32 v;
12700 if (tg3_nvram_read_be32(tp, offset, &v))
12701 return;
12702
12703 offset += sizeof(v);
12704
12705 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12706 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12707 break;
12708 }
12709
12710 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12711 vlen += sizeof(v);
12712 }
12713}
12714
12715static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12716{
12717 int vlen;
12718 u32 apedata;
12719
12720 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12721 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12722 return;
12723
12724 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12725 if (apedata != APE_SEG_SIG_MAGIC)
12726 return;
12727
12728 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12729 if (!(apedata & APE_FW_STATUS_READY))
12730 return;
12731
12732 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12733
12734 vlen = strlen(tp->fw_ver);
12735
12736 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12737 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12738 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12739 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12740 (apedata & APE_FW_VERSION_BLDMSK));
12741}
12742
12743static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12744{
12745 u32 val;
12746 bool vpd_vers = false;
12747
12748 if (tp->fw_ver[0] != 0)
12749 vpd_vers = true;
12750
12751 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12752 strcat(tp->fw_ver, "sb");
12753 return;
12754 }
12755
12756 if (tg3_nvram_read(tp, 0, &val))
12757 return;
12758
12759 if (val == TG3_EEPROM_MAGIC)
12760 tg3_read_bc_ver(tp);
12761 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12762 tg3_read_sb_ver(tp, val);
12763 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12764 tg3_read_hwsb_ver(tp);
12765 else
12766 return;
12767
12768 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12769 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12770 goto done;
12771
12772 tg3_read_mgmtfw_ver(tp);
12773
12774done:
12775 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12776}
12777
12778static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12779
12780static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12781{
12782#if TG3_VLAN_TAG_USED
12783 dev->vlan_features |= flags;
12784#endif
12785}
12786
12787static int __devinit tg3_get_invariants(struct tg3 *tp)
12788{
12789 static struct pci_device_id write_reorder_chipsets[] = {
12790 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12791 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12792 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12793 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12794 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12795 PCI_DEVICE_ID_VIA_8385_0) },
12796 { },
12797 };
12798 u32 misc_ctrl_reg;
12799 u32 pci_state_reg, grc_misc_cfg;
12800 u32 val;
12801 u16 pci_cmd;
12802 int err;
12803
12804 /* Force memory write invalidate off. If we leave it on,
12805 * then on 5700_BX chips we have to enable a workaround.
12806 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12807 * to match the cacheline size. The Broadcom driver have this
12808 * workaround but turns MWI off all the times so never uses
12809 * it. This seems to suggest that the workaround is insufficient.
12810 */
12811 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12812 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12813 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12814
12815 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12816 * has the register indirect write enable bit set before
12817 * we try to access any of the MMIO registers. It is also
12818 * critical that the PCI-X hw workaround situation is decided
12819 * before that as well.
12820 */
12821 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12822 &misc_ctrl_reg);
12823
12824 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12825 MISC_HOST_CTRL_CHIPREV_SHIFT);
12826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12827 u32 prod_id_asic_rev;
12828
12829 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12830 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12831 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12832 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12833 pci_read_config_dword(tp->pdev,
12834 TG3PCI_GEN2_PRODID_ASICREV,
12835 &prod_id_asic_rev);
12836 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12837 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12838 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12839 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12840 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12841 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12842 pci_read_config_dword(tp->pdev,
12843 TG3PCI_GEN15_PRODID_ASICREV,
12844 &prod_id_asic_rev);
12845 else
12846 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12847 &prod_id_asic_rev);
12848
12849 tp->pci_chip_rev_id = prod_id_asic_rev;
12850 }
12851
12852 /* Wrong chip ID in 5752 A0. This code can be removed later
12853 * as A0 is not in production.
12854 */
12855 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12856 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12857
12858 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12859 * we need to disable memory and use config. cycles
12860 * only to access all registers. The 5702/03 chips
12861 * can mistakenly decode the special cycles from the
12862 * ICH chipsets as memory write cycles, causing corruption
12863 * of register and memory space. Only certain ICH bridges
12864 * will drive special cycles with non-zero data during the
12865 * address phase which can fall within the 5703's address
12866 * range. This is not an ICH bug as the PCI spec allows
12867 * non-zero address during special cycles. However, only
12868 * these ICH bridges are known to drive non-zero addresses
12869 * during special cycles.
12870 *
12871 * Since special cycles do not cross PCI bridges, we only
12872 * enable this workaround if the 5703 is on the secondary
12873 * bus of these ICH bridges.
12874 */
12875 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12876 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12877 static struct tg3_dev_id {
12878 u32 vendor;
12879 u32 device;
12880 u32 rev;
12881 } ich_chipsets[] = {
12882 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12883 PCI_ANY_ID },
12884 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12885 PCI_ANY_ID },
12886 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12887 0xa },
12888 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12889 PCI_ANY_ID },
12890 { },
12891 };
12892 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12893 struct pci_dev *bridge = NULL;
12894
12895 while (pci_id->vendor != 0) {
12896 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12897 bridge);
12898 if (!bridge) {
12899 pci_id++;
12900 continue;
12901 }
12902 if (pci_id->rev != PCI_ANY_ID) {
12903 if (bridge->revision > pci_id->rev)
12904 continue;
12905 }
12906 if (bridge->subordinate &&
12907 (bridge->subordinate->number ==
12908 tp->pdev->bus->number)) {
12909
12910 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12911 pci_dev_put(bridge);
12912 break;
12913 }
12914 }
12915 }
12916
12917 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12918 static struct tg3_dev_id {
12919 u32 vendor;
12920 u32 device;
12921 } bridge_chipsets[] = {
12922 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12923 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12924 { },
12925 };
12926 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12927 struct pci_dev *bridge = NULL;
12928
12929 while (pci_id->vendor != 0) {
12930 bridge = pci_get_device(pci_id->vendor,
12931 pci_id->device,
12932 bridge);
12933 if (!bridge) {
12934 pci_id++;
12935 continue;
12936 }
12937 if (bridge->subordinate &&
12938 (bridge->subordinate->number <=
12939 tp->pdev->bus->number) &&
12940 (bridge->subordinate->subordinate >=
12941 tp->pdev->bus->number)) {
12942 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12943 pci_dev_put(bridge);
12944 break;
12945 }
12946 }
12947 }
12948
12949 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12950 * DMA addresses > 40-bit. This bridge may have other additional
12951 * 57xx devices behind it in some 4-port NIC designs for example.
12952 * Any tg3 device found behind the bridge will also need the 40-bit
12953 * DMA workaround.
12954 */
12955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12957 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12958 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12959 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12960 } else {
12961 struct pci_dev *bridge = NULL;
12962
12963 do {
12964 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12965 PCI_DEVICE_ID_SERVERWORKS_EPB,
12966 bridge);
12967 if (bridge && bridge->subordinate &&
12968 (bridge->subordinate->number <=
12969 tp->pdev->bus->number) &&
12970 (bridge->subordinate->subordinate >=
12971 tp->pdev->bus->number)) {
12972 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12973 pci_dev_put(bridge);
12974 break;
12975 }
12976 } while (bridge);
12977 }
12978
12979 /* Initialize misc host control in PCI block. */
12980 tp->misc_host_ctrl |= (misc_ctrl_reg &
12981 MISC_HOST_CTRL_CHIPREV);
12982 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12983 tp->misc_host_ctrl);
12984
12985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12988 tp->pdev_peer = tg3_find_peer(tp);
12989
12990 /* Intentionally exclude ASIC_REV_5906 */
12991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12993 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
12999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13000 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13001
13002 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13004 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13005 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13006 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13007 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13008
13009 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13010 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13011 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13012
13013 /* 5700 B0 chips do not support checksumming correctly due
13014 * to hardware bugs.
13015 */
13016 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13017 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13018 else {
13019 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13020
13021 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13022 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13023 features |= NETIF_F_IPV6_CSUM;
13024 tp->dev->features |= features;
13025 vlan_features_add(tp->dev, features);
13026 }
13027
13028 /* Determine TSO capabilities */
13029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13032 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13033 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13035 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13036 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13037 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13039 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13040 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13041 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13042 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13043 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13044 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13045 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13046 tp->fw_needed = FIRMWARE_TG3TSO5;
13047 else
13048 tp->fw_needed = FIRMWARE_TG3TSO;
13049 }
13050
13051 tp->irq_max = 1;
13052
13053 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13054 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13055 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13056 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13057 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13058 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13059 tp->pdev_peer == tp->pdev))
13060 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13061
13062 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13063 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13064 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13065 }
13066
13067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13068 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13070 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13071 tp->irq_max = TG3_IRQ_MAX_VECS;
13072 }
13073 }
13074
13075 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13076 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13077 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13078 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13079 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13080 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13081 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13082 }
13083
13084 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13087 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13088
13089 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13090 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13091 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13092 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13093
13094 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13095 &pci_state_reg);
13096
13097 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13098 if (tp->pcie_cap != 0) {
13099 u16 lnkctl;
13100
13101 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13102
13103 pcie_set_readrq(tp->pdev, 4096);
13104
13105 pci_read_config_word(tp->pdev,
13106 tp->pcie_cap + PCI_EXP_LNKCTL,
13107 &lnkctl);
13108 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13110 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13113 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13114 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13115 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13116 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13117 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13118 }
13119 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13120 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13121 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13122 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13123 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13124 if (!tp->pcix_cap) {
13125 dev_err(&tp->pdev->dev,
13126 "Cannot find PCI-X capability, aborting\n");
13127 return -EIO;
13128 }
13129
13130 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13131 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13132 }
13133
13134 /* If we have an AMD 762 or VIA K8T800 chipset, write
13135 * reordering to the mailbox registers done by the host
13136 * controller can cause major troubles. We read back from
13137 * every mailbox register write to force the writes to be
13138 * posted to the chip in order.
13139 */
13140 if (pci_dev_present(write_reorder_chipsets) &&
13141 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13142 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13143
13144 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13145 &tp->pci_cacheline_sz);
13146 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13147 &tp->pci_lat_timer);
13148 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13149 tp->pci_lat_timer < 64) {
13150 tp->pci_lat_timer = 64;
13151 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13152 tp->pci_lat_timer);
13153 }
13154
13155 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13156 /* 5700 BX chips need to have their TX producer index
13157 * mailboxes written twice to workaround a bug.
13158 */
13159 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13160
13161 /* If we are in PCI-X mode, enable register write workaround.
13162 *
13163 * The workaround is to use indirect register accesses
13164 * for all chip writes not to mailbox registers.
13165 */
13166 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13167 u32 pm_reg;
13168
13169 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13170
13171 /* The chip can have it's power management PCI config
13172 * space registers clobbered due to this bug.
13173 * So explicitly force the chip into D0 here.
13174 */
13175 pci_read_config_dword(tp->pdev,
13176 tp->pm_cap + PCI_PM_CTRL,
13177 &pm_reg);
13178 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13179 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13180 pci_write_config_dword(tp->pdev,
13181 tp->pm_cap + PCI_PM_CTRL,
13182 pm_reg);
13183
13184 /* Also, force SERR#/PERR# in PCI command. */
13185 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13186 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13187 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13188 }
13189 }
13190
13191 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13192 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13193 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13194 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13195
13196 /* Chip-specific fixup from Broadcom driver */
13197 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13198 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13199 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13200 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13201 }
13202
13203 /* Default fast path register access methods */
13204 tp->read32 = tg3_read32;
13205 tp->write32 = tg3_write32;
13206 tp->read32_mbox = tg3_read32;
13207 tp->write32_mbox = tg3_write32;
13208 tp->write32_tx_mbox = tg3_write32;
13209 tp->write32_rx_mbox = tg3_write32;
13210
13211 /* Various workaround register access methods */
13212 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13213 tp->write32 = tg3_write_indirect_reg32;
13214 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13215 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13216 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13217 /*
13218 * Back to back register writes can cause problems on these
13219 * chips, the workaround is to read back all reg writes
13220 * except those to mailbox regs.
13221 *
13222 * See tg3_write_indirect_reg32().
13223 */
13224 tp->write32 = tg3_write_flush_reg32;
13225 }
13226
13227 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13228 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13229 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13230 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13231 tp->write32_rx_mbox = tg3_write_flush_reg32;
13232 }
13233
13234 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13235 tp->read32 = tg3_read_indirect_reg32;
13236 tp->write32 = tg3_write_indirect_reg32;
13237 tp->read32_mbox = tg3_read_indirect_mbox;
13238 tp->write32_mbox = tg3_write_indirect_mbox;
13239 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13240 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13241
13242 iounmap(tp->regs);
13243 tp->regs = NULL;
13244
13245 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13246 pci_cmd &= ~PCI_COMMAND_MEMORY;
13247 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13248 }
13249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13250 tp->read32_mbox = tg3_read32_mbox_5906;
13251 tp->write32_mbox = tg3_write32_mbox_5906;
13252 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13253 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13254 }
13255
13256 if (tp->write32 == tg3_write_indirect_reg32 ||
13257 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13258 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13259 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13260 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13261
13262 /* Get eeprom hw config before calling tg3_set_power_state().
13263 * In particular, the TG3_FLG2_IS_NIC flag must be
13264 * determined before calling tg3_set_power_state() so that
13265 * we know whether or not to switch out of Vaux power.
13266 * When the flag is set, it means that GPIO1 is used for eeprom
13267 * write protect and also implies that it is a LOM where GPIOs
13268 * are not used to switch power.
13269 */
13270 tg3_get_eeprom_hw_cfg(tp);
13271
13272 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13273 /* Allow reads and writes to the
13274 * APE register and memory space.
13275 */
13276 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13277 PCISTATE_ALLOW_APE_SHMEM_WR |
13278 PCISTATE_ALLOW_APE_PSPACE_WR;
13279 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13280 pci_state_reg);
13281 }
13282
13283 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13284 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13286 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13287 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13288 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13289 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13290 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13291
13292 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13293 * GPIO1 driven high will bring 5700's external PHY out of reset.
13294 * It is also used as eeprom write protect on LOMs.
13295 */
13296 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13297 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13298 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13299 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13300 GRC_LCLCTRL_GPIO_OUTPUT1);
13301 /* Unused GPIO3 must be driven as output on 5752 because there
13302 * are no pull-up resistors on unused GPIO pins.
13303 */
13304 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13305 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13306
13307 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13310 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13311
13312 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13313 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13314 /* Turn off the debug UART. */
13315 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13316 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13317 /* Keep VMain power. */
13318 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13319 GRC_LCLCTRL_GPIO_OUTPUT0;
13320 }
13321
13322 /* Force the chip into D0. */
13323 err = tg3_set_power_state(tp, PCI_D0);
13324 if (err) {
13325 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13326 return err;
13327 }
13328
13329 /* Derive initial jumbo mode from MTU assigned in
13330 * ether_setup() via the alloc_etherdev() call
13331 */
13332 if (tp->dev->mtu > ETH_DATA_LEN &&
13333 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13334 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13335
13336 /* Determine WakeOnLan speed to use. */
13337 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13338 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13339 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13340 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13341 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13342 } else {
13343 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13344 }
13345
13346 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13347 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13348
13349 /* A few boards don't want Ethernet@WireSpeed phy feature */
13350 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13351 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13352 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13353 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13354 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13355 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13356 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13357
13358 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13359 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13360 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13361 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13362 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13363
13364 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13365 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13366 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13367 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13368 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13369 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
13370 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13371 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13372 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13373 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13374 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13375 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13376 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13377 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13378 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13379 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13380 } else
13381 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13382 }
13383
13384 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13385 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13386 tp->phy_otp = tg3_read_otp_phycfg(tp);
13387 if (tp->phy_otp == 0)
13388 tp->phy_otp = TG3_OTP_DEFAULT;
13389 }
13390
13391 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13392 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13393 else
13394 tp->mi_mode = MAC_MI_MODE_BASE;
13395
13396 tp->coalesce_mode = 0;
13397 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13398 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13399 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13400
13401 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13402 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13403 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13404
13405 err = tg3_mdio_init(tp);
13406 if (err)
13407 return err;
13408
13409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13410 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
13411 return -ENOTSUPP;
13412
13413 /* Initialize data/descriptor byte/word swapping. */
13414 val = tr32(GRC_MODE);
13415 val &= GRC_MODE_HOST_STACKUP;
13416 tw32(GRC_MODE, val | tp->grc_mode);
13417
13418 tg3_switch_clocks(tp);
13419
13420 /* Clear this out for sanity. */
13421 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13422
13423 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13424 &pci_state_reg);
13425 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13426 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13427 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13428
13429 if (chiprevid == CHIPREV_ID_5701_A0 ||
13430 chiprevid == CHIPREV_ID_5701_B0 ||
13431 chiprevid == CHIPREV_ID_5701_B2 ||
13432 chiprevid == CHIPREV_ID_5701_B5) {
13433 void __iomem *sram_base;
13434
13435 /* Write some dummy words into the SRAM status block
13436 * area, see if it reads back correctly. If the return
13437 * value is bad, force enable the PCIX workaround.
13438 */
13439 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13440
13441 writel(0x00000000, sram_base);
13442 writel(0x00000000, sram_base + 4);
13443 writel(0xffffffff, sram_base + 4);
13444 if (readl(sram_base) != 0x00000000)
13445 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13446 }
13447 }
13448
13449 udelay(50);
13450 tg3_nvram_init(tp);
13451
13452 grc_misc_cfg = tr32(GRC_MISC_CFG);
13453 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13454
13455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13456 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13457 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13458 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13459
13460 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13461 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13462 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13463 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13464 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13465 HOSTCC_MODE_CLRTICK_TXBD);
13466
13467 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13468 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13469 tp->misc_host_ctrl);
13470 }
13471
13472 /* Preserve the APE MAC_MODE bits */
13473 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13474 tp->mac_mode = tr32(MAC_MODE) |
13475 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13476 else
13477 tp->mac_mode = TG3_DEF_MAC_MODE;
13478
13479 /* these are limited to 10/100 only */
13480 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13481 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13482 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13483 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13484 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13485 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13486 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13487 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13488 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13489 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13490 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13491 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13492 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13493 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13494 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13495 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13496
13497 err = tg3_phy_probe(tp);
13498 if (err) {
13499 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13500 /* ... but do not return immediately ... */
13501 tg3_mdio_fini(tp);
13502 }
13503
13504 tg3_read_vpd(tp);
13505 tg3_read_fw_ver(tp);
13506
13507 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13508 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13509 } else {
13510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13511 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13512 else
13513 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13514 }
13515
13516 /* 5700 {AX,BX} chips have a broken status block link
13517 * change bit implementation, so we must use the
13518 * status register in those cases.
13519 */
13520 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13521 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13522 else
13523 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13524
13525 /* The led_ctrl is set during tg3_phy_probe, here we might
13526 * have to force the link status polling mechanism based
13527 * upon subsystem IDs.
13528 */
13529 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13531 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13532 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13533 TG3_FLAG_USE_LINKCHG_REG);
13534 }
13535
13536 /* For all SERDES we poll the MAC status register. */
13537 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13538 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13539 else
13540 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13541
13542 tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13543 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13545 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13546 tp->rx_offset -= NET_IP_ALIGN;
13547#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13548 tp->rx_copy_thresh = ~(u16)0;
13549#endif
13550 }
13551
13552 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13553
13554 /* Increment the rx prod index on the rx std ring by at most
13555 * 8 for these chips to workaround hw errata.
13556 */
13557 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13558 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13559 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13560 tp->rx_std_max_post = 8;
13561
13562 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13563 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13564 PCIE_PWR_MGMT_L1_THRESH_MSK;
13565
13566 return err;
13567}
13568
13569#ifdef CONFIG_SPARC
13570static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13571{
13572 struct net_device *dev = tp->dev;
13573 struct pci_dev *pdev = tp->pdev;
13574 struct device_node *dp = pci_device_to_OF_node(pdev);
13575 const unsigned char *addr;
13576 int len;
13577
13578 addr = of_get_property(dp, "local-mac-address", &len);
13579 if (addr && len == 6) {
13580 memcpy(dev->dev_addr, addr, 6);
13581 memcpy(dev->perm_addr, dev->dev_addr, 6);
13582 return 0;
13583 }
13584 return -ENODEV;
13585}
13586
13587static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13588{
13589 struct net_device *dev = tp->dev;
13590
13591 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13592 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13593 return 0;
13594}
13595#endif
13596
13597static int __devinit tg3_get_device_address(struct tg3 *tp)
13598{
13599 struct net_device *dev = tp->dev;
13600 u32 hi, lo, mac_offset;
13601 int addr_ok = 0;
13602
13603#ifdef CONFIG_SPARC
13604 if (!tg3_get_macaddr_sparc(tp))
13605 return 0;
13606#endif
13607
13608 mac_offset = 0x7c;
13609 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13610 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13611 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13612 mac_offset = 0xcc;
13613 if (tg3_nvram_lock(tp))
13614 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13615 else
13616 tg3_nvram_unlock(tp);
13617 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13618 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13619 if (PCI_FUNC(tp->pdev->devfn) & 1)
13620 mac_offset = 0xcc;
13621 if (PCI_FUNC(tp->pdev->devfn) > 1)
13622 mac_offset += 0x18c;
13623 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13624 mac_offset = 0x10;
13625
13626 /* First try to get it from MAC address mailbox. */
13627 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13628 if ((hi >> 16) == 0x484b) {
13629 dev->dev_addr[0] = (hi >> 8) & 0xff;
13630 dev->dev_addr[1] = (hi >> 0) & 0xff;
13631
13632 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13633 dev->dev_addr[2] = (lo >> 24) & 0xff;
13634 dev->dev_addr[3] = (lo >> 16) & 0xff;
13635 dev->dev_addr[4] = (lo >> 8) & 0xff;
13636 dev->dev_addr[5] = (lo >> 0) & 0xff;
13637
13638 /* Some old bootcode may report a 0 MAC address in SRAM */
13639 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13640 }
13641 if (!addr_ok) {
13642 /* Next, try NVRAM. */
13643 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13644 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13645 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13646 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13647 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13648 }
13649 /* Finally just fetch it out of the MAC control regs. */
13650 else {
13651 hi = tr32(MAC_ADDR_0_HIGH);
13652 lo = tr32(MAC_ADDR_0_LOW);
13653
13654 dev->dev_addr[5] = lo & 0xff;
13655 dev->dev_addr[4] = (lo >> 8) & 0xff;
13656 dev->dev_addr[3] = (lo >> 16) & 0xff;
13657 dev->dev_addr[2] = (lo >> 24) & 0xff;
13658 dev->dev_addr[1] = hi & 0xff;
13659 dev->dev_addr[0] = (hi >> 8) & 0xff;
13660 }
13661 }
13662
13663 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13664#ifdef CONFIG_SPARC
13665 if (!tg3_get_default_macaddr_sparc(tp))
13666 return 0;
13667#endif
13668 return -EINVAL;
13669 }
13670 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13671 return 0;
13672}
13673
13674#define BOUNDARY_SINGLE_CACHELINE 1
13675#define BOUNDARY_MULTI_CACHELINE 2
13676
13677static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13678{
13679 int cacheline_size;
13680 u8 byte;
13681 int goal;
13682
13683 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13684 if (byte == 0)
13685 cacheline_size = 1024;
13686 else
13687 cacheline_size = (int) byte * 4;
13688
13689 /* On 5703 and later chips, the boundary bits have no
13690 * effect.
13691 */
13692 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13693 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13694 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13695 goto out;
13696
13697#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13698 goal = BOUNDARY_MULTI_CACHELINE;
13699#else
13700#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13701 goal = BOUNDARY_SINGLE_CACHELINE;
13702#else
13703 goal = 0;
13704#endif
13705#endif
13706
13707 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13709 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13710 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13711 goto out;
13712 }
13713
13714 if (!goal)
13715 goto out;
13716
13717 /* PCI controllers on most RISC systems tend to disconnect
13718 * when a device tries to burst across a cache-line boundary.
13719 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13720 *
13721 * Unfortunately, for PCI-E there are only limited
13722 * write-side controls for this, and thus for reads
13723 * we will still get the disconnects. We'll also waste
13724 * these PCI cycles for both read and write for chips
13725 * other than 5700 and 5701 which do not implement the
13726 * boundary bits.
13727 */
13728 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13729 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13730 switch (cacheline_size) {
13731 case 16:
13732 case 32:
13733 case 64:
13734 case 128:
13735 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13736 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13737 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13738 } else {
13739 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13740 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13741 }
13742 break;
13743
13744 case 256:
13745 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13746 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13747 break;
13748
13749 default:
13750 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13751 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13752 break;
13753 }
13754 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13755 switch (cacheline_size) {
13756 case 16:
13757 case 32:
13758 case 64:
13759 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13760 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13761 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13762 break;
13763 }
13764 /* fallthrough */
13765 case 128:
13766 default:
13767 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13768 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13769 break;
13770 }
13771 } else {
13772 switch (cacheline_size) {
13773 case 16:
13774 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13775 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13776 DMA_RWCTRL_WRITE_BNDRY_16);
13777 break;
13778 }
13779 /* fallthrough */
13780 case 32:
13781 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13782 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13783 DMA_RWCTRL_WRITE_BNDRY_32);
13784 break;
13785 }
13786 /* fallthrough */
13787 case 64:
13788 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13789 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13790 DMA_RWCTRL_WRITE_BNDRY_64);
13791 break;
13792 }
13793 /* fallthrough */
13794 case 128:
13795 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13796 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13797 DMA_RWCTRL_WRITE_BNDRY_128);
13798 break;
13799 }
13800 /* fallthrough */
13801 case 256:
13802 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13803 DMA_RWCTRL_WRITE_BNDRY_256);
13804 break;
13805 case 512:
13806 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13807 DMA_RWCTRL_WRITE_BNDRY_512);
13808 break;
13809 case 1024:
13810 default:
13811 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13812 DMA_RWCTRL_WRITE_BNDRY_1024);
13813 break;
13814 }
13815 }
13816
13817out:
13818 return val;
13819}
13820
13821static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13822{
13823 struct tg3_internal_buffer_desc test_desc;
13824 u32 sram_dma_descs;
13825 int i, ret;
13826
13827 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13828
13829 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13830 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13831 tw32(RDMAC_STATUS, 0);
13832 tw32(WDMAC_STATUS, 0);
13833
13834 tw32(BUFMGR_MODE, 0);
13835 tw32(FTQ_RESET, 0);
13836
13837 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13838 test_desc.addr_lo = buf_dma & 0xffffffff;
13839 test_desc.nic_mbuf = 0x00002100;
13840 test_desc.len = size;
13841
13842 /*
13843 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13844 * the *second* time the tg3 driver was getting loaded after an
13845 * initial scan.
13846 *
13847 * Broadcom tells me:
13848 * ...the DMA engine is connected to the GRC block and a DMA
13849 * reset may affect the GRC block in some unpredictable way...
13850 * The behavior of resets to individual blocks has not been tested.
13851 *
13852 * Broadcom noted the GRC reset will also reset all sub-components.
13853 */
13854 if (to_device) {
13855 test_desc.cqid_sqid = (13 << 8) | 2;
13856
13857 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13858 udelay(40);
13859 } else {
13860 test_desc.cqid_sqid = (16 << 8) | 7;
13861
13862 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13863 udelay(40);
13864 }
13865 test_desc.flags = 0x00000005;
13866
13867 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13868 u32 val;
13869
13870 val = *(((u32 *)&test_desc) + i);
13871 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13872 sram_dma_descs + (i * sizeof(u32)));
13873 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13874 }
13875 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13876
13877 if (to_device)
13878 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13879 else
13880 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13881
13882 ret = -ENODEV;
13883 for (i = 0; i < 40; i++) {
13884 u32 val;
13885
13886 if (to_device)
13887 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13888 else
13889 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13890 if ((val & 0xffff) == sram_dma_descs) {
13891 ret = 0;
13892 break;
13893 }
13894
13895 udelay(100);
13896 }
13897
13898 return ret;
13899}
13900
13901#define TEST_BUFFER_SIZE 0x2000
13902
13903static int __devinit tg3_test_dma(struct tg3 *tp)
13904{
13905 dma_addr_t buf_dma;
13906 u32 *buf, saved_dma_rwctrl;
13907 int ret = 0;
13908
13909 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13910 if (!buf) {
13911 ret = -ENOMEM;
13912 goto out_nofree;
13913 }
13914
13915 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13916 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13917
13918 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13919
13920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13923 goto out;
13924
13925 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13926 /* DMA read watermark not used on PCIE */
13927 tp->dma_rwctrl |= 0x00180000;
13928 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13929 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13931 tp->dma_rwctrl |= 0x003f0000;
13932 else
13933 tp->dma_rwctrl |= 0x003f000f;
13934 } else {
13935 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13937 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13938 u32 read_water = 0x7;
13939
13940 /* If the 5704 is behind the EPB bridge, we can
13941 * do the less restrictive ONE_DMA workaround for
13942 * better performance.
13943 */
13944 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13946 tp->dma_rwctrl |= 0x8000;
13947 else if (ccval == 0x6 || ccval == 0x7)
13948 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13949
13950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13951 read_water = 4;
13952 /* Set bit 23 to enable PCIX hw bug fix */
13953 tp->dma_rwctrl |=
13954 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13955 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13956 (1 << 23);
13957 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13958 /* 5780 always in PCIX mode */
13959 tp->dma_rwctrl |= 0x00144000;
13960 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13961 /* 5714 always in PCIX mode */
13962 tp->dma_rwctrl |= 0x00148000;
13963 } else {
13964 tp->dma_rwctrl |= 0x001b000f;
13965 }
13966 }
13967
13968 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13970 tp->dma_rwctrl &= 0xfffffff0;
13971
13972 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13973 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13974 /* Remove this if it causes problems for some boards. */
13975 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13976
13977 /* On 5700/5701 chips, we need to set this bit.
13978 * Otherwise the chip will issue cacheline transactions
13979 * to streamable DMA memory with not all the byte
13980 * enables turned on. This is an error on several
13981 * RISC PCI controllers, in particular sparc64.
13982 *
13983 * On 5703/5704 chips, this bit has been reassigned
13984 * a different meaning. In particular, it is used
13985 * on those chips to enable a PCI-X workaround.
13986 */
13987 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13988 }
13989
13990 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13991
13992#if 0
13993 /* Unneeded, already done by tg3_get_invariants. */
13994 tg3_switch_clocks(tp);
13995#endif
13996
13997 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13998 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13999 goto out;
14000
14001 /* It is best to perform DMA test with maximum write burst size
14002 * to expose the 5700/5701 write DMA bug.
14003 */
14004 saved_dma_rwctrl = tp->dma_rwctrl;
14005 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14006 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14007
14008 while (1) {
14009 u32 *p = buf, i;
14010
14011 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14012 p[i] = i;
14013
14014 /* Send the buffer to the chip. */
14015 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14016 if (ret) {
14017 dev_err(&tp->pdev->dev,
14018 "%s: Buffer write failed. err = %d\n",
14019 __func__, ret);
14020 break;
14021 }
14022
14023#if 0
14024 /* validate data reached card RAM correctly. */
14025 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14026 u32 val;
14027 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14028 if (le32_to_cpu(val) != p[i]) {
14029 dev_err(&tp->pdev->dev,
14030 "%s: Buffer corrupted on device! "
14031 "(%d != %d)\n", __func__, val, i);
14032 /* ret = -ENODEV here? */
14033 }
14034 p[i] = 0;
14035 }
14036#endif
14037 /* Now read it back. */
14038 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14039 if (ret) {
14040 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14041 "err = %d\n", __func__, ret);
14042 break;
14043 }
14044
14045 /* Verify it. */
14046 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14047 if (p[i] == i)
14048 continue;
14049
14050 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14051 DMA_RWCTRL_WRITE_BNDRY_16) {
14052 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14053 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14054 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14055 break;
14056 } else {
14057 dev_err(&tp->pdev->dev,
14058 "%s: Buffer corrupted on read back! "
14059 "(%d != %d)\n", __func__, p[i], i);
14060 ret = -ENODEV;
14061 goto out;
14062 }
14063 }
14064
14065 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14066 /* Success. */
14067 ret = 0;
14068 break;
14069 }
14070 }
14071 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14072 DMA_RWCTRL_WRITE_BNDRY_16) {
14073 static struct pci_device_id dma_wait_state_chipsets[] = {
14074 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14075 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14076 { },
14077 };
14078
14079 /* DMA test passed without adjusting DMA boundary,
14080 * now look for chipsets that are known to expose the
14081 * DMA bug without failing the test.
14082 */
14083 if (pci_dev_present(dma_wait_state_chipsets)) {
14084 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14085 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14086 } else {
14087 /* Safe to use the calculated DMA boundary. */
14088 tp->dma_rwctrl = saved_dma_rwctrl;
14089 }
14090
14091 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14092 }
14093
14094out:
14095 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14096out_nofree:
14097 return ret;
14098}
14099
14100static void __devinit tg3_init_link_config(struct tg3 *tp)
14101{
14102 tp->link_config.advertising =
14103 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14104 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14105 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14106 ADVERTISED_Autoneg | ADVERTISED_MII);
14107 tp->link_config.speed = SPEED_INVALID;
14108 tp->link_config.duplex = DUPLEX_INVALID;
14109 tp->link_config.autoneg = AUTONEG_ENABLE;
14110 tp->link_config.active_speed = SPEED_INVALID;
14111 tp->link_config.active_duplex = DUPLEX_INVALID;
14112 tp->link_config.phy_is_low_power = 0;
14113 tp->link_config.orig_speed = SPEED_INVALID;
14114 tp->link_config.orig_duplex = DUPLEX_INVALID;
14115 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14116}
14117
14118static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14119{
14120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14121 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14122 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14123 tp->bufmgr_config.mbuf_read_dma_low_water =
14124 DEFAULT_MB_RDMA_LOW_WATER_5705;
14125 tp->bufmgr_config.mbuf_mac_rx_low_water =
14126 DEFAULT_MB_MACRX_LOW_WATER_57765;
14127 tp->bufmgr_config.mbuf_high_water =
14128 DEFAULT_MB_HIGH_WATER_57765;
14129
14130 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14131 DEFAULT_MB_RDMA_LOW_WATER_5705;
14132 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14133 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14134 tp->bufmgr_config.mbuf_high_water_jumbo =
14135 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14136 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14137 tp->bufmgr_config.mbuf_read_dma_low_water =
14138 DEFAULT_MB_RDMA_LOW_WATER_5705;
14139 tp->bufmgr_config.mbuf_mac_rx_low_water =
14140 DEFAULT_MB_MACRX_LOW_WATER_5705;
14141 tp->bufmgr_config.mbuf_high_water =
14142 DEFAULT_MB_HIGH_WATER_5705;
14143 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14144 tp->bufmgr_config.mbuf_mac_rx_low_water =
14145 DEFAULT_MB_MACRX_LOW_WATER_5906;
14146 tp->bufmgr_config.mbuf_high_water =
14147 DEFAULT_MB_HIGH_WATER_5906;
14148 }
14149
14150 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14151 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14152 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14153 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14154 tp->bufmgr_config.mbuf_high_water_jumbo =
14155 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14156 } else {
14157 tp->bufmgr_config.mbuf_read_dma_low_water =
14158 DEFAULT_MB_RDMA_LOW_WATER;
14159 tp->bufmgr_config.mbuf_mac_rx_low_water =
14160 DEFAULT_MB_MACRX_LOW_WATER;
14161 tp->bufmgr_config.mbuf_high_water =
14162 DEFAULT_MB_HIGH_WATER;
14163
14164 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14165 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14166 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14167 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14168 tp->bufmgr_config.mbuf_high_water_jumbo =
14169 DEFAULT_MB_HIGH_WATER_JUMBO;
14170 }
14171
14172 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14173 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14174}
14175
14176static char * __devinit tg3_phy_string(struct tg3 *tp)
14177{
14178 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14179 case TG3_PHY_ID_BCM5400: return "5400";
14180 case TG3_PHY_ID_BCM5401: return "5401";
14181 case TG3_PHY_ID_BCM5411: return "5411";
14182 case TG3_PHY_ID_BCM5701: return "5701";
14183 case TG3_PHY_ID_BCM5703: return "5703";
14184 case TG3_PHY_ID_BCM5704: return "5704";
14185 case TG3_PHY_ID_BCM5705: return "5705";
14186 case TG3_PHY_ID_BCM5750: return "5750";
14187 case TG3_PHY_ID_BCM5752: return "5752";
14188 case TG3_PHY_ID_BCM5714: return "5714";
14189 case TG3_PHY_ID_BCM5780: return "5780";
14190 case TG3_PHY_ID_BCM5755: return "5755";
14191 case TG3_PHY_ID_BCM5787: return "5787";
14192 case TG3_PHY_ID_BCM5784: return "5784";
14193 case TG3_PHY_ID_BCM5756: return "5722/5756";
14194 case TG3_PHY_ID_BCM5906: return "5906";
14195 case TG3_PHY_ID_BCM5761: return "5761";
14196 case TG3_PHY_ID_BCM5718C: return "5718C";
14197 case TG3_PHY_ID_BCM5718S: return "5718S";
14198 case TG3_PHY_ID_BCM57765: return "57765";
14199 case TG3_PHY_ID_BCM5719C: return "5719C";
14200 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14201 case 0: return "serdes";
14202 default: return "unknown";
14203 }
14204}
14205
14206static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14207{
14208 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14209 strcpy(str, "PCI Express");
14210 return str;
14211 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14212 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14213
14214 strcpy(str, "PCIX:");
14215
14216 if ((clock_ctrl == 7) ||
14217 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14218 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14219 strcat(str, "133MHz");
14220 else if (clock_ctrl == 0)
14221 strcat(str, "33MHz");
14222 else if (clock_ctrl == 2)
14223 strcat(str, "50MHz");
14224 else if (clock_ctrl == 4)
14225 strcat(str, "66MHz");
14226 else if (clock_ctrl == 6)
14227 strcat(str, "100MHz");
14228 } else {
14229 strcpy(str, "PCI:");
14230 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14231 strcat(str, "66MHz");
14232 else
14233 strcat(str, "33MHz");
14234 }
14235 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14236 strcat(str, ":32-bit");
14237 else
14238 strcat(str, ":64-bit");
14239 return str;
14240}
14241
14242static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14243{
14244 struct pci_dev *peer;
14245 unsigned int func, devnr = tp->pdev->devfn & ~7;
14246
14247 for (func = 0; func < 8; func++) {
14248 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14249 if (peer && peer != tp->pdev)
14250 break;
14251 pci_dev_put(peer);
14252 }
14253 /* 5704 can be configured in single-port mode, set peer to
14254 * tp->pdev in that case.
14255 */
14256 if (!peer) {
14257 peer = tp->pdev;
14258 return peer;
14259 }
14260
14261 /*
14262 * We don't need to keep the refcount elevated; there's no way
14263 * to remove one half of this device without removing the other
14264 */
14265 pci_dev_put(peer);
14266
14267 return peer;
14268}
14269
14270static void __devinit tg3_init_coal(struct tg3 *tp)
14271{
14272 struct ethtool_coalesce *ec = &tp->coal;
14273
14274 memset(ec, 0, sizeof(*ec));
14275 ec->cmd = ETHTOOL_GCOALESCE;
14276 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14277 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14278 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14279 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14280 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14281 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14282 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14283 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14284 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14285
14286 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14287 HOSTCC_MODE_CLRTICK_TXBD)) {
14288 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14289 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14290 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14291 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14292 }
14293
14294 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14295 ec->rx_coalesce_usecs_irq = 0;
14296 ec->tx_coalesce_usecs_irq = 0;
14297 ec->stats_block_coalesce_usecs = 0;
14298 }
14299}
14300
14301static const struct net_device_ops tg3_netdev_ops = {
14302 .ndo_open = tg3_open,
14303 .ndo_stop = tg3_close,
14304 .ndo_start_xmit = tg3_start_xmit,
14305 .ndo_get_stats64 = tg3_get_stats64,
14306 .ndo_validate_addr = eth_validate_addr,
14307 .ndo_set_multicast_list = tg3_set_rx_mode,
14308 .ndo_set_mac_address = tg3_set_mac_addr,
14309 .ndo_do_ioctl = tg3_ioctl,
14310 .ndo_tx_timeout = tg3_tx_timeout,
14311 .ndo_change_mtu = tg3_change_mtu,
14312#if TG3_VLAN_TAG_USED
14313 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14314#endif
14315#ifdef CONFIG_NET_POLL_CONTROLLER
14316 .ndo_poll_controller = tg3_poll_controller,
14317#endif
14318};
14319
14320static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14321 .ndo_open = tg3_open,
14322 .ndo_stop = tg3_close,
14323 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14324 .ndo_get_stats64 = tg3_get_stats64,
14325 .ndo_validate_addr = eth_validate_addr,
14326 .ndo_set_multicast_list = tg3_set_rx_mode,
14327 .ndo_set_mac_address = tg3_set_mac_addr,
14328 .ndo_do_ioctl = tg3_ioctl,
14329 .ndo_tx_timeout = tg3_tx_timeout,
14330 .ndo_change_mtu = tg3_change_mtu,
14331#if TG3_VLAN_TAG_USED
14332 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14333#endif
14334#ifdef CONFIG_NET_POLL_CONTROLLER
14335 .ndo_poll_controller = tg3_poll_controller,
14336#endif
14337};
14338
14339static int __devinit tg3_init_one(struct pci_dev *pdev,
14340 const struct pci_device_id *ent)
14341{
14342 struct net_device *dev;
14343 struct tg3 *tp;
14344 int i, err, pm_cap;
14345 u32 sndmbx, rcvmbx, intmbx;
14346 char str[40];
14347 u64 dma_mask, persist_dma_mask;
14348
14349 printk_once(KERN_INFO "%s\n", version);
14350
14351 err = pci_enable_device(pdev);
14352 if (err) {
14353 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14354 return err;
14355 }
14356
14357 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14358 if (err) {
14359 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14360 goto err_out_disable_pdev;
14361 }
14362
14363 pci_set_master(pdev);
14364
14365 /* Find power-management capability. */
14366 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14367 if (pm_cap == 0) {
14368 dev_err(&pdev->dev,
14369 "Cannot find Power Management capability, aborting\n");
14370 err = -EIO;
14371 goto err_out_free_res;
14372 }
14373
14374 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14375 if (!dev) {
14376 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14377 err = -ENOMEM;
14378 goto err_out_free_res;
14379 }
14380
14381 SET_NETDEV_DEV(dev, &pdev->dev);
14382
14383#if TG3_VLAN_TAG_USED
14384 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14385#endif
14386
14387 tp = netdev_priv(dev);
14388 tp->pdev = pdev;
14389 tp->dev = dev;
14390 tp->pm_cap = pm_cap;
14391 tp->rx_mode = TG3_DEF_RX_MODE;
14392 tp->tx_mode = TG3_DEF_TX_MODE;
14393
14394 if (tg3_debug > 0)
14395 tp->msg_enable = tg3_debug;
14396 else
14397 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14398
14399 /* The word/byte swap controls here control register access byte
14400 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14401 * setting below.
14402 */
14403 tp->misc_host_ctrl =
14404 MISC_HOST_CTRL_MASK_PCI_INT |
14405 MISC_HOST_CTRL_WORD_SWAP |
14406 MISC_HOST_CTRL_INDIR_ACCESS |
14407 MISC_HOST_CTRL_PCISTATE_RW;
14408
14409 /* The NONFRM (non-frame) byte/word swap controls take effect
14410 * on descriptor entries, anything which isn't packet data.
14411 *
14412 * The StrongARM chips on the board (one for tx, one for rx)
14413 * are running in big-endian mode.
14414 */
14415 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14416 GRC_MODE_WSWAP_NONFRM_DATA);
14417#ifdef __BIG_ENDIAN
14418 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14419#endif
14420 spin_lock_init(&tp->lock);
14421 spin_lock_init(&tp->indirect_lock);
14422 INIT_WORK(&tp->reset_task, tg3_reset_task);
14423
14424 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14425 if (!tp->regs) {
14426 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14427 err = -ENOMEM;
14428 goto err_out_free_dev;
14429 }
14430
14431 tg3_init_link_config(tp);
14432
14433 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14434 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14435
14436 dev->ethtool_ops = &tg3_ethtool_ops;
14437 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14438 dev->irq = pdev->irq;
14439
14440 err = tg3_get_invariants(tp);
14441 if (err) {
14442 dev_err(&pdev->dev,
14443 "Problem fetching invariants of chip, aborting\n");
14444 goto err_out_iounmap;
14445 }
14446
14447 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14448 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
14449 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14450 dev->netdev_ops = &tg3_netdev_ops;
14451 else
14452 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14453
14454
14455 /* The EPB bridge inside 5714, 5715, and 5780 and any
14456 * device behind the EPB cannot support DMA addresses > 40-bit.
14457 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14458 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14459 * do DMA address check in tg3_start_xmit().
14460 */
14461 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14462 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14463 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14464 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14465#ifdef CONFIG_HIGHMEM
14466 dma_mask = DMA_BIT_MASK(64);
14467#endif
14468 } else
14469 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14470
14471 /* Configure DMA attributes. */
14472 if (dma_mask > DMA_BIT_MASK(32)) {
14473 err = pci_set_dma_mask(pdev, dma_mask);
14474 if (!err) {
14475 dev->features |= NETIF_F_HIGHDMA;
14476 err = pci_set_consistent_dma_mask(pdev,
14477 persist_dma_mask);
14478 if (err < 0) {
14479 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14480 "DMA for consistent allocations\n");
14481 goto err_out_iounmap;
14482 }
14483 }
14484 }
14485 if (err || dma_mask == DMA_BIT_MASK(32)) {
14486 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14487 if (err) {
14488 dev_err(&pdev->dev,
14489 "No usable DMA configuration, aborting\n");
14490 goto err_out_iounmap;
14491 }
14492 }
14493
14494 tg3_init_bufmgr_config(tp);
14495
14496 /* Selectively allow TSO based on operating conditions */
14497 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14498 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14499 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14500 else {
14501 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14502 tp->fw_needed = NULL;
14503 }
14504
14505 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14506 tp->fw_needed = FIRMWARE_TG3;
14507
14508 /* TSO is on by default on chips that support hardware TSO.
14509 * Firmware TSO on older chips gives lower performance, so it
14510 * is off by default, but can be enabled using ethtool.
14511 */
14512 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14513 (dev->features & NETIF_F_IP_CSUM)) {
14514 dev->features |= NETIF_F_TSO;
14515 vlan_features_add(dev, NETIF_F_TSO);
14516 }
14517 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14518 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14519 if (dev->features & NETIF_F_IPV6_CSUM) {
14520 dev->features |= NETIF_F_TSO6;
14521 vlan_features_add(dev, NETIF_F_TSO6);
14522 }
14523 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14524 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14525 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14526 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14527 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14528 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14529 dev->features |= NETIF_F_TSO_ECN;
14530 vlan_features_add(dev, NETIF_F_TSO_ECN);
14531 }
14532 }
14533
14534 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14535 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14536 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14537 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14538 tp->rx_pending = 63;
14539 }
14540
14541 err = tg3_get_device_address(tp);
14542 if (err) {
14543 dev_err(&pdev->dev,
14544 "Could not obtain valid ethernet address, aborting\n");
14545 goto err_out_iounmap;
14546 }
14547
14548 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14549 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14550 if (!tp->aperegs) {
14551 dev_err(&pdev->dev,
14552 "Cannot map APE registers, aborting\n");
14553 err = -ENOMEM;
14554 goto err_out_iounmap;
14555 }
14556
14557 tg3_ape_lock_init(tp);
14558
14559 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14560 tg3_read_dash_ver(tp);
14561 }
14562
14563 /*
14564 * Reset chip in case UNDI or EFI driver did not shutdown
14565 * DMA self test will enable WDMAC and we'll see (spurious)
14566 * pending DMA on the PCI bus at that point.
14567 */
14568 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14569 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14570 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14571 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14572 }
14573
14574 err = tg3_test_dma(tp);
14575 if (err) {
14576 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14577 goto err_out_apeunmap;
14578 }
14579
14580 /* flow control autonegotiation is default behavior */
14581 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14582 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14583
14584 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14585 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14586 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14587 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14588 struct tg3_napi *tnapi = &tp->napi[i];
14589
14590 tnapi->tp = tp;
14591 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14592
14593 tnapi->int_mbox = intmbx;
14594 if (i < 4)
14595 intmbx += 0x8;
14596 else
14597 intmbx += 0x4;
14598
14599 tnapi->consmbox = rcvmbx;
14600 tnapi->prodmbox = sndmbx;
14601
14602 if (i) {
14603 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14604 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14605 } else {
14606 tnapi->coal_now = HOSTCC_MODE_NOW;
14607 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14608 }
14609
14610 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14611 break;
14612
14613 /*
14614 * If we support MSIX, we'll be using RSS. If we're using
14615 * RSS, the first vector only handles link interrupts and the
14616 * remaining vectors handle rx and tx interrupts. Reuse the
14617 * mailbox values for the next iteration. The values we setup
14618 * above are still useful for the single vectored mode.
14619 */
14620 if (!i)
14621 continue;
14622
14623 rcvmbx += 0x8;
14624
14625 if (sndmbx & 0x4)
14626 sndmbx -= 0x4;
14627 else
14628 sndmbx += 0xc;
14629 }
14630
14631 tg3_init_coal(tp);
14632
14633 pci_set_drvdata(pdev, dev);
14634
14635 err = register_netdev(dev);
14636 if (err) {
14637 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14638 goto err_out_apeunmap;
14639 }
14640
14641 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14642 tp->board_part_number,
14643 tp->pci_chip_rev_id,
14644 tg3_bus_string(tp, str),
14645 dev->dev_addr);
14646
14647 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14648 struct phy_device *phydev;
14649 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14650 netdev_info(dev,
14651 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14652 phydev->drv->name, dev_name(&phydev->dev));
14653 } else
14654 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14655 "(WireSpeed[%d])\n", tg3_phy_string(tp),
14656 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14657 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14658 "10/100/1000Base-T")),
14659 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14660
14661 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14662 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14663 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14664 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14665 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14666 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14667 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14668 tp->dma_rwctrl,
14669 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14670 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14671
14672 return 0;
14673
14674err_out_apeunmap:
14675 if (tp->aperegs) {
14676 iounmap(tp->aperegs);
14677 tp->aperegs = NULL;
14678 }
14679
14680err_out_iounmap:
14681 if (tp->regs) {
14682 iounmap(tp->regs);
14683 tp->regs = NULL;
14684 }
14685
14686err_out_free_dev:
14687 free_netdev(dev);
14688
14689err_out_free_res:
14690 pci_release_regions(pdev);
14691
14692err_out_disable_pdev:
14693 pci_disable_device(pdev);
14694 pci_set_drvdata(pdev, NULL);
14695 return err;
14696}
14697
14698static void __devexit tg3_remove_one(struct pci_dev *pdev)
14699{
14700 struct net_device *dev = pci_get_drvdata(pdev);
14701
14702 if (dev) {
14703 struct tg3 *tp = netdev_priv(dev);
14704
14705 if (tp->fw)
14706 release_firmware(tp->fw);
14707
14708 flush_scheduled_work();
14709
14710 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14711 tg3_phy_fini(tp);
14712 tg3_mdio_fini(tp);
14713 }
14714
14715 unregister_netdev(dev);
14716 if (tp->aperegs) {
14717 iounmap(tp->aperegs);
14718 tp->aperegs = NULL;
14719 }
14720 if (tp->regs) {
14721 iounmap(tp->regs);
14722 tp->regs = NULL;
14723 }
14724 free_netdev(dev);
14725 pci_release_regions(pdev);
14726 pci_disable_device(pdev);
14727 pci_set_drvdata(pdev, NULL);
14728 }
14729}
14730
14731static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14732{
14733 struct net_device *dev = pci_get_drvdata(pdev);
14734 struct tg3 *tp = netdev_priv(dev);
14735 pci_power_t target_state;
14736 int err;
14737
14738 /* PCI register 4 needs to be saved whether netif_running() or not.
14739 * MSI address and data need to be saved if using MSI and
14740 * netif_running().
14741 */
14742 pci_save_state(pdev);
14743
14744 if (!netif_running(dev))
14745 return 0;
14746
14747 flush_scheduled_work();
14748 tg3_phy_stop(tp);
14749 tg3_netif_stop(tp);
14750
14751 del_timer_sync(&tp->timer);
14752
14753 tg3_full_lock(tp, 1);
14754 tg3_disable_ints(tp);
14755 tg3_full_unlock(tp);
14756
14757 netif_device_detach(dev);
14758
14759 tg3_full_lock(tp, 0);
14760 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14761 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14762 tg3_full_unlock(tp);
14763
14764 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14765
14766 err = tg3_set_power_state(tp, target_state);
14767 if (err) {
14768 int err2;
14769
14770 tg3_full_lock(tp, 0);
14771
14772 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14773 err2 = tg3_restart_hw(tp, 1);
14774 if (err2)
14775 goto out;
14776
14777 tp->timer.expires = jiffies + tp->timer_offset;
14778 add_timer(&tp->timer);
14779
14780 netif_device_attach(dev);
14781 tg3_netif_start(tp);
14782
14783out:
14784 tg3_full_unlock(tp);
14785
14786 if (!err2)
14787 tg3_phy_start(tp);
14788 }
14789
14790 return err;
14791}
14792
14793static int tg3_resume(struct pci_dev *pdev)
14794{
14795 struct net_device *dev = pci_get_drvdata(pdev);
14796 struct tg3 *tp = netdev_priv(dev);
14797 int err;
14798
14799 pci_restore_state(tp->pdev);
14800
14801 if (!netif_running(dev))
14802 return 0;
14803
14804 err = tg3_set_power_state(tp, PCI_D0);
14805 if (err)
14806 return err;
14807
14808 netif_device_attach(dev);
14809
14810 tg3_full_lock(tp, 0);
14811
14812 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14813 err = tg3_restart_hw(tp, 1);
14814 if (err)
14815 goto out;
14816
14817 tp->timer.expires = jiffies + tp->timer_offset;
14818 add_timer(&tp->timer);
14819
14820 tg3_netif_start(tp);
14821
14822out:
14823 tg3_full_unlock(tp);
14824
14825 if (!err)
14826 tg3_phy_start(tp);
14827
14828 return err;
14829}
14830
14831static struct pci_driver tg3_driver = {
14832 .name = DRV_MODULE_NAME,
14833 .id_table = tg3_pci_tbl,
14834 .probe = tg3_init_one,
14835 .remove = __devexit_p(tg3_remove_one),
14836 .suspend = tg3_suspend,
14837 .resume = tg3_resume
14838};
14839
14840static int __init tg3_init(void)
14841{
14842 return pci_register_driver(&tg3_driver);
14843}
14844
14845static void __exit tg3_cleanup(void)
14846{
14847 pci_unregister_driver(&tg3_driver);
14848}
14849
14850module_init(tg3_init);
14851module_exit(tg3_cleanup);
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