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tg3: Add 5785 ASIC revision
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1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
26#include <linux/in.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/phy.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/workqueue.h>
40#include <linux/prefetch.h>
41#include <linux/dma-mapping.h>
42
43#include <net/checksum.h>
44#include <net/ip.h>
45
46#include <asm/system.h>
47#include <asm/io.h>
48#include <asm/byteorder.h>
49#include <asm/uaccess.h>
50
51#ifdef CONFIG_SPARC
52#include <asm/idprom.h>
53#include <asm/prom.h>
54#endif
55
56#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
57#define TG3_VLAN_TAG_USED 1
58#else
59#define TG3_VLAN_TAG_USED 0
60#endif
61
62#define TG3_TSO_SUPPORT 1
63
64#include "tg3.h"
65
66#define DRV_MODULE_NAME "tg3"
67#define PFX DRV_MODULE_NAME ": "
68#define DRV_MODULE_VERSION "3.92"
69#define DRV_MODULE_RELDATE "May 2, 2008"
70
71#define TG3_DEF_MAC_MODE 0
72#define TG3_DEF_RX_MODE 0
73#define TG3_DEF_TX_MODE 0
74#define TG3_DEF_MSG_ENABLE \
75 (NETIF_MSG_DRV | \
76 NETIF_MSG_PROBE | \
77 NETIF_MSG_LINK | \
78 NETIF_MSG_TIMER | \
79 NETIF_MSG_IFDOWN | \
80 NETIF_MSG_IFUP | \
81 NETIF_MSG_RX_ERR | \
82 NETIF_MSG_TX_ERR)
83
84/* length of time before we decide the hardware is borked,
85 * and dev->tx_timeout() should be called to fix the problem
86 */
87#define TG3_TX_TIMEOUT (5 * HZ)
88
89/* hardware minimum and maximum for a single frame's data payload */
90#define TG3_MIN_MTU 60
91#define TG3_MAX_MTU(tp) \
92 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
93
94/* These numbers seem to be hard coded in the NIC firmware somehow.
95 * You can't change the ring sizes, but you can change where you place
96 * them in the NIC onboard memory.
97 */
98#define TG3_RX_RING_SIZE 512
99#define TG3_DEF_RX_RING_PENDING 200
100#define TG3_RX_JUMBO_RING_SIZE 256
101#define TG3_DEF_RX_JUMBO_RING_PENDING 100
102
103/* Do not place this n-ring entries value into the tp struct itself,
104 * we really want to expose these constants to GCC so that modulo et
105 * al. operations are done with shifts and masks instead of with
106 * hw multiply/modulo instructions. Another solution would be to
107 * replace things like '% foo' with '& (foo - 1)'.
108 */
109#define TG3_RX_RCB_RING_SIZE(tp) \
110 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
111
112#define TG3_TX_RING_SIZE 512
113#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
114
115#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
116 TG3_RX_RING_SIZE)
117#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
118 TG3_RX_JUMBO_RING_SIZE)
119#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_RCB_RING_SIZE(tp))
121#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
122 TG3_TX_RING_SIZE)
123#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
124
125#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
126#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
127
128/* minimum number of free TX descriptors required to wake up TX process */
129#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
130
131/* number of ETHTOOL_GSTATS u64's */
132#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
133
134#define TG3_NUM_TEST 6
135
136static char version[] __devinitdata =
137 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
138
139MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
140MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_MODULE_VERSION);
143
144static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
145module_param(tg3_debug, int, 0);
146MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
147
148static struct pci_device_id tg3_pci_tbl[] = {
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
208 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
209 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
210 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
211 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
212 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
213 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
214 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
215 {}
216};
217
218MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
219
220static const struct {
221 const char string[ETH_GSTRING_LEN];
222} ethtool_stats_keys[TG3_NUM_STATS] = {
223 { "rx_octets" },
224 { "rx_fragments" },
225 { "rx_ucast_packets" },
226 { "rx_mcast_packets" },
227 { "rx_bcast_packets" },
228 { "rx_fcs_errors" },
229 { "rx_align_errors" },
230 { "rx_xon_pause_rcvd" },
231 { "rx_xoff_pause_rcvd" },
232 { "rx_mac_ctrl_rcvd" },
233 { "rx_xoff_entered" },
234 { "rx_frame_too_long_errors" },
235 { "rx_jabbers" },
236 { "rx_undersize_packets" },
237 { "rx_in_length_errors" },
238 { "rx_out_length_errors" },
239 { "rx_64_or_less_octet_packets" },
240 { "rx_65_to_127_octet_packets" },
241 { "rx_128_to_255_octet_packets" },
242 { "rx_256_to_511_octet_packets" },
243 { "rx_512_to_1023_octet_packets" },
244 { "rx_1024_to_1522_octet_packets" },
245 { "rx_1523_to_2047_octet_packets" },
246 { "rx_2048_to_4095_octet_packets" },
247 { "rx_4096_to_8191_octet_packets" },
248 { "rx_8192_to_9022_octet_packets" },
249
250 { "tx_octets" },
251 { "tx_collisions" },
252
253 { "tx_xon_sent" },
254 { "tx_xoff_sent" },
255 { "tx_flow_control" },
256 { "tx_mac_errors" },
257 { "tx_single_collisions" },
258 { "tx_mult_collisions" },
259 { "tx_deferred" },
260 { "tx_excessive_collisions" },
261 { "tx_late_collisions" },
262 { "tx_collide_2times" },
263 { "tx_collide_3times" },
264 { "tx_collide_4times" },
265 { "tx_collide_5times" },
266 { "tx_collide_6times" },
267 { "tx_collide_7times" },
268 { "tx_collide_8times" },
269 { "tx_collide_9times" },
270 { "tx_collide_10times" },
271 { "tx_collide_11times" },
272 { "tx_collide_12times" },
273 { "tx_collide_13times" },
274 { "tx_collide_14times" },
275 { "tx_collide_15times" },
276 { "tx_ucast_packets" },
277 { "tx_mcast_packets" },
278 { "tx_bcast_packets" },
279 { "tx_carrier_sense_errors" },
280 { "tx_discards" },
281 { "tx_errors" },
282
283 { "dma_writeq_full" },
284 { "dma_write_prioq_full" },
285 { "rxbds_empty" },
286 { "rx_discards" },
287 { "rx_errors" },
288 { "rx_threshold_hit" },
289
290 { "dma_readq_full" },
291 { "dma_read_prioq_full" },
292 { "tx_comp_queue_full" },
293
294 { "ring_set_send_prod_index" },
295 { "ring_status_update" },
296 { "nic_irqs" },
297 { "nic_avoided_irqs" },
298 { "nic_tx_threshold_hit" }
299};
300
301static const struct {
302 const char string[ETH_GSTRING_LEN];
303} ethtool_test_keys[TG3_NUM_TEST] = {
304 { "nvram test (online) " },
305 { "link test (online) " },
306 { "register test (offline)" },
307 { "memory test (offline)" },
308 { "loopback test (offline)" },
309 { "interrupt test (offline)" },
310};
311
312static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
313{
314 writel(val, tp->regs + off);
315}
316
317static u32 tg3_read32(struct tg3 *tp, u32 off)
318{
319 return (readl(tp->regs + off));
320}
321
322static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
323{
324 writel(val, tp->aperegs + off);
325}
326
327static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
328{
329 return (readl(tp->aperegs + off));
330}
331
332static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
333{
334 unsigned long flags;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340}
341
342static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
343{
344 writel(val, tp->regs + off);
345 readl(tp->regs + off);
346}
347
348static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
349{
350 unsigned long flags;
351 u32 val;
352
353 spin_lock_irqsave(&tp->indirect_lock, flags);
354 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
355 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
356 spin_unlock_irqrestore(&tp->indirect_lock, flags);
357 return val;
358}
359
360static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
361{
362 unsigned long flags;
363
364 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
365 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
366 TG3_64BIT_REG_LOW, val);
367 return;
368 }
369 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
370 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
371 TG3_64BIT_REG_LOW, val);
372 return;
373 }
374
375 spin_lock_irqsave(&tp->indirect_lock, flags);
376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
379
380 /* In indirect mode when disabling interrupts, we also need
381 * to clear the interrupt bit in the GRC local ctrl register.
382 */
383 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
384 (val == 0x1)) {
385 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
386 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
387 }
388}
389
390static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
391{
392 unsigned long flags;
393 u32 val;
394
395 spin_lock_irqsave(&tp->indirect_lock, flags);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
397 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
398 spin_unlock_irqrestore(&tp->indirect_lock, flags);
399 return val;
400}
401
402/* usec_wait specifies the wait time in usec when writing to certain registers
403 * where it is unsafe to read back the register without some delay.
404 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
405 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
406 */
407static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
408{
409 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
410 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
411 /* Non-posted methods */
412 tp->write32(tp, off, val);
413 else {
414 /* Posted method */
415 tg3_write32(tp, off, val);
416 if (usec_wait)
417 udelay(usec_wait);
418 tp->read32(tp, off);
419 }
420 /* Wait again after the read for the posted method to guarantee that
421 * the wait time is met.
422 */
423 if (usec_wait)
424 udelay(usec_wait);
425}
426
427static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
428{
429 tp->write32_mbox(tp, off, val);
430 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
431 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
432 tp->read32_mbox(tp, off);
433}
434
435static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
436{
437 void __iomem *mbox = tp->regs + off;
438 writel(val, mbox);
439 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
440 writel(val, mbox);
441 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
442 readl(mbox);
443}
444
445static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
446{
447 return (readl(tp->regs + off + GRCMBOX_BASE));
448}
449
450static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
451{
452 writel(val, tp->regs + off + GRCMBOX_BASE);
453}
454
455#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
456#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
457#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
458#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
459#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
460
461#define tw32(reg,val) tp->write32(tp, reg, val)
462#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
463#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
464#define tr32(reg) tp->read32(tp, reg)
465
466static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
467{
468 unsigned long flags;
469
470 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
471 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
472 return;
473
474 spin_lock_irqsave(&tp->indirect_lock, flags);
475 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
476 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
477 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
478
479 /* Always leave this as zero. */
480 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
481 } else {
482 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
483 tw32_f(TG3PCI_MEM_WIN_DATA, val);
484
485 /* Always leave this as zero. */
486 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
487 }
488 spin_unlock_irqrestore(&tp->indirect_lock, flags);
489}
490
491static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
492{
493 unsigned long flags;
494
495 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
496 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
497 *val = 0;
498 return;
499 }
500
501 spin_lock_irqsave(&tp->indirect_lock, flags);
502 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
503 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
504 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
505
506 /* Always leave this as zero. */
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
508 } else {
509 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
510 *val = tr32(TG3PCI_MEM_WIN_DATA);
511
512 /* Always leave this as zero. */
513 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
514 }
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516}
517
518static void tg3_ape_lock_init(struct tg3 *tp)
519{
520 int i;
521
522 /* Make sure the driver hasn't any stale locks. */
523 for (i = 0; i < 8; i++)
524 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
525 APE_LOCK_GRANT_DRIVER);
526}
527
528static int tg3_ape_lock(struct tg3 *tp, int locknum)
529{
530 int i, off;
531 int ret = 0;
532 u32 status;
533
534 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
535 return 0;
536
537 switch (locknum) {
538 case TG3_APE_LOCK_MEM:
539 break;
540 default:
541 return -EINVAL;
542 }
543
544 off = 4 * locknum;
545
546 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
547
548 /* Wait for up to 1 millisecond to acquire lock. */
549 for (i = 0; i < 100; i++) {
550 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
551 if (status == APE_LOCK_GRANT_DRIVER)
552 break;
553 udelay(10);
554 }
555
556 if (status != APE_LOCK_GRANT_DRIVER) {
557 /* Revoke the lock request. */
558 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
559 APE_LOCK_GRANT_DRIVER);
560
561 ret = -EBUSY;
562 }
563
564 return ret;
565}
566
567static void tg3_ape_unlock(struct tg3 *tp, int locknum)
568{
569 int off;
570
571 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
572 return;
573
574 switch (locknum) {
575 case TG3_APE_LOCK_MEM:
576 break;
577 default:
578 return;
579 }
580
581 off = 4 * locknum;
582 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
583}
584
585static void tg3_disable_ints(struct tg3 *tp)
586{
587 tw32(TG3PCI_MISC_HOST_CTRL,
588 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
589 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
590}
591
592static inline void tg3_cond_int(struct tg3 *tp)
593{
594 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
595 (tp->hw_status->status & SD_STATUS_UPDATED))
596 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
597 else
598 tw32(HOSTCC_MODE, tp->coalesce_mode |
599 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
600}
601
602static void tg3_enable_ints(struct tg3 *tp)
603{
604 tp->irq_sync = 0;
605 wmb();
606
607 tw32(TG3PCI_MISC_HOST_CTRL,
608 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
609 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
610 (tp->last_tag << 24));
611 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
612 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
613 (tp->last_tag << 24));
614 tg3_cond_int(tp);
615}
616
617static inline unsigned int tg3_has_work(struct tg3 *tp)
618{
619 struct tg3_hw_status *sblk = tp->hw_status;
620 unsigned int work_exists = 0;
621
622 /* check for phy events */
623 if (!(tp->tg3_flags &
624 (TG3_FLAG_USE_LINKCHG_REG |
625 TG3_FLAG_POLL_SERDES))) {
626 if (sblk->status & SD_STATUS_LINK_CHG)
627 work_exists = 1;
628 }
629 /* check for RX/TX work to do */
630 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
631 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
632 work_exists = 1;
633
634 return work_exists;
635}
636
637/* tg3_restart_ints
638 * similar to tg3_enable_ints, but it accurately determines whether there
639 * is new work pending and can return without flushing the PIO write
640 * which reenables interrupts
641 */
642static void tg3_restart_ints(struct tg3 *tp)
643{
644 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
645 tp->last_tag << 24);
646 mmiowb();
647
648 /* When doing tagged status, this work check is unnecessary.
649 * The last_tag we write above tells the chip which piece of
650 * work we've completed.
651 */
652 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
653 tg3_has_work(tp))
654 tw32(HOSTCC_MODE, tp->coalesce_mode |
655 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
656}
657
658static inline void tg3_netif_stop(struct tg3 *tp)
659{
660 tp->dev->trans_start = jiffies; /* prevent tx timeout */
661 napi_disable(&tp->napi);
662 netif_tx_disable(tp->dev);
663}
664
665static inline void tg3_netif_start(struct tg3 *tp)
666{
667 netif_wake_queue(tp->dev);
668 /* NOTE: unconditional netif_wake_queue is only appropriate
669 * so long as all callers are assured to have free tx slots
670 * (such as after tg3_init_hw)
671 */
672 napi_enable(&tp->napi);
673 tp->hw_status->status |= SD_STATUS_UPDATED;
674 tg3_enable_ints(tp);
675}
676
677static void tg3_switch_clocks(struct tg3 *tp)
678{
679 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
680 u32 orig_clock_ctrl;
681
682 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
683 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
684 return;
685
686 orig_clock_ctrl = clock_ctrl;
687 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
688 CLOCK_CTRL_CLKRUN_OENABLE |
689 0x1f);
690 tp->pci_clock_ctrl = clock_ctrl;
691
692 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
693 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
694 tw32_wait_f(TG3PCI_CLOCK_CTRL,
695 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
696 }
697 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
698 tw32_wait_f(TG3PCI_CLOCK_CTRL,
699 clock_ctrl |
700 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
701 40);
702 tw32_wait_f(TG3PCI_CLOCK_CTRL,
703 clock_ctrl | (CLOCK_CTRL_ALTCLK),
704 40);
705 }
706 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
707}
708
709#define PHY_BUSY_LOOPS 5000
710
711static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
712{
713 u32 frame_val;
714 unsigned int loops;
715 int ret;
716
717 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
718 tw32_f(MAC_MI_MODE,
719 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
720 udelay(80);
721 }
722
723 *val = 0x0;
724
725 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
726 MI_COM_PHY_ADDR_MASK);
727 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
728 MI_COM_REG_ADDR_MASK);
729 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
730
731 tw32_f(MAC_MI_COM, frame_val);
732
733 loops = PHY_BUSY_LOOPS;
734 while (loops != 0) {
735 udelay(10);
736 frame_val = tr32(MAC_MI_COM);
737
738 if ((frame_val & MI_COM_BUSY) == 0) {
739 udelay(5);
740 frame_val = tr32(MAC_MI_COM);
741 break;
742 }
743 loops -= 1;
744 }
745
746 ret = -EBUSY;
747 if (loops != 0) {
748 *val = frame_val & MI_COM_DATA_MASK;
749 ret = 0;
750 }
751
752 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
753 tw32_f(MAC_MI_MODE, tp->mi_mode);
754 udelay(80);
755 }
756
757 return ret;
758}
759
760static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
761{
762 u32 frame_val;
763 unsigned int loops;
764 int ret;
765
766 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
767 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
768 return 0;
769
770 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
771 tw32_f(MAC_MI_MODE,
772 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
773 udelay(80);
774 }
775
776 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
777 MI_COM_PHY_ADDR_MASK);
778 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
779 MI_COM_REG_ADDR_MASK);
780 frame_val |= (val & MI_COM_DATA_MASK);
781 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
782
783 tw32_f(MAC_MI_COM, frame_val);
784
785 loops = PHY_BUSY_LOOPS;
786 while (loops != 0) {
787 udelay(10);
788 frame_val = tr32(MAC_MI_COM);
789 if ((frame_val & MI_COM_BUSY) == 0) {
790 udelay(5);
791 frame_val = tr32(MAC_MI_COM);
792 break;
793 }
794 loops -= 1;
795 }
796
797 ret = -EBUSY;
798 if (loops != 0)
799 ret = 0;
800
801 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
802 tw32_f(MAC_MI_MODE, tp->mi_mode);
803 udelay(80);
804 }
805
806 return ret;
807}
808
809static int tg3_bmcr_reset(struct tg3 *tp)
810{
811 u32 phy_control;
812 int limit, err;
813
814 /* OK, reset it, and poll the BMCR_RESET bit until it
815 * clears or we time out.
816 */
817 phy_control = BMCR_RESET;
818 err = tg3_writephy(tp, MII_BMCR, phy_control);
819 if (err != 0)
820 return -EBUSY;
821
822 limit = 5000;
823 while (limit--) {
824 err = tg3_readphy(tp, MII_BMCR, &phy_control);
825 if (err != 0)
826 return -EBUSY;
827
828 if ((phy_control & BMCR_RESET) == 0) {
829 udelay(40);
830 break;
831 }
832 udelay(10);
833 }
834 if (limit <= 0)
835 return -EBUSY;
836
837 return 0;
838}
839
840static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
841{
842 struct tg3 *tp = (struct tg3 *)bp->priv;
843 u32 val;
844
845 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
846 return -EAGAIN;
847
848 if (tg3_readphy(tp, reg, &val))
849 return -EIO;
850
851 return val;
852}
853
854static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
855{
856 struct tg3 *tp = (struct tg3 *)bp->priv;
857
858 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
859 return -EAGAIN;
860
861 if (tg3_writephy(tp, reg, val))
862 return -EIO;
863
864 return 0;
865}
866
867static int tg3_mdio_reset(struct mii_bus *bp)
868{
869 return 0;
870}
871
872static void tg3_mdio_start(struct tg3 *tp)
873{
874 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
875 mutex_lock(&tp->mdio_bus.mdio_lock);
876 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
877 mutex_unlock(&tp->mdio_bus.mdio_lock);
878 }
879
880 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
881 tw32_f(MAC_MI_MODE, tp->mi_mode);
882 udelay(80);
883}
884
885static void tg3_mdio_stop(struct tg3 *tp)
886{
887 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
888 mutex_lock(&tp->mdio_bus.mdio_lock);
889 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
890 mutex_unlock(&tp->mdio_bus.mdio_lock);
891 }
892}
893
894static int tg3_mdio_init(struct tg3 *tp)
895{
896 int i;
897 u32 reg;
898 struct mii_bus *mdio_bus = &tp->mdio_bus;
899
900 tg3_mdio_start(tp);
901
902 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
903 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
904 return 0;
905
906 memset(mdio_bus, 0, sizeof(*mdio_bus));
907
908 mdio_bus->name = "tg3 mdio bus";
909 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
910 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
911 mdio_bus->priv = tp;
912 mdio_bus->dev = &tp->pdev->dev;
913 mdio_bus->read = &tg3_mdio_read;
914 mdio_bus->write = &tg3_mdio_write;
915 mdio_bus->reset = &tg3_mdio_reset;
916 mdio_bus->phy_mask = ~(1 << PHY_ADDR);
917 mdio_bus->irq = &tp->mdio_irq[0];
918
919 for (i = 0; i < PHY_MAX_ADDR; i++)
920 mdio_bus->irq[i] = PHY_POLL;
921
922 /* The bus registration will look for all the PHYs on the mdio bus.
923 * Unfortunately, it does not ensure the PHY is powered up before
924 * accessing the PHY ID registers. A chip reset is the
925 * quickest way to bring the device back to an operational state..
926 */
927 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
928 tg3_bmcr_reset(tp);
929
930 i = mdiobus_register(mdio_bus);
931 if (!i)
932 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
933 else
934 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
935 tp->dev->name, i);
936
937 return i;
938}
939
940static void tg3_mdio_fini(struct tg3 *tp)
941{
942 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
943 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
944 mdiobus_unregister(&tp->mdio_bus);
945 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
946 }
947}
948
949/* tp->lock is held. */
950static void tg3_wait_for_event_ack(struct tg3 *tp)
951{
952 int i;
953
954 /* Wait for up to 2.5 milliseconds */
955 for (i = 0; i < 250000; i++) {
956 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
957 break;
958 udelay(10);
959 }
960}
961
962/* tp->lock is held. */
963static void tg3_ump_link_report(struct tg3 *tp)
964{
965 u32 reg;
966 u32 val;
967
968 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
969 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
970 return;
971
972 tg3_wait_for_event_ack(tp);
973
974 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
975
976 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
977
978 val = 0;
979 if (!tg3_readphy(tp, MII_BMCR, &reg))
980 val = reg << 16;
981 if (!tg3_readphy(tp, MII_BMSR, &reg))
982 val |= (reg & 0xffff);
983 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
984
985 val = 0;
986 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
987 val = reg << 16;
988 if (!tg3_readphy(tp, MII_LPA, &reg))
989 val |= (reg & 0xffff);
990 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
991
992 val = 0;
993 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
994 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
995 val = reg << 16;
996 if (!tg3_readphy(tp, MII_STAT1000, &reg))
997 val |= (reg & 0xffff);
998 }
999 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1000
1001 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1002 val = reg << 16;
1003 else
1004 val = 0;
1005 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1006
1007 val = tr32(GRC_RX_CPU_EVENT);
1008 val |= GRC_RX_CPU_DRIVER_EVENT;
1009 tw32_f(GRC_RX_CPU_EVENT, val);
1010}
1011
1012static void tg3_link_report(struct tg3 *tp)
1013{
1014 if (!netif_carrier_ok(tp->dev)) {
1015 if (netif_msg_link(tp))
1016 printk(KERN_INFO PFX "%s: Link is down.\n",
1017 tp->dev->name);
1018 tg3_ump_link_report(tp);
1019 } else if (netif_msg_link(tp)) {
1020 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1021 tp->dev->name,
1022 (tp->link_config.active_speed == SPEED_1000 ?
1023 1000 :
1024 (tp->link_config.active_speed == SPEED_100 ?
1025 100 : 10)),
1026 (tp->link_config.active_duplex == DUPLEX_FULL ?
1027 "full" : "half"));
1028
1029 printk(KERN_INFO PFX
1030 "%s: Flow control is %s for TX and %s for RX.\n",
1031 tp->dev->name,
1032 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1033 "on" : "off",
1034 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1035 "on" : "off");
1036 tg3_ump_link_report(tp);
1037 }
1038}
1039
1040static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1041{
1042 u16 miireg;
1043
1044 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1045 miireg = ADVERTISE_PAUSE_CAP;
1046 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1047 miireg = ADVERTISE_PAUSE_ASYM;
1048 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1049 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1050 else
1051 miireg = 0;
1052
1053 return miireg;
1054}
1055
1056static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1057{
1058 u16 miireg;
1059
1060 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1061 miireg = ADVERTISE_1000XPAUSE;
1062 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1063 miireg = ADVERTISE_1000XPSE_ASYM;
1064 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1065 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1066 else
1067 miireg = 0;
1068
1069 return miireg;
1070}
1071
1072static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1073{
1074 u8 cap = 0;
1075
1076 if (lcladv & ADVERTISE_PAUSE_CAP) {
1077 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1078 if (rmtadv & LPA_PAUSE_CAP)
1079 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1080 else if (rmtadv & LPA_PAUSE_ASYM)
1081 cap = TG3_FLOW_CTRL_RX;
1082 } else {
1083 if (rmtadv & LPA_PAUSE_CAP)
1084 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1085 }
1086 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1087 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1088 cap = TG3_FLOW_CTRL_TX;
1089 }
1090
1091 return cap;
1092}
1093
1094static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1095{
1096 u8 cap = 0;
1097
1098 if (lcladv & ADVERTISE_1000XPAUSE) {
1099 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1100 if (rmtadv & LPA_1000XPAUSE)
1101 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1102 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1103 cap = TG3_FLOW_CTRL_RX;
1104 } else {
1105 if (rmtadv & LPA_1000XPAUSE)
1106 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1107 }
1108 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1109 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1110 cap = TG3_FLOW_CTRL_TX;
1111 }
1112
1113 return cap;
1114}
1115
1116static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1117{
1118 u8 autoneg;
1119 u8 flowctrl = 0;
1120 u32 old_rx_mode = tp->rx_mode;
1121 u32 old_tx_mode = tp->tx_mode;
1122
1123 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1124 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1125 else
1126 autoneg = tp->link_config.autoneg;
1127
1128 if (autoneg == AUTONEG_ENABLE &&
1129 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1130 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1131 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1132 else
1133 flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1134 } else
1135 flowctrl = tp->link_config.flowctrl;
1136
1137 tp->link_config.active_flowctrl = flowctrl;
1138
1139 if (flowctrl & TG3_FLOW_CTRL_RX)
1140 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1141 else
1142 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1143
1144 if (old_rx_mode != tp->rx_mode)
1145 tw32_f(MAC_RX_MODE, tp->rx_mode);
1146
1147 if (flowctrl & TG3_FLOW_CTRL_TX)
1148 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1149 else
1150 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1151
1152 if (old_tx_mode != tp->tx_mode)
1153 tw32_f(MAC_TX_MODE, tp->tx_mode);
1154}
1155
1156static void tg3_adjust_link(struct net_device *dev)
1157{
1158 u8 oldflowctrl, linkmesg = 0;
1159 u32 mac_mode, lcl_adv, rmt_adv;
1160 struct tg3 *tp = netdev_priv(dev);
1161 struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1162
1163 spin_lock(&tp->lock);
1164
1165 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1166 MAC_MODE_HALF_DUPLEX);
1167
1168 oldflowctrl = tp->link_config.active_flowctrl;
1169
1170 if (phydev->link) {
1171 lcl_adv = 0;
1172 rmt_adv = 0;
1173
1174 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1175 mac_mode |= MAC_MODE_PORT_MODE_MII;
1176 else
1177 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1178
1179 if (phydev->duplex == DUPLEX_HALF)
1180 mac_mode |= MAC_MODE_HALF_DUPLEX;
1181 else {
1182 lcl_adv = tg3_advert_flowctrl_1000T(
1183 tp->link_config.flowctrl);
1184
1185 if (phydev->pause)
1186 rmt_adv = LPA_PAUSE_CAP;
1187 if (phydev->asym_pause)
1188 rmt_adv |= LPA_PAUSE_ASYM;
1189 }
1190
1191 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1192 } else
1193 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1194
1195 if (mac_mode != tp->mac_mode) {
1196 tp->mac_mode = mac_mode;
1197 tw32_f(MAC_MODE, tp->mac_mode);
1198 udelay(40);
1199 }
1200
1201 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1202 tw32(MAC_TX_LENGTHS,
1203 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1204 (6 << TX_LENGTHS_IPG_SHIFT) |
1205 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1206 else
1207 tw32(MAC_TX_LENGTHS,
1208 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1209 (6 << TX_LENGTHS_IPG_SHIFT) |
1210 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1211
1212 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1213 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1214 phydev->speed != tp->link_config.active_speed ||
1215 phydev->duplex != tp->link_config.active_duplex ||
1216 oldflowctrl != tp->link_config.active_flowctrl)
1217 linkmesg = 1;
1218
1219 tp->link_config.active_speed = phydev->speed;
1220 tp->link_config.active_duplex = phydev->duplex;
1221
1222 spin_unlock(&tp->lock);
1223
1224 if (linkmesg)
1225 tg3_link_report(tp);
1226}
1227
1228static int tg3_phy_init(struct tg3 *tp)
1229{
1230 struct phy_device *phydev;
1231
1232 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1233 return 0;
1234
1235 /* Bring the PHY back to a known state. */
1236 tg3_bmcr_reset(tp);
1237
1238 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1239
1240 /* Attach the MAC to the PHY. */
1241 phydev = phy_connect(tp->dev, phydev->dev.bus_id,
1242 tg3_adjust_link, 0, phydev->interface);
1243 if (IS_ERR(phydev)) {
1244 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1245 return PTR_ERR(phydev);
1246 }
1247
1248 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1249
1250 /* Mask with MAC supported features. */
1251 phydev->supported &= (PHY_GBIT_FEATURES |
1252 SUPPORTED_Pause |
1253 SUPPORTED_Asym_Pause);
1254
1255 phydev->advertising = phydev->supported;
1256
1257 printk(KERN_INFO
1258 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1259 tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1260
1261 return 0;
1262}
1263
1264static void tg3_phy_start(struct tg3 *tp)
1265{
1266 struct phy_device *phydev;
1267
1268 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1269 return;
1270
1271 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1272
1273 if (tp->link_config.phy_is_low_power) {
1274 tp->link_config.phy_is_low_power = 0;
1275 phydev->speed = tp->link_config.orig_speed;
1276 phydev->duplex = tp->link_config.orig_duplex;
1277 phydev->autoneg = tp->link_config.orig_autoneg;
1278 phydev->advertising = tp->link_config.orig_advertising;
1279 }
1280
1281 phy_start(phydev);
1282
1283 phy_start_aneg(phydev);
1284}
1285
1286static void tg3_phy_stop(struct tg3 *tp)
1287{
1288 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1289 return;
1290
1291 phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1292}
1293
1294static void tg3_phy_fini(struct tg3 *tp)
1295{
1296 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1297 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1298 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1299 }
1300}
1301
1302static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1303{
1304 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1305 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1306}
1307
1308static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1309{
1310 u32 phy;
1311
1312 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1313 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1314 return;
1315
1316 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1317 u32 ephy;
1318
1319 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1320 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1321 ephy | MII_TG3_EPHY_SHADOW_EN);
1322 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1323 if (enable)
1324 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1325 else
1326 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1327 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1328 }
1329 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1330 }
1331 } else {
1332 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1333 MII_TG3_AUXCTL_SHDWSEL_MISC;
1334 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1335 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1336 if (enable)
1337 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1338 else
1339 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1340 phy |= MII_TG3_AUXCTL_MISC_WREN;
1341 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1342 }
1343 }
1344}
1345
1346static void tg3_phy_set_wirespeed(struct tg3 *tp)
1347{
1348 u32 val;
1349
1350 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1351 return;
1352
1353 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1354 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1355 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1356 (val | (1 << 15) | (1 << 4)));
1357}
1358
1359static void tg3_phy_apply_otp(struct tg3 *tp)
1360{
1361 u32 otp, phy;
1362
1363 if (!tp->phy_otp)
1364 return;
1365
1366 otp = tp->phy_otp;
1367
1368 /* Enable SM_DSP clock and tx 6dB coding. */
1369 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1370 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1371 MII_TG3_AUXCTL_ACTL_TX_6DB;
1372 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1373
1374 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1375 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1376 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1377
1378 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1379 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1380 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1381
1382 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1383 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1384 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1385
1386 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1387 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1388
1389 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1390 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1391
1392 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1393 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1394 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1395
1396 /* Turn off SM_DSP clock. */
1397 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1398 MII_TG3_AUXCTL_ACTL_TX_6DB;
1399 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1400}
1401
1402static int tg3_wait_macro_done(struct tg3 *tp)
1403{
1404 int limit = 100;
1405
1406 while (limit--) {
1407 u32 tmp32;
1408
1409 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1410 if ((tmp32 & 0x1000) == 0)
1411 break;
1412 }
1413 }
1414 if (limit <= 0)
1415 return -EBUSY;
1416
1417 return 0;
1418}
1419
1420static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1421{
1422 static const u32 test_pat[4][6] = {
1423 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1424 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1425 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1426 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1427 };
1428 int chan;
1429
1430 for (chan = 0; chan < 4; chan++) {
1431 int i;
1432
1433 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1434 (chan * 0x2000) | 0x0200);
1435 tg3_writephy(tp, 0x16, 0x0002);
1436
1437 for (i = 0; i < 6; i++)
1438 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1439 test_pat[chan][i]);
1440
1441 tg3_writephy(tp, 0x16, 0x0202);
1442 if (tg3_wait_macro_done(tp)) {
1443 *resetp = 1;
1444 return -EBUSY;
1445 }
1446
1447 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1448 (chan * 0x2000) | 0x0200);
1449 tg3_writephy(tp, 0x16, 0x0082);
1450 if (tg3_wait_macro_done(tp)) {
1451 *resetp = 1;
1452 return -EBUSY;
1453 }
1454
1455 tg3_writephy(tp, 0x16, 0x0802);
1456 if (tg3_wait_macro_done(tp)) {
1457 *resetp = 1;
1458 return -EBUSY;
1459 }
1460
1461 for (i = 0; i < 6; i += 2) {
1462 u32 low, high;
1463
1464 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1465 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1466 tg3_wait_macro_done(tp)) {
1467 *resetp = 1;
1468 return -EBUSY;
1469 }
1470 low &= 0x7fff;
1471 high &= 0x000f;
1472 if (low != test_pat[chan][i] ||
1473 high != test_pat[chan][i+1]) {
1474 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1475 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1476 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1477
1478 return -EBUSY;
1479 }
1480 }
1481 }
1482
1483 return 0;
1484}
1485
1486static int tg3_phy_reset_chanpat(struct tg3 *tp)
1487{
1488 int chan;
1489
1490 for (chan = 0; chan < 4; chan++) {
1491 int i;
1492
1493 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1494 (chan * 0x2000) | 0x0200);
1495 tg3_writephy(tp, 0x16, 0x0002);
1496 for (i = 0; i < 6; i++)
1497 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1498 tg3_writephy(tp, 0x16, 0x0202);
1499 if (tg3_wait_macro_done(tp))
1500 return -EBUSY;
1501 }
1502
1503 return 0;
1504}
1505
1506static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1507{
1508 u32 reg32, phy9_orig;
1509 int retries, do_phy_reset, err;
1510
1511 retries = 10;
1512 do_phy_reset = 1;
1513 do {
1514 if (do_phy_reset) {
1515 err = tg3_bmcr_reset(tp);
1516 if (err)
1517 return err;
1518 do_phy_reset = 0;
1519 }
1520
1521 /* Disable transmitter and interrupt. */
1522 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1523 continue;
1524
1525 reg32 |= 0x3000;
1526 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1527
1528 /* Set full-duplex, 1000 mbps. */
1529 tg3_writephy(tp, MII_BMCR,
1530 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1531
1532 /* Set to master mode. */
1533 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1534 continue;
1535
1536 tg3_writephy(tp, MII_TG3_CTRL,
1537 (MII_TG3_CTRL_AS_MASTER |
1538 MII_TG3_CTRL_ENABLE_AS_MASTER));
1539
1540 /* Enable SM_DSP_CLOCK and 6dB. */
1541 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1542
1543 /* Block the PHY control access. */
1544 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1545 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1546
1547 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1548 if (!err)
1549 break;
1550 } while (--retries);
1551
1552 err = tg3_phy_reset_chanpat(tp);
1553 if (err)
1554 return err;
1555
1556 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1557 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1558
1559 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1560 tg3_writephy(tp, 0x16, 0x0000);
1561
1562 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1563 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1564 /* Set Extended packet length bit for jumbo frames */
1565 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1566 }
1567 else {
1568 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1569 }
1570
1571 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1572
1573 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1574 reg32 &= ~0x3000;
1575 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1576 } else if (!err)
1577 err = -EBUSY;
1578
1579 return err;
1580}
1581
1582/* This will reset the tigon3 PHY if there is no valid
1583 * link unless the FORCE argument is non-zero.
1584 */
1585static int tg3_phy_reset(struct tg3 *tp)
1586{
1587 u32 cpmuctrl;
1588 u32 phy_status;
1589 int err;
1590
1591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1592 u32 val;
1593
1594 val = tr32(GRC_MISC_CFG);
1595 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1596 udelay(40);
1597 }
1598 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1599 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1600 if (err != 0)
1601 return -EBUSY;
1602
1603 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1604 netif_carrier_off(tp->dev);
1605 tg3_link_report(tp);
1606 }
1607
1608 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1609 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1610 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1611 err = tg3_phy_reset_5703_4_5(tp);
1612 if (err)
1613 return err;
1614 goto out;
1615 }
1616
1617 cpmuctrl = 0;
1618 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1619 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1620 cpmuctrl = tr32(TG3_CPMU_CTRL);
1621 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1622 tw32(TG3_CPMU_CTRL,
1623 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1624 }
1625
1626 err = tg3_bmcr_reset(tp);
1627 if (err)
1628 return err;
1629
1630 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1631 u32 phy;
1632
1633 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1634 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1635
1636 tw32(TG3_CPMU_CTRL, cpmuctrl);
1637 }
1638
1639 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1640 u32 val;
1641
1642 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1643 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1644 CPMU_LSPD_1000MB_MACCLK_12_5) {
1645 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1646 udelay(40);
1647 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1648 }
1649
1650 /* Disable GPHY autopowerdown. */
1651 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1652 MII_TG3_MISC_SHDW_WREN |
1653 MII_TG3_MISC_SHDW_APD_SEL |
1654 MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1655 }
1656
1657 tg3_phy_apply_otp(tp);
1658
1659out:
1660 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1661 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1662 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1663 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1664 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1665 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1666 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1667 }
1668 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1669 tg3_writephy(tp, 0x1c, 0x8d68);
1670 tg3_writephy(tp, 0x1c, 0x8d68);
1671 }
1672 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1673 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1674 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1675 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1676 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1677 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1678 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1679 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1680 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1681 }
1682 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1683 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1684 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1685 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1686 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1687 tg3_writephy(tp, MII_TG3_TEST1,
1688 MII_TG3_TEST1_TRIM_EN | 0x4);
1689 } else
1690 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1691 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1692 }
1693 /* Set Extended packet length bit (bit 14) on all chips that */
1694 /* support jumbo frames */
1695 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1696 /* Cannot do read-modify-write on 5401 */
1697 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1698 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1699 u32 phy_reg;
1700
1701 /* Set bit 14 with read-modify-write to preserve other bits */
1702 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1703 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1704 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1705 }
1706
1707 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1708 * jumbo frames transmission.
1709 */
1710 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1711 u32 phy_reg;
1712
1713 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1714 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1715 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1716 }
1717
1718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1719 /* adjust output voltage */
1720 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1721 }
1722
1723 tg3_phy_toggle_automdix(tp, 1);
1724 tg3_phy_set_wirespeed(tp);
1725 return 0;
1726}
1727
1728static void tg3_frob_aux_power(struct tg3 *tp)
1729{
1730 struct tg3 *tp_peer = tp;
1731
1732 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1733 return;
1734
1735 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1736 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1737 struct net_device *dev_peer;
1738
1739 dev_peer = pci_get_drvdata(tp->pdev_peer);
1740 /* remove_one() may have been run on the peer. */
1741 if (!dev_peer)
1742 tp_peer = tp;
1743 else
1744 tp_peer = netdev_priv(dev_peer);
1745 }
1746
1747 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1748 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1749 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1750 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1751 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1752 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1753 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1754 (GRC_LCLCTRL_GPIO_OE0 |
1755 GRC_LCLCTRL_GPIO_OE1 |
1756 GRC_LCLCTRL_GPIO_OE2 |
1757 GRC_LCLCTRL_GPIO_OUTPUT0 |
1758 GRC_LCLCTRL_GPIO_OUTPUT1),
1759 100);
1760 } else {
1761 u32 no_gpio2;
1762 u32 grc_local_ctrl = 0;
1763
1764 if (tp_peer != tp &&
1765 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1766 return;
1767
1768 /* Workaround to prevent overdrawing Amps. */
1769 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1770 ASIC_REV_5714) {
1771 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1772 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1773 grc_local_ctrl, 100);
1774 }
1775
1776 /* On 5753 and variants, GPIO2 cannot be used. */
1777 no_gpio2 = tp->nic_sram_data_cfg &
1778 NIC_SRAM_DATA_CFG_NO_GPIO2;
1779
1780 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1781 GRC_LCLCTRL_GPIO_OE1 |
1782 GRC_LCLCTRL_GPIO_OE2 |
1783 GRC_LCLCTRL_GPIO_OUTPUT1 |
1784 GRC_LCLCTRL_GPIO_OUTPUT2;
1785 if (no_gpio2) {
1786 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1787 GRC_LCLCTRL_GPIO_OUTPUT2);
1788 }
1789 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1790 grc_local_ctrl, 100);
1791
1792 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1793
1794 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1795 grc_local_ctrl, 100);
1796
1797 if (!no_gpio2) {
1798 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1799 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1800 grc_local_ctrl, 100);
1801 }
1802 }
1803 } else {
1804 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1805 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1806 if (tp_peer != tp &&
1807 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1808 return;
1809
1810 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1811 (GRC_LCLCTRL_GPIO_OE1 |
1812 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1813
1814 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1815 GRC_LCLCTRL_GPIO_OE1, 100);
1816
1817 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1818 (GRC_LCLCTRL_GPIO_OE1 |
1819 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1820 }
1821 }
1822}
1823
1824static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1825{
1826 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1827 return 1;
1828 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1829 if (speed != SPEED_10)
1830 return 1;
1831 } else if (speed == SPEED_10)
1832 return 1;
1833
1834 return 0;
1835}
1836
1837static int tg3_setup_phy(struct tg3 *, int);
1838
1839#define RESET_KIND_SHUTDOWN 0
1840#define RESET_KIND_INIT 1
1841#define RESET_KIND_SUSPEND 2
1842
1843static void tg3_write_sig_post_reset(struct tg3 *, int);
1844static int tg3_halt_cpu(struct tg3 *, u32);
1845static int tg3_nvram_lock(struct tg3 *);
1846static void tg3_nvram_unlock(struct tg3 *);
1847
1848static void tg3_power_down_phy(struct tg3 *tp)
1849{
1850 u32 val;
1851
1852 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1854 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1855 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1856
1857 sg_dig_ctrl |=
1858 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1859 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1860 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1861 }
1862 return;
1863 }
1864
1865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1866 tg3_bmcr_reset(tp);
1867 val = tr32(GRC_MISC_CFG);
1868 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1869 udelay(40);
1870 return;
1871 } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1872 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1873 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1874 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1875 }
1876
1877 /* The PHY should not be powered down on some chips because
1878 * of bugs.
1879 */
1880 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1881 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1882 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1883 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1884 return;
1885
1886 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1887 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1888 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1889 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1890 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1891 }
1892
1893 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1894}
1895
1896static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1897{
1898 u32 misc_host_ctrl;
1899 u16 power_control, power_caps;
1900 int pm = tp->pm_cap;
1901
1902 /* Make sure register accesses (indirect or otherwise)
1903 * will function correctly.
1904 */
1905 pci_write_config_dword(tp->pdev,
1906 TG3PCI_MISC_HOST_CTRL,
1907 tp->misc_host_ctrl);
1908
1909 pci_read_config_word(tp->pdev,
1910 pm + PCI_PM_CTRL,
1911 &power_control);
1912 power_control |= PCI_PM_CTRL_PME_STATUS;
1913 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1914 switch (state) {
1915 case PCI_D0:
1916 power_control |= 0;
1917 pci_write_config_word(tp->pdev,
1918 pm + PCI_PM_CTRL,
1919 power_control);
1920 udelay(100); /* Delay after power state change */
1921
1922 /* Switch out of Vaux if it is a NIC */
1923 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1924 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1925
1926 return 0;
1927
1928 case PCI_D1:
1929 power_control |= 1;
1930 break;
1931
1932 case PCI_D2:
1933 power_control |= 2;
1934 break;
1935
1936 case PCI_D3hot:
1937 power_control |= 3;
1938 break;
1939
1940 default:
1941 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1942 "requested.\n",
1943 tp->dev->name, state);
1944 return -EINVAL;
1945 };
1946
1947 power_control |= PCI_PM_CTRL_PME_ENABLE;
1948
1949 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1950 tw32(TG3PCI_MISC_HOST_CTRL,
1951 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1952
1953 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
1954 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
1955 !tp->link_config.phy_is_low_power) {
1956 struct phy_device *phydev;
1957 u32 advertising;
1958
1959 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1960
1961 tp->link_config.phy_is_low_power = 1;
1962
1963 tp->link_config.orig_speed = phydev->speed;
1964 tp->link_config.orig_duplex = phydev->duplex;
1965 tp->link_config.orig_autoneg = phydev->autoneg;
1966 tp->link_config.orig_advertising = phydev->advertising;
1967
1968 advertising = ADVERTISED_TP |
1969 ADVERTISED_Pause |
1970 ADVERTISED_Autoneg |
1971 ADVERTISED_10baseT_Half;
1972
1973 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
1974 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
1975 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1976 advertising |=
1977 ADVERTISED_100baseT_Half |
1978 ADVERTISED_100baseT_Full |
1979 ADVERTISED_10baseT_Full;
1980 else
1981 advertising |= ADVERTISED_10baseT_Full;
1982 }
1983
1984 phydev->advertising = advertising;
1985
1986 phy_start_aneg(phydev);
1987 }
1988 } else {
1989 if (tp->link_config.phy_is_low_power == 0) {
1990 tp->link_config.phy_is_low_power = 1;
1991 tp->link_config.orig_speed = tp->link_config.speed;
1992 tp->link_config.orig_duplex = tp->link_config.duplex;
1993 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1994 }
1995
1996 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1997 tp->link_config.speed = SPEED_10;
1998 tp->link_config.duplex = DUPLEX_HALF;
1999 tp->link_config.autoneg = AUTONEG_ENABLE;
2000 tg3_setup_phy(tp, 0);
2001 }
2002 }
2003
2004 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2005 u32 val;
2006
2007 val = tr32(GRC_VCPU_EXT_CTRL);
2008 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2009 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2010 int i;
2011 u32 val;
2012
2013 for (i = 0; i < 200; i++) {
2014 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2015 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2016 break;
2017 msleep(1);
2018 }
2019 }
2020 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2021 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2022 WOL_DRV_STATE_SHUTDOWN |
2023 WOL_DRV_WOL |
2024 WOL_SET_MAGIC_PKT);
2025
2026 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
2027
2028 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
2029 u32 mac_mode;
2030
2031 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2032 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
2033 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2034 udelay(40);
2035 }
2036
2037 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2038 mac_mode = MAC_MODE_PORT_MODE_GMII;
2039 else
2040 mac_mode = MAC_MODE_PORT_MODE_MII;
2041
2042 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2043 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2044 ASIC_REV_5700) {
2045 u32 speed = (tp->tg3_flags &
2046 TG3_FLAG_WOL_SPEED_100MB) ?
2047 SPEED_100 : SPEED_10;
2048 if (tg3_5700_link_polarity(tp, speed))
2049 mac_mode |= MAC_MODE_LINK_POLARITY;
2050 else
2051 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2052 }
2053 } else {
2054 mac_mode = MAC_MODE_PORT_MODE_TBI;
2055 }
2056
2057 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2058 tw32(MAC_LED_CTRL, tp->led_ctrl);
2059
2060 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
2061 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
2062 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2063
2064 tw32_f(MAC_MODE, mac_mode);
2065 udelay(100);
2066
2067 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2068 udelay(10);
2069 }
2070
2071 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2072 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2073 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2074 u32 base_val;
2075
2076 base_val = tp->pci_clock_ctrl;
2077 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2078 CLOCK_CTRL_TXCLK_DISABLE);
2079
2080 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2081 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2082 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2083 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2084 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2085 /* do nothing */
2086 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2087 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2088 u32 newbits1, newbits2;
2089
2090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2092 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2093 CLOCK_CTRL_TXCLK_DISABLE |
2094 CLOCK_CTRL_ALTCLK);
2095 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2096 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2097 newbits1 = CLOCK_CTRL_625_CORE;
2098 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2099 } else {
2100 newbits1 = CLOCK_CTRL_ALTCLK;
2101 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2102 }
2103
2104 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2105 40);
2106
2107 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2108 40);
2109
2110 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2111 u32 newbits3;
2112
2113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2114 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2115 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2116 CLOCK_CTRL_TXCLK_DISABLE |
2117 CLOCK_CTRL_44MHZ_CORE);
2118 } else {
2119 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2120 }
2121
2122 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2123 tp->pci_clock_ctrl | newbits3, 40);
2124 }
2125 }
2126
2127 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
2128 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
2129 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
2130 tg3_power_down_phy(tp);
2131
2132 tg3_frob_aux_power(tp);
2133
2134 /* Workaround for unstable PLL clock */
2135 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2136 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2137 u32 val = tr32(0x7d00);
2138
2139 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2140 tw32(0x7d00, val);
2141 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2142 int err;
2143
2144 err = tg3_nvram_lock(tp);
2145 tg3_halt_cpu(tp, RX_CPU_BASE);
2146 if (!err)
2147 tg3_nvram_unlock(tp);
2148 }
2149 }
2150
2151 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2152
2153 /* Finally, set the new power state. */
2154 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
2155 udelay(100); /* Delay after power state change */
2156
2157 return 0;
2158}
2159
2160static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2161{
2162 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2163 case MII_TG3_AUX_STAT_10HALF:
2164 *speed = SPEED_10;
2165 *duplex = DUPLEX_HALF;
2166 break;
2167
2168 case MII_TG3_AUX_STAT_10FULL:
2169 *speed = SPEED_10;
2170 *duplex = DUPLEX_FULL;
2171 break;
2172
2173 case MII_TG3_AUX_STAT_100HALF:
2174 *speed = SPEED_100;
2175 *duplex = DUPLEX_HALF;
2176 break;
2177
2178 case MII_TG3_AUX_STAT_100FULL:
2179 *speed = SPEED_100;
2180 *duplex = DUPLEX_FULL;
2181 break;
2182
2183 case MII_TG3_AUX_STAT_1000HALF:
2184 *speed = SPEED_1000;
2185 *duplex = DUPLEX_HALF;
2186 break;
2187
2188 case MII_TG3_AUX_STAT_1000FULL:
2189 *speed = SPEED_1000;
2190 *duplex = DUPLEX_FULL;
2191 break;
2192
2193 default:
2194 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2195 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2196 SPEED_10;
2197 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2198 DUPLEX_HALF;
2199 break;
2200 }
2201 *speed = SPEED_INVALID;
2202 *duplex = DUPLEX_INVALID;
2203 break;
2204 };
2205}
2206
2207static void tg3_phy_copper_begin(struct tg3 *tp)
2208{
2209 u32 new_adv;
2210 int i;
2211
2212 if (tp->link_config.phy_is_low_power) {
2213 /* Entering low power mode. Disable gigabit and
2214 * 100baseT advertisements.
2215 */
2216 tg3_writephy(tp, MII_TG3_CTRL, 0);
2217
2218 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2219 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2220 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2221 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2222
2223 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2224 } else if (tp->link_config.speed == SPEED_INVALID) {
2225 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2226 tp->link_config.advertising &=
2227 ~(ADVERTISED_1000baseT_Half |
2228 ADVERTISED_1000baseT_Full);
2229
2230 new_adv = ADVERTISE_CSMA;
2231 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2232 new_adv |= ADVERTISE_10HALF;
2233 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2234 new_adv |= ADVERTISE_10FULL;
2235 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2236 new_adv |= ADVERTISE_100HALF;
2237 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2238 new_adv |= ADVERTISE_100FULL;
2239
2240 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2241
2242 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2243
2244 if (tp->link_config.advertising &
2245 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2246 new_adv = 0;
2247 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2248 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2249 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2250 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2251 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2252 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2253 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2254 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2255 MII_TG3_CTRL_ENABLE_AS_MASTER);
2256 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2257 } else {
2258 tg3_writephy(tp, MII_TG3_CTRL, 0);
2259 }
2260 } else {
2261 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2262 new_adv |= ADVERTISE_CSMA;
2263
2264 /* Asking for a specific link mode. */
2265 if (tp->link_config.speed == SPEED_1000) {
2266 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2267
2268 if (tp->link_config.duplex == DUPLEX_FULL)
2269 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2270 else
2271 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2272 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2273 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2274 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2275 MII_TG3_CTRL_ENABLE_AS_MASTER);
2276 } else {
2277 if (tp->link_config.speed == SPEED_100) {
2278 if (tp->link_config.duplex == DUPLEX_FULL)
2279 new_adv |= ADVERTISE_100FULL;
2280 else
2281 new_adv |= ADVERTISE_100HALF;
2282 } else {
2283 if (tp->link_config.duplex == DUPLEX_FULL)
2284 new_adv |= ADVERTISE_10FULL;
2285 else
2286 new_adv |= ADVERTISE_10HALF;
2287 }
2288 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2289
2290 new_adv = 0;
2291 }
2292
2293 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2294 }
2295
2296 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2297 tp->link_config.speed != SPEED_INVALID) {
2298 u32 bmcr, orig_bmcr;
2299
2300 tp->link_config.active_speed = tp->link_config.speed;
2301 tp->link_config.active_duplex = tp->link_config.duplex;
2302
2303 bmcr = 0;
2304 switch (tp->link_config.speed) {
2305 default:
2306 case SPEED_10:
2307 break;
2308
2309 case SPEED_100:
2310 bmcr |= BMCR_SPEED100;
2311 break;
2312
2313 case SPEED_1000:
2314 bmcr |= TG3_BMCR_SPEED1000;
2315 break;
2316 };
2317
2318 if (tp->link_config.duplex == DUPLEX_FULL)
2319 bmcr |= BMCR_FULLDPLX;
2320
2321 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2322 (bmcr != orig_bmcr)) {
2323 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2324 for (i = 0; i < 1500; i++) {
2325 u32 tmp;
2326
2327 udelay(10);
2328 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2329 tg3_readphy(tp, MII_BMSR, &tmp))
2330 continue;
2331 if (!(tmp & BMSR_LSTATUS)) {
2332 udelay(40);
2333 break;
2334 }
2335 }
2336 tg3_writephy(tp, MII_BMCR, bmcr);
2337 udelay(40);
2338 }
2339 } else {
2340 tg3_writephy(tp, MII_BMCR,
2341 BMCR_ANENABLE | BMCR_ANRESTART);
2342 }
2343}
2344
2345static int tg3_init_5401phy_dsp(struct tg3 *tp)
2346{
2347 int err;
2348
2349 /* Turn off tap power management. */
2350 /* Set Extended packet length bit */
2351 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2352
2353 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2354 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2355
2356 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2357 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2358
2359 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2360 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2361
2362 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2363 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2364
2365 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2366 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2367
2368 udelay(40);
2369
2370 return err;
2371}
2372
2373static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2374{
2375 u32 adv_reg, all_mask = 0;
2376
2377 if (mask & ADVERTISED_10baseT_Half)
2378 all_mask |= ADVERTISE_10HALF;
2379 if (mask & ADVERTISED_10baseT_Full)
2380 all_mask |= ADVERTISE_10FULL;
2381 if (mask & ADVERTISED_100baseT_Half)
2382 all_mask |= ADVERTISE_100HALF;
2383 if (mask & ADVERTISED_100baseT_Full)
2384 all_mask |= ADVERTISE_100FULL;
2385
2386 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2387 return 0;
2388
2389 if ((adv_reg & all_mask) != all_mask)
2390 return 0;
2391 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2392 u32 tg3_ctrl;
2393
2394 all_mask = 0;
2395 if (mask & ADVERTISED_1000baseT_Half)
2396 all_mask |= ADVERTISE_1000HALF;
2397 if (mask & ADVERTISED_1000baseT_Full)
2398 all_mask |= ADVERTISE_1000FULL;
2399
2400 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2401 return 0;
2402
2403 if ((tg3_ctrl & all_mask) != all_mask)
2404 return 0;
2405 }
2406 return 1;
2407}
2408
2409static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2410{
2411 u32 curadv, reqadv;
2412
2413 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2414 return 1;
2415
2416 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2417 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2418
2419 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2420 if (curadv != reqadv)
2421 return 0;
2422
2423 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2424 tg3_readphy(tp, MII_LPA, rmtadv);
2425 } else {
2426 /* Reprogram the advertisement register, even if it
2427 * does not affect the current link. If the link
2428 * gets renegotiated in the future, we can save an
2429 * additional renegotiation cycle by advertising
2430 * it correctly in the first place.
2431 */
2432 if (curadv != reqadv) {
2433 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2434 ADVERTISE_PAUSE_ASYM);
2435 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2436 }
2437 }
2438
2439 return 1;
2440}
2441
2442static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2443{
2444 int current_link_up;
2445 u32 bmsr, dummy;
2446 u32 lcl_adv, rmt_adv;
2447 u16 current_speed;
2448 u8 current_duplex;
2449 int i, err;
2450
2451 tw32(MAC_EVENT, 0);
2452
2453 tw32_f(MAC_STATUS,
2454 (MAC_STATUS_SYNC_CHANGED |
2455 MAC_STATUS_CFG_CHANGED |
2456 MAC_STATUS_MI_COMPLETION |
2457 MAC_STATUS_LNKSTATE_CHANGED));
2458 udelay(40);
2459
2460 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2461 tw32_f(MAC_MI_MODE,
2462 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2463 udelay(80);
2464 }
2465
2466 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2467
2468 /* Some third-party PHYs need to be reset on link going
2469 * down.
2470 */
2471 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2472 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2474 netif_carrier_ok(tp->dev)) {
2475 tg3_readphy(tp, MII_BMSR, &bmsr);
2476 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2477 !(bmsr & BMSR_LSTATUS))
2478 force_reset = 1;
2479 }
2480 if (force_reset)
2481 tg3_phy_reset(tp);
2482
2483 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2484 tg3_readphy(tp, MII_BMSR, &bmsr);
2485 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2486 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2487 bmsr = 0;
2488
2489 if (!(bmsr & BMSR_LSTATUS)) {
2490 err = tg3_init_5401phy_dsp(tp);
2491 if (err)
2492 return err;
2493
2494 tg3_readphy(tp, MII_BMSR, &bmsr);
2495 for (i = 0; i < 1000; i++) {
2496 udelay(10);
2497 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2498 (bmsr & BMSR_LSTATUS)) {
2499 udelay(40);
2500 break;
2501 }
2502 }
2503
2504 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2505 !(bmsr & BMSR_LSTATUS) &&
2506 tp->link_config.active_speed == SPEED_1000) {
2507 err = tg3_phy_reset(tp);
2508 if (!err)
2509 err = tg3_init_5401phy_dsp(tp);
2510 if (err)
2511 return err;
2512 }
2513 }
2514 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2515 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2516 /* 5701 {A0,B0} CRC bug workaround */
2517 tg3_writephy(tp, 0x15, 0x0a75);
2518 tg3_writephy(tp, 0x1c, 0x8c68);
2519 tg3_writephy(tp, 0x1c, 0x8d68);
2520 tg3_writephy(tp, 0x1c, 0x8c68);
2521 }
2522
2523 /* Clear pending interrupts... */
2524 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2525 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2526
2527 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2528 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2529 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2530 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2531
2532 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2534 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2535 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2536 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2537 else
2538 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2539 }
2540
2541 current_link_up = 0;
2542 current_speed = SPEED_INVALID;
2543 current_duplex = DUPLEX_INVALID;
2544
2545 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2546 u32 val;
2547
2548 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2549 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2550 if (!(val & (1 << 10))) {
2551 val |= (1 << 10);
2552 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2553 goto relink;
2554 }
2555 }
2556
2557 bmsr = 0;
2558 for (i = 0; i < 100; i++) {
2559 tg3_readphy(tp, MII_BMSR, &bmsr);
2560 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2561 (bmsr & BMSR_LSTATUS))
2562 break;
2563 udelay(40);
2564 }
2565
2566 if (bmsr & BMSR_LSTATUS) {
2567 u32 aux_stat, bmcr;
2568
2569 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2570 for (i = 0; i < 2000; i++) {
2571 udelay(10);
2572 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2573 aux_stat)
2574 break;
2575 }
2576
2577 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2578 &current_speed,
2579 &current_duplex);
2580
2581 bmcr = 0;
2582 for (i = 0; i < 200; i++) {
2583 tg3_readphy(tp, MII_BMCR, &bmcr);
2584 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2585 continue;
2586 if (bmcr && bmcr != 0x7fff)
2587 break;
2588 udelay(10);
2589 }
2590
2591 lcl_adv = 0;
2592 rmt_adv = 0;
2593
2594 tp->link_config.active_speed = current_speed;
2595 tp->link_config.active_duplex = current_duplex;
2596
2597 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2598 if ((bmcr & BMCR_ANENABLE) &&
2599 tg3_copper_is_advertising_all(tp,
2600 tp->link_config.advertising)) {
2601 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2602 &rmt_adv))
2603 current_link_up = 1;
2604 }
2605 } else {
2606 if (!(bmcr & BMCR_ANENABLE) &&
2607 tp->link_config.speed == current_speed &&
2608 tp->link_config.duplex == current_duplex &&
2609 tp->link_config.flowctrl ==
2610 tp->link_config.active_flowctrl) {
2611 current_link_up = 1;
2612 }
2613 }
2614
2615 if (current_link_up == 1 &&
2616 tp->link_config.active_duplex == DUPLEX_FULL)
2617 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2618 }
2619
2620relink:
2621 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2622 u32 tmp;
2623
2624 tg3_phy_copper_begin(tp);
2625
2626 tg3_readphy(tp, MII_BMSR, &tmp);
2627 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2628 (tmp & BMSR_LSTATUS))
2629 current_link_up = 1;
2630 }
2631
2632 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2633 if (current_link_up == 1) {
2634 if (tp->link_config.active_speed == SPEED_100 ||
2635 tp->link_config.active_speed == SPEED_10)
2636 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2637 else
2638 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2639 } else
2640 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2641
2642 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2643 if (tp->link_config.active_duplex == DUPLEX_HALF)
2644 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2645
2646 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2647 if (current_link_up == 1 &&
2648 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2649 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2650 else
2651 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2652 }
2653
2654 /* ??? Without this setting Netgear GA302T PHY does not
2655 * ??? send/receive packets...
2656 */
2657 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2658 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2659 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2660 tw32_f(MAC_MI_MODE, tp->mi_mode);
2661 udelay(80);
2662 }
2663
2664 tw32_f(MAC_MODE, tp->mac_mode);
2665 udelay(40);
2666
2667 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2668 /* Polled via timer. */
2669 tw32_f(MAC_EVENT, 0);
2670 } else {
2671 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2672 }
2673 udelay(40);
2674
2675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2676 current_link_up == 1 &&
2677 tp->link_config.active_speed == SPEED_1000 &&
2678 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2679 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2680 udelay(120);
2681 tw32_f(MAC_STATUS,
2682 (MAC_STATUS_SYNC_CHANGED |
2683 MAC_STATUS_CFG_CHANGED));
2684 udelay(40);
2685 tg3_write_mem(tp,
2686 NIC_SRAM_FIRMWARE_MBOX,
2687 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2688 }
2689
2690 if (current_link_up != netif_carrier_ok(tp->dev)) {
2691 if (current_link_up)
2692 netif_carrier_on(tp->dev);
2693 else
2694 netif_carrier_off(tp->dev);
2695 tg3_link_report(tp);
2696 }
2697
2698 return 0;
2699}
2700
2701struct tg3_fiber_aneginfo {
2702 int state;
2703#define ANEG_STATE_UNKNOWN 0
2704#define ANEG_STATE_AN_ENABLE 1
2705#define ANEG_STATE_RESTART_INIT 2
2706#define ANEG_STATE_RESTART 3
2707#define ANEG_STATE_DISABLE_LINK_OK 4
2708#define ANEG_STATE_ABILITY_DETECT_INIT 5
2709#define ANEG_STATE_ABILITY_DETECT 6
2710#define ANEG_STATE_ACK_DETECT_INIT 7
2711#define ANEG_STATE_ACK_DETECT 8
2712#define ANEG_STATE_COMPLETE_ACK_INIT 9
2713#define ANEG_STATE_COMPLETE_ACK 10
2714#define ANEG_STATE_IDLE_DETECT_INIT 11
2715#define ANEG_STATE_IDLE_DETECT 12
2716#define ANEG_STATE_LINK_OK 13
2717#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2718#define ANEG_STATE_NEXT_PAGE_WAIT 15
2719
2720 u32 flags;
2721#define MR_AN_ENABLE 0x00000001
2722#define MR_RESTART_AN 0x00000002
2723#define MR_AN_COMPLETE 0x00000004
2724#define MR_PAGE_RX 0x00000008
2725#define MR_NP_LOADED 0x00000010
2726#define MR_TOGGLE_TX 0x00000020
2727#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2728#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2729#define MR_LP_ADV_SYM_PAUSE 0x00000100
2730#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2731#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2732#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2733#define MR_LP_ADV_NEXT_PAGE 0x00001000
2734#define MR_TOGGLE_RX 0x00002000
2735#define MR_NP_RX 0x00004000
2736
2737#define MR_LINK_OK 0x80000000
2738
2739 unsigned long link_time, cur_time;
2740
2741 u32 ability_match_cfg;
2742 int ability_match_count;
2743
2744 char ability_match, idle_match, ack_match;
2745
2746 u32 txconfig, rxconfig;
2747#define ANEG_CFG_NP 0x00000080
2748#define ANEG_CFG_ACK 0x00000040
2749#define ANEG_CFG_RF2 0x00000020
2750#define ANEG_CFG_RF1 0x00000010
2751#define ANEG_CFG_PS2 0x00000001
2752#define ANEG_CFG_PS1 0x00008000
2753#define ANEG_CFG_HD 0x00004000
2754#define ANEG_CFG_FD 0x00002000
2755#define ANEG_CFG_INVAL 0x00001f06
2756
2757};
2758#define ANEG_OK 0
2759#define ANEG_DONE 1
2760#define ANEG_TIMER_ENAB 2
2761#define ANEG_FAILED -1
2762
2763#define ANEG_STATE_SETTLE_TIME 10000
2764
2765static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2766 struct tg3_fiber_aneginfo *ap)
2767{
2768 u16 flowctrl;
2769 unsigned long delta;
2770 u32 rx_cfg_reg;
2771 int ret;
2772
2773 if (ap->state == ANEG_STATE_UNKNOWN) {
2774 ap->rxconfig = 0;
2775 ap->link_time = 0;
2776 ap->cur_time = 0;
2777 ap->ability_match_cfg = 0;
2778 ap->ability_match_count = 0;
2779 ap->ability_match = 0;
2780 ap->idle_match = 0;
2781 ap->ack_match = 0;
2782 }
2783 ap->cur_time++;
2784
2785 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2786 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2787
2788 if (rx_cfg_reg != ap->ability_match_cfg) {
2789 ap->ability_match_cfg = rx_cfg_reg;
2790 ap->ability_match = 0;
2791 ap->ability_match_count = 0;
2792 } else {
2793 if (++ap->ability_match_count > 1) {
2794 ap->ability_match = 1;
2795 ap->ability_match_cfg = rx_cfg_reg;
2796 }
2797 }
2798 if (rx_cfg_reg & ANEG_CFG_ACK)
2799 ap->ack_match = 1;
2800 else
2801 ap->ack_match = 0;
2802
2803 ap->idle_match = 0;
2804 } else {
2805 ap->idle_match = 1;
2806 ap->ability_match_cfg = 0;
2807 ap->ability_match_count = 0;
2808 ap->ability_match = 0;
2809 ap->ack_match = 0;
2810
2811 rx_cfg_reg = 0;
2812 }
2813
2814 ap->rxconfig = rx_cfg_reg;
2815 ret = ANEG_OK;
2816
2817 switch(ap->state) {
2818 case ANEG_STATE_UNKNOWN:
2819 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2820 ap->state = ANEG_STATE_AN_ENABLE;
2821
2822 /* fallthru */
2823 case ANEG_STATE_AN_ENABLE:
2824 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2825 if (ap->flags & MR_AN_ENABLE) {
2826 ap->link_time = 0;
2827 ap->cur_time = 0;
2828 ap->ability_match_cfg = 0;
2829 ap->ability_match_count = 0;
2830 ap->ability_match = 0;
2831 ap->idle_match = 0;
2832 ap->ack_match = 0;
2833
2834 ap->state = ANEG_STATE_RESTART_INIT;
2835 } else {
2836 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2837 }
2838 break;
2839
2840 case ANEG_STATE_RESTART_INIT:
2841 ap->link_time = ap->cur_time;
2842 ap->flags &= ~(MR_NP_LOADED);
2843 ap->txconfig = 0;
2844 tw32(MAC_TX_AUTO_NEG, 0);
2845 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2846 tw32_f(MAC_MODE, tp->mac_mode);
2847 udelay(40);
2848
2849 ret = ANEG_TIMER_ENAB;
2850 ap->state = ANEG_STATE_RESTART;
2851
2852 /* fallthru */
2853 case ANEG_STATE_RESTART:
2854 delta = ap->cur_time - ap->link_time;
2855 if (delta > ANEG_STATE_SETTLE_TIME) {
2856 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2857 } else {
2858 ret = ANEG_TIMER_ENAB;
2859 }
2860 break;
2861
2862 case ANEG_STATE_DISABLE_LINK_OK:
2863 ret = ANEG_DONE;
2864 break;
2865
2866 case ANEG_STATE_ABILITY_DETECT_INIT:
2867 ap->flags &= ~(MR_TOGGLE_TX);
2868 ap->txconfig = ANEG_CFG_FD;
2869 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2870 if (flowctrl & ADVERTISE_1000XPAUSE)
2871 ap->txconfig |= ANEG_CFG_PS1;
2872 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2873 ap->txconfig |= ANEG_CFG_PS2;
2874 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2875 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2876 tw32_f(MAC_MODE, tp->mac_mode);
2877 udelay(40);
2878
2879 ap->state = ANEG_STATE_ABILITY_DETECT;
2880 break;
2881
2882 case ANEG_STATE_ABILITY_DETECT:
2883 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2884 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2885 }
2886 break;
2887
2888 case ANEG_STATE_ACK_DETECT_INIT:
2889 ap->txconfig |= ANEG_CFG_ACK;
2890 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2891 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2892 tw32_f(MAC_MODE, tp->mac_mode);
2893 udelay(40);
2894
2895 ap->state = ANEG_STATE_ACK_DETECT;
2896
2897 /* fallthru */
2898 case ANEG_STATE_ACK_DETECT:
2899 if (ap->ack_match != 0) {
2900 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2901 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2902 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2903 } else {
2904 ap->state = ANEG_STATE_AN_ENABLE;
2905 }
2906 } else if (ap->ability_match != 0 &&
2907 ap->rxconfig == 0) {
2908 ap->state = ANEG_STATE_AN_ENABLE;
2909 }
2910 break;
2911
2912 case ANEG_STATE_COMPLETE_ACK_INIT:
2913 if (ap->rxconfig & ANEG_CFG_INVAL) {
2914 ret = ANEG_FAILED;
2915 break;
2916 }
2917 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2918 MR_LP_ADV_HALF_DUPLEX |
2919 MR_LP_ADV_SYM_PAUSE |
2920 MR_LP_ADV_ASYM_PAUSE |
2921 MR_LP_ADV_REMOTE_FAULT1 |
2922 MR_LP_ADV_REMOTE_FAULT2 |
2923 MR_LP_ADV_NEXT_PAGE |
2924 MR_TOGGLE_RX |
2925 MR_NP_RX);
2926 if (ap->rxconfig & ANEG_CFG_FD)
2927 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2928 if (ap->rxconfig & ANEG_CFG_HD)
2929 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2930 if (ap->rxconfig & ANEG_CFG_PS1)
2931 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2932 if (ap->rxconfig & ANEG_CFG_PS2)
2933 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2934 if (ap->rxconfig & ANEG_CFG_RF1)
2935 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2936 if (ap->rxconfig & ANEG_CFG_RF2)
2937 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2938 if (ap->rxconfig & ANEG_CFG_NP)
2939 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2940
2941 ap->link_time = ap->cur_time;
2942
2943 ap->flags ^= (MR_TOGGLE_TX);
2944 if (ap->rxconfig & 0x0008)
2945 ap->flags |= MR_TOGGLE_RX;
2946 if (ap->rxconfig & ANEG_CFG_NP)
2947 ap->flags |= MR_NP_RX;
2948 ap->flags |= MR_PAGE_RX;
2949
2950 ap->state = ANEG_STATE_COMPLETE_ACK;
2951 ret = ANEG_TIMER_ENAB;
2952 break;
2953
2954 case ANEG_STATE_COMPLETE_ACK:
2955 if (ap->ability_match != 0 &&
2956 ap->rxconfig == 0) {
2957 ap->state = ANEG_STATE_AN_ENABLE;
2958 break;
2959 }
2960 delta = ap->cur_time - ap->link_time;
2961 if (delta > ANEG_STATE_SETTLE_TIME) {
2962 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2963 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2964 } else {
2965 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2966 !(ap->flags & MR_NP_RX)) {
2967 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2968 } else {
2969 ret = ANEG_FAILED;
2970 }
2971 }
2972 }
2973 break;
2974
2975 case ANEG_STATE_IDLE_DETECT_INIT:
2976 ap->link_time = ap->cur_time;
2977 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2978 tw32_f(MAC_MODE, tp->mac_mode);
2979 udelay(40);
2980
2981 ap->state = ANEG_STATE_IDLE_DETECT;
2982 ret = ANEG_TIMER_ENAB;
2983 break;
2984
2985 case ANEG_STATE_IDLE_DETECT:
2986 if (ap->ability_match != 0 &&
2987 ap->rxconfig == 0) {
2988 ap->state = ANEG_STATE_AN_ENABLE;
2989 break;
2990 }
2991 delta = ap->cur_time - ap->link_time;
2992 if (delta > ANEG_STATE_SETTLE_TIME) {
2993 /* XXX another gem from the Broadcom driver :( */
2994 ap->state = ANEG_STATE_LINK_OK;
2995 }
2996 break;
2997
2998 case ANEG_STATE_LINK_OK:
2999 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3000 ret = ANEG_DONE;
3001 break;
3002
3003 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3004 /* ??? unimplemented */
3005 break;
3006
3007 case ANEG_STATE_NEXT_PAGE_WAIT:
3008 /* ??? unimplemented */
3009 break;
3010
3011 default:
3012 ret = ANEG_FAILED;
3013 break;
3014 };
3015
3016 return ret;
3017}
3018
3019static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3020{
3021 int res = 0;
3022 struct tg3_fiber_aneginfo aninfo;
3023 int status = ANEG_FAILED;
3024 unsigned int tick;
3025 u32 tmp;
3026
3027 tw32_f(MAC_TX_AUTO_NEG, 0);
3028
3029 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3030 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3031 udelay(40);
3032
3033 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3034 udelay(40);
3035
3036 memset(&aninfo, 0, sizeof(aninfo));
3037 aninfo.flags |= MR_AN_ENABLE;
3038 aninfo.state = ANEG_STATE_UNKNOWN;
3039 aninfo.cur_time = 0;
3040 tick = 0;
3041 while (++tick < 195000) {
3042 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3043 if (status == ANEG_DONE || status == ANEG_FAILED)
3044 break;
3045
3046 udelay(1);
3047 }
3048
3049 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3050 tw32_f(MAC_MODE, tp->mac_mode);
3051 udelay(40);
3052
3053 *txflags = aninfo.txconfig;
3054 *rxflags = aninfo.flags;
3055
3056 if (status == ANEG_DONE &&
3057 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3058 MR_LP_ADV_FULL_DUPLEX)))
3059 res = 1;
3060
3061 return res;
3062}
3063
3064static void tg3_init_bcm8002(struct tg3 *tp)
3065{
3066 u32 mac_status = tr32(MAC_STATUS);
3067 int i;
3068
3069 /* Reset when initting first time or we have a link. */
3070 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3071 !(mac_status & MAC_STATUS_PCS_SYNCED))
3072 return;
3073
3074 /* Set PLL lock range. */
3075 tg3_writephy(tp, 0x16, 0x8007);
3076
3077 /* SW reset */
3078 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3079
3080 /* Wait for reset to complete. */
3081 /* XXX schedule_timeout() ... */
3082 for (i = 0; i < 500; i++)
3083 udelay(10);
3084
3085 /* Config mode; select PMA/Ch 1 regs. */
3086 tg3_writephy(tp, 0x10, 0x8411);
3087
3088 /* Enable auto-lock and comdet, select txclk for tx. */
3089 tg3_writephy(tp, 0x11, 0x0a10);
3090
3091 tg3_writephy(tp, 0x18, 0x00a0);
3092 tg3_writephy(tp, 0x16, 0x41ff);
3093
3094 /* Assert and deassert POR. */
3095 tg3_writephy(tp, 0x13, 0x0400);
3096 udelay(40);
3097 tg3_writephy(tp, 0x13, 0x0000);
3098
3099 tg3_writephy(tp, 0x11, 0x0a50);
3100 udelay(40);
3101 tg3_writephy(tp, 0x11, 0x0a10);
3102
3103 /* Wait for signal to stabilize */
3104 /* XXX schedule_timeout() ... */
3105 for (i = 0; i < 15000; i++)
3106 udelay(10);
3107
3108 /* Deselect the channel register so we can read the PHYID
3109 * later.
3110 */
3111 tg3_writephy(tp, 0x10, 0x8011);
3112}
3113
3114static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3115{
3116 u16 flowctrl;
3117 u32 sg_dig_ctrl, sg_dig_status;
3118 u32 serdes_cfg, expected_sg_dig_ctrl;
3119 int workaround, port_a;
3120 int current_link_up;
3121
3122 serdes_cfg = 0;
3123 expected_sg_dig_ctrl = 0;
3124 workaround = 0;
3125 port_a = 1;
3126 current_link_up = 0;
3127
3128 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3129 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3130 workaround = 1;
3131 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3132 port_a = 0;
3133
3134 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3135 /* preserve bits 20-23 for voltage regulator */
3136 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3137 }
3138
3139 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3140
3141 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3142 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3143 if (workaround) {
3144 u32 val = serdes_cfg;
3145
3146 if (port_a)
3147 val |= 0xc010000;
3148 else
3149 val |= 0x4010000;
3150 tw32_f(MAC_SERDES_CFG, val);
3151 }
3152
3153 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3154 }
3155 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3156 tg3_setup_flow_control(tp, 0, 0);
3157 current_link_up = 1;
3158 }
3159 goto out;
3160 }
3161
3162 /* Want auto-negotiation. */
3163 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3164
3165 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3166 if (flowctrl & ADVERTISE_1000XPAUSE)
3167 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3168 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3169 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3170
3171 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3172 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3173 tp->serdes_counter &&
3174 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3175 MAC_STATUS_RCVD_CFG)) ==
3176 MAC_STATUS_PCS_SYNCED)) {
3177 tp->serdes_counter--;
3178 current_link_up = 1;
3179 goto out;
3180 }
3181restart_autoneg:
3182 if (workaround)
3183 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3184 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3185 udelay(5);
3186 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3187
3188 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3189 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3190 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3191 MAC_STATUS_SIGNAL_DET)) {
3192 sg_dig_status = tr32(SG_DIG_STATUS);
3193 mac_status = tr32(MAC_STATUS);
3194
3195 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3196 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3197 u32 local_adv = 0, remote_adv = 0;
3198
3199 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3200 local_adv |= ADVERTISE_1000XPAUSE;
3201 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3202 local_adv |= ADVERTISE_1000XPSE_ASYM;
3203
3204 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3205 remote_adv |= LPA_1000XPAUSE;
3206 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3207 remote_adv |= LPA_1000XPAUSE_ASYM;
3208
3209 tg3_setup_flow_control(tp, local_adv, remote_adv);
3210 current_link_up = 1;
3211 tp->serdes_counter = 0;
3212 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3213 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3214 if (tp->serdes_counter)
3215 tp->serdes_counter--;
3216 else {
3217 if (workaround) {
3218 u32 val = serdes_cfg;
3219
3220 if (port_a)
3221 val |= 0xc010000;
3222 else
3223 val |= 0x4010000;
3224
3225 tw32_f(MAC_SERDES_CFG, val);
3226 }
3227
3228 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3229 udelay(40);
3230
3231 /* Link parallel detection - link is up */
3232 /* only if we have PCS_SYNC and not */
3233 /* receiving config code words */
3234 mac_status = tr32(MAC_STATUS);
3235 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3236 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3237 tg3_setup_flow_control(tp, 0, 0);
3238 current_link_up = 1;
3239 tp->tg3_flags2 |=
3240 TG3_FLG2_PARALLEL_DETECT;
3241 tp->serdes_counter =
3242 SERDES_PARALLEL_DET_TIMEOUT;
3243 } else
3244 goto restart_autoneg;
3245 }
3246 }
3247 } else {
3248 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3249 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3250 }
3251
3252out:
3253 return current_link_up;
3254}
3255
3256static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3257{
3258 int current_link_up = 0;
3259
3260 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3261 goto out;
3262
3263 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3264 u32 txflags, rxflags;
3265 int i;
3266
3267 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3268 u32 local_adv = 0, remote_adv = 0;
3269
3270 if (txflags & ANEG_CFG_PS1)
3271 local_adv |= ADVERTISE_1000XPAUSE;
3272 if (txflags & ANEG_CFG_PS2)
3273 local_adv |= ADVERTISE_1000XPSE_ASYM;
3274
3275 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3276 remote_adv |= LPA_1000XPAUSE;
3277 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3278 remote_adv |= LPA_1000XPAUSE_ASYM;
3279
3280 tg3_setup_flow_control(tp, local_adv, remote_adv);
3281
3282 current_link_up = 1;
3283 }
3284 for (i = 0; i < 30; i++) {
3285 udelay(20);
3286 tw32_f(MAC_STATUS,
3287 (MAC_STATUS_SYNC_CHANGED |
3288 MAC_STATUS_CFG_CHANGED));
3289 udelay(40);
3290 if ((tr32(MAC_STATUS) &
3291 (MAC_STATUS_SYNC_CHANGED |
3292 MAC_STATUS_CFG_CHANGED)) == 0)
3293 break;
3294 }
3295
3296 mac_status = tr32(MAC_STATUS);
3297 if (current_link_up == 0 &&
3298 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3299 !(mac_status & MAC_STATUS_RCVD_CFG))
3300 current_link_up = 1;
3301 } else {
3302 tg3_setup_flow_control(tp, 0, 0);
3303
3304 /* Forcing 1000FD link up. */
3305 current_link_up = 1;
3306
3307 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3308 udelay(40);
3309
3310 tw32_f(MAC_MODE, tp->mac_mode);
3311 udelay(40);
3312 }
3313
3314out:
3315 return current_link_up;
3316}
3317
3318static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3319{
3320 u32 orig_pause_cfg;
3321 u16 orig_active_speed;
3322 u8 orig_active_duplex;
3323 u32 mac_status;
3324 int current_link_up;
3325 int i;
3326
3327 orig_pause_cfg = tp->link_config.active_flowctrl;
3328 orig_active_speed = tp->link_config.active_speed;
3329 orig_active_duplex = tp->link_config.active_duplex;
3330
3331 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3332 netif_carrier_ok(tp->dev) &&
3333 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3334 mac_status = tr32(MAC_STATUS);
3335 mac_status &= (MAC_STATUS_PCS_SYNCED |
3336 MAC_STATUS_SIGNAL_DET |
3337 MAC_STATUS_CFG_CHANGED |
3338 MAC_STATUS_RCVD_CFG);
3339 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3340 MAC_STATUS_SIGNAL_DET)) {
3341 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3342 MAC_STATUS_CFG_CHANGED));
3343 return 0;
3344 }
3345 }
3346
3347 tw32_f(MAC_TX_AUTO_NEG, 0);
3348
3349 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3350 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3351 tw32_f(MAC_MODE, tp->mac_mode);
3352 udelay(40);
3353
3354 if (tp->phy_id == PHY_ID_BCM8002)
3355 tg3_init_bcm8002(tp);
3356
3357 /* Enable link change event even when serdes polling. */
3358 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3359 udelay(40);
3360
3361 current_link_up = 0;
3362 mac_status = tr32(MAC_STATUS);
3363
3364 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3365 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3366 else
3367 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3368
3369 tp->hw_status->status =
3370 (SD_STATUS_UPDATED |
3371 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3372
3373 for (i = 0; i < 100; i++) {
3374 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3375 MAC_STATUS_CFG_CHANGED));
3376 udelay(5);
3377 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3378 MAC_STATUS_CFG_CHANGED |
3379 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3380 break;
3381 }
3382
3383 mac_status = tr32(MAC_STATUS);
3384 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3385 current_link_up = 0;
3386 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3387 tp->serdes_counter == 0) {
3388 tw32_f(MAC_MODE, (tp->mac_mode |
3389 MAC_MODE_SEND_CONFIGS));
3390 udelay(1);
3391 tw32_f(MAC_MODE, tp->mac_mode);
3392 }
3393 }
3394
3395 if (current_link_up == 1) {
3396 tp->link_config.active_speed = SPEED_1000;
3397 tp->link_config.active_duplex = DUPLEX_FULL;
3398 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3399 LED_CTRL_LNKLED_OVERRIDE |
3400 LED_CTRL_1000MBPS_ON));
3401 } else {
3402 tp->link_config.active_speed = SPEED_INVALID;
3403 tp->link_config.active_duplex = DUPLEX_INVALID;
3404 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3405 LED_CTRL_LNKLED_OVERRIDE |
3406 LED_CTRL_TRAFFIC_OVERRIDE));
3407 }
3408
3409 if (current_link_up != netif_carrier_ok(tp->dev)) {
3410 if (current_link_up)
3411 netif_carrier_on(tp->dev);
3412 else
3413 netif_carrier_off(tp->dev);
3414 tg3_link_report(tp);
3415 } else {
3416 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3417 if (orig_pause_cfg != now_pause_cfg ||
3418 orig_active_speed != tp->link_config.active_speed ||
3419 orig_active_duplex != tp->link_config.active_duplex)
3420 tg3_link_report(tp);
3421 }
3422
3423 return 0;
3424}
3425
3426static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3427{
3428 int current_link_up, err = 0;
3429 u32 bmsr, bmcr;
3430 u16 current_speed;
3431 u8 current_duplex;
3432 u32 local_adv, remote_adv;
3433
3434 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3435 tw32_f(MAC_MODE, tp->mac_mode);
3436 udelay(40);
3437
3438 tw32(MAC_EVENT, 0);
3439
3440 tw32_f(MAC_STATUS,
3441 (MAC_STATUS_SYNC_CHANGED |
3442 MAC_STATUS_CFG_CHANGED |
3443 MAC_STATUS_MI_COMPLETION |
3444 MAC_STATUS_LNKSTATE_CHANGED));
3445 udelay(40);
3446
3447 if (force_reset)
3448 tg3_phy_reset(tp);
3449
3450 current_link_up = 0;
3451 current_speed = SPEED_INVALID;
3452 current_duplex = DUPLEX_INVALID;
3453
3454 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3455 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3457 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3458 bmsr |= BMSR_LSTATUS;
3459 else
3460 bmsr &= ~BMSR_LSTATUS;
3461 }
3462
3463 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3464
3465 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3466 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3467 tp->link_config.flowctrl == tp->link_config.active_flowctrl) {
3468 /* do nothing, just check for link up at the end */
3469 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3470 u32 adv, new_adv;
3471
3472 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3473 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3474 ADVERTISE_1000XPAUSE |
3475 ADVERTISE_1000XPSE_ASYM |
3476 ADVERTISE_SLCT);
3477
3478 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3479
3480 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3481 new_adv |= ADVERTISE_1000XHALF;
3482 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3483 new_adv |= ADVERTISE_1000XFULL;
3484
3485 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3486 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3487 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3488 tg3_writephy(tp, MII_BMCR, bmcr);
3489
3490 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3491 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3492 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3493
3494 return err;
3495 }
3496 } else {
3497 u32 new_bmcr;
3498
3499 bmcr &= ~BMCR_SPEED1000;
3500 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3501
3502 if (tp->link_config.duplex == DUPLEX_FULL)
3503 new_bmcr |= BMCR_FULLDPLX;
3504
3505 if (new_bmcr != bmcr) {
3506 /* BMCR_SPEED1000 is a reserved bit that needs
3507 * to be set on write.
3508 */
3509 new_bmcr |= BMCR_SPEED1000;
3510
3511 /* Force a linkdown */
3512 if (netif_carrier_ok(tp->dev)) {
3513 u32 adv;
3514
3515 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3516 adv &= ~(ADVERTISE_1000XFULL |
3517 ADVERTISE_1000XHALF |
3518 ADVERTISE_SLCT);
3519 tg3_writephy(tp, MII_ADVERTISE, adv);
3520 tg3_writephy(tp, MII_BMCR, bmcr |
3521 BMCR_ANRESTART |
3522 BMCR_ANENABLE);
3523 udelay(10);
3524 netif_carrier_off(tp->dev);
3525 }
3526 tg3_writephy(tp, MII_BMCR, new_bmcr);
3527 bmcr = new_bmcr;
3528 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3529 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3530 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3531 ASIC_REV_5714) {
3532 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3533 bmsr |= BMSR_LSTATUS;
3534 else
3535 bmsr &= ~BMSR_LSTATUS;
3536 }
3537 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3538 }
3539 }
3540
3541 if (bmsr & BMSR_LSTATUS) {
3542 current_speed = SPEED_1000;
3543 current_link_up = 1;
3544 if (bmcr & BMCR_FULLDPLX)
3545 current_duplex = DUPLEX_FULL;
3546 else
3547 current_duplex = DUPLEX_HALF;
3548
3549 local_adv = 0;
3550 remote_adv = 0;
3551
3552 if (bmcr & BMCR_ANENABLE) {
3553 u32 common;
3554
3555 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3556 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3557 common = local_adv & remote_adv;
3558 if (common & (ADVERTISE_1000XHALF |
3559 ADVERTISE_1000XFULL)) {
3560 if (common & ADVERTISE_1000XFULL)
3561 current_duplex = DUPLEX_FULL;
3562 else
3563 current_duplex = DUPLEX_HALF;
3564 }
3565 else
3566 current_link_up = 0;
3567 }
3568 }
3569
3570 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3571 tg3_setup_flow_control(tp, local_adv, remote_adv);
3572
3573 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3574 if (tp->link_config.active_duplex == DUPLEX_HALF)
3575 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3576
3577 tw32_f(MAC_MODE, tp->mac_mode);
3578 udelay(40);
3579
3580 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3581
3582 tp->link_config.active_speed = current_speed;
3583 tp->link_config.active_duplex = current_duplex;
3584
3585 if (current_link_up != netif_carrier_ok(tp->dev)) {
3586 if (current_link_up)
3587 netif_carrier_on(tp->dev);
3588 else {
3589 netif_carrier_off(tp->dev);
3590 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3591 }
3592 tg3_link_report(tp);
3593 }
3594 return err;
3595}
3596
3597static void tg3_serdes_parallel_detect(struct tg3 *tp)
3598{
3599 if (tp->serdes_counter) {
3600 /* Give autoneg time to complete. */
3601 tp->serdes_counter--;
3602 return;
3603 }
3604 if (!netif_carrier_ok(tp->dev) &&
3605 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3606 u32 bmcr;
3607
3608 tg3_readphy(tp, MII_BMCR, &bmcr);
3609 if (bmcr & BMCR_ANENABLE) {
3610 u32 phy1, phy2;
3611
3612 /* Select shadow register 0x1f */
3613 tg3_writephy(tp, 0x1c, 0x7c00);
3614 tg3_readphy(tp, 0x1c, &phy1);
3615
3616 /* Select expansion interrupt status register */
3617 tg3_writephy(tp, 0x17, 0x0f01);
3618 tg3_readphy(tp, 0x15, &phy2);
3619 tg3_readphy(tp, 0x15, &phy2);
3620
3621 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3622 /* We have signal detect and not receiving
3623 * config code words, link is up by parallel
3624 * detection.
3625 */
3626
3627 bmcr &= ~BMCR_ANENABLE;
3628 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3629 tg3_writephy(tp, MII_BMCR, bmcr);
3630 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3631 }
3632 }
3633 }
3634 else if (netif_carrier_ok(tp->dev) &&
3635 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3636 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3637 u32 phy2;
3638
3639 /* Select expansion interrupt status register */
3640 tg3_writephy(tp, 0x17, 0x0f01);
3641 tg3_readphy(tp, 0x15, &phy2);
3642 if (phy2 & 0x20) {
3643 u32 bmcr;
3644
3645 /* Config code words received, turn on autoneg. */
3646 tg3_readphy(tp, MII_BMCR, &bmcr);
3647 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3648
3649 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3650
3651 }
3652 }
3653}
3654
3655static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3656{
3657 int err;
3658
3659 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3660 err = tg3_setup_fiber_phy(tp, force_reset);
3661 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3662 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3663 } else {
3664 err = tg3_setup_copper_phy(tp, force_reset);
3665 }
3666
3667 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3668 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3669 u32 val, scale;
3670
3671 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3672 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3673 scale = 65;
3674 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3675 scale = 6;
3676 else
3677 scale = 12;
3678
3679 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3680 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3681 tw32(GRC_MISC_CFG, val);
3682 }
3683
3684 if (tp->link_config.active_speed == SPEED_1000 &&
3685 tp->link_config.active_duplex == DUPLEX_HALF)
3686 tw32(MAC_TX_LENGTHS,
3687 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3688 (6 << TX_LENGTHS_IPG_SHIFT) |
3689 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3690 else
3691 tw32(MAC_TX_LENGTHS,
3692 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3693 (6 << TX_LENGTHS_IPG_SHIFT) |
3694 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3695
3696 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3697 if (netif_carrier_ok(tp->dev)) {
3698 tw32(HOSTCC_STAT_COAL_TICKS,
3699 tp->coal.stats_block_coalesce_usecs);
3700 } else {
3701 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3702 }
3703 }
3704
3705 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3706 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3707 if (!netif_carrier_ok(tp->dev))
3708 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3709 tp->pwrmgmt_thresh;
3710 else
3711 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3712 tw32(PCIE_PWR_MGMT_THRESH, val);
3713 }
3714
3715 return err;
3716}
3717
3718/* This is called whenever we suspect that the system chipset is re-
3719 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3720 * is bogus tx completions. We try to recover by setting the
3721 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3722 * in the workqueue.
3723 */
3724static void tg3_tx_recover(struct tg3 *tp)
3725{
3726 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3727 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3728
3729 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3730 "mapped I/O cycles to the network device, attempting to "
3731 "recover. Please report the problem to the driver maintainer "
3732 "and include system chipset information.\n", tp->dev->name);
3733
3734 spin_lock(&tp->lock);
3735 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3736 spin_unlock(&tp->lock);
3737}
3738
3739static inline u32 tg3_tx_avail(struct tg3 *tp)
3740{
3741 smp_mb();
3742 return (tp->tx_pending -
3743 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3744}
3745
3746/* Tigon3 never reports partial packet sends. So we do not
3747 * need special logic to handle SKBs that have not had all
3748 * of their frags sent yet, like SunGEM does.
3749 */
3750static void tg3_tx(struct tg3 *tp)
3751{
3752 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3753 u32 sw_idx = tp->tx_cons;
3754
3755 while (sw_idx != hw_idx) {
3756 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3757 struct sk_buff *skb = ri->skb;
3758 int i, tx_bug = 0;
3759
3760 if (unlikely(skb == NULL)) {
3761 tg3_tx_recover(tp);
3762 return;
3763 }
3764
3765 pci_unmap_single(tp->pdev,
3766 pci_unmap_addr(ri, mapping),
3767 skb_headlen(skb),
3768 PCI_DMA_TODEVICE);
3769
3770 ri->skb = NULL;
3771
3772 sw_idx = NEXT_TX(sw_idx);
3773
3774 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3775 ri = &tp->tx_buffers[sw_idx];
3776 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3777 tx_bug = 1;
3778
3779 pci_unmap_page(tp->pdev,
3780 pci_unmap_addr(ri, mapping),
3781 skb_shinfo(skb)->frags[i].size,
3782 PCI_DMA_TODEVICE);
3783
3784 sw_idx = NEXT_TX(sw_idx);
3785 }
3786
3787 dev_kfree_skb(skb);
3788
3789 if (unlikely(tx_bug)) {
3790 tg3_tx_recover(tp);
3791 return;
3792 }
3793 }
3794
3795 tp->tx_cons = sw_idx;
3796
3797 /* Need to make the tx_cons update visible to tg3_start_xmit()
3798 * before checking for netif_queue_stopped(). Without the
3799 * memory barrier, there is a small possibility that tg3_start_xmit()
3800 * will miss it and cause the queue to be stopped forever.
3801 */
3802 smp_mb();
3803
3804 if (unlikely(netif_queue_stopped(tp->dev) &&
3805 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3806 netif_tx_lock(tp->dev);
3807 if (netif_queue_stopped(tp->dev) &&
3808 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3809 netif_wake_queue(tp->dev);
3810 netif_tx_unlock(tp->dev);
3811 }
3812}
3813
3814/* Returns size of skb allocated or < 0 on error.
3815 *
3816 * We only need to fill in the address because the other members
3817 * of the RX descriptor are invariant, see tg3_init_rings.
3818 *
3819 * Note the purposeful assymetry of cpu vs. chip accesses. For
3820 * posting buffers we only dirty the first cache line of the RX
3821 * descriptor (containing the address). Whereas for the RX status
3822 * buffers the cpu only reads the last cacheline of the RX descriptor
3823 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3824 */
3825static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3826 int src_idx, u32 dest_idx_unmasked)
3827{
3828 struct tg3_rx_buffer_desc *desc;
3829 struct ring_info *map, *src_map;
3830 struct sk_buff *skb;
3831 dma_addr_t mapping;
3832 int skb_size, dest_idx;
3833
3834 src_map = NULL;
3835 switch (opaque_key) {
3836 case RXD_OPAQUE_RING_STD:
3837 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3838 desc = &tp->rx_std[dest_idx];
3839 map = &tp->rx_std_buffers[dest_idx];
3840 if (src_idx >= 0)
3841 src_map = &tp->rx_std_buffers[src_idx];
3842 skb_size = tp->rx_pkt_buf_sz;
3843 break;
3844
3845 case RXD_OPAQUE_RING_JUMBO:
3846 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3847 desc = &tp->rx_jumbo[dest_idx];
3848 map = &tp->rx_jumbo_buffers[dest_idx];
3849 if (src_idx >= 0)
3850 src_map = &tp->rx_jumbo_buffers[src_idx];
3851 skb_size = RX_JUMBO_PKT_BUF_SZ;
3852 break;
3853
3854 default:
3855 return -EINVAL;
3856 };
3857
3858 /* Do not overwrite any of the map or rp information
3859 * until we are sure we can commit to a new buffer.
3860 *
3861 * Callers depend upon this behavior and assume that
3862 * we leave everything unchanged if we fail.
3863 */
3864 skb = netdev_alloc_skb(tp->dev, skb_size);
3865 if (skb == NULL)
3866 return -ENOMEM;
3867
3868 skb_reserve(skb, tp->rx_offset);
3869
3870 mapping = pci_map_single(tp->pdev, skb->data,
3871 skb_size - tp->rx_offset,
3872 PCI_DMA_FROMDEVICE);
3873
3874 map->skb = skb;
3875 pci_unmap_addr_set(map, mapping, mapping);
3876
3877 if (src_map != NULL)
3878 src_map->skb = NULL;
3879
3880 desc->addr_hi = ((u64)mapping >> 32);
3881 desc->addr_lo = ((u64)mapping & 0xffffffff);
3882
3883 return skb_size;
3884}
3885
3886/* We only need to move over in the address because the other
3887 * members of the RX descriptor are invariant. See notes above
3888 * tg3_alloc_rx_skb for full details.
3889 */
3890static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3891 int src_idx, u32 dest_idx_unmasked)
3892{
3893 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3894 struct ring_info *src_map, *dest_map;
3895 int dest_idx;
3896
3897 switch (opaque_key) {
3898 case RXD_OPAQUE_RING_STD:
3899 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3900 dest_desc = &tp->rx_std[dest_idx];
3901 dest_map = &tp->rx_std_buffers[dest_idx];
3902 src_desc = &tp->rx_std[src_idx];
3903 src_map = &tp->rx_std_buffers[src_idx];
3904 break;
3905
3906 case RXD_OPAQUE_RING_JUMBO:
3907 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3908 dest_desc = &tp->rx_jumbo[dest_idx];
3909 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3910 src_desc = &tp->rx_jumbo[src_idx];
3911 src_map = &tp->rx_jumbo_buffers[src_idx];
3912 break;
3913
3914 default:
3915 return;
3916 };
3917
3918 dest_map->skb = src_map->skb;
3919 pci_unmap_addr_set(dest_map, mapping,
3920 pci_unmap_addr(src_map, mapping));
3921 dest_desc->addr_hi = src_desc->addr_hi;
3922 dest_desc->addr_lo = src_desc->addr_lo;
3923
3924 src_map->skb = NULL;
3925}
3926
3927#if TG3_VLAN_TAG_USED
3928static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3929{
3930 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3931}
3932#endif
3933
3934/* The RX ring scheme is composed of multiple rings which post fresh
3935 * buffers to the chip, and one special ring the chip uses to report
3936 * status back to the host.
3937 *
3938 * The special ring reports the status of received packets to the
3939 * host. The chip does not write into the original descriptor the
3940 * RX buffer was obtained from. The chip simply takes the original
3941 * descriptor as provided by the host, updates the status and length
3942 * field, then writes this into the next status ring entry.
3943 *
3944 * Each ring the host uses to post buffers to the chip is described
3945 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3946 * it is first placed into the on-chip ram. When the packet's length
3947 * is known, it walks down the TG3_BDINFO entries to select the ring.
3948 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3949 * which is within the range of the new packet's length is chosen.
3950 *
3951 * The "separate ring for rx status" scheme may sound queer, but it makes
3952 * sense from a cache coherency perspective. If only the host writes
3953 * to the buffer post rings, and only the chip writes to the rx status
3954 * rings, then cache lines never move beyond shared-modified state.
3955 * If both the host and chip were to write into the same ring, cache line
3956 * eviction could occur since both entities want it in an exclusive state.
3957 */
3958static int tg3_rx(struct tg3 *tp, int budget)
3959{
3960 u32 work_mask, rx_std_posted = 0;
3961 u32 sw_idx = tp->rx_rcb_ptr;
3962 u16 hw_idx;
3963 int received;
3964
3965 hw_idx = tp->hw_status->idx[0].rx_producer;
3966 /*
3967 * We need to order the read of hw_idx and the read of
3968 * the opaque cookie.
3969 */
3970 rmb();
3971 work_mask = 0;
3972 received = 0;
3973 while (sw_idx != hw_idx && budget > 0) {
3974 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3975 unsigned int len;
3976 struct sk_buff *skb;
3977 dma_addr_t dma_addr;
3978 u32 opaque_key, desc_idx, *post_ptr;
3979
3980 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3981 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3982 if (opaque_key == RXD_OPAQUE_RING_STD) {
3983 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3984 mapping);
3985 skb = tp->rx_std_buffers[desc_idx].skb;
3986 post_ptr = &tp->rx_std_ptr;
3987 rx_std_posted++;
3988 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3989 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3990 mapping);
3991 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3992 post_ptr = &tp->rx_jumbo_ptr;
3993 }
3994 else {
3995 goto next_pkt_nopost;
3996 }
3997
3998 work_mask |= opaque_key;
3999
4000 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4001 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4002 drop_it:
4003 tg3_recycle_rx(tp, opaque_key,
4004 desc_idx, *post_ptr);
4005 drop_it_no_recycle:
4006 /* Other statistics kept track of by card. */
4007 tp->net_stats.rx_dropped++;
4008 goto next_pkt;
4009 }
4010
4011 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
4012
4013 if (len > RX_COPY_THRESHOLD
4014 && tp->rx_offset == 2
4015 /* rx_offset != 2 iff this is a 5701 card running
4016 * in PCI-X mode [see tg3_get_invariants()] */
4017 ) {
4018 int skb_size;
4019
4020 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4021 desc_idx, *post_ptr);
4022 if (skb_size < 0)
4023 goto drop_it;
4024
4025 pci_unmap_single(tp->pdev, dma_addr,
4026 skb_size - tp->rx_offset,
4027 PCI_DMA_FROMDEVICE);
4028
4029 skb_put(skb, len);
4030 } else {
4031 struct sk_buff *copy_skb;
4032
4033 tg3_recycle_rx(tp, opaque_key,
4034 desc_idx, *post_ptr);
4035
4036 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
4037 if (copy_skb == NULL)
4038 goto drop_it_no_recycle;
4039
4040 skb_reserve(copy_skb, 2);
4041 skb_put(copy_skb, len);
4042 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4043 skb_copy_from_linear_data(skb, copy_skb->data, len);
4044 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4045
4046 /* We'll reuse the original ring buffer. */
4047 skb = copy_skb;
4048 }
4049
4050 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4051 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4052 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4053 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4054 skb->ip_summed = CHECKSUM_UNNECESSARY;
4055 else
4056 skb->ip_summed = CHECKSUM_NONE;
4057
4058 skb->protocol = eth_type_trans(skb, tp->dev);
4059#if TG3_VLAN_TAG_USED
4060 if (tp->vlgrp != NULL &&
4061 desc->type_flags & RXD_FLAG_VLAN) {
4062 tg3_vlan_rx(tp, skb,
4063 desc->err_vlan & RXD_VLAN_MASK);
4064 } else
4065#endif
4066 netif_receive_skb(skb);
4067
4068 tp->dev->last_rx = jiffies;
4069 received++;
4070 budget--;
4071
4072next_pkt:
4073 (*post_ptr)++;
4074
4075 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4076 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4077
4078 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4079 TG3_64BIT_REG_LOW, idx);
4080 work_mask &= ~RXD_OPAQUE_RING_STD;
4081 rx_std_posted = 0;
4082 }
4083next_pkt_nopost:
4084 sw_idx++;
4085 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4086
4087 /* Refresh hw_idx to see if there is new work */
4088 if (sw_idx == hw_idx) {
4089 hw_idx = tp->hw_status->idx[0].rx_producer;
4090 rmb();
4091 }
4092 }
4093
4094 /* ACK the status ring. */
4095 tp->rx_rcb_ptr = sw_idx;
4096 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4097
4098 /* Refill RX ring(s). */
4099 if (work_mask & RXD_OPAQUE_RING_STD) {
4100 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4101 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4102 sw_idx);
4103 }
4104 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4105 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4106 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4107 sw_idx);
4108 }
4109 mmiowb();
4110
4111 return received;
4112}
4113
4114static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4115{
4116 struct tg3_hw_status *sblk = tp->hw_status;
4117
4118 /* handle link change and other phy events */
4119 if (!(tp->tg3_flags &
4120 (TG3_FLAG_USE_LINKCHG_REG |
4121 TG3_FLAG_POLL_SERDES))) {
4122 if (sblk->status & SD_STATUS_LINK_CHG) {
4123 sblk->status = SD_STATUS_UPDATED |
4124 (sblk->status & ~SD_STATUS_LINK_CHG);
4125 spin_lock(&tp->lock);
4126 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4127 tw32_f(MAC_STATUS,
4128 (MAC_STATUS_SYNC_CHANGED |
4129 MAC_STATUS_CFG_CHANGED |
4130 MAC_STATUS_MI_COMPLETION |
4131 MAC_STATUS_LNKSTATE_CHANGED));
4132 udelay(40);
4133 } else
4134 tg3_setup_phy(tp, 0);
4135 spin_unlock(&tp->lock);
4136 }
4137 }
4138
4139 /* run TX completion thread */
4140 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4141 tg3_tx(tp);
4142 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4143 return work_done;
4144 }
4145
4146 /* run RX thread, within the bounds set by NAPI.
4147 * All RX "locking" is done by ensuring outside
4148 * code synchronizes with tg3->napi.poll()
4149 */
4150 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4151 work_done += tg3_rx(tp, budget - work_done);
4152
4153 return work_done;
4154}
4155
4156static int tg3_poll(struct napi_struct *napi, int budget)
4157{
4158 struct tg3 *tp = container_of(napi, struct tg3, napi);
4159 int work_done = 0;
4160 struct tg3_hw_status *sblk = tp->hw_status;
4161
4162 while (1) {
4163 work_done = tg3_poll_work(tp, work_done, budget);
4164
4165 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4166 goto tx_recovery;
4167
4168 if (unlikely(work_done >= budget))
4169 break;
4170
4171 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4172 /* tp->last_tag is used in tg3_restart_ints() below
4173 * to tell the hw how much work has been processed,
4174 * so we must read it before checking for more work.
4175 */
4176 tp->last_tag = sblk->status_tag;
4177 rmb();
4178 } else
4179 sblk->status &= ~SD_STATUS_UPDATED;
4180
4181 if (likely(!tg3_has_work(tp))) {
4182 netif_rx_complete(tp->dev, napi);
4183 tg3_restart_ints(tp);
4184 break;
4185 }
4186 }
4187
4188 return work_done;
4189
4190tx_recovery:
4191 /* work_done is guaranteed to be less than budget. */
4192 netif_rx_complete(tp->dev, napi);
4193 schedule_work(&tp->reset_task);
4194 return work_done;
4195}
4196
4197static void tg3_irq_quiesce(struct tg3 *tp)
4198{
4199 BUG_ON(tp->irq_sync);
4200
4201 tp->irq_sync = 1;
4202 smp_mb();
4203
4204 synchronize_irq(tp->pdev->irq);
4205}
4206
4207static inline int tg3_irq_sync(struct tg3 *tp)
4208{
4209 return tp->irq_sync;
4210}
4211
4212/* Fully shutdown all tg3 driver activity elsewhere in the system.
4213 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4214 * with as well. Most of the time, this is not necessary except when
4215 * shutting down the device.
4216 */
4217static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4218{
4219 spin_lock_bh(&tp->lock);
4220 if (irq_sync)
4221 tg3_irq_quiesce(tp);
4222}
4223
4224static inline void tg3_full_unlock(struct tg3 *tp)
4225{
4226 spin_unlock_bh(&tp->lock);
4227}
4228
4229/* One-shot MSI handler - Chip automatically disables interrupt
4230 * after sending MSI so driver doesn't have to do it.
4231 */
4232static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4233{
4234 struct net_device *dev = dev_id;
4235 struct tg3 *tp = netdev_priv(dev);
4236
4237 prefetch(tp->hw_status);
4238 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4239
4240 if (likely(!tg3_irq_sync(tp)))
4241 netif_rx_schedule(dev, &tp->napi);
4242
4243 return IRQ_HANDLED;
4244}
4245
4246/* MSI ISR - No need to check for interrupt sharing and no need to
4247 * flush status block and interrupt mailbox. PCI ordering rules
4248 * guarantee that MSI will arrive after the status block.
4249 */
4250static irqreturn_t tg3_msi(int irq, void *dev_id)
4251{
4252 struct net_device *dev = dev_id;
4253 struct tg3 *tp = netdev_priv(dev);
4254
4255 prefetch(tp->hw_status);
4256 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4257 /*
4258 * Writing any value to intr-mbox-0 clears PCI INTA# and
4259 * chip-internal interrupt pending events.
4260 * Writing non-zero to intr-mbox-0 additional tells the
4261 * NIC to stop sending us irqs, engaging "in-intr-handler"
4262 * event coalescing.
4263 */
4264 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4265 if (likely(!tg3_irq_sync(tp)))
4266 netif_rx_schedule(dev, &tp->napi);
4267
4268 return IRQ_RETVAL(1);
4269}
4270
4271static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4272{
4273 struct net_device *dev = dev_id;
4274 struct tg3 *tp = netdev_priv(dev);
4275 struct tg3_hw_status *sblk = tp->hw_status;
4276 unsigned int handled = 1;
4277
4278 /* In INTx mode, it is possible for the interrupt to arrive at
4279 * the CPU before the status block posted prior to the interrupt.
4280 * Reading the PCI State register will confirm whether the
4281 * interrupt is ours and will flush the status block.
4282 */
4283 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4284 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4285 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4286 handled = 0;
4287 goto out;
4288 }
4289 }
4290
4291 /*
4292 * Writing any value to intr-mbox-0 clears PCI INTA# and
4293 * chip-internal interrupt pending events.
4294 * Writing non-zero to intr-mbox-0 additional tells the
4295 * NIC to stop sending us irqs, engaging "in-intr-handler"
4296 * event coalescing.
4297 *
4298 * Flush the mailbox to de-assert the IRQ immediately to prevent
4299 * spurious interrupts. The flush impacts performance but
4300 * excessive spurious interrupts can be worse in some cases.
4301 */
4302 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4303 if (tg3_irq_sync(tp))
4304 goto out;
4305 sblk->status &= ~SD_STATUS_UPDATED;
4306 if (likely(tg3_has_work(tp))) {
4307 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4308 netif_rx_schedule(dev, &tp->napi);
4309 } else {
4310 /* No work, shared interrupt perhaps? re-enable
4311 * interrupts, and flush that PCI write
4312 */
4313 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4314 0x00000000);
4315 }
4316out:
4317 return IRQ_RETVAL(handled);
4318}
4319
4320static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4321{
4322 struct net_device *dev = dev_id;
4323 struct tg3 *tp = netdev_priv(dev);
4324 struct tg3_hw_status *sblk = tp->hw_status;
4325 unsigned int handled = 1;
4326
4327 /* In INTx mode, it is possible for the interrupt to arrive at
4328 * the CPU before the status block posted prior to the interrupt.
4329 * Reading the PCI State register will confirm whether the
4330 * interrupt is ours and will flush the status block.
4331 */
4332 if (unlikely(sblk->status_tag == tp->last_tag)) {
4333 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4334 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4335 handled = 0;
4336 goto out;
4337 }
4338 }
4339
4340 /*
4341 * writing any value to intr-mbox-0 clears PCI INTA# and
4342 * chip-internal interrupt pending events.
4343 * writing non-zero to intr-mbox-0 additional tells the
4344 * NIC to stop sending us irqs, engaging "in-intr-handler"
4345 * event coalescing.
4346 *
4347 * Flush the mailbox to de-assert the IRQ immediately to prevent
4348 * spurious interrupts. The flush impacts performance but
4349 * excessive spurious interrupts can be worse in some cases.
4350 */
4351 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4352 if (tg3_irq_sync(tp))
4353 goto out;
4354 if (netif_rx_schedule_prep(dev, &tp->napi)) {
4355 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4356 /* Update last_tag to mark that this status has been
4357 * seen. Because interrupt may be shared, we may be
4358 * racing with tg3_poll(), so only update last_tag
4359 * if tg3_poll() is not scheduled.
4360 */
4361 tp->last_tag = sblk->status_tag;
4362 __netif_rx_schedule(dev, &tp->napi);
4363 }
4364out:
4365 return IRQ_RETVAL(handled);
4366}
4367
4368/* ISR for interrupt test */
4369static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4370{
4371 struct net_device *dev = dev_id;
4372 struct tg3 *tp = netdev_priv(dev);
4373 struct tg3_hw_status *sblk = tp->hw_status;
4374
4375 if ((sblk->status & SD_STATUS_UPDATED) ||
4376 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4377 tg3_disable_ints(tp);
4378 return IRQ_RETVAL(1);
4379 }
4380 return IRQ_RETVAL(0);
4381}
4382
4383static int tg3_init_hw(struct tg3 *, int);
4384static int tg3_halt(struct tg3 *, int, int);
4385
4386/* Restart hardware after configuration changes, self-test, etc.
4387 * Invoked with tp->lock held.
4388 */
4389static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4390 __releases(tp->lock)
4391 __acquires(tp->lock)
4392{
4393 int err;
4394
4395 err = tg3_init_hw(tp, reset_phy);
4396 if (err) {
4397 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4398 "aborting.\n", tp->dev->name);
4399 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4400 tg3_full_unlock(tp);
4401 del_timer_sync(&tp->timer);
4402 tp->irq_sync = 0;
4403 napi_enable(&tp->napi);
4404 dev_close(tp->dev);
4405 tg3_full_lock(tp, 0);
4406 }
4407 return err;
4408}
4409
4410#ifdef CONFIG_NET_POLL_CONTROLLER
4411static void tg3_poll_controller(struct net_device *dev)
4412{
4413 struct tg3 *tp = netdev_priv(dev);
4414
4415 tg3_interrupt(tp->pdev->irq, dev);
4416}
4417#endif
4418
4419static void tg3_reset_task(struct work_struct *work)
4420{
4421 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4422 int err;
4423 unsigned int restart_timer;
4424
4425 tg3_full_lock(tp, 0);
4426
4427 if (!netif_running(tp->dev)) {
4428 tg3_full_unlock(tp);
4429 return;
4430 }
4431
4432 tg3_full_unlock(tp);
4433
4434 tg3_phy_stop(tp);
4435
4436 tg3_netif_stop(tp);
4437
4438 tg3_full_lock(tp, 1);
4439
4440 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4441 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4442
4443 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4444 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4445 tp->write32_rx_mbox = tg3_write_flush_reg32;
4446 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4447 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4448 }
4449
4450 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4451 err = tg3_init_hw(tp, 1);
4452 if (err)
4453 goto out;
4454
4455 tg3_netif_start(tp);
4456
4457 if (restart_timer)
4458 mod_timer(&tp->timer, jiffies + 1);
4459
4460out:
4461 tg3_full_unlock(tp);
4462
4463 if (!err)
4464 tg3_phy_start(tp);
4465}
4466
4467static void tg3_dump_short_state(struct tg3 *tp)
4468{
4469 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4470 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4471 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4472 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4473}
4474
4475static void tg3_tx_timeout(struct net_device *dev)
4476{
4477 struct tg3 *tp = netdev_priv(dev);
4478
4479 if (netif_msg_tx_err(tp)) {
4480 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4481 dev->name);
4482 tg3_dump_short_state(tp);
4483 }
4484
4485 schedule_work(&tp->reset_task);
4486}
4487
4488/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4489static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4490{
4491 u32 base = (u32) mapping & 0xffffffff;
4492
4493 return ((base > 0xffffdcc0) &&
4494 (base + len + 8 < base));
4495}
4496
4497/* Test for DMA addresses > 40-bit */
4498static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4499 int len)
4500{
4501#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4502 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4503 return (((u64) mapping + len) > DMA_40BIT_MASK);
4504 return 0;
4505#else
4506 return 0;
4507#endif
4508}
4509
4510static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4511
4512/* Workaround 4GB and 40-bit hardware DMA bugs. */
4513static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4514 u32 last_plus_one, u32 *start,
4515 u32 base_flags, u32 mss)
4516{
4517 struct sk_buff *new_skb;
4518 dma_addr_t new_addr = 0;
4519 u32 entry = *start;
4520 int i, ret = 0;
4521
4522 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4523 new_skb = skb_copy(skb, GFP_ATOMIC);
4524 else {
4525 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4526
4527 new_skb = skb_copy_expand(skb,
4528 skb_headroom(skb) + more_headroom,
4529 skb_tailroom(skb), GFP_ATOMIC);
4530 }
4531
4532 if (!new_skb) {
4533 ret = -1;
4534 } else {
4535 /* New SKB is guaranteed to be linear. */
4536 entry = *start;
4537 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4538 PCI_DMA_TODEVICE);
4539 /* Make sure new skb does not cross any 4G boundaries.
4540 * Drop the packet if it does.
4541 */
4542 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4543 ret = -1;
4544 dev_kfree_skb(new_skb);
4545 new_skb = NULL;
4546 } else {
4547 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4548 base_flags, 1 | (mss << 1));
4549 *start = NEXT_TX(entry);
4550 }
4551 }
4552
4553 /* Now clean up the sw ring entries. */
4554 i = 0;
4555 while (entry != last_plus_one) {
4556 int len;
4557
4558 if (i == 0)
4559 len = skb_headlen(skb);
4560 else
4561 len = skb_shinfo(skb)->frags[i-1].size;
4562 pci_unmap_single(tp->pdev,
4563 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4564 len, PCI_DMA_TODEVICE);
4565 if (i == 0) {
4566 tp->tx_buffers[entry].skb = new_skb;
4567 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4568 } else {
4569 tp->tx_buffers[entry].skb = NULL;
4570 }
4571 entry = NEXT_TX(entry);
4572 i++;
4573 }
4574
4575 dev_kfree_skb(skb);
4576
4577 return ret;
4578}
4579
4580static void tg3_set_txd(struct tg3 *tp, int entry,
4581 dma_addr_t mapping, int len, u32 flags,
4582 u32 mss_and_is_end)
4583{
4584 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4585 int is_end = (mss_and_is_end & 0x1);
4586 u32 mss = (mss_and_is_end >> 1);
4587 u32 vlan_tag = 0;
4588
4589 if (is_end)
4590 flags |= TXD_FLAG_END;
4591 if (flags & TXD_FLAG_VLAN) {
4592 vlan_tag = flags >> 16;
4593 flags &= 0xffff;
4594 }
4595 vlan_tag |= (mss << TXD_MSS_SHIFT);
4596
4597 txd->addr_hi = ((u64) mapping >> 32);
4598 txd->addr_lo = ((u64) mapping & 0xffffffff);
4599 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4600 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4601}
4602
4603/* hard_start_xmit for devices that don't have any bugs and
4604 * support TG3_FLG2_HW_TSO_2 only.
4605 */
4606static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4607{
4608 struct tg3 *tp = netdev_priv(dev);
4609 dma_addr_t mapping;
4610 u32 len, entry, base_flags, mss;
4611
4612 len = skb_headlen(skb);
4613
4614 /* We are running in BH disabled context with netif_tx_lock
4615 * and TX reclaim runs via tp->napi.poll inside of a software
4616 * interrupt. Furthermore, IRQ processing runs lockless so we have
4617 * no IRQ context deadlocks to worry about either. Rejoice!
4618 */
4619 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4620 if (!netif_queue_stopped(dev)) {
4621 netif_stop_queue(dev);
4622
4623 /* This is a hard error, log it. */
4624 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4625 "queue awake!\n", dev->name);
4626 }
4627 return NETDEV_TX_BUSY;
4628 }
4629
4630 entry = tp->tx_prod;
4631 base_flags = 0;
4632 mss = 0;
4633 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4634 int tcp_opt_len, ip_tcp_len;
4635
4636 if (skb_header_cloned(skb) &&
4637 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4638 dev_kfree_skb(skb);
4639 goto out_unlock;
4640 }
4641
4642 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4643 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4644 else {
4645 struct iphdr *iph = ip_hdr(skb);
4646
4647 tcp_opt_len = tcp_optlen(skb);
4648 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4649
4650 iph->check = 0;
4651 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4652 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4653 }
4654
4655 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4656 TXD_FLAG_CPU_POST_DMA);
4657
4658 tcp_hdr(skb)->check = 0;
4659
4660 }
4661 else if (skb->ip_summed == CHECKSUM_PARTIAL)
4662 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4663#if TG3_VLAN_TAG_USED
4664 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4665 base_flags |= (TXD_FLAG_VLAN |
4666 (vlan_tx_tag_get(skb) << 16));
4667#endif
4668
4669 /* Queue skb data, a.k.a. the main skb fragment. */
4670 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4671
4672 tp->tx_buffers[entry].skb = skb;
4673 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4674
4675 tg3_set_txd(tp, entry, mapping, len, base_flags,
4676 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4677
4678 entry = NEXT_TX(entry);
4679
4680 /* Now loop through additional data fragments, and queue them. */
4681 if (skb_shinfo(skb)->nr_frags > 0) {
4682 unsigned int i, last;
4683
4684 last = skb_shinfo(skb)->nr_frags - 1;
4685 for (i = 0; i <= last; i++) {
4686 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4687
4688 len = frag->size;
4689 mapping = pci_map_page(tp->pdev,
4690 frag->page,
4691 frag->page_offset,
4692 len, PCI_DMA_TODEVICE);
4693
4694 tp->tx_buffers[entry].skb = NULL;
4695 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4696
4697 tg3_set_txd(tp, entry, mapping, len,
4698 base_flags, (i == last) | (mss << 1));
4699
4700 entry = NEXT_TX(entry);
4701 }
4702 }
4703
4704 /* Packets are ready, update Tx producer idx local and on card. */
4705 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4706
4707 tp->tx_prod = entry;
4708 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4709 netif_stop_queue(dev);
4710 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4711 netif_wake_queue(tp->dev);
4712 }
4713
4714out_unlock:
4715 mmiowb();
4716
4717 dev->trans_start = jiffies;
4718
4719 return NETDEV_TX_OK;
4720}
4721
4722static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4723
4724/* Use GSO to workaround a rare TSO bug that may be triggered when the
4725 * TSO header is greater than 80 bytes.
4726 */
4727static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4728{
4729 struct sk_buff *segs, *nskb;
4730
4731 /* Estimate the number of fragments in the worst case */
4732 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4733 netif_stop_queue(tp->dev);
4734 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4735 return NETDEV_TX_BUSY;
4736
4737 netif_wake_queue(tp->dev);
4738 }
4739
4740 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4741 if (IS_ERR(segs))
4742 goto tg3_tso_bug_end;
4743
4744 do {
4745 nskb = segs;
4746 segs = segs->next;
4747 nskb->next = NULL;
4748 tg3_start_xmit_dma_bug(nskb, tp->dev);
4749 } while (segs);
4750
4751tg3_tso_bug_end:
4752 dev_kfree_skb(skb);
4753
4754 return NETDEV_TX_OK;
4755}
4756
4757/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4758 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4759 */
4760static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4761{
4762 struct tg3 *tp = netdev_priv(dev);
4763 dma_addr_t mapping;
4764 u32 len, entry, base_flags, mss;
4765 int would_hit_hwbug;
4766
4767 len = skb_headlen(skb);
4768
4769 /* We are running in BH disabled context with netif_tx_lock
4770 * and TX reclaim runs via tp->napi.poll inside of a software
4771 * interrupt. Furthermore, IRQ processing runs lockless so we have
4772 * no IRQ context deadlocks to worry about either. Rejoice!
4773 */
4774 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4775 if (!netif_queue_stopped(dev)) {
4776 netif_stop_queue(dev);
4777
4778 /* This is a hard error, log it. */
4779 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4780 "queue awake!\n", dev->name);
4781 }
4782 return NETDEV_TX_BUSY;
4783 }
4784
4785 entry = tp->tx_prod;
4786 base_flags = 0;
4787 if (skb->ip_summed == CHECKSUM_PARTIAL)
4788 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4789 mss = 0;
4790 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4791 struct iphdr *iph;
4792 int tcp_opt_len, ip_tcp_len, hdr_len;
4793
4794 if (skb_header_cloned(skb) &&
4795 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4796 dev_kfree_skb(skb);
4797 goto out_unlock;
4798 }
4799
4800 tcp_opt_len = tcp_optlen(skb);
4801 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4802
4803 hdr_len = ip_tcp_len + tcp_opt_len;
4804 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4805 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4806 return (tg3_tso_bug(tp, skb));
4807
4808 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4809 TXD_FLAG_CPU_POST_DMA);
4810
4811 iph = ip_hdr(skb);
4812 iph->check = 0;
4813 iph->tot_len = htons(mss + hdr_len);
4814 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4815 tcp_hdr(skb)->check = 0;
4816 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4817 } else
4818 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4819 iph->daddr, 0,
4820 IPPROTO_TCP,
4821 0);
4822
4823 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4824 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4825 if (tcp_opt_len || iph->ihl > 5) {
4826 int tsflags;
4827
4828 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4829 mss |= (tsflags << 11);
4830 }
4831 } else {
4832 if (tcp_opt_len || iph->ihl > 5) {
4833 int tsflags;
4834
4835 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4836 base_flags |= tsflags << 12;
4837 }
4838 }
4839 }
4840#if TG3_VLAN_TAG_USED
4841 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4842 base_flags |= (TXD_FLAG_VLAN |
4843 (vlan_tx_tag_get(skb) << 16));
4844#endif
4845
4846 /* Queue skb data, a.k.a. the main skb fragment. */
4847 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4848
4849 tp->tx_buffers[entry].skb = skb;
4850 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4851
4852 would_hit_hwbug = 0;
4853
4854 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4855 would_hit_hwbug = 1;
4856 else if (tg3_4g_overflow_test(mapping, len))
4857 would_hit_hwbug = 1;
4858
4859 tg3_set_txd(tp, entry, mapping, len, base_flags,
4860 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4861
4862 entry = NEXT_TX(entry);
4863
4864 /* Now loop through additional data fragments, and queue them. */
4865 if (skb_shinfo(skb)->nr_frags > 0) {
4866 unsigned int i, last;
4867
4868 last = skb_shinfo(skb)->nr_frags - 1;
4869 for (i = 0; i <= last; i++) {
4870 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4871
4872 len = frag->size;
4873 mapping = pci_map_page(tp->pdev,
4874 frag->page,
4875 frag->page_offset,
4876 len, PCI_DMA_TODEVICE);
4877
4878 tp->tx_buffers[entry].skb = NULL;
4879 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4880
4881 if (tg3_4g_overflow_test(mapping, len))
4882 would_hit_hwbug = 1;
4883
4884 if (tg3_40bit_overflow_test(tp, mapping, len))
4885 would_hit_hwbug = 1;
4886
4887 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4888 tg3_set_txd(tp, entry, mapping, len,
4889 base_flags, (i == last)|(mss << 1));
4890 else
4891 tg3_set_txd(tp, entry, mapping, len,
4892 base_flags, (i == last));
4893
4894 entry = NEXT_TX(entry);
4895 }
4896 }
4897
4898 if (would_hit_hwbug) {
4899 u32 last_plus_one = entry;
4900 u32 start;
4901
4902 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4903 start &= (TG3_TX_RING_SIZE - 1);
4904
4905 /* If the workaround fails due to memory/mapping
4906 * failure, silently drop this packet.
4907 */
4908 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4909 &start, base_flags, mss))
4910 goto out_unlock;
4911
4912 entry = start;
4913 }
4914
4915 /* Packets are ready, update Tx producer idx local and on card. */
4916 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4917
4918 tp->tx_prod = entry;
4919 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4920 netif_stop_queue(dev);
4921 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4922 netif_wake_queue(tp->dev);
4923 }
4924
4925out_unlock:
4926 mmiowb();
4927
4928 dev->trans_start = jiffies;
4929
4930 return NETDEV_TX_OK;
4931}
4932
4933static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4934 int new_mtu)
4935{
4936 dev->mtu = new_mtu;
4937
4938 if (new_mtu > ETH_DATA_LEN) {
4939 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4940 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4941 ethtool_op_set_tso(dev, 0);
4942 }
4943 else
4944 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4945 } else {
4946 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4947 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4948 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4949 }
4950}
4951
4952static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4953{
4954 struct tg3 *tp = netdev_priv(dev);
4955 int err;
4956
4957 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4958 return -EINVAL;
4959
4960 if (!netif_running(dev)) {
4961 /* We'll just catch it later when the
4962 * device is up'd.
4963 */
4964 tg3_set_mtu(dev, tp, new_mtu);
4965 return 0;
4966 }
4967
4968 tg3_phy_stop(tp);
4969
4970 tg3_netif_stop(tp);
4971
4972 tg3_full_lock(tp, 1);
4973
4974 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4975
4976 tg3_set_mtu(dev, tp, new_mtu);
4977
4978 err = tg3_restart_hw(tp, 0);
4979
4980 if (!err)
4981 tg3_netif_start(tp);
4982
4983 tg3_full_unlock(tp);
4984
4985 if (!err)
4986 tg3_phy_start(tp);
4987
4988 return err;
4989}
4990
4991/* Free up pending packets in all rx/tx rings.
4992 *
4993 * The chip has been shut down and the driver detached from
4994 * the networking, so no interrupts or new tx packets will
4995 * end up in the driver. tp->{tx,}lock is not held and we are not
4996 * in an interrupt context and thus may sleep.
4997 */
4998static void tg3_free_rings(struct tg3 *tp)
4999{
5000 struct ring_info *rxp;
5001 int i;
5002
5003 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5004 rxp = &tp->rx_std_buffers[i];
5005
5006 if (rxp->skb == NULL)
5007 continue;
5008 pci_unmap_single(tp->pdev,
5009 pci_unmap_addr(rxp, mapping),
5010 tp->rx_pkt_buf_sz - tp->rx_offset,
5011 PCI_DMA_FROMDEVICE);
5012 dev_kfree_skb_any(rxp->skb);
5013 rxp->skb = NULL;
5014 }
5015
5016 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5017 rxp = &tp->rx_jumbo_buffers[i];
5018
5019 if (rxp->skb == NULL)
5020 continue;
5021 pci_unmap_single(tp->pdev,
5022 pci_unmap_addr(rxp, mapping),
5023 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5024 PCI_DMA_FROMDEVICE);
5025 dev_kfree_skb_any(rxp->skb);
5026 rxp->skb = NULL;
5027 }
5028
5029 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5030 struct tx_ring_info *txp;
5031 struct sk_buff *skb;
5032 int j;
5033
5034 txp = &tp->tx_buffers[i];
5035 skb = txp->skb;
5036
5037 if (skb == NULL) {
5038 i++;
5039 continue;
5040 }
5041
5042 pci_unmap_single(tp->pdev,
5043 pci_unmap_addr(txp, mapping),
5044 skb_headlen(skb),
5045 PCI_DMA_TODEVICE);
5046 txp->skb = NULL;
5047
5048 i++;
5049
5050 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
5051 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
5052 pci_unmap_page(tp->pdev,
5053 pci_unmap_addr(txp, mapping),
5054 skb_shinfo(skb)->frags[j].size,
5055 PCI_DMA_TODEVICE);
5056 i++;
5057 }
5058
5059 dev_kfree_skb_any(skb);
5060 }
5061}
5062
5063/* Initialize tx/rx rings for packet processing.
5064 *
5065 * The chip has been shut down and the driver detached from
5066 * the networking, so no interrupts or new tx packets will
5067 * end up in the driver. tp->{tx,}lock are held and thus
5068 * we may not sleep.
5069 */
5070static int tg3_init_rings(struct tg3 *tp)
5071{
5072 u32 i;
5073
5074 /* Free up all the SKBs. */
5075 tg3_free_rings(tp);
5076
5077 /* Zero out all descriptors. */
5078 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5079 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5080 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5081 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5082
5083 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5084 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5085 (tp->dev->mtu > ETH_DATA_LEN))
5086 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5087
5088 /* Initialize invariants of the rings, we only set this
5089 * stuff once. This works because the card does not
5090 * write into the rx buffer posting rings.
5091 */
5092 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5093 struct tg3_rx_buffer_desc *rxd;
5094
5095 rxd = &tp->rx_std[i];
5096 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5097 << RXD_LEN_SHIFT;
5098 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5099 rxd->opaque = (RXD_OPAQUE_RING_STD |
5100 (i << RXD_OPAQUE_INDEX_SHIFT));
5101 }
5102
5103 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5104 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5105 struct tg3_rx_buffer_desc *rxd;
5106
5107 rxd = &tp->rx_jumbo[i];
5108 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5109 << RXD_LEN_SHIFT;
5110 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5111 RXD_FLAG_JUMBO;
5112 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5113 (i << RXD_OPAQUE_INDEX_SHIFT));
5114 }
5115 }
5116
5117 /* Now allocate fresh SKBs for each rx ring. */
5118 for (i = 0; i < tp->rx_pending; i++) {
5119 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5120 printk(KERN_WARNING PFX
5121 "%s: Using a smaller RX standard ring, "
5122 "only %d out of %d buffers were allocated "
5123 "successfully.\n",
5124 tp->dev->name, i, tp->rx_pending);
5125 if (i == 0)
5126 return -ENOMEM;
5127 tp->rx_pending = i;
5128 break;
5129 }
5130 }
5131
5132 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5133 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5134 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5135 -1, i) < 0) {
5136 printk(KERN_WARNING PFX
5137 "%s: Using a smaller RX jumbo ring, "
5138 "only %d out of %d buffers were "
5139 "allocated successfully.\n",
5140 tp->dev->name, i, tp->rx_jumbo_pending);
5141 if (i == 0) {
5142 tg3_free_rings(tp);
5143 return -ENOMEM;
5144 }
5145 tp->rx_jumbo_pending = i;
5146 break;
5147 }
5148 }
5149 }
5150 return 0;
5151}
5152
5153/*
5154 * Must not be invoked with interrupt sources disabled and
5155 * the hardware shutdown down.
5156 */
5157static void tg3_free_consistent(struct tg3 *tp)
5158{
5159 kfree(tp->rx_std_buffers);
5160 tp->rx_std_buffers = NULL;
5161 if (tp->rx_std) {
5162 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5163 tp->rx_std, tp->rx_std_mapping);
5164 tp->rx_std = NULL;
5165 }
5166 if (tp->rx_jumbo) {
5167 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5168 tp->rx_jumbo, tp->rx_jumbo_mapping);
5169 tp->rx_jumbo = NULL;
5170 }
5171 if (tp->rx_rcb) {
5172 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5173 tp->rx_rcb, tp->rx_rcb_mapping);
5174 tp->rx_rcb = NULL;
5175 }
5176 if (tp->tx_ring) {
5177 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5178 tp->tx_ring, tp->tx_desc_mapping);
5179 tp->tx_ring = NULL;
5180 }
5181 if (tp->hw_status) {
5182 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5183 tp->hw_status, tp->status_mapping);
5184 tp->hw_status = NULL;
5185 }
5186 if (tp->hw_stats) {
5187 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5188 tp->hw_stats, tp->stats_mapping);
5189 tp->hw_stats = NULL;
5190 }
5191}
5192
5193/*
5194 * Must not be invoked with interrupt sources disabled and
5195 * the hardware shutdown down. Can sleep.
5196 */
5197static int tg3_alloc_consistent(struct tg3 *tp)
5198{
5199 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5200 (TG3_RX_RING_SIZE +
5201 TG3_RX_JUMBO_RING_SIZE)) +
5202 (sizeof(struct tx_ring_info) *
5203 TG3_TX_RING_SIZE),
5204 GFP_KERNEL);
5205 if (!tp->rx_std_buffers)
5206 return -ENOMEM;
5207
5208 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5209 tp->tx_buffers = (struct tx_ring_info *)
5210 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5211
5212 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5213 &tp->rx_std_mapping);
5214 if (!tp->rx_std)
5215 goto err_out;
5216
5217 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5218 &tp->rx_jumbo_mapping);
5219
5220 if (!tp->rx_jumbo)
5221 goto err_out;
5222
5223 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5224 &tp->rx_rcb_mapping);
5225 if (!tp->rx_rcb)
5226 goto err_out;
5227
5228 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5229 &tp->tx_desc_mapping);
5230 if (!tp->tx_ring)
5231 goto err_out;
5232
5233 tp->hw_status = pci_alloc_consistent(tp->pdev,
5234 TG3_HW_STATUS_SIZE,
5235 &tp->status_mapping);
5236 if (!tp->hw_status)
5237 goto err_out;
5238
5239 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5240 sizeof(struct tg3_hw_stats),
5241 &tp->stats_mapping);
5242 if (!tp->hw_stats)
5243 goto err_out;
5244
5245 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5246 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5247
5248 return 0;
5249
5250err_out:
5251 tg3_free_consistent(tp);
5252 return -ENOMEM;
5253}
5254
5255#define MAX_WAIT_CNT 1000
5256
5257/* To stop a block, clear the enable bit and poll till it
5258 * clears. tp->lock is held.
5259 */
5260static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5261{
5262 unsigned int i;
5263 u32 val;
5264
5265 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5266 switch (ofs) {
5267 case RCVLSC_MODE:
5268 case DMAC_MODE:
5269 case MBFREE_MODE:
5270 case BUFMGR_MODE:
5271 case MEMARB_MODE:
5272 /* We can't enable/disable these bits of the
5273 * 5705/5750, just say success.
5274 */
5275 return 0;
5276
5277 default:
5278 break;
5279 };
5280 }
5281
5282 val = tr32(ofs);
5283 val &= ~enable_bit;
5284 tw32_f(ofs, val);
5285
5286 for (i = 0; i < MAX_WAIT_CNT; i++) {
5287 udelay(100);
5288 val = tr32(ofs);
5289 if ((val & enable_bit) == 0)
5290 break;
5291 }
5292
5293 if (i == MAX_WAIT_CNT && !silent) {
5294 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5295 "ofs=%lx enable_bit=%x\n",
5296 ofs, enable_bit);
5297 return -ENODEV;
5298 }
5299
5300 return 0;
5301}
5302
5303/* tp->lock is held. */
5304static int tg3_abort_hw(struct tg3 *tp, int silent)
5305{
5306 int i, err;
5307
5308 tg3_disable_ints(tp);
5309
5310 tp->rx_mode &= ~RX_MODE_ENABLE;
5311 tw32_f(MAC_RX_MODE, tp->rx_mode);
5312 udelay(10);
5313
5314 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5315 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5316 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5317 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5318 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5319 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5320
5321 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5322 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5323 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5324 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5325 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5326 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5327 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5328
5329 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5330 tw32_f(MAC_MODE, tp->mac_mode);
5331 udelay(40);
5332
5333 tp->tx_mode &= ~TX_MODE_ENABLE;
5334 tw32_f(MAC_TX_MODE, tp->tx_mode);
5335
5336 for (i = 0; i < MAX_WAIT_CNT; i++) {
5337 udelay(100);
5338 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5339 break;
5340 }
5341 if (i >= MAX_WAIT_CNT) {
5342 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5343 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5344 tp->dev->name, tr32(MAC_TX_MODE));
5345 err |= -ENODEV;
5346 }
5347
5348 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5349 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5350 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5351
5352 tw32(FTQ_RESET, 0xffffffff);
5353 tw32(FTQ_RESET, 0x00000000);
5354
5355 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5356 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5357
5358 if (tp->hw_status)
5359 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5360 if (tp->hw_stats)
5361 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5362
5363 return err;
5364}
5365
5366/* tp->lock is held. */
5367static int tg3_nvram_lock(struct tg3 *tp)
5368{
5369 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5370 int i;
5371
5372 if (tp->nvram_lock_cnt == 0) {
5373 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5374 for (i = 0; i < 8000; i++) {
5375 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5376 break;
5377 udelay(20);
5378 }
5379 if (i == 8000) {
5380 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5381 return -ENODEV;
5382 }
5383 }
5384 tp->nvram_lock_cnt++;
5385 }
5386 return 0;
5387}
5388
5389/* tp->lock is held. */
5390static void tg3_nvram_unlock(struct tg3 *tp)
5391{
5392 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5393 if (tp->nvram_lock_cnt > 0)
5394 tp->nvram_lock_cnt--;
5395 if (tp->nvram_lock_cnt == 0)
5396 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5397 }
5398}
5399
5400/* tp->lock is held. */
5401static void tg3_enable_nvram_access(struct tg3 *tp)
5402{
5403 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5404 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5405 u32 nvaccess = tr32(NVRAM_ACCESS);
5406
5407 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5408 }
5409}
5410
5411/* tp->lock is held. */
5412static void tg3_disable_nvram_access(struct tg3 *tp)
5413{
5414 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5415 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5416 u32 nvaccess = tr32(NVRAM_ACCESS);
5417
5418 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5419 }
5420}
5421
5422static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5423{
5424 int i;
5425 u32 apedata;
5426
5427 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5428 if (apedata != APE_SEG_SIG_MAGIC)
5429 return;
5430
5431 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5432 if (apedata != APE_FW_STATUS_READY)
5433 return;
5434
5435 /* Wait for up to 1 millisecond for APE to service previous event. */
5436 for (i = 0; i < 10; i++) {
5437 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5438 return;
5439
5440 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5441
5442 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5443 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5444 event | APE_EVENT_STATUS_EVENT_PENDING);
5445
5446 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5447
5448 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5449 break;
5450
5451 udelay(100);
5452 }
5453
5454 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5455 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5456}
5457
5458static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5459{
5460 u32 event;
5461 u32 apedata;
5462
5463 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5464 return;
5465
5466 switch (kind) {
5467 case RESET_KIND_INIT:
5468 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5469 APE_HOST_SEG_SIG_MAGIC);
5470 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5471 APE_HOST_SEG_LEN_MAGIC);
5472 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5473 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5474 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5475 APE_HOST_DRIVER_ID_MAGIC);
5476 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5477 APE_HOST_BEHAV_NO_PHYLOCK);
5478
5479 event = APE_EVENT_STATUS_STATE_START;
5480 break;
5481 case RESET_KIND_SHUTDOWN:
5482 event = APE_EVENT_STATUS_STATE_UNLOAD;
5483 break;
5484 case RESET_KIND_SUSPEND:
5485 event = APE_EVENT_STATUS_STATE_SUSPEND;
5486 break;
5487 default:
5488 return;
5489 }
5490
5491 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5492
5493 tg3_ape_send_event(tp, event);
5494}
5495
5496/* tp->lock is held. */
5497static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5498{
5499 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5500 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5501
5502 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5503 switch (kind) {
5504 case RESET_KIND_INIT:
5505 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5506 DRV_STATE_START);
5507 break;
5508
5509 case RESET_KIND_SHUTDOWN:
5510 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5511 DRV_STATE_UNLOAD);
5512 break;
5513
5514 case RESET_KIND_SUSPEND:
5515 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5516 DRV_STATE_SUSPEND);
5517 break;
5518
5519 default:
5520 break;
5521 };
5522 }
5523
5524 if (kind == RESET_KIND_INIT ||
5525 kind == RESET_KIND_SUSPEND)
5526 tg3_ape_driver_state_change(tp, kind);
5527}
5528
5529/* tp->lock is held. */
5530static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5531{
5532 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5533 switch (kind) {
5534 case RESET_KIND_INIT:
5535 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5536 DRV_STATE_START_DONE);
5537 break;
5538
5539 case RESET_KIND_SHUTDOWN:
5540 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5541 DRV_STATE_UNLOAD_DONE);
5542 break;
5543
5544 default:
5545 break;
5546 };
5547 }
5548
5549 if (kind == RESET_KIND_SHUTDOWN)
5550 tg3_ape_driver_state_change(tp, kind);
5551}
5552
5553/* tp->lock is held. */
5554static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5555{
5556 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5557 switch (kind) {
5558 case RESET_KIND_INIT:
5559 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5560 DRV_STATE_START);
5561 break;
5562
5563 case RESET_KIND_SHUTDOWN:
5564 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5565 DRV_STATE_UNLOAD);
5566 break;
5567
5568 case RESET_KIND_SUSPEND:
5569 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5570 DRV_STATE_SUSPEND);
5571 break;
5572
5573 default:
5574 break;
5575 };
5576 }
5577}
5578
5579static int tg3_poll_fw(struct tg3 *tp)
5580{
5581 int i;
5582 u32 val;
5583
5584 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5585 /* Wait up to 20ms for init done. */
5586 for (i = 0; i < 200; i++) {
5587 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5588 return 0;
5589 udelay(100);
5590 }
5591 return -ENODEV;
5592 }
5593
5594 /* Wait for firmware initialization to complete. */
5595 for (i = 0; i < 100000; i++) {
5596 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5597 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5598 break;
5599 udelay(10);
5600 }
5601
5602 /* Chip might not be fitted with firmware. Some Sun onboard
5603 * parts are configured like that. So don't signal the timeout
5604 * of the above loop as an error, but do report the lack of
5605 * running firmware once.
5606 */
5607 if (i >= 100000 &&
5608 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5609 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5610
5611 printk(KERN_INFO PFX "%s: No firmware running.\n",
5612 tp->dev->name);
5613 }
5614
5615 return 0;
5616}
5617
5618/* Save PCI command register before chip reset */
5619static void tg3_save_pci_state(struct tg3 *tp)
5620{
5621 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5622}
5623
5624/* Restore PCI state after chip reset */
5625static void tg3_restore_pci_state(struct tg3 *tp)
5626{
5627 u32 val;
5628
5629 /* Re-enable indirect register accesses. */
5630 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5631 tp->misc_host_ctrl);
5632
5633 /* Set MAX PCI retry to zero. */
5634 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5635 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5636 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5637 val |= PCISTATE_RETRY_SAME_DMA;
5638 /* Allow reads and writes to the APE register and memory space. */
5639 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5640 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5641 PCISTATE_ALLOW_APE_SHMEM_WR;
5642 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5643
5644 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5645
5646 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5647 pcie_set_readrq(tp->pdev, 4096);
5648 else {
5649 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5650 tp->pci_cacheline_sz);
5651 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5652 tp->pci_lat_timer);
5653 }
5654
5655 /* Make sure PCI-X relaxed ordering bit is clear. */
5656 if (tp->pcix_cap) {
5657 u16 pcix_cmd;
5658
5659 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5660 &pcix_cmd);
5661 pcix_cmd &= ~PCI_X_CMD_ERO;
5662 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5663 pcix_cmd);
5664 }
5665
5666 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5667
5668 /* Chip reset on 5780 will reset MSI enable bit,
5669 * so need to restore it.
5670 */
5671 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5672 u16 ctrl;
5673
5674 pci_read_config_word(tp->pdev,
5675 tp->msi_cap + PCI_MSI_FLAGS,
5676 &ctrl);
5677 pci_write_config_word(tp->pdev,
5678 tp->msi_cap + PCI_MSI_FLAGS,
5679 ctrl | PCI_MSI_FLAGS_ENABLE);
5680 val = tr32(MSGINT_MODE);
5681 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5682 }
5683 }
5684}
5685
5686static void tg3_stop_fw(struct tg3 *);
5687
5688/* tp->lock is held. */
5689static int tg3_chip_reset(struct tg3 *tp)
5690{
5691 u32 val;
5692 void (*write_op)(struct tg3 *, u32, u32);
5693 int err;
5694
5695 tg3_nvram_lock(tp);
5696
5697 tg3_mdio_stop(tp);
5698
5699 /* No matching tg3_nvram_unlock() after this because
5700 * chip reset below will undo the nvram lock.
5701 */
5702 tp->nvram_lock_cnt = 0;
5703
5704 /* GRC_MISC_CFG core clock reset will clear the memory
5705 * enable bit in PCI register 4 and the MSI enable bit
5706 * on some chips, so we save relevant registers here.
5707 */
5708 tg3_save_pci_state(tp);
5709
5710 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5711 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5712 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5713 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5714 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
5715 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
5716 tw32(GRC_FASTBOOT_PC, 0);
5717
5718 /*
5719 * We must avoid the readl() that normally takes place.
5720 * It locks machines, causes machine checks, and other
5721 * fun things. So, temporarily disable the 5701
5722 * hardware workaround, while we do the reset.
5723 */
5724 write_op = tp->write32;
5725 if (write_op == tg3_write_flush_reg32)
5726 tp->write32 = tg3_write32;
5727
5728 /* Prevent the irq handler from reading or writing PCI registers
5729 * during chip reset when the memory enable bit in the PCI command
5730 * register may be cleared. The chip does not generate interrupt
5731 * at this time, but the irq handler may still be called due to irq
5732 * sharing or irqpoll.
5733 */
5734 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5735 if (tp->hw_status) {
5736 tp->hw_status->status = 0;
5737 tp->hw_status->status_tag = 0;
5738 }
5739 tp->last_tag = 0;
5740 smp_mb();
5741 synchronize_irq(tp->pdev->irq);
5742
5743 /* do the reset */
5744 val = GRC_MISC_CFG_CORECLK_RESET;
5745
5746 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5747 if (tr32(0x7e2c) == 0x60) {
5748 tw32(0x7e2c, 0x20);
5749 }
5750 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5751 tw32(GRC_MISC_CFG, (1 << 29));
5752 val |= (1 << 29);
5753 }
5754 }
5755
5756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5757 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5758 tw32(GRC_VCPU_EXT_CTRL,
5759 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5760 }
5761
5762 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5763 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5764 tw32(GRC_MISC_CFG, val);
5765
5766 /* restore 5701 hardware bug workaround write method */
5767 tp->write32 = write_op;
5768
5769 /* Unfortunately, we have to delay before the PCI read back.
5770 * Some 575X chips even will not respond to a PCI cfg access
5771 * when the reset command is given to the chip.
5772 *
5773 * How do these hardware designers expect things to work
5774 * properly if the PCI write is posted for a long period
5775 * of time? It is always necessary to have some method by
5776 * which a register read back can occur to push the write
5777 * out which does the reset.
5778 *
5779 * For most tg3 variants the trick below was working.
5780 * Ho hum...
5781 */
5782 udelay(120);
5783
5784 /* Flush PCI posted writes. The normal MMIO registers
5785 * are inaccessible at this time so this is the only
5786 * way to make this reliably (actually, this is no longer
5787 * the case, see above). I tried to use indirect
5788 * register read/write but this upset some 5701 variants.
5789 */
5790 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5791
5792 udelay(120);
5793
5794 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5795 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5796 int i;
5797 u32 cfg_val;
5798
5799 /* Wait for link training to complete. */
5800 for (i = 0; i < 5000; i++)
5801 udelay(100);
5802
5803 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5804 pci_write_config_dword(tp->pdev, 0xc4,
5805 cfg_val | (1 << 15));
5806 }
5807 /* Set PCIE max payload size and clear error status. */
5808 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5809 }
5810
5811 tg3_restore_pci_state(tp);
5812
5813 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5814
5815 val = 0;
5816 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5817 val = tr32(MEMARB_MODE);
5818 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5819
5820 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5821 tg3_stop_fw(tp);
5822 tw32(0x5000, 0x400);
5823 }
5824
5825 tw32(GRC_MODE, tp->grc_mode);
5826
5827 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5828 val = tr32(0xc4);
5829
5830 tw32(0xc4, val | (1 << 15));
5831 }
5832
5833 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5835 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5836 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5837 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5838 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5839 }
5840
5841 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5842 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5843 tw32_f(MAC_MODE, tp->mac_mode);
5844 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5845 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5846 tw32_f(MAC_MODE, tp->mac_mode);
5847 } else
5848 tw32_f(MAC_MODE, 0);
5849 udelay(40);
5850
5851 tg3_mdio_start(tp);
5852
5853 err = tg3_poll_fw(tp);
5854 if (err)
5855 return err;
5856
5857 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5858 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5859 val = tr32(0x7c00);
5860
5861 tw32(0x7c00, val | (1 << 25));
5862 }
5863
5864 /* Reprobe ASF enable state. */
5865 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5866 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5867 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5868 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5869 u32 nic_cfg;
5870
5871 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5872 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5873 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5874 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5875 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5876 }
5877 }
5878
5879 return 0;
5880}
5881
5882/* tp->lock is held. */
5883static void tg3_stop_fw(struct tg3 *tp)
5884{
5885 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5886 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5887 u32 val;
5888
5889 /* Wait for RX cpu to ACK the previous event. */
5890 tg3_wait_for_event_ack(tp);
5891
5892 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5893 val = tr32(GRC_RX_CPU_EVENT);
5894 val |= GRC_RX_CPU_DRIVER_EVENT;
5895 tw32(GRC_RX_CPU_EVENT, val);
5896
5897 /* Wait for RX cpu to ACK this event. */
5898 tg3_wait_for_event_ack(tp);
5899 }
5900}
5901
5902/* tp->lock is held. */
5903static int tg3_halt(struct tg3 *tp, int kind, int silent)
5904{
5905 int err;
5906
5907 tg3_stop_fw(tp);
5908
5909 tg3_write_sig_pre_reset(tp, kind);
5910
5911 tg3_abort_hw(tp, silent);
5912 err = tg3_chip_reset(tp);
5913
5914 tg3_write_sig_legacy(tp, kind);
5915 tg3_write_sig_post_reset(tp, kind);
5916
5917 if (err)
5918 return err;
5919
5920 return 0;
5921}
5922
5923#define TG3_FW_RELEASE_MAJOR 0x0
5924#define TG3_FW_RELASE_MINOR 0x0
5925#define TG3_FW_RELEASE_FIX 0x0
5926#define TG3_FW_START_ADDR 0x08000000
5927#define TG3_FW_TEXT_ADDR 0x08000000
5928#define TG3_FW_TEXT_LEN 0x9c0
5929#define TG3_FW_RODATA_ADDR 0x080009c0
5930#define TG3_FW_RODATA_LEN 0x60
5931#define TG3_FW_DATA_ADDR 0x08000a40
5932#define TG3_FW_DATA_LEN 0x20
5933#define TG3_FW_SBSS_ADDR 0x08000a60
5934#define TG3_FW_SBSS_LEN 0xc
5935#define TG3_FW_BSS_ADDR 0x08000a70
5936#define TG3_FW_BSS_LEN 0x10
5937
5938static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5939 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5940 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5941 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5942 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5943 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5944 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5945 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5946 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5947 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5948 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5949 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5950 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5951 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5952 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5953 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5954 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5955 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5956 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5957 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5958 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5959 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5960 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5961 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5962 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5963 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5964 0, 0, 0, 0, 0, 0,
5965 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5966 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5967 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5968 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5969 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5970 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5971 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5972 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5973 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5974 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5975 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5976 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5977 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5978 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5979 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5980 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5981 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5982 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5983 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5984 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5985 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5986 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5987 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5988 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5989 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5990 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5991 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5992 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5993 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5994 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5995 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5996 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5997 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5998 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5999 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
6000 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
6001 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
6002 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
6003 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
6004 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
6005 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
6006 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
6007 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
6008 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
6009 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
6010 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
6011 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
6012 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
6013 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
6014 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
6015 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
6016 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
6017 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
6018 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
6019 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
6020 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
6021 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
6022 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
6023 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
6024 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
6025 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
6026 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
6027 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
6028 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
6029 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
6030};
6031
6032static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
6033 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
6034 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
6035 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6036 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
6037 0x00000000
6038};
6039
6040#if 0 /* All zeros, don't eat up space with it. */
6041u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
6042 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6043 0x00000000, 0x00000000, 0x00000000, 0x00000000
6044};
6045#endif
6046
6047#define RX_CPU_SCRATCH_BASE 0x30000
6048#define RX_CPU_SCRATCH_SIZE 0x04000
6049#define TX_CPU_SCRATCH_BASE 0x34000
6050#define TX_CPU_SCRATCH_SIZE 0x04000
6051
6052/* tp->lock is held. */
6053static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6054{
6055 int i;
6056
6057 BUG_ON(offset == TX_CPU_BASE &&
6058 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6059
6060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6061 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6062
6063 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6064 return 0;
6065 }
6066 if (offset == RX_CPU_BASE) {
6067 for (i = 0; i < 10000; i++) {
6068 tw32(offset + CPU_STATE, 0xffffffff);
6069 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6070 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6071 break;
6072 }
6073
6074 tw32(offset + CPU_STATE, 0xffffffff);
6075 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6076 udelay(10);
6077 } else {
6078 for (i = 0; i < 10000; i++) {
6079 tw32(offset + CPU_STATE, 0xffffffff);
6080 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6081 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6082 break;
6083 }
6084 }
6085
6086 if (i >= 10000) {
6087 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6088 "and %s CPU\n",
6089 tp->dev->name,
6090 (offset == RX_CPU_BASE ? "RX" : "TX"));
6091 return -ENODEV;
6092 }
6093
6094 /* Clear firmware's nvram arbitration. */
6095 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6096 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6097 return 0;
6098}
6099
6100struct fw_info {
6101 unsigned int text_base;
6102 unsigned int text_len;
6103 const u32 *text_data;
6104 unsigned int rodata_base;
6105 unsigned int rodata_len;
6106 const u32 *rodata_data;
6107 unsigned int data_base;
6108 unsigned int data_len;
6109 const u32 *data_data;
6110};
6111
6112/* tp->lock is held. */
6113static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6114 int cpu_scratch_size, struct fw_info *info)
6115{
6116 int err, lock_err, i;
6117 void (*write_op)(struct tg3 *, u32, u32);
6118
6119 if (cpu_base == TX_CPU_BASE &&
6120 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6121 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6122 "TX cpu firmware on %s which is 5705.\n",
6123 tp->dev->name);
6124 return -EINVAL;
6125 }
6126
6127 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6128 write_op = tg3_write_mem;
6129 else
6130 write_op = tg3_write_indirect_reg32;
6131
6132 /* It is possible that bootcode is still loading at this point.
6133 * Get the nvram lock first before halting the cpu.
6134 */
6135 lock_err = tg3_nvram_lock(tp);
6136 err = tg3_halt_cpu(tp, cpu_base);
6137 if (!lock_err)
6138 tg3_nvram_unlock(tp);
6139 if (err)
6140 goto out;
6141
6142 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6143 write_op(tp, cpu_scratch_base + i, 0);
6144 tw32(cpu_base + CPU_STATE, 0xffffffff);
6145 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6146 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
6147 write_op(tp, (cpu_scratch_base +
6148 (info->text_base & 0xffff) +
6149 (i * sizeof(u32))),
6150 (info->text_data ?
6151 info->text_data[i] : 0));
6152 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
6153 write_op(tp, (cpu_scratch_base +
6154 (info->rodata_base & 0xffff) +
6155 (i * sizeof(u32))),
6156 (info->rodata_data ?
6157 info->rodata_data[i] : 0));
6158 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
6159 write_op(tp, (cpu_scratch_base +
6160 (info->data_base & 0xffff) +
6161 (i * sizeof(u32))),
6162 (info->data_data ?
6163 info->data_data[i] : 0));
6164
6165 err = 0;
6166
6167out:
6168 return err;
6169}
6170
6171/* tp->lock is held. */
6172static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6173{
6174 struct fw_info info;
6175 int err, i;
6176
6177 info.text_base = TG3_FW_TEXT_ADDR;
6178 info.text_len = TG3_FW_TEXT_LEN;
6179 info.text_data = &tg3FwText[0];
6180 info.rodata_base = TG3_FW_RODATA_ADDR;
6181 info.rodata_len = TG3_FW_RODATA_LEN;
6182 info.rodata_data = &tg3FwRodata[0];
6183 info.data_base = TG3_FW_DATA_ADDR;
6184 info.data_len = TG3_FW_DATA_LEN;
6185 info.data_data = NULL;
6186
6187 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6188 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6189 &info);
6190 if (err)
6191 return err;
6192
6193 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6194 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6195 &info);
6196 if (err)
6197 return err;
6198
6199 /* Now startup only the RX cpu. */
6200 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6201 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
6202
6203 for (i = 0; i < 5; i++) {
6204 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
6205 break;
6206 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6207 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6208 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
6209 udelay(1000);
6210 }
6211 if (i >= 5) {
6212 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6213 "to set RX CPU PC, is %08x should be %08x\n",
6214 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6215 TG3_FW_TEXT_ADDR);
6216 return -ENODEV;
6217 }
6218 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6219 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6220
6221 return 0;
6222}
6223
6224
6225#define TG3_TSO_FW_RELEASE_MAJOR 0x1
6226#define TG3_TSO_FW_RELASE_MINOR 0x6
6227#define TG3_TSO_FW_RELEASE_FIX 0x0
6228#define TG3_TSO_FW_START_ADDR 0x08000000
6229#define TG3_TSO_FW_TEXT_ADDR 0x08000000
6230#define TG3_TSO_FW_TEXT_LEN 0x1aa0
6231#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
6232#define TG3_TSO_FW_RODATA_LEN 0x60
6233#define TG3_TSO_FW_DATA_ADDR 0x08001b20
6234#define TG3_TSO_FW_DATA_LEN 0x30
6235#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
6236#define TG3_TSO_FW_SBSS_LEN 0x2c
6237#define TG3_TSO_FW_BSS_ADDR 0x08001b80
6238#define TG3_TSO_FW_BSS_LEN 0x894
6239
6240static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
6241 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
6242 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
6243 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6244 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
6245 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
6246 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
6247 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
6248 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
6249 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
6250 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
6251 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
6252 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
6253 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
6254 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
6255 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
6256 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
6257 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
6258 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
6259 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6260 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
6261 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
6262 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
6263 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
6264 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
6265 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
6266 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
6267 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
6268 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
6269 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
6270 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6271 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
6272 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
6273 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
6274 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
6275 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
6276 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
6277 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
6278 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
6279 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6280 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
6281 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
6282 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
6283 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
6284 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
6285 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
6286 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
6287 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
6288 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6289 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
6290 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6291 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
6292 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
6293 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
6294 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
6295 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
6296 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
6297 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
6298 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
6299 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
6300 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
6301 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
6302 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
6303 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
6304 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
6305 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
6306 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
6307 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
6308 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
6309 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
6310 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
6311 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
6312 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
6313 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
6314 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
6315 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
6316 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
6317 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
6318 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
6319 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
6320 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6321 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6322 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6323 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6324 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6325 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6326 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6327 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6328 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6329 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6330 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6331 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6332 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6333 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6334 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6335 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6336 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6337 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6338 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6339 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6340 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6341 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6342 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6343 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6344 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6345 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6346 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6347 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6348 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6349 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6350 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6351 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6352 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6353 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6354 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6355 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6356 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6357 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6358 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6359 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6360 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6361 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6362 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6363 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6364 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6365 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6366 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6367 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6368 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6369 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6370 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6371 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6372 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6373 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6374 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6375 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6376 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6377 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6378 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6379 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6380 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6381 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6382 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6383 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6384 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6385 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6386 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6387 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6388 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6389 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6390 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6391 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6392 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6393 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6394 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6395 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6396 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6397 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6398 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6399 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6400 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6401 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6402 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6403 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6404 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6405 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6406 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6407 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6408 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6409 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6410 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6411 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6412 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6413 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6414 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6415 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6416 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6417 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6418 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6419 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6420 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6421 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6422 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6423 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6424 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6425 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6426 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6427 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6428 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6429 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6430 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6431 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6432 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6433 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6434 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6435 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6436 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6437 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6438 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6439 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6440 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6441 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6442 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6443 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6444 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6445 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6446 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6447 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6448 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6449 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6450 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6451 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6452 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6453 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6454 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6455 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6456 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6457 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6458 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6459 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6460 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6461 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6462 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6463 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6464 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6465 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6466 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6467 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6468 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6469 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6470 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6471 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6472 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6473 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6474 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6475 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6476 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6477 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6478 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6479 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6480 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6481 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6482 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6483 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6484 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6485 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6486 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6487 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6488 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6489 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6490 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6491 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6492 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6493 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6494 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6495 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6496 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6497 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6498 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6499 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6500 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6501 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6502 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6503 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6504 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6505 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6506 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6507 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6508 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6509 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6510 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6511 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6512 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6513 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6514 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6515 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6516 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6517 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6518 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6519 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6520 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6521 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6522 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6523 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6524 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6525};
6526
6527static const u32 tg3TsoFwRodata[] = {
6528 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6529 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6530 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6531 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6532 0x00000000,
6533};
6534
6535static const u32 tg3TsoFwData[] = {
6536 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6537 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6538 0x00000000,
6539};
6540
6541/* 5705 needs a special version of the TSO firmware. */
6542#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
6543#define TG3_TSO5_FW_RELASE_MINOR 0x2
6544#define TG3_TSO5_FW_RELEASE_FIX 0x0
6545#define TG3_TSO5_FW_START_ADDR 0x00010000
6546#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
6547#define TG3_TSO5_FW_TEXT_LEN 0xe90
6548#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
6549#define TG3_TSO5_FW_RODATA_LEN 0x50
6550#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
6551#define TG3_TSO5_FW_DATA_LEN 0x20
6552#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
6553#define TG3_TSO5_FW_SBSS_LEN 0x28
6554#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
6555#define TG3_TSO5_FW_BSS_LEN 0x88
6556
6557static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6558 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6559 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6560 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6561 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6562 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6563 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6564 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6565 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6566 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6567 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6568 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6569 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6570 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6571 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6572 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6573 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6574 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6575 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6576 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6577 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6578 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6579 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6580 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6581 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6582 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6583 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6584 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6585 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6586 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6587 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6588 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6589 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6590 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6591 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6592 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6593 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6594 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6595 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6596 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6597 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6598 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6599 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6600 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6601 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6602 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6603 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6604 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6605 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6606 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6607 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6608 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6609 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6610 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6611 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6612 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6613 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6614 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6615 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6616 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6617 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6618 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6619 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6620 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6621 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6622 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6623 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6624 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6625 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6626 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6627 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6628 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6629 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6630 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6631 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6632 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6633 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6634 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6635 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6636 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6637 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6638 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6639 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6640 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6641 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6642 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6643 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6644 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6645 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6646 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6647 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6648 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6649 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6650 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6651 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6652 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6653 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6654 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6655 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6656 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6657 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6658 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6659 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6660 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6661 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6662 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6663 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6664 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6665 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6666 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6667 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6668 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6669 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6670 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6671 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6672 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6673 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6674 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6675 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6676 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6677 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6678 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6679 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6680 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6681 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6682 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6683 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6684 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6685 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6686 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6687 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6688 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6689 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6690 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6691 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6692 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6693 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6694 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6695 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6696 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6697 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6698 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6699 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6700 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6701 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6702 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6703 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6704 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6705 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6706 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6707 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6708 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6709 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6710 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6711 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6712 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6713 0x00000000, 0x00000000, 0x00000000,
6714};
6715
6716static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6717 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6718 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6719 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6720 0x00000000, 0x00000000, 0x00000000,
6721};
6722
6723static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6724 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6725 0x00000000, 0x00000000, 0x00000000,
6726};
6727
6728/* tp->lock is held. */
6729static int tg3_load_tso_firmware(struct tg3 *tp)
6730{
6731 struct fw_info info;
6732 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6733 int err, i;
6734
6735 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6736 return 0;
6737
6738 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6739 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6740 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6741 info.text_data = &tg3Tso5FwText[0];
6742 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6743 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6744 info.rodata_data = &tg3Tso5FwRodata[0];
6745 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6746 info.data_len = TG3_TSO5_FW_DATA_LEN;
6747 info.data_data = &tg3Tso5FwData[0];
6748 cpu_base = RX_CPU_BASE;
6749 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6750 cpu_scratch_size = (info.text_len +
6751 info.rodata_len +
6752 info.data_len +
6753 TG3_TSO5_FW_SBSS_LEN +
6754 TG3_TSO5_FW_BSS_LEN);
6755 } else {
6756 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6757 info.text_len = TG3_TSO_FW_TEXT_LEN;
6758 info.text_data = &tg3TsoFwText[0];
6759 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6760 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6761 info.rodata_data = &tg3TsoFwRodata[0];
6762 info.data_base = TG3_TSO_FW_DATA_ADDR;
6763 info.data_len = TG3_TSO_FW_DATA_LEN;
6764 info.data_data = &tg3TsoFwData[0];
6765 cpu_base = TX_CPU_BASE;
6766 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6767 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6768 }
6769
6770 err = tg3_load_firmware_cpu(tp, cpu_base,
6771 cpu_scratch_base, cpu_scratch_size,
6772 &info);
6773 if (err)
6774 return err;
6775
6776 /* Now startup the cpu. */
6777 tw32(cpu_base + CPU_STATE, 0xffffffff);
6778 tw32_f(cpu_base + CPU_PC, info.text_base);
6779
6780 for (i = 0; i < 5; i++) {
6781 if (tr32(cpu_base + CPU_PC) == info.text_base)
6782 break;
6783 tw32(cpu_base + CPU_STATE, 0xffffffff);
6784 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6785 tw32_f(cpu_base + CPU_PC, info.text_base);
6786 udelay(1000);
6787 }
6788 if (i >= 5) {
6789 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6790 "to set CPU PC, is %08x should be %08x\n",
6791 tp->dev->name, tr32(cpu_base + CPU_PC),
6792 info.text_base);
6793 return -ENODEV;
6794 }
6795 tw32(cpu_base + CPU_STATE, 0xffffffff);
6796 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6797 return 0;
6798}
6799
6800
6801/* tp->lock is held. */
6802static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6803{
6804 u32 addr_high, addr_low;
6805 int i;
6806
6807 addr_high = ((tp->dev->dev_addr[0] << 8) |
6808 tp->dev->dev_addr[1]);
6809 addr_low = ((tp->dev->dev_addr[2] << 24) |
6810 (tp->dev->dev_addr[3] << 16) |
6811 (tp->dev->dev_addr[4] << 8) |
6812 (tp->dev->dev_addr[5] << 0));
6813 for (i = 0; i < 4; i++) {
6814 if (i == 1 && skip_mac_1)
6815 continue;
6816 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6817 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6818 }
6819
6820 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6821 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6822 for (i = 0; i < 12; i++) {
6823 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6824 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6825 }
6826 }
6827
6828 addr_high = (tp->dev->dev_addr[0] +
6829 tp->dev->dev_addr[1] +
6830 tp->dev->dev_addr[2] +
6831 tp->dev->dev_addr[3] +
6832 tp->dev->dev_addr[4] +
6833 tp->dev->dev_addr[5]) &
6834 TX_BACKOFF_SEED_MASK;
6835 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6836}
6837
6838static int tg3_set_mac_addr(struct net_device *dev, void *p)
6839{
6840 struct tg3 *tp = netdev_priv(dev);
6841 struct sockaddr *addr = p;
6842 int err = 0, skip_mac_1 = 0;
6843
6844 if (!is_valid_ether_addr(addr->sa_data))
6845 return -EINVAL;
6846
6847 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6848
6849 if (!netif_running(dev))
6850 return 0;
6851
6852 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6853 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6854
6855 addr0_high = tr32(MAC_ADDR_0_HIGH);
6856 addr0_low = tr32(MAC_ADDR_0_LOW);
6857 addr1_high = tr32(MAC_ADDR_1_HIGH);
6858 addr1_low = tr32(MAC_ADDR_1_LOW);
6859
6860 /* Skip MAC addr 1 if ASF is using it. */
6861 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6862 !(addr1_high == 0 && addr1_low == 0))
6863 skip_mac_1 = 1;
6864 }
6865 spin_lock_bh(&tp->lock);
6866 __tg3_set_mac_addr(tp, skip_mac_1);
6867 spin_unlock_bh(&tp->lock);
6868
6869 return err;
6870}
6871
6872/* tp->lock is held. */
6873static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6874 dma_addr_t mapping, u32 maxlen_flags,
6875 u32 nic_addr)
6876{
6877 tg3_write_mem(tp,
6878 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6879 ((u64) mapping >> 32));
6880 tg3_write_mem(tp,
6881 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6882 ((u64) mapping & 0xffffffff));
6883 tg3_write_mem(tp,
6884 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6885 maxlen_flags);
6886
6887 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6888 tg3_write_mem(tp,
6889 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6890 nic_addr);
6891}
6892
6893static void __tg3_set_rx_mode(struct net_device *);
6894static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6895{
6896 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6897 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6898 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6899 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6900 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6901 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6902 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6903 }
6904 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6905 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6906 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6907 u32 val = ec->stats_block_coalesce_usecs;
6908
6909 if (!netif_carrier_ok(tp->dev))
6910 val = 0;
6911
6912 tw32(HOSTCC_STAT_COAL_TICKS, val);
6913 }
6914}
6915
6916/* tp->lock is held. */
6917static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6918{
6919 u32 val, rdmac_mode;
6920 int i, err, limit;
6921
6922 tg3_disable_ints(tp);
6923
6924 tg3_stop_fw(tp);
6925
6926 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6927
6928 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6929 tg3_abort_hw(tp, 1);
6930 }
6931
6932 if (reset_phy &&
6933 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6934 tg3_phy_reset(tp);
6935
6936 err = tg3_chip_reset(tp);
6937 if (err)
6938 return err;
6939
6940 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6941
6942 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
6943 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
6944 val = tr32(TG3_CPMU_CTRL);
6945 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6946 tw32(TG3_CPMU_CTRL, val);
6947
6948 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6949 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6950 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6951 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6952
6953 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6954 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6955 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6956 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6957
6958 val = tr32(TG3_CPMU_HST_ACC);
6959 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6960 val |= CPMU_HST_ACC_MACCLK_6_25;
6961 tw32(TG3_CPMU_HST_ACC, val);
6962 }
6963
6964 /* This works around an issue with Athlon chipsets on
6965 * B3 tigon3 silicon. This bit has no effect on any
6966 * other revision. But do not set this on PCI Express
6967 * chips and don't even touch the clocks if the CPMU is present.
6968 */
6969 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6970 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6971 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6972 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6973 }
6974
6975 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6976 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6977 val = tr32(TG3PCI_PCISTATE);
6978 val |= PCISTATE_RETRY_SAME_DMA;
6979 tw32(TG3PCI_PCISTATE, val);
6980 }
6981
6982 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6983 /* Allow reads and writes to the
6984 * APE register and memory space.
6985 */
6986 val = tr32(TG3PCI_PCISTATE);
6987 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6988 PCISTATE_ALLOW_APE_SHMEM_WR;
6989 tw32(TG3PCI_PCISTATE, val);
6990 }
6991
6992 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6993 /* Enable some hw fixes. */
6994 val = tr32(TG3PCI_MSI_DATA);
6995 val |= (1 << 26) | (1 << 28) | (1 << 29);
6996 tw32(TG3PCI_MSI_DATA, val);
6997 }
6998
6999 /* Descriptor ring init may make accesses to the
7000 * NIC SRAM area to setup the TX descriptors, so we
7001 * can only do this after the hardware has been
7002 * successfully reset.
7003 */
7004 err = tg3_init_rings(tp);
7005 if (err)
7006 return err;
7007
7008 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7009 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7010 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7011 /* This value is determined during the probe time DMA
7012 * engine test, tg3_test_dma.
7013 */
7014 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7015 }
7016
7017 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7018 GRC_MODE_4X_NIC_SEND_RINGS |
7019 GRC_MODE_NO_TX_PHDR_CSUM |
7020 GRC_MODE_NO_RX_PHDR_CSUM);
7021 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7022
7023 /* Pseudo-header checksum is done by hardware logic and not
7024 * the offload processers, so make the chip do the pseudo-
7025 * header checksums on receive. For transmit it is more
7026 * convenient to do the pseudo-header checksum in software
7027 * as Linux does that on transmit for us in all cases.
7028 */
7029 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7030
7031 tw32(GRC_MODE,
7032 tp->grc_mode |
7033 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7034
7035 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7036 val = tr32(GRC_MISC_CFG);
7037 val &= ~0xff;
7038 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7039 tw32(GRC_MISC_CFG, val);
7040
7041 /* Initialize MBUF/DESC pool. */
7042 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7043 /* Do nothing. */
7044 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7045 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7047 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7048 else
7049 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7050 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7051 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7052 }
7053 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7054 int fw_len;
7055
7056 fw_len = (TG3_TSO5_FW_TEXT_LEN +
7057 TG3_TSO5_FW_RODATA_LEN +
7058 TG3_TSO5_FW_DATA_LEN +
7059 TG3_TSO5_FW_SBSS_LEN +
7060 TG3_TSO5_FW_BSS_LEN);
7061 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7062 tw32(BUFMGR_MB_POOL_ADDR,
7063 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7064 tw32(BUFMGR_MB_POOL_SIZE,
7065 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7066 }
7067
7068 if (tp->dev->mtu <= ETH_DATA_LEN) {
7069 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7070 tp->bufmgr_config.mbuf_read_dma_low_water);
7071 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7072 tp->bufmgr_config.mbuf_mac_rx_low_water);
7073 tw32(BUFMGR_MB_HIGH_WATER,
7074 tp->bufmgr_config.mbuf_high_water);
7075 } else {
7076 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7077 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7078 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7079 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7080 tw32(BUFMGR_MB_HIGH_WATER,
7081 tp->bufmgr_config.mbuf_high_water_jumbo);
7082 }
7083 tw32(BUFMGR_DMA_LOW_WATER,
7084 tp->bufmgr_config.dma_low_water);
7085 tw32(BUFMGR_DMA_HIGH_WATER,
7086 tp->bufmgr_config.dma_high_water);
7087
7088 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7089 for (i = 0; i < 2000; i++) {
7090 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7091 break;
7092 udelay(10);
7093 }
7094 if (i >= 2000) {
7095 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7096 tp->dev->name);
7097 return -ENODEV;
7098 }
7099
7100 /* Setup replenish threshold. */
7101 val = tp->rx_pending / 8;
7102 if (val == 0)
7103 val = 1;
7104 else if (val > tp->rx_std_max_post)
7105 val = tp->rx_std_max_post;
7106 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7107 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7108 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7109
7110 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7111 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7112 }
7113
7114 tw32(RCVBDI_STD_THRESH, val);
7115
7116 /* Initialize TG3_BDINFO's at:
7117 * RCVDBDI_STD_BD: standard eth size rx ring
7118 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7119 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7120 *
7121 * like so:
7122 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7123 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7124 * ring attribute flags
7125 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7126 *
7127 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7128 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7129 *
7130 * The size of each ring is fixed in the firmware, but the location is
7131 * configurable.
7132 */
7133 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7134 ((u64) tp->rx_std_mapping >> 32));
7135 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7136 ((u64) tp->rx_std_mapping & 0xffffffff));
7137 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7138 NIC_SRAM_RX_BUFFER_DESC);
7139
7140 /* Don't even try to program the JUMBO/MINI buffer descriptor
7141 * configs on 5705.
7142 */
7143 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7144 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7145 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
7146 } else {
7147 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7148 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7149
7150 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7151 BDINFO_FLAGS_DISABLED);
7152
7153 /* Setup replenish threshold. */
7154 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7155
7156 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7157 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7158 ((u64) tp->rx_jumbo_mapping >> 32));
7159 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7160 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
7161 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7162 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7163 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7164 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7165 } else {
7166 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7167 BDINFO_FLAGS_DISABLED);
7168 }
7169
7170 }
7171
7172 /* There is only one send ring on 5705/5750, no need to explicitly
7173 * disable the others.
7174 */
7175 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7176 /* Clear out send RCB ring in SRAM. */
7177 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7178 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7179 BDINFO_FLAGS_DISABLED);
7180 }
7181
7182 tp->tx_prod = 0;
7183 tp->tx_cons = 0;
7184 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7185 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7186
7187 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7188 tp->tx_desc_mapping,
7189 (TG3_TX_RING_SIZE <<
7190 BDINFO_FLAGS_MAXLEN_SHIFT),
7191 NIC_SRAM_TX_BUFFER_DESC);
7192
7193 /* There is only one receive return ring on 5705/5750, no need
7194 * to explicitly disable the others.
7195 */
7196 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7197 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7198 i += TG3_BDINFO_SIZE) {
7199 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7200 BDINFO_FLAGS_DISABLED);
7201 }
7202 }
7203
7204 tp->rx_rcb_ptr = 0;
7205 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7206
7207 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7208 tp->rx_rcb_mapping,
7209 (TG3_RX_RCB_RING_SIZE(tp) <<
7210 BDINFO_FLAGS_MAXLEN_SHIFT),
7211 0);
7212
7213 tp->rx_std_ptr = tp->rx_pending;
7214 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7215 tp->rx_std_ptr);
7216
7217 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7218 tp->rx_jumbo_pending : 0;
7219 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7220 tp->rx_jumbo_ptr);
7221
7222 /* Initialize MAC address and backoff seed. */
7223 __tg3_set_mac_addr(tp, 0);
7224
7225 /* MTU + ethernet header + FCS + optional VLAN tag */
7226 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
7227
7228 /* The slot time is changed by tg3_setup_phy if we
7229 * run at gigabit with half duplex.
7230 */
7231 tw32(MAC_TX_LENGTHS,
7232 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7233 (6 << TX_LENGTHS_IPG_SHIFT) |
7234 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7235
7236 /* Receive rules. */
7237 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7238 tw32(RCVLPC_CONFIG, 0x0181);
7239
7240 /* Calculate RDMAC_MODE setting early, we need it to determine
7241 * the RCVLPC_STATE_ENABLE mask.
7242 */
7243 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7244 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7245 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7246 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7247 RDMAC_MODE_LNGREAD_ENAB);
7248
7249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7251 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7252 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7253 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7254
7255 /* If statement applies to 5705 and 5750 PCI devices only */
7256 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7257 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7258 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7259 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7260 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7261 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7262 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7263 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7264 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7265 }
7266 }
7267
7268 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7269 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7270
7271 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7272 rdmac_mode |= (1 << 27);
7273
7274 /* Receive/send statistics. */
7275 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7276 val = tr32(RCVLPC_STATS_ENABLE);
7277 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7278 tw32(RCVLPC_STATS_ENABLE, val);
7279 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7280 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7281 val = tr32(RCVLPC_STATS_ENABLE);
7282 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7283 tw32(RCVLPC_STATS_ENABLE, val);
7284 } else {
7285 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7286 }
7287 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7288 tw32(SNDDATAI_STATSENAB, 0xffffff);
7289 tw32(SNDDATAI_STATSCTRL,
7290 (SNDDATAI_SCTRL_ENABLE |
7291 SNDDATAI_SCTRL_FASTUPD));
7292
7293 /* Setup host coalescing engine. */
7294 tw32(HOSTCC_MODE, 0);
7295 for (i = 0; i < 2000; i++) {
7296 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7297 break;
7298 udelay(10);
7299 }
7300
7301 __tg3_set_coalesce(tp, &tp->coal);
7302
7303 /* set status block DMA address */
7304 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7305 ((u64) tp->status_mapping >> 32));
7306 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7307 ((u64) tp->status_mapping & 0xffffffff));
7308
7309 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7310 /* Status/statistics block address. See tg3_timer,
7311 * the tg3_periodic_fetch_stats call there, and
7312 * tg3_get_stats to see how this works for 5705/5750 chips.
7313 */
7314 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7315 ((u64) tp->stats_mapping >> 32));
7316 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7317 ((u64) tp->stats_mapping & 0xffffffff));
7318 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7319 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7320 }
7321
7322 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7323
7324 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7325 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7326 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7327 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7328
7329 /* Clear statistics/status block in chip, and status block in ram. */
7330 for (i = NIC_SRAM_STATS_BLK;
7331 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7332 i += sizeof(u32)) {
7333 tg3_write_mem(tp, i, 0);
7334 udelay(40);
7335 }
7336 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7337
7338 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7339 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7340 /* reset to prevent losing 1st rx packet intermittently */
7341 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7342 udelay(10);
7343 }
7344
7345 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7346 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7347 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7348 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7349 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7350 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7351 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7352 udelay(40);
7353
7354 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7355 * If TG3_FLG2_IS_NIC is zero, we should read the
7356 * register to preserve the GPIO settings for LOMs. The GPIOs,
7357 * whether used as inputs or outputs, are set by boot code after
7358 * reset.
7359 */
7360 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7361 u32 gpio_mask;
7362
7363 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7364 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7365 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7366
7367 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7368 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7369 GRC_LCLCTRL_GPIO_OUTPUT3;
7370
7371 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7372 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7373
7374 tp->grc_local_ctrl &= ~gpio_mask;
7375 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7376
7377 /* GPIO1 must be driven high for eeprom write protect */
7378 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7379 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7380 GRC_LCLCTRL_GPIO_OUTPUT1);
7381 }
7382 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7383 udelay(100);
7384
7385 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7386 tp->last_tag = 0;
7387
7388 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7389 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7390 udelay(40);
7391 }
7392
7393 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7394 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7395 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7396 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7397 WDMAC_MODE_LNGREAD_ENAB);
7398
7399 /* If statement applies to 5705 and 5750 PCI devices only */
7400 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7401 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7402 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7403 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7404 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7405 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7406 /* nothing */
7407 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7408 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7409 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7410 val |= WDMAC_MODE_RX_ACCEL;
7411 }
7412 }
7413
7414 /* Enable host coalescing bug fix */
7415 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7416 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7417 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7418 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) ||
7419 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785))
7420 val |= WDMAC_MODE_STATUS_TAG_FIX;
7421
7422 tw32_f(WDMAC_MODE, val);
7423 udelay(40);
7424
7425 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7426 u16 pcix_cmd;
7427
7428 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7429 &pcix_cmd);
7430 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7431 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7432 pcix_cmd |= PCI_X_CMD_READ_2K;
7433 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7434 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7435 pcix_cmd |= PCI_X_CMD_READ_2K;
7436 }
7437 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7438 pcix_cmd);
7439 }
7440
7441 tw32_f(RDMAC_MODE, rdmac_mode);
7442 udelay(40);
7443
7444 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7445 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7446 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7447
7448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7449 tw32(SNDDATAC_MODE,
7450 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7451 else
7452 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7453
7454 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7455 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7456 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7457 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7458 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7459 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7460 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7461 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7462
7463 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7464 err = tg3_load_5701_a0_firmware_fix(tp);
7465 if (err)
7466 return err;
7467 }
7468
7469 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7470 err = tg3_load_tso_firmware(tp);
7471 if (err)
7472 return err;
7473 }
7474
7475 tp->tx_mode = TX_MODE_ENABLE;
7476 tw32_f(MAC_TX_MODE, tp->tx_mode);
7477 udelay(100);
7478
7479 tp->rx_mode = RX_MODE_ENABLE;
7480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7481 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7482 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
7483 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7484 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7485
7486 tw32_f(MAC_RX_MODE, tp->rx_mode);
7487 udelay(10);
7488
7489 tw32(MAC_LED_CTRL, tp->led_ctrl);
7490
7491 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7492 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7493 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7494 udelay(10);
7495 }
7496 tw32_f(MAC_RX_MODE, tp->rx_mode);
7497 udelay(10);
7498
7499 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7501 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7502 /* Set drive transmission level to 1.2V */
7503 /* only if the signal pre-emphasis bit is not set */
7504 val = tr32(MAC_SERDES_CFG);
7505 val &= 0xfffff000;
7506 val |= 0x880;
7507 tw32(MAC_SERDES_CFG, val);
7508 }
7509 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7510 tw32(MAC_SERDES_CFG, 0x616000);
7511 }
7512
7513 /* Prevent chip from dropping frames when flow control
7514 * is enabled.
7515 */
7516 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7517
7518 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7519 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7520 /* Use hardware link auto-negotiation */
7521 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7522 }
7523
7524 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7525 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7526 u32 tmp;
7527
7528 tmp = tr32(SERDES_RX_CTRL);
7529 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7530 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7531 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7532 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7533 }
7534
7535 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7536 if (tp->link_config.phy_is_low_power) {
7537 tp->link_config.phy_is_low_power = 0;
7538 tp->link_config.speed = tp->link_config.orig_speed;
7539 tp->link_config.duplex = tp->link_config.orig_duplex;
7540 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7541 }
7542
7543 err = tg3_setup_phy(tp, 0);
7544 if (err)
7545 return err;
7546
7547 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7548 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7549 u32 tmp;
7550
7551 /* Clear CRC stats. */
7552 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7553 tg3_writephy(tp, MII_TG3_TEST1,
7554 tmp | MII_TG3_TEST1_CRC_EN);
7555 tg3_readphy(tp, 0x14, &tmp);
7556 }
7557 }
7558 }
7559
7560 __tg3_set_rx_mode(tp->dev);
7561
7562 /* Initialize receive rules. */
7563 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7564 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7565 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7566 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7567
7568 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7569 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7570 limit = 8;
7571 else
7572 limit = 16;
7573 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7574 limit -= 4;
7575 switch (limit) {
7576 case 16:
7577 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7578 case 15:
7579 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7580 case 14:
7581 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7582 case 13:
7583 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7584 case 12:
7585 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7586 case 11:
7587 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7588 case 10:
7589 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7590 case 9:
7591 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7592 case 8:
7593 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7594 case 7:
7595 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7596 case 6:
7597 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7598 case 5:
7599 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7600 case 4:
7601 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7602 case 3:
7603 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7604 case 2:
7605 case 1:
7606
7607 default:
7608 break;
7609 };
7610
7611 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7612 /* Write our heartbeat update interval to APE. */
7613 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7614 APE_HOST_HEARTBEAT_INT_DISABLE);
7615
7616 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7617
7618 return 0;
7619}
7620
7621/* Called at device open time to get the chip ready for
7622 * packet processing. Invoked with tp->lock held.
7623 */
7624static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7625{
7626 int err;
7627
7628 /* Force the chip into D0. */
7629 err = tg3_set_power_state(tp, PCI_D0);
7630 if (err)
7631 goto out;
7632
7633 tg3_switch_clocks(tp);
7634
7635 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7636
7637 err = tg3_reset_hw(tp, reset_phy);
7638
7639out:
7640 return err;
7641}
7642
7643#define TG3_STAT_ADD32(PSTAT, REG) \
7644do { u32 __val = tr32(REG); \
7645 (PSTAT)->low += __val; \
7646 if ((PSTAT)->low < __val) \
7647 (PSTAT)->high += 1; \
7648} while (0)
7649
7650static void tg3_periodic_fetch_stats(struct tg3 *tp)
7651{
7652 struct tg3_hw_stats *sp = tp->hw_stats;
7653
7654 if (!netif_carrier_ok(tp->dev))
7655 return;
7656
7657 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7658 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7659 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7660 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7661 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7662 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7663 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7664 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7665 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7666 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7667 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7668 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7669 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7670
7671 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7672 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7673 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7674 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7675 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7676 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7677 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7678 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7679 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7680 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7681 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7682 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7683 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7684 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7685
7686 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7687 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7688 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7689}
7690
7691static void tg3_timer(unsigned long __opaque)
7692{
7693 struct tg3 *tp = (struct tg3 *) __opaque;
7694
7695 if (tp->irq_sync)
7696 goto restart_timer;
7697
7698 spin_lock(&tp->lock);
7699
7700 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7701 /* All of this garbage is because when using non-tagged
7702 * IRQ status the mailbox/status_block protocol the chip
7703 * uses with the cpu is race prone.
7704 */
7705 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7706 tw32(GRC_LOCAL_CTRL,
7707 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7708 } else {
7709 tw32(HOSTCC_MODE, tp->coalesce_mode |
7710 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7711 }
7712
7713 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7714 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7715 spin_unlock(&tp->lock);
7716 schedule_work(&tp->reset_task);
7717 return;
7718 }
7719 }
7720
7721 /* This part only runs once per second. */
7722 if (!--tp->timer_counter) {
7723 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7724 tg3_periodic_fetch_stats(tp);
7725
7726 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7727 u32 mac_stat;
7728 int phy_event;
7729
7730 mac_stat = tr32(MAC_STATUS);
7731
7732 phy_event = 0;
7733 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7734 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7735 phy_event = 1;
7736 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7737 phy_event = 1;
7738
7739 if (phy_event)
7740 tg3_setup_phy(tp, 0);
7741 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7742 u32 mac_stat = tr32(MAC_STATUS);
7743 int need_setup = 0;
7744
7745 if (netif_carrier_ok(tp->dev) &&
7746 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7747 need_setup = 1;
7748 }
7749 if (! netif_carrier_ok(tp->dev) &&
7750 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7751 MAC_STATUS_SIGNAL_DET))) {
7752 need_setup = 1;
7753 }
7754 if (need_setup) {
7755 if (!tp->serdes_counter) {
7756 tw32_f(MAC_MODE,
7757 (tp->mac_mode &
7758 ~MAC_MODE_PORT_MODE_MASK));
7759 udelay(40);
7760 tw32_f(MAC_MODE, tp->mac_mode);
7761 udelay(40);
7762 }
7763 tg3_setup_phy(tp, 0);
7764 }
7765 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7766 tg3_serdes_parallel_detect(tp);
7767
7768 tp->timer_counter = tp->timer_multiplier;
7769 }
7770
7771 /* Heartbeat is only sent once every 2 seconds.
7772 *
7773 * The heartbeat is to tell the ASF firmware that the host
7774 * driver is still alive. In the event that the OS crashes,
7775 * ASF needs to reset the hardware to free up the FIFO space
7776 * that may be filled with rx packets destined for the host.
7777 * If the FIFO is full, ASF will no longer function properly.
7778 *
7779 * Unintended resets have been reported on real time kernels
7780 * where the timer doesn't run on time. Netpoll will also have
7781 * same problem.
7782 *
7783 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7784 * to check the ring condition when the heartbeat is expiring
7785 * before doing the reset. This will prevent most unintended
7786 * resets.
7787 */
7788 if (!--tp->asf_counter) {
7789 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7790 u32 val;
7791
7792 tg3_wait_for_event_ack(tp);
7793
7794 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7795 FWCMD_NICDRV_ALIVE3);
7796 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7797 /* 5 seconds timeout */
7798 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7799 val = tr32(GRC_RX_CPU_EVENT);
7800 val |= GRC_RX_CPU_DRIVER_EVENT;
7801 tw32_f(GRC_RX_CPU_EVENT, val);
7802 }
7803 tp->asf_counter = tp->asf_multiplier;
7804 }
7805
7806 spin_unlock(&tp->lock);
7807
7808restart_timer:
7809 tp->timer.expires = jiffies + tp->timer_offset;
7810 add_timer(&tp->timer);
7811}
7812
7813static int tg3_request_irq(struct tg3 *tp)
7814{
7815 irq_handler_t fn;
7816 unsigned long flags;
7817 struct net_device *dev = tp->dev;
7818
7819 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7820 fn = tg3_msi;
7821 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7822 fn = tg3_msi_1shot;
7823 flags = IRQF_SAMPLE_RANDOM;
7824 } else {
7825 fn = tg3_interrupt;
7826 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7827 fn = tg3_interrupt_tagged;
7828 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7829 }
7830 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7831}
7832
7833static int tg3_test_interrupt(struct tg3 *tp)
7834{
7835 struct net_device *dev = tp->dev;
7836 int err, i, intr_ok = 0;
7837
7838 if (!netif_running(dev))
7839 return -ENODEV;
7840
7841 tg3_disable_ints(tp);
7842
7843 free_irq(tp->pdev->irq, dev);
7844
7845 err = request_irq(tp->pdev->irq, tg3_test_isr,
7846 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7847 if (err)
7848 return err;
7849
7850 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7851 tg3_enable_ints(tp);
7852
7853 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7854 HOSTCC_MODE_NOW);
7855
7856 for (i = 0; i < 5; i++) {
7857 u32 int_mbox, misc_host_ctrl;
7858
7859 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7860 TG3_64BIT_REG_LOW);
7861 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7862
7863 if ((int_mbox != 0) ||
7864 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7865 intr_ok = 1;
7866 break;
7867 }
7868
7869 msleep(10);
7870 }
7871
7872 tg3_disable_ints(tp);
7873
7874 free_irq(tp->pdev->irq, dev);
7875
7876 err = tg3_request_irq(tp);
7877
7878 if (err)
7879 return err;
7880
7881 if (intr_ok)
7882 return 0;
7883
7884 return -EIO;
7885}
7886
7887/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7888 * successfully restored
7889 */
7890static int tg3_test_msi(struct tg3 *tp)
7891{
7892 struct net_device *dev = tp->dev;
7893 int err;
7894 u16 pci_cmd;
7895
7896 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7897 return 0;
7898
7899 /* Turn off SERR reporting in case MSI terminates with Master
7900 * Abort.
7901 */
7902 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7903 pci_write_config_word(tp->pdev, PCI_COMMAND,
7904 pci_cmd & ~PCI_COMMAND_SERR);
7905
7906 err = tg3_test_interrupt(tp);
7907
7908 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7909
7910 if (!err)
7911 return 0;
7912
7913 /* other failures */
7914 if (err != -EIO)
7915 return err;
7916
7917 /* MSI test failed, go back to INTx mode */
7918 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7919 "switching to INTx mode. Please report this failure to "
7920 "the PCI maintainer and include system chipset information.\n",
7921 tp->dev->name);
7922
7923 free_irq(tp->pdev->irq, dev);
7924 pci_disable_msi(tp->pdev);
7925
7926 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7927
7928 err = tg3_request_irq(tp);
7929 if (err)
7930 return err;
7931
7932 /* Need to reset the chip because the MSI cycle may have terminated
7933 * with Master Abort.
7934 */
7935 tg3_full_lock(tp, 1);
7936
7937 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938 err = tg3_init_hw(tp, 1);
7939
7940 tg3_full_unlock(tp);
7941
7942 if (err)
7943 free_irq(tp->pdev->irq, dev);
7944
7945 return err;
7946}
7947
7948static int tg3_open(struct net_device *dev)
7949{
7950 struct tg3 *tp = netdev_priv(dev);
7951 int err;
7952
7953 netif_carrier_off(tp->dev);
7954
7955 tg3_full_lock(tp, 0);
7956
7957 err = tg3_set_power_state(tp, PCI_D0);
7958 if (err) {
7959 tg3_full_unlock(tp);
7960 return err;
7961 }
7962
7963 tg3_disable_ints(tp);
7964 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7965
7966 tg3_full_unlock(tp);
7967
7968 /* The placement of this call is tied
7969 * to the setup and use of Host TX descriptors.
7970 */
7971 err = tg3_alloc_consistent(tp);
7972 if (err)
7973 return err;
7974
7975 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7976 /* All MSI supporting chips should support tagged
7977 * status. Assert that this is the case.
7978 */
7979 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7980 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7981 "Not using MSI.\n", tp->dev->name);
7982 } else if (pci_enable_msi(tp->pdev) == 0) {
7983 u32 msi_mode;
7984
7985 msi_mode = tr32(MSGINT_MODE);
7986 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7987 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7988 }
7989 }
7990 err = tg3_request_irq(tp);
7991
7992 if (err) {
7993 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7994 pci_disable_msi(tp->pdev);
7995 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7996 }
7997 tg3_free_consistent(tp);
7998 return err;
7999 }
8000
8001 napi_enable(&tp->napi);
8002
8003 tg3_full_lock(tp, 0);
8004
8005 err = tg3_init_hw(tp, 1);
8006 if (err) {
8007 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8008 tg3_free_rings(tp);
8009 } else {
8010 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8011 tp->timer_offset = HZ;
8012 else
8013 tp->timer_offset = HZ / 10;
8014
8015 BUG_ON(tp->timer_offset > HZ);
8016 tp->timer_counter = tp->timer_multiplier =
8017 (HZ / tp->timer_offset);
8018 tp->asf_counter = tp->asf_multiplier =
8019 ((HZ / tp->timer_offset) * 2);
8020
8021 init_timer(&tp->timer);
8022 tp->timer.expires = jiffies + tp->timer_offset;
8023 tp->timer.data = (unsigned long) tp;
8024 tp->timer.function = tg3_timer;
8025 }
8026
8027 tg3_full_unlock(tp);
8028
8029 if (err) {
8030 napi_disable(&tp->napi);
8031 free_irq(tp->pdev->irq, dev);
8032 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8033 pci_disable_msi(tp->pdev);
8034 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8035 }
8036 tg3_free_consistent(tp);
8037 return err;
8038 }
8039
8040 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8041 err = tg3_test_msi(tp);
8042
8043 if (err) {
8044 tg3_full_lock(tp, 0);
8045
8046 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8047 pci_disable_msi(tp->pdev);
8048 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8049 }
8050 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8051 tg3_free_rings(tp);
8052 tg3_free_consistent(tp);
8053
8054 tg3_full_unlock(tp);
8055
8056 napi_disable(&tp->napi);
8057
8058 return err;
8059 }
8060
8061 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8062 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8063 u32 val = tr32(PCIE_TRANSACTION_CFG);
8064
8065 tw32(PCIE_TRANSACTION_CFG,
8066 val | PCIE_TRANS_CFG_1SHOT_MSI);
8067 }
8068 }
8069 }
8070
8071 tg3_phy_start(tp);
8072
8073 tg3_full_lock(tp, 0);
8074
8075 add_timer(&tp->timer);
8076 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8077 tg3_enable_ints(tp);
8078
8079 tg3_full_unlock(tp);
8080
8081 netif_start_queue(dev);
8082
8083 return 0;
8084}
8085
8086#if 0
8087/*static*/ void tg3_dump_state(struct tg3 *tp)
8088{
8089 u32 val32, val32_2, val32_3, val32_4, val32_5;
8090 u16 val16;
8091 int i;
8092
8093 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8094 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8095 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8096 val16, val32);
8097
8098 /* MAC block */
8099 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8100 tr32(MAC_MODE), tr32(MAC_STATUS));
8101 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8102 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8103 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8104 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8105 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8106 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8107
8108 /* Send data initiator control block */
8109 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8110 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8111 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8112 tr32(SNDDATAI_STATSCTRL));
8113
8114 /* Send data completion control block */
8115 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8116
8117 /* Send BD ring selector block */
8118 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8119 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8120
8121 /* Send BD initiator control block */
8122 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8123 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8124
8125 /* Send BD completion control block */
8126 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8127
8128 /* Receive list placement control block */
8129 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8130 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8131 printk(" RCVLPC_STATSCTRL[%08x]\n",
8132 tr32(RCVLPC_STATSCTRL));
8133
8134 /* Receive data and receive BD initiator control block */
8135 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8136 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8137
8138 /* Receive data completion control block */
8139 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8140 tr32(RCVDCC_MODE));
8141
8142 /* Receive BD initiator control block */
8143 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8144 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8145
8146 /* Receive BD completion control block */
8147 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8148 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8149
8150 /* Receive list selector control block */
8151 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8152 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8153
8154 /* Mbuf cluster free block */
8155 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8156 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8157
8158 /* Host coalescing control block */
8159 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8160 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8161 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8162 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8163 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8164 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8165 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8166 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8167 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8168 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8169 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8170 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8171
8172 /* Memory arbiter control block */
8173 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8174 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8175
8176 /* Buffer manager control block */
8177 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8178 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8179 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8180 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8181 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8182 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8183 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8184 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8185
8186 /* Read DMA control block */
8187 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8188 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8189
8190 /* Write DMA control block */
8191 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8192 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8193
8194 /* DMA completion block */
8195 printk("DEBUG: DMAC_MODE[%08x]\n",
8196 tr32(DMAC_MODE));
8197
8198 /* GRC block */
8199 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8200 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8201 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8202 tr32(GRC_LOCAL_CTRL));
8203
8204 /* TG3_BDINFOs */
8205 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8206 tr32(RCVDBDI_JUMBO_BD + 0x0),
8207 tr32(RCVDBDI_JUMBO_BD + 0x4),
8208 tr32(RCVDBDI_JUMBO_BD + 0x8),
8209 tr32(RCVDBDI_JUMBO_BD + 0xc));
8210 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8211 tr32(RCVDBDI_STD_BD + 0x0),
8212 tr32(RCVDBDI_STD_BD + 0x4),
8213 tr32(RCVDBDI_STD_BD + 0x8),
8214 tr32(RCVDBDI_STD_BD + 0xc));
8215 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8216 tr32(RCVDBDI_MINI_BD + 0x0),
8217 tr32(RCVDBDI_MINI_BD + 0x4),
8218 tr32(RCVDBDI_MINI_BD + 0x8),
8219 tr32(RCVDBDI_MINI_BD + 0xc));
8220
8221 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8222 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8223 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8224 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8225 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8226 val32, val32_2, val32_3, val32_4);
8227
8228 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8229 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8230 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8231 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8232 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8233 val32, val32_2, val32_3, val32_4);
8234
8235 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8236 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8237 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8238 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8239 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8240 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8241 val32, val32_2, val32_3, val32_4, val32_5);
8242
8243 /* SW status block */
8244 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8245 tp->hw_status->status,
8246 tp->hw_status->status_tag,
8247 tp->hw_status->rx_jumbo_consumer,
8248 tp->hw_status->rx_consumer,
8249 tp->hw_status->rx_mini_consumer,
8250 tp->hw_status->idx[0].rx_producer,
8251 tp->hw_status->idx[0].tx_consumer);
8252
8253 /* SW statistics block */
8254 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8255 ((u32 *)tp->hw_stats)[0],
8256 ((u32 *)tp->hw_stats)[1],
8257 ((u32 *)tp->hw_stats)[2],
8258 ((u32 *)tp->hw_stats)[3]);
8259
8260 /* Mailboxes */
8261 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8262 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8263 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8264 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8265 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8266
8267 /* NIC side send descriptors. */
8268 for (i = 0; i < 6; i++) {
8269 unsigned long txd;
8270
8271 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8272 + (i * sizeof(struct tg3_tx_buffer_desc));
8273 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8274 i,
8275 readl(txd + 0x0), readl(txd + 0x4),
8276 readl(txd + 0x8), readl(txd + 0xc));
8277 }
8278
8279 /* NIC side RX descriptors. */
8280 for (i = 0; i < 6; i++) {
8281 unsigned long rxd;
8282
8283 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8284 + (i * sizeof(struct tg3_rx_buffer_desc));
8285 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8286 i,
8287 readl(rxd + 0x0), readl(rxd + 0x4),
8288 readl(rxd + 0x8), readl(rxd + 0xc));
8289 rxd += (4 * sizeof(u32));
8290 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8291 i,
8292 readl(rxd + 0x0), readl(rxd + 0x4),
8293 readl(rxd + 0x8), readl(rxd + 0xc));
8294 }
8295
8296 for (i = 0; i < 6; i++) {
8297 unsigned long rxd;
8298
8299 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8300 + (i * sizeof(struct tg3_rx_buffer_desc));
8301 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8302 i,
8303 readl(rxd + 0x0), readl(rxd + 0x4),
8304 readl(rxd + 0x8), readl(rxd + 0xc));
8305 rxd += (4 * sizeof(u32));
8306 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8307 i,
8308 readl(rxd + 0x0), readl(rxd + 0x4),
8309 readl(rxd + 0x8), readl(rxd + 0xc));
8310 }
8311}
8312#endif
8313
8314static struct net_device_stats *tg3_get_stats(struct net_device *);
8315static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8316
8317static int tg3_close(struct net_device *dev)
8318{
8319 struct tg3 *tp = netdev_priv(dev);
8320
8321 napi_disable(&tp->napi);
8322 cancel_work_sync(&tp->reset_task);
8323
8324 netif_stop_queue(dev);
8325
8326 del_timer_sync(&tp->timer);
8327
8328 tg3_full_lock(tp, 1);
8329#if 0
8330 tg3_dump_state(tp);
8331#endif
8332
8333 tg3_disable_ints(tp);
8334
8335 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8336 tg3_free_rings(tp);
8337 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8338
8339 tg3_full_unlock(tp);
8340
8341 free_irq(tp->pdev->irq, dev);
8342 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8343 pci_disable_msi(tp->pdev);
8344 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8345 }
8346
8347 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8348 sizeof(tp->net_stats_prev));
8349 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8350 sizeof(tp->estats_prev));
8351
8352 tg3_free_consistent(tp);
8353
8354 tg3_set_power_state(tp, PCI_D3hot);
8355
8356 netif_carrier_off(tp->dev);
8357
8358 return 0;
8359}
8360
8361static inline unsigned long get_stat64(tg3_stat64_t *val)
8362{
8363 unsigned long ret;
8364
8365#if (BITS_PER_LONG == 32)
8366 ret = val->low;
8367#else
8368 ret = ((u64)val->high << 32) | ((u64)val->low);
8369#endif
8370 return ret;
8371}
8372
8373static unsigned long calc_crc_errors(struct tg3 *tp)
8374{
8375 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8376
8377 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8378 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8379 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8380 u32 val;
8381
8382 spin_lock_bh(&tp->lock);
8383 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8384 tg3_writephy(tp, MII_TG3_TEST1,
8385 val | MII_TG3_TEST1_CRC_EN);
8386 tg3_readphy(tp, 0x14, &val);
8387 } else
8388 val = 0;
8389 spin_unlock_bh(&tp->lock);
8390
8391 tp->phy_crc_errors += val;
8392
8393 return tp->phy_crc_errors;
8394 }
8395
8396 return get_stat64(&hw_stats->rx_fcs_errors);
8397}
8398
8399#define ESTAT_ADD(member) \
8400 estats->member = old_estats->member + \
8401 get_stat64(&hw_stats->member)
8402
8403static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8404{
8405 struct tg3_ethtool_stats *estats = &tp->estats;
8406 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8407 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8408
8409 if (!hw_stats)
8410 return old_estats;
8411
8412 ESTAT_ADD(rx_octets);
8413 ESTAT_ADD(rx_fragments);
8414 ESTAT_ADD(rx_ucast_packets);
8415 ESTAT_ADD(rx_mcast_packets);
8416 ESTAT_ADD(rx_bcast_packets);
8417 ESTAT_ADD(rx_fcs_errors);
8418 ESTAT_ADD(rx_align_errors);
8419 ESTAT_ADD(rx_xon_pause_rcvd);
8420 ESTAT_ADD(rx_xoff_pause_rcvd);
8421 ESTAT_ADD(rx_mac_ctrl_rcvd);
8422 ESTAT_ADD(rx_xoff_entered);
8423 ESTAT_ADD(rx_frame_too_long_errors);
8424 ESTAT_ADD(rx_jabbers);
8425 ESTAT_ADD(rx_undersize_packets);
8426 ESTAT_ADD(rx_in_length_errors);
8427 ESTAT_ADD(rx_out_length_errors);
8428 ESTAT_ADD(rx_64_or_less_octet_packets);
8429 ESTAT_ADD(rx_65_to_127_octet_packets);
8430 ESTAT_ADD(rx_128_to_255_octet_packets);
8431 ESTAT_ADD(rx_256_to_511_octet_packets);
8432 ESTAT_ADD(rx_512_to_1023_octet_packets);
8433 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8434 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8435 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8436 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8437 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8438
8439 ESTAT_ADD(tx_octets);
8440 ESTAT_ADD(tx_collisions);
8441 ESTAT_ADD(tx_xon_sent);
8442 ESTAT_ADD(tx_xoff_sent);
8443 ESTAT_ADD(tx_flow_control);
8444 ESTAT_ADD(tx_mac_errors);
8445 ESTAT_ADD(tx_single_collisions);
8446 ESTAT_ADD(tx_mult_collisions);
8447 ESTAT_ADD(tx_deferred);
8448 ESTAT_ADD(tx_excessive_collisions);
8449 ESTAT_ADD(tx_late_collisions);
8450 ESTAT_ADD(tx_collide_2times);
8451 ESTAT_ADD(tx_collide_3times);
8452 ESTAT_ADD(tx_collide_4times);
8453 ESTAT_ADD(tx_collide_5times);
8454 ESTAT_ADD(tx_collide_6times);
8455 ESTAT_ADD(tx_collide_7times);
8456 ESTAT_ADD(tx_collide_8times);
8457 ESTAT_ADD(tx_collide_9times);
8458 ESTAT_ADD(tx_collide_10times);
8459 ESTAT_ADD(tx_collide_11times);
8460 ESTAT_ADD(tx_collide_12times);
8461 ESTAT_ADD(tx_collide_13times);
8462 ESTAT_ADD(tx_collide_14times);
8463 ESTAT_ADD(tx_collide_15times);
8464 ESTAT_ADD(tx_ucast_packets);
8465 ESTAT_ADD(tx_mcast_packets);
8466 ESTAT_ADD(tx_bcast_packets);
8467 ESTAT_ADD(tx_carrier_sense_errors);
8468 ESTAT_ADD(tx_discards);
8469 ESTAT_ADD(tx_errors);
8470
8471 ESTAT_ADD(dma_writeq_full);
8472 ESTAT_ADD(dma_write_prioq_full);
8473 ESTAT_ADD(rxbds_empty);
8474 ESTAT_ADD(rx_discards);
8475 ESTAT_ADD(rx_errors);
8476 ESTAT_ADD(rx_threshold_hit);
8477
8478 ESTAT_ADD(dma_readq_full);
8479 ESTAT_ADD(dma_read_prioq_full);
8480 ESTAT_ADD(tx_comp_queue_full);
8481
8482 ESTAT_ADD(ring_set_send_prod_index);
8483 ESTAT_ADD(ring_status_update);
8484 ESTAT_ADD(nic_irqs);
8485 ESTAT_ADD(nic_avoided_irqs);
8486 ESTAT_ADD(nic_tx_threshold_hit);
8487
8488 return estats;
8489}
8490
8491static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8492{
8493 struct tg3 *tp = netdev_priv(dev);
8494 struct net_device_stats *stats = &tp->net_stats;
8495 struct net_device_stats *old_stats = &tp->net_stats_prev;
8496 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8497
8498 if (!hw_stats)
8499 return old_stats;
8500
8501 stats->rx_packets = old_stats->rx_packets +
8502 get_stat64(&hw_stats->rx_ucast_packets) +
8503 get_stat64(&hw_stats->rx_mcast_packets) +
8504 get_stat64(&hw_stats->rx_bcast_packets);
8505
8506 stats->tx_packets = old_stats->tx_packets +
8507 get_stat64(&hw_stats->tx_ucast_packets) +
8508 get_stat64(&hw_stats->tx_mcast_packets) +
8509 get_stat64(&hw_stats->tx_bcast_packets);
8510
8511 stats->rx_bytes = old_stats->rx_bytes +
8512 get_stat64(&hw_stats->rx_octets);
8513 stats->tx_bytes = old_stats->tx_bytes +
8514 get_stat64(&hw_stats->tx_octets);
8515
8516 stats->rx_errors = old_stats->rx_errors +
8517 get_stat64(&hw_stats->rx_errors);
8518 stats->tx_errors = old_stats->tx_errors +
8519 get_stat64(&hw_stats->tx_errors) +
8520 get_stat64(&hw_stats->tx_mac_errors) +
8521 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8522 get_stat64(&hw_stats->tx_discards);
8523
8524 stats->multicast = old_stats->multicast +
8525 get_stat64(&hw_stats->rx_mcast_packets);
8526 stats->collisions = old_stats->collisions +
8527 get_stat64(&hw_stats->tx_collisions);
8528
8529 stats->rx_length_errors = old_stats->rx_length_errors +
8530 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8531 get_stat64(&hw_stats->rx_undersize_packets);
8532
8533 stats->rx_over_errors = old_stats->rx_over_errors +
8534 get_stat64(&hw_stats->rxbds_empty);
8535 stats->rx_frame_errors = old_stats->rx_frame_errors +
8536 get_stat64(&hw_stats->rx_align_errors);
8537 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8538 get_stat64(&hw_stats->tx_discards);
8539 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8540 get_stat64(&hw_stats->tx_carrier_sense_errors);
8541
8542 stats->rx_crc_errors = old_stats->rx_crc_errors +
8543 calc_crc_errors(tp);
8544
8545 stats->rx_missed_errors = old_stats->rx_missed_errors +
8546 get_stat64(&hw_stats->rx_discards);
8547
8548 return stats;
8549}
8550
8551static inline u32 calc_crc(unsigned char *buf, int len)
8552{
8553 u32 reg;
8554 u32 tmp;
8555 int j, k;
8556
8557 reg = 0xffffffff;
8558
8559 for (j = 0; j < len; j++) {
8560 reg ^= buf[j];
8561
8562 for (k = 0; k < 8; k++) {
8563 tmp = reg & 0x01;
8564
8565 reg >>= 1;
8566
8567 if (tmp) {
8568 reg ^= 0xedb88320;
8569 }
8570 }
8571 }
8572
8573 return ~reg;
8574}
8575
8576static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8577{
8578 /* accept or reject all multicast frames */
8579 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8580 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8581 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8582 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8583}
8584
8585static void __tg3_set_rx_mode(struct net_device *dev)
8586{
8587 struct tg3 *tp = netdev_priv(dev);
8588 u32 rx_mode;
8589
8590 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8591 RX_MODE_KEEP_VLAN_TAG);
8592
8593 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8594 * flag clear.
8595 */
8596#if TG3_VLAN_TAG_USED
8597 if (!tp->vlgrp &&
8598 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8599 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8600#else
8601 /* By definition, VLAN is disabled always in this
8602 * case.
8603 */
8604 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8605 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8606#endif
8607
8608 if (dev->flags & IFF_PROMISC) {
8609 /* Promiscuous mode. */
8610 rx_mode |= RX_MODE_PROMISC;
8611 } else if (dev->flags & IFF_ALLMULTI) {
8612 /* Accept all multicast. */
8613 tg3_set_multi (tp, 1);
8614 } else if (dev->mc_count < 1) {
8615 /* Reject all multicast. */
8616 tg3_set_multi (tp, 0);
8617 } else {
8618 /* Accept one or more multicast(s). */
8619 struct dev_mc_list *mclist;
8620 unsigned int i;
8621 u32 mc_filter[4] = { 0, };
8622 u32 regidx;
8623 u32 bit;
8624 u32 crc;
8625
8626 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8627 i++, mclist = mclist->next) {
8628
8629 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8630 bit = ~crc & 0x7f;
8631 regidx = (bit & 0x60) >> 5;
8632 bit &= 0x1f;
8633 mc_filter[regidx] |= (1 << bit);
8634 }
8635
8636 tw32(MAC_HASH_REG_0, mc_filter[0]);
8637 tw32(MAC_HASH_REG_1, mc_filter[1]);
8638 tw32(MAC_HASH_REG_2, mc_filter[2]);
8639 tw32(MAC_HASH_REG_3, mc_filter[3]);
8640 }
8641
8642 if (rx_mode != tp->rx_mode) {
8643 tp->rx_mode = rx_mode;
8644 tw32_f(MAC_RX_MODE, rx_mode);
8645 udelay(10);
8646 }
8647}
8648
8649static void tg3_set_rx_mode(struct net_device *dev)
8650{
8651 struct tg3 *tp = netdev_priv(dev);
8652
8653 if (!netif_running(dev))
8654 return;
8655
8656 tg3_full_lock(tp, 0);
8657 __tg3_set_rx_mode(dev);
8658 tg3_full_unlock(tp);
8659}
8660
8661#define TG3_REGDUMP_LEN (32 * 1024)
8662
8663static int tg3_get_regs_len(struct net_device *dev)
8664{
8665 return TG3_REGDUMP_LEN;
8666}
8667
8668static void tg3_get_regs(struct net_device *dev,
8669 struct ethtool_regs *regs, void *_p)
8670{
8671 u32 *p = _p;
8672 struct tg3 *tp = netdev_priv(dev);
8673 u8 *orig_p = _p;
8674 int i;
8675
8676 regs->version = 0;
8677
8678 memset(p, 0, TG3_REGDUMP_LEN);
8679
8680 if (tp->link_config.phy_is_low_power)
8681 return;
8682
8683 tg3_full_lock(tp, 0);
8684
8685#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8686#define GET_REG32_LOOP(base,len) \
8687do { p = (u32 *)(orig_p + (base)); \
8688 for (i = 0; i < len; i += 4) \
8689 __GET_REG32((base) + i); \
8690} while (0)
8691#define GET_REG32_1(reg) \
8692do { p = (u32 *)(orig_p + (reg)); \
8693 __GET_REG32((reg)); \
8694} while (0)
8695
8696 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8697 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8698 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8699 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8700 GET_REG32_1(SNDDATAC_MODE);
8701 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8702 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8703 GET_REG32_1(SNDBDC_MODE);
8704 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8705 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8706 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8707 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8708 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8709 GET_REG32_1(RCVDCC_MODE);
8710 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8711 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8712 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8713 GET_REG32_1(MBFREE_MODE);
8714 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8715 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8716 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8717 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8718 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8719 GET_REG32_1(RX_CPU_MODE);
8720 GET_REG32_1(RX_CPU_STATE);
8721 GET_REG32_1(RX_CPU_PGMCTR);
8722 GET_REG32_1(RX_CPU_HWBKPT);
8723 GET_REG32_1(TX_CPU_MODE);
8724 GET_REG32_1(TX_CPU_STATE);
8725 GET_REG32_1(TX_CPU_PGMCTR);
8726 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8727 GET_REG32_LOOP(FTQ_RESET, 0x120);
8728 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8729 GET_REG32_1(DMAC_MODE);
8730 GET_REG32_LOOP(GRC_MODE, 0x4c);
8731 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8732 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8733
8734#undef __GET_REG32
8735#undef GET_REG32_LOOP
8736#undef GET_REG32_1
8737
8738 tg3_full_unlock(tp);
8739}
8740
8741static int tg3_get_eeprom_len(struct net_device *dev)
8742{
8743 struct tg3 *tp = netdev_priv(dev);
8744
8745 return tp->nvram_size;
8746}
8747
8748static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8749static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8750static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8751
8752static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8753{
8754 struct tg3 *tp = netdev_priv(dev);
8755 int ret;
8756 u8 *pd;
8757 u32 i, offset, len, b_offset, b_count;
8758 __le32 val;
8759
8760 if (tp->link_config.phy_is_low_power)
8761 return -EAGAIN;
8762
8763 offset = eeprom->offset;
8764 len = eeprom->len;
8765 eeprom->len = 0;
8766
8767 eeprom->magic = TG3_EEPROM_MAGIC;
8768
8769 if (offset & 3) {
8770 /* adjustments to start on required 4 byte boundary */
8771 b_offset = offset & 3;
8772 b_count = 4 - b_offset;
8773 if (b_count > len) {
8774 /* i.e. offset=1 len=2 */
8775 b_count = len;
8776 }
8777 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8778 if (ret)
8779 return ret;
8780 memcpy(data, ((char*)&val) + b_offset, b_count);
8781 len -= b_count;
8782 offset += b_count;
8783 eeprom->len += b_count;
8784 }
8785
8786 /* read bytes upto the last 4 byte boundary */
8787 pd = &data[eeprom->len];
8788 for (i = 0; i < (len - (len & 3)); i += 4) {
8789 ret = tg3_nvram_read_le(tp, offset + i, &val);
8790 if (ret) {
8791 eeprom->len += i;
8792 return ret;
8793 }
8794 memcpy(pd + i, &val, 4);
8795 }
8796 eeprom->len += i;
8797
8798 if (len & 3) {
8799 /* read last bytes not ending on 4 byte boundary */
8800 pd = &data[eeprom->len];
8801 b_count = len & 3;
8802 b_offset = offset + len - b_count;
8803 ret = tg3_nvram_read_le(tp, b_offset, &val);
8804 if (ret)
8805 return ret;
8806 memcpy(pd, &val, b_count);
8807 eeprom->len += b_count;
8808 }
8809 return 0;
8810}
8811
8812static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8813
8814static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8815{
8816 struct tg3 *tp = netdev_priv(dev);
8817 int ret;
8818 u32 offset, len, b_offset, odd_len;
8819 u8 *buf;
8820 __le32 start, end;
8821
8822 if (tp->link_config.phy_is_low_power)
8823 return -EAGAIN;
8824
8825 if (eeprom->magic != TG3_EEPROM_MAGIC)
8826 return -EINVAL;
8827
8828 offset = eeprom->offset;
8829 len = eeprom->len;
8830
8831 if ((b_offset = (offset & 3))) {
8832 /* adjustments to start on required 4 byte boundary */
8833 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8834 if (ret)
8835 return ret;
8836 len += b_offset;
8837 offset &= ~3;
8838 if (len < 4)
8839 len = 4;
8840 }
8841
8842 odd_len = 0;
8843 if (len & 3) {
8844 /* adjustments to end on required 4 byte boundary */
8845 odd_len = 1;
8846 len = (len + 3) & ~3;
8847 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8848 if (ret)
8849 return ret;
8850 }
8851
8852 buf = data;
8853 if (b_offset || odd_len) {
8854 buf = kmalloc(len, GFP_KERNEL);
8855 if (!buf)
8856 return -ENOMEM;
8857 if (b_offset)
8858 memcpy(buf, &start, 4);
8859 if (odd_len)
8860 memcpy(buf+len-4, &end, 4);
8861 memcpy(buf + b_offset, data, eeprom->len);
8862 }
8863
8864 ret = tg3_nvram_write_block(tp, offset, len, buf);
8865
8866 if (buf != data)
8867 kfree(buf);
8868
8869 return ret;
8870}
8871
8872static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8873{
8874 struct tg3 *tp = netdev_priv(dev);
8875
8876 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8877 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8878 return -EAGAIN;
8879 return phy_ethtool_gset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8880 }
8881
8882 cmd->supported = (SUPPORTED_Autoneg);
8883
8884 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8885 cmd->supported |= (SUPPORTED_1000baseT_Half |
8886 SUPPORTED_1000baseT_Full);
8887
8888 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8889 cmd->supported |= (SUPPORTED_100baseT_Half |
8890 SUPPORTED_100baseT_Full |
8891 SUPPORTED_10baseT_Half |
8892 SUPPORTED_10baseT_Full |
8893 SUPPORTED_TP);
8894 cmd->port = PORT_TP;
8895 } else {
8896 cmd->supported |= SUPPORTED_FIBRE;
8897 cmd->port = PORT_FIBRE;
8898 }
8899
8900 cmd->advertising = tp->link_config.advertising;
8901 if (netif_running(dev)) {
8902 cmd->speed = tp->link_config.active_speed;
8903 cmd->duplex = tp->link_config.active_duplex;
8904 }
8905 cmd->phy_address = PHY_ADDR;
8906 cmd->transceiver = 0;
8907 cmd->autoneg = tp->link_config.autoneg;
8908 cmd->maxtxpkt = 0;
8909 cmd->maxrxpkt = 0;
8910 return 0;
8911}
8912
8913static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8914{
8915 struct tg3 *tp = netdev_priv(dev);
8916
8917 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8918 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8919 return -EAGAIN;
8920 return phy_ethtool_sset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8921 }
8922
8923 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8924 /* These are the only valid advertisement bits allowed. */
8925 if (cmd->autoneg == AUTONEG_ENABLE &&
8926 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8927 ADVERTISED_1000baseT_Full |
8928 ADVERTISED_Autoneg |
8929 ADVERTISED_FIBRE)))
8930 return -EINVAL;
8931 /* Fiber can only do SPEED_1000. */
8932 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8933 (cmd->speed != SPEED_1000))
8934 return -EINVAL;
8935 /* Copper cannot force SPEED_1000. */
8936 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8937 (cmd->speed == SPEED_1000))
8938 return -EINVAL;
8939 else if ((cmd->speed == SPEED_1000) &&
8940 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8941 return -EINVAL;
8942
8943 tg3_full_lock(tp, 0);
8944
8945 tp->link_config.autoneg = cmd->autoneg;
8946 if (cmd->autoneg == AUTONEG_ENABLE) {
8947 tp->link_config.advertising = (cmd->advertising |
8948 ADVERTISED_Autoneg);
8949 tp->link_config.speed = SPEED_INVALID;
8950 tp->link_config.duplex = DUPLEX_INVALID;
8951 } else {
8952 tp->link_config.advertising = 0;
8953 tp->link_config.speed = cmd->speed;
8954 tp->link_config.duplex = cmd->duplex;
8955 }
8956
8957 tp->link_config.orig_speed = tp->link_config.speed;
8958 tp->link_config.orig_duplex = tp->link_config.duplex;
8959 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8960
8961 if (netif_running(dev))
8962 tg3_setup_phy(tp, 1);
8963
8964 tg3_full_unlock(tp);
8965
8966 return 0;
8967}
8968
8969static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8970{
8971 struct tg3 *tp = netdev_priv(dev);
8972
8973 strcpy(info->driver, DRV_MODULE_NAME);
8974 strcpy(info->version, DRV_MODULE_VERSION);
8975 strcpy(info->fw_version, tp->fw_ver);
8976 strcpy(info->bus_info, pci_name(tp->pdev));
8977}
8978
8979static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8980{
8981 struct tg3 *tp = netdev_priv(dev);
8982
8983 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8984 wol->supported = WAKE_MAGIC;
8985 else
8986 wol->supported = 0;
8987 wol->wolopts = 0;
8988 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8989 wol->wolopts = WAKE_MAGIC;
8990 memset(&wol->sopass, 0, sizeof(wol->sopass));
8991}
8992
8993static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8994{
8995 struct tg3 *tp = netdev_priv(dev);
8996
8997 if (wol->wolopts & ~WAKE_MAGIC)
8998 return -EINVAL;
8999 if ((wol->wolopts & WAKE_MAGIC) &&
9000 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
9001 return -EINVAL;
9002
9003 spin_lock_bh(&tp->lock);
9004 if (wol->wolopts & WAKE_MAGIC)
9005 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9006 else
9007 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9008 spin_unlock_bh(&tp->lock);
9009
9010 return 0;
9011}
9012
9013static u32 tg3_get_msglevel(struct net_device *dev)
9014{
9015 struct tg3 *tp = netdev_priv(dev);
9016 return tp->msg_enable;
9017}
9018
9019static void tg3_set_msglevel(struct net_device *dev, u32 value)
9020{
9021 struct tg3 *tp = netdev_priv(dev);
9022 tp->msg_enable = value;
9023}
9024
9025static int tg3_set_tso(struct net_device *dev, u32 value)
9026{
9027 struct tg3 *tp = netdev_priv(dev);
9028
9029 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9030 if (value)
9031 return -EINVAL;
9032 return 0;
9033 }
9034 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
9035 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9036 if (value) {
9037 dev->features |= NETIF_F_TSO6;
9038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9039 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9040 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9042 dev->features |= NETIF_F_TSO_ECN;
9043 } else
9044 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9045 }
9046 return ethtool_op_set_tso(dev, value);
9047}
9048
9049static int tg3_nway_reset(struct net_device *dev)
9050{
9051 struct tg3 *tp = netdev_priv(dev);
9052 int r;
9053
9054 if (!netif_running(dev))
9055 return -EAGAIN;
9056
9057 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9058 return -EINVAL;
9059
9060 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9061 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9062 return -EAGAIN;
9063 r = phy_start_aneg(tp->mdio_bus.phy_map[PHY_ADDR]);
9064 } else {
9065 u32 bmcr;
9066
9067 spin_lock_bh(&tp->lock);
9068 r = -EINVAL;
9069 tg3_readphy(tp, MII_BMCR, &bmcr);
9070 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9071 ((bmcr & BMCR_ANENABLE) ||
9072 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9073 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9074 BMCR_ANENABLE);
9075 r = 0;
9076 }
9077 spin_unlock_bh(&tp->lock);
9078 }
9079
9080 return r;
9081}
9082
9083static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9084{
9085 struct tg3 *tp = netdev_priv(dev);
9086
9087 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9088 ering->rx_mini_max_pending = 0;
9089 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9090 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9091 else
9092 ering->rx_jumbo_max_pending = 0;
9093
9094 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9095
9096 ering->rx_pending = tp->rx_pending;
9097 ering->rx_mini_pending = 0;
9098 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9099 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9100 else
9101 ering->rx_jumbo_pending = 0;
9102
9103 ering->tx_pending = tp->tx_pending;
9104}
9105
9106static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9107{
9108 struct tg3 *tp = netdev_priv(dev);
9109 int irq_sync = 0, err = 0;
9110
9111 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9112 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9113 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9114 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9115 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9116 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9117 return -EINVAL;
9118
9119 if (netif_running(dev)) {
9120 tg3_phy_stop(tp);
9121 tg3_netif_stop(tp);
9122 irq_sync = 1;
9123 }
9124
9125 tg3_full_lock(tp, irq_sync);
9126
9127 tp->rx_pending = ering->rx_pending;
9128
9129 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9130 tp->rx_pending > 63)
9131 tp->rx_pending = 63;
9132 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9133 tp->tx_pending = ering->tx_pending;
9134
9135 if (netif_running(dev)) {
9136 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9137 err = tg3_restart_hw(tp, 1);
9138 if (!err)
9139 tg3_netif_start(tp);
9140 }
9141
9142 tg3_full_unlock(tp);
9143
9144 if (irq_sync && !err)
9145 tg3_phy_start(tp);
9146
9147 return err;
9148}
9149
9150static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9151{
9152 struct tg3 *tp = netdev_priv(dev);
9153
9154 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9155
9156 if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
9157 epause->rx_pause = 1;
9158 else
9159 epause->rx_pause = 0;
9160
9161 if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
9162 epause->tx_pause = 1;
9163 else
9164 epause->tx_pause = 0;
9165}
9166
9167static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9168{
9169 struct tg3 *tp = netdev_priv(dev);
9170 int err = 0;
9171
9172 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9173 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9174 return -EAGAIN;
9175
9176 if (epause->autoneg) {
9177 u32 newadv;
9178 struct phy_device *phydev;
9179
9180 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
9181
9182 if (epause->rx_pause) {
9183 if (epause->tx_pause)
9184 newadv = ADVERTISED_Pause;
9185 else
9186 newadv = ADVERTISED_Pause |
9187 ADVERTISED_Asym_Pause;
9188 } else if (epause->tx_pause) {
9189 newadv = ADVERTISED_Asym_Pause;
9190 } else
9191 newadv = 0;
9192
9193 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9194 u32 oldadv = phydev->advertising &
9195 (ADVERTISED_Pause |
9196 ADVERTISED_Asym_Pause);
9197 if (oldadv != newadv) {
9198 phydev->advertising &=
9199 ~(ADVERTISED_Pause |
9200 ADVERTISED_Asym_Pause);
9201 phydev->advertising |= newadv;
9202 err = phy_start_aneg(phydev);
9203 }
9204 } else {
9205 tp->link_config.advertising &=
9206 ~(ADVERTISED_Pause |
9207 ADVERTISED_Asym_Pause);
9208 tp->link_config.advertising |= newadv;
9209 }
9210 } else {
9211 if (epause->rx_pause)
9212 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9213 else
9214 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9215
9216 if (epause->tx_pause)
9217 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9218 else
9219 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9220
9221 if (netif_running(dev))
9222 tg3_setup_flow_control(tp, 0, 0);
9223 }
9224 } else {
9225 int irq_sync = 0;
9226
9227 if (netif_running(dev)) {
9228 tg3_netif_stop(tp);
9229 irq_sync = 1;
9230 }
9231
9232 tg3_full_lock(tp, irq_sync);
9233
9234 if (epause->autoneg)
9235 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9236 else
9237 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9238 if (epause->rx_pause)
9239 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9240 else
9241 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9242 if (epause->tx_pause)
9243 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9244 else
9245 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9246
9247 if (netif_running(dev)) {
9248 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9249 err = tg3_restart_hw(tp, 1);
9250 if (!err)
9251 tg3_netif_start(tp);
9252 }
9253
9254 tg3_full_unlock(tp);
9255 }
9256
9257 return err;
9258}
9259
9260static u32 tg3_get_rx_csum(struct net_device *dev)
9261{
9262 struct tg3 *tp = netdev_priv(dev);
9263 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9264}
9265
9266static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9267{
9268 struct tg3 *tp = netdev_priv(dev);
9269
9270 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9271 if (data != 0)
9272 return -EINVAL;
9273 return 0;
9274 }
9275
9276 spin_lock_bh(&tp->lock);
9277 if (data)
9278 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9279 else
9280 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9281 spin_unlock_bh(&tp->lock);
9282
9283 return 0;
9284}
9285
9286static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9287{
9288 struct tg3 *tp = netdev_priv(dev);
9289
9290 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9291 if (data != 0)
9292 return -EINVAL;
9293 return 0;
9294 }
9295
9296 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9297 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9298 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9299 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9300 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9301 ethtool_op_set_tx_ipv6_csum(dev, data);
9302 else
9303 ethtool_op_set_tx_csum(dev, data);
9304
9305 return 0;
9306}
9307
9308static int tg3_get_sset_count (struct net_device *dev, int sset)
9309{
9310 switch (sset) {
9311 case ETH_SS_TEST:
9312 return TG3_NUM_TEST;
9313 case ETH_SS_STATS:
9314 return TG3_NUM_STATS;
9315 default:
9316 return -EOPNOTSUPP;
9317 }
9318}
9319
9320static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9321{
9322 switch (stringset) {
9323 case ETH_SS_STATS:
9324 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9325 break;
9326 case ETH_SS_TEST:
9327 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9328 break;
9329 default:
9330 WARN_ON(1); /* we need a WARN() */
9331 break;
9332 }
9333}
9334
9335static int tg3_phys_id(struct net_device *dev, u32 data)
9336{
9337 struct tg3 *tp = netdev_priv(dev);
9338 int i;
9339
9340 if (!netif_running(tp->dev))
9341 return -EAGAIN;
9342
9343 if (data == 0)
9344 data = UINT_MAX / 2;
9345
9346 for (i = 0; i < (data * 2); i++) {
9347 if ((i % 2) == 0)
9348 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9349 LED_CTRL_1000MBPS_ON |
9350 LED_CTRL_100MBPS_ON |
9351 LED_CTRL_10MBPS_ON |
9352 LED_CTRL_TRAFFIC_OVERRIDE |
9353 LED_CTRL_TRAFFIC_BLINK |
9354 LED_CTRL_TRAFFIC_LED);
9355
9356 else
9357 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9358 LED_CTRL_TRAFFIC_OVERRIDE);
9359
9360 if (msleep_interruptible(500))
9361 break;
9362 }
9363 tw32(MAC_LED_CTRL, tp->led_ctrl);
9364 return 0;
9365}
9366
9367static void tg3_get_ethtool_stats (struct net_device *dev,
9368 struct ethtool_stats *estats, u64 *tmp_stats)
9369{
9370 struct tg3 *tp = netdev_priv(dev);
9371 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9372}
9373
9374#define NVRAM_TEST_SIZE 0x100
9375#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9376#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9377#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9378#define NVRAM_SELFBOOT_HW_SIZE 0x20
9379#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9380
9381static int tg3_test_nvram(struct tg3 *tp)
9382{
9383 u32 csum, magic;
9384 __le32 *buf;
9385 int i, j, k, err = 0, size;
9386
9387 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9388 return -EIO;
9389
9390 if (magic == TG3_EEPROM_MAGIC)
9391 size = NVRAM_TEST_SIZE;
9392 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9393 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9394 TG3_EEPROM_SB_FORMAT_1) {
9395 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9396 case TG3_EEPROM_SB_REVISION_0:
9397 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9398 break;
9399 case TG3_EEPROM_SB_REVISION_2:
9400 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9401 break;
9402 case TG3_EEPROM_SB_REVISION_3:
9403 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9404 break;
9405 default:
9406 return 0;
9407 }
9408 } else
9409 return 0;
9410 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9411 size = NVRAM_SELFBOOT_HW_SIZE;
9412 else
9413 return -EIO;
9414
9415 buf = kmalloc(size, GFP_KERNEL);
9416 if (buf == NULL)
9417 return -ENOMEM;
9418
9419 err = -EIO;
9420 for (i = 0, j = 0; i < size; i += 4, j++) {
9421 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9422 break;
9423 }
9424 if (i < size)
9425 goto out;
9426
9427 /* Selfboot format */
9428 magic = swab32(le32_to_cpu(buf[0]));
9429 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9430 TG3_EEPROM_MAGIC_FW) {
9431 u8 *buf8 = (u8 *) buf, csum8 = 0;
9432
9433 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9434 TG3_EEPROM_SB_REVISION_2) {
9435 /* For rev 2, the csum doesn't include the MBA. */
9436 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9437 csum8 += buf8[i];
9438 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9439 csum8 += buf8[i];
9440 } else {
9441 for (i = 0; i < size; i++)
9442 csum8 += buf8[i];
9443 }
9444
9445 if (csum8 == 0) {
9446 err = 0;
9447 goto out;
9448 }
9449
9450 err = -EIO;
9451 goto out;
9452 }
9453
9454 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9455 TG3_EEPROM_MAGIC_HW) {
9456 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9457 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9458 u8 *buf8 = (u8 *) buf;
9459
9460 /* Separate the parity bits and the data bytes. */
9461 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9462 if ((i == 0) || (i == 8)) {
9463 int l;
9464 u8 msk;
9465
9466 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9467 parity[k++] = buf8[i] & msk;
9468 i++;
9469 }
9470 else if (i == 16) {
9471 int l;
9472 u8 msk;
9473
9474 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9475 parity[k++] = buf8[i] & msk;
9476 i++;
9477
9478 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9479 parity[k++] = buf8[i] & msk;
9480 i++;
9481 }
9482 data[j++] = buf8[i];
9483 }
9484
9485 err = -EIO;
9486 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9487 u8 hw8 = hweight8(data[i]);
9488
9489 if ((hw8 & 0x1) && parity[i])
9490 goto out;
9491 else if (!(hw8 & 0x1) && !parity[i])
9492 goto out;
9493 }
9494 err = 0;
9495 goto out;
9496 }
9497
9498 /* Bootstrap checksum at offset 0x10 */
9499 csum = calc_crc((unsigned char *) buf, 0x10);
9500 if(csum != le32_to_cpu(buf[0x10/4]))
9501 goto out;
9502
9503 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9504 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9505 if (csum != le32_to_cpu(buf[0xfc/4]))
9506 goto out;
9507
9508 err = 0;
9509
9510out:
9511 kfree(buf);
9512 return err;
9513}
9514
9515#define TG3_SERDES_TIMEOUT_SEC 2
9516#define TG3_COPPER_TIMEOUT_SEC 6
9517
9518static int tg3_test_link(struct tg3 *tp)
9519{
9520 int i, max;
9521
9522 if (!netif_running(tp->dev))
9523 return -ENODEV;
9524
9525 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9526 max = TG3_SERDES_TIMEOUT_SEC;
9527 else
9528 max = TG3_COPPER_TIMEOUT_SEC;
9529
9530 for (i = 0; i < max; i++) {
9531 if (netif_carrier_ok(tp->dev))
9532 return 0;
9533
9534 if (msleep_interruptible(1000))
9535 break;
9536 }
9537
9538 return -EIO;
9539}
9540
9541/* Only test the commonly used registers */
9542static int tg3_test_registers(struct tg3 *tp)
9543{
9544 int i, is_5705, is_5750;
9545 u32 offset, read_mask, write_mask, val, save_val, read_val;
9546 static struct {
9547 u16 offset;
9548 u16 flags;
9549#define TG3_FL_5705 0x1
9550#define TG3_FL_NOT_5705 0x2
9551#define TG3_FL_NOT_5788 0x4
9552#define TG3_FL_NOT_5750 0x8
9553 u32 read_mask;
9554 u32 write_mask;
9555 } reg_tbl[] = {
9556 /* MAC Control Registers */
9557 { MAC_MODE, TG3_FL_NOT_5705,
9558 0x00000000, 0x00ef6f8c },
9559 { MAC_MODE, TG3_FL_5705,
9560 0x00000000, 0x01ef6b8c },
9561 { MAC_STATUS, TG3_FL_NOT_5705,
9562 0x03800107, 0x00000000 },
9563 { MAC_STATUS, TG3_FL_5705,
9564 0x03800100, 0x00000000 },
9565 { MAC_ADDR_0_HIGH, 0x0000,
9566 0x00000000, 0x0000ffff },
9567 { MAC_ADDR_0_LOW, 0x0000,
9568 0x00000000, 0xffffffff },
9569 { MAC_RX_MTU_SIZE, 0x0000,
9570 0x00000000, 0x0000ffff },
9571 { MAC_TX_MODE, 0x0000,
9572 0x00000000, 0x00000070 },
9573 { MAC_TX_LENGTHS, 0x0000,
9574 0x00000000, 0x00003fff },
9575 { MAC_RX_MODE, TG3_FL_NOT_5705,
9576 0x00000000, 0x000007fc },
9577 { MAC_RX_MODE, TG3_FL_5705,
9578 0x00000000, 0x000007dc },
9579 { MAC_HASH_REG_0, 0x0000,
9580 0x00000000, 0xffffffff },
9581 { MAC_HASH_REG_1, 0x0000,
9582 0x00000000, 0xffffffff },
9583 { MAC_HASH_REG_2, 0x0000,
9584 0x00000000, 0xffffffff },
9585 { MAC_HASH_REG_3, 0x0000,
9586 0x00000000, 0xffffffff },
9587
9588 /* Receive Data and Receive BD Initiator Control Registers. */
9589 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9590 0x00000000, 0xffffffff },
9591 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9592 0x00000000, 0xffffffff },
9593 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9594 0x00000000, 0x00000003 },
9595 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9596 0x00000000, 0xffffffff },
9597 { RCVDBDI_STD_BD+0, 0x0000,
9598 0x00000000, 0xffffffff },
9599 { RCVDBDI_STD_BD+4, 0x0000,
9600 0x00000000, 0xffffffff },
9601 { RCVDBDI_STD_BD+8, 0x0000,
9602 0x00000000, 0xffff0002 },
9603 { RCVDBDI_STD_BD+0xc, 0x0000,
9604 0x00000000, 0xffffffff },
9605
9606 /* Receive BD Initiator Control Registers. */
9607 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9608 0x00000000, 0xffffffff },
9609 { RCVBDI_STD_THRESH, TG3_FL_5705,
9610 0x00000000, 0x000003ff },
9611 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9612 0x00000000, 0xffffffff },
9613
9614 /* Host Coalescing Control Registers. */
9615 { HOSTCC_MODE, TG3_FL_NOT_5705,
9616 0x00000000, 0x00000004 },
9617 { HOSTCC_MODE, TG3_FL_5705,
9618 0x00000000, 0x000000f6 },
9619 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9620 0x00000000, 0xffffffff },
9621 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9622 0x00000000, 0x000003ff },
9623 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9624 0x00000000, 0xffffffff },
9625 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9626 0x00000000, 0x000003ff },
9627 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9628 0x00000000, 0xffffffff },
9629 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9630 0x00000000, 0x000000ff },
9631 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9632 0x00000000, 0xffffffff },
9633 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9634 0x00000000, 0x000000ff },
9635 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9636 0x00000000, 0xffffffff },
9637 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9638 0x00000000, 0xffffffff },
9639 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9640 0x00000000, 0xffffffff },
9641 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9642 0x00000000, 0x000000ff },
9643 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9644 0x00000000, 0xffffffff },
9645 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9646 0x00000000, 0x000000ff },
9647 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9648 0x00000000, 0xffffffff },
9649 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9650 0x00000000, 0xffffffff },
9651 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9652 0x00000000, 0xffffffff },
9653 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9654 0x00000000, 0xffffffff },
9655 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9656 0x00000000, 0xffffffff },
9657 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9658 0xffffffff, 0x00000000 },
9659 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9660 0xffffffff, 0x00000000 },
9661
9662 /* Buffer Manager Control Registers. */
9663 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9664 0x00000000, 0x007fff80 },
9665 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9666 0x00000000, 0x007fffff },
9667 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9668 0x00000000, 0x0000003f },
9669 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9670 0x00000000, 0x000001ff },
9671 { BUFMGR_MB_HIGH_WATER, 0x0000,
9672 0x00000000, 0x000001ff },
9673 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9674 0xffffffff, 0x00000000 },
9675 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9676 0xffffffff, 0x00000000 },
9677
9678 /* Mailbox Registers */
9679 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9680 0x00000000, 0x000001ff },
9681 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9682 0x00000000, 0x000001ff },
9683 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9684 0x00000000, 0x000007ff },
9685 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9686 0x00000000, 0x000001ff },
9687
9688 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9689 };
9690
9691 is_5705 = is_5750 = 0;
9692 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9693 is_5705 = 1;
9694 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9695 is_5750 = 1;
9696 }
9697
9698 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9699 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9700 continue;
9701
9702 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9703 continue;
9704
9705 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9706 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9707 continue;
9708
9709 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9710 continue;
9711
9712 offset = (u32) reg_tbl[i].offset;
9713 read_mask = reg_tbl[i].read_mask;
9714 write_mask = reg_tbl[i].write_mask;
9715
9716 /* Save the original register content */
9717 save_val = tr32(offset);
9718
9719 /* Determine the read-only value. */
9720 read_val = save_val & read_mask;
9721
9722 /* Write zero to the register, then make sure the read-only bits
9723 * are not changed and the read/write bits are all zeros.
9724 */
9725 tw32(offset, 0);
9726
9727 val = tr32(offset);
9728
9729 /* Test the read-only and read/write bits. */
9730 if (((val & read_mask) != read_val) || (val & write_mask))
9731 goto out;
9732
9733 /* Write ones to all the bits defined by RdMask and WrMask, then
9734 * make sure the read-only bits are not changed and the
9735 * read/write bits are all ones.
9736 */
9737 tw32(offset, read_mask | write_mask);
9738
9739 val = tr32(offset);
9740
9741 /* Test the read-only bits. */
9742 if ((val & read_mask) != read_val)
9743 goto out;
9744
9745 /* Test the read/write bits. */
9746 if ((val & write_mask) != write_mask)
9747 goto out;
9748
9749 tw32(offset, save_val);
9750 }
9751
9752 return 0;
9753
9754out:
9755 if (netif_msg_hw(tp))
9756 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9757 offset);
9758 tw32(offset, save_val);
9759 return -EIO;
9760}
9761
9762static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9763{
9764 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9765 int i;
9766 u32 j;
9767
9768 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9769 for (j = 0; j < len; j += 4) {
9770 u32 val;
9771
9772 tg3_write_mem(tp, offset + j, test_pattern[i]);
9773 tg3_read_mem(tp, offset + j, &val);
9774 if (val != test_pattern[i])
9775 return -EIO;
9776 }
9777 }
9778 return 0;
9779}
9780
9781static int tg3_test_memory(struct tg3 *tp)
9782{
9783 static struct mem_entry {
9784 u32 offset;
9785 u32 len;
9786 } mem_tbl_570x[] = {
9787 { 0x00000000, 0x00b50},
9788 { 0x00002000, 0x1c000},
9789 { 0xffffffff, 0x00000}
9790 }, mem_tbl_5705[] = {
9791 { 0x00000100, 0x0000c},
9792 { 0x00000200, 0x00008},
9793 { 0x00004000, 0x00800},
9794 { 0x00006000, 0x01000},
9795 { 0x00008000, 0x02000},
9796 { 0x00010000, 0x0e000},
9797 { 0xffffffff, 0x00000}
9798 }, mem_tbl_5755[] = {
9799 { 0x00000200, 0x00008},
9800 { 0x00004000, 0x00800},
9801 { 0x00006000, 0x00800},
9802 { 0x00008000, 0x02000},
9803 { 0x00010000, 0x0c000},
9804 { 0xffffffff, 0x00000}
9805 }, mem_tbl_5906[] = {
9806 { 0x00000200, 0x00008},
9807 { 0x00004000, 0x00400},
9808 { 0x00006000, 0x00400},
9809 { 0x00008000, 0x01000},
9810 { 0x00010000, 0x01000},
9811 { 0xffffffff, 0x00000}
9812 };
9813 struct mem_entry *mem_tbl;
9814 int err = 0;
9815 int i;
9816
9817 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9818 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9819 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9820 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9821 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9822 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9823 mem_tbl = mem_tbl_5755;
9824 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9825 mem_tbl = mem_tbl_5906;
9826 else
9827 mem_tbl = mem_tbl_5705;
9828 } else
9829 mem_tbl = mem_tbl_570x;
9830
9831 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9832 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9833 mem_tbl[i].len)) != 0)
9834 break;
9835 }
9836
9837 return err;
9838}
9839
9840#define TG3_MAC_LOOPBACK 0
9841#define TG3_PHY_LOOPBACK 1
9842
9843static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9844{
9845 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9846 u32 desc_idx;
9847 struct sk_buff *skb, *rx_skb;
9848 u8 *tx_data;
9849 dma_addr_t map;
9850 int num_pkts, tx_len, rx_len, i, err;
9851 struct tg3_rx_buffer_desc *desc;
9852
9853 if (loopback_mode == TG3_MAC_LOOPBACK) {
9854 /* HW errata - mac loopback fails in some cases on 5780.
9855 * Normal traffic and PHY loopback are not affected by
9856 * errata.
9857 */
9858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9859 return 0;
9860
9861 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9862 MAC_MODE_PORT_INT_LPBACK;
9863 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9864 mac_mode |= MAC_MODE_LINK_POLARITY;
9865 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9866 mac_mode |= MAC_MODE_PORT_MODE_MII;
9867 else
9868 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9869 tw32(MAC_MODE, mac_mode);
9870 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9871 u32 val;
9872
9873 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9874 u32 phytest;
9875
9876 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9877 u32 phy;
9878
9879 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9880 phytest | MII_TG3_EPHY_SHADOW_EN);
9881 if (!tg3_readphy(tp, 0x1b, &phy))
9882 tg3_writephy(tp, 0x1b, phy & ~0x20);
9883 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9884 }
9885 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9886 } else
9887 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9888
9889 tg3_phy_toggle_automdix(tp, 0);
9890
9891 tg3_writephy(tp, MII_BMCR, val);
9892 udelay(40);
9893
9894 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9896 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9897 mac_mode |= MAC_MODE_PORT_MODE_MII;
9898 } else
9899 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9900
9901 /* reset to prevent losing 1st rx packet intermittently */
9902 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9903 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9904 udelay(10);
9905 tw32_f(MAC_RX_MODE, tp->rx_mode);
9906 }
9907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9908 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9909 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9910 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9911 mac_mode |= MAC_MODE_LINK_POLARITY;
9912 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9913 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9914 }
9915 tw32(MAC_MODE, mac_mode);
9916 }
9917 else
9918 return -EINVAL;
9919
9920 err = -EIO;
9921
9922 tx_len = 1514;
9923 skb = netdev_alloc_skb(tp->dev, tx_len);
9924 if (!skb)
9925 return -ENOMEM;
9926
9927 tx_data = skb_put(skb, tx_len);
9928 memcpy(tx_data, tp->dev->dev_addr, 6);
9929 memset(tx_data + 6, 0x0, 8);
9930
9931 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9932
9933 for (i = 14; i < tx_len; i++)
9934 tx_data[i] = (u8) (i & 0xff);
9935
9936 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9937
9938 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9939 HOSTCC_MODE_NOW);
9940
9941 udelay(10);
9942
9943 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9944
9945 num_pkts = 0;
9946
9947 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9948
9949 tp->tx_prod++;
9950 num_pkts++;
9951
9952 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9953 tp->tx_prod);
9954 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9955
9956 udelay(10);
9957
9958 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9959 for (i = 0; i < 25; i++) {
9960 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9961 HOSTCC_MODE_NOW);
9962
9963 udelay(10);
9964
9965 tx_idx = tp->hw_status->idx[0].tx_consumer;
9966 rx_idx = tp->hw_status->idx[0].rx_producer;
9967 if ((tx_idx == tp->tx_prod) &&
9968 (rx_idx == (rx_start_idx + num_pkts)))
9969 break;
9970 }
9971
9972 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9973 dev_kfree_skb(skb);
9974
9975 if (tx_idx != tp->tx_prod)
9976 goto out;
9977
9978 if (rx_idx != rx_start_idx + num_pkts)
9979 goto out;
9980
9981 desc = &tp->rx_rcb[rx_start_idx];
9982 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9983 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9984 if (opaque_key != RXD_OPAQUE_RING_STD)
9985 goto out;
9986
9987 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9988 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9989 goto out;
9990
9991 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9992 if (rx_len != tx_len)
9993 goto out;
9994
9995 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9996
9997 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9998 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9999
10000 for (i = 14; i < tx_len; i++) {
10001 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10002 goto out;
10003 }
10004 err = 0;
10005
10006 /* tg3_free_rings will unmap and free the rx_skb */
10007out:
10008 return err;
10009}
10010
10011#define TG3_MAC_LOOPBACK_FAILED 1
10012#define TG3_PHY_LOOPBACK_FAILED 2
10013#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10014 TG3_PHY_LOOPBACK_FAILED)
10015
10016static int tg3_test_loopback(struct tg3 *tp)
10017{
10018 int err = 0;
10019 u32 cpmuctrl = 0;
10020
10021 if (!netif_running(tp->dev))
10022 return TG3_LOOPBACK_FAILED;
10023
10024 err = tg3_reset_hw(tp, 1);
10025 if (err)
10026 return TG3_LOOPBACK_FAILED;
10027
10028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10031 int i;
10032 u32 status;
10033
10034 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10035
10036 /* Wait for up to 40 microseconds to acquire lock. */
10037 for (i = 0; i < 4; i++) {
10038 status = tr32(TG3_CPMU_MUTEX_GNT);
10039 if (status == CPMU_MUTEX_GNT_DRIVER)
10040 break;
10041 udelay(10);
10042 }
10043
10044 if (status != CPMU_MUTEX_GNT_DRIVER)
10045 return TG3_LOOPBACK_FAILED;
10046
10047 /* Turn off link-based power management. */
10048 cpmuctrl = tr32(TG3_CPMU_CTRL);
10049 tw32(TG3_CPMU_CTRL,
10050 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10051 CPMU_CTRL_LINK_AWARE_MODE));
10052 }
10053
10054 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10055 err |= TG3_MAC_LOOPBACK_FAILED;
10056
10057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10060 tw32(TG3_CPMU_CTRL, cpmuctrl);
10061
10062 /* Release the mutex */
10063 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10064 }
10065
10066 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10067 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10068 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10069 err |= TG3_PHY_LOOPBACK_FAILED;
10070 }
10071
10072 return err;
10073}
10074
10075static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10076 u64 *data)
10077{
10078 struct tg3 *tp = netdev_priv(dev);
10079
10080 if (tp->link_config.phy_is_low_power)
10081 tg3_set_power_state(tp, PCI_D0);
10082
10083 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10084
10085 if (tg3_test_nvram(tp) != 0) {
10086 etest->flags |= ETH_TEST_FL_FAILED;
10087 data[0] = 1;
10088 }
10089 if (tg3_test_link(tp) != 0) {
10090 etest->flags |= ETH_TEST_FL_FAILED;
10091 data[1] = 1;
10092 }
10093 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10094 int err, err2 = 0, irq_sync = 0;
10095
10096 if (netif_running(dev)) {
10097 tg3_phy_stop(tp);
10098 tg3_netif_stop(tp);
10099 irq_sync = 1;
10100 }
10101
10102 tg3_full_lock(tp, irq_sync);
10103
10104 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10105 err = tg3_nvram_lock(tp);
10106 tg3_halt_cpu(tp, RX_CPU_BASE);
10107 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10108 tg3_halt_cpu(tp, TX_CPU_BASE);
10109 if (!err)
10110 tg3_nvram_unlock(tp);
10111
10112 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10113 tg3_phy_reset(tp);
10114
10115 if (tg3_test_registers(tp) != 0) {
10116 etest->flags |= ETH_TEST_FL_FAILED;
10117 data[2] = 1;
10118 }
10119 if (tg3_test_memory(tp) != 0) {
10120 etest->flags |= ETH_TEST_FL_FAILED;
10121 data[3] = 1;
10122 }
10123 if ((data[4] = tg3_test_loopback(tp)) != 0)
10124 etest->flags |= ETH_TEST_FL_FAILED;
10125
10126 tg3_full_unlock(tp);
10127
10128 if (tg3_test_interrupt(tp) != 0) {
10129 etest->flags |= ETH_TEST_FL_FAILED;
10130 data[5] = 1;
10131 }
10132
10133 tg3_full_lock(tp, 0);
10134
10135 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10136 if (netif_running(dev)) {
10137 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10138 err2 = tg3_restart_hw(tp, 1);
10139 if (!err2)
10140 tg3_netif_start(tp);
10141 }
10142
10143 tg3_full_unlock(tp);
10144
10145 if (irq_sync && !err2)
10146 tg3_phy_start(tp);
10147 }
10148 if (tp->link_config.phy_is_low_power)
10149 tg3_set_power_state(tp, PCI_D3hot);
10150
10151}
10152
10153static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10154{
10155 struct mii_ioctl_data *data = if_mii(ifr);
10156 struct tg3 *tp = netdev_priv(dev);
10157 int err;
10158
10159 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10160 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10161 return -EAGAIN;
10162 return phy_mii_ioctl(tp->mdio_bus.phy_map[PHY_ADDR], data, cmd);
10163 }
10164
10165 switch(cmd) {
10166 case SIOCGMIIPHY:
10167 data->phy_id = PHY_ADDR;
10168
10169 /* fallthru */
10170 case SIOCGMIIREG: {
10171 u32 mii_regval;
10172
10173 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10174 break; /* We have no PHY */
10175
10176 if (tp->link_config.phy_is_low_power)
10177 return -EAGAIN;
10178
10179 spin_lock_bh(&tp->lock);
10180 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10181 spin_unlock_bh(&tp->lock);
10182
10183 data->val_out = mii_regval;
10184
10185 return err;
10186 }
10187
10188 case SIOCSMIIREG:
10189 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10190 break; /* We have no PHY */
10191
10192 if (!capable(CAP_NET_ADMIN))
10193 return -EPERM;
10194
10195 if (tp->link_config.phy_is_low_power)
10196 return -EAGAIN;
10197
10198 spin_lock_bh(&tp->lock);
10199 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10200 spin_unlock_bh(&tp->lock);
10201
10202 return err;
10203
10204 default:
10205 /* do nothing */
10206 break;
10207 }
10208 return -EOPNOTSUPP;
10209}
10210
10211#if TG3_VLAN_TAG_USED
10212static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10213{
10214 struct tg3 *tp = netdev_priv(dev);
10215
10216 if (netif_running(dev))
10217 tg3_netif_stop(tp);
10218
10219 tg3_full_lock(tp, 0);
10220
10221 tp->vlgrp = grp;
10222
10223 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10224 __tg3_set_rx_mode(dev);
10225
10226 if (netif_running(dev))
10227 tg3_netif_start(tp);
10228
10229 tg3_full_unlock(tp);
10230}
10231#endif
10232
10233static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10234{
10235 struct tg3 *tp = netdev_priv(dev);
10236
10237 memcpy(ec, &tp->coal, sizeof(*ec));
10238 return 0;
10239}
10240
10241static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10242{
10243 struct tg3 *tp = netdev_priv(dev);
10244 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10245 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10246
10247 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10248 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10249 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10250 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10251 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10252 }
10253
10254 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10255 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10256 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10257 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10258 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10259 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10260 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10261 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10262 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10263 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10264 return -EINVAL;
10265
10266 /* No rx interrupts will be generated if both are zero */
10267 if ((ec->rx_coalesce_usecs == 0) &&
10268 (ec->rx_max_coalesced_frames == 0))
10269 return -EINVAL;
10270
10271 /* No tx interrupts will be generated if both are zero */
10272 if ((ec->tx_coalesce_usecs == 0) &&
10273 (ec->tx_max_coalesced_frames == 0))
10274 return -EINVAL;
10275
10276 /* Only copy relevant parameters, ignore all others. */
10277 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10278 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10279 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10280 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10281 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10282 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10283 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10284 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10285 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10286
10287 if (netif_running(dev)) {
10288 tg3_full_lock(tp, 0);
10289 __tg3_set_coalesce(tp, &tp->coal);
10290 tg3_full_unlock(tp);
10291 }
10292 return 0;
10293}
10294
10295static const struct ethtool_ops tg3_ethtool_ops = {
10296 .get_settings = tg3_get_settings,
10297 .set_settings = tg3_set_settings,
10298 .get_drvinfo = tg3_get_drvinfo,
10299 .get_regs_len = tg3_get_regs_len,
10300 .get_regs = tg3_get_regs,
10301 .get_wol = tg3_get_wol,
10302 .set_wol = tg3_set_wol,
10303 .get_msglevel = tg3_get_msglevel,
10304 .set_msglevel = tg3_set_msglevel,
10305 .nway_reset = tg3_nway_reset,
10306 .get_link = ethtool_op_get_link,
10307 .get_eeprom_len = tg3_get_eeprom_len,
10308 .get_eeprom = tg3_get_eeprom,
10309 .set_eeprom = tg3_set_eeprom,
10310 .get_ringparam = tg3_get_ringparam,
10311 .set_ringparam = tg3_set_ringparam,
10312 .get_pauseparam = tg3_get_pauseparam,
10313 .set_pauseparam = tg3_set_pauseparam,
10314 .get_rx_csum = tg3_get_rx_csum,
10315 .set_rx_csum = tg3_set_rx_csum,
10316 .set_tx_csum = tg3_set_tx_csum,
10317 .set_sg = ethtool_op_set_sg,
10318 .set_tso = tg3_set_tso,
10319 .self_test = tg3_self_test,
10320 .get_strings = tg3_get_strings,
10321 .phys_id = tg3_phys_id,
10322 .get_ethtool_stats = tg3_get_ethtool_stats,
10323 .get_coalesce = tg3_get_coalesce,
10324 .set_coalesce = tg3_set_coalesce,
10325 .get_sset_count = tg3_get_sset_count,
10326};
10327
10328static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10329{
10330 u32 cursize, val, magic;
10331
10332 tp->nvram_size = EEPROM_CHIP_SIZE;
10333
10334 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
10335 return;
10336
10337 if ((magic != TG3_EEPROM_MAGIC) &&
10338 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10339 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10340 return;
10341
10342 /*
10343 * Size the chip by reading offsets at increasing powers of two.
10344 * When we encounter our validation signature, we know the addressing
10345 * has wrapped around, and thus have our chip size.
10346 */
10347 cursize = 0x10;
10348
10349 while (cursize < tp->nvram_size) {
10350 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
10351 return;
10352
10353 if (val == magic)
10354 break;
10355
10356 cursize <<= 1;
10357 }
10358
10359 tp->nvram_size = cursize;
10360}
10361
10362static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10363{
10364 u32 val;
10365
10366 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
10367 return;
10368
10369 /* Selfboot format */
10370 if (val != TG3_EEPROM_MAGIC) {
10371 tg3_get_eeprom_size(tp);
10372 return;
10373 }
10374
10375 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10376 if (val != 0) {
10377 tp->nvram_size = (val >> 16) * 1024;
10378 return;
10379 }
10380 }
10381 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10382}
10383
10384static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10385{
10386 u32 nvcfg1;
10387
10388 nvcfg1 = tr32(NVRAM_CFG1);
10389 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10390 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10391 }
10392 else {
10393 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10394 tw32(NVRAM_CFG1, nvcfg1);
10395 }
10396
10397 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10398 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10399 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10400 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10401 tp->nvram_jedecnum = JEDEC_ATMEL;
10402 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10403 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10404 break;
10405 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10406 tp->nvram_jedecnum = JEDEC_ATMEL;
10407 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10408 break;
10409 case FLASH_VENDOR_ATMEL_EEPROM:
10410 tp->nvram_jedecnum = JEDEC_ATMEL;
10411 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10412 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10413 break;
10414 case FLASH_VENDOR_ST:
10415 tp->nvram_jedecnum = JEDEC_ST;
10416 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10417 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10418 break;
10419 case FLASH_VENDOR_SAIFUN:
10420 tp->nvram_jedecnum = JEDEC_SAIFUN;
10421 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10422 break;
10423 case FLASH_VENDOR_SST_SMALL:
10424 case FLASH_VENDOR_SST_LARGE:
10425 tp->nvram_jedecnum = JEDEC_SST;
10426 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10427 break;
10428 }
10429 }
10430 else {
10431 tp->nvram_jedecnum = JEDEC_ATMEL;
10432 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10433 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10434 }
10435}
10436
10437static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10438{
10439 u32 nvcfg1;
10440
10441 nvcfg1 = tr32(NVRAM_CFG1);
10442
10443 /* NVRAM protection for TPM */
10444 if (nvcfg1 & (1 << 27))
10445 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10446
10447 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10448 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10449 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10450 tp->nvram_jedecnum = JEDEC_ATMEL;
10451 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10452 break;
10453 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10454 tp->nvram_jedecnum = JEDEC_ATMEL;
10455 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10456 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10457 break;
10458 case FLASH_5752VENDOR_ST_M45PE10:
10459 case FLASH_5752VENDOR_ST_M45PE20:
10460 case FLASH_5752VENDOR_ST_M45PE40:
10461 tp->nvram_jedecnum = JEDEC_ST;
10462 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10463 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10464 break;
10465 }
10466
10467 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10468 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10469 case FLASH_5752PAGE_SIZE_256:
10470 tp->nvram_pagesize = 256;
10471 break;
10472 case FLASH_5752PAGE_SIZE_512:
10473 tp->nvram_pagesize = 512;
10474 break;
10475 case FLASH_5752PAGE_SIZE_1K:
10476 tp->nvram_pagesize = 1024;
10477 break;
10478 case FLASH_5752PAGE_SIZE_2K:
10479 tp->nvram_pagesize = 2048;
10480 break;
10481 case FLASH_5752PAGE_SIZE_4K:
10482 tp->nvram_pagesize = 4096;
10483 break;
10484 case FLASH_5752PAGE_SIZE_264:
10485 tp->nvram_pagesize = 264;
10486 break;
10487 }
10488 }
10489 else {
10490 /* For eeprom, set pagesize to maximum eeprom size */
10491 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10492
10493 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10494 tw32(NVRAM_CFG1, nvcfg1);
10495 }
10496}
10497
10498static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10499{
10500 u32 nvcfg1, protect = 0;
10501
10502 nvcfg1 = tr32(NVRAM_CFG1);
10503
10504 /* NVRAM protection for TPM */
10505 if (nvcfg1 & (1 << 27)) {
10506 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10507 protect = 1;
10508 }
10509
10510 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10511 switch (nvcfg1) {
10512 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10513 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10514 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10515 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10516 tp->nvram_jedecnum = JEDEC_ATMEL;
10517 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10518 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10519 tp->nvram_pagesize = 264;
10520 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10521 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10522 tp->nvram_size = (protect ? 0x3e200 :
10523 TG3_NVRAM_SIZE_512KB);
10524 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10525 tp->nvram_size = (protect ? 0x1f200 :
10526 TG3_NVRAM_SIZE_256KB);
10527 else
10528 tp->nvram_size = (protect ? 0x1f200 :
10529 TG3_NVRAM_SIZE_128KB);
10530 break;
10531 case FLASH_5752VENDOR_ST_M45PE10:
10532 case FLASH_5752VENDOR_ST_M45PE20:
10533 case FLASH_5752VENDOR_ST_M45PE40:
10534 tp->nvram_jedecnum = JEDEC_ST;
10535 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10536 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10537 tp->nvram_pagesize = 256;
10538 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10539 tp->nvram_size = (protect ?
10540 TG3_NVRAM_SIZE_64KB :
10541 TG3_NVRAM_SIZE_128KB);
10542 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10543 tp->nvram_size = (protect ?
10544 TG3_NVRAM_SIZE_64KB :
10545 TG3_NVRAM_SIZE_256KB);
10546 else
10547 tp->nvram_size = (protect ?
10548 TG3_NVRAM_SIZE_128KB :
10549 TG3_NVRAM_SIZE_512KB);
10550 break;
10551 }
10552}
10553
10554static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10555{
10556 u32 nvcfg1;
10557
10558 nvcfg1 = tr32(NVRAM_CFG1);
10559
10560 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10561 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10562 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10563 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10564 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10565 tp->nvram_jedecnum = JEDEC_ATMEL;
10566 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10567 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10568
10569 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10570 tw32(NVRAM_CFG1, nvcfg1);
10571 break;
10572 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10573 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10574 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10575 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10576 tp->nvram_jedecnum = JEDEC_ATMEL;
10577 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10578 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10579 tp->nvram_pagesize = 264;
10580 break;
10581 case FLASH_5752VENDOR_ST_M45PE10:
10582 case FLASH_5752VENDOR_ST_M45PE20:
10583 case FLASH_5752VENDOR_ST_M45PE40:
10584 tp->nvram_jedecnum = JEDEC_ST;
10585 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10586 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10587 tp->nvram_pagesize = 256;
10588 break;
10589 }
10590}
10591
10592static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10593{
10594 u32 nvcfg1, protect = 0;
10595
10596 nvcfg1 = tr32(NVRAM_CFG1);
10597
10598 /* NVRAM protection for TPM */
10599 if (nvcfg1 & (1 << 27)) {
10600 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10601 protect = 1;
10602 }
10603
10604 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10605 switch (nvcfg1) {
10606 case FLASH_5761VENDOR_ATMEL_ADB021D:
10607 case FLASH_5761VENDOR_ATMEL_ADB041D:
10608 case FLASH_5761VENDOR_ATMEL_ADB081D:
10609 case FLASH_5761VENDOR_ATMEL_ADB161D:
10610 case FLASH_5761VENDOR_ATMEL_MDB021D:
10611 case FLASH_5761VENDOR_ATMEL_MDB041D:
10612 case FLASH_5761VENDOR_ATMEL_MDB081D:
10613 case FLASH_5761VENDOR_ATMEL_MDB161D:
10614 tp->nvram_jedecnum = JEDEC_ATMEL;
10615 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10616 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10617 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10618 tp->nvram_pagesize = 256;
10619 break;
10620 case FLASH_5761VENDOR_ST_A_M45PE20:
10621 case FLASH_5761VENDOR_ST_A_M45PE40:
10622 case FLASH_5761VENDOR_ST_A_M45PE80:
10623 case FLASH_5761VENDOR_ST_A_M45PE16:
10624 case FLASH_5761VENDOR_ST_M_M45PE20:
10625 case FLASH_5761VENDOR_ST_M_M45PE40:
10626 case FLASH_5761VENDOR_ST_M_M45PE80:
10627 case FLASH_5761VENDOR_ST_M_M45PE16:
10628 tp->nvram_jedecnum = JEDEC_ST;
10629 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10630 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10631 tp->nvram_pagesize = 256;
10632 break;
10633 }
10634
10635 if (protect) {
10636 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10637 } else {
10638 switch (nvcfg1) {
10639 case FLASH_5761VENDOR_ATMEL_ADB161D:
10640 case FLASH_5761VENDOR_ATMEL_MDB161D:
10641 case FLASH_5761VENDOR_ST_A_M45PE16:
10642 case FLASH_5761VENDOR_ST_M_M45PE16:
10643 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10644 break;
10645 case FLASH_5761VENDOR_ATMEL_ADB081D:
10646 case FLASH_5761VENDOR_ATMEL_MDB081D:
10647 case FLASH_5761VENDOR_ST_A_M45PE80:
10648 case FLASH_5761VENDOR_ST_M_M45PE80:
10649 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10650 break;
10651 case FLASH_5761VENDOR_ATMEL_ADB041D:
10652 case FLASH_5761VENDOR_ATMEL_MDB041D:
10653 case FLASH_5761VENDOR_ST_A_M45PE40:
10654 case FLASH_5761VENDOR_ST_M_M45PE40:
10655 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10656 break;
10657 case FLASH_5761VENDOR_ATMEL_ADB021D:
10658 case FLASH_5761VENDOR_ATMEL_MDB021D:
10659 case FLASH_5761VENDOR_ST_A_M45PE20:
10660 case FLASH_5761VENDOR_ST_M_M45PE20:
10661 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10662 break;
10663 }
10664 }
10665}
10666
10667static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10668{
10669 tp->nvram_jedecnum = JEDEC_ATMEL;
10670 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10671 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10672}
10673
10674/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10675static void __devinit tg3_nvram_init(struct tg3 *tp)
10676{
10677 tw32_f(GRC_EEPROM_ADDR,
10678 (EEPROM_ADDR_FSM_RESET |
10679 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10680 EEPROM_ADDR_CLKPERD_SHIFT)));
10681
10682 msleep(1);
10683
10684 /* Enable seeprom accesses. */
10685 tw32_f(GRC_LOCAL_CTRL,
10686 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10687 udelay(100);
10688
10689 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10690 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10691 tp->tg3_flags |= TG3_FLAG_NVRAM;
10692
10693 if (tg3_nvram_lock(tp)) {
10694 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10695 "tg3_nvram_init failed.\n", tp->dev->name);
10696 return;
10697 }
10698 tg3_enable_nvram_access(tp);
10699
10700 tp->nvram_size = 0;
10701
10702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10703 tg3_get_5752_nvram_info(tp);
10704 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10705 tg3_get_5755_nvram_info(tp);
10706 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10707 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10709 tg3_get_5787_nvram_info(tp);
10710 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10711 tg3_get_5761_nvram_info(tp);
10712 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10713 tg3_get_5906_nvram_info(tp);
10714 else
10715 tg3_get_nvram_info(tp);
10716
10717 if (tp->nvram_size == 0)
10718 tg3_get_nvram_size(tp);
10719
10720 tg3_disable_nvram_access(tp);
10721 tg3_nvram_unlock(tp);
10722
10723 } else {
10724 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10725
10726 tg3_get_eeprom_size(tp);
10727 }
10728}
10729
10730static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10731 u32 offset, u32 *val)
10732{
10733 u32 tmp;
10734 int i;
10735
10736 if (offset > EEPROM_ADDR_ADDR_MASK ||
10737 (offset % 4) != 0)
10738 return -EINVAL;
10739
10740 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10741 EEPROM_ADDR_DEVID_MASK |
10742 EEPROM_ADDR_READ);
10743 tw32(GRC_EEPROM_ADDR,
10744 tmp |
10745 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10746 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10747 EEPROM_ADDR_ADDR_MASK) |
10748 EEPROM_ADDR_READ | EEPROM_ADDR_START);
10749
10750 for (i = 0; i < 1000; i++) {
10751 tmp = tr32(GRC_EEPROM_ADDR);
10752
10753 if (tmp & EEPROM_ADDR_COMPLETE)
10754 break;
10755 msleep(1);
10756 }
10757 if (!(tmp & EEPROM_ADDR_COMPLETE))
10758 return -EBUSY;
10759
10760 *val = tr32(GRC_EEPROM_DATA);
10761 return 0;
10762}
10763
10764#define NVRAM_CMD_TIMEOUT 10000
10765
10766static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10767{
10768 int i;
10769
10770 tw32(NVRAM_CMD, nvram_cmd);
10771 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10772 udelay(10);
10773 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10774 udelay(10);
10775 break;
10776 }
10777 }
10778 if (i == NVRAM_CMD_TIMEOUT) {
10779 return -EBUSY;
10780 }
10781 return 0;
10782}
10783
10784static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10785{
10786 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10787 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10788 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10789 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10790 (tp->nvram_jedecnum == JEDEC_ATMEL))
10791
10792 addr = ((addr / tp->nvram_pagesize) <<
10793 ATMEL_AT45DB0X1B_PAGE_POS) +
10794 (addr % tp->nvram_pagesize);
10795
10796 return addr;
10797}
10798
10799static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10800{
10801 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10802 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10803 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10804 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10805 (tp->nvram_jedecnum == JEDEC_ATMEL))
10806
10807 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10808 tp->nvram_pagesize) +
10809 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10810
10811 return addr;
10812}
10813
10814static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10815{
10816 int ret;
10817
10818 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10819 return tg3_nvram_read_using_eeprom(tp, offset, val);
10820
10821 offset = tg3_nvram_phys_addr(tp, offset);
10822
10823 if (offset > NVRAM_ADDR_MSK)
10824 return -EINVAL;
10825
10826 ret = tg3_nvram_lock(tp);
10827 if (ret)
10828 return ret;
10829
10830 tg3_enable_nvram_access(tp);
10831
10832 tw32(NVRAM_ADDR, offset);
10833 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10834 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10835
10836 if (ret == 0)
10837 *val = swab32(tr32(NVRAM_RDDATA));
10838
10839 tg3_disable_nvram_access(tp);
10840
10841 tg3_nvram_unlock(tp);
10842
10843 return ret;
10844}
10845
10846static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10847{
10848 u32 v;
10849 int res = tg3_nvram_read(tp, offset, &v);
10850 if (!res)
10851 *val = cpu_to_le32(v);
10852 return res;
10853}
10854
10855static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10856{
10857 int err;
10858 u32 tmp;
10859
10860 err = tg3_nvram_read(tp, offset, &tmp);
10861 *val = swab32(tmp);
10862 return err;
10863}
10864
10865static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10866 u32 offset, u32 len, u8 *buf)
10867{
10868 int i, j, rc = 0;
10869 u32 val;
10870
10871 for (i = 0; i < len; i += 4) {
10872 u32 addr;
10873 __le32 data;
10874
10875 addr = offset + i;
10876
10877 memcpy(&data, buf + i, 4);
10878
10879 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10880
10881 val = tr32(GRC_EEPROM_ADDR);
10882 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10883
10884 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10885 EEPROM_ADDR_READ);
10886 tw32(GRC_EEPROM_ADDR, val |
10887 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10888 (addr & EEPROM_ADDR_ADDR_MASK) |
10889 EEPROM_ADDR_START |
10890 EEPROM_ADDR_WRITE);
10891
10892 for (j = 0; j < 1000; j++) {
10893 val = tr32(GRC_EEPROM_ADDR);
10894
10895 if (val & EEPROM_ADDR_COMPLETE)
10896 break;
10897 msleep(1);
10898 }
10899 if (!(val & EEPROM_ADDR_COMPLETE)) {
10900 rc = -EBUSY;
10901 break;
10902 }
10903 }
10904
10905 return rc;
10906}
10907
10908/* offset and length are dword aligned */
10909static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10910 u8 *buf)
10911{
10912 int ret = 0;
10913 u32 pagesize = tp->nvram_pagesize;
10914 u32 pagemask = pagesize - 1;
10915 u32 nvram_cmd;
10916 u8 *tmp;
10917
10918 tmp = kmalloc(pagesize, GFP_KERNEL);
10919 if (tmp == NULL)
10920 return -ENOMEM;
10921
10922 while (len) {
10923 int j;
10924 u32 phy_addr, page_off, size;
10925
10926 phy_addr = offset & ~pagemask;
10927
10928 for (j = 0; j < pagesize; j += 4) {
10929 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
10930 (__le32 *) (tmp + j))))
10931 break;
10932 }
10933 if (ret)
10934 break;
10935
10936 page_off = offset & pagemask;
10937 size = pagesize;
10938 if (len < size)
10939 size = len;
10940
10941 len -= size;
10942
10943 memcpy(tmp + page_off, buf, size);
10944
10945 offset = offset + (pagesize - page_off);
10946
10947 tg3_enable_nvram_access(tp);
10948
10949 /*
10950 * Before we can erase the flash page, we need
10951 * to issue a special "write enable" command.
10952 */
10953 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10954
10955 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10956 break;
10957
10958 /* Erase the target page */
10959 tw32(NVRAM_ADDR, phy_addr);
10960
10961 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10962 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10963
10964 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10965 break;
10966
10967 /* Issue another write enable to start the write. */
10968 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10969
10970 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10971 break;
10972
10973 for (j = 0; j < pagesize; j += 4) {
10974 __be32 data;
10975
10976 data = *((__be32 *) (tmp + j));
10977 /* swab32(le32_to_cpu(data)), actually */
10978 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10979
10980 tw32(NVRAM_ADDR, phy_addr + j);
10981
10982 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10983 NVRAM_CMD_WR;
10984
10985 if (j == 0)
10986 nvram_cmd |= NVRAM_CMD_FIRST;
10987 else if (j == (pagesize - 4))
10988 nvram_cmd |= NVRAM_CMD_LAST;
10989
10990 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10991 break;
10992 }
10993 if (ret)
10994 break;
10995 }
10996
10997 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10998 tg3_nvram_exec_cmd(tp, nvram_cmd);
10999
11000 kfree(tmp);
11001
11002 return ret;
11003}
11004
11005/* offset and length are dword aligned */
11006static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11007 u8 *buf)
11008{
11009 int i, ret = 0;
11010
11011 for (i = 0; i < len; i += 4, offset += 4) {
11012 u32 page_off, phy_addr, nvram_cmd;
11013 __be32 data;
11014
11015 memcpy(&data, buf + i, 4);
11016 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11017
11018 page_off = offset % tp->nvram_pagesize;
11019
11020 phy_addr = tg3_nvram_phys_addr(tp, offset);
11021
11022 tw32(NVRAM_ADDR, phy_addr);
11023
11024 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11025
11026 if ((page_off == 0) || (i == 0))
11027 nvram_cmd |= NVRAM_CMD_FIRST;
11028 if (page_off == (tp->nvram_pagesize - 4))
11029 nvram_cmd |= NVRAM_CMD_LAST;
11030
11031 if (i == (len - 4))
11032 nvram_cmd |= NVRAM_CMD_LAST;
11033
11034 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
11035 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
11036 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
11037 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
11038 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
11039 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) &&
11040 (tp->nvram_jedecnum == JEDEC_ST) &&
11041 (nvram_cmd & NVRAM_CMD_FIRST)) {
11042
11043 if ((ret = tg3_nvram_exec_cmd(tp,
11044 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11045 NVRAM_CMD_DONE)))
11046
11047 break;
11048 }
11049 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11050 /* We always do complete word writes to eeprom. */
11051 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11052 }
11053
11054 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11055 break;
11056 }
11057 return ret;
11058}
11059
11060/* offset and length are dword aligned */
11061static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11062{
11063 int ret;
11064
11065 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11066 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11067 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11068 udelay(40);
11069 }
11070
11071 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11072 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11073 }
11074 else {
11075 u32 grc_mode;
11076
11077 ret = tg3_nvram_lock(tp);
11078 if (ret)
11079 return ret;
11080
11081 tg3_enable_nvram_access(tp);
11082 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11083 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11084 tw32(NVRAM_WRITE1, 0x406);
11085
11086 grc_mode = tr32(GRC_MODE);
11087 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11088
11089 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11090 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11091
11092 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11093 buf);
11094 }
11095 else {
11096 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11097 buf);
11098 }
11099
11100 grc_mode = tr32(GRC_MODE);
11101 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11102
11103 tg3_disable_nvram_access(tp);
11104 tg3_nvram_unlock(tp);
11105 }
11106
11107 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11108 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11109 udelay(40);
11110 }
11111
11112 return ret;
11113}
11114
11115struct subsys_tbl_ent {
11116 u16 subsys_vendor, subsys_devid;
11117 u32 phy_id;
11118};
11119
11120static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11121 /* Broadcom boards. */
11122 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11123 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11124 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11125 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11126 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11127 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11128 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11129 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11130 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11131 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11132 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11133
11134 /* 3com boards. */
11135 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11136 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11137 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11138 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11139 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11140
11141 /* DELL boards. */
11142 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11143 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11144 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11145 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11146
11147 /* Compaq boards. */
11148 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11149 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11150 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11151 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11152 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11153
11154 /* IBM boards. */
11155 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11156};
11157
11158static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11159{
11160 int i;
11161
11162 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11163 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11164 tp->pdev->subsystem_vendor) &&
11165 (subsys_id_to_phy_id[i].subsys_devid ==
11166 tp->pdev->subsystem_device))
11167 return &subsys_id_to_phy_id[i];
11168 }
11169 return NULL;
11170}
11171
11172static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11173{
11174 u32 val;
11175 u16 pmcsr;
11176
11177 /* On some early chips the SRAM cannot be accessed in D3hot state,
11178 * so need make sure we're in D0.
11179 */
11180 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11181 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11182 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11183 msleep(1);
11184
11185 /* Make sure register accesses (indirect or otherwise)
11186 * will function correctly.
11187 */
11188 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11189 tp->misc_host_ctrl);
11190
11191 /* The memory arbiter has to be enabled in order for SRAM accesses
11192 * to succeed. Normally on powerup the tg3 chip firmware will make
11193 * sure it is enabled, but other entities such as system netboot
11194 * code might disable it.
11195 */
11196 val = tr32(MEMARB_MODE);
11197 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11198
11199 tp->phy_id = PHY_ID_INVALID;
11200 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11201
11202 /* Assume an onboard device and WOL capable by default. */
11203 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11204
11205 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11206 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11207 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11208 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11209 }
11210 val = tr32(VCPU_CFGSHDW);
11211 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11212 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11213 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11214 (val & VCPU_CFGSHDW_WOL_MAGPKT))
11215 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11216 return;
11217 }
11218
11219 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11220 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11221 u32 nic_cfg, led_cfg;
11222 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
11223 int eeprom_phy_serdes = 0;
11224
11225 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11226 tp->nic_sram_data_cfg = nic_cfg;
11227
11228 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11229 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11230 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11231 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11232 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11233 (ver > 0) && (ver < 0x100))
11234 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11235
11236 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11237 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11238 eeprom_phy_serdes = 1;
11239
11240 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11241 if (nic_phy_id != 0) {
11242 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11243 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11244
11245 eeprom_phy_id = (id1 >> 16) << 10;
11246 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11247 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11248 } else
11249 eeprom_phy_id = 0;
11250
11251 tp->phy_id = eeprom_phy_id;
11252 if (eeprom_phy_serdes) {
11253 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11254 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11255 else
11256 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11257 }
11258
11259 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11260 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11261 SHASTA_EXT_LED_MODE_MASK);
11262 else
11263 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11264
11265 switch (led_cfg) {
11266 default:
11267 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11268 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11269 break;
11270
11271 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11272 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11273 break;
11274
11275 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11276 tp->led_ctrl = LED_CTRL_MODE_MAC;
11277
11278 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11279 * read on some older 5700/5701 bootcode.
11280 */
11281 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11282 ASIC_REV_5700 ||
11283 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11284 ASIC_REV_5701)
11285 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11286
11287 break;
11288
11289 case SHASTA_EXT_LED_SHARED:
11290 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11291 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11292 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11293 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11294 LED_CTRL_MODE_PHY_2);
11295 break;
11296
11297 case SHASTA_EXT_LED_MAC:
11298 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11299 break;
11300
11301 case SHASTA_EXT_LED_COMBO:
11302 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11303 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11304 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11305 LED_CTRL_MODE_PHY_2);
11306 break;
11307
11308 };
11309
11310 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11312 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11313 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11314
11315 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11316 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11317
11318 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11319 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11320 if ((tp->pdev->subsystem_vendor ==
11321 PCI_VENDOR_ID_ARIMA) &&
11322 (tp->pdev->subsystem_device == 0x205a ||
11323 tp->pdev->subsystem_device == 0x2063))
11324 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11325 } else {
11326 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11327 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11328 }
11329
11330 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11331 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11332 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11333 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11334 }
11335 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
11336 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11338 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11339 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11340
11341 if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
11342 nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
11343 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11344
11345 if (cfg2 & (1 << 17))
11346 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11347
11348 /* serdes signal pre-emphasis in register 0x590 set by */
11349 /* bootcode if bit 18 is set */
11350 if (cfg2 & (1 << 18))
11351 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11352
11353 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11354 u32 cfg3;
11355
11356 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11357 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11358 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11359 }
11360 }
11361}
11362
11363static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11364{
11365 int i;
11366 u32 val;
11367
11368 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11369 tw32(OTP_CTRL, cmd);
11370
11371 /* Wait for up to 1 ms for command to execute. */
11372 for (i = 0; i < 100; i++) {
11373 val = tr32(OTP_STATUS);
11374 if (val & OTP_STATUS_CMD_DONE)
11375 break;
11376 udelay(10);
11377 }
11378
11379 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11380}
11381
11382/* Read the gphy configuration from the OTP region of the chip. The gphy
11383 * configuration is a 32-bit value that straddles the alignment boundary.
11384 * We do two 32-bit reads and then shift and merge the results.
11385 */
11386static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11387{
11388 u32 bhalf_otp, thalf_otp;
11389
11390 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11391
11392 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11393 return 0;
11394
11395 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11396
11397 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11398 return 0;
11399
11400 thalf_otp = tr32(OTP_READ_DATA);
11401
11402 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11403
11404 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11405 return 0;
11406
11407 bhalf_otp = tr32(OTP_READ_DATA);
11408
11409 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11410}
11411
11412static int __devinit tg3_phy_probe(struct tg3 *tp)
11413{
11414 u32 hw_phy_id_1, hw_phy_id_2;
11415 u32 hw_phy_id, hw_phy_id_masked;
11416 int err;
11417
11418 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11419 return tg3_phy_init(tp);
11420
11421 /* Reading the PHY ID register can conflict with ASF
11422 * firwmare access to the PHY hardware.
11423 */
11424 err = 0;
11425 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11426 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11427 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11428 } else {
11429 /* Now read the physical PHY_ID from the chip and verify
11430 * that it is sane. If it doesn't look good, we fall back
11431 * to either the hard-coded table based PHY_ID and failing
11432 * that the value found in the eeprom area.
11433 */
11434 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11435 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11436
11437 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11438 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11439 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11440
11441 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11442 }
11443
11444 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11445 tp->phy_id = hw_phy_id;
11446 if (hw_phy_id_masked == PHY_ID_BCM8002)
11447 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11448 else
11449 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11450 } else {
11451 if (tp->phy_id != PHY_ID_INVALID) {
11452 /* Do nothing, phy ID already set up in
11453 * tg3_get_eeprom_hw_cfg().
11454 */
11455 } else {
11456 struct subsys_tbl_ent *p;
11457
11458 /* No eeprom signature? Try the hardcoded
11459 * subsys device table.
11460 */
11461 p = lookup_by_subsys(tp);
11462 if (!p)
11463 return -ENODEV;
11464
11465 tp->phy_id = p->phy_id;
11466 if (!tp->phy_id ||
11467 tp->phy_id == PHY_ID_BCM8002)
11468 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11469 }
11470 }
11471
11472 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11473 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11474 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11475 u32 bmsr, adv_reg, tg3_ctrl, mask;
11476
11477 tg3_readphy(tp, MII_BMSR, &bmsr);
11478 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11479 (bmsr & BMSR_LSTATUS))
11480 goto skip_phy_reset;
11481
11482 err = tg3_phy_reset(tp);
11483 if (err)
11484 return err;
11485
11486 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11487 ADVERTISE_100HALF | ADVERTISE_100FULL |
11488 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11489 tg3_ctrl = 0;
11490 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11491 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11492 MII_TG3_CTRL_ADV_1000_FULL);
11493 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11494 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11495 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11496 MII_TG3_CTRL_ENABLE_AS_MASTER);
11497 }
11498
11499 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11500 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11501 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11502 if (!tg3_copper_is_advertising_all(tp, mask)) {
11503 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11504
11505 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11506 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11507
11508 tg3_writephy(tp, MII_BMCR,
11509 BMCR_ANENABLE | BMCR_ANRESTART);
11510 }
11511 tg3_phy_set_wirespeed(tp);
11512
11513 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11514 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11515 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11516 }
11517
11518skip_phy_reset:
11519 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11520 err = tg3_init_5401phy_dsp(tp);
11521 if (err)
11522 return err;
11523 }
11524
11525 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11526 err = tg3_init_5401phy_dsp(tp);
11527 }
11528
11529 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11530 tp->link_config.advertising =
11531 (ADVERTISED_1000baseT_Half |
11532 ADVERTISED_1000baseT_Full |
11533 ADVERTISED_Autoneg |
11534 ADVERTISED_FIBRE);
11535 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11536 tp->link_config.advertising &=
11537 ~(ADVERTISED_1000baseT_Half |
11538 ADVERTISED_1000baseT_Full);
11539
11540 return err;
11541}
11542
11543static void __devinit tg3_read_partno(struct tg3 *tp)
11544{
11545 unsigned char vpd_data[256];
11546 unsigned int i;
11547 u32 magic;
11548
11549 if (tg3_nvram_read_swab(tp, 0x0, &magic))
11550 goto out_not_found;
11551
11552 if (magic == TG3_EEPROM_MAGIC) {
11553 for (i = 0; i < 256; i += 4) {
11554 u32 tmp;
11555
11556 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11557 goto out_not_found;
11558
11559 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
11560 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
11561 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11562 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11563 }
11564 } else {
11565 int vpd_cap;
11566
11567 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11568 for (i = 0; i < 256; i += 4) {
11569 u32 tmp, j = 0;
11570 __le32 v;
11571 u16 tmp16;
11572
11573 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11574 i);
11575 while (j++ < 100) {
11576 pci_read_config_word(tp->pdev, vpd_cap +
11577 PCI_VPD_ADDR, &tmp16);
11578 if (tmp16 & 0x8000)
11579 break;
11580 msleep(1);
11581 }
11582 if (!(tmp16 & 0x8000))
11583 goto out_not_found;
11584
11585 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11586 &tmp);
11587 v = cpu_to_le32(tmp);
11588 memcpy(&vpd_data[i], &v, 4);
11589 }
11590 }
11591
11592 /* Now parse and find the part number. */
11593 for (i = 0; i < 254; ) {
11594 unsigned char val = vpd_data[i];
11595 unsigned int block_end;
11596
11597 if (val == 0x82 || val == 0x91) {
11598 i = (i + 3 +
11599 (vpd_data[i + 1] +
11600 (vpd_data[i + 2] << 8)));
11601 continue;
11602 }
11603
11604 if (val != 0x90)
11605 goto out_not_found;
11606
11607 block_end = (i + 3 +
11608 (vpd_data[i + 1] +
11609 (vpd_data[i + 2] << 8)));
11610 i += 3;
11611
11612 if (block_end > 256)
11613 goto out_not_found;
11614
11615 while (i < (block_end - 2)) {
11616 if (vpd_data[i + 0] == 'P' &&
11617 vpd_data[i + 1] == 'N') {
11618 int partno_len = vpd_data[i + 2];
11619
11620 i += 3;
11621 if (partno_len > 24 || (partno_len + i) > 256)
11622 goto out_not_found;
11623
11624 memcpy(tp->board_part_number,
11625 &vpd_data[i], partno_len);
11626
11627 /* Success. */
11628 return;
11629 }
11630 i += 3 + vpd_data[i + 2];
11631 }
11632
11633 /* Part number not found. */
11634 goto out_not_found;
11635 }
11636
11637out_not_found:
11638 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11639 strcpy(tp->board_part_number, "BCM95906");
11640 else
11641 strcpy(tp->board_part_number, "none");
11642}
11643
11644static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11645{
11646 u32 val;
11647
11648 if (tg3_nvram_read_swab(tp, offset, &val) ||
11649 (val & 0xfc000000) != 0x0c000000 ||
11650 tg3_nvram_read_swab(tp, offset + 4, &val) ||
11651 val != 0)
11652 return 0;
11653
11654 return 1;
11655}
11656
11657static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11658{
11659 u32 val, offset, start;
11660 u32 ver_offset;
11661 int i, bcnt;
11662
11663 if (tg3_nvram_read_swab(tp, 0, &val))
11664 return;
11665
11666 if (val != TG3_EEPROM_MAGIC)
11667 return;
11668
11669 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11670 tg3_nvram_read_swab(tp, 0x4, &start))
11671 return;
11672
11673 offset = tg3_nvram_logical_addr(tp, offset);
11674
11675 if (!tg3_fw_img_is_valid(tp, offset) ||
11676 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11677 return;
11678
11679 offset = offset + ver_offset - start;
11680 for (i = 0; i < 16; i += 4) {
11681 __le32 v;
11682 if (tg3_nvram_read_le(tp, offset + i, &v))
11683 return;
11684
11685 memcpy(tp->fw_ver + i, &v, 4);
11686 }
11687
11688 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11689 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11690 return;
11691
11692 for (offset = TG3_NVM_DIR_START;
11693 offset < TG3_NVM_DIR_END;
11694 offset += TG3_NVM_DIRENT_SIZE) {
11695 if (tg3_nvram_read_swab(tp, offset, &val))
11696 return;
11697
11698 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11699 break;
11700 }
11701
11702 if (offset == TG3_NVM_DIR_END)
11703 return;
11704
11705 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11706 start = 0x08000000;
11707 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11708 return;
11709
11710 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11711 !tg3_fw_img_is_valid(tp, offset) ||
11712 tg3_nvram_read_swab(tp, offset + 8, &val))
11713 return;
11714
11715 offset += val - start;
11716
11717 bcnt = strlen(tp->fw_ver);
11718
11719 tp->fw_ver[bcnt++] = ',';
11720 tp->fw_ver[bcnt++] = ' ';
11721
11722 for (i = 0; i < 4; i++) {
11723 __le32 v;
11724 if (tg3_nvram_read_le(tp, offset, &v))
11725 return;
11726
11727 offset += sizeof(v);
11728
11729 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11730 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11731 break;
11732 }
11733
11734 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11735 bcnt += sizeof(v);
11736 }
11737
11738 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11739}
11740
11741static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11742
11743static int __devinit tg3_get_invariants(struct tg3 *tp)
11744{
11745 static struct pci_device_id write_reorder_chipsets[] = {
11746 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11747 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11748 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11749 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11750 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11751 PCI_DEVICE_ID_VIA_8385_0) },
11752 { },
11753 };
11754 u32 misc_ctrl_reg;
11755 u32 cacheline_sz_reg;
11756 u32 pci_state_reg, grc_misc_cfg;
11757 u32 val;
11758 u16 pci_cmd;
11759 int err, pcie_cap;
11760
11761 /* Force memory write invalidate off. If we leave it on,
11762 * then on 5700_BX chips we have to enable a workaround.
11763 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11764 * to match the cacheline size. The Broadcom driver have this
11765 * workaround but turns MWI off all the times so never uses
11766 * it. This seems to suggest that the workaround is insufficient.
11767 */
11768 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11769 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11770 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11771
11772 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11773 * has the register indirect write enable bit set before
11774 * we try to access any of the MMIO registers. It is also
11775 * critical that the PCI-X hw workaround situation is decided
11776 * before that as well.
11777 */
11778 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11779 &misc_ctrl_reg);
11780
11781 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11782 MISC_HOST_CTRL_CHIPREV_SHIFT);
11783 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11784 u32 prod_id_asic_rev;
11785
11786 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11787 &prod_id_asic_rev);
11788 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11789 }
11790
11791 /* Wrong chip ID in 5752 A0. This code can be removed later
11792 * as A0 is not in production.
11793 */
11794 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11795 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11796
11797 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11798 * we need to disable memory and use config. cycles
11799 * only to access all registers. The 5702/03 chips
11800 * can mistakenly decode the special cycles from the
11801 * ICH chipsets as memory write cycles, causing corruption
11802 * of register and memory space. Only certain ICH bridges
11803 * will drive special cycles with non-zero data during the
11804 * address phase which can fall within the 5703's address
11805 * range. This is not an ICH bug as the PCI spec allows
11806 * non-zero address during special cycles. However, only
11807 * these ICH bridges are known to drive non-zero addresses
11808 * during special cycles.
11809 *
11810 * Since special cycles do not cross PCI bridges, we only
11811 * enable this workaround if the 5703 is on the secondary
11812 * bus of these ICH bridges.
11813 */
11814 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11815 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11816 static struct tg3_dev_id {
11817 u32 vendor;
11818 u32 device;
11819 u32 rev;
11820 } ich_chipsets[] = {
11821 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11822 PCI_ANY_ID },
11823 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11824 PCI_ANY_ID },
11825 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11826 0xa },
11827 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11828 PCI_ANY_ID },
11829 { },
11830 };
11831 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11832 struct pci_dev *bridge = NULL;
11833
11834 while (pci_id->vendor != 0) {
11835 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11836 bridge);
11837 if (!bridge) {
11838 pci_id++;
11839 continue;
11840 }
11841 if (pci_id->rev != PCI_ANY_ID) {
11842 if (bridge->revision > pci_id->rev)
11843 continue;
11844 }
11845 if (bridge->subordinate &&
11846 (bridge->subordinate->number ==
11847 tp->pdev->bus->number)) {
11848
11849 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11850 pci_dev_put(bridge);
11851 break;
11852 }
11853 }
11854 }
11855
11856 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11857 static struct tg3_dev_id {
11858 u32 vendor;
11859 u32 device;
11860 } bridge_chipsets[] = {
11861 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11862 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11863 { },
11864 };
11865 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11866 struct pci_dev *bridge = NULL;
11867
11868 while (pci_id->vendor != 0) {
11869 bridge = pci_get_device(pci_id->vendor,
11870 pci_id->device,
11871 bridge);
11872 if (!bridge) {
11873 pci_id++;
11874 continue;
11875 }
11876 if (bridge->subordinate &&
11877 (bridge->subordinate->number <=
11878 tp->pdev->bus->number) &&
11879 (bridge->subordinate->subordinate >=
11880 tp->pdev->bus->number)) {
11881 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11882 pci_dev_put(bridge);
11883 break;
11884 }
11885 }
11886 }
11887
11888 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11889 * DMA addresses > 40-bit. This bridge may have other additional
11890 * 57xx devices behind it in some 4-port NIC designs for example.
11891 * Any tg3 device found behind the bridge will also need the 40-bit
11892 * DMA workaround.
11893 */
11894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11895 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11896 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11897 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11898 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11899 }
11900 else {
11901 struct pci_dev *bridge = NULL;
11902
11903 do {
11904 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11905 PCI_DEVICE_ID_SERVERWORKS_EPB,
11906 bridge);
11907 if (bridge && bridge->subordinate &&
11908 (bridge->subordinate->number <=
11909 tp->pdev->bus->number) &&
11910 (bridge->subordinate->subordinate >=
11911 tp->pdev->bus->number)) {
11912 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11913 pci_dev_put(bridge);
11914 break;
11915 }
11916 } while (bridge);
11917 }
11918
11919 /* Initialize misc host control in PCI block. */
11920 tp->misc_host_ctrl |= (misc_ctrl_reg &
11921 MISC_HOST_CTRL_CHIPREV);
11922 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11923 tp->misc_host_ctrl);
11924
11925 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11926 &cacheline_sz_reg);
11927
11928 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
11929 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
11930 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
11931 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
11932
11933 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11934 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11935 tp->pdev_peer = tg3_find_peer(tp);
11936
11937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11940 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11945 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11946 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11947
11948 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11949 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11950 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11951
11952 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11953 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11954 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11955 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11956 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11957 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11958 tp->pdev_peer == tp->pdev))
11959 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11960
11961 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11962 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11963 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11964 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11966 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11967 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11968 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11969 } else {
11970 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11971 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11972 ASIC_REV_5750 &&
11973 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11974 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11975 }
11976 }
11977
11978 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11979 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11980 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11981
11982 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11983 if (pcie_cap != 0) {
11984 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11985
11986 pcie_set_readrq(tp->pdev, 4096);
11987
11988 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11989 u16 lnkctl;
11990
11991 pci_read_config_word(tp->pdev,
11992 pcie_cap + PCI_EXP_LNKCTL,
11993 &lnkctl);
11994 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
11995 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11996 }
11997 }
11998
11999 /* If we have an AMD 762 or VIA K8T800 chipset, write
12000 * reordering to the mailbox registers done by the host
12001 * controller can cause major troubles. We read back from
12002 * every mailbox register write to force the writes to be
12003 * posted to the chip in order.
12004 */
12005 if (pci_dev_present(write_reorder_chipsets) &&
12006 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12007 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12008
12009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12010 tp->pci_lat_timer < 64) {
12011 tp->pci_lat_timer = 64;
12012
12013 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
12014 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
12015 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
12016 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
12017
12018 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12019 cacheline_sz_reg);
12020 }
12021
12022 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12023 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12024 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12025 if (!tp->pcix_cap) {
12026 printk(KERN_ERR PFX "Cannot find PCI-X "
12027 "capability, aborting.\n");
12028 return -EIO;
12029 }
12030 }
12031
12032 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12033 &pci_state_reg);
12034
12035 if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
12036 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12037
12038 /* If this is a 5700 BX chipset, and we are in PCI-X
12039 * mode, enable register write workaround.
12040 *
12041 * The workaround is to use indirect register accesses
12042 * for all chip writes not to mailbox registers.
12043 */
12044 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12045 u32 pm_reg;
12046
12047 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12048
12049 /* The chip can have it's power management PCI config
12050 * space registers clobbered due to this bug.
12051 * So explicitly force the chip into D0 here.
12052 */
12053 pci_read_config_dword(tp->pdev,
12054 tp->pm_cap + PCI_PM_CTRL,
12055 &pm_reg);
12056 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12057 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12058 pci_write_config_dword(tp->pdev,
12059 tp->pm_cap + PCI_PM_CTRL,
12060 pm_reg);
12061
12062 /* Also, force SERR#/PERR# in PCI command. */
12063 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12064 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12065 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12066 }
12067 }
12068
12069 /* 5700 BX chips need to have their TX producer index mailboxes
12070 * written twice to workaround a bug.
12071 */
12072 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
12073 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12074
12075 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12076 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12077 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12078 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12079
12080 /* Chip-specific fixup from Broadcom driver */
12081 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12082 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12083 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12084 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12085 }
12086
12087 /* Default fast path register access methods */
12088 tp->read32 = tg3_read32;
12089 tp->write32 = tg3_write32;
12090 tp->read32_mbox = tg3_read32;
12091 tp->write32_mbox = tg3_write32;
12092 tp->write32_tx_mbox = tg3_write32;
12093 tp->write32_rx_mbox = tg3_write32;
12094
12095 /* Various workaround register access methods */
12096 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12097 tp->write32 = tg3_write_indirect_reg32;
12098 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12099 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12100 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12101 /*
12102 * Back to back register writes can cause problems on these
12103 * chips, the workaround is to read back all reg writes
12104 * except those to mailbox regs.
12105 *
12106 * See tg3_write_indirect_reg32().
12107 */
12108 tp->write32 = tg3_write_flush_reg32;
12109 }
12110
12111
12112 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12113 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12114 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12115 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12116 tp->write32_rx_mbox = tg3_write_flush_reg32;
12117 }
12118
12119 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12120 tp->read32 = tg3_read_indirect_reg32;
12121 tp->write32 = tg3_write_indirect_reg32;
12122 tp->read32_mbox = tg3_read_indirect_mbox;
12123 tp->write32_mbox = tg3_write_indirect_mbox;
12124 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12125 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12126
12127 iounmap(tp->regs);
12128 tp->regs = NULL;
12129
12130 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12131 pci_cmd &= ~PCI_COMMAND_MEMORY;
12132 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12133 }
12134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12135 tp->read32_mbox = tg3_read32_mbox_5906;
12136 tp->write32_mbox = tg3_write32_mbox_5906;
12137 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12138 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12139 }
12140
12141 if (tp->write32 == tg3_write_indirect_reg32 ||
12142 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12143 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12144 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12145 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12146
12147 /* Get eeprom hw config before calling tg3_set_power_state().
12148 * In particular, the TG3_FLG2_IS_NIC flag must be
12149 * determined before calling tg3_set_power_state() so that
12150 * we know whether or not to switch out of Vaux power.
12151 * When the flag is set, it means that GPIO1 is used for eeprom
12152 * write protect and also implies that it is a LOM where GPIOs
12153 * are not used to switch power.
12154 */
12155 tg3_get_eeprom_hw_cfg(tp);
12156
12157 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12158 /* Allow reads and writes to the
12159 * APE register and memory space.
12160 */
12161 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12162 PCISTATE_ALLOW_APE_SHMEM_WR;
12163 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12164 pci_state_reg);
12165 }
12166
12167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12168 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12169 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12170 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12171
12172 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
12173 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
12174 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
12175 tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
12176 tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
12177 }
12178
12179 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12180 * GPIO1 driven high will bring 5700's external PHY out of reset.
12181 * It is also used as eeprom write protect on LOMs.
12182 */
12183 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12184 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12185 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12186 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12187 GRC_LCLCTRL_GPIO_OUTPUT1);
12188 /* Unused GPIO3 must be driven as output on 5752 because there
12189 * are no pull-up resistors on unused GPIO pins.
12190 */
12191 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12192 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12193
12194 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12195 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12196
12197 /* Force the chip into D0. */
12198 err = tg3_set_power_state(tp, PCI_D0);
12199 if (err) {
12200 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12201 pci_name(tp->pdev));
12202 return err;
12203 }
12204
12205 /* 5700 B0 chips do not support checksumming correctly due
12206 * to hardware bugs.
12207 */
12208 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12209 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12210
12211 /* Derive initial jumbo mode from MTU assigned in
12212 * ether_setup() via the alloc_etherdev() call
12213 */
12214 if (tp->dev->mtu > ETH_DATA_LEN &&
12215 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12216 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12217
12218 /* Determine WakeOnLan speed to use. */
12219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12220 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12221 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12222 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12223 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12224 } else {
12225 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12226 }
12227
12228 /* A few boards don't want Ethernet@WireSpeed phy feature */
12229 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12230 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12231 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12232 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12233 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12234 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12235 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12236
12237 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12238 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12239 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12240 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12241 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12242
12243 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12244 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12245 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12247 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12248 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12249 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12250 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12251 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12252 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12253 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12254 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
12255 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12256 }
12257
12258 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12259 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12260 tp->phy_otp = tg3_read_otp_phycfg(tp);
12261 if (tp->phy_otp == 0)
12262 tp->phy_otp = TG3_OTP_DEFAULT;
12263 }
12264
12265 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12266 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12267 else
12268 tp->mi_mode = MAC_MI_MODE_BASE;
12269
12270 tp->coalesce_mode = 0;
12271 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12272 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12273 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12274
12275 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12276 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12277
12278 err = tg3_mdio_init(tp);
12279 if (err)
12280 return err;
12281
12282 /* Initialize data/descriptor byte/word swapping. */
12283 val = tr32(GRC_MODE);
12284 val &= GRC_MODE_HOST_STACKUP;
12285 tw32(GRC_MODE, val | tp->grc_mode);
12286
12287 tg3_switch_clocks(tp);
12288
12289 /* Clear this out for sanity. */
12290 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12291
12292 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12293 &pci_state_reg);
12294 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12295 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12296 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12297
12298 if (chiprevid == CHIPREV_ID_5701_A0 ||
12299 chiprevid == CHIPREV_ID_5701_B0 ||
12300 chiprevid == CHIPREV_ID_5701_B2 ||
12301 chiprevid == CHIPREV_ID_5701_B5) {
12302 void __iomem *sram_base;
12303
12304 /* Write some dummy words into the SRAM status block
12305 * area, see if it reads back correctly. If the return
12306 * value is bad, force enable the PCIX workaround.
12307 */
12308 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12309
12310 writel(0x00000000, sram_base);
12311 writel(0x00000000, sram_base + 4);
12312 writel(0xffffffff, sram_base + 4);
12313 if (readl(sram_base) != 0x00000000)
12314 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12315 }
12316 }
12317
12318 udelay(50);
12319 tg3_nvram_init(tp);
12320
12321 grc_misc_cfg = tr32(GRC_MISC_CFG);
12322 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12323
12324 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12325 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12326 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12327 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12328
12329 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12330 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12331 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12332 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12333 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12334 HOSTCC_MODE_CLRTICK_TXBD);
12335
12336 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12337 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12338 tp->misc_host_ctrl);
12339 }
12340
12341 /* these are limited to 10/100 only */
12342 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12343 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12344 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12345 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12346 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12347 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12348 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12349 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12350 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12351 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12352 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12353 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12354 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12355
12356 err = tg3_phy_probe(tp);
12357 if (err) {
12358 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12359 pci_name(tp->pdev), err);
12360 /* ... but do not return immediately ... */
12361 tg3_mdio_fini(tp);
12362 }
12363
12364 tg3_read_partno(tp);
12365 tg3_read_fw_ver(tp);
12366
12367 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12368 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12369 } else {
12370 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12371 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12372 else
12373 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12374 }
12375
12376 /* 5700 {AX,BX} chips have a broken status block link
12377 * change bit implementation, so we must use the
12378 * status register in those cases.
12379 */
12380 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12381 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12382 else
12383 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12384
12385 /* The led_ctrl is set during tg3_phy_probe, here we might
12386 * have to force the link status polling mechanism based
12387 * upon subsystem IDs.
12388 */
12389 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12390 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12391 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12392 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12393 TG3_FLAG_USE_LINKCHG_REG);
12394 }
12395
12396 /* For all SERDES we poll the MAC status register. */
12397 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12398 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12399 else
12400 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12401
12402 /* All chips before 5787 can get confused if TX buffers
12403 * straddle the 4GB address boundary in some cases.
12404 */
12405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12406 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12407 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12408 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12409 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12411 tp->dev->hard_start_xmit = tg3_start_xmit;
12412 else
12413 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
12414
12415 tp->rx_offset = 2;
12416 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12417 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12418 tp->rx_offset = 0;
12419
12420 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12421
12422 /* Increment the rx prod index on the rx std ring by at most
12423 * 8 for these chips to workaround hw errata.
12424 */
12425 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12428 tp->rx_std_max_post = 8;
12429
12430 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12431 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12432 PCIE_PWR_MGMT_L1_THRESH_MSK;
12433
12434 return err;
12435}
12436
12437#ifdef CONFIG_SPARC
12438static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12439{
12440 struct net_device *dev = tp->dev;
12441 struct pci_dev *pdev = tp->pdev;
12442 struct device_node *dp = pci_device_to_OF_node(pdev);
12443 const unsigned char *addr;
12444 int len;
12445
12446 addr = of_get_property(dp, "local-mac-address", &len);
12447 if (addr && len == 6) {
12448 memcpy(dev->dev_addr, addr, 6);
12449 memcpy(dev->perm_addr, dev->dev_addr, 6);
12450 return 0;
12451 }
12452 return -ENODEV;
12453}
12454
12455static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12456{
12457 struct net_device *dev = tp->dev;
12458
12459 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12460 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12461 return 0;
12462}
12463#endif
12464
12465static int __devinit tg3_get_device_address(struct tg3 *tp)
12466{
12467 struct net_device *dev = tp->dev;
12468 u32 hi, lo, mac_offset;
12469 int addr_ok = 0;
12470
12471#ifdef CONFIG_SPARC
12472 if (!tg3_get_macaddr_sparc(tp))
12473 return 0;
12474#endif
12475
12476 mac_offset = 0x7c;
12477 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12478 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12479 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12480 mac_offset = 0xcc;
12481 if (tg3_nvram_lock(tp))
12482 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12483 else
12484 tg3_nvram_unlock(tp);
12485 }
12486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12487 mac_offset = 0x10;
12488
12489 /* First try to get it from MAC address mailbox. */
12490 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12491 if ((hi >> 16) == 0x484b) {
12492 dev->dev_addr[0] = (hi >> 8) & 0xff;
12493 dev->dev_addr[1] = (hi >> 0) & 0xff;
12494
12495 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12496 dev->dev_addr[2] = (lo >> 24) & 0xff;
12497 dev->dev_addr[3] = (lo >> 16) & 0xff;
12498 dev->dev_addr[4] = (lo >> 8) & 0xff;
12499 dev->dev_addr[5] = (lo >> 0) & 0xff;
12500
12501 /* Some old bootcode may report a 0 MAC address in SRAM */
12502 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12503 }
12504 if (!addr_ok) {
12505 /* Next, try NVRAM. */
12506 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12507 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12508 dev->dev_addr[0] = ((hi >> 16) & 0xff);
12509 dev->dev_addr[1] = ((hi >> 24) & 0xff);
12510 dev->dev_addr[2] = ((lo >> 0) & 0xff);
12511 dev->dev_addr[3] = ((lo >> 8) & 0xff);
12512 dev->dev_addr[4] = ((lo >> 16) & 0xff);
12513 dev->dev_addr[5] = ((lo >> 24) & 0xff);
12514 }
12515 /* Finally just fetch it out of the MAC control regs. */
12516 else {
12517 hi = tr32(MAC_ADDR_0_HIGH);
12518 lo = tr32(MAC_ADDR_0_LOW);
12519
12520 dev->dev_addr[5] = lo & 0xff;
12521 dev->dev_addr[4] = (lo >> 8) & 0xff;
12522 dev->dev_addr[3] = (lo >> 16) & 0xff;
12523 dev->dev_addr[2] = (lo >> 24) & 0xff;
12524 dev->dev_addr[1] = hi & 0xff;
12525 dev->dev_addr[0] = (hi >> 8) & 0xff;
12526 }
12527 }
12528
12529 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12530#ifdef CONFIG_SPARC
12531 if (!tg3_get_default_macaddr_sparc(tp))
12532 return 0;
12533#endif
12534 return -EINVAL;
12535 }
12536 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12537 return 0;
12538}
12539
12540#define BOUNDARY_SINGLE_CACHELINE 1
12541#define BOUNDARY_MULTI_CACHELINE 2
12542
12543static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12544{
12545 int cacheline_size;
12546 u8 byte;
12547 int goal;
12548
12549 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12550 if (byte == 0)
12551 cacheline_size = 1024;
12552 else
12553 cacheline_size = (int) byte * 4;
12554
12555 /* On 5703 and later chips, the boundary bits have no
12556 * effect.
12557 */
12558 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12559 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12560 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12561 goto out;
12562
12563#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12564 goal = BOUNDARY_MULTI_CACHELINE;
12565#else
12566#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12567 goal = BOUNDARY_SINGLE_CACHELINE;
12568#else
12569 goal = 0;
12570#endif
12571#endif
12572
12573 if (!goal)
12574 goto out;
12575
12576 /* PCI controllers on most RISC systems tend to disconnect
12577 * when a device tries to burst across a cache-line boundary.
12578 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12579 *
12580 * Unfortunately, for PCI-E there are only limited
12581 * write-side controls for this, and thus for reads
12582 * we will still get the disconnects. We'll also waste
12583 * these PCI cycles for both read and write for chips
12584 * other than 5700 and 5701 which do not implement the
12585 * boundary bits.
12586 */
12587 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12588 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12589 switch (cacheline_size) {
12590 case 16:
12591 case 32:
12592 case 64:
12593 case 128:
12594 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12595 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12596 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12597 } else {
12598 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12599 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12600 }
12601 break;
12602
12603 case 256:
12604 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12605 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12606 break;
12607
12608 default:
12609 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12610 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12611 break;
12612 };
12613 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12614 switch (cacheline_size) {
12615 case 16:
12616 case 32:
12617 case 64:
12618 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12619 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12620 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12621 break;
12622 }
12623 /* fallthrough */
12624 case 128:
12625 default:
12626 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12627 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12628 break;
12629 };
12630 } else {
12631 switch (cacheline_size) {
12632 case 16:
12633 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12634 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12635 DMA_RWCTRL_WRITE_BNDRY_16);
12636 break;
12637 }
12638 /* fallthrough */
12639 case 32:
12640 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12641 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12642 DMA_RWCTRL_WRITE_BNDRY_32);
12643 break;
12644 }
12645 /* fallthrough */
12646 case 64:
12647 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12648 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12649 DMA_RWCTRL_WRITE_BNDRY_64);
12650 break;
12651 }
12652 /* fallthrough */
12653 case 128:
12654 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12655 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12656 DMA_RWCTRL_WRITE_BNDRY_128);
12657 break;
12658 }
12659 /* fallthrough */
12660 case 256:
12661 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12662 DMA_RWCTRL_WRITE_BNDRY_256);
12663 break;
12664 case 512:
12665 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12666 DMA_RWCTRL_WRITE_BNDRY_512);
12667 break;
12668 case 1024:
12669 default:
12670 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12671 DMA_RWCTRL_WRITE_BNDRY_1024);
12672 break;
12673 };
12674 }
12675
12676out:
12677 return val;
12678}
12679
12680static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12681{
12682 struct tg3_internal_buffer_desc test_desc;
12683 u32 sram_dma_descs;
12684 int i, ret;
12685
12686 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12687
12688 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12689 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12690 tw32(RDMAC_STATUS, 0);
12691 tw32(WDMAC_STATUS, 0);
12692
12693 tw32(BUFMGR_MODE, 0);
12694 tw32(FTQ_RESET, 0);
12695
12696 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12697 test_desc.addr_lo = buf_dma & 0xffffffff;
12698 test_desc.nic_mbuf = 0x00002100;
12699 test_desc.len = size;
12700
12701 /*
12702 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12703 * the *second* time the tg3 driver was getting loaded after an
12704 * initial scan.
12705 *
12706 * Broadcom tells me:
12707 * ...the DMA engine is connected to the GRC block and a DMA
12708 * reset may affect the GRC block in some unpredictable way...
12709 * The behavior of resets to individual blocks has not been tested.
12710 *
12711 * Broadcom noted the GRC reset will also reset all sub-components.
12712 */
12713 if (to_device) {
12714 test_desc.cqid_sqid = (13 << 8) | 2;
12715
12716 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12717 udelay(40);
12718 } else {
12719 test_desc.cqid_sqid = (16 << 8) | 7;
12720
12721 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12722 udelay(40);
12723 }
12724 test_desc.flags = 0x00000005;
12725
12726 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12727 u32 val;
12728
12729 val = *(((u32 *)&test_desc) + i);
12730 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12731 sram_dma_descs + (i * sizeof(u32)));
12732 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12733 }
12734 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12735
12736 if (to_device) {
12737 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12738 } else {
12739 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12740 }
12741
12742 ret = -ENODEV;
12743 for (i = 0; i < 40; i++) {
12744 u32 val;
12745
12746 if (to_device)
12747 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12748 else
12749 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12750 if ((val & 0xffff) == sram_dma_descs) {
12751 ret = 0;
12752 break;
12753 }
12754
12755 udelay(100);
12756 }
12757
12758 return ret;
12759}
12760
12761#define TEST_BUFFER_SIZE 0x2000
12762
12763static int __devinit tg3_test_dma(struct tg3 *tp)
12764{
12765 dma_addr_t buf_dma;
12766 u32 *buf, saved_dma_rwctrl;
12767 int ret;
12768
12769 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12770 if (!buf) {
12771 ret = -ENOMEM;
12772 goto out_nofree;
12773 }
12774
12775 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12776 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12777
12778 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12779
12780 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12781 /* DMA read watermark not used on PCIE */
12782 tp->dma_rwctrl |= 0x00180000;
12783 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12785 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12786 tp->dma_rwctrl |= 0x003f0000;
12787 else
12788 tp->dma_rwctrl |= 0x003f000f;
12789 } else {
12790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12791 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12792 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12793 u32 read_water = 0x7;
12794
12795 /* If the 5704 is behind the EPB bridge, we can
12796 * do the less restrictive ONE_DMA workaround for
12797 * better performance.
12798 */
12799 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12800 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12801 tp->dma_rwctrl |= 0x8000;
12802 else if (ccval == 0x6 || ccval == 0x7)
12803 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12804
12805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12806 read_water = 4;
12807 /* Set bit 23 to enable PCIX hw bug fix */
12808 tp->dma_rwctrl |=
12809 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12810 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12811 (1 << 23);
12812 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12813 /* 5780 always in PCIX mode */
12814 tp->dma_rwctrl |= 0x00144000;
12815 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12816 /* 5714 always in PCIX mode */
12817 tp->dma_rwctrl |= 0x00148000;
12818 } else {
12819 tp->dma_rwctrl |= 0x001b000f;
12820 }
12821 }
12822
12823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12824 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12825 tp->dma_rwctrl &= 0xfffffff0;
12826
12827 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12828 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12829 /* Remove this if it causes problems for some boards. */
12830 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12831
12832 /* On 5700/5701 chips, we need to set this bit.
12833 * Otherwise the chip will issue cacheline transactions
12834 * to streamable DMA memory with not all the byte
12835 * enables turned on. This is an error on several
12836 * RISC PCI controllers, in particular sparc64.
12837 *
12838 * On 5703/5704 chips, this bit has been reassigned
12839 * a different meaning. In particular, it is used
12840 * on those chips to enable a PCI-X workaround.
12841 */
12842 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12843 }
12844
12845 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12846
12847#if 0
12848 /* Unneeded, already done by tg3_get_invariants. */
12849 tg3_switch_clocks(tp);
12850#endif
12851
12852 ret = 0;
12853 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12854 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12855 goto out;
12856
12857 /* It is best to perform DMA test with maximum write burst size
12858 * to expose the 5700/5701 write DMA bug.
12859 */
12860 saved_dma_rwctrl = tp->dma_rwctrl;
12861 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12862 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12863
12864 while (1) {
12865 u32 *p = buf, i;
12866
12867 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12868 p[i] = i;
12869
12870 /* Send the buffer to the chip. */
12871 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12872 if (ret) {
12873 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12874 break;
12875 }
12876
12877#if 0
12878 /* validate data reached card RAM correctly. */
12879 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12880 u32 val;
12881 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12882 if (le32_to_cpu(val) != p[i]) {
12883 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12884 /* ret = -ENODEV here? */
12885 }
12886 p[i] = 0;
12887 }
12888#endif
12889 /* Now read it back. */
12890 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12891 if (ret) {
12892 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12893
12894 break;
12895 }
12896
12897 /* Verify it. */
12898 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12899 if (p[i] == i)
12900 continue;
12901
12902 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12903 DMA_RWCTRL_WRITE_BNDRY_16) {
12904 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12905 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12906 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12907 break;
12908 } else {
12909 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12910 ret = -ENODEV;
12911 goto out;
12912 }
12913 }
12914
12915 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12916 /* Success. */
12917 ret = 0;
12918 break;
12919 }
12920 }
12921 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12922 DMA_RWCTRL_WRITE_BNDRY_16) {
12923 static struct pci_device_id dma_wait_state_chipsets[] = {
12924 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12925 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12926 { },
12927 };
12928
12929 /* DMA test passed without adjusting DMA boundary,
12930 * now look for chipsets that are known to expose the
12931 * DMA bug without failing the test.
12932 */
12933 if (pci_dev_present(dma_wait_state_chipsets)) {
12934 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12935 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12936 }
12937 else
12938 /* Safe to use the calculated DMA boundary. */
12939 tp->dma_rwctrl = saved_dma_rwctrl;
12940
12941 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12942 }
12943
12944out:
12945 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12946out_nofree:
12947 return ret;
12948}
12949
12950static void __devinit tg3_init_link_config(struct tg3 *tp)
12951{
12952 tp->link_config.advertising =
12953 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12954 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12955 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12956 ADVERTISED_Autoneg | ADVERTISED_MII);
12957 tp->link_config.speed = SPEED_INVALID;
12958 tp->link_config.duplex = DUPLEX_INVALID;
12959 tp->link_config.autoneg = AUTONEG_ENABLE;
12960 tp->link_config.active_speed = SPEED_INVALID;
12961 tp->link_config.active_duplex = DUPLEX_INVALID;
12962 tp->link_config.phy_is_low_power = 0;
12963 tp->link_config.orig_speed = SPEED_INVALID;
12964 tp->link_config.orig_duplex = DUPLEX_INVALID;
12965 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12966}
12967
12968static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12969{
12970 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12971 tp->bufmgr_config.mbuf_read_dma_low_water =
12972 DEFAULT_MB_RDMA_LOW_WATER_5705;
12973 tp->bufmgr_config.mbuf_mac_rx_low_water =
12974 DEFAULT_MB_MACRX_LOW_WATER_5705;
12975 tp->bufmgr_config.mbuf_high_water =
12976 DEFAULT_MB_HIGH_WATER_5705;
12977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12978 tp->bufmgr_config.mbuf_mac_rx_low_water =
12979 DEFAULT_MB_MACRX_LOW_WATER_5906;
12980 tp->bufmgr_config.mbuf_high_water =
12981 DEFAULT_MB_HIGH_WATER_5906;
12982 }
12983
12984 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12985 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12986 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12987 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12988 tp->bufmgr_config.mbuf_high_water_jumbo =
12989 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12990 } else {
12991 tp->bufmgr_config.mbuf_read_dma_low_water =
12992 DEFAULT_MB_RDMA_LOW_WATER;
12993 tp->bufmgr_config.mbuf_mac_rx_low_water =
12994 DEFAULT_MB_MACRX_LOW_WATER;
12995 tp->bufmgr_config.mbuf_high_water =
12996 DEFAULT_MB_HIGH_WATER;
12997
12998 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12999 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13000 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13001 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13002 tp->bufmgr_config.mbuf_high_water_jumbo =
13003 DEFAULT_MB_HIGH_WATER_JUMBO;
13004 }
13005
13006 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13007 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13008}
13009
13010static char * __devinit tg3_phy_string(struct tg3 *tp)
13011{
13012 switch (tp->phy_id & PHY_ID_MASK) {
13013 case PHY_ID_BCM5400: return "5400";
13014 case PHY_ID_BCM5401: return "5401";
13015 case PHY_ID_BCM5411: return "5411";
13016 case PHY_ID_BCM5701: return "5701";
13017 case PHY_ID_BCM5703: return "5703";
13018 case PHY_ID_BCM5704: return "5704";
13019 case PHY_ID_BCM5705: return "5705";
13020 case PHY_ID_BCM5750: return "5750";
13021 case PHY_ID_BCM5752: return "5752";
13022 case PHY_ID_BCM5714: return "5714";
13023 case PHY_ID_BCM5780: return "5780";
13024 case PHY_ID_BCM5755: return "5755";
13025 case PHY_ID_BCM5787: return "5787";
13026 case PHY_ID_BCM5784: return "5784";
13027 case PHY_ID_BCM5756: return "5722/5756";
13028 case PHY_ID_BCM5906: return "5906";
13029 case PHY_ID_BCM5761: return "5761";
13030 case PHY_ID_BCM8002: return "8002/serdes";
13031 case 0: return "serdes";
13032 default: return "unknown";
13033 };
13034}
13035
13036static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13037{
13038 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13039 strcpy(str, "PCI Express");
13040 return str;
13041 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13042 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13043
13044 strcpy(str, "PCIX:");
13045
13046 if ((clock_ctrl == 7) ||
13047 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13048 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13049 strcat(str, "133MHz");
13050 else if (clock_ctrl == 0)
13051 strcat(str, "33MHz");
13052 else if (clock_ctrl == 2)
13053 strcat(str, "50MHz");
13054 else if (clock_ctrl == 4)
13055 strcat(str, "66MHz");
13056 else if (clock_ctrl == 6)
13057 strcat(str, "100MHz");
13058 } else {
13059 strcpy(str, "PCI:");
13060 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13061 strcat(str, "66MHz");
13062 else
13063 strcat(str, "33MHz");
13064 }
13065 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13066 strcat(str, ":32-bit");
13067 else
13068 strcat(str, ":64-bit");
13069 return str;
13070}
13071
13072static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13073{
13074 struct pci_dev *peer;
13075 unsigned int func, devnr = tp->pdev->devfn & ~7;
13076
13077 for (func = 0; func < 8; func++) {
13078 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13079 if (peer && peer != tp->pdev)
13080 break;
13081 pci_dev_put(peer);
13082 }
13083 /* 5704 can be configured in single-port mode, set peer to
13084 * tp->pdev in that case.
13085 */
13086 if (!peer) {
13087 peer = tp->pdev;
13088 return peer;
13089 }
13090
13091 /*
13092 * We don't need to keep the refcount elevated; there's no way
13093 * to remove one half of this device without removing the other
13094 */
13095 pci_dev_put(peer);
13096
13097 return peer;
13098}
13099
13100static void __devinit tg3_init_coal(struct tg3 *tp)
13101{
13102 struct ethtool_coalesce *ec = &tp->coal;
13103
13104 memset(ec, 0, sizeof(*ec));
13105 ec->cmd = ETHTOOL_GCOALESCE;
13106 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13107 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13108 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13109 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13110 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13111 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13112 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13113 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13114 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13115
13116 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13117 HOSTCC_MODE_CLRTICK_TXBD)) {
13118 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13119 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13120 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13121 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13122 }
13123
13124 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13125 ec->rx_coalesce_usecs_irq = 0;
13126 ec->tx_coalesce_usecs_irq = 0;
13127 ec->stats_block_coalesce_usecs = 0;
13128 }
13129}
13130
13131static int __devinit tg3_init_one(struct pci_dev *pdev,
13132 const struct pci_device_id *ent)
13133{
13134 static int tg3_version_printed = 0;
13135 resource_size_t tg3reg_base;
13136 unsigned long tg3reg_len;
13137 struct net_device *dev;
13138 struct tg3 *tp;
13139 int err, pm_cap;
13140 char str[40];
13141 u64 dma_mask, persist_dma_mask;
13142 DECLARE_MAC_BUF(mac);
13143
13144 if (tg3_version_printed++ == 0)
13145 printk(KERN_INFO "%s", version);
13146
13147 err = pci_enable_device(pdev);
13148 if (err) {
13149 printk(KERN_ERR PFX "Cannot enable PCI device, "
13150 "aborting.\n");
13151 return err;
13152 }
13153
13154 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13155 printk(KERN_ERR PFX "Cannot find proper PCI device "
13156 "base address, aborting.\n");
13157 err = -ENODEV;
13158 goto err_out_disable_pdev;
13159 }
13160
13161 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13162 if (err) {
13163 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13164 "aborting.\n");
13165 goto err_out_disable_pdev;
13166 }
13167
13168 pci_set_master(pdev);
13169
13170 /* Find power-management capability. */
13171 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13172 if (pm_cap == 0) {
13173 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13174 "aborting.\n");
13175 err = -EIO;
13176 goto err_out_free_res;
13177 }
13178
13179 tg3reg_base = pci_resource_start(pdev, 0);
13180 tg3reg_len = pci_resource_len(pdev, 0);
13181
13182 dev = alloc_etherdev(sizeof(*tp));
13183 if (!dev) {
13184 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13185 err = -ENOMEM;
13186 goto err_out_free_res;
13187 }
13188
13189 SET_NETDEV_DEV(dev, &pdev->dev);
13190
13191#if TG3_VLAN_TAG_USED
13192 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13193 dev->vlan_rx_register = tg3_vlan_rx_register;
13194#endif
13195
13196 tp = netdev_priv(dev);
13197 tp->pdev = pdev;
13198 tp->dev = dev;
13199 tp->pm_cap = pm_cap;
13200 tp->mac_mode = TG3_DEF_MAC_MODE;
13201 tp->rx_mode = TG3_DEF_RX_MODE;
13202 tp->tx_mode = TG3_DEF_TX_MODE;
13203
13204 if (tg3_debug > 0)
13205 tp->msg_enable = tg3_debug;
13206 else
13207 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13208
13209 /* The word/byte swap controls here control register access byte
13210 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13211 * setting below.
13212 */
13213 tp->misc_host_ctrl =
13214 MISC_HOST_CTRL_MASK_PCI_INT |
13215 MISC_HOST_CTRL_WORD_SWAP |
13216 MISC_HOST_CTRL_INDIR_ACCESS |
13217 MISC_HOST_CTRL_PCISTATE_RW;
13218
13219 /* The NONFRM (non-frame) byte/word swap controls take effect
13220 * on descriptor entries, anything which isn't packet data.
13221 *
13222 * The StrongARM chips on the board (one for tx, one for rx)
13223 * are running in big-endian mode.
13224 */
13225 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13226 GRC_MODE_WSWAP_NONFRM_DATA);
13227#ifdef __BIG_ENDIAN
13228 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13229#endif
13230 spin_lock_init(&tp->lock);
13231 spin_lock_init(&tp->indirect_lock);
13232 INIT_WORK(&tp->reset_task, tg3_reset_task);
13233
13234 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
13235 if (!tp->regs) {
13236 printk(KERN_ERR PFX "Cannot map device registers, "
13237 "aborting.\n");
13238 err = -ENOMEM;
13239 goto err_out_free_dev;
13240 }
13241
13242 tg3_init_link_config(tp);
13243
13244 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13245 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13246 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13247
13248 dev->open = tg3_open;
13249 dev->stop = tg3_close;
13250 dev->get_stats = tg3_get_stats;
13251 dev->set_multicast_list = tg3_set_rx_mode;
13252 dev->set_mac_address = tg3_set_mac_addr;
13253 dev->do_ioctl = tg3_ioctl;
13254 dev->tx_timeout = tg3_tx_timeout;
13255 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13256 dev->ethtool_ops = &tg3_ethtool_ops;
13257 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13258 dev->change_mtu = tg3_change_mtu;
13259 dev->irq = pdev->irq;
13260#ifdef CONFIG_NET_POLL_CONTROLLER
13261 dev->poll_controller = tg3_poll_controller;
13262#endif
13263
13264 err = tg3_get_invariants(tp);
13265 if (err) {
13266 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13267 "aborting.\n");
13268 goto err_out_iounmap;
13269 }
13270
13271 /* The EPB bridge inside 5714, 5715, and 5780 and any
13272 * device behind the EPB cannot support DMA addresses > 40-bit.
13273 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13274 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13275 * do DMA address check in tg3_start_xmit().
13276 */
13277 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13278 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13279 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13280 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13281#ifdef CONFIG_HIGHMEM
13282 dma_mask = DMA_64BIT_MASK;
13283#endif
13284 } else
13285 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13286
13287 /* Configure DMA attributes. */
13288 if (dma_mask > DMA_32BIT_MASK) {
13289 err = pci_set_dma_mask(pdev, dma_mask);
13290 if (!err) {
13291 dev->features |= NETIF_F_HIGHDMA;
13292 err = pci_set_consistent_dma_mask(pdev,
13293 persist_dma_mask);
13294 if (err < 0) {
13295 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13296 "DMA for consistent allocations\n");
13297 goto err_out_iounmap;
13298 }
13299 }
13300 }
13301 if (err || dma_mask == DMA_32BIT_MASK) {
13302 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13303 if (err) {
13304 printk(KERN_ERR PFX "No usable DMA configuration, "
13305 "aborting.\n");
13306 goto err_out_iounmap;
13307 }
13308 }
13309
13310 tg3_init_bufmgr_config(tp);
13311
13312 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13313 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13314 }
13315 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13316 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13317 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13318 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13319 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13320 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13321 } else {
13322 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13323 }
13324
13325 /* TSO is on by default on chips that support hardware TSO.
13326 * Firmware TSO on older chips gives lower performance, so it
13327 * is off by default, but can be enabled using ethtool.
13328 */
13329 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13330 dev->features |= NETIF_F_TSO;
13331 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
13332 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
13333 dev->features |= NETIF_F_TSO6;
13334 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13335 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13336 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13337 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13338 dev->features |= NETIF_F_TSO_ECN;
13339 }
13340
13341
13342 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13343 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13344 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13345 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13346 tp->rx_pending = 63;
13347 }
13348
13349 err = tg3_get_device_address(tp);
13350 if (err) {
13351 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13352 "aborting.\n");
13353 goto err_out_iounmap;
13354 }
13355
13356 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13357 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13358 printk(KERN_ERR PFX "Cannot find proper PCI device "
13359 "base address for APE, aborting.\n");
13360 err = -ENODEV;
13361 goto err_out_iounmap;
13362 }
13363
13364 tg3reg_base = pci_resource_start(pdev, 2);
13365 tg3reg_len = pci_resource_len(pdev, 2);
13366
13367 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
13368 if (!tp->aperegs) {
13369 printk(KERN_ERR PFX "Cannot map APE registers, "
13370 "aborting.\n");
13371 err = -ENOMEM;
13372 goto err_out_iounmap;
13373 }
13374
13375 tg3_ape_lock_init(tp);
13376 }
13377
13378 /*
13379 * Reset chip in case UNDI or EFI driver did not shutdown
13380 * DMA self test will enable WDMAC and we'll see (spurious)
13381 * pending DMA on the PCI bus at that point.
13382 */
13383 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13384 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13385 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13386 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13387 }
13388
13389 err = tg3_test_dma(tp);
13390 if (err) {
13391 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13392 goto err_out_apeunmap;
13393 }
13394
13395 /* Tigon3 can do ipv4 only... and some chips have buggy
13396 * checksumming.
13397 */
13398 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
13399 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13400 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13401 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13402 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13403 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13404 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13405 dev->features |= NETIF_F_IPV6_CSUM;
13406
13407 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13408 } else
13409 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
13410
13411 /* flow control autonegotiation is default behavior */
13412 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13413 tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
13414
13415 tg3_init_coal(tp);
13416
13417 pci_set_drvdata(pdev, dev);
13418
13419 err = register_netdev(dev);
13420 if (err) {
13421 printk(KERN_ERR PFX "Cannot register net device, "
13422 "aborting.\n");
13423 goto err_out_apeunmap;
13424 }
13425
13426 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
13427 "(%s) %s Ethernet %s\n",
13428 dev->name,
13429 tp->board_part_number,
13430 tp->pci_chip_rev_id,
13431 tg3_phy_string(tp),
13432 tg3_bus_string(tp, str),
13433 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13434 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13435 "10/100/1000Base-T")),
13436 print_mac(mac, dev->dev_addr));
13437
13438 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
13439 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
13440 dev->name,
13441 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13442 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13443 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13444 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13445 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
13446 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13447 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13448 dev->name, tp->dma_rwctrl,
13449 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13450 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13451
13452 return 0;
13453
13454err_out_apeunmap:
13455 if (tp->aperegs) {
13456 iounmap(tp->aperegs);
13457 tp->aperegs = NULL;
13458 }
13459
13460err_out_iounmap:
13461 if (tp->regs) {
13462 iounmap(tp->regs);
13463 tp->regs = NULL;
13464 }
13465
13466err_out_free_dev:
13467 free_netdev(dev);
13468
13469err_out_free_res:
13470 pci_release_regions(pdev);
13471
13472err_out_disable_pdev:
13473 pci_disable_device(pdev);
13474 pci_set_drvdata(pdev, NULL);
13475 return err;
13476}
13477
13478static void __devexit tg3_remove_one(struct pci_dev *pdev)
13479{
13480 struct net_device *dev = pci_get_drvdata(pdev);
13481
13482 if (dev) {
13483 struct tg3 *tp = netdev_priv(dev);
13484
13485 flush_scheduled_work();
13486
13487 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13488 tg3_phy_fini(tp);
13489 tg3_mdio_fini(tp);
13490 }
13491
13492 unregister_netdev(dev);
13493 if (tp->aperegs) {
13494 iounmap(tp->aperegs);
13495 tp->aperegs = NULL;
13496 }
13497 if (tp->regs) {
13498 iounmap(tp->regs);
13499 tp->regs = NULL;
13500 }
13501 free_netdev(dev);
13502 pci_release_regions(pdev);
13503 pci_disable_device(pdev);
13504 pci_set_drvdata(pdev, NULL);
13505 }
13506}
13507
13508static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13509{
13510 struct net_device *dev = pci_get_drvdata(pdev);
13511 struct tg3 *tp = netdev_priv(dev);
13512 int err;
13513
13514 /* PCI register 4 needs to be saved whether netif_running() or not.
13515 * MSI address and data need to be saved if using MSI and
13516 * netif_running().
13517 */
13518 pci_save_state(pdev);
13519
13520 if (!netif_running(dev))
13521 return 0;
13522
13523 flush_scheduled_work();
13524 tg3_phy_stop(tp);
13525 tg3_netif_stop(tp);
13526
13527 del_timer_sync(&tp->timer);
13528
13529 tg3_full_lock(tp, 1);
13530 tg3_disable_ints(tp);
13531 tg3_full_unlock(tp);
13532
13533 netif_device_detach(dev);
13534
13535 tg3_full_lock(tp, 0);
13536 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13537 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13538 tg3_full_unlock(tp);
13539
13540 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
13541 if (err) {
13542 int err2;
13543
13544 tg3_full_lock(tp, 0);
13545
13546 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13547 err2 = tg3_restart_hw(tp, 1);
13548 if (err2)
13549 goto out;
13550
13551 tp->timer.expires = jiffies + tp->timer_offset;
13552 add_timer(&tp->timer);
13553
13554 netif_device_attach(dev);
13555 tg3_netif_start(tp);
13556
13557out:
13558 tg3_full_unlock(tp);
13559
13560 if (!err2)
13561 tg3_phy_start(tp);
13562 }
13563
13564 return err;
13565}
13566
13567static int tg3_resume(struct pci_dev *pdev)
13568{
13569 struct net_device *dev = pci_get_drvdata(pdev);
13570 struct tg3 *tp = netdev_priv(dev);
13571 int err;
13572
13573 pci_restore_state(tp->pdev);
13574
13575 if (!netif_running(dev))
13576 return 0;
13577
13578 err = tg3_set_power_state(tp, PCI_D0);
13579 if (err)
13580 return err;
13581
13582 netif_device_attach(dev);
13583
13584 tg3_full_lock(tp, 0);
13585
13586 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13587 err = tg3_restart_hw(tp, 1);
13588 if (err)
13589 goto out;
13590
13591 tp->timer.expires = jiffies + tp->timer_offset;
13592 add_timer(&tp->timer);
13593
13594 tg3_netif_start(tp);
13595
13596out:
13597 tg3_full_unlock(tp);
13598
13599 if (!err)
13600 tg3_phy_start(tp);
13601
13602 return err;
13603}
13604
13605static struct pci_driver tg3_driver = {
13606 .name = DRV_MODULE_NAME,
13607 .id_table = tg3_pci_tbl,
13608 .probe = tg3_init_one,
13609 .remove = __devexit_p(tg3_remove_one),
13610 .suspend = tg3_suspend,
13611 .resume = tg3_resume
13612};
13613
13614static int __init tg3_init(void)
13615{
13616 return pci_register_driver(&tg3_driver);
13617}
13618
13619static void __exit tg3_cleanup(void)
13620{
13621 pci_unregister_driver(&tg3_driver);
13622}
13623
13624module_init(tg3_init);
13625module_exit(tg3_cleanup);
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