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1 | /* | |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
7 | * Copyright (C) 2005-2010 Broadcom Corporation. | |
8 | * | |
9 | * Firmware is: | |
10 | * Derived from proprietary unpublished source code, | |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
16 | */ | |
17 | ||
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/compiler.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/in.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/mii.h> | |
35 | #include <linux/phy.h> | |
36 | #include <linux/brcmphy.h> | |
37 | #include <linux/if_vlan.h> | |
38 | #include <linux/ip.h> | |
39 | #include <linux/tcp.h> | |
40 | #include <linux/workqueue.h> | |
41 | #include <linux/prefetch.h> | |
42 | #include <linux/dma-mapping.h> | |
43 | #include <linux/firmware.h> | |
44 | ||
45 | #include <net/checksum.h> | |
46 | #include <net/ip.h> | |
47 | ||
48 | #include <asm/system.h> | |
49 | #include <asm/io.h> | |
50 | #include <asm/byteorder.h> | |
51 | #include <asm/uaccess.h> | |
52 | ||
53 | #ifdef CONFIG_SPARC | |
54 | #include <asm/idprom.h> | |
55 | #include <asm/prom.h> | |
56 | #endif | |
57 | ||
58 | #define BAR_0 0 | |
59 | #define BAR_2 2 | |
60 | ||
61 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
62 | #define TG3_VLAN_TAG_USED 1 | |
63 | #else | |
64 | #define TG3_VLAN_TAG_USED 0 | |
65 | #endif | |
66 | ||
67 | #include "tg3.h" | |
68 | ||
69 | #define DRV_MODULE_NAME "tg3" | |
70 | #define PFX DRV_MODULE_NAME ": " | |
71 | #define DRV_MODULE_VERSION "3.106" | |
72 | #define DRV_MODULE_RELDATE "January 12, 2010" | |
73 | ||
74 | #define TG3_DEF_MAC_MODE 0 | |
75 | #define TG3_DEF_RX_MODE 0 | |
76 | #define TG3_DEF_TX_MODE 0 | |
77 | #define TG3_DEF_MSG_ENABLE \ | |
78 | (NETIF_MSG_DRV | \ | |
79 | NETIF_MSG_PROBE | \ | |
80 | NETIF_MSG_LINK | \ | |
81 | NETIF_MSG_TIMER | \ | |
82 | NETIF_MSG_IFDOWN | \ | |
83 | NETIF_MSG_IFUP | \ | |
84 | NETIF_MSG_RX_ERR | \ | |
85 | NETIF_MSG_TX_ERR) | |
86 | ||
87 | /* length of time before we decide the hardware is borked, | |
88 | * and dev->tx_timeout() should be called to fix the problem | |
89 | */ | |
90 | #define TG3_TX_TIMEOUT (5 * HZ) | |
91 | ||
92 | /* hardware minimum and maximum for a single frame's data payload */ | |
93 | #define TG3_MIN_MTU 60 | |
94 | #define TG3_MAX_MTU(tp) \ | |
95 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500) | |
96 | ||
97 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
98 | * You can't change the ring sizes, but you can change where you place | |
99 | * them in the NIC onboard memory. | |
100 | */ | |
101 | #define TG3_RX_RING_SIZE 512 | |
102 | #define TG3_DEF_RX_RING_PENDING 200 | |
103 | #define TG3_RX_JUMBO_RING_SIZE 256 | |
104 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 | |
105 | #define TG3_RSS_INDIR_TBL_SIZE 128 | |
106 | ||
107 | /* Do not place this n-ring entries value into the tp struct itself, | |
108 | * we really want to expose these constants to GCC so that modulo et | |
109 | * al. operations are done with shifts and masks instead of with | |
110 | * hw multiply/modulo instructions. Another solution would be to | |
111 | * replace things like '% foo' with '& (foo - 1)'. | |
112 | */ | |
113 | #define TG3_RX_RCB_RING_SIZE(tp) \ | |
114 | (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \ | |
115 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512) | |
116 | ||
117 | #define TG3_TX_RING_SIZE 512 | |
118 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
119 | ||
120 | #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \ | |
121 | TG3_RX_RING_SIZE) | |
122 | #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \ | |
123 | TG3_RX_JUMBO_RING_SIZE) | |
124 | #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \ | |
125 | TG3_RX_RCB_RING_SIZE(tp)) | |
126 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ | |
127 | TG3_TX_RING_SIZE) | |
128 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) | |
129 | ||
130 | #define TG3_DMA_BYTE_ENAB 64 | |
131 | ||
132 | #define TG3_RX_STD_DMA_SZ 1536 | |
133 | #define TG3_RX_JMB_DMA_SZ 9046 | |
134 | ||
135 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
136 | ||
137 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
138 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
139 | ||
140 | #define TG3_RX_STD_BUFF_RING_SIZE \ | |
141 | (sizeof(struct ring_info) * TG3_RX_RING_SIZE) | |
142 | ||
143 | #define TG3_RX_JMB_BUFF_RING_SIZE \ | |
144 | (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE) | |
145 | ||
146 | /* minimum number of free TX descriptors required to wake up TX process */ | |
147 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) | |
148 | ||
149 | #define TG3_RAW_IP_ALIGN 2 | |
150 | ||
151 | /* number of ETHTOOL_GSTATS u64's */ | |
152 | #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64)) | |
153 | ||
154 | #define TG3_NUM_TEST 6 | |
155 | ||
156 | #define FIRMWARE_TG3 "tigon/tg3.bin" | |
157 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
158 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
159 | ||
160 | static char version[] __devinitdata = | |
161 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | |
162 | ||
163 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
164 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
165 | MODULE_LICENSE("GPL"); | |
166 | MODULE_VERSION(DRV_MODULE_VERSION); | |
167 | MODULE_FIRMWARE(FIRMWARE_TG3); | |
168 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
169 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
170 | ||
171 | #define TG3_RSS_MIN_NUM_MSIX_VECS 2 | |
172 | ||
173 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ | |
174 | module_param(tg3_debug, int, 0); | |
175 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
176 | ||
177 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { | |
178 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, | |
179 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
180 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
181 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
182 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
183 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
184 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
185 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
186 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
187 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
188 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
189 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
190 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
191 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
192 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
193 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
194 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
195 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
196 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
197 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
198 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
199 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
200 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)}, | |
201 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, | |
202 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, | |
203 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)}, | |
204 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, | |
205 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)}, | |
206 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, | |
207 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
208 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
209 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
210 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
211 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
212 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
213 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
214 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
215 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
216 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
217 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, | |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, | |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, | |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, | |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, | |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
253 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, | |
254 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
255 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
256 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
258 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
259 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
260 | {} | |
261 | }; | |
262 | ||
263 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
264 | ||
265 | static const struct { | |
266 | const char string[ETH_GSTRING_LEN]; | |
267 | } ethtool_stats_keys[TG3_NUM_STATS] = { | |
268 | { "rx_octets" }, | |
269 | { "rx_fragments" }, | |
270 | { "rx_ucast_packets" }, | |
271 | { "rx_mcast_packets" }, | |
272 | { "rx_bcast_packets" }, | |
273 | { "rx_fcs_errors" }, | |
274 | { "rx_align_errors" }, | |
275 | { "rx_xon_pause_rcvd" }, | |
276 | { "rx_xoff_pause_rcvd" }, | |
277 | { "rx_mac_ctrl_rcvd" }, | |
278 | { "rx_xoff_entered" }, | |
279 | { "rx_frame_too_long_errors" }, | |
280 | { "rx_jabbers" }, | |
281 | { "rx_undersize_packets" }, | |
282 | { "rx_in_length_errors" }, | |
283 | { "rx_out_length_errors" }, | |
284 | { "rx_64_or_less_octet_packets" }, | |
285 | { "rx_65_to_127_octet_packets" }, | |
286 | { "rx_128_to_255_octet_packets" }, | |
287 | { "rx_256_to_511_octet_packets" }, | |
288 | { "rx_512_to_1023_octet_packets" }, | |
289 | { "rx_1024_to_1522_octet_packets" }, | |
290 | { "rx_1523_to_2047_octet_packets" }, | |
291 | { "rx_2048_to_4095_octet_packets" }, | |
292 | { "rx_4096_to_8191_octet_packets" }, | |
293 | { "rx_8192_to_9022_octet_packets" }, | |
294 | ||
295 | { "tx_octets" }, | |
296 | { "tx_collisions" }, | |
297 | ||
298 | { "tx_xon_sent" }, | |
299 | { "tx_xoff_sent" }, | |
300 | { "tx_flow_control" }, | |
301 | { "tx_mac_errors" }, | |
302 | { "tx_single_collisions" }, | |
303 | { "tx_mult_collisions" }, | |
304 | { "tx_deferred" }, | |
305 | { "tx_excessive_collisions" }, | |
306 | { "tx_late_collisions" }, | |
307 | { "tx_collide_2times" }, | |
308 | { "tx_collide_3times" }, | |
309 | { "tx_collide_4times" }, | |
310 | { "tx_collide_5times" }, | |
311 | { "tx_collide_6times" }, | |
312 | { "tx_collide_7times" }, | |
313 | { "tx_collide_8times" }, | |
314 | { "tx_collide_9times" }, | |
315 | { "tx_collide_10times" }, | |
316 | { "tx_collide_11times" }, | |
317 | { "tx_collide_12times" }, | |
318 | { "tx_collide_13times" }, | |
319 | { "tx_collide_14times" }, | |
320 | { "tx_collide_15times" }, | |
321 | { "tx_ucast_packets" }, | |
322 | { "tx_mcast_packets" }, | |
323 | { "tx_bcast_packets" }, | |
324 | { "tx_carrier_sense_errors" }, | |
325 | { "tx_discards" }, | |
326 | { "tx_errors" }, | |
327 | ||
328 | { "dma_writeq_full" }, | |
329 | { "dma_write_prioq_full" }, | |
330 | { "rxbds_empty" }, | |
331 | { "rx_discards" }, | |
332 | { "rx_errors" }, | |
333 | { "rx_threshold_hit" }, | |
334 | ||
335 | { "dma_readq_full" }, | |
336 | { "dma_read_prioq_full" }, | |
337 | { "tx_comp_queue_full" }, | |
338 | ||
339 | { "ring_set_send_prod_index" }, | |
340 | { "ring_status_update" }, | |
341 | { "nic_irqs" }, | |
342 | { "nic_avoided_irqs" }, | |
343 | { "nic_tx_threshold_hit" } | |
344 | }; | |
345 | ||
346 | static const struct { | |
347 | const char string[ETH_GSTRING_LEN]; | |
348 | } ethtool_test_keys[TG3_NUM_TEST] = { | |
349 | { "nvram test (online) " }, | |
350 | { "link test (online) " }, | |
351 | { "register test (offline)" }, | |
352 | { "memory test (offline)" }, | |
353 | { "loopback test (offline)" }, | |
354 | { "interrupt test (offline)" }, | |
355 | }; | |
356 | ||
357 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) | |
358 | { | |
359 | writel(val, tp->regs + off); | |
360 | } | |
361 | ||
362 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
363 | { | |
364 | return (readl(tp->regs + off)); | |
365 | } | |
366 | ||
367 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) | |
368 | { | |
369 | writel(val, tp->aperegs + off); | |
370 | } | |
371 | ||
372 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
373 | { | |
374 | return (readl(tp->aperegs + off)); | |
375 | } | |
376 | ||
377 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) | |
378 | { | |
379 | unsigned long flags; | |
380 | ||
381 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
382 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
383 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
384 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
385 | } | |
386 | ||
387 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
388 | { | |
389 | writel(val, tp->regs + off); | |
390 | readl(tp->regs + off); | |
391 | } | |
392 | ||
393 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) | |
394 | { | |
395 | unsigned long flags; | |
396 | u32 val; | |
397 | ||
398 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
399 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
400 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
401 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
402 | return val; | |
403 | } | |
404 | ||
405 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
406 | { | |
407 | unsigned long flags; | |
408 | ||
409 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
410 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
411 | TG3_64BIT_REG_LOW, val); | |
412 | return; | |
413 | } | |
414 | if (off == TG3_RX_STD_PROD_IDX_REG) { | |
415 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + | |
416 | TG3_64BIT_REG_LOW, val); | |
417 | return; | |
418 | } | |
419 | ||
420 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
421 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
422 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
423 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
424 | ||
425 | /* In indirect mode when disabling interrupts, we also need | |
426 | * to clear the interrupt bit in the GRC local ctrl register. | |
427 | */ | |
428 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
429 | (val == 0x1)) { | |
430 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
431 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
432 | } | |
433 | } | |
434 | ||
435 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
436 | { | |
437 | unsigned long flags; | |
438 | u32 val; | |
439 | ||
440 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
441 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
442 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
443 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
444 | return val; | |
445 | } | |
446 | ||
447 | /* usec_wait specifies the wait time in usec when writing to certain registers | |
448 | * where it is unsafe to read back the register without some delay. | |
449 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
450 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
451 | */ | |
452 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
453 | { | |
454 | if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) || | |
455 | (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
456 | /* Non-posted methods */ | |
457 | tp->write32(tp, off, val); | |
458 | else { | |
459 | /* Posted method */ | |
460 | tg3_write32(tp, off, val); | |
461 | if (usec_wait) | |
462 | udelay(usec_wait); | |
463 | tp->read32(tp, off); | |
464 | } | |
465 | /* Wait again after the read for the posted method to guarantee that | |
466 | * the wait time is met. | |
467 | */ | |
468 | if (usec_wait) | |
469 | udelay(usec_wait); | |
470 | } | |
471 | ||
472 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) | |
473 | { | |
474 | tp->write32_mbox(tp, off, val); | |
475 | if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && | |
476 | !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
477 | tp->read32_mbox(tp, off); | |
478 | } | |
479 | ||
480 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) | |
481 | { | |
482 | void __iomem *mbox = tp->regs + off; | |
483 | writel(val, mbox); | |
484 | if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) | |
485 | writel(val, mbox); | |
486 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
487 | readl(mbox); | |
488 | } | |
489 | ||
490 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) | |
491 | { | |
492 | return (readl(tp->regs + off + GRCMBOX_BASE)); | |
493 | } | |
494 | ||
495 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
496 | { | |
497 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
498 | } | |
499 | ||
500 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) | |
501 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) | |
502 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) | |
503 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
504 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
505 | ||
506 | #define tw32(reg,val) tp->write32(tp, reg, val) | |
507 | #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0) | |
508 | #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us)) | |
509 | #define tr32(reg) tp->read32(tp, reg) | |
510 | ||
511 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
512 | { | |
513 | unsigned long flags; | |
514 | ||
515 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && | |
516 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | |
517 | return; | |
518 | ||
519 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
520 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { | |
521 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
522 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
523 | ||
524 | /* Always leave this as zero. */ | |
525 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
526 | } else { | |
527 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
528 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
529 | ||
530 | /* Always leave this as zero. */ | |
531 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
532 | } | |
533 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
534 | } | |
535 | ||
536 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) | |
537 | { | |
538 | unsigned long flags; | |
539 | ||
540 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && | |
541 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | |
542 | *val = 0; | |
543 | return; | |
544 | } | |
545 | ||
546 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
547 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { | |
548 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
549 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
550 | ||
551 | /* Always leave this as zero. */ | |
552 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
553 | } else { | |
554 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
555 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
556 | ||
557 | /* Always leave this as zero. */ | |
558 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
559 | } | |
560 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
561 | } | |
562 | ||
563 | static void tg3_ape_lock_init(struct tg3 *tp) | |
564 | { | |
565 | int i; | |
566 | ||
567 | /* Make sure the driver hasn't any stale locks. */ | |
568 | for (i = 0; i < 8; i++) | |
569 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i, | |
570 | APE_LOCK_GRANT_DRIVER); | |
571 | } | |
572 | ||
573 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
574 | { | |
575 | int i, off; | |
576 | int ret = 0; | |
577 | u32 status; | |
578 | ||
579 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
580 | return 0; | |
581 | ||
582 | switch (locknum) { | |
583 | case TG3_APE_LOCK_GRC: | |
584 | case TG3_APE_LOCK_MEM: | |
585 | break; | |
586 | default: | |
587 | return -EINVAL; | |
588 | } | |
589 | ||
590 | off = 4 * locknum; | |
591 | ||
592 | tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER); | |
593 | ||
594 | /* Wait for up to 1 millisecond to acquire lock. */ | |
595 | for (i = 0; i < 100; i++) { | |
596 | status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off); | |
597 | if (status == APE_LOCK_GRANT_DRIVER) | |
598 | break; | |
599 | udelay(10); | |
600 | } | |
601 | ||
602 | if (status != APE_LOCK_GRANT_DRIVER) { | |
603 | /* Revoke the lock request. */ | |
604 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, | |
605 | APE_LOCK_GRANT_DRIVER); | |
606 | ||
607 | ret = -EBUSY; | |
608 | } | |
609 | ||
610 | return ret; | |
611 | } | |
612 | ||
613 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
614 | { | |
615 | int off; | |
616 | ||
617 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
618 | return; | |
619 | ||
620 | switch (locknum) { | |
621 | case TG3_APE_LOCK_GRC: | |
622 | case TG3_APE_LOCK_MEM: | |
623 | break; | |
624 | default: | |
625 | return; | |
626 | } | |
627 | ||
628 | off = 4 * locknum; | |
629 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER); | |
630 | } | |
631 | ||
632 | static void tg3_disable_ints(struct tg3 *tp) | |
633 | { | |
634 | int i; | |
635 | ||
636 | tw32(TG3PCI_MISC_HOST_CTRL, | |
637 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
638 | for (i = 0; i < tp->irq_max; i++) | |
639 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
640 | } | |
641 | ||
642 | static void tg3_enable_ints(struct tg3 *tp) | |
643 | { | |
644 | int i; | |
645 | ||
646 | tp->irq_sync = 0; | |
647 | wmb(); | |
648 | ||
649 | tw32(TG3PCI_MISC_HOST_CTRL, | |
650 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
651 | ||
652 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; | |
653 | for (i = 0; i < tp->irq_cnt; i++) { | |
654 | struct tg3_napi *tnapi = &tp->napi[i]; | |
655 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
656 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
657 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
658 | ||
659 | tp->coal_now |= tnapi->coal_now; | |
660 | } | |
661 | ||
662 | /* Force an initial interrupt */ | |
663 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
664 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) | |
665 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
666 | else | |
667 | tw32(HOSTCC_MODE, tp->coal_now); | |
668 | ||
669 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
670 | } | |
671 | ||
672 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) | |
673 | { | |
674 | struct tg3 *tp = tnapi->tp; | |
675 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
676 | unsigned int work_exists = 0; | |
677 | ||
678 | /* check for phy events */ | |
679 | if (!(tp->tg3_flags & | |
680 | (TG3_FLAG_USE_LINKCHG_REG | | |
681 | TG3_FLAG_POLL_SERDES))) { | |
682 | if (sblk->status & SD_STATUS_LINK_CHG) | |
683 | work_exists = 1; | |
684 | } | |
685 | /* check for RX/TX work to do */ | |
686 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || | |
687 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) | |
688 | work_exists = 1; | |
689 | ||
690 | return work_exists; | |
691 | } | |
692 | ||
693 | /* tg3_int_reenable | |
694 | * similar to tg3_enable_ints, but it accurately determines whether there | |
695 | * is new work pending and can return without flushing the PIO write | |
696 | * which reenables interrupts | |
697 | */ | |
698 | static void tg3_int_reenable(struct tg3_napi *tnapi) | |
699 | { | |
700 | struct tg3 *tp = tnapi->tp; | |
701 | ||
702 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
703 | mmiowb(); | |
704 | ||
705 | /* When doing tagged status, this work check is unnecessary. | |
706 | * The last_tag we write above tells the chip which piece of | |
707 | * work we've completed. | |
708 | */ | |
709 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
710 | tg3_has_work(tnapi)) | |
711 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
712 | HOSTCC_MODE_ENABLE | tnapi->coal_now); | |
713 | } | |
714 | ||
715 | static void tg3_napi_disable(struct tg3 *tp) | |
716 | { | |
717 | int i; | |
718 | ||
719 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
720 | napi_disable(&tp->napi[i].napi); | |
721 | } | |
722 | ||
723 | static void tg3_napi_enable(struct tg3 *tp) | |
724 | { | |
725 | int i; | |
726 | ||
727 | for (i = 0; i < tp->irq_cnt; i++) | |
728 | napi_enable(&tp->napi[i].napi); | |
729 | } | |
730 | ||
731 | static inline void tg3_netif_stop(struct tg3 *tp) | |
732 | { | |
733 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
734 | tg3_napi_disable(tp); | |
735 | netif_tx_disable(tp->dev); | |
736 | } | |
737 | ||
738 | static inline void tg3_netif_start(struct tg3 *tp) | |
739 | { | |
740 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
741 | * appropriate so long as all callers are assured to | |
742 | * have free tx slots (such as after tg3_init_hw) | |
743 | */ | |
744 | netif_tx_wake_all_queues(tp->dev); | |
745 | ||
746 | tg3_napi_enable(tp); | |
747 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
748 | tg3_enable_ints(tp); | |
749 | } | |
750 | ||
751 | static void tg3_switch_clocks(struct tg3 *tp) | |
752 | { | |
753 | u32 clock_ctrl; | |
754 | u32 orig_clock_ctrl; | |
755 | ||
756 | if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || | |
757 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
758 | return; | |
759 | ||
760 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); | |
761 | ||
762 | orig_clock_ctrl = clock_ctrl; | |
763 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
764 | CLOCK_CTRL_CLKRUN_OENABLE | | |
765 | 0x1f); | |
766 | tp->pci_clock_ctrl = clock_ctrl; | |
767 | ||
768 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
769 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { | |
770 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
771 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
772 | } | |
773 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
774 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
775 | clock_ctrl | | |
776 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
777 | 40); | |
778 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
779 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
780 | 40); | |
781 | } | |
782 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); | |
783 | } | |
784 | ||
785 | #define PHY_BUSY_LOOPS 5000 | |
786 | ||
787 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
788 | { | |
789 | u32 frame_val; | |
790 | unsigned int loops; | |
791 | int ret; | |
792 | ||
793 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
794 | tw32_f(MAC_MI_MODE, | |
795 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
796 | udelay(80); | |
797 | } | |
798 | ||
799 | *val = 0x0; | |
800 | ||
801 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & | |
802 | MI_COM_PHY_ADDR_MASK); | |
803 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
804 | MI_COM_REG_ADDR_MASK); | |
805 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
806 | ||
807 | tw32_f(MAC_MI_COM, frame_val); | |
808 | ||
809 | loops = PHY_BUSY_LOOPS; | |
810 | while (loops != 0) { | |
811 | udelay(10); | |
812 | frame_val = tr32(MAC_MI_COM); | |
813 | ||
814 | if ((frame_val & MI_COM_BUSY) == 0) { | |
815 | udelay(5); | |
816 | frame_val = tr32(MAC_MI_COM); | |
817 | break; | |
818 | } | |
819 | loops -= 1; | |
820 | } | |
821 | ||
822 | ret = -EBUSY; | |
823 | if (loops != 0) { | |
824 | *val = frame_val & MI_COM_DATA_MASK; | |
825 | ret = 0; | |
826 | } | |
827 | ||
828 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
829 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
830 | udelay(80); | |
831 | } | |
832 | ||
833 | return ret; | |
834 | } | |
835 | ||
836 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
837 | { | |
838 | u32 frame_val; | |
839 | unsigned int loops; | |
840 | int ret; | |
841 | ||
842 | if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && | |
843 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) | |
844 | return 0; | |
845 | ||
846 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
847 | tw32_f(MAC_MI_MODE, | |
848 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
849 | udelay(80); | |
850 | } | |
851 | ||
852 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & | |
853 | MI_COM_PHY_ADDR_MASK); | |
854 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
855 | MI_COM_REG_ADDR_MASK); | |
856 | frame_val |= (val & MI_COM_DATA_MASK); | |
857 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
858 | ||
859 | tw32_f(MAC_MI_COM, frame_val); | |
860 | ||
861 | loops = PHY_BUSY_LOOPS; | |
862 | while (loops != 0) { | |
863 | udelay(10); | |
864 | frame_val = tr32(MAC_MI_COM); | |
865 | if ((frame_val & MI_COM_BUSY) == 0) { | |
866 | udelay(5); | |
867 | frame_val = tr32(MAC_MI_COM); | |
868 | break; | |
869 | } | |
870 | loops -= 1; | |
871 | } | |
872 | ||
873 | ret = -EBUSY; | |
874 | if (loops != 0) | |
875 | ret = 0; | |
876 | ||
877 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
878 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
879 | udelay(80); | |
880 | } | |
881 | ||
882 | return ret; | |
883 | } | |
884 | ||
885 | static int tg3_bmcr_reset(struct tg3 *tp) | |
886 | { | |
887 | u32 phy_control; | |
888 | int limit, err; | |
889 | ||
890 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
891 | * clears or we time out. | |
892 | */ | |
893 | phy_control = BMCR_RESET; | |
894 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
895 | if (err != 0) | |
896 | return -EBUSY; | |
897 | ||
898 | limit = 5000; | |
899 | while (limit--) { | |
900 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
901 | if (err != 0) | |
902 | return -EBUSY; | |
903 | ||
904 | if ((phy_control & BMCR_RESET) == 0) { | |
905 | udelay(40); | |
906 | break; | |
907 | } | |
908 | udelay(10); | |
909 | } | |
910 | if (limit < 0) | |
911 | return -EBUSY; | |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
916 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) | |
917 | { | |
918 | struct tg3 *tp = bp->priv; | |
919 | u32 val; | |
920 | ||
921 | spin_lock_bh(&tp->lock); | |
922 | ||
923 | if (tg3_readphy(tp, reg, &val)) | |
924 | val = -EIO; | |
925 | ||
926 | spin_unlock_bh(&tp->lock); | |
927 | ||
928 | return val; | |
929 | } | |
930 | ||
931 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
932 | { | |
933 | struct tg3 *tp = bp->priv; | |
934 | u32 ret = 0; | |
935 | ||
936 | spin_lock_bh(&tp->lock); | |
937 | ||
938 | if (tg3_writephy(tp, reg, val)) | |
939 | ret = -EIO; | |
940 | ||
941 | spin_unlock_bh(&tp->lock); | |
942 | ||
943 | return ret; | |
944 | } | |
945 | ||
946 | static int tg3_mdio_reset(struct mii_bus *bp) | |
947 | { | |
948 | return 0; | |
949 | } | |
950 | ||
951 | static void tg3_mdio_config_5785(struct tg3 *tp) | |
952 | { | |
953 | u32 val; | |
954 | struct phy_device *phydev; | |
955 | ||
956 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
957 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
958 | case TG3_PHY_ID_BCM50610: | |
959 | case TG3_PHY_ID_BCM50610M: | |
960 | val = MAC_PHYCFG2_50610_LED_MODES; | |
961 | break; | |
962 | case TG3_PHY_ID_BCMAC131: | |
963 | val = MAC_PHYCFG2_AC131_LED_MODES; | |
964 | break; | |
965 | case TG3_PHY_ID_RTL8211C: | |
966 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; | |
967 | break; | |
968 | case TG3_PHY_ID_RTL8201E: | |
969 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; | |
970 | break; | |
971 | default: | |
972 | return; | |
973 | } | |
974 | ||
975 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
976 | tw32(MAC_PHYCFG2, val); | |
977 | ||
978 | val = tr32(MAC_PHYCFG1); | |
979 | val &= ~(MAC_PHYCFG1_RGMII_INT | | |
980 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
981 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
982 | tw32(MAC_PHYCFG1, val); | |
983 | ||
984 | return; | |
985 | } | |
986 | ||
987 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) | |
988 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | | |
989 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
990 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
991 | MAC_PHYCFG2_ACT_MASK_MASK | | |
992 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
993 | MAC_PHYCFG2_INBAND_ENABLE; | |
994 | ||
995 | tw32(MAC_PHYCFG2, val); | |
996 | ||
997 | val = tr32(MAC_PHYCFG1); | |
998 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
999 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
1000 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) { | |
1001 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1002 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; | |
1003 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1004 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; | |
1005 | } | |
1006 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | | |
1007 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1008 | tw32(MAC_PHYCFG1, val); | |
1009 | ||
1010 | val = tr32(MAC_EXT_RGMII_MODE); | |
1011 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1012 | MAC_RGMII_MODE_RX_QUALITY | | |
1013 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1014 | MAC_RGMII_MODE_RX_ENG_DET | | |
1015 | MAC_RGMII_MODE_TX_ENABLE | | |
1016 | MAC_RGMII_MODE_TX_LOWPWR | | |
1017 | MAC_RGMII_MODE_TX_RESET); | |
1018 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) { | |
1019 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1020 | val |= MAC_RGMII_MODE_RX_INT_B | | |
1021 | MAC_RGMII_MODE_RX_QUALITY | | |
1022 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1023 | MAC_RGMII_MODE_RX_ENG_DET; | |
1024 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1025 | val |= MAC_RGMII_MODE_TX_ENABLE | | |
1026 | MAC_RGMII_MODE_TX_LOWPWR | | |
1027 | MAC_RGMII_MODE_TX_RESET; | |
1028 | } | |
1029 | tw32(MAC_EXT_RGMII_MODE, val); | |
1030 | } | |
1031 | ||
1032 | static void tg3_mdio_start(struct tg3 *tp) | |
1033 | { | |
1034 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; | |
1035 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1036 | udelay(80); | |
1037 | ||
1038 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
1039 | u32 funcnum, is_serdes; | |
1040 | ||
1041 | funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC; | |
1042 | if (funcnum) | |
1043 | tp->phy_addr = 2; | |
1044 | else | |
1045 | tp->phy_addr = 1; | |
1046 | ||
1047 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) | |
1048 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1049 | else | |
1050 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1051 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
1052 | if (is_serdes) | |
1053 | tp->phy_addr += 7; | |
1054 | } else | |
1055 | tp->phy_addr = TG3_PHY_MII_ADDR; | |
1056 | ||
1057 | if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && | |
1058 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1059 | tg3_mdio_config_5785(tp); | |
1060 | } | |
1061 | ||
1062 | static int tg3_mdio_init(struct tg3 *tp) | |
1063 | { | |
1064 | int i; | |
1065 | u32 reg; | |
1066 | struct phy_device *phydev; | |
1067 | ||
1068 | tg3_mdio_start(tp); | |
1069 | ||
1070 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) || | |
1071 | (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)) | |
1072 | return 0; | |
1073 | ||
1074 | tp->mdio_bus = mdiobus_alloc(); | |
1075 | if (tp->mdio_bus == NULL) | |
1076 | return -ENOMEM; | |
1077 | ||
1078 | tp->mdio_bus->name = "tg3 mdio bus"; | |
1079 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
1080 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); | |
1081 | tp->mdio_bus->priv = tp; | |
1082 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1083 | tp->mdio_bus->read = &tg3_mdio_read; | |
1084 | tp->mdio_bus->write = &tg3_mdio_write; | |
1085 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
1086 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); | |
1087 | tp->mdio_bus->irq = &tp->mdio_irq[0]; | |
1088 | ||
1089 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
1090 | tp->mdio_bus->irq[i] = PHY_POLL; | |
1091 | ||
1092 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1093 | * Unfortunately, it does not ensure the PHY is powered up before | |
1094 | * accessing the PHY ID registers. A chip reset is the | |
1095 | * quickest way to bring the device back to an operational state.. | |
1096 | */ | |
1097 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1098 | tg3_bmcr_reset(tp); | |
1099 | ||
1100 | i = mdiobus_register(tp->mdio_bus); | |
1101 | if (i) { | |
1102 | printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n", | |
1103 | tp->dev->name, i); | |
1104 | mdiobus_free(tp->mdio_bus); | |
1105 | return i; | |
1106 | } | |
1107 | ||
1108 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
1109 | ||
1110 | if (!phydev || !phydev->drv) { | |
1111 | printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name); | |
1112 | mdiobus_unregister(tp->mdio_bus); | |
1113 | mdiobus_free(tp->mdio_bus); | |
1114 | return -ENODEV; | |
1115 | } | |
1116 | ||
1117 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
1118 | case TG3_PHY_ID_BCM57780: | |
1119 | phydev->interface = PHY_INTERFACE_MODE_GMII; | |
1120 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; | |
1121 | break; | |
1122 | case TG3_PHY_ID_BCM50610: | |
1123 | case TG3_PHY_ID_BCM50610M: | |
1124 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | | |
1125 | PHY_BRCM_RX_REFCLK_UNUSED | | |
1126 | PHY_BRCM_DIS_TXCRXC_NOENRGY | | |
1127 | PHY_BRCM_AUTO_PWRDWN_ENABLE; | |
1128 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) | |
1129 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; | |
1130 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1131 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; | |
1132 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1133 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; | |
1134 | /* fallthru */ | |
1135 | case TG3_PHY_ID_RTL8211C: | |
1136 | phydev->interface = PHY_INTERFACE_MODE_RGMII; | |
1137 | break; | |
1138 | case TG3_PHY_ID_RTL8201E: | |
1139 | case TG3_PHY_ID_BCMAC131: | |
1140 | phydev->interface = PHY_INTERFACE_MODE_MII; | |
1141 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; | |
1142 | tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; | |
1143 | break; | |
1144 | } | |
1145 | ||
1146 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED; | |
1147 | ||
1148 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1149 | tg3_mdio_config_5785(tp); | |
1150 | ||
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | static void tg3_mdio_fini(struct tg3 *tp) | |
1155 | { | |
1156 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
1157 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED; | |
1158 | mdiobus_unregister(tp->mdio_bus); | |
1159 | mdiobus_free(tp->mdio_bus); | |
1160 | } | |
1161 | } | |
1162 | ||
1163 | /* tp->lock is held. */ | |
1164 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1165 | { | |
1166 | u32 val; | |
1167 | ||
1168 | val = tr32(GRC_RX_CPU_EVENT); | |
1169 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1170 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1171 | ||
1172 | tp->last_event_jiffies = jiffies; | |
1173 | } | |
1174 | ||
1175 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1176 | ||
1177 | /* tp->lock is held. */ | |
1178 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1179 | { | |
1180 | int i; | |
1181 | unsigned int delay_cnt; | |
1182 | long time_remain; | |
1183 | ||
1184 | /* If enough time has passed, no wait is necessary. */ | |
1185 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1186 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1187 | (long)jiffies; | |
1188 | if (time_remain < 0) | |
1189 | return; | |
1190 | ||
1191 | /* Check if we can shorten the wait time. */ | |
1192 | delay_cnt = jiffies_to_usecs(time_remain); | |
1193 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1194 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1195 | delay_cnt = (delay_cnt >> 3) + 1; | |
1196 | ||
1197 | for (i = 0; i < delay_cnt; i++) { | |
1198 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) | |
1199 | break; | |
1200 | udelay(8); | |
1201 | } | |
1202 | } | |
1203 | ||
1204 | /* tp->lock is held. */ | |
1205 | static void tg3_ump_link_report(struct tg3 *tp) | |
1206 | { | |
1207 | u32 reg; | |
1208 | u32 val; | |
1209 | ||
1210 | if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
1211 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
1212 | return; | |
1213 | ||
1214 | tg3_wait_for_event_ack(tp); | |
1215 | ||
1216 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1217 | ||
1218 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1219 | ||
1220 | val = 0; | |
1221 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1222 | val = reg << 16; | |
1223 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1224 | val |= (reg & 0xffff); | |
1225 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1226 | ||
1227 | val = 0; | |
1228 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1229 | val = reg << 16; | |
1230 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1231 | val |= (reg & 0xffff); | |
1232 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1233 | ||
1234 | val = 0; | |
1235 | if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) { | |
1236 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) | |
1237 | val = reg << 16; | |
1238 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1239 | val |= (reg & 0xffff); | |
1240 | } | |
1241 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1242 | ||
1243 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1244 | val = reg << 16; | |
1245 | else | |
1246 | val = 0; | |
1247 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1248 | ||
1249 | tg3_generate_fw_event(tp); | |
1250 | } | |
1251 | ||
1252 | static void tg3_link_report(struct tg3 *tp) | |
1253 | { | |
1254 | if (!netif_carrier_ok(tp->dev)) { | |
1255 | if (netif_msg_link(tp)) | |
1256 | printk(KERN_INFO PFX "%s: Link is down.\n", | |
1257 | tp->dev->name); | |
1258 | tg3_ump_link_report(tp); | |
1259 | } else if (netif_msg_link(tp)) { | |
1260 | printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n", | |
1261 | tp->dev->name, | |
1262 | (tp->link_config.active_speed == SPEED_1000 ? | |
1263 | 1000 : | |
1264 | (tp->link_config.active_speed == SPEED_100 ? | |
1265 | 100 : 10)), | |
1266 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1267 | "full" : "half")); | |
1268 | ||
1269 | printk(KERN_INFO PFX | |
1270 | "%s: Flow control is %s for TX and %s for RX.\n", | |
1271 | tp->dev->name, | |
1272 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1273 | "on" : "off", | |
1274 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1275 | "on" : "off"); | |
1276 | tg3_ump_link_report(tp); | |
1277 | } | |
1278 | } | |
1279 | ||
1280 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1281 | { | |
1282 | u16 miireg; | |
1283 | ||
1284 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) | |
1285 | miireg = ADVERTISE_PAUSE_CAP; | |
1286 | else if (flow_ctrl & FLOW_CTRL_TX) | |
1287 | miireg = ADVERTISE_PAUSE_ASYM; | |
1288 | else if (flow_ctrl & FLOW_CTRL_RX) | |
1289 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
1290 | else | |
1291 | miireg = 0; | |
1292 | ||
1293 | return miireg; | |
1294 | } | |
1295 | ||
1296 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1297 | { | |
1298 | u16 miireg; | |
1299 | ||
1300 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) | |
1301 | miireg = ADVERTISE_1000XPAUSE; | |
1302 | else if (flow_ctrl & FLOW_CTRL_TX) | |
1303 | miireg = ADVERTISE_1000XPSE_ASYM; | |
1304 | else if (flow_ctrl & FLOW_CTRL_RX) | |
1305 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; | |
1306 | else | |
1307 | miireg = 0; | |
1308 | ||
1309 | return miireg; | |
1310 | } | |
1311 | ||
1312 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) | |
1313 | { | |
1314 | u8 cap = 0; | |
1315 | ||
1316 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1317 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1318 | if (rmtadv & LPA_1000XPAUSE) | |
1319 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1320 | else if (rmtadv & LPA_1000XPAUSE_ASYM) | |
1321 | cap = FLOW_CTRL_RX; | |
1322 | } else { | |
1323 | if (rmtadv & LPA_1000XPAUSE) | |
1324 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1325 | } | |
1326 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1327 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
1328 | cap = FLOW_CTRL_TX; | |
1329 | } | |
1330 | ||
1331 | return cap; | |
1332 | } | |
1333 | ||
1334 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) | |
1335 | { | |
1336 | u8 autoneg; | |
1337 | u8 flowctrl = 0; | |
1338 | u32 old_rx_mode = tp->rx_mode; | |
1339 | u32 old_tx_mode = tp->tx_mode; | |
1340 | ||
1341 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) | |
1342 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; | |
1343 | else | |
1344 | autoneg = tp->link_config.autoneg; | |
1345 | ||
1346 | if (autoneg == AUTONEG_ENABLE && | |
1347 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { | |
1348 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) | |
1349 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); | |
1350 | else | |
1351 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); | |
1352 | } else | |
1353 | flowctrl = tp->link_config.flowctrl; | |
1354 | ||
1355 | tp->link_config.active_flowctrl = flowctrl; | |
1356 | ||
1357 | if (flowctrl & FLOW_CTRL_RX) | |
1358 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; | |
1359 | else | |
1360 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1361 | ||
1362 | if (old_rx_mode != tp->rx_mode) | |
1363 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
1364 | ||
1365 | if (flowctrl & FLOW_CTRL_TX) | |
1366 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; | |
1367 | else | |
1368 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1369 | ||
1370 | if (old_tx_mode != tp->tx_mode) | |
1371 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
1372 | } | |
1373 | ||
1374 | static void tg3_adjust_link(struct net_device *dev) | |
1375 | { | |
1376 | u8 oldflowctrl, linkmesg = 0; | |
1377 | u32 mac_mode, lcl_adv, rmt_adv; | |
1378 | struct tg3 *tp = netdev_priv(dev); | |
1379 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
1380 | ||
1381 | spin_lock_bh(&tp->lock); | |
1382 | ||
1383 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1384 | MAC_MODE_HALF_DUPLEX); | |
1385 | ||
1386 | oldflowctrl = tp->link_config.active_flowctrl; | |
1387 | ||
1388 | if (phydev->link) { | |
1389 | lcl_adv = 0; | |
1390 | rmt_adv = 0; | |
1391 | ||
1392 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1393 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
1394 | else if (phydev->speed == SPEED_1000 || | |
1395 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
1396 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1397 | else | |
1398 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
1399 | ||
1400 | if (phydev->duplex == DUPLEX_HALF) | |
1401 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1402 | else { | |
1403 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1404 | tp->link_config.flowctrl); | |
1405 | ||
1406 | if (phydev->pause) | |
1407 | rmt_adv = LPA_PAUSE_CAP; | |
1408 | if (phydev->asym_pause) | |
1409 | rmt_adv |= LPA_PAUSE_ASYM; | |
1410 | } | |
1411 | ||
1412 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1413 | } else | |
1414 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1415 | ||
1416 | if (mac_mode != tp->mac_mode) { | |
1417 | tp->mac_mode = mac_mode; | |
1418 | tw32_f(MAC_MODE, tp->mac_mode); | |
1419 | udelay(40); | |
1420 | } | |
1421 | ||
1422 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
1423 | if (phydev->speed == SPEED_10) | |
1424 | tw32(MAC_MI_STAT, | |
1425 | MAC_MI_STAT_10MBPS_MODE | | |
1426 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1427 | else | |
1428 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1429 | } | |
1430 | ||
1431 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) | |
1432 | tw32(MAC_TX_LENGTHS, | |
1433 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1434 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1435 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1436 | else | |
1437 | tw32(MAC_TX_LENGTHS, | |
1438 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1439 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1440 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1441 | ||
1442 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1443 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1444 | phydev->speed != tp->link_config.active_speed || | |
1445 | phydev->duplex != tp->link_config.active_duplex || | |
1446 | oldflowctrl != tp->link_config.active_flowctrl) | |
1447 | linkmesg = 1; | |
1448 | ||
1449 | tp->link_config.active_speed = phydev->speed; | |
1450 | tp->link_config.active_duplex = phydev->duplex; | |
1451 | ||
1452 | spin_unlock_bh(&tp->lock); | |
1453 | ||
1454 | if (linkmesg) | |
1455 | tg3_link_report(tp); | |
1456 | } | |
1457 | ||
1458 | static int tg3_phy_init(struct tg3 *tp) | |
1459 | { | |
1460 | struct phy_device *phydev; | |
1461 | ||
1462 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) | |
1463 | return 0; | |
1464 | ||
1465 | /* Bring the PHY back to a known state. */ | |
1466 | tg3_bmcr_reset(tp); | |
1467 | ||
1468 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
1469 | ||
1470 | /* Attach the MAC to the PHY. */ | |
1471 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, | |
1472 | phydev->dev_flags, phydev->interface); | |
1473 | if (IS_ERR(phydev)) { | |
1474 | printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name); | |
1475 | return PTR_ERR(phydev); | |
1476 | } | |
1477 | ||
1478 | /* Mask with MAC supported features. */ | |
1479 | switch (phydev->interface) { | |
1480 | case PHY_INTERFACE_MODE_GMII: | |
1481 | case PHY_INTERFACE_MODE_RGMII: | |
1482 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
1483 | phydev->supported &= (PHY_GBIT_FEATURES | | |
1484 | SUPPORTED_Pause | | |
1485 | SUPPORTED_Asym_Pause); | |
1486 | break; | |
1487 | } | |
1488 | /* fallthru */ | |
1489 | case PHY_INTERFACE_MODE_MII: | |
1490 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1491 | SUPPORTED_Pause | | |
1492 | SUPPORTED_Asym_Pause); | |
1493 | break; | |
1494 | default: | |
1495 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); | |
1496 | return -EINVAL; | |
1497 | } | |
1498 | ||
1499 | tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED; | |
1500 | ||
1501 | phydev->advertising = phydev->supported; | |
1502 | ||
1503 | return 0; | |
1504 | } | |
1505 | ||
1506 | static void tg3_phy_start(struct tg3 *tp) | |
1507 | { | |
1508 | struct phy_device *phydev; | |
1509 | ||
1510 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
1511 | return; | |
1512 | ||
1513 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
1514 | ||
1515 | if (tp->link_config.phy_is_low_power) { | |
1516 | tp->link_config.phy_is_low_power = 0; | |
1517 | phydev->speed = tp->link_config.orig_speed; | |
1518 | phydev->duplex = tp->link_config.orig_duplex; | |
1519 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1520 | phydev->advertising = tp->link_config.orig_advertising; | |
1521 | } | |
1522 | ||
1523 | phy_start(phydev); | |
1524 | ||
1525 | phy_start_aneg(phydev); | |
1526 | } | |
1527 | ||
1528 | static void tg3_phy_stop(struct tg3 *tp) | |
1529 | { | |
1530 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
1531 | return; | |
1532 | ||
1533 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); | |
1534 | } | |
1535 | ||
1536 | static void tg3_phy_fini(struct tg3 *tp) | |
1537 | { | |
1538 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
1539 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); | |
1540 | tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED; | |
1541 | } | |
1542 | } | |
1543 | ||
1544 | static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
1545 | { | |
1546 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1547 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1548 | } | |
1549 | ||
1550 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) | |
1551 | { | |
1552 | u32 phytest; | |
1553 | ||
1554 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1555 | u32 phy; | |
1556 | ||
1557 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1558 | phytest | MII_TG3_FET_SHADOW_EN); | |
1559 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1560 | if (enable) | |
1561 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1562 | else | |
1563 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1564 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1565 | } | |
1566 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) | |
1571 | { | |
1572 | u32 reg; | |
1573 | ||
1574 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
1575 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | |
1576 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) | |
1577 | return; | |
1578 | ||
1579 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { | |
1580 | tg3_phy_fet_toggle_apd(tp, enable); | |
1581 | return; | |
1582 | } | |
1583 | ||
1584 | reg = MII_TG3_MISC_SHDW_WREN | | |
1585 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1586 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1587 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1588 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1589 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1590 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1591 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1592 | ||
1593 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1594 | ||
1595 | ||
1596 | reg = MII_TG3_MISC_SHDW_WREN | | |
1597 | MII_TG3_MISC_SHDW_APD_SEL | | |
1598 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1599 | if (enable) | |
1600 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1601 | ||
1602 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1603 | } | |
1604 | ||
1605 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) | |
1606 | { | |
1607 | u32 phy; | |
1608 | ||
1609 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
1610 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
1611 | return; | |
1612 | ||
1613 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { | |
1614 | u32 ephy; | |
1615 | ||
1616 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { | |
1617 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1618 | ||
1619 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1620 | ephy | MII_TG3_FET_SHADOW_EN); | |
1621 | if (!tg3_readphy(tp, reg, &phy)) { | |
1622 | if (enable) | |
1623 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; | |
1624 | else | |
1625 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; | |
1626 | tg3_writephy(tp, reg, phy); | |
1627 | } | |
1628 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); | |
1629 | } | |
1630 | } else { | |
1631 | phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | | |
1632 | MII_TG3_AUXCTL_SHDWSEL_MISC; | |
1633 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) && | |
1634 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) { | |
1635 | if (enable) | |
1636 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1637 | else | |
1638 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1639 | phy |= MII_TG3_AUXCTL_MISC_WREN; | |
1640 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1641 | } | |
1642 | } | |
1643 | } | |
1644 | ||
1645 | static void tg3_phy_set_wirespeed(struct tg3 *tp) | |
1646 | { | |
1647 | u32 val; | |
1648 | ||
1649 | if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) | |
1650 | return; | |
1651 | ||
1652 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) && | |
1653 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) | |
1654 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1655 | (val | (1 << 15) | (1 << 4))); | |
1656 | } | |
1657 | ||
1658 | static void tg3_phy_apply_otp(struct tg3 *tp) | |
1659 | { | |
1660 | u32 otp, phy; | |
1661 | ||
1662 | if (!tp->phy_otp) | |
1663 | return; | |
1664 | ||
1665 | otp = tp->phy_otp; | |
1666 | ||
1667 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
1668 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1669 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
1670 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1671 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1672 | ||
1673 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1674 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1675 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1676 | ||
1677 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1678 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1679 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1680 | ||
1681 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1682 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1683 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1684 | ||
1685 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1686 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1687 | ||
1688 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1689 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1690 | ||
1691 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1692 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1693 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1694 | ||
1695 | /* Turn off SM_DSP clock. */ | |
1696 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1697 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1698 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1699 | } | |
1700 | ||
1701 | static int tg3_wait_macro_done(struct tg3 *tp) | |
1702 | { | |
1703 | int limit = 100; | |
1704 | ||
1705 | while (limit--) { | |
1706 | u32 tmp32; | |
1707 | ||
1708 | if (!tg3_readphy(tp, 0x16, &tmp32)) { | |
1709 | if ((tmp32 & 0x1000) == 0) | |
1710 | break; | |
1711 | } | |
1712 | } | |
1713 | if (limit < 0) | |
1714 | return -EBUSY; | |
1715 | ||
1716 | return 0; | |
1717 | } | |
1718 | ||
1719 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1720 | { | |
1721 | static const u32 test_pat[4][6] = { | |
1722 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1723 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1724 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1725 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1726 | }; | |
1727 | int chan; | |
1728 | ||
1729 | for (chan = 0; chan < 4; chan++) { | |
1730 | int i; | |
1731 | ||
1732 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1733 | (chan * 0x2000) | 0x0200); | |
1734 | tg3_writephy(tp, 0x16, 0x0002); | |
1735 | ||
1736 | for (i = 0; i < 6; i++) | |
1737 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1738 | test_pat[chan][i]); | |
1739 | ||
1740 | tg3_writephy(tp, 0x16, 0x0202); | |
1741 | if (tg3_wait_macro_done(tp)) { | |
1742 | *resetp = 1; | |
1743 | return -EBUSY; | |
1744 | } | |
1745 | ||
1746 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1747 | (chan * 0x2000) | 0x0200); | |
1748 | tg3_writephy(tp, 0x16, 0x0082); | |
1749 | if (tg3_wait_macro_done(tp)) { | |
1750 | *resetp = 1; | |
1751 | return -EBUSY; | |
1752 | } | |
1753 | ||
1754 | tg3_writephy(tp, 0x16, 0x0802); | |
1755 | if (tg3_wait_macro_done(tp)) { | |
1756 | *resetp = 1; | |
1757 | return -EBUSY; | |
1758 | } | |
1759 | ||
1760 | for (i = 0; i < 6; i += 2) { | |
1761 | u32 low, high; | |
1762 | ||
1763 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1764 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1765 | tg3_wait_macro_done(tp)) { | |
1766 | *resetp = 1; | |
1767 | return -EBUSY; | |
1768 | } | |
1769 | low &= 0x7fff; | |
1770 | high &= 0x000f; | |
1771 | if (low != test_pat[chan][i] || | |
1772 | high != test_pat[chan][i+1]) { | |
1773 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1774 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1775 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1776 | ||
1777 | return -EBUSY; | |
1778 | } | |
1779 | } | |
1780 | } | |
1781 | ||
1782 | return 0; | |
1783 | } | |
1784 | ||
1785 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1786 | { | |
1787 | int chan; | |
1788 | ||
1789 | for (chan = 0; chan < 4; chan++) { | |
1790 | int i; | |
1791 | ||
1792 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1793 | (chan * 0x2000) | 0x0200); | |
1794 | tg3_writephy(tp, 0x16, 0x0002); | |
1795 | for (i = 0; i < 6; i++) | |
1796 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
1797 | tg3_writephy(tp, 0x16, 0x0202); | |
1798 | if (tg3_wait_macro_done(tp)) | |
1799 | return -EBUSY; | |
1800 | } | |
1801 | ||
1802 | return 0; | |
1803 | } | |
1804 | ||
1805 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1806 | { | |
1807 | u32 reg32, phy9_orig; | |
1808 | int retries, do_phy_reset, err; | |
1809 | ||
1810 | retries = 10; | |
1811 | do_phy_reset = 1; | |
1812 | do { | |
1813 | if (do_phy_reset) { | |
1814 | err = tg3_bmcr_reset(tp); | |
1815 | if (err) | |
1816 | return err; | |
1817 | do_phy_reset = 0; | |
1818 | } | |
1819 | ||
1820 | /* Disable transmitter and interrupt. */ | |
1821 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
1822 | continue; | |
1823 | ||
1824 | reg32 |= 0x3000; | |
1825 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1826 | ||
1827 | /* Set full-duplex, 1000 mbps. */ | |
1828 | tg3_writephy(tp, MII_BMCR, | |
1829 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | |
1830 | ||
1831 | /* Set to master mode. */ | |
1832 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | |
1833 | continue; | |
1834 | ||
1835 | tg3_writephy(tp, MII_TG3_CTRL, | |
1836 | (MII_TG3_CTRL_AS_MASTER | | |
1837 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | |
1838 | ||
1839 | /* Enable SM_DSP_CLOCK and 6dB. */ | |
1840 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1841 | ||
1842 | /* Block the PHY control access. */ | |
1843 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); | |
1844 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800); | |
1845 | ||
1846 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
1847 | if (!err) | |
1848 | break; | |
1849 | } while (--retries); | |
1850 | ||
1851 | err = tg3_phy_reset_chanpat(tp); | |
1852 | if (err) | |
1853 | return err; | |
1854 | ||
1855 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); | |
1856 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000); | |
1857 | ||
1858 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
1859 | tg3_writephy(tp, 0x16, 0x0000); | |
1860 | ||
1861 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
1862 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
1863 | /* Set Extended packet length bit for jumbo frames */ | |
1864 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400); | |
1865 | } | |
1866 | else { | |
1867 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1868 | } | |
1869 | ||
1870 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | |
1871 | ||
1872 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
1873 | reg32 &= ~0x3000; | |
1874 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1875 | } else if (!err) | |
1876 | err = -EBUSY; | |
1877 | ||
1878 | return err; | |
1879 | } | |
1880 | ||
1881 | /* This will reset the tigon3 PHY if there is no valid | |
1882 | * link unless the FORCE argument is non-zero. | |
1883 | */ | |
1884 | static int tg3_phy_reset(struct tg3 *tp) | |
1885 | { | |
1886 | u32 cpmuctrl; | |
1887 | u32 phy_status; | |
1888 | int err; | |
1889 | ||
1890 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
1891 | u32 val; | |
1892 | ||
1893 | val = tr32(GRC_MISC_CFG); | |
1894 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
1895 | udelay(40); | |
1896 | } | |
1897 | err = tg3_readphy(tp, MII_BMSR, &phy_status); | |
1898 | err |= tg3_readphy(tp, MII_BMSR, &phy_status); | |
1899 | if (err != 0) | |
1900 | return -EBUSY; | |
1901 | ||
1902 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { | |
1903 | netif_carrier_off(tp->dev); | |
1904 | tg3_link_report(tp); | |
1905 | } | |
1906 | ||
1907 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
1908 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
1909 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
1910 | err = tg3_phy_reset_5703_4_5(tp); | |
1911 | if (err) | |
1912 | return err; | |
1913 | goto out; | |
1914 | } | |
1915 | ||
1916 | cpmuctrl = 0; | |
1917 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
1918 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
1919 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
1920 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
1921 | tw32(TG3_CPMU_CTRL, | |
1922 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
1923 | } | |
1924 | ||
1925 | err = tg3_bmcr_reset(tp); | |
1926 | if (err) | |
1927 | return err; | |
1928 | ||
1929 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { | |
1930 | u32 phy; | |
1931 | ||
1932 | phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; | |
1933 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy); | |
1934 | ||
1935 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
1936 | } | |
1937 | ||
1938 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || | |
1939 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
1940 | u32 val; | |
1941 | ||
1942 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | |
1943 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
1944 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
1945 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
1946 | udelay(40); | |
1947 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
1948 | } | |
1949 | } | |
1950 | ||
1951 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | |
1952 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) | |
1953 | return 0; | |
1954 | ||
1955 | tg3_phy_apply_otp(tp); | |
1956 | ||
1957 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
1958 | tg3_phy_toggle_apd(tp, true); | |
1959 | else | |
1960 | tg3_phy_toggle_apd(tp, false); | |
1961 | ||
1962 | out: | |
1963 | if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) { | |
1964 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1965 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
1966 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa); | |
1967 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1968 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323); | |
1969 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1970 | } | |
1971 | if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) { | |
1972 | tg3_writephy(tp, 0x1c, 0x8d68); | |
1973 | tg3_writephy(tp, 0x1c, 0x8d68); | |
1974 | } | |
1975 | if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) { | |
1976 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1977 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1978 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b); | |
1979 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
1980 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506); | |
1981 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f); | |
1982 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2); | |
1983 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1984 | } | |
1985 | else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) { | |
1986 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1987 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1988 | if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) { | |
1989 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
1990 | tg3_writephy(tp, MII_TG3_TEST1, | |
1991 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
1992 | } else | |
1993 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
1994 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1995 | } | |
1996 | /* Set Extended packet length bit (bit 14) on all chips that */ | |
1997 | /* support jumbo frames */ | |
1998 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
1999 | /* Cannot do read-modify-write on 5401 */ | |
2000 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
2001 | } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
2002 | u32 phy_reg; | |
2003 | ||
2004 | /* Set bit 14 with read-modify-write to preserve other bits */ | |
2005 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) && | |
2006 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg)) | |
2007 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000); | |
2008 | } | |
2009 | ||
2010 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2011 | * jumbo frames transmission. | |
2012 | */ | |
2013 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
2014 | u32 phy_reg; | |
2015 | ||
2016 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) | |
2017 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
2018 | phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC); | |
2019 | } | |
2020 | ||
2021 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2022 | /* adjust output voltage */ | |
2023 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); | |
2024 | } | |
2025 | ||
2026 | tg3_phy_toggle_automdix(tp, 1); | |
2027 | tg3_phy_set_wirespeed(tp); | |
2028 | return 0; | |
2029 | } | |
2030 | ||
2031 | static void tg3_frob_aux_power(struct tg3 *tp) | |
2032 | { | |
2033 | struct tg3 *tp_peer = tp; | |
2034 | ||
2035 | /* The GPIOs do something completely different on 57765. */ | |
2036 | if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 || | |
2037 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2038 | return; | |
2039 | ||
2040 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2041 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
2042 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
2043 | struct net_device *dev_peer; | |
2044 | ||
2045 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
2046 | /* remove_one() may have been run on the peer. */ | |
2047 | if (!dev_peer) | |
2048 | tp_peer = tp; | |
2049 | else | |
2050 | tp_peer = netdev_priv(dev_peer); | |
2051 | } | |
2052 | ||
2053 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || | |
2054 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 || | |
2055 | (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || | |
2056 | (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { | |
2057 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2058 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2059 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2060 | (GRC_LCLCTRL_GPIO_OE0 | | |
2061 | GRC_LCLCTRL_GPIO_OE1 | | |
2062 | GRC_LCLCTRL_GPIO_OE2 | | |
2063 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2064 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2065 | 100); | |
2066 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
2067 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
2068 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
2069 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2070 | GRC_LCLCTRL_GPIO_OE1 | | |
2071 | GRC_LCLCTRL_GPIO_OE2 | | |
2072 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2073 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2074 | tp->grc_local_ctrl; | |
2075 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2076 | ||
2077 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2078 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2079 | ||
2080 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2081 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2082 | } else { | |
2083 | u32 no_gpio2; | |
2084 | u32 grc_local_ctrl = 0; | |
2085 | ||
2086 | if (tp_peer != tp && | |
2087 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2088 | return; | |
2089 | ||
2090 | /* Workaround to prevent overdrawing Amps. */ | |
2091 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2092 | ASIC_REV_5714) { | |
2093 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
2094 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2095 | grc_local_ctrl, 100); | |
2096 | } | |
2097 | ||
2098 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
2099 | no_gpio2 = tp->nic_sram_data_cfg & | |
2100 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2101 | ||
2102 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
2103 | GRC_LCLCTRL_GPIO_OE1 | | |
2104 | GRC_LCLCTRL_GPIO_OE2 | | |
2105 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2106 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2107 | if (no_gpio2) { | |
2108 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2109 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2110 | } | |
2111 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2112 | grc_local_ctrl, 100); | |
2113 | ||
2114 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2115 | ||
2116 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2117 | grc_local_ctrl, 100); | |
2118 | ||
2119 | if (!no_gpio2) { | |
2120 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2121 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2122 | grc_local_ctrl, 100); | |
2123 | } | |
2124 | } | |
2125 | } else { | |
2126 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
2127 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
2128 | if (tp_peer != tp && | |
2129 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2130 | return; | |
2131 | ||
2132 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2133 | (GRC_LCLCTRL_GPIO_OE1 | | |
2134 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
2135 | ||
2136 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2137 | GRC_LCLCTRL_GPIO_OE1, 100); | |
2138 | ||
2139 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2140 | (GRC_LCLCTRL_GPIO_OE1 | | |
2141 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
2142 | } | |
2143 | } | |
2144 | } | |
2145 | ||
2146 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) | |
2147 | { | |
2148 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2149 | return 1; | |
2150 | else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) { | |
2151 | if (speed != SPEED_10) | |
2152 | return 1; | |
2153 | } else if (speed == SPEED_10) | |
2154 | return 1; | |
2155 | ||
2156 | return 0; | |
2157 | } | |
2158 | ||
2159 | static int tg3_setup_phy(struct tg3 *, int); | |
2160 | ||
2161 | #define RESET_KIND_SHUTDOWN 0 | |
2162 | #define RESET_KIND_INIT 1 | |
2163 | #define RESET_KIND_SUSPEND 2 | |
2164 | ||
2165 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2166 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2167 | ||
2168 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) | |
2169 | { | |
2170 | u32 val; | |
2171 | ||
2172 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
2173 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2174 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2175 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2176 | ||
2177 | sg_dig_ctrl |= | |
2178 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2179 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2180 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2181 | } | |
2182 | return; | |
2183 | } | |
2184 | ||
2185 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2186 | tg3_bmcr_reset(tp); | |
2187 | val = tr32(GRC_MISC_CFG); | |
2188 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2189 | udelay(40); | |
2190 | return; | |
2191 | } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { | |
2192 | u32 phytest; | |
2193 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2194 | u32 phy; | |
2195 | ||
2196 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2197 | tg3_writephy(tp, MII_BMCR, | |
2198 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2199 | ||
2200 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2201 | phytest | MII_TG3_FET_SHADOW_EN); | |
2202 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2203 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2204 | tg3_writephy(tp, | |
2205 | MII_TG3_FET_SHDW_AUXMODE4, | |
2206 | phy); | |
2207 | } | |
2208 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2209 | } | |
2210 | return; | |
2211 | } else if (do_low_power) { | |
2212 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
2213 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
2214 | ||
2215 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
2216 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL | | |
2217 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2218 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2219 | MII_TG3_AUXCTL_PCTL_VREG_11V); | |
2220 | } | |
2221 | ||
2222 | /* The PHY should not be powered down on some chips because | |
2223 | * of bugs. | |
2224 | */ | |
2225 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2226 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2227 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
2228 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) | |
2229 | return; | |
2230 | ||
2231 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || | |
2232 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
2233 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | |
2234 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2235 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2236 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2237 | } | |
2238 | ||
2239 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
2240 | } | |
2241 | ||
2242 | /* tp->lock is held. */ | |
2243 | static int tg3_nvram_lock(struct tg3 *tp) | |
2244 | { | |
2245 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2246 | int i; | |
2247 | ||
2248 | if (tp->nvram_lock_cnt == 0) { | |
2249 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2250 | for (i = 0; i < 8000; i++) { | |
2251 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2252 | break; | |
2253 | udelay(20); | |
2254 | } | |
2255 | if (i == 8000) { | |
2256 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2257 | return -ENODEV; | |
2258 | } | |
2259 | } | |
2260 | tp->nvram_lock_cnt++; | |
2261 | } | |
2262 | return 0; | |
2263 | } | |
2264 | ||
2265 | /* tp->lock is held. */ | |
2266 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2267 | { | |
2268 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2269 | if (tp->nvram_lock_cnt > 0) | |
2270 | tp->nvram_lock_cnt--; | |
2271 | if (tp->nvram_lock_cnt == 0) | |
2272 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2273 | } | |
2274 | } | |
2275 | ||
2276 | /* tp->lock is held. */ | |
2277 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2278 | { | |
2279 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
2280 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { | |
2281 | u32 nvaccess = tr32(NVRAM_ACCESS); | |
2282 | ||
2283 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2284 | } | |
2285 | } | |
2286 | ||
2287 | /* tp->lock is held. */ | |
2288 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2289 | { | |
2290 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
2291 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { | |
2292 | u32 nvaccess = tr32(NVRAM_ACCESS); | |
2293 | ||
2294 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2295 | } | |
2296 | } | |
2297 | ||
2298 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2299 | u32 offset, u32 *val) | |
2300 | { | |
2301 | u32 tmp; | |
2302 | int i; | |
2303 | ||
2304 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2305 | return -EINVAL; | |
2306 | ||
2307 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2308 | EEPROM_ADDR_DEVID_MASK | | |
2309 | EEPROM_ADDR_READ); | |
2310 | tw32(GRC_EEPROM_ADDR, | |
2311 | tmp | | |
2312 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2313 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2314 | EEPROM_ADDR_ADDR_MASK) | | |
2315 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2316 | ||
2317 | for (i = 0; i < 1000; i++) { | |
2318 | tmp = tr32(GRC_EEPROM_ADDR); | |
2319 | ||
2320 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2321 | break; | |
2322 | msleep(1); | |
2323 | } | |
2324 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2325 | return -EBUSY; | |
2326 | ||
2327 | tmp = tr32(GRC_EEPROM_DATA); | |
2328 | ||
2329 | /* | |
2330 | * The data will always be opposite the native endian | |
2331 | * format. Perform a blind byteswap to compensate. | |
2332 | */ | |
2333 | *val = swab32(tmp); | |
2334 | ||
2335 | return 0; | |
2336 | } | |
2337 | ||
2338 | #define NVRAM_CMD_TIMEOUT 10000 | |
2339 | ||
2340 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2341 | { | |
2342 | int i; | |
2343 | ||
2344 | tw32(NVRAM_CMD, nvram_cmd); | |
2345 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2346 | udelay(10); | |
2347 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2348 | udelay(10); | |
2349 | break; | |
2350 | } | |
2351 | } | |
2352 | ||
2353 | if (i == NVRAM_CMD_TIMEOUT) | |
2354 | return -EBUSY; | |
2355 | ||
2356 | return 0; | |
2357 | } | |
2358 | ||
2359 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2360 | { | |
2361 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2362 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2363 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2364 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2365 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2366 | ||
2367 | addr = ((addr / tp->nvram_pagesize) << | |
2368 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2369 | (addr % tp->nvram_pagesize); | |
2370 | ||
2371 | return addr; | |
2372 | } | |
2373 | ||
2374 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2375 | { | |
2376 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2377 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2378 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2379 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2380 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2381 | ||
2382 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2383 | tp->nvram_pagesize) + | |
2384 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2385 | ||
2386 | return addr; | |
2387 | } | |
2388 | ||
2389 | /* NOTE: Data read in from NVRAM is byteswapped according to | |
2390 | * the byteswapping settings for all other register accesses. | |
2391 | * tg3 devices are BE devices, so on a BE machine, the data | |
2392 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2393 | * machine, the 32-bit value will be byteswapped. | |
2394 | */ | |
2395 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) | |
2396 | { | |
2397 | int ret; | |
2398 | ||
2399 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | |
2400 | return tg3_nvram_read_using_eeprom(tp, offset, val); | |
2401 | ||
2402 | offset = tg3_nvram_phys_addr(tp, offset); | |
2403 | ||
2404 | if (offset > NVRAM_ADDR_MSK) | |
2405 | return -EINVAL; | |
2406 | ||
2407 | ret = tg3_nvram_lock(tp); | |
2408 | if (ret) | |
2409 | return ret; | |
2410 | ||
2411 | tg3_enable_nvram_access(tp); | |
2412 | ||
2413 | tw32(NVRAM_ADDR, offset); | |
2414 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2415 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2416 | ||
2417 | if (ret == 0) | |
2418 | *val = tr32(NVRAM_RDDATA); | |
2419 | ||
2420 | tg3_disable_nvram_access(tp); | |
2421 | ||
2422 | tg3_nvram_unlock(tp); | |
2423 | ||
2424 | return ret; | |
2425 | } | |
2426 | ||
2427 | /* Ensures NVRAM data is in bytestream format. */ | |
2428 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
2429 | { | |
2430 | u32 v; | |
2431 | int res = tg3_nvram_read(tp, offset, &v); | |
2432 | if (!res) | |
2433 | *val = cpu_to_be32(v); | |
2434 | return res; | |
2435 | } | |
2436 | ||
2437 | /* tp->lock is held. */ | |
2438 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2439 | { | |
2440 | u32 addr_high, addr_low; | |
2441 | int i; | |
2442 | ||
2443 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2444 | tp->dev->dev_addr[1]); | |
2445 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2446 | (tp->dev->dev_addr[3] << 16) | | |
2447 | (tp->dev->dev_addr[4] << 8) | | |
2448 | (tp->dev->dev_addr[5] << 0)); | |
2449 | for (i = 0; i < 4; i++) { | |
2450 | if (i == 1 && skip_mac_1) | |
2451 | continue; | |
2452 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2453 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2454 | } | |
2455 | ||
2456 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2457 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2458 | for (i = 0; i < 12; i++) { | |
2459 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2460 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2461 | } | |
2462 | } | |
2463 | ||
2464 | addr_high = (tp->dev->dev_addr[0] + | |
2465 | tp->dev->dev_addr[1] + | |
2466 | tp->dev->dev_addr[2] + | |
2467 | tp->dev->dev_addr[3] + | |
2468 | tp->dev->dev_addr[4] + | |
2469 | tp->dev->dev_addr[5]) & | |
2470 | TX_BACKOFF_SEED_MASK; | |
2471 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2472 | } | |
2473 | ||
2474 | static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) | |
2475 | { | |
2476 | u32 misc_host_ctrl; | |
2477 | bool device_should_wake, do_low_power; | |
2478 | ||
2479 | /* Make sure register accesses (indirect or otherwise) | |
2480 | * will function correctly. | |
2481 | */ | |
2482 | pci_write_config_dword(tp->pdev, | |
2483 | TG3PCI_MISC_HOST_CTRL, | |
2484 | tp->misc_host_ctrl); | |
2485 | ||
2486 | switch (state) { | |
2487 | case PCI_D0: | |
2488 | pci_enable_wake(tp->pdev, state, false); | |
2489 | pci_set_power_state(tp->pdev, PCI_D0); | |
2490 | ||
2491 | /* Switch out of Vaux if it is a NIC */ | |
2492 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
2493 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); | |
2494 | ||
2495 | return 0; | |
2496 | ||
2497 | case PCI_D1: | |
2498 | case PCI_D2: | |
2499 | case PCI_D3hot: | |
2500 | break; | |
2501 | ||
2502 | default: | |
2503 | printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n", | |
2504 | tp->dev->name, state); | |
2505 | return -EINVAL; | |
2506 | } | |
2507 | ||
2508 | /* Restore the CLKREQ setting. */ | |
2509 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
2510 | u16 lnkctl; | |
2511 | ||
2512 | pci_read_config_word(tp->pdev, | |
2513 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2514 | &lnkctl); | |
2515 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2516 | pci_write_config_word(tp->pdev, | |
2517 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2518 | lnkctl); | |
2519 | } | |
2520 | ||
2521 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); | |
2522 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2523 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2524 | ||
2525 | device_should_wake = pci_pme_capable(tp->pdev, state) && | |
2526 | device_may_wakeup(&tp->pdev->dev) && | |
2527 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
2528 | ||
2529 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
2530 | do_low_power = false; | |
2531 | if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) && | |
2532 | !tp->link_config.phy_is_low_power) { | |
2533 | struct phy_device *phydev; | |
2534 | u32 phyid, advertising; | |
2535 | ||
2536 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
2537 | ||
2538 | tp->link_config.phy_is_low_power = 1; | |
2539 | ||
2540 | tp->link_config.orig_speed = phydev->speed; | |
2541 | tp->link_config.orig_duplex = phydev->duplex; | |
2542 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2543 | tp->link_config.orig_advertising = phydev->advertising; | |
2544 | ||
2545 | advertising = ADVERTISED_TP | | |
2546 | ADVERTISED_Pause | | |
2547 | ADVERTISED_Autoneg | | |
2548 | ADVERTISED_10baseT_Half; | |
2549 | ||
2550 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2551 | device_should_wake) { | |
2552 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2553 | advertising |= | |
2554 | ADVERTISED_100baseT_Half | | |
2555 | ADVERTISED_100baseT_Full | | |
2556 | ADVERTISED_10baseT_Full; | |
2557 | else | |
2558 | advertising |= ADVERTISED_10baseT_Full; | |
2559 | } | |
2560 | ||
2561 | phydev->advertising = advertising; | |
2562 | ||
2563 | phy_start_aneg(phydev); | |
2564 | ||
2565 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
2566 | if (phyid != TG3_PHY_ID_BCMAC131) { | |
2567 | phyid &= TG3_PHY_OUI_MASK; | |
2568 | if (phyid == TG3_PHY_OUI_1 || | |
2569 | phyid == TG3_PHY_OUI_2 || | |
2570 | phyid == TG3_PHY_OUI_3) | |
2571 | do_low_power = true; | |
2572 | } | |
2573 | } | |
2574 | } else { | |
2575 | do_low_power = true; | |
2576 | ||
2577 | if (tp->link_config.phy_is_low_power == 0) { | |
2578 | tp->link_config.phy_is_low_power = 1; | |
2579 | tp->link_config.orig_speed = tp->link_config.speed; | |
2580 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2581 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2582 | } | |
2583 | ||
2584 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { | |
2585 | tp->link_config.speed = SPEED_10; | |
2586 | tp->link_config.duplex = DUPLEX_HALF; | |
2587 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2588 | tg3_setup_phy(tp, 0); | |
2589 | } | |
2590 | } | |
2591 | ||
2592 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2593 | u32 val; | |
2594 | ||
2595 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2596 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
2597 | } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
2598 | int i; | |
2599 | u32 val; | |
2600 | ||
2601 | for (i = 0; i < 200; i++) { | |
2602 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2603 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2604 | break; | |
2605 | msleep(1); | |
2606 | } | |
2607 | } | |
2608 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) | |
2609 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | | |
2610 | WOL_DRV_STATE_SHUTDOWN | | |
2611 | WOL_DRV_WOL | | |
2612 | WOL_SET_MAGIC_PKT); | |
2613 | ||
2614 | if (device_should_wake) { | |
2615 | u32 mac_mode; | |
2616 | ||
2617 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
2618 | if (do_low_power) { | |
2619 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); | |
2620 | udelay(40); | |
2621 | } | |
2622 | ||
2623 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) | |
2624 | mac_mode = MAC_MODE_PORT_MODE_GMII; | |
2625 | else | |
2626 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
2627 | ||
2628 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; | |
2629 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2630 | ASIC_REV_5700) { | |
2631 | u32 speed = (tp->tg3_flags & | |
2632 | TG3_FLAG_WOL_SPEED_100MB) ? | |
2633 | SPEED_100 : SPEED_10; | |
2634 | if (tg3_5700_link_polarity(tp, speed)) | |
2635 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2636 | else | |
2637 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2638 | } | |
2639 | } else { | |
2640 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2641 | } | |
2642 | ||
2643 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
2644 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
2645 | ||
2646 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; | |
2647 | if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
2648 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) && | |
2649 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2650 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))) | |
2651 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; | |
2652 | ||
2653 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { | |
2654 | mac_mode |= tp->mac_mode & | |
2655 | (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); | |
2656 | if (mac_mode & MAC_MODE_APE_TX_EN) | |
2657 | mac_mode |= MAC_MODE_TDE_ENABLE; | |
2658 | } | |
2659 | ||
2660 | tw32_f(MAC_MODE, mac_mode); | |
2661 | udelay(100); | |
2662 | ||
2663 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2664 | udelay(10); | |
2665 | } | |
2666 | ||
2667 | if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) && | |
2668 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2669 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2670 | u32 base_val; | |
2671 | ||
2672 | base_val = tp->pci_clock_ctrl; | |
2673 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2674 | CLOCK_CTRL_TXCLK_DISABLE); | |
2675 | ||
2676 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | | |
2677 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
2678 | } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
2679 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || | |
2680 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { | |
2681 | /* do nothing */ | |
2682 | } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
2683 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { | |
2684 | u32 newbits1, newbits2; | |
2685 | ||
2686 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2687 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2688 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2689 | CLOCK_CTRL_TXCLK_DISABLE | | |
2690 | CLOCK_CTRL_ALTCLK); | |
2691 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2692 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
2693 | newbits1 = CLOCK_CTRL_625_CORE; | |
2694 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2695 | } else { | |
2696 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2697 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2698 | } | |
2699 | ||
2700 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, | |
2701 | 40); | |
2702 | ||
2703 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, | |
2704 | 40); | |
2705 | ||
2706 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
2707 | u32 newbits3; | |
2708 | ||
2709 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2710 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2711 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2712 | CLOCK_CTRL_TXCLK_DISABLE | | |
2713 | CLOCK_CTRL_44MHZ_CORE); | |
2714 | } else { | |
2715 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2716 | } | |
2717 | ||
2718 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
2719 | tp->pci_clock_ctrl | newbits3, 40); | |
2720 | } | |
2721 | } | |
2722 | ||
2723 | if (!(device_should_wake) && | |
2724 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
2725 | tg3_power_down_phy(tp, do_low_power); | |
2726 | ||
2727 | tg3_frob_aux_power(tp); | |
2728 | ||
2729 | /* Workaround for unstable PLL clock */ | |
2730 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2731 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2732 | u32 val = tr32(0x7d00); | |
2733 | ||
2734 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2735 | tw32(0x7d00, val); | |
2736 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
2737 | int err; | |
2738 | ||
2739 | err = tg3_nvram_lock(tp); | |
2740 | tg3_halt_cpu(tp, RX_CPU_BASE); | |
2741 | if (!err) | |
2742 | tg3_nvram_unlock(tp); | |
2743 | } | |
2744 | } | |
2745 | ||
2746 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); | |
2747 | ||
2748 | if (device_should_wake) | |
2749 | pci_enable_wake(tp->pdev, state, true); | |
2750 | ||
2751 | /* Finally, set the new power state. */ | |
2752 | pci_set_power_state(tp->pdev, state); | |
2753 | ||
2754 | return 0; | |
2755 | } | |
2756 | ||
2757 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) | |
2758 | { | |
2759 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2760 | case MII_TG3_AUX_STAT_10HALF: | |
2761 | *speed = SPEED_10; | |
2762 | *duplex = DUPLEX_HALF; | |
2763 | break; | |
2764 | ||
2765 | case MII_TG3_AUX_STAT_10FULL: | |
2766 | *speed = SPEED_10; | |
2767 | *duplex = DUPLEX_FULL; | |
2768 | break; | |
2769 | ||
2770 | case MII_TG3_AUX_STAT_100HALF: | |
2771 | *speed = SPEED_100; | |
2772 | *duplex = DUPLEX_HALF; | |
2773 | break; | |
2774 | ||
2775 | case MII_TG3_AUX_STAT_100FULL: | |
2776 | *speed = SPEED_100; | |
2777 | *duplex = DUPLEX_FULL; | |
2778 | break; | |
2779 | ||
2780 | case MII_TG3_AUX_STAT_1000HALF: | |
2781 | *speed = SPEED_1000; | |
2782 | *duplex = DUPLEX_HALF; | |
2783 | break; | |
2784 | ||
2785 | case MII_TG3_AUX_STAT_1000FULL: | |
2786 | *speed = SPEED_1000; | |
2787 | *duplex = DUPLEX_FULL; | |
2788 | break; | |
2789 | ||
2790 | default: | |
2791 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { | |
2792 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : | |
2793 | SPEED_10; | |
2794 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
2795 | DUPLEX_HALF; | |
2796 | break; | |
2797 | } | |
2798 | *speed = SPEED_INVALID; | |
2799 | *duplex = DUPLEX_INVALID; | |
2800 | break; | |
2801 | } | |
2802 | } | |
2803 | ||
2804 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
2805 | { | |
2806 | u32 new_adv; | |
2807 | int i; | |
2808 | ||
2809 | if (tp->link_config.phy_is_low_power) { | |
2810 | /* Entering low power mode. Disable gigabit and | |
2811 | * 100baseT advertisements. | |
2812 | */ | |
2813 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2814 | ||
2815 | new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2816 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
2817 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2818 | new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL); | |
2819 | ||
2820 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2821 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
2822 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) | |
2823 | tp->link_config.advertising &= | |
2824 | ~(ADVERTISED_1000baseT_Half | | |
2825 | ADVERTISED_1000baseT_Full); | |
2826 | ||
2827 | new_adv = ADVERTISE_CSMA; | |
2828 | if (tp->link_config.advertising & ADVERTISED_10baseT_Half) | |
2829 | new_adv |= ADVERTISE_10HALF; | |
2830 | if (tp->link_config.advertising & ADVERTISED_10baseT_Full) | |
2831 | new_adv |= ADVERTISE_10FULL; | |
2832 | if (tp->link_config.advertising & ADVERTISED_100baseT_Half) | |
2833 | new_adv |= ADVERTISE_100HALF; | |
2834 | if (tp->link_config.advertising & ADVERTISED_100baseT_Full) | |
2835 | new_adv |= ADVERTISE_100FULL; | |
2836 | ||
2837 | new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2838 | ||
2839 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2840 | ||
2841 | if (tp->link_config.advertising & | |
2842 | (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { | |
2843 | new_adv = 0; | |
2844 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
2845 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | |
2846 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
2847 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | |
2848 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) && | |
2849 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2850 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) | |
2851 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2852 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2853 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2854 | } else { | |
2855 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2856 | } | |
2857 | } else { | |
2858 | new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2859 | new_adv |= ADVERTISE_CSMA; | |
2860 | ||
2861 | /* Asking for a specific link mode. */ | |
2862 | if (tp->link_config.speed == SPEED_1000) { | |
2863 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2864 | ||
2865 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2866 | new_adv = MII_TG3_CTRL_ADV_1000_FULL; | |
2867 | else | |
2868 | new_adv = MII_TG3_CTRL_ADV_1000_HALF; | |
2869 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2870 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
2871 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2872 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2873 | } else { | |
2874 | if (tp->link_config.speed == SPEED_100) { | |
2875 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2876 | new_adv |= ADVERTISE_100FULL; | |
2877 | else | |
2878 | new_adv |= ADVERTISE_100HALF; | |
2879 | } else { | |
2880 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2881 | new_adv |= ADVERTISE_10FULL; | |
2882 | else | |
2883 | new_adv |= ADVERTISE_10HALF; | |
2884 | } | |
2885 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2886 | ||
2887 | new_adv = 0; | |
2888 | } | |
2889 | ||
2890 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2891 | } | |
2892 | ||
2893 | if (tp->link_config.autoneg == AUTONEG_DISABLE && | |
2894 | tp->link_config.speed != SPEED_INVALID) { | |
2895 | u32 bmcr, orig_bmcr; | |
2896 | ||
2897 | tp->link_config.active_speed = tp->link_config.speed; | |
2898 | tp->link_config.active_duplex = tp->link_config.duplex; | |
2899 | ||
2900 | bmcr = 0; | |
2901 | switch (tp->link_config.speed) { | |
2902 | default: | |
2903 | case SPEED_10: | |
2904 | break; | |
2905 | ||
2906 | case SPEED_100: | |
2907 | bmcr |= BMCR_SPEED100; | |
2908 | break; | |
2909 | ||
2910 | case SPEED_1000: | |
2911 | bmcr |= TG3_BMCR_SPEED1000; | |
2912 | break; | |
2913 | } | |
2914 | ||
2915 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2916 | bmcr |= BMCR_FULLDPLX; | |
2917 | ||
2918 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
2919 | (bmcr != orig_bmcr)) { | |
2920 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
2921 | for (i = 0; i < 1500; i++) { | |
2922 | u32 tmp; | |
2923 | ||
2924 | udelay(10); | |
2925 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
2926 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
2927 | continue; | |
2928 | if (!(tmp & BMSR_LSTATUS)) { | |
2929 | udelay(40); | |
2930 | break; | |
2931 | } | |
2932 | } | |
2933 | tg3_writephy(tp, MII_BMCR, bmcr); | |
2934 | udelay(40); | |
2935 | } | |
2936 | } else { | |
2937 | tg3_writephy(tp, MII_BMCR, | |
2938 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2939 | } | |
2940 | } | |
2941 | ||
2942 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
2943 | { | |
2944 | int err; | |
2945 | ||
2946 | /* Turn off tap power management. */ | |
2947 | /* Set Extended packet length bit */ | |
2948 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
2949 | ||
2950 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012); | |
2951 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804); | |
2952 | ||
2953 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013); | |
2954 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204); | |
2955 | ||
2956 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006); | |
2957 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132); | |
2958 | ||
2959 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006); | |
2960 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232); | |
2961 | ||
2962 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
2963 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20); | |
2964 | ||
2965 | udelay(40); | |
2966 | ||
2967 | return err; | |
2968 | } | |
2969 | ||
2970 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) | |
2971 | { | |
2972 | u32 adv_reg, all_mask = 0; | |
2973 | ||
2974 | if (mask & ADVERTISED_10baseT_Half) | |
2975 | all_mask |= ADVERTISE_10HALF; | |
2976 | if (mask & ADVERTISED_10baseT_Full) | |
2977 | all_mask |= ADVERTISE_10FULL; | |
2978 | if (mask & ADVERTISED_100baseT_Half) | |
2979 | all_mask |= ADVERTISE_100HALF; | |
2980 | if (mask & ADVERTISED_100baseT_Full) | |
2981 | all_mask |= ADVERTISE_100FULL; | |
2982 | ||
2983 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
2984 | return 0; | |
2985 | ||
2986 | if ((adv_reg & all_mask) != all_mask) | |
2987 | return 0; | |
2988 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
2989 | u32 tg3_ctrl; | |
2990 | ||
2991 | all_mask = 0; | |
2992 | if (mask & ADVERTISED_1000baseT_Half) | |
2993 | all_mask |= ADVERTISE_1000HALF; | |
2994 | if (mask & ADVERTISED_1000baseT_Full) | |
2995 | all_mask |= ADVERTISE_1000FULL; | |
2996 | ||
2997 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) | |
2998 | return 0; | |
2999 | ||
3000 | if ((tg3_ctrl & all_mask) != all_mask) | |
3001 | return 0; | |
3002 | } | |
3003 | return 1; | |
3004 | } | |
3005 | ||
3006 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) | |
3007 | { | |
3008 | u32 curadv, reqadv; | |
3009 | ||
3010 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3011 | return 1; | |
3012 | ||
3013 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3014 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3015 | ||
3016 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3017 | if (curadv != reqadv) | |
3018 | return 0; | |
3019 | ||
3020 | if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) | |
3021 | tg3_readphy(tp, MII_LPA, rmtadv); | |
3022 | } else { | |
3023 | /* Reprogram the advertisement register, even if it | |
3024 | * does not affect the current link. If the link | |
3025 | * gets renegotiated in the future, we can save an | |
3026 | * additional renegotiation cycle by advertising | |
3027 | * it correctly in the first place. | |
3028 | */ | |
3029 | if (curadv != reqadv) { | |
3030 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3031 | ADVERTISE_PAUSE_ASYM); | |
3032 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3033 | } | |
3034 | } | |
3035 | ||
3036 | return 1; | |
3037 | } | |
3038 | ||
3039 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |
3040 | { | |
3041 | int current_link_up; | |
3042 | u32 bmsr, dummy; | |
3043 | u32 lcl_adv, rmt_adv; | |
3044 | u16 current_speed; | |
3045 | u8 current_duplex; | |
3046 | int i, err; | |
3047 | ||
3048 | tw32(MAC_EVENT, 0); | |
3049 | ||
3050 | tw32_f(MAC_STATUS, | |
3051 | (MAC_STATUS_SYNC_CHANGED | | |
3052 | MAC_STATUS_CFG_CHANGED | | |
3053 | MAC_STATUS_MI_COMPLETION | | |
3054 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3055 | udelay(40); | |
3056 | ||
3057 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
3058 | tw32_f(MAC_MI_MODE, | |
3059 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3060 | udelay(80); | |
3061 | } | |
3062 | ||
3063 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); | |
3064 | ||
3065 | /* Some third-party PHYs need to be reset on link going | |
3066 | * down. | |
3067 | */ | |
3068 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3069 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3070 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3071 | netif_carrier_ok(tp->dev)) { | |
3072 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3073 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3074 | !(bmsr & BMSR_LSTATUS)) | |
3075 | force_reset = 1; | |
3076 | } | |
3077 | if (force_reset) | |
3078 | tg3_phy_reset(tp); | |
3079 | ||
3080 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
3081 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3082 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
3083 | !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) | |
3084 | bmsr = 0; | |
3085 | ||
3086 | if (!(bmsr & BMSR_LSTATUS)) { | |
3087 | err = tg3_init_5401phy_dsp(tp); | |
3088 | if (err) | |
3089 | return err; | |
3090 | ||
3091 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3092 | for (i = 0; i < 1000; i++) { | |
3093 | udelay(10); | |
3094 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3095 | (bmsr & BMSR_LSTATUS)) { | |
3096 | udelay(40); | |
3097 | break; | |
3098 | } | |
3099 | } | |
3100 | ||
3101 | if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 && | |
3102 | !(bmsr & BMSR_LSTATUS) && | |
3103 | tp->link_config.active_speed == SPEED_1000) { | |
3104 | err = tg3_phy_reset(tp); | |
3105 | if (!err) | |
3106 | err = tg3_init_5401phy_dsp(tp); | |
3107 | if (err) | |
3108 | return err; | |
3109 | } | |
3110 | } | |
3111 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3112 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3113 | /* 5701 {A0,B0} CRC bug workaround */ | |
3114 | tg3_writephy(tp, 0x15, 0x0a75); | |
3115 | tg3_writephy(tp, 0x1c, 0x8c68); | |
3116 | tg3_writephy(tp, 0x1c, 0x8d68); | |
3117 | tg3_writephy(tp, 0x1c, 0x8c68); | |
3118 | } | |
3119 | ||
3120 | /* Clear pending interrupts... */ | |
3121 | tg3_readphy(tp, MII_TG3_ISTAT, &dummy); | |
3122 | tg3_readphy(tp, MII_TG3_ISTAT, &dummy); | |
3123 | ||
3124 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) | |
3125 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); | |
3126 | else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) | |
3127 | tg3_writephy(tp, MII_TG3_IMASK, ~0); | |
3128 | ||
3129 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3130 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3131 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3132 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3133 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3134 | else | |
3135 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3136 | } | |
3137 | ||
3138 | current_link_up = 0; | |
3139 | current_speed = SPEED_INVALID; | |
3140 | current_duplex = DUPLEX_INVALID; | |
3141 | ||
3142 | if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) { | |
3143 | u32 val; | |
3144 | ||
3145 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007); | |
3146 | tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); | |
3147 | if (!(val & (1 << 10))) { | |
3148 | val |= (1 << 10); | |
3149 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
3150 | goto relink; | |
3151 | } | |
3152 | } | |
3153 | ||
3154 | bmsr = 0; | |
3155 | for (i = 0; i < 100; i++) { | |
3156 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3157 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3158 | (bmsr & BMSR_LSTATUS)) | |
3159 | break; | |
3160 | udelay(40); | |
3161 | } | |
3162 | ||
3163 | if (bmsr & BMSR_LSTATUS) { | |
3164 | u32 aux_stat, bmcr; | |
3165 | ||
3166 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3167 | for (i = 0; i < 2000; i++) { | |
3168 | udelay(10); | |
3169 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3170 | aux_stat) | |
3171 | break; | |
3172 | } | |
3173 | ||
3174 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3175 | ¤t_speed, | |
3176 | ¤t_duplex); | |
3177 | ||
3178 | bmcr = 0; | |
3179 | for (i = 0; i < 200; i++) { | |
3180 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3181 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3182 | continue; | |
3183 | if (bmcr && bmcr != 0x7fff) | |
3184 | break; | |
3185 | udelay(10); | |
3186 | } | |
3187 | ||
3188 | lcl_adv = 0; | |
3189 | rmt_adv = 0; | |
3190 | ||
3191 | tp->link_config.active_speed = current_speed; | |
3192 | tp->link_config.active_duplex = current_duplex; | |
3193 | ||
3194 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3195 | if ((bmcr & BMCR_ANENABLE) && | |
3196 | tg3_copper_is_advertising_all(tp, | |
3197 | tp->link_config.advertising)) { | |
3198 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3199 | &rmt_adv)) | |
3200 | current_link_up = 1; | |
3201 | } | |
3202 | } else { | |
3203 | if (!(bmcr & BMCR_ANENABLE) && | |
3204 | tp->link_config.speed == current_speed && | |
3205 | tp->link_config.duplex == current_duplex && | |
3206 | tp->link_config.flowctrl == | |
3207 | tp->link_config.active_flowctrl) { | |
3208 | current_link_up = 1; | |
3209 | } | |
3210 | } | |
3211 | ||
3212 | if (current_link_up == 1 && | |
3213 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3214 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
3215 | } | |
3216 | ||
3217 | relink: | |
3218 | if (current_link_up == 0 || tp->link_config.phy_is_low_power) { | |
3219 | u32 tmp; | |
3220 | ||
3221 | tg3_phy_copper_begin(tp); | |
3222 | ||
3223 | tg3_readphy(tp, MII_BMSR, &tmp); | |
3224 | if (!tg3_readphy(tp, MII_BMSR, &tmp) && | |
3225 | (tmp & BMSR_LSTATUS)) | |
3226 | current_link_up = 1; | |
3227 | } | |
3228 | ||
3229 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3230 | if (current_link_up == 1) { | |
3231 | if (tp->link_config.active_speed == SPEED_100 || | |
3232 | tp->link_config.active_speed == SPEED_10) | |
3233 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3234 | else | |
3235 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
3236 | } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) | |
3237 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3238 | else | |
3239 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
3240 | ||
3241 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3242 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3243 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3244 | ||
3245 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
3246 | if (current_link_up == 1 && | |
3247 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
3248 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
3249 | else | |
3250 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
3251 | } | |
3252 | ||
3253 | /* ??? Without this setting Netgear GA302T PHY does not | |
3254 | * ??? send/receive packets... | |
3255 | */ | |
3256 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 && | |
3257 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { | |
3258 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3259 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3260 | udelay(80); | |
3261 | } | |
3262 | ||
3263 | tw32_f(MAC_MODE, tp->mac_mode); | |
3264 | udelay(40); | |
3265 | ||
3266 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { | |
3267 | /* Polled via timer. */ | |
3268 | tw32_f(MAC_EVENT, 0); | |
3269 | } else { | |
3270 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3271 | } | |
3272 | udelay(40); | |
3273 | ||
3274 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3275 | current_link_up == 1 && | |
3276 | tp->link_config.active_speed == SPEED_1000 && | |
3277 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || | |
3278 | (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { | |
3279 | udelay(120); | |
3280 | tw32_f(MAC_STATUS, | |
3281 | (MAC_STATUS_SYNC_CHANGED | | |
3282 | MAC_STATUS_CFG_CHANGED)); | |
3283 | udelay(40); | |
3284 | tg3_write_mem(tp, | |
3285 | NIC_SRAM_FIRMWARE_MBOX, | |
3286 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3287 | } | |
3288 | ||
3289 | /* Prevent send BD corruption. */ | |
3290 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
3291 | u16 oldlnkctl, newlnkctl; | |
3292 | ||
3293 | pci_read_config_word(tp->pdev, | |
3294 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3295 | &oldlnkctl); | |
3296 | if (tp->link_config.active_speed == SPEED_100 || | |
3297 | tp->link_config.active_speed == SPEED_10) | |
3298 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3299 | else | |
3300 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3301 | if (newlnkctl != oldlnkctl) | |
3302 | pci_write_config_word(tp->pdev, | |
3303 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3304 | newlnkctl); | |
3305 | } | |
3306 | ||
3307 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
3308 | if (current_link_up) | |
3309 | netif_carrier_on(tp->dev); | |
3310 | else | |
3311 | netif_carrier_off(tp->dev); | |
3312 | tg3_link_report(tp); | |
3313 | } | |
3314 | ||
3315 | return 0; | |
3316 | } | |
3317 | ||
3318 | struct tg3_fiber_aneginfo { | |
3319 | int state; | |
3320 | #define ANEG_STATE_UNKNOWN 0 | |
3321 | #define ANEG_STATE_AN_ENABLE 1 | |
3322 | #define ANEG_STATE_RESTART_INIT 2 | |
3323 | #define ANEG_STATE_RESTART 3 | |
3324 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3325 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3326 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3327 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3328 | #define ANEG_STATE_ACK_DETECT 8 | |
3329 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3330 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3331 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3332 | #define ANEG_STATE_IDLE_DETECT 12 | |
3333 | #define ANEG_STATE_LINK_OK 13 | |
3334 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3335 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3336 | ||
3337 | u32 flags; | |
3338 | #define MR_AN_ENABLE 0x00000001 | |
3339 | #define MR_RESTART_AN 0x00000002 | |
3340 | #define MR_AN_COMPLETE 0x00000004 | |
3341 | #define MR_PAGE_RX 0x00000008 | |
3342 | #define MR_NP_LOADED 0x00000010 | |
3343 | #define MR_TOGGLE_TX 0x00000020 | |
3344 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3345 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3346 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3347 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3348 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3349 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3350 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3351 | #define MR_TOGGLE_RX 0x00002000 | |
3352 | #define MR_NP_RX 0x00004000 | |
3353 | ||
3354 | #define MR_LINK_OK 0x80000000 | |
3355 | ||
3356 | unsigned long link_time, cur_time; | |
3357 | ||
3358 | u32 ability_match_cfg; | |
3359 | int ability_match_count; | |
3360 | ||
3361 | char ability_match, idle_match, ack_match; | |
3362 | ||
3363 | u32 txconfig, rxconfig; | |
3364 | #define ANEG_CFG_NP 0x00000080 | |
3365 | #define ANEG_CFG_ACK 0x00000040 | |
3366 | #define ANEG_CFG_RF2 0x00000020 | |
3367 | #define ANEG_CFG_RF1 0x00000010 | |
3368 | #define ANEG_CFG_PS2 0x00000001 | |
3369 | #define ANEG_CFG_PS1 0x00008000 | |
3370 | #define ANEG_CFG_HD 0x00004000 | |
3371 | #define ANEG_CFG_FD 0x00002000 | |
3372 | #define ANEG_CFG_INVAL 0x00001f06 | |
3373 | ||
3374 | }; | |
3375 | #define ANEG_OK 0 | |
3376 | #define ANEG_DONE 1 | |
3377 | #define ANEG_TIMER_ENAB 2 | |
3378 | #define ANEG_FAILED -1 | |
3379 | ||
3380 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3381 | ||
3382 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3383 | struct tg3_fiber_aneginfo *ap) | |
3384 | { | |
3385 | u16 flowctrl; | |
3386 | unsigned long delta; | |
3387 | u32 rx_cfg_reg; | |
3388 | int ret; | |
3389 | ||
3390 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3391 | ap->rxconfig = 0; | |
3392 | ap->link_time = 0; | |
3393 | ap->cur_time = 0; | |
3394 | ap->ability_match_cfg = 0; | |
3395 | ap->ability_match_count = 0; | |
3396 | ap->ability_match = 0; | |
3397 | ap->idle_match = 0; | |
3398 | ap->ack_match = 0; | |
3399 | } | |
3400 | ap->cur_time++; | |
3401 | ||
3402 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3403 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3404 | ||
3405 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3406 | ap->ability_match_cfg = rx_cfg_reg; | |
3407 | ap->ability_match = 0; | |
3408 | ap->ability_match_count = 0; | |
3409 | } else { | |
3410 | if (++ap->ability_match_count > 1) { | |
3411 | ap->ability_match = 1; | |
3412 | ap->ability_match_cfg = rx_cfg_reg; | |
3413 | } | |
3414 | } | |
3415 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3416 | ap->ack_match = 1; | |
3417 | else | |
3418 | ap->ack_match = 0; | |
3419 | ||
3420 | ap->idle_match = 0; | |
3421 | } else { | |
3422 | ap->idle_match = 1; | |
3423 | ap->ability_match_cfg = 0; | |
3424 | ap->ability_match_count = 0; | |
3425 | ap->ability_match = 0; | |
3426 | ap->ack_match = 0; | |
3427 | ||
3428 | rx_cfg_reg = 0; | |
3429 | } | |
3430 | ||
3431 | ap->rxconfig = rx_cfg_reg; | |
3432 | ret = ANEG_OK; | |
3433 | ||
3434 | switch(ap->state) { | |
3435 | case ANEG_STATE_UNKNOWN: | |
3436 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3437 | ap->state = ANEG_STATE_AN_ENABLE; | |
3438 | ||
3439 | /* fallthru */ | |
3440 | case ANEG_STATE_AN_ENABLE: | |
3441 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3442 | if (ap->flags & MR_AN_ENABLE) { | |
3443 | ap->link_time = 0; | |
3444 | ap->cur_time = 0; | |
3445 | ap->ability_match_cfg = 0; | |
3446 | ap->ability_match_count = 0; | |
3447 | ap->ability_match = 0; | |
3448 | ap->idle_match = 0; | |
3449 | ap->ack_match = 0; | |
3450 | ||
3451 | ap->state = ANEG_STATE_RESTART_INIT; | |
3452 | } else { | |
3453 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3454 | } | |
3455 | break; | |
3456 | ||
3457 | case ANEG_STATE_RESTART_INIT: | |
3458 | ap->link_time = ap->cur_time; | |
3459 | ap->flags &= ~(MR_NP_LOADED); | |
3460 | ap->txconfig = 0; | |
3461 | tw32(MAC_TX_AUTO_NEG, 0); | |
3462 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3463 | tw32_f(MAC_MODE, tp->mac_mode); | |
3464 | udelay(40); | |
3465 | ||
3466 | ret = ANEG_TIMER_ENAB; | |
3467 | ap->state = ANEG_STATE_RESTART; | |
3468 | ||
3469 | /* fallthru */ | |
3470 | case ANEG_STATE_RESTART: | |
3471 | delta = ap->cur_time - ap->link_time; | |
3472 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3473 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; | |
3474 | } else { | |
3475 | ret = ANEG_TIMER_ENAB; | |
3476 | } | |
3477 | break; | |
3478 | ||
3479 | case ANEG_STATE_DISABLE_LINK_OK: | |
3480 | ret = ANEG_DONE; | |
3481 | break; | |
3482 | ||
3483 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3484 | ap->flags &= ~(MR_TOGGLE_TX); | |
3485 | ap->txconfig = ANEG_CFG_FD; | |
3486 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3487 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3488 | ap->txconfig |= ANEG_CFG_PS1; | |
3489 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3490 | ap->txconfig |= ANEG_CFG_PS2; | |
3491 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3492 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3493 | tw32_f(MAC_MODE, tp->mac_mode); | |
3494 | udelay(40); | |
3495 | ||
3496 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3497 | break; | |
3498 | ||
3499 | case ANEG_STATE_ABILITY_DETECT: | |
3500 | if (ap->ability_match != 0 && ap->rxconfig != 0) { | |
3501 | ap->state = ANEG_STATE_ACK_DETECT_INIT; | |
3502 | } | |
3503 | break; | |
3504 | ||
3505 | case ANEG_STATE_ACK_DETECT_INIT: | |
3506 | ap->txconfig |= ANEG_CFG_ACK; | |
3507 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3508 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3509 | tw32_f(MAC_MODE, tp->mac_mode); | |
3510 | udelay(40); | |
3511 | ||
3512 | ap->state = ANEG_STATE_ACK_DETECT; | |
3513 | ||
3514 | /* fallthru */ | |
3515 | case ANEG_STATE_ACK_DETECT: | |
3516 | if (ap->ack_match != 0) { | |
3517 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3518 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3519 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3520 | } else { | |
3521 | ap->state = ANEG_STATE_AN_ENABLE; | |
3522 | } | |
3523 | } else if (ap->ability_match != 0 && | |
3524 | ap->rxconfig == 0) { | |
3525 | ap->state = ANEG_STATE_AN_ENABLE; | |
3526 | } | |
3527 | break; | |
3528 | ||
3529 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3530 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3531 | ret = ANEG_FAILED; | |
3532 | break; | |
3533 | } | |
3534 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3535 | MR_LP_ADV_HALF_DUPLEX | | |
3536 | MR_LP_ADV_SYM_PAUSE | | |
3537 | MR_LP_ADV_ASYM_PAUSE | | |
3538 | MR_LP_ADV_REMOTE_FAULT1 | | |
3539 | MR_LP_ADV_REMOTE_FAULT2 | | |
3540 | MR_LP_ADV_NEXT_PAGE | | |
3541 | MR_TOGGLE_RX | | |
3542 | MR_NP_RX); | |
3543 | if (ap->rxconfig & ANEG_CFG_FD) | |
3544 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3545 | if (ap->rxconfig & ANEG_CFG_HD) | |
3546 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3547 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3548 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3549 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3550 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3551 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3552 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3553 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3554 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3555 | if (ap->rxconfig & ANEG_CFG_NP) | |
3556 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3557 | ||
3558 | ap->link_time = ap->cur_time; | |
3559 | ||
3560 | ap->flags ^= (MR_TOGGLE_TX); | |
3561 | if (ap->rxconfig & 0x0008) | |
3562 | ap->flags |= MR_TOGGLE_RX; | |
3563 | if (ap->rxconfig & ANEG_CFG_NP) | |
3564 | ap->flags |= MR_NP_RX; | |
3565 | ap->flags |= MR_PAGE_RX; | |
3566 | ||
3567 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3568 | ret = ANEG_TIMER_ENAB; | |
3569 | break; | |
3570 | ||
3571 | case ANEG_STATE_COMPLETE_ACK: | |
3572 | if (ap->ability_match != 0 && | |
3573 | ap->rxconfig == 0) { | |
3574 | ap->state = ANEG_STATE_AN_ENABLE; | |
3575 | break; | |
3576 | } | |
3577 | delta = ap->cur_time - ap->link_time; | |
3578 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3579 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3580 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3581 | } else { | |
3582 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3583 | !(ap->flags & MR_NP_RX)) { | |
3584 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3585 | } else { | |
3586 | ret = ANEG_FAILED; | |
3587 | } | |
3588 | } | |
3589 | } | |
3590 | break; | |
3591 | ||
3592 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3593 | ap->link_time = ap->cur_time; | |
3594 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3595 | tw32_f(MAC_MODE, tp->mac_mode); | |
3596 | udelay(40); | |
3597 | ||
3598 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3599 | ret = ANEG_TIMER_ENAB; | |
3600 | break; | |
3601 | ||
3602 | case ANEG_STATE_IDLE_DETECT: | |
3603 | if (ap->ability_match != 0 && | |
3604 | ap->rxconfig == 0) { | |
3605 | ap->state = ANEG_STATE_AN_ENABLE; | |
3606 | break; | |
3607 | } | |
3608 | delta = ap->cur_time - ap->link_time; | |
3609 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3610 | /* XXX another gem from the Broadcom driver :( */ | |
3611 | ap->state = ANEG_STATE_LINK_OK; | |
3612 | } | |
3613 | break; | |
3614 | ||
3615 | case ANEG_STATE_LINK_OK: | |
3616 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3617 | ret = ANEG_DONE; | |
3618 | break; | |
3619 | ||
3620 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3621 | /* ??? unimplemented */ | |
3622 | break; | |
3623 | ||
3624 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3625 | /* ??? unimplemented */ | |
3626 | break; | |
3627 | ||
3628 | default: | |
3629 | ret = ANEG_FAILED; | |
3630 | break; | |
3631 | } | |
3632 | ||
3633 | return ret; | |
3634 | } | |
3635 | ||
3636 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) | |
3637 | { | |
3638 | int res = 0; | |
3639 | struct tg3_fiber_aneginfo aninfo; | |
3640 | int status = ANEG_FAILED; | |
3641 | unsigned int tick; | |
3642 | u32 tmp; | |
3643 | ||
3644 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3645 | ||
3646 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3647 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3648 | udelay(40); | |
3649 | ||
3650 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3651 | udelay(40); | |
3652 | ||
3653 | memset(&aninfo, 0, sizeof(aninfo)); | |
3654 | aninfo.flags |= MR_AN_ENABLE; | |
3655 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3656 | aninfo.cur_time = 0; | |
3657 | tick = 0; | |
3658 | while (++tick < 195000) { | |
3659 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3660 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3661 | break; | |
3662 | ||
3663 | udelay(1); | |
3664 | } | |
3665 | ||
3666 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3667 | tw32_f(MAC_MODE, tp->mac_mode); | |
3668 | udelay(40); | |
3669 | ||
3670 | *txflags = aninfo.txconfig; | |
3671 | *rxflags = aninfo.flags; | |
3672 | ||
3673 | if (status == ANEG_DONE && | |
3674 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3675 | MR_LP_ADV_FULL_DUPLEX))) | |
3676 | res = 1; | |
3677 | ||
3678 | return res; | |
3679 | } | |
3680 | ||
3681 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3682 | { | |
3683 | u32 mac_status = tr32(MAC_STATUS); | |
3684 | int i; | |
3685 | ||
3686 | /* Reset when initting first time or we have a link. */ | |
3687 | if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) && | |
3688 | !(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3689 | return; | |
3690 | ||
3691 | /* Set PLL lock range. */ | |
3692 | tg3_writephy(tp, 0x16, 0x8007); | |
3693 | ||
3694 | /* SW reset */ | |
3695 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3696 | ||
3697 | /* Wait for reset to complete. */ | |
3698 | /* XXX schedule_timeout() ... */ | |
3699 | for (i = 0; i < 500; i++) | |
3700 | udelay(10); | |
3701 | ||
3702 | /* Config mode; select PMA/Ch 1 regs. */ | |
3703 | tg3_writephy(tp, 0x10, 0x8411); | |
3704 | ||
3705 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3706 | tg3_writephy(tp, 0x11, 0x0a10); | |
3707 | ||
3708 | tg3_writephy(tp, 0x18, 0x00a0); | |
3709 | tg3_writephy(tp, 0x16, 0x41ff); | |
3710 | ||
3711 | /* Assert and deassert POR. */ | |
3712 | tg3_writephy(tp, 0x13, 0x0400); | |
3713 | udelay(40); | |
3714 | tg3_writephy(tp, 0x13, 0x0000); | |
3715 | ||
3716 | tg3_writephy(tp, 0x11, 0x0a50); | |
3717 | udelay(40); | |
3718 | tg3_writephy(tp, 0x11, 0x0a10); | |
3719 | ||
3720 | /* Wait for signal to stabilize */ | |
3721 | /* XXX schedule_timeout() ... */ | |
3722 | for (i = 0; i < 15000; i++) | |
3723 | udelay(10); | |
3724 | ||
3725 | /* Deselect the channel register so we can read the PHYID | |
3726 | * later. | |
3727 | */ | |
3728 | tg3_writephy(tp, 0x10, 0x8011); | |
3729 | } | |
3730 | ||
3731 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3732 | { | |
3733 | u16 flowctrl; | |
3734 | u32 sg_dig_ctrl, sg_dig_status; | |
3735 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3736 | int workaround, port_a; | |
3737 | int current_link_up; | |
3738 | ||
3739 | serdes_cfg = 0; | |
3740 | expected_sg_dig_ctrl = 0; | |
3741 | workaround = 0; | |
3742 | port_a = 1; | |
3743 | current_link_up = 0; | |
3744 | ||
3745 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3746 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3747 | workaround = 1; | |
3748 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3749 | port_a = 0; | |
3750 | ||
3751 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3752 | /* preserve bits 20-23 for voltage regulator */ | |
3753 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3754 | } | |
3755 | ||
3756 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3757 | ||
3758 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
3759 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { | |
3760 | if (workaround) { | |
3761 | u32 val = serdes_cfg; | |
3762 | ||
3763 | if (port_a) | |
3764 | val |= 0xc010000; | |
3765 | else | |
3766 | val |= 0x4010000; | |
3767 | tw32_f(MAC_SERDES_CFG, val); | |
3768 | } | |
3769 | ||
3770 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
3771 | } | |
3772 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
3773 | tg3_setup_flow_control(tp, 0, 0); | |
3774 | current_link_up = 1; | |
3775 | } | |
3776 | goto out; | |
3777 | } | |
3778 | ||
3779 | /* Want auto-negotiation. */ | |
3780 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; | |
3781 | ||
3782 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3783 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3784 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
3785 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3786 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
3787 | ||
3788 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
3789 | if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) && | |
3790 | tp->serdes_counter && | |
3791 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
3792 | MAC_STATUS_RCVD_CFG)) == | |
3793 | MAC_STATUS_PCS_SYNCED)) { | |
3794 | tp->serdes_counter--; | |
3795 | current_link_up = 1; | |
3796 | goto out; | |
3797 | } | |
3798 | restart_autoneg: | |
3799 | if (workaround) | |
3800 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
3801 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); | |
3802 | udelay(5); | |
3803 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
3804 | ||
3805 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
3806 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
3807 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | | |
3808 | MAC_STATUS_SIGNAL_DET)) { | |
3809 | sg_dig_status = tr32(SG_DIG_STATUS); | |
3810 | mac_status = tr32(MAC_STATUS); | |
3811 | ||
3812 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && | |
3813 | (mac_status & MAC_STATUS_PCS_SYNCED)) { | |
3814 | u32 local_adv = 0, remote_adv = 0; | |
3815 | ||
3816 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
3817 | local_adv |= ADVERTISE_1000XPAUSE; | |
3818 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
3819 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
3820 | ||
3821 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) | |
3822 | remote_adv |= LPA_1000XPAUSE; | |
3823 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) | |
3824 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
3825 | ||
3826 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3827 | current_link_up = 1; | |
3828 | tp->serdes_counter = 0; | |
3829 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
3830 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { | |
3831 | if (tp->serdes_counter) | |
3832 | tp->serdes_counter--; | |
3833 | else { | |
3834 | if (workaround) { | |
3835 | u32 val = serdes_cfg; | |
3836 | ||
3837 | if (port_a) | |
3838 | val |= 0xc010000; | |
3839 | else | |
3840 | val |= 0x4010000; | |
3841 | ||
3842 | tw32_f(MAC_SERDES_CFG, val); | |
3843 | } | |
3844 | ||
3845 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
3846 | udelay(40); | |
3847 | ||
3848 | /* Link parallel detection - link is up */ | |
3849 | /* only if we have PCS_SYNC and not */ | |
3850 | /* receiving config code words */ | |
3851 | mac_status = tr32(MAC_STATUS); | |
3852 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
3853 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
3854 | tg3_setup_flow_control(tp, 0, 0); | |
3855 | current_link_up = 1; | |
3856 | tp->tg3_flags2 |= | |
3857 | TG3_FLG2_PARALLEL_DETECT; | |
3858 | tp->serdes_counter = | |
3859 | SERDES_PARALLEL_DET_TIMEOUT; | |
3860 | } else | |
3861 | goto restart_autoneg; | |
3862 | } | |
3863 | } | |
3864 | } else { | |
3865 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
3866 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
3867 | } | |
3868 | ||
3869 | out: | |
3870 | return current_link_up; | |
3871 | } | |
3872 | ||
3873 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
3874 | { | |
3875 | int current_link_up = 0; | |
3876 | ||
3877 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3878 | goto out; | |
3879 | ||
3880 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3881 | u32 txflags, rxflags; | |
3882 | int i; | |
3883 | ||
3884 | if (fiber_autoneg(tp, &txflags, &rxflags)) { | |
3885 | u32 local_adv = 0, remote_adv = 0; | |
3886 | ||
3887 | if (txflags & ANEG_CFG_PS1) | |
3888 | local_adv |= ADVERTISE_1000XPAUSE; | |
3889 | if (txflags & ANEG_CFG_PS2) | |
3890 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
3891 | ||
3892 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
3893 | remote_adv |= LPA_1000XPAUSE; | |
3894 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
3895 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
3896 | ||
3897 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3898 | ||
3899 | current_link_up = 1; | |
3900 | } | |
3901 | for (i = 0; i < 30; i++) { | |
3902 | udelay(20); | |
3903 | tw32_f(MAC_STATUS, | |
3904 | (MAC_STATUS_SYNC_CHANGED | | |
3905 | MAC_STATUS_CFG_CHANGED)); | |
3906 | udelay(40); | |
3907 | if ((tr32(MAC_STATUS) & | |
3908 | (MAC_STATUS_SYNC_CHANGED | | |
3909 | MAC_STATUS_CFG_CHANGED)) == 0) | |
3910 | break; | |
3911 | } | |
3912 | ||
3913 | mac_status = tr32(MAC_STATUS); | |
3914 | if (current_link_up == 0 && | |
3915 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
3916 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
3917 | current_link_up = 1; | |
3918 | } else { | |
3919 | tg3_setup_flow_control(tp, 0, 0); | |
3920 | ||
3921 | /* Forcing 1000FD link up. */ | |
3922 | current_link_up = 1; | |
3923 | ||
3924 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
3925 | udelay(40); | |
3926 | ||
3927 | tw32_f(MAC_MODE, tp->mac_mode); | |
3928 | udelay(40); | |
3929 | } | |
3930 | ||
3931 | out: | |
3932 | return current_link_up; | |
3933 | } | |
3934 | ||
3935 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
3936 | { | |
3937 | u32 orig_pause_cfg; | |
3938 | u16 orig_active_speed; | |
3939 | u8 orig_active_duplex; | |
3940 | u32 mac_status; | |
3941 | int current_link_up; | |
3942 | int i; | |
3943 | ||
3944 | orig_pause_cfg = tp->link_config.active_flowctrl; | |
3945 | orig_active_speed = tp->link_config.active_speed; | |
3946 | orig_active_duplex = tp->link_config.active_duplex; | |
3947 | ||
3948 | if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) && | |
3949 | netif_carrier_ok(tp->dev) && | |
3950 | (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) { | |
3951 | mac_status = tr32(MAC_STATUS); | |
3952 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
3953 | MAC_STATUS_SIGNAL_DET | | |
3954 | MAC_STATUS_CFG_CHANGED | | |
3955 | MAC_STATUS_RCVD_CFG); | |
3956 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
3957 | MAC_STATUS_SIGNAL_DET)) { | |
3958 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
3959 | MAC_STATUS_CFG_CHANGED)); | |
3960 | return 0; | |
3961 | } | |
3962 | } | |
3963 | ||
3964 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3965 | ||
3966 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
3967 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
3968 | tw32_f(MAC_MODE, tp->mac_mode); | |
3969 | udelay(40); | |
3970 | ||
3971 | if (tp->phy_id == PHY_ID_BCM8002) | |
3972 | tg3_init_bcm8002(tp); | |
3973 | ||
3974 | /* Enable link change event even when serdes polling. */ | |
3975 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3976 | udelay(40); | |
3977 | ||
3978 | current_link_up = 0; | |
3979 | mac_status = tr32(MAC_STATUS); | |
3980 | ||
3981 | if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) | |
3982 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); | |
3983 | else | |
3984 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
3985 | ||
3986 | tp->napi[0].hw_status->status = | |
3987 | (SD_STATUS_UPDATED | | |
3988 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); | |
3989 | ||
3990 | for (i = 0; i < 100; i++) { | |
3991 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
3992 | MAC_STATUS_CFG_CHANGED)); | |
3993 | udelay(5); | |
3994 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3995 | MAC_STATUS_CFG_CHANGED | | |
3996 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
3997 | break; | |
3998 | } | |
3999 | ||
4000 | mac_status = tr32(MAC_STATUS); | |
4001 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4002 | current_link_up = 0; | |
4003 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
4004 | tp->serdes_counter == 0) { | |
4005 | tw32_f(MAC_MODE, (tp->mac_mode | | |
4006 | MAC_MODE_SEND_CONFIGS)); | |
4007 | udelay(1); | |
4008 | tw32_f(MAC_MODE, tp->mac_mode); | |
4009 | } | |
4010 | } | |
4011 | ||
4012 | if (current_link_up == 1) { | |
4013 | tp->link_config.active_speed = SPEED_1000; | |
4014 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4015 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4016 | LED_CTRL_LNKLED_OVERRIDE | | |
4017 | LED_CTRL_1000MBPS_ON)); | |
4018 | } else { | |
4019 | tp->link_config.active_speed = SPEED_INVALID; | |
4020 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4021 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4022 | LED_CTRL_LNKLED_OVERRIDE | | |
4023 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4024 | } | |
4025 | ||
4026 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4027 | if (current_link_up) | |
4028 | netif_carrier_on(tp->dev); | |
4029 | else | |
4030 | netif_carrier_off(tp->dev); | |
4031 | tg3_link_report(tp); | |
4032 | } else { | |
4033 | u32 now_pause_cfg = tp->link_config.active_flowctrl; | |
4034 | if (orig_pause_cfg != now_pause_cfg || | |
4035 | orig_active_speed != tp->link_config.active_speed || | |
4036 | orig_active_duplex != tp->link_config.active_duplex) | |
4037 | tg3_link_report(tp); | |
4038 | } | |
4039 | ||
4040 | return 0; | |
4041 | } | |
4042 | ||
4043 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) | |
4044 | { | |
4045 | int current_link_up, err = 0; | |
4046 | u32 bmsr, bmcr; | |
4047 | u16 current_speed; | |
4048 | u8 current_duplex; | |
4049 | u32 local_adv, remote_adv; | |
4050 | ||
4051 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4052 | tw32_f(MAC_MODE, tp->mac_mode); | |
4053 | udelay(40); | |
4054 | ||
4055 | tw32(MAC_EVENT, 0); | |
4056 | ||
4057 | tw32_f(MAC_STATUS, | |
4058 | (MAC_STATUS_SYNC_CHANGED | | |
4059 | MAC_STATUS_CFG_CHANGED | | |
4060 | MAC_STATUS_MI_COMPLETION | | |
4061 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4062 | udelay(40); | |
4063 | ||
4064 | if (force_reset) | |
4065 | tg3_phy_reset(tp); | |
4066 | ||
4067 | current_link_up = 0; | |
4068 | current_speed = SPEED_INVALID; | |
4069 | current_duplex = DUPLEX_INVALID; | |
4070 | ||
4071 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4072 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4073 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
4074 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4075 | bmsr |= BMSR_LSTATUS; | |
4076 | else | |
4077 | bmsr &= ~BMSR_LSTATUS; | |
4078 | } | |
4079 | ||
4080 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4081 | ||
4082 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
4083 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) { | |
4084 | /* do nothing, just check for link up at the end */ | |
4085 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4086 | u32 adv, new_adv; | |
4087 | ||
4088 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4089 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4090 | ADVERTISE_1000XPAUSE | | |
4091 | ADVERTISE_1000XPSE_ASYM | | |
4092 | ADVERTISE_SLCT); | |
4093 | ||
4094 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
4095 | ||
4096 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4097 | new_adv |= ADVERTISE_1000XHALF; | |
4098 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4099 | new_adv |= ADVERTISE_1000XFULL; | |
4100 | ||
4101 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4102 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4103 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4104 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4105 | ||
4106 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4107 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; | |
4108 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
4109 | ||
4110 | return err; | |
4111 | } | |
4112 | } else { | |
4113 | u32 new_bmcr; | |
4114 | ||
4115 | bmcr &= ~BMCR_SPEED1000; | |
4116 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4117 | ||
4118 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4119 | new_bmcr |= BMCR_FULLDPLX; | |
4120 | ||
4121 | if (new_bmcr != bmcr) { | |
4122 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4123 | * to be set on write. | |
4124 | */ | |
4125 | new_bmcr |= BMCR_SPEED1000; | |
4126 | ||
4127 | /* Force a linkdown */ | |
4128 | if (netif_carrier_ok(tp->dev)) { | |
4129 | u32 adv; | |
4130 | ||
4131 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4132 | adv &= ~(ADVERTISE_1000XFULL | | |
4133 | ADVERTISE_1000XHALF | | |
4134 | ADVERTISE_SLCT); | |
4135 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4136 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4137 | BMCR_ANRESTART | | |
4138 | BMCR_ANENABLE); | |
4139 | udelay(10); | |
4140 | netif_carrier_off(tp->dev); | |
4141 | } | |
4142 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4143 | bmcr = new_bmcr; | |
4144 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4145 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4146 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
4147 | ASIC_REV_5714) { | |
4148 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4149 | bmsr |= BMSR_LSTATUS; | |
4150 | else | |
4151 | bmsr &= ~BMSR_LSTATUS; | |
4152 | } | |
4153 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
4154 | } | |
4155 | } | |
4156 | ||
4157 | if (bmsr & BMSR_LSTATUS) { | |
4158 | current_speed = SPEED_1000; | |
4159 | current_link_up = 1; | |
4160 | if (bmcr & BMCR_FULLDPLX) | |
4161 | current_duplex = DUPLEX_FULL; | |
4162 | else | |
4163 | current_duplex = DUPLEX_HALF; | |
4164 | ||
4165 | local_adv = 0; | |
4166 | remote_adv = 0; | |
4167 | ||
4168 | if (bmcr & BMCR_ANENABLE) { | |
4169 | u32 common; | |
4170 | ||
4171 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4172 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4173 | common = local_adv & remote_adv; | |
4174 | if (common & (ADVERTISE_1000XHALF | | |
4175 | ADVERTISE_1000XFULL)) { | |
4176 | if (common & ADVERTISE_1000XFULL) | |
4177 | current_duplex = DUPLEX_FULL; | |
4178 | else | |
4179 | current_duplex = DUPLEX_HALF; | |
4180 | } | |
4181 | else | |
4182 | current_link_up = 0; | |
4183 | } | |
4184 | } | |
4185 | ||
4186 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) | |
4187 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4188 | ||
4189 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
4190 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4191 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4192 | ||
4193 | tw32_f(MAC_MODE, tp->mac_mode); | |
4194 | udelay(40); | |
4195 | ||
4196 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4197 | ||
4198 | tp->link_config.active_speed = current_speed; | |
4199 | tp->link_config.active_duplex = current_duplex; | |
4200 | ||
4201 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4202 | if (current_link_up) | |
4203 | netif_carrier_on(tp->dev); | |
4204 | else { | |
4205 | netif_carrier_off(tp->dev); | |
4206 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
4207 | } | |
4208 | tg3_link_report(tp); | |
4209 | } | |
4210 | return err; | |
4211 | } | |
4212 | ||
4213 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4214 | { | |
4215 | if (tp->serdes_counter) { | |
4216 | /* Give autoneg time to complete. */ | |
4217 | tp->serdes_counter--; | |
4218 | return; | |
4219 | } | |
4220 | if (!netif_carrier_ok(tp->dev) && | |
4221 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4222 | u32 bmcr; | |
4223 | ||
4224 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4225 | if (bmcr & BMCR_ANENABLE) { | |
4226 | u32 phy1, phy2; | |
4227 | ||
4228 | /* Select shadow register 0x1f */ | |
4229 | tg3_writephy(tp, 0x1c, 0x7c00); | |
4230 | tg3_readphy(tp, 0x1c, &phy1); | |
4231 | ||
4232 | /* Select expansion interrupt status register */ | |
4233 | tg3_writephy(tp, 0x17, 0x0f01); | |
4234 | tg3_readphy(tp, 0x15, &phy2); | |
4235 | tg3_readphy(tp, 0x15, &phy2); | |
4236 | ||
4237 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4238 | /* We have signal detect and not receiving | |
4239 | * config code words, link is up by parallel | |
4240 | * detection. | |
4241 | */ | |
4242 | ||
4243 | bmcr &= ~BMCR_ANENABLE; | |
4244 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4245 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4246 | tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT; | |
4247 | } | |
4248 | } | |
4249 | } | |
4250 | else if (netif_carrier_ok(tp->dev) && | |
4251 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
4252 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) { | |
4253 | u32 phy2; | |
4254 | ||
4255 | /* Select expansion interrupt status register */ | |
4256 | tg3_writephy(tp, 0x17, 0x0f01); | |
4257 | tg3_readphy(tp, 0x15, &phy2); | |
4258 | if (phy2 & 0x20) { | |
4259 | u32 bmcr; | |
4260 | ||
4261 | /* Config code words received, turn on autoneg. */ | |
4262 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4263 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4264 | ||
4265 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
4266 | ||
4267 | } | |
4268 | } | |
4269 | } | |
4270 | ||
4271 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) | |
4272 | { | |
4273 | int err; | |
4274 | ||
4275 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
4276 | err = tg3_setup_fiber_phy(tp, force_reset); | |
4277 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
4278 | err = tg3_setup_fiber_mii_phy(tp, force_reset); | |
4279 | } else { | |
4280 | err = tg3_setup_copper_phy(tp, force_reset); | |
4281 | } | |
4282 | ||
4283 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { | |
4284 | u32 val, scale; | |
4285 | ||
4286 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4287 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4288 | scale = 65; | |
4289 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4290 | scale = 6; | |
4291 | else | |
4292 | scale = 12; | |
4293 | ||
4294 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4295 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4296 | tw32(GRC_MISC_CFG, val); | |
4297 | } | |
4298 | ||
4299 | if (tp->link_config.active_speed == SPEED_1000 && | |
4300 | tp->link_config.active_duplex == DUPLEX_HALF) | |
4301 | tw32(MAC_TX_LENGTHS, | |
4302 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4303 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4304 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4305 | else | |
4306 | tw32(MAC_TX_LENGTHS, | |
4307 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4308 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4309 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4310 | ||
4311 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
4312 | if (netif_carrier_ok(tp->dev)) { | |
4313 | tw32(HOSTCC_STAT_COAL_TICKS, | |
4314 | tp->coal.stats_block_coalesce_usecs); | |
4315 | } else { | |
4316 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4317 | } | |
4318 | } | |
4319 | ||
4320 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { | |
4321 | u32 val = tr32(PCIE_PWR_MGMT_THRESH); | |
4322 | if (!netif_carrier_ok(tp->dev)) | |
4323 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4324 | tp->pwrmgmt_thresh; | |
4325 | else | |
4326 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4327 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4328 | } | |
4329 | ||
4330 | return err; | |
4331 | } | |
4332 | ||
4333 | /* This is called whenever we suspect that the system chipset is re- | |
4334 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4335 | * is bogus tx completions. We try to recover by setting the | |
4336 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4337 | * in the workqueue. | |
4338 | */ | |
4339 | static void tg3_tx_recover(struct tg3 *tp) | |
4340 | { | |
4341 | BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || | |
4342 | tp->write32_tx_mbox == tg3_write_indirect_mbox); | |
4343 | ||
4344 | printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-" | |
4345 | "mapped I/O cycles to the network device, attempting to " | |
4346 | "recover. Please report the problem to the driver maintainer " | |
4347 | "and include system chipset information.\n", tp->dev->name); | |
4348 | ||
4349 | spin_lock(&tp->lock); | |
4350 | tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; | |
4351 | spin_unlock(&tp->lock); | |
4352 | } | |
4353 | ||
4354 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) | |
4355 | { | |
4356 | smp_mb(); | |
4357 | return tnapi->tx_pending - | |
4358 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
4359 | } | |
4360 | ||
4361 | /* Tigon3 never reports partial packet sends. So we do not | |
4362 | * need special logic to handle SKBs that have not had all | |
4363 | * of their frags sent yet, like SunGEM does. | |
4364 | */ | |
4365 | static void tg3_tx(struct tg3_napi *tnapi) | |
4366 | { | |
4367 | struct tg3 *tp = tnapi->tp; | |
4368 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; | |
4369 | u32 sw_idx = tnapi->tx_cons; | |
4370 | struct netdev_queue *txq; | |
4371 | int index = tnapi - tp->napi; | |
4372 | ||
4373 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) | |
4374 | index--; | |
4375 | ||
4376 | txq = netdev_get_tx_queue(tp->dev, index); | |
4377 | ||
4378 | while (sw_idx != hw_idx) { | |
4379 | struct ring_info *ri = &tnapi->tx_buffers[sw_idx]; | |
4380 | struct sk_buff *skb = ri->skb; | |
4381 | int i, tx_bug = 0; | |
4382 | ||
4383 | if (unlikely(skb == NULL)) { | |
4384 | tg3_tx_recover(tp); | |
4385 | return; | |
4386 | } | |
4387 | ||
4388 | pci_unmap_single(tp->pdev, | |
4389 | pci_unmap_addr(ri, mapping), | |
4390 | skb_headlen(skb), | |
4391 | PCI_DMA_TODEVICE); | |
4392 | ||
4393 | ri->skb = NULL; | |
4394 | ||
4395 | sw_idx = NEXT_TX(sw_idx); | |
4396 | ||
4397 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
4398 | ri = &tnapi->tx_buffers[sw_idx]; | |
4399 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) | |
4400 | tx_bug = 1; | |
4401 | ||
4402 | pci_unmap_page(tp->pdev, | |
4403 | pci_unmap_addr(ri, mapping), | |
4404 | skb_shinfo(skb)->frags[i].size, | |
4405 | PCI_DMA_TODEVICE); | |
4406 | sw_idx = NEXT_TX(sw_idx); | |
4407 | } | |
4408 | ||
4409 | dev_kfree_skb(skb); | |
4410 | ||
4411 | if (unlikely(tx_bug)) { | |
4412 | tg3_tx_recover(tp); | |
4413 | return; | |
4414 | } | |
4415 | } | |
4416 | ||
4417 | tnapi->tx_cons = sw_idx; | |
4418 | ||
4419 | /* Need to make the tx_cons update visible to tg3_start_xmit() | |
4420 | * before checking for netif_queue_stopped(). Without the | |
4421 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4422 | * will miss it and cause the queue to be stopped forever. | |
4423 | */ | |
4424 | smp_mb(); | |
4425 | ||
4426 | if (unlikely(netif_tx_queue_stopped(txq) && | |
4427 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { | |
4428 | __netif_tx_lock(txq, smp_processor_id()); | |
4429 | if (netif_tx_queue_stopped(txq) && | |
4430 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) | |
4431 | netif_tx_wake_queue(txq); | |
4432 | __netif_tx_unlock(txq); | |
4433 | } | |
4434 | } | |
4435 | ||
4436 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) | |
4437 | { | |
4438 | if (!ri->skb) | |
4439 | return; | |
4440 | ||
4441 | pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping), | |
4442 | map_sz, PCI_DMA_FROMDEVICE); | |
4443 | dev_kfree_skb_any(ri->skb); | |
4444 | ri->skb = NULL; | |
4445 | } | |
4446 | ||
4447 | /* Returns size of skb allocated or < 0 on error. | |
4448 | * | |
4449 | * We only need to fill in the address because the other members | |
4450 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4451 | * | |
4452 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4453 | * posting buffers we only dirty the first cache line of the RX | |
4454 | * descriptor (containing the address). Whereas for the RX status | |
4455 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4456 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4457 | */ | |
4458 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, | |
4459 | u32 opaque_key, u32 dest_idx_unmasked) | |
4460 | { | |
4461 | struct tg3_rx_buffer_desc *desc; | |
4462 | struct ring_info *map, *src_map; | |
4463 | struct sk_buff *skb; | |
4464 | dma_addr_t mapping; | |
4465 | int skb_size, dest_idx; | |
4466 | ||
4467 | src_map = NULL; | |
4468 | switch (opaque_key) { | |
4469 | case RXD_OPAQUE_RING_STD: | |
4470 | dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE; | |
4471 | desc = &tpr->rx_std[dest_idx]; | |
4472 | map = &tpr->rx_std_buffers[dest_idx]; | |
4473 | skb_size = tp->rx_pkt_map_sz; | |
4474 | break; | |
4475 | ||
4476 | case RXD_OPAQUE_RING_JUMBO: | |
4477 | dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE; | |
4478 | desc = &tpr->rx_jmb[dest_idx].std; | |
4479 | map = &tpr->rx_jmb_buffers[dest_idx]; | |
4480 | skb_size = TG3_RX_JMB_MAP_SZ; | |
4481 | break; | |
4482 | ||
4483 | default: | |
4484 | return -EINVAL; | |
4485 | } | |
4486 | ||
4487 | /* Do not overwrite any of the map or rp information | |
4488 | * until we are sure we can commit to a new buffer. | |
4489 | * | |
4490 | * Callers depend upon this behavior and assume that | |
4491 | * we leave everything unchanged if we fail. | |
4492 | */ | |
4493 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); | |
4494 | if (skb == NULL) | |
4495 | return -ENOMEM; | |
4496 | ||
4497 | skb_reserve(skb, tp->rx_offset); | |
4498 | ||
4499 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, | |
4500 | PCI_DMA_FROMDEVICE); | |
4501 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
4502 | dev_kfree_skb(skb); | |
4503 | return -EIO; | |
4504 | } | |
4505 | ||
4506 | map->skb = skb; | |
4507 | pci_unmap_addr_set(map, mapping, mapping); | |
4508 | ||
4509 | desc->addr_hi = ((u64)mapping >> 32); | |
4510 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4511 | ||
4512 | return skb_size; | |
4513 | } | |
4514 | ||
4515 | /* We only need to move over in the address because the other | |
4516 | * members of the RX descriptor are invariant. See notes above | |
4517 | * tg3_alloc_rx_skb for full details. | |
4518 | */ | |
4519 | static void tg3_recycle_rx(struct tg3_napi *tnapi, | |
4520 | struct tg3_rx_prodring_set *dpr, | |
4521 | u32 opaque_key, int src_idx, | |
4522 | u32 dest_idx_unmasked) | |
4523 | { | |
4524 | struct tg3 *tp = tnapi->tp; | |
4525 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; | |
4526 | struct ring_info *src_map, *dest_map; | |
4527 | int dest_idx; | |
4528 | struct tg3_rx_prodring_set *spr = &tp->prodring[0]; | |
4529 | ||
4530 | switch (opaque_key) { | |
4531 | case RXD_OPAQUE_RING_STD: | |
4532 | dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE; | |
4533 | dest_desc = &dpr->rx_std[dest_idx]; | |
4534 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
4535 | src_desc = &spr->rx_std[src_idx]; | |
4536 | src_map = &spr->rx_std_buffers[src_idx]; | |
4537 | break; | |
4538 | ||
4539 | case RXD_OPAQUE_RING_JUMBO: | |
4540 | dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE; | |
4541 | dest_desc = &dpr->rx_jmb[dest_idx].std; | |
4542 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
4543 | src_desc = &spr->rx_jmb[src_idx].std; | |
4544 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
4545 | break; | |
4546 | ||
4547 | default: | |
4548 | return; | |
4549 | } | |
4550 | ||
4551 | dest_map->skb = src_map->skb; | |
4552 | pci_unmap_addr_set(dest_map, mapping, | |
4553 | pci_unmap_addr(src_map, mapping)); | |
4554 | dest_desc->addr_hi = src_desc->addr_hi; | |
4555 | dest_desc->addr_lo = src_desc->addr_lo; | |
4556 | ||
4557 | /* Ensure that the update to the skb happens after the physical | |
4558 | * addresses have been transferred to the new BD location. | |
4559 | */ | |
4560 | smp_wmb(); | |
4561 | ||
4562 | src_map->skb = NULL; | |
4563 | } | |
4564 | ||
4565 | /* The RX ring scheme is composed of multiple rings which post fresh | |
4566 | * buffers to the chip, and one special ring the chip uses to report | |
4567 | * status back to the host. | |
4568 | * | |
4569 | * The special ring reports the status of received packets to the | |
4570 | * host. The chip does not write into the original descriptor the | |
4571 | * RX buffer was obtained from. The chip simply takes the original | |
4572 | * descriptor as provided by the host, updates the status and length | |
4573 | * field, then writes this into the next status ring entry. | |
4574 | * | |
4575 | * Each ring the host uses to post buffers to the chip is described | |
4576 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4577 | * it is first placed into the on-chip ram. When the packet's length | |
4578 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4579 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4580 | * which is within the range of the new packet's length is chosen. | |
4581 | * | |
4582 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4583 | * sense from a cache coherency perspective. If only the host writes | |
4584 | * to the buffer post rings, and only the chip writes to the rx status | |
4585 | * rings, then cache lines never move beyond shared-modified state. | |
4586 | * If both the host and chip were to write into the same ring, cache line | |
4587 | * eviction could occur since both entities want it in an exclusive state. | |
4588 | */ | |
4589 | static int tg3_rx(struct tg3_napi *tnapi, int budget) | |
4590 | { | |
4591 | struct tg3 *tp = tnapi->tp; | |
4592 | u32 work_mask, rx_std_posted = 0; | |
4593 | u32 std_prod_idx, jmb_prod_idx; | |
4594 | u32 sw_idx = tnapi->rx_rcb_ptr; | |
4595 | u16 hw_idx; | |
4596 | int received; | |
4597 | struct tg3_rx_prodring_set *tpr = tnapi->prodring; | |
4598 | ||
4599 | hw_idx = *(tnapi->rx_rcb_prod_idx); | |
4600 | /* | |
4601 | * We need to order the read of hw_idx and the read of | |
4602 | * the opaque cookie. | |
4603 | */ | |
4604 | rmb(); | |
4605 | work_mask = 0; | |
4606 | received = 0; | |
4607 | std_prod_idx = tpr->rx_std_prod_idx; | |
4608 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
4609 | while (sw_idx != hw_idx && budget > 0) { | |
4610 | struct ring_info *ri; | |
4611 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; | |
4612 | unsigned int len; | |
4613 | struct sk_buff *skb; | |
4614 | dma_addr_t dma_addr; | |
4615 | u32 opaque_key, desc_idx, *post_ptr; | |
4616 | ||
4617 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4618 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4619 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
4620 | ri = &tp->prodring[0].rx_std_buffers[desc_idx]; | |
4621 | dma_addr = pci_unmap_addr(ri, mapping); | |
4622 | skb = ri->skb; | |
4623 | post_ptr = &std_prod_idx; | |
4624 | rx_std_posted++; | |
4625 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
4626 | ri = &tp->prodring[0].rx_jmb_buffers[desc_idx]; | |
4627 | dma_addr = pci_unmap_addr(ri, mapping); | |
4628 | skb = ri->skb; | |
4629 | post_ptr = &jmb_prod_idx; | |
4630 | } else | |
4631 | goto next_pkt_nopost; | |
4632 | ||
4633 | work_mask |= opaque_key; | |
4634 | ||
4635 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
4636 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
4637 | drop_it: | |
4638 | tg3_recycle_rx(tnapi, tpr, opaque_key, | |
4639 | desc_idx, *post_ptr); | |
4640 | drop_it_no_recycle: | |
4641 | /* Other statistics kept track of by card. */ | |
4642 | tp->net_stats.rx_dropped++; | |
4643 | goto next_pkt; | |
4644 | } | |
4645 | ||
4646 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - | |
4647 | ETH_FCS_LEN; | |
4648 | ||
4649 | if (len > RX_COPY_THRESHOLD && | |
4650 | tp->rx_offset == NET_IP_ALIGN) { | |
4651 | /* rx_offset will likely not equal NET_IP_ALIGN | |
4652 | * if this is a 5701 card running in PCI-X mode | |
4653 | * [see tg3_get_invariants()] | |
4654 | */ | |
4655 | int skb_size; | |
4656 | ||
4657 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, | |
4658 | *post_ptr); | |
4659 | if (skb_size < 0) | |
4660 | goto drop_it; | |
4661 | ||
4662 | ri->skb = NULL; | |
4663 | ||
4664 | pci_unmap_single(tp->pdev, dma_addr, skb_size, | |
4665 | PCI_DMA_FROMDEVICE); | |
4666 | ||
4667 | skb_put(skb, len); | |
4668 | } else { | |
4669 | struct sk_buff *copy_skb; | |
4670 | ||
4671 | tg3_recycle_rx(tnapi, tpr, opaque_key, | |
4672 | desc_idx, *post_ptr); | |
4673 | ||
4674 | copy_skb = netdev_alloc_skb(tp->dev, | |
4675 | len + TG3_RAW_IP_ALIGN); | |
4676 | if (copy_skb == NULL) | |
4677 | goto drop_it_no_recycle; | |
4678 | ||
4679 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); | |
4680 | skb_put(copy_skb, len); | |
4681 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
4682 | skb_copy_from_linear_data(skb, copy_skb->data, len); | |
4683 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
4684 | ||
4685 | /* We'll reuse the original ring buffer. */ | |
4686 | skb = copy_skb; | |
4687 | } | |
4688 | ||
4689 | if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) && | |
4690 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
4691 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
4692 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
4693 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4694 | else | |
4695 | skb->ip_summed = CHECKSUM_NONE; | |
4696 | ||
4697 | skb->protocol = eth_type_trans(skb, tp->dev); | |
4698 | ||
4699 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
4700 | skb->protocol != htons(ETH_P_8021Q)) { | |
4701 | dev_kfree_skb(skb); | |
4702 | goto next_pkt; | |
4703 | } | |
4704 | ||
4705 | #if TG3_VLAN_TAG_USED | |
4706 | if (tp->vlgrp != NULL && | |
4707 | desc->type_flags & RXD_FLAG_VLAN) { | |
4708 | vlan_gro_receive(&tnapi->napi, tp->vlgrp, | |
4709 | desc->err_vlan & RXD_VLAN_MASK, skb); | |
4710 | } else | |
4711 | #endif | |
4712 | napi_gro_receive(&tnapi->napi, skb); | |
4713 | ||
4714 | received++; | |
4715 | budget--; | |
4716 | ||
4717 | next_pkt: | |
4718 | (*post_ptr)++; | |
4719 | ||
4720 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
4721 | tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE; | |
4722 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
4723 | tpr->rx_std_prod_idx); | |
4724 | work_mask &= ~RXD_OPAQUE_RING_STD; | |
4725 | rx_std_posted = 0; | |
4726 | } | |
4727 | next_pkt_nopost: | |
4728 | sw_idx++; | |
4729 | sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1); | |
4730 | ||
4731 | /* Refresh hw_idx to see if there is new work */ | |
4732 | if (sw_idx == hw_idx) { | |
4733 | hw_idx = *(tnapi->rx_rcb_prod_idx); | |
4734 | rmb(); | |
4735 | } | |
4736 | } | |
4737 | ||
4738 | /* ACK the status ring. */ | |
4739 | tnapi->rx_rcb_ptr = sw_idx; | |
4740 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
4741 | ||
4742 | /* Refill RX ring(s). */ | |
4743 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { | |
4744 | if (work_mask & RXD_OPAQUE_RING_STD) { | |
4745 | tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE; | |
4746 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
4747 | tpr->rx_std_prod_idx); | |
4748 | } | |
4749 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
4750 | tpr->rx_jmb_prod_idx = jmb_prod_idx % | |
4751 | TG3_RX_JUMBO_RING_SIZE; | |
4752 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
4753 | tpr->rx_jmb_prod_idx); | |
4754 | } | |
4755 | mmiowb(); | |
4756 | } else if (work_mask) { | |
4757 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
4758 | * updated before the producer indices can be updated. | |
4759 | */ | |
4760 | smp_wmb(); | |
4761 | ||
4762 | tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE; | |
4763 | tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE; | |
4764 | ||
4765 | if (tnapi != &tp->napi[1]) | |
4766 | napi_schedule(&tp->napi[1].napi); | |
4767 | } | |
4768 | ||
4769 | return received; | |
4770 | } | |
4771 | ||
4772 | static void tg3_poll_link(struct tg3 *tp) | |
4773 | { | |
4774 | /* handle link change and other phy events */ | |
4775 | if (!(tp->tg3_flags & | |
4776 | (TG3_FLAG_USE_LINKCHG_REG | | |
4777 | TG3_FLAG_POLL_SERDES))) { | |
4778 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; | |
4779 | ||
4780 | if (sblk->status & SD_STATUS_LINK_CHG) { | |
4781 | sblk->status = SD_STATUS_UPDATED | | |
4782 | (sblk->status & ~SD_STATUS_LINK_CHG); | |
4783 | spin_lock(&tp->lock); | |
4784 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
4785 | tw32_f(MAC_STATUS, | |
4786 | (MAC_STATUS_SYNC_CHANGED | | |
4787 | MAC_STATUS_CFG_CHANGED | | |
4788 | MAC_STATUS_MI_COMPLETION | | |
4789 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4790 | udelay(40); | |
4791 | } else | |
4792 | tg3_setup_phy(tp, 0); | |
4793 | spin_unlock(&tp->lock); | |
4794 | } | |
4795 | } | |
4796 | } | |
4797 | ||
4798 | static int tg3_rx_prodring_xfer(struct tg3 *tp, | |
4799 | struct tg3_rx_prodring_set *dpr, | |
4800 | struct tg3_rx_prodring_set *spr) | |
4801 | { | |
4802 | u32 si, di, cpycnt, src_prod_idx; | |
4803 | int i, err = 0; | |
4804 | ||
4805 | while (1) { | |
4806 | src_prod_idx = spr->rx_std_prod_idx; | |
4807 | ||
4808 | /* Make sure updates to the rx_std_buffers[] entries and the | |
4809 | * standard producer index are seen in the correct order. | |
4810 | */ | |
4811 | smp_rmb(); | |
4812 | ||
4813 | if (spr->rx_std_cons_idx == src_prod_idx) | |
4814 | break; | |
4815 | ||
4816 | if (spr->rx_std_cons_idx < src_prod_idx) | |
4817 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
4818 | else | |
4819 | cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx; | |
4820 | ||
4821 | cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx); | |
4822 | ||
4823 | si = spr->rx_std_cons_idx; | |
4824 | di = dpr->rx_std_prod_idx; | |
4825 | ||
4826 | for (i = di; i < di + cpycnt; i++) { | |
4827 | if (dpr->rx_std_buffers[i].skb) { | |
4828 | cpycnt = i - di; | |
4829 | err = -ENOSPC; | |
4830 | break; | |
4831 | } | |
4832 | } | |
4833 | ||
4834 | if (!cpycnt) | |
4835 | break; | |
4836 | ||
4837 | /* Ensure that updates to the rx_std_buffers ring and the | |
4838 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
4839 | * ordered correctly WRT the skb check above. | |
4840 | */ | |
4841 | smp_rmb(); | |
4842 | ||
4843 | memcpy(&dpr->rx_std_buffers[di], | |
4844 | &spr->rx_std_buffers[si], | |
4845 | cpycnt * sizeof(struct ring_info)); | |
4846 | ||
4847 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
4848 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
4849 | sbd = &spr->rx_std[si]; | |
4850 | dbd = &dpr->rx_std[di]; | |
4851 | dbd->addr_hi = sbd->addr_hi; | |
4852 | dbd->addr_lo = sbd->addr_lo; | |
4853 | } | |
4854 | ||
4855 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) % | |
4856 | TG3_RX_RING_SIZE; | |
4857 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) % | |
4858 | TG3_RX_RING_SIZE; | |
4859 | } | |
4860 | ||
4861 | while (1) { | |
4862 | src_prod_idx = spr->rx_jmb_prod_idx; | |
4863 | ||
4864 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
4865 | * the jumbo producer index are seen in the correct order. | |
4866 | */ | |
4867 | smp_rmb(); | |
4868 | ||
4869 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
4870 | break; | |
4871 | ||
4872 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
4873 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
4874 | else | |
4875 | cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx; | |
4876 | ||
4877 | cpycnt = min(cpycnt, | |
4878 | TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx); | |
4879 | ||
4880 | si = spr->rx_jmb_cons_idx; | |
4881 | di = dpr->rx_jmb_prod_idx; | |
4882 | ||
4883 | for (i = di; i < di + cpycnt; i++) { | |
4884 | if (dpr->rx_jmb_buffers[i].skb) { | |
4885 | cpycnt = i - di; | |
4886 | err = -ENOSPC; | |
4887 | break; | |
4888 | } | |
4889 | } | |
4890 | ||
4891 | if (!cpycnt) | |
4892 | break; | |
4893 | ||
4894 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
4895 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
4896 | * ordered correctly WRT the skb check above. | |
4897 | */ | |
4898 | smp_rmb(); | |
4899 | ||
4900 | memcpy(&dpr->rx_jmb_buffers[di], | |
4901 | &spr->rx_jmb_buffers[si], | |
4902 | cpycnt * sizeof(struct ring_info)); | |
4903 | ||
4904 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
4905 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
4906 | sbd = &spr->rx_jmb[si].std; | |
4907 | dbd = &dpr->rx_jmb[di].std; | |
4908 | dbd->addr_hi = sbd->addr_hi; | |
4909 | dbd->addr_lo = sbd->addr_lo; | |
4910 | } | |
4911 | ||
4912 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) % | |
4913 | TG3_RX_JUMBO_RING_SIZE; | |
4914 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) % | |
4915 | TG3_RX_JUMBO_RING_SIZE; | |
4916 | } | |
4917 | ||
4918 | return err; | |
4919 | } | |
4920 | ||
4921 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) | |
4922 | { | |
4923 | struct tg3 *tp = tnapi->tp; | |
4924 | ||
4925 | /* run TX completion thread */ | |
4926 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { | |
4927 | tg3_tx(tnapi); | |
4928 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
4929 | return work_done; | |
4930 | } | |
4931 | ||
4932 | /* run RX thread, within the bounds set by NAPI. | |
4933 | * All RX "locking" is done by ensuring outside | |
4934 | * code synchronizes with tg3->napi.poll() | |
4935 | */ | |
4936 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) | |
4937 | work_done += tg3_rx(tnapi, budget - work_done); | |
4938 | ||
4939 | if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) { | |
4940 | struct tg3_rx_prodring_set *dpr = &tp->prodring[0]; | |
4941 | int i, err = 0; | |
4942 | u32 std_prod_idx = dpr->rx_std_prod_idx; | |
4943 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
4944 | ||
4945 | for (i = 1; i < tp->irq_cnt; i++) | |
4946 | err |= tg3_rx_prodring_xfer(tp, dpr, | |
4947 | tp->napi[i].prodring); | |
4948 | ||
4949 | wmb(); | |
4950 | ||
4951 | if (std_prod_idx != dpr->rx_std_prod_idx) | |
4952 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
4953 | dpr->rx_std_prod_idx); | |
4954 | ||
4955 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) | |
4956 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
4957 | dpr->rx_jmb_prod_idx); | |
4958 | ||
4959 | mmiowb(); | |
4960 | ||
4961 | if (err) | |
4962 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
4963 | } | |
4964 | ||
4965 | return work_done; | |
4966 | } | |
4967 | ||
4968 | static int tg3_poll_msix(struct napi_struct *napi, int budget) | |
4969 | { | |
4970 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
4971 | struct tg3 *tp = tnapi->tp; | |
4972 | int work_done = 0; | |
4973 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
4974 | ||
4975 | while (1) { | |
4976 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
4977 | ||
4978 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
4979 | goto tx_recovery; | |
4980 | ||
4981 | if (unlikely(work_done >= budget)) | |
4982 | break; | |
4983 | ||
4984 | /* tp->last_tag is used in tg3_restart_ints() below | |
4985 | * to tell the hw how much work has been processed, | |
4986 | * so we must read it before checking for more work. | |
4987 | */ | |
4988 | tnapi->last_tag = sblk->status_tag; | |
4989 | tnapi->last_irq_tag = tnapi->last_tag; | |
4990 | rmb(); | |
4991 | ||
4992 | /* check for RX/TX work to do */ | |
4993 | if (sblk->idx[0].tx_consumer == tnapi->tx_cons && | |
4994 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) { | |
4995 | napi_complete(napi); | |
4996 | /* Reenable interrupts. */ | |
4997 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
4998 | mmiowb(); | |
4999 | break; | |
5000 | } | |
5001 | } | |
5002 | ||
5003 | return work_done; | |
5004 | ||
5005 | tx_recovery: | |
5006 | /* work_done is guaranteed to be less than budget. */ | |
5007 | napi_complete(napi); | |
5008 | schedule_work(&tp->reset_task); | |
5009 | return work_done; | |
5010 | } | |
5011 | ||
5012 | static int tg3_poll(struct napi_struct *napi, int budget) | |
5013 | { | |
5014 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5015 | struct tg3 *tp = tnapi->tp; | |
5016 | int work_done = 0; | |
5017 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5018 | ||
5019 | while (1) { | |
5020 | tg3_poll_link(tp); | |
5021 | ||
5022 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5023 | ||
5024 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5025 | goto tx_recovery; | |
5026 | ||
5027 | if (unlikely(work_done >= budget)) | |
5028 | break; | |
5029 | ||
5030 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
5031 | /* tp->last_tag is used in tg3_int_reenable() below | |
5032 | * to tell the hw how much work has been processed, | |
5033 | * so we must read it before checking for more work. | |
5034 | */ | |
5035 | tnapi->last_tag = sblk->status_tag; | |
5036 | tnapi->last_irq_tag = tnapi->last_tag; | |
5037 | rmb(); | |
5038 | } else | |
5039 | sblk->status &= ~SD_STATUS_UPDATED; | |
5040 | ||
5041 | if (likely(!tg3_has_work(tnapi))) { | |
5042 | napi_complete(napi); | |
5043 | tg3_int_reenable(tnapi); | |
5044 | break; | |
5045 | } | |
5046 | } | |
5047 | ||
5048 | return work_done; | |
5049 | ||
5050 | tx_recovery: | |
5051 | /* work_done is guaranteed to be less than budget. */ | |
5052 | napi_complete(napi); | |
5053 | schedule_work(&tp->reset_task); | |
5054 | return work_done; | |
5055 | } | |
5056 | ||
5057 | static void tg3_irq_quiesce(struct tg3 *tp) | |
5058 | { | |
5059 | int i; | |
5060 | ||
5061 | BUG_ON(tp->irq_sync); | |
5062 | ||
5063 | tp->irq_sync = 1; | |
5064 | smp_mb(); | |
5065 | ||
5066 | for (i = 0; i < tp->irq_cnt; i++) | |
5067 | synchronize_irq(tp->napi[i].irq_vec); | |
5068 | } | |
5069 | ||
5070 | static inline int tg3_irq_sync(struct tg3 *tp) | |
5071 | { | |
5072 | return tp->irq_sync; | |
5073 | } | |
5074 | ||
5075 | /* Fully shutdown all tg3 driver activity elsewhere in the system. | |
5076 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
5077 | * with as well. Most of the time, this is not necessary except when | |
5078 | * shutting down the device. | |
5079 | */ | |
5080 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
5081 | { | |
5082 | spin_lock_bh(&tp->lock); | |
5083 | if (irq_sync) | |
5084 | tg3_irq_quiesce(tp); | |
5085 | } | |
5086 | ||
5087 | static inline void tg3_full_unlock(struct tg3 *tp) | |
5088 | { | |
5089 | spin_unlock_bh(&tp->lock); | |
5090 | } | |
5091 | ||
5092 | /* One-shot MSI handler - Chip automatically disables interrupt | |
5093 | * after sending MSI so driver doesn't have to do it. | |
5094 | */ | |
5095 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) | |
5096 | { | |
5097 | struct tg3_napi *tnapi = dev_id; | |
5098 | struct tg3 *tp = tnapi->tp; | |
5099 | ||
5100 | prefetch(tnapi->hw_status); | |
5101 | if (tnapi->rx_rcb) | |
5102 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
5103 | ||
5104 | if (likely(!tg3_irq_sync(tp))) | |
5105 | napi_schedule(&tnapi->napi); | |
5106 | ||
5107 | return IRQ_HANDLED; | |
5108 | } | |
5109 | ||
5110 | /* MSI ISR - No need to check for interrupt sharing and no need to | |
5111 | * flush status block and interrupt mailbox. PCI ordering rules | |
5112 | * guarantee that MSI will arrive after the status block. | |
5113 | */ | |
5114 | static irqreturn_t tg3_msi(int irq, void *dev_id) | |
5115 | { | |
5116 | struct tg3_napi *tnapi = dev_id; | |
5117 | struct tg3 *tp = tnapi->tp; | |
5118 | ||
5119 | prefetch(tnapi->hw_status); | |
5120 | if (tnapi->rx_rcb) | |
5121 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
5122 | /* | |
5123 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5124 | * chip-internal interrupt pending events. | |
5125 | * Writing non-zero to intr-mbox-0 additional tells the | |
5126 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5127 | * event coalescing. | |
5128 | */ | |
5129 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
5130 | if (likely(!tg3_irq_sync(tp))) | |
5131 | napi_schedule(&tnapi->napi); | |
5132 | ||
5133 | return IRQ_RETVAL(1); | |
5134 | } | |
5135 | ||
5136 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) | |
5137 | { | |
5138 | struct tg3_napi *tnapi = dev_id; | |
5139 | struct tg3 *tp = tnapi->tp; | |
5140 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5141 | unsigned int handled = 1; | |
5142 | ||
5143 | /* In INTx mode, it is possible for the interrupt to arrive at | |
5144 | * the CPU before the status block posted prior to the interrupt. | |
5145 | * Reading the PCI State register will confirm whether the | |
5146 | * interrupt is ours and will flush the status block. | |
5147 | */ | |
5148 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { | |
5149 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
5150 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5151 | handled = 0; | |
5152 | goto out; | |
5153 | } | |
5154 | } | |
5155 | ||
5156 | /* | |
5157 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5158 | * chip-internal interrupt pending events. | |
5159 | * Writing non-zero to intr-mbox-0 additional tells the | |
5160 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5161 | * event coalescing. | |
5162 | * | |
5163 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5164 | * spurious interrupts. The flush impacts performance but | |
5165 | * excessive spurious interrupts can be worse in some cases. | |
5166 | */ | |
5167 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
5168 | if (tg3_irq_sync(tp)) | |
5169 | goto out; | |
5170 | sblk->status &= ~SD_STATUS_UPDATED; | |
5171 | if (likely(tg3_has_work(tnapi))) { | |
5172 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
5173 | napi_schedule(&tnapi->napi); | |
5174 | } else { | |
5175 | /* No work, shared interrupt perhaps? re-enable | |
5176 | * interrupts, and flush that PCI write | |
5177 | */ | |
5178 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
5179 | 0x00000000); | |
5180 | } | |
5181 | out: | |
5182 | return IRQ_RETVAL(handled); | |
5183 | } | |
5184 | ||
5185 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) | |
5186 | { | |
5187 | struct tg3_napi *tnapi = dev_id; | |
5188 | struct tg3 *tp = tnapi->tp; | |
5189 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5190 | unsigned int handled = 1; | |
5191 | ||
5192 | /* In INTx mode, it is possible for the interrupt to arrive at | |
5193 | * the CPU before the status block posted prior to the interrupt. | |
5194 | * Reading the PCI State register will confirm whether the | |
5195 | * interrupt is ours and will flush the status block. | |
5196 | */ | |
5197 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { | |
5198 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
5199 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5200 | handled = 0; | |
5201 | goto out; | |
5202 | } | |
5203 | } | |
5204 | ||
5205 | /* | |
5206 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
5207 | * chip-internal interrupt pending events. | |
5208 | * writing non-zero to intr-mbox-0 additional tells the | |
5209 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5210 | * event coalescing. | |
5211 | * | |
5212 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5213 | * spurious interrupts. The flush impacts performance but | |
5214 | * excessive spurious interrupts can be worse in some cases. | |
5215 | */ | |
5216 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
5217 | ||
5218 | /* | |
5219 | * In a shared interrupt configuration, sometimes other devices' | |
5220 | * interrupts will scream. We record the current status tag here | |
5221 | * so that the above check can report that the screaming interrupts | |
5222 | * are unhandled. Eventually they will be silenced. | |
5223 | */ | |
5224 | tnapi->last_irq_tag = sblk->status_tag; | |
5225 | ||
5226 | if (tg3_irq_sync(tp)) | |
5227 | goto out; | |
5228 | ||
5229 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
5230 | ||
5231 | napi_schedule(&tnapi->napi); | |
5232 | ||
5233 | out: | |
5234 | return IRQ_RETVAL(handled); | |
5235 | } | |
5236 | ||
5237 | /* ISR for interrupt test */ | |
5238 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) | |
5239 | { | |
5240 | struct tg3_napi *tnapi = dev_id; | |
5241 | struct tg3 *tp = tnapi->tp; | |
5242 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5243 | ||
5244 | if ((sblk->status & SD_STATUS_UPDATED) || | |
5245 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5246 | tg3_disable_ints(tp); | |
5247 | return IRQ_RETVAL(1); | |
5248 | } | |
5249 | return IRQ_RETVAL(0); | |
5250 | } | |
5251 | ||
5252 | static int tg3_init_hw(struct tg3 *, int); | |
5253 | static int tg3_halt(struct tg3 *, int, int); | |
5254 | ||
5255 | /* Restart hardware after configuration changes, self-test, etc. | |
5256 | * Invoked with tp->lock held. | |
5257 | */ | |
5258 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
5259 | __releases(tp->lock) | |
5260 | __acquires(tp->lock) | |
5261 | { | |
5262 | int err; | |
5263 | ||
5264 | err = tg3_init_hw(tp, reset_phy); | |
5265 | if (err) { | |
5266 | printk(KERN_ERR PFX "%s: Failed to re-initialize device, " | |
5267 | "aborting.\n", tp->dev->name); | |
5268 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
5269 | tg3_full_unlock(tp); | |
5270 | del_timer_sync(&tp->timer); | |
5271 | tp->irq_sync = 0; | |
5272 | tg3_napi_enable(tp); | |
5273 | dev_close(tp->dev); | |
5274 | tg3_full_lock(tp, 0); | |
5275 | } | |
5276 | return err; | |
5277 | } | |
5278 | ||
5279 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5280 | static void tg3_poll_controller(struct net_device *dev) | |
5281 | { | |
5282 | int i; | |
5283 | struct tg3 *tp = netdev_priv(dev); | |
5284 | ||
5285 | for (i = 0; i < tp->irq_cnt; i++) | |
5286 | tg3_interrupt(tp->napi[i].irq_vec, dev); | |
5287 | } | |
5288 | #endif | |
5289 | ||
5290 | static void tg3_reset_task(struct work_struct *work) | |
5291 | { | |
5292 | struct tg3 *tp = container_of(work, struct tg3, reset_task); | |
5293 | int err; | |
5294 | unsigned int restart_timer; | |
5295 | ||
5296 | tg3_full_lock(tp, 0); | |
5297 | ||
5298 | if (!netif_running(tp->dev)) { | |
5299 | tg3_full_unlock(tp); | |
5300 | return; | |
5301 | } | |
5302 | ||
5303 | tg3_full_unlock(tp); | |
5304 | ||
5305 | tg3_phy_stop(tp); | |
5306 | ||
5307 | tg3_netif_stop(tp); | |
5308 | ||
5309 | tg3_full_lock(tp, 1); | |
5310 | ||
5311 | restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; | |
5312 | tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; | |
5313 | ||
5314 | if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) { | |
5315 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
5316 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
5317 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
5318 | tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; | |
5319 | } | |
5320 | ||
5321 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
5322 | err = tg3_init_hw(tp, 1); | |
5323 | if (err) | |
5324 | goto out; | |
5325 | ||
5326 | tg3_netif_start(tp); | |
5327 | ||
5328 | if (restart_timer) | |
5329 | mod_timer(&tp->timer, jiffies + 1); | |
5330 | ||
5331 | out: | |
5332 | tg3_full_unlock(tp); | |
5333 | ||
5334 | if (!err) | |
5335 | tg3_phy_start(tp); | |
5336 | } | |
5337 | ||
5338 | static void tg3_dump_short_state(struct tg3 *tp) | |
5339 | { | |
5340 | printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n", | |
5341 | tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS)); | |
5342 | printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n", | |
5343 | tr32(RDMAC_STATUS), tr32(WDMAC_STATUS)); | |
5344 | } | |
5345 | ||
5346 | static void tg3_tx_timeout(struct net_device *dev) | |
5347 | { | |
5348 | struct tg3 *tp = netdev_priv(dev); | |
5349 | ||
5350 | if (netif_msg_tx_err(tp)) { | |
5351 | printk(KERN_ERR PFX "%s: transmit timed out, resetting\n", | |
5352 | dev->name); | |
5353 | tg3_dump_short_state(tp); | |
5354 | } | |
5355 | ||
5356 | schedule_work(&tp->reset_task); | |
5357 | } | |
5358 | ||
5359 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ | |
5360 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5361 | { | |
5362 | u32 base = (u32) mapping & 0xffffffff; | |
5363 | ||
5364 | return ((base > 0xffffdcc0) && | |
5365 | (base + len + 8 < base)); | |
5366 | } | |
5367 | ||
5368 | /* Test for DMA addresses > 40-bit */ | |
5369 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5370 | int len) | |
5371 | { | |
5372 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
5373 | if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) | |
5374 | return (((u64) mapping + len) > DMA_BIT_MASK(40)); | |
5375 | return 0; | |
5376 | #else | |
5377 | return 0; | |
5378 | #endif | |
5379 | } | |
5380 | ||
5381 | static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32); | |
5382 | ||
5383 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ | |
5384 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, | |
5385 | struct sk_buff *skb, u32 last_plus_one, | |
5386 | u32 *start, u32 base_flags, u32 mss) | |
5387 | { | |
5388 | struct tg3 *tp = tnapi->tp; | |
5389 | struct sk_buff *new_skb; | |
5390 | dma_addr_t new_addr = 0; | |
5391 | u32 entry = *start; | |
5392 | int i, ret = 0; | |
5393 | ||
5394 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
5395 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5396 | else { | |
5397 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5398 | ||
5399 | new_skb = skb_copy_expand(skb, | |
5400 | skb_headroom(skb) + more_headroom, | |
5401 | skb_tailroom(skb), GFP_ATOMIC); | |
5402 | } | |
5403 | ||
5404 | if (!new_skb) { | |
5405 | ret = -1; | |
5406 | } else { | |
5407 | /* New SKB is guaranteed to be linear. */ | |
5408 | entry = *start; | |
5409 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, | |
5410 | PCI_DMA_TODEVICE); | |
5411 | /* Make sure the mapping succeeded */ | |
5412 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
5413 | ret = -1; | |
5414 | dev_kfree_skb(new_skb); | |
5415 | new_skb = NULL; | |
5416 | ||
5417 | /* Make sure new skb does not cross any 4G boundaries. | |
5418 | * Drop the packet if it does. | |
5419 | */ | |
5420 | } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && | |
5421 | tg3_4g_overflow_test(new_addr, new_skb->len)) { | |
5422 | pci_unmap_single(tp->pdev, new_addr, new_skb->len, | |
5423 | PCI_DMA_TODEVICE); | |
5424 | ret = -1; | |
5425 | dev_kfree_skb(new_skb); | |
5426 | new_skb = NULL; | |
5427 | } else { | |
5428 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, | |
5429 | base_flags, 1 | (mss << 1)); | |
5430 | *start = NEXT_TX(entry); | |
5431 | } | |
5432 | } | |
5433 | ||
5434 | /* Now clean up the sw ring entries. */ | |
5435 | i = 0; | |
5436 | while (entry != last_plus_one) { | |
5437 | int len; | |
5438 | ||
5439 | if (i == 0) | |
5440 | len = skb_headlen(skb); | |
5441 | else | |
5442 | len = skb_shinfo(skb)->frags[i-1].size; | |
5443 | ||
5444 | pci_unmap_single(tp->pdev, | |
5445 | pci_unmap_addr(&tnapi->tx_buffers[entry], | |
5446 | mapping), | |
5447 | len, PCI_DMA_TODEVICE); | |
5448 | if (i == 0) { | |
5449 | tnapi->tx_buffers[entry].skb = new_skb; | |
5450 | pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, | |
5451 | new_addr); | |
5452 | } else { | |
5453 | tnapi->tx_buffers[entry].skb = NULL; | |
5454 | } | |
5455 | entry = NEXT_TX(entry); | |
5456 | i++; | |
5457 | } | |
5458 | ||
5459 | dev_kfree_skb(skb); | |
5460 | ||
5461 | return ret; | |
5462 | } | |
5463 | ||
5464 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, | |
5465 | dma_addr_t mapping, int len, u32 flags, | |
5466 | u32 mss_and_is_end) | |
5467 | { | |
5468 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; | |
5469 | int is_end = (mss_and_is_end & 0x1); | |
5470 | u32 mss = (mss_and_is_end >> 1); | |
5471 | u32 vlan_tag = 0; | |
5472 | ||
5473 | if (is_end) | |
5474 | flags |= TXD_FLAG_END; | |
5475 | if (flags & TXD_FLAG_VLAN) { | |
5476 | vlan_tag = flags >> 16; | |
5477 | flags &= 0xffff; | |
5478 | } | |
5479 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5480 | ||
5481 | txd->addr_hi = ((u64) mapping >> 32); | |
5482 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5483 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5484 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5485 | } | |
5486 | ||
5487 | /* hard_start_xmit for devices that don't have any bugs and | |
5488 | * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only. | |
5489 | */ | |
5490 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, | |
5491 | struct net_device *dev) | |
5492 | { | |
5493 | struct tg3 *tp = netdev_priv(dev); | |
5494 | u32 len, entry, base_flags, mss; | |
5495 | dma_addr_t mapping; | |
5496 | struct tg3_napi *tnapi; | |
5497 | struct netdev_queue *txq; | |
5498 | unsigned int i, last; | |
5499 | ||
5500 | ||
5501 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); | |
5502 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
5503 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) | |
5504 | tnapi++; | |
5505 | ||
5506 | /* We are running in BH disabled context with netif_tx_lock | |
5507 | * and TX reclaim runs via tp->napi.poll inside of a software | |
5508 | * interrupt. Furthermore, IRQ processing runs lockless so we have | |
5509 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5510 | */ | |
5511 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { | |
5512 | if (!netif_tx_queue_stopped(txq)) { | |
5513 | netif_tx_stop_queue(txq); | |
5514 | ||
5515 | /* This is a hard error, log it. */ | |
5516 | printk(KERN_ERR PFX "%s: BUG! Tx Ring full when " | |
5517 | "queue awake!\n", dev->name); | |
5518 | } | |
5519 | return NETDEV_TX_BUSY; | |
5520 | } | |
5521 | ||
5522 | entry = tnapi->tx_prod; | |
5523 | base_flags = 0; | |
5524 | mss = 0; | |
5525 | if ((mss = skb_shinfo(skb)->gso_size) != 0) { | |
5526 | int tcp_opt_len, ip_tcp_len; | |
5527 | u32 hdrlen; | |
5528 | ||
5529 | if (skb_header_cloned(skb) && | |
5530 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5531 | dev_kfree_skb(skb); | |
5532 | goto out_unlock; | |
5533 | } | |
5534 | ||
5535 | if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) | |
5536 | hdrlen = skb_headlen(skb) - ETH_HLEN; | |
5537 | else { | |
5538 | struct iphdr *iph = ip_hdr(skb); | |
5539 | ||
5540 | tcp_opt_len = tcp_optlen(skb); | |
5541 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
5542 | ||
5543 | iph->check = 0; | |
5544 | iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); | |
5545 | hdrlen = ip_tcp_len + tcp_opt_len; | |
5546 | } | |
5547 | ||
5548 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { | |
5549 | mss |= (hdrlen & 0xc) << 12; | |
5550 | if (hdrlen & 0x10) | |
5551 | base_flags |= 0x00000010; | |
5552 | base_flags |= (hdrlen & 0x3e0) << 5; | |
5553 | } else | |
5554 | mss |= hdrlen << 9; | |
5555 | ||
5556 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | | |
5557 | TXD_FLAG_CPU_POST_DMA); | |
5558 | ||
5559 | tcp_hdr(skb)->check = 0; | |
5560 | ||
5561 | } | |
5562 | else if (skb->ip_summed == CHECKSUM_PARTIAL) | |
5563 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
5564 | #if TG3_VLAN_TAG_USED | |
5565 | if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) | |
5566 | base_flags |= (TXD_FLAG_VLAN | | |
5567 | (vlan_tx_tag_get(skb) << 16)); | |
5568 | #endif | |
5569 | ||
5570 | len = skb_headlen(skb); | |
5571 | ||
5572 | /* Queue skb data, a.k.a. the main skb fragment. */ | |
5573 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
5574 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
5575 | dev_kfree_skb(skb); | |
5576 | goto out_unlock; | |
5577 | } | |
5578 | ||
5579 | tnapi->tx_buffers[entry].skb = skb; | |
5580 | pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); | |
5581 | ||
5582 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && | |
5583 | !mss && skb->len > ETH_DATA_LEN) | |
5584 | base_flags |= TXD_FLAG_JMB_PKT; | |
5585 | ||
5586 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, | |
5587 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); | |
5588 | ||
5589 | entry = NEXT_TX(entry); | |
5590 | ||
5591 | /* Now loop through additional data fragments, and queue them. */ | |
5592 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5593 | last = skb_shinfo(skb)->nr_frags - 1; | |
5594 | for (i = 0; i <= last; i++) { | |
5595 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5596 | ||
5597 | len = frag->size; | |
5598 | mapping = pci_map_page(tp->pdev, | |
5599 | frag->page, | |
5600 | frag->page_offset, | |
5601 | len, PCI_DMA_TODEVICE); | |
5602 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
5603 | goto dma_error; | |
5604 | ||
5605 | tnapi->tx_buffers[entry].skb = NULL; | |
5606 | pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, | |
5607 | mapping); | |
5608 | ||
5609 | tg3_set_txd(tnapi, entry, mapping, len, | |
5610 | base_flags, (i == last) | (mss << 1)); | |
5611 | ||
5612 | entry = NEXT_TX(entry); | |
5613 | } | |
5614 | } | |
5615 | ||
5616 | /* Packets are ready, update Tx producer idx local and on card. */ | |
5617 | tw32_tx_mbox(tnapi->prodmbox, entry); | |
5618 | ||
5619 | tnapi->tx_prod = entry; | |
5620 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
5621 | netif_tx_stop_queue(txq); | |
5622 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) | |
5623 | netif_tx_wake_queue(txq); | |
5624 | } | |
5625 | ||
5626 | out_unlock: | |
5627 | mmiowb(); | |
5628 | ||
5629 | return NETDEV_TX_OK; | |
5630 | ||
5631 | dma_error: | |
5632 | last = i; | |
5633 | entry = tnapi->tx_prod; | |
5634 | tnapi->tx_buffers[entry].skb = NULL; | |
5635 | pci_unmap_single(tp->pdev, | |
5636 | pci_unmap_addr(&tnapi->tx_buffers[entry], mapping), | |
5637 | skb_headlen(skb), | |
5638 | PCI_DMA_TODEVICE); | |
5639 | for (i = 0; i <= last; i++) { | |
5640 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5641 | entry = NEXT_TX(entry); | |
5642 | ||
5643 | pci_unmap_page(tp->pdev, | |
5644 | pci_unmap_addr(&tnapi->tx_buffers[entry], | |
5645 | mapping), | |
5646 | frag->size, PCI_DMA_TODEVICE); | |
5647 | } | |
5648 | ||
5649 | dev_kfree_skb(skb); | |
5650 | return NETDEV_TX_OK; | |
5651 | } | |
5652 | ||
5653 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *, | |
5654 | struct net_device *); | |
5655 | ||
5656 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5657 | * TSO header is greater than 80 bytes. | |
5658 | */ | |
5659 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5660 | { | |
5661 | struct sk_buff *segs, *nskb; | |
5662 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; | |
5663 | ||
5664 | /* Estimate the number of fragments in the worst case */ | |
5665 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { | |
5666 | netif_stop_queue(tp->dev); | |
5667 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) | |
5668 | return NETDEV_TX_BUSY; | |
5669 | ||
5670 | netif_wake_queue(tp->dev); | |
5671 | } | |
5672 | ||
5673 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
5674 | if (IS_ERR(segs)) | |
5675 | goto tg3_tso_bug_end; | |
5676 | ||
5677 | do { | |
5678 | nskb = segs; | |
5679 | segs = segs->next; | |
5680 | nskb->next = NULL; | |
5681 | tg3_start_xmit_dma_bug(nskb, tp->dev); | |
5682 | } while (segs); | |
5683 | ||
5684 | tg3_tso_bug_end: | |
5685 | dev_kfree_skb(skb); | |
5686 | ||
5687 | return NETDEV_TX_OK; | |
5688 | } | |
5689 | ||
5690 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and | |
5691 | * support TG3_FLG2_HW_TSO_1 or firmware TSO only. | |
5692 | */ | |
5693 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb, | |
5694 | struct net_device *dev) | |
5695 | { | |
5696 | struct tg3 *tp = netdev_priv(dev); | |
5697 | u32 len, entry, base_flags, mss; | |
5698 | int would_hit_hwbug; | |
5699 | dma_addr_t mapping; | |
5700 | struct tg3_napi *tnapi; | |
5701 | struct netdev_queue *txq; | |
5702 | unsigned int i, last; | |
5703 | ||
5704 | ||
5705 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); | |
5706 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
5707 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) | |
5708 | tnapi++; | |
5709 | ||
5710 | /* We are running in BH disabled context with netif_tx_lock | |
5711 | * and TX reclaim runs via tp->napi.poll inside of a software | |
5712 | * interrupt. Furthermore, IRQ processing runs lockless so we have | |
5713 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5714 | */ | |
5715 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { | |
5716 | if (!netif_tx_queue_stopped(txq)) { | |
5717 | netif_tx_stop_queue(txq); | |
5718 | ||
5719 | /* This is a hard error, log it. */ | |
5720 | printk(KERN_ERR PFX "%s: BUG! Tx Ring full when " | |
5721 | "queue awake!\n", dev->name); | |
5722 | } | |
5723 | return NETDEV_TX_BUSY; | |
5724 | } | |
5725 | ||
5726 | entry = tnapi->tx_prod; | |
5727 | base_flags = 0; | |
5728 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
5729 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
5730 | ||
5731 | if ((mss = skb_shinfo(skb)->gso_size) != 0) { | |
5732 | struct iphdr *iph; | |
5733 | u32 tcp_opt_len, ip_tcp_len, hdr_len; | |
5734 | ||
5735 | if (skb_header_cloned(skb) && | |
5736 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5737 | dev_kfree_skb(skb); | |
5738 | goto out_unlock; | |
5739 | } | |
5740 | ||
5741 | tcp_opt_len = tcp_optlen(skb); | |
5742 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
5743 | ||
5744 | hdr_len = ip_tcp_len + tcp_opt_len; | |
5745 | if (unlikely((ETH_HLEN + hdr_len) > 80) && | |
5746 | (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) | |
5747 | return (tg3_tso_bug(tp, skb)); | |
5748 | ||
5749 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | | |
5750 | TXD_FLAG_CPU_POST_DMA); | |
5751 | ||
5752 | iph = ip_hdr(skb); | |
5753 | iph->check = 0; | |
5754 | iph->tot_len = htons(mss + hdr_len); | |
5755 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { | |
5756 | tcp_hdr(skb)->check = 0; | |
5757 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; | |
5758 | } else | |
5759 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5760 | iph->daddr, 0, | |
5761 | IPPROTO_TCP, | |
5762 | 0); | |
5763 | ||
5764 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { | |
5765 | mss |= (hdr_len & 0xc) << 12; | |
5766 | if (hdr_len & 0x10) | |
5767 | base_flags |= 0x00000010; | |
5768 | base_flags |= (hdr_len & 0x3e0) << 5; | |
5769 | } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) | |
5770 | mss |= hdr_len << 9; | |
5771 | else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) || | |
5772 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
5773 | if (tcp_opt_len || iph->ihl > 5) { | |
5774 | int tsflags; | |
5775 | ||
5776 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); | |
5777 | mss |= (tsflags << 11); | |
5778 | } | |
5779 | } else { | |
5780 | if (tcp_opt_len || iph->ihl > 5) { | |
5781 | int tsflags; | |
5782 | ||
5783 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); | |
5784 | base_flags |= tsflags << 12; | |
5785 | } | |
5786 | } | |
5787 | } | |
5788 | #if TG3_VLAN_TAG_USED | |
5789 | if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) | |
5790 | base_flags |= (TXD_FLAG_VLAN | | |
5791 | (vlan_tx_tag_get(skb) << 16)); | |
5792 | #endif | |
5793 | ||
5794 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && | |
5795 | !mss && skb->len > ETH_DATA_LEN) | |
5796 | base_flags |= TXD_FLAG_JMB_PKT; | |
5797 | ||
5798 | len = skb_headlen(skb); | |
5799 | ||
5800 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
5801 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
5802 | dev_kfree_skb(skb); | |
5803 | goto out_unlock; | |
5804 | } | |
5805 | ||
5806 | tnapi->tx_buffers[entry].skb = skb; | |
5807 | pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); | |
5808 | ||
5809 | would_hit_hwbug = 0; | |
5810 | ||
5811 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8) | |
5812 | would_hit_hwbug = 1; | |
5813 | ||
5814 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && | |
5815 | tg3_4g_overflow_test(mapping, len)) | |
5816 | would_hit_hwbug = 1; | |
5817 | ||
5818 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && | |
5819 | tg3_40bit_overflow_test(tp, mapping, len)) | |
5820 | would_hit_hwbug = 1; | |
5821 | ||
5822 | if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG) | |
5823 | would_hit_hwbug = 1; | |
5824 | ||
5825 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, | |
5826 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); | |
5827 | ||
5828 | entry = NEXT_TX(entry); | |
5829 | ||
5830 | /* Now loop through additional data fragments, and queue them. */ | |
5831 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5832 | last = skb_shinfo(skb)->nr_frags - 1; | |
5833 | for (i = 0; i <= last; i++) { | |
5834 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5835 | ||
5836 | len = frag->size; | |
5837 | mapping = pci_map_page(tp->pdev, | |
5838 | frag->page, | |
5839 | frag->page_offset, | |
5840 | len, PCI_DMA_TODEVICE); | |
5841 | ||
5842 | tnapi->tx_buffers[entry].skb = NULL; | |
5843 | pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, | |
5844 | mapping); | |
5845 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
5846 | goto dma_error; | |
5847 | ||
5848 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && | |
5849 | len <= 8) | |
5850 | would_hit_hwbug = 1; | |
5851 | ||
5852 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && | |
5853 | tg3_4g_overflow_test(mapping, len)) | |
5854 | would_hit_hwbug = 1; | |
5855 | ||
5856 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && | |
5857 | tg3_40bit_overflow_test(tp, mapping, len)) | |
5858 | would_hit_hwbug = 1; | |
5859 | ||
5860 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
5861 | tg3_set_txd(tnapi, entry, mapping, len, | |
5862 | base_flags, (i == last)|(mss << 1)); | |
5863 | else | |
5864 | tg3_set_txd(tnapi, entry, mapping, len, | |
5865 | base_flags, (i == last)); | |
5866 | ||
5867 | entry = NEXT_TX(entry); | |
5868 | } | |
5869 | } | |
5870 | ||
5871 | if (would_hit_hwbug) { | |
5872 | u32 last_plus_one = entry; | |
5873 | u32 start; | |
5874 | ||
5875 | start = entry - 1 - skb_shinfo(skb)->nr_frags; | |
5876 | start &= (TG3_TX_RING_SIZE - 1); | |
5877 | ||
5878 | /* If the workaround fails due to memory/mapping | |
5879 | * failure, silently drop this packet. | |
5880 | */ | |
5881 | if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one, | |
5882 | &start, base_flags, mss)) | |
5883 | goto out_unlock; | |
5884 | ||
5885 | entry = start; | |
5886 | } | |
5887 | ||
5888 | /* Packets are ready, update Tx producer idx local and on card. */ | |
5889 | tw32_tx_mbox(tnapi->prodmbox, entry); | |
5890 | ||
5891 | tnapi->tx_prod = entry; | |
5892 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
5893 | netif_tx_stop_queue(txq); | |
5894 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) | |
5895 | netif_tx_wake_queue(txq); | |
5896 | } | |
5897 | ||
5898 | out_unlock: | |
5899 | mmiowb(); | |
5900 | ||
5901 | return NETDEV_TX_OK; | |
5902 | ||
5903 | dma_error: | |
5904 | last = i; | |
5905 | entry = tnapi->tx_prod; | |
5906 | tnapi->tx_buffers[entry].skb = NULL; | |
5907 | pci_unmap_single(tp->pdev, | |
5908 | pci_unmap_addr(&tnapi->tx_buffers[entry], mapping), | |
5909 | skb_headlen(skb), | |
5910 | PCI_DMA_TODEVICE); | |
5911 | for (i = 0; i <= last; i++) { | |
5912 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5913 | entry = NEXT_TX(entry); | |
5914 | ||
5915 | pci_unmap_page(tp->pdev, | |
5916 | pci_unmap_addr(&tnapi->tx_buffers[entry], | |
5917 | mapping), | |
5918 | frag->size, PCI_DMA_TODEVICE); | |
5919 | } | |
5920 | ||
5921 | dev_kfree_skb(skb); | |
5922 | return NETDEV_TX_OK; | |
5923 | } | |
5924 | ||
5925 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, | |
5926 | int new_mtu) | |
5927 | { | |
5928 | dev->mtu = new_mtu; | |
5929 | ||
5930 | if (new_mtu > ETH_DATA_LEN) { | |
5931 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
5932 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; | |
5933 | ethtool_op_set_tso(dev, 0); | |
5934 | } | |
5935 | else | |
5936 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; | |
5937 | } else { | |
5938 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
5939 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; | |
5940 | tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE; | |
5941 | } | |
5942 | } | |
5943 | ||
5944 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
5945 | { | |
5946 | struct tg3 *tp = netdev_priv(dev); | |
5947 | int err; | |
5948 | ||
5949 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
5950 | return -EINVAL; | |
5951 | ||
5952 | if (!netif_running(dev)) { | |
5953 | /* We'll just catch it later when the | |
5954 | * device is up'd. | |
5955 | */ | |
5956 | tg3_set_mtu(dev, tp, new_mtu); | |
5957 | return 0; | |
5958 | } | |
5959 | ||
5960 | tg3_phy_stop(tp); | |
5961 | ||
5962 | tg3_netif_stop(tp); | |
5963 | ||
5964 | tg3_full_lock(tp, 1); | |
5965 | ||
5966 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
5967 | ||
5968 | tg3_set_mtu(dev, tp, new_mtu); | |
5969 | ||
5970 | err = tg3_restart_hw(tp, 0); | |
5971 | ||
5972 | if (!err) | |
5973 | tg3_netif_start(tp); | |
5974 | ||
5975 | tg3_full_unlock(tp); | |
5976 | ||
5977 | if (!err) | |
5978 | tg3_phy_start(tp); | |
5979 | ||
5980 | return err; | |
5981 | } | |
5982 | ||
5983 | static void tg3_rx_prodring_free(struct tg3 *tp, | |
5984 | struct tg3_rx_prodring_set *tpr) | |
5985 | { | |
5986 | int i; | |
5987 | ||
5988 | if (tpr != &tp->prodring[0]) { | |
5989 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; | |
5990 | i = (i + 1) % TG3_RX_RING_SIZE) | |
5991 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], | |
5992 | tp->rx_pkt_map_sz); | |
5993 | ||
5994 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
5995 | for (i = tpr->rx_jmb_cons_idx; | |
5996 | i != tpr->rx_jmb_prod_idx; | |
5997 | i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) { | |
5998 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], | |
5999 | TG3_RX_JMB_MAP_SZ); | |
6000 | } | |
6001 | } | |
6002 | ||
6003 | return; | |
6004 | } | |
6005 | ||
6006 | for (i = 0; i < TG3_RX_RING_SIZE; i++) | |
6007 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], | |
6008 | tp->rx_pkt_map_sz); | |
6009 | ||
6010 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
6011 | for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) | |
6012 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], | |
6013 | TG3_RX_JMB_MAP_SZ); | |
6014 | } | |
6015 | } | |
6016 | ||
6017 | /* Initialize tx/rx rings for packet processing. | |
6018 | * | |
6019 | * The chip has been shut down and the driver detached from | |
6020 | * the networking, so no interrupts or new tx packets will | |
6021 | * end up in the driver. tp->{tx,}lock are held and thus | |
6022 | * we may not sleep. | |
6023 | */ | |
6024 | static int tg3_rx_prodring_alloc(struct tg3 *tp, | |
6025 | struct tg3_rx_prodring_set *tpr) | |
6026 | { | |
6027 | u32 i, rx_pkt_dma_sz; | |
6028 | ||
6029 | tpr->rx_std_cons_idx = 0; | |
6030 | tpr->rx_std_prod_idx = 0; | |
6031 | tpr->rx_jmb_cons_idx = 0; | |
6032 | tpr->rx_jmb_prod_idx = 0; | |
6033 | ||
6034 | if (tpr != &tp->prodring[0]) { | |
6035 | memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE); | |
6036 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) | |
6037 | memset(&tpr->rx_jmb_buffers[0], 0, | |
6038 | TG3_RX_JMB_BUFF_RING_SIZE); | |
6039 | goto done; | |
6040 | } | |
6041 | ||
6042 | /* Zero out all descriptors. */ | |
6043 | memset(tpr->rx_std, 0, TG3_RX_RING_BYTES); | |
6044 | ||
6045 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; | |
6046 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && | |
6047 | tp->dev->mtu > ETH_DATA_LEN) | |
6048 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
6049 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
6050 | ||
6051 | /* Initialize invariants of the rings, we only set this | |
6052 | * stuff once. This works because the card does not | |
6053 | * write into the rx buffer posting rings. | |
6054 | */ | |
6055 | for (i = 0; i < TG3_RX_RING_SIZE; i++) { | |
6056 | struct tg3_rx_buffer_desc *rxd; | |
6057 | ||
6058 | rxd = &tpr->rx_std[i]; | |
6059 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; | |
6060 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); | |
6061 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
6062 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6063 | } | |
6064 | ||
6065 | /* Now allocate fresh SKBs for each rx ring. */ | |
6066 | for (i = 0; i < tp->rx_pending; i++) { | |
6067 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { | |
6068 | printk(KERN_WARNING PFX | |
6069 | "%s: Using a smaller RX standard ring, " | |
6070 | "only %d out of %d buffers were allocated " | |
6071 | "successfully.\n", | |
6072 | tp->dev->name, i, tp->rx_pending); | |
6073 | if (i == 0) | |
6074 | goto initfail; | |
6075 | tp->rx_pending = i; | |
6076 | break; | |
6077 | } | |
6078 | } | |
6079 | ||
6080 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)) | |
6081 | goto done; | |
6082 | ||
6083 | memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES); | |
6084 | ||
6085 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { | |
6086 | for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { | |
6087 | struct tg3_rx_buffer_desc *rxd; | |
6088 | ||
6089 | rxd = &tpr->rx_jmb[i].std; | |
6090 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
6091 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
6092 | RXD_FLAG_JUMBO; | |
6093 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
6094 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6095 | } | |
6096 | ||
6097 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
6098 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, | |
6099 | i) < 0) { | |
6100 | printk(KERN_WARNING PFX | |
6101 | "%s: Using a smaller RX jumbo ring, " | |
6102 | "only %d out of %d buffers were " | |
6103 | "allocated successfully.\n", | |
6104 | tp->dev->name, i, tp->rx_jumbo_pending); | |
6105 | if (i == 0) | |
6106 | goto initfail; | |
6107 | tp->rx_jumbo_pending = i; | |
6108 | break; | |
6109 | } | |
6110 | } | |
6111 | } | |
6112 | ||
6113 | done: | |
6114 | return 0; | |
6115 | ||
6116 | initfail: | |
6117 | tg3_rx_prodring_free(tp, tpr); | |
6118 | return -ENOMEM; | |
6119 | } | |
6120 | ||
6121 | static void tg3_rx_prodring_fini(struct tg3 *tp, | |
6122 | struct tg3_rx_prodring_set *tpr) | |
6123 | { | |
6124 | kfree(tpr->rx_std_buffers); | |
6125 | tpr->rx_std_buffers = NULL; | |
6126 | kfree(tpr->rx_jmb_buffers); | |
6127 | tpr->rx_jmb_buffers = NULL; | |
6128 | if (tpr->rx_std) { | |
6129 | pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES, | |
6130 | tpr->rx_std, tpr->rx_std_mapping); | |
6131 | tpr->rx_std = NULL; | |
6132 | } | |
6133 | if (tpr->rx_jmb) { | |
6134 | pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES, | |
6135 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
6136 | tpr->rx_jmb = NULL; | |
6137 | } | |
6138 | } | |
6139 | ||
6140 | static int tg3_rx_prodring_init(struct tg3 *tp, | |
6141 | struct tg3_rx_prodring_set *tpr) | |
6142 | { | |
6143 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL); | |
6144 | if (!tpr->rx_std_buffers) | |
6145 | return -ENOMEM; | |
6146 | ||
6147 | tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES, | |
6148 | &tpr->rx_std_mapping); | |
6149 | if (!tpr->rx_std) | |
6150 | goto err_out; | |
6151 | ||
6152 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
6153 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE, | |
6154 | GFP_KERNEL); | |
6155 | if (!tpr->rx_jmb_buffers) | |
6156 | goto err_out; | |
6157 | ||
6158 | tpr->rx_jmb = pci_alloc_consistent(tp->pdev, | |
6159 | TG3_RX_JUMBO_RING_BYTES, | |
6160 | &tpr->rx_jmb_mapping); | |
6161 | if (!tpr->rx_jmb) | |
6162 | goto err_out; | |
6163 | } | |
6164 | ||
6165 | return 0; | |
6166 | ||
6167 | err_out: | |
6168 | tg3_rx_prodring_fini(tp, tpr); | |
6169 | return -ENOMEM; | |
6170 | } | |
6171 | ||
6172 | /* Free up pending packets in all rx/tx rings. | |
6173 | * | |
6174 | * The chip has been shut down and the driver detached from | |
6175 | * the networking, so no interrupts or new tx packets will | |
6176 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
6177 | * in an interrupt context and thus may sleep. | |
6178 | */ | |
6179 | static void tg3_free_rings(struct tg3 *tp) | |
6180 | { | |
6181 | int i, j; | |
6182 | ||
6183 | for (j = 0; j < tp->irq_cnt; j++) { | |
6184 | struct tg3_napi *tnapi = &tp->napi[j]; | |
6185 | ||
6186 | if (!tnapi->tx_buffers) | |
6187 | continue; | |
6188 | ||
6189 | for (i = 0; i < TG3_TX_RING_SIZE; ) { | |
6190 | struct ring_info *txp; | |
6191 | struct sk_buff *skb; | |
6192 | unsigned int k; | |
6193 | ||
6194 | txp = &tnapi->tx_buffers[i]; | |
6195 | skb = txp->skb; | |
6196 | ||
6197 | if (skb == NULL) { | |
6198 | i++; | |
6199 | continue; | |
6200 | } | |
6201 | ||
6202 | pci_unmap_single(tp->pdev, | |
6203 | pci_unmap_addr(txp, mapping), | |
6204 | skb_headlen(skb), | |
6205 | PCI_DMA_TODEVICE); | |
6206 | txp->skb = NULL; | |
6207 | ||
6208 | i++; | |
6209 | ||
6210 | for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) { | |
6211 | txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)]; | |
6212 | pci_unmap_page(tp->pdev, | |
6213 | pci_unmap_addr(txp, mapping), | |
6214 | skb_shinfo(skb)->frags[k].size, | |
6215 | PCI_DMA_TODEVICE); | |
6216 | i++; | |
6217 | } | |
6218 | ||
6219 | dev_kfree_skb_any(skb); | |
6220 | } | |
6221 | ||
6222 | tg3_rx_prodring_free(tp, &tp->prodring[j]); | |
6223 | } | |
6224 | } | |
6225 | ||
6226 | /* Initialize tx/rx rings for packet processing. | |
6227 | * | |
6228 | * The chip has been shut down and the driver detached from | |
6229 | * the networking, so no interrupts or new tx packets will | |
6230 | * end up in the driver. tp->{tx,}lock are held and thus | |
6231 | * we may not sleep. | |
6232 | */ | |
6233 | static int tg3_init_rings(struct tg3 *tp) | |
6234 | { | |
6235 | int i; | |
6236 | ||
6237 | /* Free up all the SKBs. */ | |
6238 | tg3_free_rings(tp); | |
6239 | ||
6240 | for (i = 0; i < tp->irq_cnt; i++) { | |
6241 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6242 | ||
6243 | tnapi->last_tag = 0; | |
6244 | tnapi->last_irq_tag = 0; | |
6245 | tnapi->hw_status->status = 0; | |
6246 | tnapi->hw_status->status_tag = 0; | |
6247 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6248 | ||
6249 | tnapi->tx_prod = 0; | |
6250 | tnapi->tx_cons = 0; | |
6251 | if (tnapi->tx_ring) | |
6252 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
6253 | ||
6254 | tnapi->rx_rcb_ptr = 0; | |
6255 | if (tnapi->rx_rcb) | |
6256 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
6257 | ||
6258 | if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) { | |
6259 | tg3_free_rings(tp); | |
6260 | return -ENOMEM; | |
6261 | } | |
6262 | } | |
6263 | ||
6264 | return 0; | |
6265 | } | |
6266 | ||
6267 | /* | |
6268 | * Must not be invoked with interrupt sources disabled and | |
6269 | * the hardware shutdown down. | |
6270 | */ | |
6271 | static void tg3_free_consistent(struct tg3 *tp) | |
6272 | { | |
6273 | int i; | |
6274 | ||
6275 | for (i = 0; i < tp->irq_cnt; i++) { | |
6276 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6277 | ||
6278 | if (tnapi->tx_ring) { | |
6279 | pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES, | |
6280 | tnapi->tx_ring, tnapi->tx_desc_mapping); | |
6281 | tnapi->tx_ring = NULL; | |
6282 | } | |
6283 | ||
6284 | kfree(tnapi->tx_buffers); | |
6285 | tnapi->tx_buffers = NULL; | |
6286 | ||
6287 | if (tnapi->rx_rcb) { | |
6288 | pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp), | |
6289 | tnapi->rx_rcb, | |
6290 | tnapi->rx_rcb_mapping); | |
6291 | tnapi->rx_rcb = NULL; | |
6292 | } | |
6293 | ||
6294 | if (tnapi->hw_status) { | |
6295 | pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE, | |
6296 | tnapi->hw_status, | |
6297 | tnapi->status_mapping); | |
6298 | tnapi->hw_status = NULL; | |
6299 | } | |
6300 | } | |
6301 | ||
6302 | if (tp->hw_stats) { | |
6303 | pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats), | |
6304 | tp->hw_stats, tp->stats_mapping); | |
6305 | tp->hw_stats = NULL; | |
6306 | } | |
6307 | ||
6308 | for (i = 0; i < tp->irq_cnt; i++) | |
6309 | tg3_rx_prodring_fini(tp, &tp->prodring[i]); | |
6310 | } | |
6311 | ||
6312 | /* | |
6313 | * Must not be invoked with interrupt sources disabled and | |
6314 | * the hardware shutdown down. Can sleep. | |
6315 | */ | |
6316 | static int tg3_alloc_consistent(struct tg3 *tp) | |
6317 | { | |
6318 | int i; | |
6319 | ||
6320 | for (i = 0; i < tp->irq_cnt; i++) { | |
6321 | if (tg3_rx_prodring_init(tp, &tp->prodring[i])) | |
6322 | goto err_out; | |
6323 | } | |
6324 | ||
6325 | tp->hw_stats = pci_alloc_consistent(tp->pdev, | |
6326 | sizeof(struct tg3_hw_stats), | |
6327 | &tp->stats_mapping); | |
6328 | if (!tp->hw_stats) | |
6329 | goto err_out; | |
6330 | ||
6331 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6332 | ||
6333 | for (i = 0; i < tp->irq_cnt; i++) { | |
6334 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6335 | struct tg3_hw_status *sblk; | |
6336 | ||
6337 | tnapi->hw_status = pci_alloc_consistent(tp->pdev, | |
6338 | TG3_HW_STATUS_SIZE, | |
6339 | &tnapi->status_mapping); | |
6340 | if (!tnapi->hw_status) | |
6341 | goto err_out; | |
6342 | ||
6343 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6344 | sblk = tnapi->hw_status; | |
6345 | ||
6346 | /* If multivector TSS is enabled, vector 0 does not handle | |
6347 | * tx interrupts. Don't allocate any resources for it. | |
6348 | */ | |
6349 | if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) || | |
6350 | (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) { | |
6351 | tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) * | |
6352 | TG3_TX_RING_SIZE, | |
6353 | GFP_KERNEL); | |
6354 | if (!tnapi->tx_buffers) | |
6355 | goto err_out; | |
6356 | ||
6357 | tnapi->tx_ring = pci_alloc_consistent(tp->pdev, | |
6358 | TG3_TX_RING_BYTES, | |
6359 | &tnapi->tx_desc_mapping); | |
6360 | if (!tnapi->tx_ring) | |
6361 | goto err_out; | |
6362 | } | |
6363 | ||
6364 | /* | |
6365 | * When RSS is enabled, the status block format changes | |
6366 | * slightly. The "rx_jumbo_consumer", "reserved", | |
6367 | * and "rx_mini_consumer" members get mapped to the | |
6368 | * other three rx return ring producer indexes. | |
6369 | */ | |
6370 | switch (i) { | |
6371 | default: | |
6372 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
6373 | break; | |
6374 | case 2: | |
6375 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6376 | break; | |
6377 | case 3: | |
6378 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6379 | break; | |
6380 | case 4: | |
6381 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6382 | break; | |
6383 | } | |
6384 | ||
6385 | tnapi->prodring = &tp->prodring[i]; | |
6386 | ||
6387 | /* | |
6388 | * If multivector RSS is enabled, vector 0 does not handle | |
6389 | * rx or tx interrupts. Don't allocate any resources for it. | |
6390 | */ | |
6391 | if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) | |
6392 | continue; | |
6393 | ||
6394 | tnapi->rx_rcb = pci_alloc_consistent(tp->pdev, | |
6395 | TG3_RX_RCB_RING_BYTES(tp), | |
6396 | &tnapi->rx_rcb_mapping); | |
6397 | if (!tnapi->rx_rcb) | |
6398 | goto err_out; | |
6399 | ||
6400 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
6401 | } | |
6402 | ||
6403 | return 0; | |
6404 | ||
6405 | err_out: | |
6406 | tg3_free_consistent(tp); | |
6407 | return -ENOMEM; | |
6408 | } | |
6409 | ||
6410 | #define MAX_WAIT_CNT 1000 | |
6411 | ||
6412 | /* To stop a block, clear the enable bit and poll till it | |
6413 | * clears. tp->lock is held. | |
6414 | */ | |
6415 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) | |
6416 | { | |
6417 | unsigned int i; | |
6418 | u32 val; | |
6419 | ||
6420 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
6421 | switch (ofs) { | |
6422 | case RCVLSC_MODE: | |
6423 | case DMAC_MODE: | |
6424 | case MBFREE_MODE: | |
6425 | case BUFMGR_MODE: | |
6426 | case MEMARB_MODE: | |
6427 | /* We can't enable/disable these bits of the | |
6428 | * 5705/5750, just say success. | |
6429 | */ | |
6430 | return 0; | |
6431 | ||
6432 | default: | |
6433 | break; | |
6434 | } | |
6435 | } | |
6436 | ||
6437 | val = tr32(ofs); | |
6438 | val &= ~enable_bit; | |
6439 | tw32_f(ofs, val); | |
6440 | ||
6441 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6442 | udelay(100); | |
6443 | val = tr32(ofs); | |
6444 | if ((val & enable_bit) == 0) | |
6445 | break; | |
6446 | } | |
6447 | ||
6448 | if (i == MAX_WAIT_CNT && !silent) { | |
6449 | printk(KERN_ERR PFX "tg3_stop_block timed out, " | |
6450 | "ofs=%lx enable_bit=%x\n", | |
6451 | ofs, enable_bit); | |
6452 | return -ENODEV; | |
6453 | } | |
6454 | ||
6455 | return 0; | |
6456 | } | |
6457 | ||
6458 | /* tp->lock is held. */ | |
6459 | static int tg3_abort_hw(struct tg3 *tp, int silent) | |
6460 | { | |
6461 | int i, err; | |
6462 | ||
6463 | tg3_disable_ints(tp); | |
6464 | ||
6465 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6466 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6467 | udelay(10); | |
6468 | ||
6469 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); | |
6470 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6471 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6472 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6473 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6474 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6475 | ||
6476 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6477 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6478 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6479 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6480 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6481 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6482 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
6483 | ||
6484 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6485 | tw32_f(MAC_MODE, tp->mac_mode); | |
6486 | udelay(40); | |
6487 | ||
6488 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6489 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6490 | ||
6491 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6492 | udelay(100); | |
6493 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6494 | break; | |
6495 | } | |
6496 | if (i >= MAX_WAIT_CNT) { | |
6497 | printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, " | |
6498 | "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n", | |
6499 | tp->dev->name, tr32(MAC_TX_MODE)); | |
6500 | err |= -ENODEV; | |
6501 | } | |
6502 | ||
6503 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); | |
6504 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); | |
6505 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
6506 | ||
6507 | tw32(FTQ_RESET, 0xffffffff); | |
6508 | tw32(FTQ_RESET, 0x00000000); | |
6509 | ||
6510 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); | |
6511 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
6512 | ||
6513 | for (i = 0; i < tp->irq_cnt; i++) { | |
6514 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6515 | if (tnapi->hw_status) | |
6516 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6517 | } | |
6518 | if (tp->hw_stats) | |
6519 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6520 | ||
6521 | return err; | |
6522 | } | |
6523 | ||
6524 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) | |
6525 | { | |
6526 | int i; | |
6527 | u32 apedata; | |
6528 | ||
6529 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
6530 | if (apedata != APE_SEG_SIG_MAGIC) | |
6531 | return; | |
6532 | ||
6533 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
6534 | if (!(apedata & APE_FW_STATUS_READY)) | |
6535 | return; | |
6536 | ||
6537 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
6538 | for (i = 0; i < 10; i++) { | |
6539 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
6540 | return; | |
6541 | ||
6542 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
6543 | ||
6544 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6545 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
6546 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
6547 | ||
6548 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
6549 | ||
6550 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6551 | break; | |
6552 | ||
6553 | udelay(100); | |
6554 | } | |
6555 | ||
6556 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6557 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
6558 | } | |
6559 | ||
6560 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6561 | { | |
6562 | u32 event; | |
6563 | u32 apedata; | |
6564 | ||
6565 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
6566 | return; | |
6567 | ||
6568 | switch (kind) { | |
6569 | case RESET_KIND_INIT: | |
6570 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6571 | APE_HOST_SEG_SIG_MAGIC); | |
6572 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6573 | APE_HOST_SEG_LEN_MAGIC); | |
6574 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6575 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6576 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6577 | APE_HOST_DRIVER_ID_MAGIC); | |
6578 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
6579 | APE_HOST_BEHAV_NO_PHYLOCK); | |
6580 | ||
6581 | event = APE_EVENT_STATUS_STATE_START; | |
6582 | break; | |
6583 | case RESET_KIND_SHUTDOWN: | |
6584 | /* With the interface we are currently using, | |
6585 | * APE does not track driver state. Wiping | |
6586 | * out the HOST SEGMENT SIGNATURE forces | |
6587 | * the APE to assume OS absent status. | |
6588 | */ | |
6589 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
6590 | ||
6591 | event = APE_EVENT_STATUS_STATE_UNLOAD; | |
6592 | break; | |
6593 | case RESET_KIND_SUSPEND: | |
6594 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
6595 | break; | |
6596 | default: | |
6597 | return; | |
6598 | } | |
6599 | ||
6600 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
6601 | ||
6602 | tg3_ape_send_event(tp, event); | |
6603 | } | |
6604 | ||
6605 | /* tp->lock is held. */ | |
6606 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
6607 | { | |
6608 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, | |
6609 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
6610 | ||
6611 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6612 | switch (kind) { | |
6613 | case RESET_KIND_INIT: | |
6614 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6615 | DRV_STATE_START); | |
6616 | break; | |
6617 | ||
6618 | case RESET_KIND_SHUTDOWN: | |
6619 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6620 | DRV_STATE_UNLOAD); | |
6621 | break; | |
6622 | ||
6623 | case RESET_KIND_SUSPEND: | |
6624 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6625 | DRV_STATE_SUSPEND); | |
6626 | break; | |
6627 | ||
6628 | default: | |
6629 | break; | |
6630 | } | |
6631 | } | |
6632 | ||
6633 | if (kind == RESET_KIND_INIT || | |
6634 | kind == RESET_KIND_SUSPEND) | |
6635 | tg3_ape_driver_state_change(tp, kind); | |
6636 | } | |
6637 | ||
6638 | /* tp->lock is held. */ | |
6639 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
6640 | { | |
6641 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6642 | switch (kind) { | |
6643 | case RESET_KIND_INIT: | |
6644 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6645 | DRV_STATE_START_DONE); | |
6646 | break; | |
6647 | ||
6648 | case RESET_KIND_SHUTDOWN: | |
6649 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6650 | DRV_STATE_UNLOAD_DONE); | |
6651 | break; | |
6652 | ||
6653 | default: | |
6654 | break; | |
6655 | } | |
6656 | } | |
6657 | ||
6658 | if (kind == RESET_KIND_SHUTDOWN) | |
6659 | tg3_ape_driver_state_change(tp, kind); | |
6660 | } | |
6661 | ||
6662 | /* tp->lock is held. */ | |
6663 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
6664 | { | |
6665 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
6666 | switch (kind) { | |
6667 | case RESET_KIND_INIT: | |
6668 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6669 | DRV_STATE_START); | |
6670 | break; | |
6671 | ||
6672 | case RESET_KIND_SHUTDOWN: | |
6673 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6674 | DRV_STATE_UNLOAD); | |
6675 | break; | |
6676 | ||
6677 | case RESET_KIND_SUSPEND: | |
6678 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6679 | DRV_STATE_SUSPEND); | |
6680 | break; | |
6681 | ||
6682 | default: | |
6683 | break; | |
6684 | } | |
6685 | } | |
6686 | } | |
6687 | ||
6688 | static int tg3_poll_fw(struct tg3 *tp) | |
6689 | { | |
6690 | int i; | |
6691 | u32 val; | |
6692 | ||
6693 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
6694 | /* Wait up to 20ms for init done. */ | |
6695 | for (i = 0; i < 200; i++) { | |
6696 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) | |
6697 | return 0; | |
6698 | udelay(100); | |
6699 | } | |
6700 | return -ENODEV; | |
6701 | } | |
6702 | ||
6703 | /* Wait for firmware initialization to complete. */ | |
6704 | for (i = 0; i < 100000; i++) { | |
6705 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
6706 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
6707 | break; | |
6708 | udelay(10); | |
6709 | } | |
6710 | ||
6711 | /* Chip might not be fitted with firmware. Some Sun onboard | |
6712 | * parts are configured like that. So don't signal the timeout | |
6713 | * of the above loop as an error, but do report the lack of | |
6714 | * running firmware once. | |
6715 | */ | |
6716 | if (i >= 100000 && | |
6717 | !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) { | |
6718 | tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED; | |
6719 | ||
6720 | printk(KERN_INFO PFX "%s: No firmware running.\n", | |
6721 | tp->dev->name); | |
6722 | } | |
6723 | ||
6724 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
6725 | /* The 57765 A0 needs a little more | |
6726 | * time to do some important work. | |
6727 | */ | |
6728 | mdelay(10); | |
6729 | } | |
6730 | ||
6731 | return 0; | |
6732 | } | |
6733 | ||
6734 | /* Save PCI command register before chip reset */ | |
6735 | static void tg3_save_pci_state(struct tg3 *tp) | |
6736 | { | |
6737 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); | |
6738 | } | |
6739 | ||
6740 | /* Restore PCI state after chip reset */ | |
6741 | static void tg3_restore_pci_state(struct tg3 *tp) | |
6742 | { | |
6743 | u32 val; | |
6744 | ||
6745 | /* Re-enable indirect register accesses. */ | |
6746 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
6747 | tp->misc_host_ctrl); | |
6748 | ||
6749 | /* Set MAX PCI retry to zero. */ | |
6750 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
6751 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
6752 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) | |
6753 | val |= PCISTATE_RETRY_SAME_DMA; | |
6754 | /* Allow reads and writes to the APE register and memory space. */ | |
6755 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
6756 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
6757 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
6758 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); | |
6759 | ||
6760 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); | |
6761 | ||
6762 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { | |
6763 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
6764 | pcie_set_readrq(tp->pdev, 4096); | |
6765 | else { | |
6766 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
6767 | tp->pci_cacheline_sz); | |
6768 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
6769 | tp->pci_lat_timer); | |
6770 | } | |
6771 | } | |
6772 | ||
6773 | /* Make sure PCI-X relaxed ordering bit is clear. */ | |
6774 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
6775 | u16 pcix_cmd; | |
6776 | ||
6777 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
6778 | &pcix_cmd); | |
6779 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
6780 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
6781 | pcix_cmd); | |
6782 | } | |
6783 | ||
6784 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
6785 | ||
6786 | /* Chip reset on 5780 will reset MSI enable bit, | |
6787 | * so need to restore it. | |
6788 | */ | |
6789 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
6790 | u16 ctrl; | |
6791 | ||
6792 | pci_read_config_word(tp->pdev, | |
6793 | tp->msi_cap + PCI_MSI_FLAGS, | |
6794 | &ctrl); | |
6795 | pci_write_config_word(tp->pdev, | |
6796 | tp->msi_cap + PCI_MSI_FLAGS, | |
6797 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
6798 | val = tr32(MSGINT_MODE); | |
6799 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
6800 | } | |
6801 | } | |
6802 | } | |
6803 | ||
6804 | static void tg3_stop_fw(struct tg3 *); | |
6805 | ||
6806 | /* tp->lock is held. */ | |
6807 | static int tg3_chip_reset(struct tg3 *tp) | |
6808 | { | |
6809 | u32 val; | |
6810 | void (*write_op)(struct tg3 *, u32, u32); | |
6811 | int i, err; | |
6812 | ||
6813 | tg3_nvram_lock(tp); | |
6814 | ||
6815 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); | |
6816 | ||
6817 | /* No matching tg3_nvram_unlock() after this because | |
6818 | * chip reset below will undo the nvram lock. | |
6819 | */ | |
6820 | tp->nvram_lock_cnt = 0; | |
6821 | ||
6822 | /* GRC_MISC_CFG core clock reset will clear the memory | |
6823 | * enable bit in PCI register 4 and the MSI enable bit | |
6824 | * on some chips, so we save relevant registers here. | |
6825 | */ | |
6826 | tg3_save_pci_state(tp); | |
6827 | ||
6828 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
6829 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) | |
6830 | tw32(GRC_FASTBOOT_PC, 0); | |
6831 | ||
6832 | /* | |
6833 | * We must avoid the readl() that normally takes place. | |
6834 | * It locks machines, causes machine checks, and other | |
6835 | * fun things. So, temporarily disable the 5701 | |
6836 | * hardware workaround, while we do the reset. | |
6837 | */ | |
6838 | write_op = tp->write32; | |
6839 | if (write_op == tg3_write_flush_reg32) | |
6840 | tp->write32 = tg3_write32; | |
6841 | ||
6842 | /* Prevent the irq handler from reading or writing PCI registers | |
6843 | * during chip reset when the memory enable bit in the PCI command | |
6844 | * register may be cleared. The chip does not generate interrupt | |
6845 | * at this time, but the irq handler may still be called due to irq | |
6846 | * sharing or irqpoll. | |
6847 | */ | |
6848 | tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; | |
6849 | for (i = 0; i < tp->irq_cnt; i++) { | |
6850 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6851 | if (tnapi->hw_status) { | |
6852 | tnapi->hw_status->status = 0; | |
6853 | tnapi->hw_status->status_tag = 0; | |
6854 | } | |
6855 | tnapi->last_tag = 0; | |
6856 | tnapi->last_irq_tag = 0; | |
6857 | } | |
6858 | smp_mb(); | |
6859 | ||
6860 | for (i = 0; i < tp->irq_cnt; i++) | |
6861 | synchronize_irq(tp->napi[i].irq_vec); | |
6862 | ||
6863 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
6864 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
6865 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
6866 | } | |
6867 | ||
6868 | /* do the reset */ | |
6869 | val = GRC_MISC_CFG_CORECLK_RESET; | |
6870 | ||
6871 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
6872 | if (tr32(0x7e2c) == 0x60) { | |
6873 | tw32(0x7e2c, 0x20); | |
6874 | } | |
6875 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { | |
6876 | tw32(GRC_MISC_CFG, (1 << 29)); | |
6877 | val |= (1 << 29); | |
6878 | } | |
6879 | } | |
6880 | ||
6881 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
6882 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
6883 | tw32(GRC_VCPU_EXT_CTRL, | |
6884 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
6885 | } | |
6886 | ||
6887 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
6888 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; | |
6889 | tw32(GRC_MISC_CFG, val); | |
6890 | ||
6891 | /* restore 5701 hardware bug workaround write method */ | |
6892 | tp->write32 = write_op; | |
6893 | ||
6894 | /* Unfortunately, we have to delay before the PCI read back. | |
6895 | * Some 575X chips even will not respond to a PCI cfg access | |
6896 | * when the reset command is given to the chip. | |
6897 | * | |
6898 | * How do these hardware designers expect things to work | |
6899 | * properly if the PCI write is posted for a long period | |
6900 | * of time? It is always necessary to have some method by | |
6901 | * which a register read back can occur to push the write | |
6902 | * out which does the reset. | |
6903 | * | |
6904 | * For most tg3 variants the trick below was working. | |
6905 | * Ho hum... | |
6906 | */ | |
6907 | udelay(120); | |
6908 | ||
6909 | /* Flush PCI posted writes. The normal MMIO registers | |
6910 | * are inaccessible at this time so this is the only | |
6911 | * way to make this reliably (actually, this is no longer | |
6912 | * the case, see above). I tried to use indirect | |
6913 | * register read/write but this upset some 5701 variants. | |
6914 | */ | |
6915 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
6916 | ||
6917 | udelay(120); | |
6918 | ||
6919 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { | |
6920 | u16 val16; | |
6921 | ||
6922 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { | |
6923 | int i; | |
6924 | u32 cfg_val; | |
6925 | ||
6926 | /* Wait for link training to complete. */ | |
6927 | for (i = 0; i < 5000; i++) | |
6928 | udelay(100); | |
6929 | ||
6930 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
6931 | pci_write_config_dword(tp->pdev, 0xc4, | |
6932 | cfg_val | (1 << 15)); | |
6933 | } | |
6934 | ||
6935 | /* Clear the "no snoop" and "relaxed ordering" bits. */ | |
6936 | pci_read_config_word(tp->pdev, | |
6937 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
6938 | &val16); | |
6939 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
6940 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
6941 | /* | |
6942 | * Older PCIe devices only support the 128 byte | |
6943 | * MPS setting. Enforce the restriction. | |
6944 | */ | |
6945 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || | |
6946 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)) | |
6947 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; | |
6948 | pci_write_config_word(tp->pdev, | |
6949 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
6950 | val16); | |
6951 | ||
6952 | pcie_set_readrq(tp->pdev, 4096); | |
6953 | ||
6954 | /* Clear error status */ | |
6955 | pci_write_config_word(tp->pdev, | |
6956 | tp->pcie_cap + PCI_EXP_DEVSTA, | |
6957 | PCI_EXP_DEVSTA_CED | | |
6958 | PCI_EXP_DEVSTA_NFED | | |
6959 | PCI_EXP_DEVSTA_FED | | |
6960 | PCI_EXP_DEVSTA_URD); | |
6961 | } | |
6962 | ||
6963 | tg3_restore_pci_state(tp); | |
6964 | ||
6965 | tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING; | |
6966 | ||
6967 | val = 0; | |
6968 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
6969 | val = tr32(MEMARB_MODE); | |
6970 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
6971 | ||
6972 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
6973 | tg3_stop_fw(tp); | |
6974 | tw32(0x5000, 0x400); | |
6975 | } | |
6976 | ||
6977 | tw32(GRC_MODE, tp->grc_mode); | |
6978 | ||
6979 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
6980 | val = tr32(0xc4); | |
6981 | ||
6982 | tw32(0xc4, val | (1 << 15)); | |
6983 | } | |
6984 | ||
6985 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
6986 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
6987 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
6988 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
6989 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
6990 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
6991 | } | |
6992 | ||
6993 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
6994 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; | |
6995 | tw32_f(MAC_MODE, tp->mac_mode); | |
6996 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
6997 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; | |
6998 | tw32_f(MAC_MODE, tp->mac_mode); | |
6999 | } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { | |
7000 | tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); | |
7001 | if (tp->mac_mode & MAC_MODE_APE_TX_EN) | |
7002 | tp->mac_mode |= MAC_MODE_TDE_ENABLE; | |
7003 | tw32_f(MAC_MODE, tp->mac_mode); | |
7004 | } else | |
7005 | tw32_f(MAC_MODE, 0); | |
7006 | udelay(40); | |
7007 | ||
7008 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); | |
7009 | ||
7010 | err = tg3_poll_fw(tp); | |
7011 | if (err) | |
7012 | return err; | |
7013 | ||
7014 | tg3_mdio_start(tp); | |
7015 | ||
7016 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
7017 | u8 phy_addr; | |
7018 | ||
7019 | phy_addr = tp->phy_addr; | |
7020 | tp->phy_addr = TG3_PHY_PCIE_ADDR; | |
7021 | ||
7022 | tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR, | |
7023 | TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT); | |
7024 | val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL | | |
7025 | TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL | | |
7026 | TG3_PCIEPHY_TX0CTRL1_NB_EN; | |
7027 | tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val); | |
7028 | udelay(10); | |
7029 | ||
7030 | tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR, | |
7031 | TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT); | |
7032 | val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN | | |
7033 | TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN; | |
7034 | tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val); | |
7035 | udelay(10); | |
7036 | ||
7037 | tp->phy_addr = phy_addr; | |
7038 | } | |
7039 | ||
7040 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
7041 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
7042 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
7043 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
7044 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) { | |
7045 | val = tr32(0x7c00); | |
7046 | ||
7047 | tw32(0x7c00, val | (1 << 25)); | |
7048 | } | |
7049 | ||
7050 | /* Reprobe ASF enable state. */ | |
7051 | tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF; | |
7052 | tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE; | |
7053 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
7054 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7055 | u32 nic_cfg; | |
7056 | ||
7057 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7058 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
7059 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
7060 | tp->last_event_jiffies = jiffies; | |
7061 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) | |
7062 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; | |
7063 | } | |
7064 | } | |
7065 | ||
7066 | return 0; | |
7067 | } | |
7068 | ||
7069 | /* tp->lock is held. */ | |
7070 | static void tg3_stop_fw(struct tg3 *tp) | |
7071 | { | |
7072 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && | |
7073 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7074 | /* Wait for RX cpu to ACK the previous event. */ | |
7075 | tg3_wait_for_event_ack(tp); | |
7076 | ||
7077 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
7078 | ||
7079 | tg3_generate_fw_event(tp); | |
7080 | ||
7081 | /* Wait for RX cpu to ACK this event. */ | |
7082 | tg3_wait_for_event_ack(tp); | |
7083 | } | |
7084 | } | |
7085 | ||
7086 | /* tp->lock is held. */ | |
7087 | static int tg3_halt(struct tg3 *tp, int kind, int silent) | |
7088 | { | |
7089 | int err; | |
7090 | ||
7091 | tg3_stop_fw(tp); | |
7092 | ||
7093 | tg3_write_sig_pre_reset(tp, kind); | |
7094 | ||
7095 | tg3_abort_hw(tp, silent); | |
7096 | err = tg3_chip_reset(tp); | |
7097 | ||
7098 | __tg3_set_mac_addr(tp, 0); | |
7099 | ||
7100 | tg3_write_sig_legacy(tp, kind); | |
7101 | tg3_write_sig_post_reset(tp, kind); | |
7102 | ||
7103 | if (err) | |
7104 | return err; | |
7105 | ||
7106 | return 0; | |
7107 | } | |
7108 | ||
7109 | #define RX_CPU_SCRATCH_BASE 0x30000 | |
7110 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
7111 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
7112 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
7113 | ||
7114 | /* tp->lock is held. */ | |
7115 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
7116 | { | |
7117 | int i; | |
7118 | ||
7119 | BUG_ON(offset == TX_CPU_BASE && | |
7120 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)); | |
7121 | ||
7122 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
7123 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
7124 | ||
7125 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7126 | return 0; | |
7127 | } | |
7128 | if (offset == RX_CPU_BASE) { | |
7129 | for (i = 0; i < 10000; i++) { | |
7130 | tw32(offset + CPU_STATE, 0xffffffff); | |
7131 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7132 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7133 | break; | |
7134 | } | |
7135 | ||
7136 | tw32(offset + CPU_STATE, 0xffffffff); | |
7137 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
7138 | udelay(10); | |
7139 | } else { | |
7140 | for (i = 0; i < 10000; i++) { | |
7141 | tw32(offset + CPU_STATE, 0xffffffff); | |
7142 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7143 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7144 | break; | |
7145 | } | |
7146 | } | |
7147 | ||
7148 | if (i >= 10000) { | |
7149 | printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, " | |
7150 | "and %s CPU\n", | |
7151 | tp->dev->name, | |
7152 | (offset == RX_CPU_BASE ? "RX" : "TX")); | |
7153 | return -ENODEV; | |
7154 | } | |
7155 | ||
7156 | /* Clear firmware's nvram arbitration. */ | |
7157 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
7158 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
7159 | return 0; | |
7160 | } | |
7161 | ||
7162 | struct fw_info { | |
7163 | unsigned int fw_base; | |
7164 | unsigned int fw_len; | |
7165 | const __be32 *fw_data; | |
7166 | }; | |
7167 | ||
7168 | /* tp->lock is held. */ | |
7169 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
7170 | int cpu_scratch_size, struct fw_info *info) | |
7171 | { | |
7172 | int err, lock_err, i; | |
7173 | void (*write_op)(struct tg3 *, u32, u32); | |
7174 | ||
7175 | if (cpu_base == TX_CPU_BASE && | |
7176 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7177 | printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load " | |
7178 | "TX cpu firmware on %s which is 5705.\n", | |
7179 | tp->dev->name); | |
7180 | return -EINVAL; | |
7181 | } | |
7182 | ||
7183 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
7184 | write_op = tg3_write_mem; | |
7185 | else | |
7186 | write_op = tg3_write_indirect_reg32; | |
7187 | ||
7188 | /* It is possible that bootcode is still loading at this point. | |
7189 | * Get the nvram lock first before halting the cpu. | |
7190 | */ | |
7191 | lock_err = tg3_nvram_lock(tp); | |
7192 | err = tg3_halt_cpu(tp, cpu_base); | |
7193 | if (!lock_err) | |
7194 | tg3_nvram_unlock(tp); | |
7195 | if (err) | |
7196 | goto out; | |
7197 | ||
7198 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
7199 | write_op(tp, cpu_scratch_base + i, 0); | |
7200 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7201 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
7202 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) | |
7203 | write_op(tp, (cpu_scratch_base + | |
7204 | (info->fw_base & 0xffff) + | |
7205 | (i * sizeof(u32))), | |
7206 | be32_to_cpu(info->fw_data[i])); | |
7207 | ||
7208 | err = 0; | |
7209 | ||
7210 | out: | |
7211 | return err; | |
7212 | } | |
7213 | ||
7214 | /* tp->lock is held. */ | |
7215 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
7216 | { | |
7217 | struct fw_info info; | |
7218 | const __be32 *fw_data; | |
7219 | int err, i; | |
7220 | ||
7221 | fw_data = (void *)tp->fw->data; | |
7222 | ||
7223 | /* Firmware blob starts with version numbers, followed by | |
7224 | start address and length. We are setting complete length. | |
7225 | length = end_address_of_bss - start_address_of_text. | |
7226 | Remainder is the blob to be loaded contiguously | |
7227 | from start address. */ | |
7228 | ||
7229 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7230 | info.fw_len = tp->fw->size - 12; | |
7231 | info.fw_data = &fw_data[3]; | |
7232 | ||
7233 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
7234 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
7235 | &info); | |
7236 | if (err) | |
7237 | return err; | |
7238 | ||
7239 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
7240 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
7241 | &info); | |
7242 | if (err) | |
7243 | return err; | |
7244 | ||
7245 | /* Now startup only the RX cpu. */ | |
7246 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7247 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
7248 | ||
7249 | for (i = 0; i < 5; i++) { | |
7250 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) | |
7251 | break; | |
7252 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7253 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
7254 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
7255 | udelay(1000); | |
7256 | } | |
7257 | if (i >= 5) { | |
7258 | printk(KERN_ERR PFX "tg3_load_firmware fails for %s " | |
7259 | "to set RX CPU PC, is %08x should be %08x\n", | |
7260 | tp->dev->name, tr32(RX_CPU_BASE + CPU_PC), | |
7261 | info.fw_base); | |
7262 | return -ENODEV; | |
7263 | } | |
7264 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7265 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
7266 | ||
7267 | return 0; | |
7268 | } | |
7269 | ||
7270 | /* 5705 needs a special version of the TSO firmware. */ | |
7271 | ||
7272 | /* tp->lock is held. */ | |
7273 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
7274 | { | |
7275 | struct fw_info info; | |
7276 | const __be32 *fw_data; | |
7277 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; | |
7278 | int err, i; | |
7279 | ||
7280 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
7281 | return 0; | |
7282 | ||
7283 | fw_data = (void *)tp->fw->data; | |
7284 | ||
7285 | /* Firmware blob starts with version numbers, followed by | |
7286 | start address and length. We are setting complete length. | |
7287 | length = end_address_of_bss - start_address_of_text. | |
7288 | Remainder is the blob to be loaded contiguously | |
7289 | from start address. */ | |
7290 | ||
7291 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7292 | cpu_scratch_size = tp->fw_len; | |
7293 | info.fw_len = tp->fw->size - 12; | |
7294 | info.fw_data = &fw_data[3]; | |
7295 | ||
7296 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7297 | cpu_base = RX_CPU_BASE; | |
7298 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
7299 | } else { | |
7300 | cpu_base = TX_CPU_BASE; | |
7301 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
7302 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
7303 | } | |
7304 | ||
7305 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
7306 | cpu_scratch_base, cpu_scratch_size, | |
7307 | &info); | |
7308 | if (err) | |
7309 | return err; | |
7310 | ||
7311 | /* Now startup the cpu. */ | |
7312 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7313 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
7314 | ||
7315 | for (i = 0; i < 5; i++) { | |
7316 | if (tr32(cpu_base + CPU_PC) == info.fw_base) | |
7317 | break; | |
7318 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7319 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
7320 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
7321 | udelay(1000); | |
7322 | } | |
7323 | if (i >= 5) { | |
7324 | printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s " | |
7325 | "to set CPU PC, is %08x should be %08x\n", | |
7326 | tp->dev->name, tr32(cpu_base + CPU_PC), | |
7327 | info.fw_base); | |
7328 | return -ENODEV; | |
7329 | } | |
7330 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7331 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
7332 | return 0; | |
7333 | } | |
7334 | ||
7335 | ||
7336 | static int tg3_set_mac_addr(struct net_device *dev, void *p) | |
7337 | { | |
7338 | struct tg3 *tp = netdev_priv(dev); | |
7339 | struct sockaddr *addr = p; | |
7340 | int err = 0, skip_mac_1 = 0; | |
7341 | ||
7342 | if (!is_valid_ether_addr(addr->sa_data)) | |
7343 | return -EINVAL; | |
7344 | ||
7345 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
7346 | ||
7347 | if (!netif_running(dev)) | |
7348 | return 0; | |
7349 | ||
7350 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
7351 | u32 addr0_high, addr0_low, addr1_high, addr1_low; | |
7352 | ||
7353 | addr0_high = tr32(MAC_ADDR_0_HIGH); | |
7354 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7355 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7356 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7357 | ||
7358 | /* Skip MAC addr 1 if ASF is using it. */ | |
7359 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7360 | !(addr1_high == 0 && addr1_low == 0)) | |
7361 | skip_mac_1 = 1; | |
7362 | } | |
7363 | spin_lock_bh(&tp->lock); | |
7364 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7365 | spin_unlock_bh(&tp->lock); | |
7366 | ||
7367 | return err; | |
7368 | } | |
7369 | ||
7370 | /* tp->lock is held. */ | |
7371 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7372 | dma_addr_t mapping, u32 maxlen_flags, | |
7373 | u32 nic_addr) | |
7374 | { | |
7375 | tg3_write_mem(tp, | |
7376 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7377 | ((u64) mapping >> 32)); | |
7378 | tg3_write_mem(tp, | |
7379 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7380 | ((u64) mapping & 0xffffffff)); | |
7381 | tg3_write_mem(tp, | |
7382 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7383 | maxlen_flags); | |
7384 | ||
7385 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7386 | tg3_write_mem(tp, | |
7387 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7388 | nic_addr); | |
7389 | } | |
7390 | ||
7391 | static void __tg3_set_rx_mode(struct net_device *); | |
7392 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) | |
7393 | { | |
7394 | int i; | |
7395 | ||
7396 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) { | |
7397 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); | |
7398 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7399 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
7400 | } else { | |
7401 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7402 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7403 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
7404 | } | |
7405 | ||
7406 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { | |
7407 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); | |
7408 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7409 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7410 | } else { | |
7411 | tw32(HOSTCC_RXCOL_TICKS, 0); | |
7412 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7413 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
7414 | } | |
7415 | ||
7416 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7417 | u32 val = ec->stats_block_coalesce_usecs; | |
7418 | ||
7419 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); | |
7420 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7421 | ||
7422 | if (!netif_carrier_ok(tp->dev)) | |
7423 | val = 0; | |
7424 | ||
7425 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7426 | } | |
7427 | ||
7428 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7429 | u32 reg; | |
7430 | ||
7431 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7432 | tw32(reg, ec->rx_coalesce_usecs); | |
7433 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; | |
7434 | tw32(reg, ec->rx_max_coalesced_frames); | |
7435 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7436 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
7437 | ||
7438 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7439 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; | |
7440 | tw32(reg, ec->tx_coalesce_usecs); | |
7441 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7442 | tw32(reg, ec->tx_max_coalesced_frames); | |
7443 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7444 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7445 | } | |
7446 | } | |
7447 | ||
7448 | for (; i < tp->irq_max - 1; i++) { | |
7449 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7450 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7451 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7452 | ||
7453 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7454 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7455 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7456 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7457 | } | |
7458 | } | |
7459 | } | |
7460 | ||
7461 | /* tp->lock is held. */ | |
7462 | static void tg3_rings_reset(struct tg3 *tp) | |
7463 | { | |
7464 | int i; | |
7465 | u32 stblk, txrcb, rxrcb, limit; | |
7466 | struct tg3_napi *tnapi = &tp->napi[0]; | |
7467 | ||
7468 | /* Disable all transmit rings but the first. */ | |
7469 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7470 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; | |
7471 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
7472 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
7473 | else | |
7474 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7475 | ||
7476 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7477 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7478 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7479 | BDINFO_FLAGS_DISABLED); | |
7480 | ||
7481 | ||
7482 | /* Disable all receive return rings but the first. */ | |
7483 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
7484 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; | |
7485 | else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7486 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; | |
7487 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
7488 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
7489 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; | |
7490 | else | |
7491 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7492 | ||
7493 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7494 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7495 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7496 | BDINFO_FLAGS_DISABLED); | |
7497 | ||
7498 | /* Disable interrupts */ | |
7499 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
7500 | ||
7501 | /* Zero mailbox registers. */ | |
7502 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) { | |
7503 | for (i = 1; i < TG3_IRQ_MAX_VECS; i++) { | |
7504 | tp->napi[i].tx_prod = 0; | |
7505 | tp->napi[i].tx_cons = 0; | |
7506 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) | |
7507 | tw32_mailbox(tp->napi[i].prodmbox, 0); | |
7508 | tw32_rx_mbox(tp->napi[i].consmbox, 0); | |
7509 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7510 | } | |
7511 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) | |
7512 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7513 | } else { | |
7514 | tp->napi[0].tx_prod = 0; | |
7515 | tp->napi[0].tx_cons = 0; | |
7516 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7517 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7518 | } | |
7519 | ||
7520 | /* Make sure the NIC-based send BD rings are disabled. */ | |
7521 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7522 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
7523 | for (i = 0; i < 16; i++) | |
7524 | tw32_tx_mbox(mbox + i * 8, 0); | |
7525 | } | |
7526 | ||
7527 | txrcb = NIC_SRAM_SEND_RCB; | |
7528 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
7529 | ||
7530 | /* Clear status block in ram. */ | |
7531 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7532 | ||
7533 | /* Set status block DMA address */ | |
7534 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7535 | ((u64) tnapi->status_mapping >> 32)); | |
7536 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7537 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
7538 | ||
7539 | if (tnapi->tx_ring) { | |
7540 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7541 | (TG3_TX_RING_SIZE << | |
7542 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7543 | NIC_SRAM_TX_BUFFER_DESC); | |
7544 | txrcb += TG3_BDINFO_SIZE; | |
7545 | } | |
7546 | ||
7547 | if (tnapi->rx_rcb) { | |
7548 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7549 | (TG3_RX_RCB_RING_SIZE(tp) << | |
7550 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); | |
7551 | rxrcb += TG3_BDINFO_SIZE; | |
7552 | } | |
7553 | ||
7554 | stblk = HOSTCC_STATBLCK_RING1; | |
7555 | ||
7556 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { | |
7557 | u64 mapping = (u64)tnapi->status_mapping; | |
7558 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
7559 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
7560 | ||
7561 | /* Clear status block in ram. */ | |
7562 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7563 | ||
7564 | if (tnapi->tx_ring) { | |
7565 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7566 | (TG3_TX_RING_SIZE << | |
7567 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7568 | NIC_SRAM_TX_BUFFER_DESC); | |
7569 | txrcb += TG3_BDINFO_SIZE; | |
7570 | } | |
7571 | ||
7572 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7573 | (TG3_RX_RCB_RING_SIZE(tp) << | |
7574 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); | |
7575 | ||
7576 | stblk += 8; | |
7577 | rxrcb += TG3_BDINFO_SIZE; | |
7578 | } | |
7579 | } | |
7580 | ||
7581 | /* tp->lock is held. */ | |
7582 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |
7583 | { | |
7584 | u32 val, rdmac_mode; | |
7585 | int i, err, limit; | |
7586 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; | |
7587 | ||
7588 | tg3_disable_ints(tp); | |
7589 | ||
7590 | tg3_stop_fw(tp); | |
7591 | ||
7592 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
7593 | ||
7594 | if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) { | |
7595 | tg3_abort_hw(tp, 1); | |
7596 | } | |
7597 | ||
7598 | if (reset_phy && | |
7599 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) | |
7600 | tg3_phy_reset(tp); | |
7601 | ||
7602 | err = tg3_chip_reset(tp); | |
7603 | if (err) | |
7604 | return err; | |
7605 | ||
7606 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
7607 | ||
7608 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { | |
7609 | val = tr32(TG3_CPMU_CTRL); | |
7610 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
7611 | tw32(TG3_CPMU_CTRL, val); | |
7612 | ||
7613 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
7614 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
7615 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
7616 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
7617 | ||
7618 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
7619 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
7620 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
7621 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
7622 | ||
7623 | val = tr32(TG3_CPMU_HST_ACC); | |
7624 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
7625 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
7626 | tw32(TG3_CPMU_HST_ACC, val); | |
7627 | } | |
7628 | ||
7629 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
7630 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
7631 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
7632 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
7633 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
7634 | ||
7635 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
7636 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
7637 | ||
7638 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
7639 | ||
7640 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7641 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7642 | } | |
7643 | ||
7644 | if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) { | |
7645 | u32 grc_mode = tr32(GRC_MODE); | |
7646 | ||
7647 | /* Access the lower 1K of PL PCIE block registers. */ | |
7648 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
7649 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
7650 | ||
7651 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
7652 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
7653 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
7654 | ||
7655 | tw32(GRC_MODE, grc_mode); | |
7656 | } | |
7657 | ||
7658 | /* This works around an issue with Athlon chipsets on | |
7659 | * B3 tigon3 silicon. This bit has no effect on any | |
7660 | * other revision. But do not set this on PCI Express | |
7661 | * chips and don't even touch the clocks if the CPMU is present. | |
7662 | */ | |
7663 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) { | |
7664 | if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
7665 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; | |
7666 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7667 | } | |
7668 | ||
7669 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
7670 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
7671 | val = tr32(TG3PCI_PCISTATE); | |
7672 | val |= PCISTATE_RETRY_SAME_DMA; | |
7673 | tw32(TG3PCI_PCISTATE, val); | |
7674 | } | |
7675 | ||
7676 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { | |
7677 | /* Allow reads and writes to the | |
7678 | * APE register and memory space. | |
7679 | */ | |
7680 | val = tr32(TG3PCI_PCISTATE); | |
7681 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
7682 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
7683 | tw32(TG3PCI_PCISTATE, val); | |
7684 | } | |
7685 | ||
7686 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { | |
7687 | /* Enable some hw fixes. */ | |
7688 | val = tr32(TG3PCI_MSI_DATA); | |
7689 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
7690 | tw32(TG3PCI_MSI_DATA, val); | |
7691 | } | |
7692 | ||
7693 | /* Descriptor ring init may make accesses to the | |
7694 | * NIC SRAM area to setup the TX descriptors, so we | |
7695 | * can only do this after the hardware has been | |
7696 | * successfully reset. | |
7697 | */ | |
7698 | err = tg3_init_rings(tp); | |
7699 | if (err) | |
7700 | return err; | |
7701 | ||
7702 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
7703 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
7704 | val = tr32(TG3PCI_DMA_RW_CTRL) & | |
7705 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
7706 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); | |
7707 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
7708 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
7709 | /* This value is determined during the probe time DMA | |
7710 | * engine test, tg3_test_dma. | |
7711 | */ | |
7712 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
7713 | } | |
7714 | ||
7715 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
7716 | GRC_MODE_4X_NIC_SEND_RINGS | | |
7717 | GRC_MODE_NO_TX_PHDR_CSUM | | |
7718 | GRC_MODE_NO_RX_PHDR_CSUM); | |
7719 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
7720 | ||
7721 | /* Pseudo-header checksum is done by hardware logic and not | |
7722 | * the offload processers, so make the chip do the pseudo- | |
7723 | * header checksums on receive. For transmit it is more | |
7724 | * convenient to do the pseudo-header checksum in software | |
7725 | * as Linux does that on transmit for us in all cases. | |
7726 | */ | |
7727 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
7728 | ||
7729 | tw32(GRC_MODE, | |
7730 | tp->grc_mode | | |
7731 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
7732 | ||
7733 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
7734 | val = tr32(GRC_MISC_CFG); | |
7735 | val &= ~0xff; | |
7736 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
7737 | tw32(GRC_MISC_CFG, val); | |
7738 | ||
7739 | /* Initialize MBUF/DESC pool. */ | |
7740 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
7741 | /* Do nothing. */ | |
7742 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
7743 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
7744 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
7745 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
7746 | else | |
7747 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
7748 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
7749 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
7750 | } | |
7751 | else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { | |
7752 | int fw_len; | |
7753 | ||
7754 | fw_len = tp->fw_len; | |
7755 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); | |
7756 | tw32(BUFMGR_MB_POOL_ADDR, | |
7757 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
7758 | tw32(BUFMGR_MB_POOL_SIZE, | |
7759 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
7760 | } | |
7761 | ||
7762 | if (tp->dev->mtu <= ETH_DATA_LEN) { | |
7763 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
7764 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
7765 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
7766 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
7767 | tw32(BUFMGR_MB_HIGH_WATER, | |
7768 | tp->bufmgr_config.mbuf_high_water); | |
7769 | } else { | |
7770 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
7771 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
7772 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
7773 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
7774 | tw32(BUFMGR_MB_HIGH_WATER, | |
7775 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
7776 | } | |
7777 | tw32(BUFMGR_DMA_LOW_WATER, | |
7778 | tp->bufmgr_config.dma_low_water); | |
7779 | tw32(BUFMGR_DMA_HIGH_WATER, | |
7780 | tp->bufmgr_config.dma_high_water); | |
7781 | ||
7782 | tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); | |
7783 | for (i = 0; i < 2000; i++) { | |
7784 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
7785 | break; | |
7786 | udelay(10); | |
7787 | } | |
7788 | if (i >= 2000) { | |
7789 | printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n", | |
7790 | tp->dev->name); | |
7791 | return -ENODEV; | |
7792 | } | |
7793 | ||
7794 | /* Setup replenish threshold. */ | |
7795 | val = tp->rx_pending / 8; | |
7796 | if (val == 0) | |
7797 | val = 1; | |
7798 | else if (val > tp->rx_std_max_post) | |
7799 | val = tp->rx_std_max_post; | |
7800 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
7801 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) | |
7802 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
7803 | ||
7804 | if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2)) | |
7805 | val = TG3_RX_INTERNAL_RING_SZ_5906 / 2; | |
7806 | } | |
7807 | ||
7808 | tw32(RCVBDI_STD_THRESH, val); | |
7809 | ||
7810 | /* Initialize TG3_BDINFO's at: | |
7811 | * RCVDBDI_STD_BD: standard eth size rx ring | |
7812 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
7813 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
7814 | * | |
7815 | * like so: | |
7816 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
7817 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
7818 | * ring attribute flags | |
7819 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
7820 | * | |
7821 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
7822 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
7823 | * | |
7824 | * The size of each ring is fixed in the firmware, but the location is | |
7825 | * configurable. | |
7826 | */ | |
7827 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7828 | ((u64) tpr->rx_std_mapping >> 32)); | |
7829 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7830 | ((u64) tpr->rx_std_mapping & 0xffffffff)); | |
7831 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
7832 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, | |
7833 | NIC_SRAM_RX_BUFFER_DESC); | |
7834 | ||
7835 | /* Disable the mini ring */ | |
7836 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7837 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
7838 | BDINFO_FLAGS_DISABLED); | |
7839 | ||
7840 | /* Program the jumbo buffer descriptor ring control | |
7841 | * blocks on those devices that have them. | |
7842 | */ | |
7843 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && | |
7844 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
7845 | /* Setup replenish threshold. */ | |
7846 | tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); | |
7847 | ||
7848 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { | |
7849 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7850 | ((u64) tpr->rx_jmb_mapping >> 32)); | |
7851 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7852 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); | |
7853 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
7854 | (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) | | |
7855 | BDINFO_FLAGS_USE_EXT_RECV); | |
7856 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
7857 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, | |
7858 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
7859 | } else { | |
7860 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
7861 | BDINFO_FLAGS_DISABLED); | |
7862 | } | |
7863 | ||
7864 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
7865 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
7866 | val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) | | |
7867 | (RX_STD_MAX_SIZE << 2); | |
7868 | else | |
7869 | val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT; | |
7870 | } else | |
7871 | val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT; | |
7872 | ||
7873 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
7874 | ||
7875 | tpr->rx_std_prod_idx = tp->rx_pending; | |
7876 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); | |
7877 | ||
7878 | tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? | |
7879 | tp->rx_jumbo_pending : 0; | |
7880 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); | |
7881 | ||
7882 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
7883 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
7884 | tw32(STD_REPLENISH_LWM, 32); | |
7885 | tw32(JMB_REPLENISH_LWM, 16); | |
7886 | } | |
7887 | ||
7888 | tg3_rings_reset(tp); | |
7889 | ||
7890 | /* Initialize MAC address and backoff seed. */ | |
7891 | __tg3_set_mac_addr(tp, 0); | |
7892 | ||
7893 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
7894 | tw32(MAC_RX_MTU_SIZE, | |
7895 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
7896 | ||
7897 | /* The slot time is changed by tg3_setup_phy if we | |
7898 | * run at gigabit with half duplex. | |
7899 | */ | |
7900 | tw32(MAC_TX_LENGTHS, | |
7901 | (2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
7902 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
7903 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
7904 | ||
7905 | /* Receive rules. */ | |
7906 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
7907 | tw32(RCVLPC_CONFIG, 0x0181); | |
7908 | ||
7909 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
7910 | * the RCVLPC_STATE_ENABLE mask. | |
7911 | */ | |
7912 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
7913 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
7914 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
7915 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
7916 | RDMAC_MODE_LNGREAD_ENAB); | |
7917 | ||
7918 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
7919 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; | |
7920 | ||
7921 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
7922 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
7923 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
7924 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | | |
7925 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
7926 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
7927 | ||
7928 | /* If statement applies to 5705 and 5750 PCI devices only */ | |
7929 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
7930 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
7931 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) { | |
7932 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && | |
7933 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7934 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; | |
7935 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
7936 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { | |
7937 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
7938 | } | |
7939 | } | |
7940 | ||
7941 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
7942 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
7943 | ||
7944 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
7945 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; | |
7946 | ||
7947 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || | |
7948 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
7949 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
7950 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
7951 | ||
7952 | /* Receive/send statistics. */ | |
7953 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
7954 | val = tr32(RCVLPC_STATS_ENABLE); | |
7955 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
7956 | tw32(RCVLPC_STATS_ENABLE, val); | |
7957 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
7958 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
7959 | val = tr32(RCVLPC_STATS_ENABLE); | |
7960 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
7961 | tw32(RCVLPC_STATS_ENABLE, val); | |
7962 | } else { | |
7963 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
7964 | } | |
7965 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
7966 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
7967 | tw32(SNDDATAI_STATSCTRL, | |
7968 | (SNDDATAI_SCTRL_ENABLE | | |
7969 | SNDDATAI_SCTRL_FASTUPD)); | |
7970 | ||
7971 | /* Setup host coalescing engine. */ | |
7972 | tw32(HOSTCC_MODE, 0); | |
7973 | for (i = 0; i < 2000; i++) { | |
7974 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
7975 | break; | |
7976 | udelay(10); | |
7977 | } | |
7978 | ||
7979 | __tg3_set_coalesce(tp, &tp->coal); | |
7980 | ||
7981 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7982 | /* Status/statistics block address. See tg3_timer, | |
7983 | * the tg3_periodic_fetch_stats call there, and | |
7984 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
7985 | */ | |
7986 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7987 | ((u64) tp->stats_mapping >> 32)); | |
7988 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7989 | ((u64) tp->stats_mapping & 0xffffffff)); | |
7990 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
7991 | ||
7992 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); | |
7993 | ||
7994 | /* Clear statistics and status block memory areas */ | |
7995 | for (i = NIC_SRAM_STATS_BLK; | |
7996 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
7997 | i += sizeof(u32)) { | |
7998 | tg3_write_mem(tp, i, 0); | |
7999 | udelay(40); | |
8000 | } | |
8001 | } | |
8002 | ||
8003 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8004 | ||
8005 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8006 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
8007 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8008 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); | |
8009 | ||
8010 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
8011 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
8012 | /* reset to prevent losing 1st rx packet intermittently */ | |
8013 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8014 | udelay(10); | |
8015 | } | |
8016 | ||
8017 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
8018 | tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
8019 | else | |
8020 | tp->mac_mode = 0; | |
8021 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
8022 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; | |
8023 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
8024 | !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
8025 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | |
8026 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
8027 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); | |
8028 | udelay(40); | |
8029 | ||
8030 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). | |
8031 | * If TG3_FLG2_IS_NIC is zero, we should read the | |
8032 | * register to preserve the GPIO settings for LOMs. The GPIOs, | |
8033 | * whether used as inputs or outputs, are set by boot code after | |
8034 | * reset. | |
8035 | */ | |
8036 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) { | |
8037 | u32 gpio_mask; | |
8038 | ||
8039 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | | |
8040 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8041 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
8042 | ||
8043 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8044 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8045 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8046 | ||
8047 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
8048 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8049 | ||
8050 | tp->grc_local_ctrl &= ~gpio_mask; | |
8051 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; | |
8052 | ||
8053 | /* GPIO1 must be driven high for eeprom write protect */ | |
8054 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) | |
8055 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
8056 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
8057 | } | |
8058 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8059 | udelay(100); | |
8060 | ||
8061 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) { | |
8062 | val = tr32(MSGINT_MODE); | |
8063 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
8064 | tw32(MSGINT_MODE, val); | |
8065 | } | |
8066 | ||
8067 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
8068 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | |
8069 | udelay(40); | |
8070 | } | |
8071 | ||
8072 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8073 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8074 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8075 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8076 | WDMAC_MODE_LNGREAD_ENAB); | |
8077 | ||
8078 | /* If statement applies to 5705 and 5750 PCI devices only */ | |
8079 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
8080 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
8081 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { | |
8082 | if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && | |
8083 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || | |
8084 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8085 | /* nothing */ | |
8086 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
8087 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
8088 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
8089 | val |= WDMAC_MODE_RX_ACCEL; | |
8090 | } | |
8091 | } | |
8092 | ||
8093 | /* Enable host coalescing bug fix */ | |
8094 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
8095 | val |= WDMAC_MODE_STATUS_TAG_FIX; | |
8096 | ||
8097 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
8098 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8099 | ||
8100 | tw32_f(WDMAC_MODE, val); | |
8101 | udelay(40); | |
8102 | ||
8103 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
8104 | u16 pcix_cmd; | |
8105 | ||
8106 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8107 | &pcix_cmd); | |
8108 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { | |
8109 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; | |
8110 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
8111 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
8112 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); | |
8113 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
8114 | } | |
8115 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8116 | pcix_cmd); | |
8117 | } | |
8118 | ||
8119 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8120 | udelay(40); | |
8121 | ||
8122 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
8123 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8124 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | |
8125 | ||
8126 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8127 | tw32(SNDDATAC_MODE, | |
8128 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8129 | else | |
8130 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8131 | ||
8132 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); | |
8133 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
8134 | tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ); | |
8135 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); | |
8136 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
8137 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); | |
8138 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; | |
8139 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) | |
8140 | val |= SNDBDI_MODE_MULTI_TXQ_EN; | |
8141 | tw32(SNDBDI_MODE, val); | |
8142 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); | |
8143 | ||
8144 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8145 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8146 | if (err) | |
8147 | return err; | |
8148 | } | |
8149 | ||
8150 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { | |
8151 | err = tg3_load_tso_firmware(tp); | |
8152 | if (err) | |
8153 | return err; | |
8154 | } | |
8155 | ||
8156 | tp->tx_mode = TX_MODE_ENABLE; | |
8157 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
8158 | udelay(100); | |
8159 | ||
8160 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { | |
8161 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8162 | u8 *ent = (u8 *)&val; | |
8163 | ||
8164 | /* Setup the indirection table */ | |
8165 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8166 | int idx = i % sizeof(val); | |
8167 | ||
8168 | ent[idx] = i % (tp->irq_cnt - 1); | |
8169 | if (idx == sizeof(val) - 1) { | |
8170 | tw32(reg, val); | |
8171 | reg += 4; | |
8172 | } | |
8173 | } | |
8174 | ||
8175 | /* Setup the "secret" hash key. */ | |
8176 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8177 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8178 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8179 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8180 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8181 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8182 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8183 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8184 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8185 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8186 | } | |
8187 | ||
8188 | tp->rx_mode = RX_MODE_ENABLE; | |
8189 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
8190 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; | |
8191 | ||
8192 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) | |
8193 | tp->rx_mode |= RX_MODE_RSS_ENABLE | | |
8194 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8195 | RX_MODE_RSS_IPV6_HASH_EN | | |
8196 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8197 | RX_MODE_RSS_IPV4_HASH_EN | | |
8198 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8199 | ||
8200 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8201 | udelay(10); | |
8202 | ||
8203 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
8204 | ||
8205 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
8206 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
8207 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8208 | udelay(10); | |
8209 | } | |
8210 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8211 | udelay(10); | |
8212 | ||
8213 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
8214 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && | |
8215 | !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) { | |
8216 | /* Set drive transmission level to 1.2V */ | |
8217 | /* only if the signal pre-emphasis bit is not set */ | |
8218 | val = tr32(MAC_SERDES_CFG); | |
8219 | val &= 0xfffff000; | |
8220 | val |= 0x880; | |
8221 | tw32(MAC_SERDES_CFG, val); | |
8222 | } | |
8223 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8224 | tw32(MAC_SERDES_CFG, 0x616000); | |
8225 | } | |
8226 | ||
8227 | /* Prevent chip from dropping frames when flow control | |
8228 | * is enabled. | |
8229 | */ | |
8230 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
8231 | val = 1; | |
8232 | else | |
8233 | val = 2; | |
8234 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
8235 | ||
8236 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
8237 | (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
8238 | /* Use hardware link auto-negotiation */ | |
8239 | tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG; | |
8240 | } | |
8241 | ||
8242 | if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && | |
8243 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { | |
8244 | u32 tmp; | |
8245 | ||
8246 | tmp = tr32(SERDES_RX_CTRL); | |
8247 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8248 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8249 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8250 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8251 | } | |
8252 | ||
8253 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { | |
8254 | if (tp->link_config.phy_is_low_power) { | |
8255 | tp->link_config.phy_is_low_power = 0; | |
8256 | tp->link_config.speed = tp->link_config.orig_speed; | |
8257 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
8258 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
8259 | } | |
8260 | ||
8261 | err = tg3_setup_phy(tp, 0); | |
8262 | if (err) | |
8263 | return err; | |
8264 | ||
8265 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
8266 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) { | |
8267 | u32 tmp; | |
8268 | ||
8269 | /* Clear CRC stats. */ | |
8270 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
8271 | tg3_writephy(tp, MII_TG3_TEST1, | |
8272 | tmp | MII_TG3_TEST1_CRC_EN); | |
8273 | tg3_readphy(tp, 0x14, &tmp); | |
8274 | } | |
8275 | } | |
8276 | } | |
8277 | ||
8278 | __tg3_set_rx_mode(tp->dev); | |
8279 | ||
8280 | /* Initialize receive rules. */ | |
8281 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
8282 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8283 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
8284 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8285 | ||
8286 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
8287 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
8288 | limit = 8; | |
8289 | else | |
8290 | limit = 16; | |
8291 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
8292 | limit -= 4; | |
8293 | switch (limit) { | |
8294 | case 16: | |
8295 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
8296 | case 15: | |
8297 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
8298 | case 14: | |
8299 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
8300 | case 13: | |
8301 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
8302 | case 12: | |
8303 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
8304 | case 11: | |
8305 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
8306 | case 10: | |
8307 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
8308 | case 9: | |
8309 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
8310 | case 8: | |
8311 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
8312 | case 7: | |
8313 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
8314 | case 6: | |
8315 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
8316 | case 5: | |
8317 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
8318 | case 4: | |
8319 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
8320 | case 3: | |
8321 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
8322 | case 2: | |
8323 | case 1: | |
8324 | ||
8325 | default: | |
8326 | break; | |
8327 | } | |
8328 | ||
8329 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
8330 | /* Write our heartbeat update interval to APE. */ | |
8331 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
8332 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
8333 | ||
8334 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); | |
8335 | ||
8336 | return 0; | |
8337 | } | |
8338 | ||
8339 | /* Called at device open time to get the chip ready for | |
8340 | * packet processing. Invoked with tp->lock held. | |
8341 | */ | |
8342 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) | |
8343 | { | |
8344 | tg3_switch_clocks(tp); | |
8345 | ||
8346 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
8347 | ||
8348 | return tg3_reset_hw(tp, reset_phy); | |
8349 | } | |
8350 | ||
8351 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
8352 | do { u32 __val = tr32(REG); \ | |
8353 | (PSTAT)->low += __val; \ | |
8354 | if ((PSTAT)->low < __val) \ | |
8355 | (PSTAT)->high += 1; \ | |
8356 | } while (0) | |
8357 | ||
8358 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
8359 | { | |
8360 | struct tg3_hw_stats *sp = tp->hw_stats; | |
8361 | ||
8362 | if (!netif_carrier_ok(tp->dev)) | |
8363 | return; | |
8364 | ||
8365 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
8366 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
8367 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
8368 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
8369 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
8370 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
8371 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
8372 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
8373 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
8374 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
8375 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
8376 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
8377 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
8378 | ||
8379 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
8380 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
8381 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
8382 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
8383 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
8384 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
8385 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
8386 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
8387 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
8388 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
8389 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
8390 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
8391 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
8392 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
8393 | ||
8394 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
8395 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | |
8396 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); | |
8397 | } | |
8398 | ||
8399 | static void tg3_timer(unsigned long __opaque) | |
8400 | { | |
8401 | struct tg3 *tp = (struct tg3 *) __opaque; | |
8402 | ||
8403 | if (tp->irq_sync) | |
8404 | goto restart_timer; | |
8405 | ||
8406 | spin_lock(&tp->lock); | |
8407 | ||
8408 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
8409 | /* All of this garbage is because when using non-tagged | |
8410 | * IRQ status the mailbox/status_block protocol the chip | |
8411 | * uses with the cpu is race prone. | |
8412 | */ | |
8413 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { | |
8414 | tw32(GRC_LOCAL_CTRL, | |
8415 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
8416 | } else { | |
8417 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
8418 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); | |
8419 | } | |
8420 | ||
8421 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
8422 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; | |
8423 | spin_unlock(&tp->lock); | |
8424 | schedule_work(&tp->reset_task); | |
8425 | return; | |
8426 | } | |
8427 | } | |
8428 | ||
8429 | /* This part only runs once per second. */ | |
8430 | if (!--tp->timer_counter) { | |
8431 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
8432 | tg3_periodic_fetch_stats(tp); | |
8433 | ||
8434 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { | |
8435 | u32 mac_stat; | |
8436 | int phy_event; | |
8437 | ||
8438 | mac_stat = tr32(MAC_STATUS); | |
8439 | ||
8440 | phy_event = 0; | |
8441 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) { | |
8442 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) | |
8443 | phy_event = 1; | |
8444 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
8445 | phy_event = 1; | |
8446 | ||
8447 | if (phy_event) | |
8448 | tg3_setup_phy(tp, 0); | |
8449 | } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) { | |
8450 | u32 mac_stat = tr32(MAC_STATUS); | |
8451 | int need_setup = 0; | |
8452 | ||
8453 | if (netif_carrier_ok(tp->dev) && | |
8454 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
8455 | need_setup = 1; | |
8456 | } | |
8457 | if (! netif_carrier_ok(tp->dev) && | |
8458 | (mac_stat & (MAC_STATUS_PCS_SYNCED | | |
8459 | MAC_STATUS_SIGNAL_DET))) { | |
8460 | need_setup = 1; | |
8461 | } | |
8462 | if (need_setup) { | |
8463 | if (!tp->serdes_counter) { | |
8464 | tw32_f(MAC_MODE, | |
8465 | (tp->mac_mode & | |
8466 | ~MAC_MODE_PORT_MODE_MASK)); | |
8467 | udelay(40); | |
8468 | tw32_f(MAC_MODE, tp->mac_mode); | |
8469 | udelay(40); | |
8470 | } | |
8471 | tg3_setup_phy(tp, 0); | |
8472 | } | |
8473 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) | |
8474 | tg3_serdes_parallel_detect(tp); | |
8475 | ||
8476 | tp->timer_counter = tp->timer_multiplier; | |
8477 | } | |
8478 | ||
8479 | /* Heartbeat is only sent once every 2 seconds. | |
8480 | * | |
8481 | * The heartbeat is to tell the ASF firmware that the host | |
8482 | * driver is still alive. In the event that the OS crashes, | |
8483 | * ASF needs to reset the hardware to free up the FIFO space | |
8484 | * that may be filled with rx packets destined for the host. | |
8485 | * If the FIFO is full, ASF will no longer function properly. | |
8486 | * | |
8487 | * Unintended resets have been reported on real time kernels | |
8488 | * where the timer doesn't run on time. Netpoll will also have | |
8489 | * same problem. | |
8490 | * | |
8491 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
8492 | * to check the ring condition when the heartbeat is expiring | |
8493 | * before doing the reset. This will prevent most unintended | |
8494 | * resets. | |
8495 | */ | |
8496 | if (!--tp->asf_counter) { | |
8497 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && | |
8498 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
8499 | tg3_wait_for_event_ack(tp); | |
8500 | ||
8501 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, | |
8502 | FWCMD_NICDRV_ALIVE3); | |
8503 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); | |
8504 | /* 5 seconds timeout */ | |
8505 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5); | |
8506 | ||
8507 | tg3_generate_fw_event(tp); | |
8508 | } | |
8509 | tp->asf_counter = tp->asf_multiplier; | |
8510 | } | |
8511 | ||
8512 | spin_unlock(&tp->lock); | |
8513 | ||
8514 | restart_timer: | |
8515 | tp->timer.expires = jiffies + tp->timer_offset; | |
8516 | add_timer(&tp->timer); | |
8517 | } | |
8518 | ||
8519 | static int tg3_request_irq(struct tg3 *tp, int irq_num) | |
8520 | { | |
8521 | irq_handler_t fn; | |
8522 | unsigned long flags; | |
8523 | char *name; | |
8524 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
8525 | ||
8526 | if (tp->irq_cnt == 1) | |
8527 | name = tp->dev->name; | |
8528 | else { | |
8529 | name = &tnapi->irq_lbl[0]; | |
8530 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
8531 | name[IFNAMSIZ-1] = 0; | |
8532 | } | |
8533 | ||
8534 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { | |
8535 | fn = tg3_msi; | |
8536 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
8537 | fn = tg3_msi_1shot; | |
8538 | flags = IRQF_SAMPLE_RANDOM; | |
8539 | } else { | |
8540 | fn = tg3_interrupt; | |
8541 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
8542 | fn = tg3_interrupt_tagged; | |
8543 | flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM; | |
8544 | } | |
8545 | ||
8546 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
8547 | } | |
8548 | ||
8549 | static int tg3_test_interrupt(struct tg3 *tp) | |
8550 | { | |
8551 | struct tg3_napi *tnapi = &tp->napi[0]; | |
8552 | struct net_device *dev = tp->dev; | |
8553 | int err, i, intr_ok = 0; | |
8554 | u32 val; | |
8555 | ||
8556 | if (!netif_running(dev)) | |
8557 | return -ENODEV; | |
8558 | ||
8559 | tg3_disable_ints(tp); | |
8560 | ||
8561 | free_irq(tnapi->irq_vec, tnapi); | |
8562 | ||
8563 | /* | |
8564 | * Turn off MSI one shot mode. Otherwise this test has no | |
8565 | * observable way to know whether the interrupt was delivered. | |
8566 | */ | |
8567 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
8568 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | |
8569 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { | |
8570 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; | |
8571 | tw32(MSGINT_MODE, val); | |
8572 | } | |
8573 | ||
8574 | err = request_irq(tnapi->irq_vec, tg3_test_isr, | |
8575 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); | |
8576 | if (err) | |
8577 | return err; | |
8578 | ||
8579 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; | |
8580 | tg3_enable_ints(tp); | |
8581 | ||
8582 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
8583 | tnapi->coal_now); | |
8584 | ||
8585 | for (i = 0; i < 5; i++) { | |
8586 | u32 int_mbox, misc_host_ctrl; | |
8587 | ||
8588 | int_mbox = tr32_mailbox(tnapi->int_mbox); | |
8589 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); | |
8590 | ||
8591 | if ((int_mbox != 0) || | |
8592 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
8593 | intr_ok = 1; | |
8594 | break; | |
8595 | } | |
8596 | ||
8597 | msleep(10); | |
8598 | } | |
8599 | ||
8600 | tg3_disable_ints(tp); | |
8601 | ||
8602 | free_irq(tnapi->irq_vec, tnapi); | |
8603 | ||
8604 | err = tg3_request_irq(tp, 0); | |
8605 | ||
8606 | if (err) | |
8607 | return err; | |
8608 | ||
8609 | if (intr_ok) { | |
8610 | /* Reenable MSI one shot mode. */ | |
8611 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
8612 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | |
8613 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { | |
8614 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; | |
8615 | tw32(MSGINT_MODE, val); | |
8616 | } | |
8617 | return 0; | |
8618 | } | |
8619 | ||
8620 | return -EIO; | |
8621 | } | |
8622 | ||
8623 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
8624 | * successfully restored | |
8625 | */ | |
8626 | static int tg3_test_msi(struct tg3 *tp) | |
8627 | { | |
8628 | int err; | |
8629 | u16 pci_cmd; | |
8630 | ||
8631 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) | |
8632 | return 0; | |
8633 | ||
8634 | /* Turn off SERR reporting in case MSI terminates with Master | |
8635 | * Abort. | |
8636 | */ | |
8637 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
8638 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
8639 | pci_cmd & ~PCI_COMMAND_SERR); | |
8640 | ||
8641 | err = tg3_test_interrupt(tp); | |
8642 | ||
8643 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
8644 | ||
8645 | if (!err) | |
8646 | return 0; | |
8647 | ||
8648 | /* other failures */ | |
8649 | if (err != -EIO) | |
8650 | return err; | |
8651 | ||
8652 | /* MSI test failed, go back to INTx mode */ | |
8653 | printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " | |
8654 | "switching to INTx mode. Please report this failure to " | |
8655 | "the PCI maintainer and include system chipset information.\n", | |
8656 | tp->dev->name); | |
8657 | ||
8658 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); | |
8659 | ||
8660 | pci_disable_msi(tp->pdev); | |
8661 | ||
8662 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
8663 | ||
8664 | err = tg3_request_irq(tp, 0); | |
8665 | if (err) | |
8666 | return err; | |
8667 | ||
8668 | /* Need to reset the chip because the MSI cycle may have terminated | |
8669 | * with Master Abort. | |
8670 | */ | |
8671 | tg3_full_lock(tp, 1); | |
8672 | ||
8673 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
8674 | err = tg3_init_hw(tp, 1); | |
8675 | ||
8676 | tg3_full_unlock(tp); | |
8677 | ||
8678 | if (err) | |
8679 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); | |
8680 | ||
8681 | return err; | |
8682 | } | |
8683 | ||
8684 | static int tg3_request_firmware(struct tg3 *tp) | |
8685 | { | |
8686 | const __be32 *fw_data; | |
8687 | ||
8688 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
8689 | printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n", | |
8690 | tp->dev->name, tp->fw_needed); | |
8691 | return -ENOENT; | |
8692 | } | |
8693 | ||
8694 | fw_data = (void *)tp->fw->data; | |
8695 | ||
8696 | /* Firmware blob starts with version numbers, followed by | |
8697 | * start address and _full_ length including BSS sections | |
8698 | * (which must be longer than the actual data, of course | |
8699 | */ | |
8700 | ||
8701 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
8702 | if (tp->fw_len < (tp->fw->size - 12)) { | |
8703 | printk(KERN_ERR "%s: bogus length %d in \"%s\"\n", | |
8704 | tp->dev->name, tp->fw_len, tp->fw_needed); | |
8705 | release_firmware(tp->fw); | |
8706 | tp->fw = NULL; | |
8707 | return -EINVAL; | |
8708 | } | |
8709 | ||
8710 | /* We no longer need firmware; we have it. */ | |
8711 | tp->fw_needed = NULL; | |
8712 | return 0; | |
8713 | } | |
8714 | ||
8715 | static bool tg3_enable_msix(struct tg3 *tp) | |
8716 | { | |
8717 | int i, rc, cpus = num_online_cpus(); | |
8718 | struct msix_entry msix_ent[tp->irq_max]; | |
8719 | ||
8720 | if (cpus == 1) | |
8721 | /* Just fallback to the simpler MSI mode. */ | |
8722 | return false; | |
8723 | ||
8724 | /* | |
8725 | * We want as many rx rings enabled as there are cpus. | |
8726 | * The first MSIX vector only deals with link interrupts, etc, | |
8727 | * so we add one to the number of vectors we are requesting. | |
8728 | */ | |
8729 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
8730 | ||
8731 | for (i = 0; i < tp->irq_max; i++) { | |
8732 | msix_ent[i].entry = i; | |
8733 | msix_ent[i].vector = 0; | |
8734 | } | |
8735 | ||
8736 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
8737 | if (rc != 0) { | |
8738 | if (rc < TG3_RSS_MIN_NUM_MSIX_VECS) | |
8739 | return false; | |
8740 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) | |
8741 | return false; | |
8742 | printk(KERN_NOTICE | |
8743 | "%s: Requested %d MSI-X vectors, received %d\n", | |
8744 | tp->dev->name, tp->irq_cnt, rc); | |
8745 | tp->irq_cnt = rc; | |
8746 | } | |
8747 | ||
8748 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS; | |
8749 | ||
8750 | for (i = 0; i < tp->irq_max; i++) | |
8751 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
8752 | ||
8753 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
8754 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS; | |
8755 | tp->dev->real_num_tx_queues = tp->irq_cnt - 1; | |
8756 | } else | |
8757 | tp->dev->real_num_tx_queues = 1; | |
8758 | ||
8759 | return true; | |
8760 | } | |
8761 | ||
8762 | static void tg3_ints_init(struct tg3 *tp) | |
8763 | { | |
8764 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) && | |
8765 | !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
8766 | /* All MSI supporting chips should support tagged | |
8767 | * status. Assert that this is the case. | |
8768 | */ | |
8769 | printk(KERN_WARNING PFX "%s: MSI without TAGGED? " | |
8770 | "Not using MSI.\n", tp->dev->name); | |
8771 | goto defcfg; | |
8772 | } | |
8773 | ||
8774 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp)) | |
8775 | tp->tg3_flags2 |= TG3_FLG2_USING_MSIX; | |
8776 | else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) && | |
8777 | pci_enable_msi(tp->pdev) == 0) | |
8778 | tp->tg3_flags2 |= TG3_FLG2_USING_MSI; | |
8779 | ||
8780 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { | |
8781 | u32 msi_mode = tr32(MSGINT_MODE); | |
8782 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) | |
8783 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; | |
8784 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); | |
8785 | } | |
8786 | defcfg: | |
8787 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { | |
8788 | tp->irq_cnt = 1; | |
8789 | tp->napi[0].irq_vec = tp->pdev->irq; | |
8790 | tp->dev->real_num_tx_queues = 1; | |
8791 | } | |
8792 | } | |
8793 | ||
8794 | static void tg3_ints_fini(struct tg3 *tp) | |
8795 | { | |
8796 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) | |
8797 | pci_disable_msix(tp->pdev); | |
8798 | else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) | |
8799 | pci_disable_msi(tp->pdev); | |
8800 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX; | |
8801 | tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS; | |
8802 | } | |
8803 | ||
8804 | static int tg3_open(struct net_device *dev) | |
8805 | { | |
8806 | struct tg3 *tp = netdev_priv(dev); | |
8807 | int i, err; | |
8808 | ||
8809 | if (tp->fw_needed) { | |
8810 | err = tg3_request_firmware(tp); | |
8811 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8812 | if (err) | |
8813 | return err; | |
8814 | } else if (err) { | |
8815 | printk(KERN_WARNING "%s: TSO capability disabled.\n", | |
8816 | tp->dev->name); | |
8817 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; | |
8818 | } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
8819 | printk(KERN_NOTICE "%s: TSO capability restored.\n", | |
8820 | tp->dev->name); | |
8821 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; | |
8822 | } | |
8823 | } | |
8824 | ||
8825 | netif_carrier_off(tp->dev); | |
8826 | ||
8827 | err = tg3_set_power_state(tp, PCI_D0); | |
8828 | if (err) | |
8829 | return err; | |
8830 | ||
8831 | tg3_full_lock(tp, 0); | |
8832 | ||
8833 | tg3_disable_ints(tp); | |
8834 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
8835 | ||
8836 | tg3_full_unlock(tp); | |
8837 | ||
8838 | /* | |
8839 | * Setup interrupts first so we know how | |
8840 | * many NAPI resources to allocate | |
8841 | */ | |
8842 | tg3_ints_init(tp); | |
8843 | ||
8844 | /* The placement of this call is tied | |
8845 | * to the setup and use of Host TX descriptors. | |
8846 | */ | |
8847 | err = tg3_alloc_consistent(tp); | |
8848 | if (err) | |
8849 | goto err_out1; | |
8850 | ||
8851 | tg3_napi_enable(tp); | |
8852 | ||
8853 | for (i = 0; i < tp->irq_cnt; i++) { | |
8854 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8855 | err = tg3_request_irq(tp, i); | |
8856 | if (err) { | |
8857 | for (i--; i >= 0; i--) | |
8858 | free_irq(tnapi->irq_vec, tnapi); | |
8859 | break; | |
8860 | } | |
8861 | } | |
8862 | ||
8863 | if (err) | |
8864 | goto err_out2; | |
8865 | ||
8866 | tg3_full_lock(tp, 0); | |
8867 | ||
8868 | err = tg3_init_hw(tp, 1); | |
8869 | if (err) { | |
8870 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
8871 | tg3_free_rings(tp); | |
8872 | } else { | |
8873 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
8874 | tp->timer_offset = HZ; | |
8875 | else | |
8876 | tp->timer_offset = HZ / 10; | |
8877 | ||
8878 | BUG_ON(tp->timer_offset > HZ); | |
8879 | tp->timer_counter = tp->timer_multiplier = | |
8880 | (HZ / tp->timer_offset); | |
8881 | tp->asf_counter = tp->asf_multiplier = | |
8882 | ((HZ / tp->timer_offset) * 2); | |
8883 | ||
8884 | init_timer(&tp->timer); | |
8885 | tp->timer.expires = jiffies + tp->timer_offset; | |
8886 | tp->timer.data = (unsigned long) tp; | |
8887 | tp->timer.function = tg3_timer; | |
8888 | } | |
8889 | ||
8890 | tg3_full_unlock(tp); | |
8891 | ||
8892 | if (err) | |
8893 | goto err_out3; | |
8894 | ||
8895 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
8896 | err = tg3_test_msi(tp); | |
8897 | ||
8898 | if (err) { | |
8899 | tg3_full_lock(tp, 0); | |
8900 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
8901 | tg3_free_rings(tp); | |
8902 | tg3_full_unlock(tp); | |
8903 | ||
8904 | goto err_out2; | |
8905 | } | |
8906 | ||
8907 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
8908 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && | |
8909 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI) && | |
8910 | (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) { | |
8911 | u32 val = tr32(PCIE_TRANSACTION_CFG); | |
8912 | ||
8913 | tw32(PCIE_TRANSACTION_CFG, | |
8914 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
8915 | } | |
8916 | } | |
8917 | ||
8918 | tg3_phy_start(tp); | |
8919 | ||
8920 | tg3_full_lock(tp, 0); | |
8921 | ||
8922 | add_timer(&tp->timer); | |
8923 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
8924 | tg3_enable_ints(tp); | |
8925 | ||
8926 | tg3_full_unlock(tp); | |
8927 | ||
8928 | netif_tx_start_all_queues(dev); | |
8929 | ||
8930 | return 0; | |
8931 | ||
8932 | err_out3: | |
8933 | for (i = tp->irq_cnt - 1; i >= 0; i--) { | |
8934 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8935 | free_irq(tnapi->irq_vec, tnapi); | |
8936 | } | |
8937 | ||
8938 | err_out2: | |
8939 | tg3_napi_disable(tp); | |
8940 | tg3_free_consistent(tp); | |
8941 | ||
8942 | err_out1: | |
8943 | tg3_ints_fini(tp); | |
8944 | return err; | |
8945 | } | |
8946 | ||
8947 | #if 0 | |
8948 | /*static*/ void tg3_dump_state(struct tg3 *tp) | |
8949 | { | |
8950 | u32 val32, val32_2, val32_3, val32_4, val32_5; | |
8951 | u16 val16; | |
8952 | int i; | |
8953 | struct tg3_hw_status *sblk = tp->napi[0]->hw_status; | |
8954 | ||
8955 | pci_read_config_word(tp->pdev, PCI_STATUS, &val16); | |
8956 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32); | |
8957 | printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n", | |
8958 | val16, val32); | |
8959 | ||
8960 | /* MAC block */ | |
8961 | printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n", | |
8962 | tr32(MAC_MODE), tr32(MAC_STATUS)); | |
8963 | printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n", | |
8964 | tr32(MAC_EVENT), tr32(MAC_LED_CTRL)); | |
8965 | printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n", | |
8966 | tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS)); | |
8967 | printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n", | |
8968 | tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS)); | |
8969 | ||
8970 | /* Send data initiator control block */ | |
8971 | printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n", | |
8972 | tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS)); | |
8973 | printk(" SNDDATAI_STATSCTRL[%08x]\n", | |
8974 | tr32(SNDDATAI_STATSCTRL)); | |
8975 | ||
8976 | /* Send data completion control block */ | |
8977 | printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE)); | |
8978 | ||
8979 | /* Send BD ring selector block */ | |
8980 | printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n", | |
8981 | tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS)); | |
8982 | ||
8983 | /* Send BD initiator control block */ | |
8984 | printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n", | |
8985 | tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS)); | |
8986 | ||
8987 | /* Send BD completion control block */ | |
8988 | printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE)); | |
8989 | ||
8990 | /* Receive list placement control block */ | |
8991 | printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n", | |
8992 | tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS)); | |
8993 | printk(" RCVLPC_STATSCTRL[%08x]\n", | |
8994 | tr32(RCVLPC_STATSCTRL)); | |
8995 | ||
8996 | /* Receive data and receive BD initiator control block */ | |
8997 | printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n", | |
8998 | tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS)); | |
8999 | ||
9000 | /* Receive data completion control block */ | |
9001 | printk("DEBUG: RCVDCC_MODE[%08x]\n", | |
9002 | tr32(RCVDCC_MODE)); | |
9003 | ||
9004 | /* Receive BD initiator control block */ | |
9005 | printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n", | |
9006 | tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS)); | |
9007 | ||
9008 | /* Receive BD completion control block */ | |
9009 | printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n", | |
9010 | tr32(RCVCC_MODE), tr32(RCVCC_STATUS)); | |
9011 | ||
9012 | /* Receive list selector control block */ | |
9013 | printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n", | |
9014 | tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS)); | |
9015 | ||
9016 | /* Mbuf cluster free block */ | |
9017 | printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n", | |
9018 | tr32(MBFREE_MODE), tr32(MBFREE_STATUS)); | |
9019 | ||
9020 | /* Host coalescing control block */ | |
9021 | printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n", | |
9022 | tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS)); | |
9023 | printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n", | |
9024 | tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
9025 | tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW)); | |
9026 | printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n", | |
9027 | tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
9028 | tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW)); | |
9029 | printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n", | |
9030 | tr32(HOSTCC_STATS_BLK_NIC_ADDR)); | |
9031 | printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n", | |
9032 | tr32(HOSTCC_STATUS_BLK_NIC_ADDR)); | |
9033 | ||
9034 | /* Memory arbiter control block */ | |
9035 | printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n", | |
9036 | tr32(MEMARB_MODE), tr32(MEMARB_STATUS)); | |
9037 | ||
9038 | /* Buffer manager control block */ | |
9039 | printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n", | |
9040 | tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS)); | |
9041 | printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n", | |
9042 | tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE)); | |
9043 | printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] " | |
9044 | "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n", | |
9045 | tr32(BUFMGR_DMA_DESC_POOL_ADDR), | |
9046 | tr32(BUFMGR_DMA_DESC_POOL_SIZE)); | |
9047 | ||
9048 | /* Read DMA control block */ | |
9049 | printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n", | |
9050 | tr32(RDMAC_MODE), tr32(RDMAC_STATUS)); | |
9051 | ||
9052 | /* Write DMA control block */ | |
9053 | printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n", | |
9054 | tr32(WDMAC_MODE), tr32(WDMAC_STATUS)); | |
9055 | ||
9056 | /* DMA completion block */ | |
9057 | printk("DEBUG: DMAC_MODE[%08x]\n", | |
9058 | tr32(DMAC_MODE)); | |
9059 | ||
9060 | /* GRC block */ | |
9061 | printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n", | |
9062 | tr32(GRC_MODE), tr32(GRC_MISC_CFG)); | |
9063 | printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n", | |
9064 | tr32(GRC_LOCAL_CTRL)); | |
9065 | ||
9066 | /* TG3_BDINFOs */ | |
9067 | printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n", | |
9068 | tr32(RCVDBDI_JUMBO_BD + 0x0), | |
9069 | tr32(RCVDBDI_JUMBO_BD + 0x4), | |
9070 | tr32(RCVDBDI_JUMBO_BD + 0x8), | |
9071 | tr32(RCVDBDI_JUMBO_BD + 0xc)); | |
9072 | printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n", | |
9073 | tr32(RCVDBDI_STD_BD + 0x0), | |
9074 | tr32(RCVDBDI_STD_BD + 0x4), | |
9075 | tr32(RCVDBDI_STD_BD + 0x8), | |
9076 | tr32(RCVDBDI_STD_BD + 0xc)); | |
9077 | printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n", | |
9078 | tr32(RCVDBDI_MINI_BD + 0x0), | |
9079 | tr32(RCVDBDI_MINI_BD + 0x4), | |
9080 | tr32(RCVDBDI_MINI_BD + 0x8), | |
9081 | tr32(RCVDBDI_MINI_BD + 0xc)); | |
9082 | ||
9083 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32); | |
9084 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2); | |
9085 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3); | |
9086 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4); | |
9087 | printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n", | |
9088 | val32, val32_2, val32_3, val32_4); | |
9089 | ||
9090 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32); | |
9091 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2); | |
9092 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3); | |
9093 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4); | |
9094 | printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n", | |
9095 | val32, val32_2, val32_3, val32_4); | |
9096 | ||
9097 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32); | |
9098 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2); | |
9099 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3); | |
9100 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4); | |
9101 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5); | |
9102 | printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n", | |
9103 | val32, val32_2, val32_3, val32_4, val32_5); | |
9104 | ||
9105 | /* SW status block */ | |
9106 | printk(KERN_DEBUG | |
9107 | "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
9108 | sblk->status, | |
9109 | sblk->status_tag, | |
9110 | sblk->rx_jumbo_consumer, | |
9111 | sblk->rx_consumer, | |
9112 | sblk->rx_mini_consumer, | |
9113 | sblk->idx[0].rx_producer, | |
9114 | sblk->idx[0].tx_consumer); | |
9115 | ||
9116 | /* SW statistics block */ | |
9117 | printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n", | |
9118 | ((u32 *)tp->hw_stats)[0], | |
9119 | ((u32 *)tp->hw_stats)[1], | |
9120 | ((u32 *)tp->hw_stats)[2], | |
9121 | ((u32 *)tp->hw_stats)[3]); | |
9122 | ||
9123 | /* Mailboxes */ | |
9124 | printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n", | |
9125 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0), | |
9126 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4), | |
9127 | tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0), | |
9128 | tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4)); | |
9129 | ||
9130 | /* NIC side send descriptors. */ | |
9131 | for (i = 0; i < 6; i++) { | |
9132 | unsigned long txd; | |
9133 | ||
9134 | txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC | |
9135 | + (i * sizeof(struct tg3_tx_buffer_desc)); | |
9136 | printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n", | |
9137 | i, | |
9138 | readl(txd + 0x0), readl(txd + 0x4), | |
9139 | readl(txd + 0x8), readl(txd + 0xc)); | |
9140 | } | |
9141 | ||
9142 | /* NIC side RX descriptors. */ | |
9143 | for (i = 0; i < 6; i++) { | |
9144 | unsigned long rxd; | |
9145 | ||
9146 | rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC | |
9147 | + (i * sizeof(struct tg3_rx_buffer_desc)); | |
9148 | printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n", | |
9149 | i, | |
9150 | readl(rxd + 0x0), readl(rxd + 0x4), | |
9151 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
9152 | rxd += (4 * sizeof(u32)); | |
9153 | printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n", | |
9154 | i, | |
9155 | readl(rxd + 0x0), readl(rxd + 0x4), | |
9156 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
9157 | } | |
9158 | ||
9159 | for (i = 0; i < 6; i++) { | |
9160 | unsigned long rxd; | |
9161 | ||
9162 | rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC | |
9163 | + (i * sizeof(struct tg3_rx_buffer_desc)); | |
9164 | printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n", | |
9165 | i, | |
9166 | readl(rxd + 0x0), readl(rxd + 0x4), | |
9167 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
9168 | rxd += (4 * sizeof(u32)); | |
9169 | printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n", | |
9170 | i, | |
9171 | readl(rxd + 0x0), readl(rxd + 0x4), | |
9172 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
9173 | } | |
9174 | } | |
9175 | #endif | |
9176 | ||
9177 | static struct net_device_stats *tg3_get_stats(struct net_device *); | |
9178 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); | |
9179 | ||
9180 | static int tg3_close(struct net_device *dev) | |
9181 | { | |
9182 | int i; | |
9183 | struct tg3 *tp = netdev_priv(dev); | |
9184 | ||
9185 | tg3_napi_disable(tp); | |
9186 | cancel_work_sync(&tp->reset_task); | |
9187 | ||
9188 | netif_tx_stop_all_queues(dev); | |
9189 | ||
9190 | del_timer_sync(&tp->timer); | |
9191 | ||
9192 | tg3_phy_stop(tp); | |
9193 | ||
9194 | tg3_full_lock(tp, 1); | |
9195 | #if 0 | |
9196 | tg3_dump_state(tp); | |
9197 | #endif | |
9198 | ||
9199 | tg3_disable_ints(tp); | |
9200 | ||
9201 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9202 | tg3_free_rings(tp); | |
9203 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
9204 | ||
9205 | tg3_full_unlock(tp); | |
9206 | ||
9207 | for (i = tp->irq_cnt - 1; i >= 0; i--) { | |
9208 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9209 | free_irq(tnapi->irq_vec, tnapi); | |
9210 | } | |
9211 | ||
9212 | tg3_ints_fini(tp); | |
9213 | ||
9214 | memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev), | |
9215 | sizeof(tp->net_stats_prev)); | |
9216 | memcpy(&tp->estats_prev, tg3_get_estats(tp), | |
9217 | sizeof(tp->estats_prev)); | |
9218 | ||
9219 | tg3_free_consistent(tp); | |
9220 | ||
9221 | tg3_set_power_state(tp, PCI_D3hot); | |
9222 | ||
9223 | netif_carrier_off(tp->dev); | |
9224 | ||
9225 | return 0; | |
9226 | } | |
9227 | ||
9228 | static inline unsigned long get_stat64(tg3_stat64_t *val) | |
9229 | { | |
9230 | unsigned long ret; | |
9231 | ||
9232 | #if (BITS_PER_LONG == 32) | |
9233 | ret = val->low; | |
9234 | #else | |
9235 | ret = ((u64)val->high << 32) | ((u64)val->low); | |
9236 | #endif | |
9237 | return ret; | |
9238 | } | |
9239 | ||
9240 | static inline u64 get_estat64(tg3_stat64_t *val) | |
9241 | { | |
9242 | return ((u64)val->high << 32) | ((u64)val->low); | |
9243 | } | |
9244 | ||
9245 | static unsigned long calc_crc_errors(struct tg3 *tp) | |
9246 | { | |
9247 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9248 | ||
9249 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
9250 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
9251 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
9252 | u32 val; | |
9253 | ||
9254 | spin_lock_bh(&tp->lock); | |
9255 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { | |
9256 | tg3_writephy(tp, MII_TG3_TEST1, | |
9257 | val | MII_TG3_TEST1_CRC_EN); | |
9258 | tg3_readphy(tp, 0x14, &val); | |
9259 | } else | |
9260 | val = 0; | |
9261 | spin_unlock_bh(&tp->lock); | |
9262 | ||
9263 | tp->phy_crc_errors += val; | |
9264 | ||
9265 | return tp->phy_crc_errors; | |
9266 | } | |
9267 | ||
9268 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9269 | } | |
9270 | ||
9271 | #define ESTAT_ADD(member) \ | |
9272 | estats->member = old_estats->member + \ | |
9273 | get_estat64(&hw_stats->member) | |
9274 | ||
9275 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9276 | { | |
9277 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9278 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9279 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9280 | ||
9281 | if (!hw_stats) | |
9282 | return old_estats; | |
9283 | ||
9284 | ESTAT_ADD(rx_octets); | |
9285 | ESTAT_ADD(rx_fragments); | |
9286 | ESTAT_ADD(rx_ucast_packets); | |
9287 | ESTAT_ADD(rx_mcast_packets); | |
9288 | ESTAT_ADD(rx_bcast_packets); | |
9289 | ESTAT_ADD(rx_fcs_errors); | |
9290 | ESTAT_ADD(rx_align_errors); | |
9291 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9292 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9293 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9294 | ESTAT_ADD(rx_xoff_entered); | |
9295 | ESTAT_ADD(rx_frame_too_long_errors); | |
9296 | ESTAT_ADD(rx_jabbers); | |
9297 | ESTAT_ADD(rx_undersize_packets); | |
9298 | ESTAT_ADD(rx_in_length_errors); | |
9299 | ESTAT_ADD(rx_out_length_errors); | |
9300 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9301 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9302 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9303 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9304 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9305 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9306 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9307 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9308 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9309 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9310 | ||
9311 | ESTAT_ADD(tx_octets); | |
9312 | ESTAT_ADD(tx_collisions); | |
9313 | ESTAT_ADD(tx_xon_sent); | |
9314 | ESTAT_ADD(tx_xoff_sent); | |
9315 | ESTAT_ADD(tx_flow_control); | |
9316 | ESTAT_ADD(tx_mac_errors); | |
9317 | ESTAT_ADD(tx_single_collisions); | |
9318 | ESTAT_ADD(tx_mult_collisions); | |
9319 | ESTAT_ADD(tx_deferred); | |
9320 | ESTAT_ADD(tx_excessive_collisions); | |
9321 | ESTAT_ADD(tx_late_collisions); | |
9322 | ESTAT_ADD(tx_collide_2times); | |
9323 | ESTAT_ADD(tx_collide_3times); | |
9324 | ESTAT_ADD(tx_collide_4times); | |
9325 | ESTAT_ADD(tx_collide_5times); | |
9326 | ESTAT_ADD(tx_collide_6times); | |
9327 | ESTAT_ADD(tx_collide_7times); | |
9328 | ESTAT_ADD(tx_collide_8times); | |
9329 | ESTAT_ADD(tx_collide_9times); | |
9330 | ESTAT_ADD(tx_collide_10times); | |
9331 | ESTAT_ADD(tx_collide_11times); | |
9332 | ESTAT_ADD(tx_collide_12times); | |
9333 | ESTAT_ADD(tx_collide_13times); | |
9334 | ESTAT_ADD(tx_collide_14times); | |
9335 | ESTAT_ADD(tx_collide_15times); | |
9336 | ESTAT_ADD(tx_ucast_packets); | |
9337 | ESTAT_ADD(tx_mcast_packets); | |
9338 | ESTAT_ADD(tx_bcast_packets); | |
9339 | ESTAT_ADD(tx_carrier_sense_errors); | |
9340 | ESTAT_ADD(tx_discards); | |
9341 | ESTAT_ADD(tx_errors); | |
9342 | ||
9343 | ESTAT_ADD(dma_writeq_full); | |
9344 | ESTAT_ADD(dma_write_prioq_full); | |
9345 | ESTAT_ADD(rxbds_empty); | |
9346 | ESTAT_ADD(rx_discards); | |
9347 | ESTAT_ADD(rx_errors); | |
9348 | ESTAT_ADD(rx_threshold_hit); | |
9349 | ||
9350 | ESTAT_ADD(dma_readq_full); | |
9351 | ESTAT_ADD(dma_read_prioq_full); | |
9352 | ESTAT_ADD(tx_comp_queue_full); | |
9353 | ||
9354 | ESTAT_ADD(ring_set_send_prod_index); | |
9355 | ESTAT_ADD(ring_status_update); | |
9356 | ESTAT_ADD(nic_irqs); | |
9357 | ESTAT_ADD(nic_avoided_irqs); | |
9358 | ESTAT_ADD(nic_tx_threshold_hit); | |
9359 | ||
9360 | return estats; | |
9361 | } | |
9362 | ||
9363 | static struct net_device_stats *tg3_get_stats(struct net_device *dev) | |
9364 | { | |
9365 | struct tg3 *tp = netdev_priv(dev); | |
9366 | struct net_device_stats *stats = &tp->net_stats; | |
9367 | struct net_device_stats *old_stats = &tp->net_stats_prev; | |
9368 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9369 | ||
9370 | if (!hw_stats) | |
9371 | return old_stats; | |
9372 | ||
9373 | stats->rx_packets = old_stats->rx_packets + | |
9374 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9375 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9376 | get_stat64(&hw_stats->rx_bcast_packets); | |
9377 | ||
9378 | stats->tx_packets = old_stats->tx_packets + | |
9379 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9380 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9381 | get_stat64(&hw_stats->tx_bcast_packets); | |
9382 | ||
9383 | stats->rx_bytes = old_stats->rx_bytes + | |
9384 | get_stat64(&hw_stats->rx_octets); | |
9385 | stats->tx_bytes = old_stats->tx_bytes + | |
9386 | get_stat64(&hw_stats->tx_octets); | |
9387 | ||
9388 | stats->rx_errors = old_stats->rx_errors + | |
9389 | get_stat64(&hw_stats->rx_errors); | |
9390 | stats->tx_errors = old_stats->tx_errors + | |
9391 | get_stat64(&hw_stats->tx_errors) + | |
9392 | get_stat64(&hw_stats->tx_mac_errors) + | |
9393 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9394 | get_stat64(&hw_stats->tx_discards); | |
9395 | ||
9396 | stats->multicast = old_stats->multicast + | |
9397 | get_stat64(&hw_stats->rx_mcast_packets); | |
9398 | stats->collisions = old_stats->collisions + | |
9399 | get_stat64(&hw_stats->tx_collisions); | |
9400 | ||
9401 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9402 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9403 | get_stat64(&hw_stats->rx_undersize_packets); | |
9404 | ||
9405 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9406 | get_stat64(&hw_stats->rxbds_empty); | |
9407 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9408 | get_stat64(&hw_stats->rx_align_errors); | |
9409 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9410 | get_stat64(&hw_stats->tx_discards); | |
9411 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9412 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9413 | ||
9414 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9415 | calc_crc_errors(tp); | |
9416 | ||
9417 | stats->rx_missed_errors = old_stats->rx_missed_errors + | |
9418 | get_stat64(&hw_stats->rx_discards); | |
9419 | ||
9420 | return stats; | |
9421 | } | |
9422 | ||
9423 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9424 | { | |
9425 | u32 reg; | |
9426 | u32 tmp; | |
9427 | int j, k; | |
9428 | ||
9429 | reg = 0xffffffff; | |
9430 | ||
9431 | for (j = 0; j < len; j++) { | |
9432 | reg ^= buf[j]; | |
9433 | ||
9434 | for (k = 0; k < 8; k++) { | |
9435 | tmp = reg & 0x01; | |
9436 | ||
9437 | reg >>= 1; | |
9438 | ||
9439 | if (tmp) { | |
9440 | reg ^= 0xedb88320; | |
9441 | } | |
9442 | } | |
9443 | } | |
9444 | ||
9445 | return ~reg; | |
9446 | } | |
9447 | ||
9448 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9449 | { | |
9450 | /* accept or reject all multicast frames */ | |
9451 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9452 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9453 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9454 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9455 | } | |
9456 | ||
9457 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9458 | { | |
9459 | struct tg3 *tp = netdev_priv(dev); | |
9460 | u32 rx_mode; | |
9461 | ||
9462 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9463 | RX_MODE_KEEP_VLAN_TAG); | |
9464 | ||
9465 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG | |
9466 | * flag clear. | |
9467 | */ | |
9468 | #if TG3_VLAN_TAG_USED | |
9469 | if (!tp->vlgrp && | |
9470 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
9471 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9472 | #else | |
9473 | /* By definition, VLAN is disabled always in this | |
9474 | * case. | |
9475 | */ | |
9476 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
9477 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9478 | #endif | |
9479 | ||
9480 | if (dev->flags & IFF_PROMISC) { | |
9481 | /* Promiscuous mode. */ | |
9482 | rx_mode |= RX_MODE_PROMISC; | |
9483 | } else if (dev->flags & IFF_ALLMULTI) { | |
9484 | /* Accept all multicast. */ | |
9485 | tg3_set_multi (tp, 1); | |
9486 | } else if (netdev_mc_empty(dev)) { | |
9487 | /* Reject all multicast. */ | |
9488 | tg3_set_multi (tp, 0); | |
9489 | } else { | |
9490 | /* Accept one or more multicast(s). */ | |
9491 | struct dev_mc_list *mclist; | |
9492 | unsigned int i; | |
9493 | u32 mc_filter[4] = { 0, }; | |
9494 | u32 regidx; | |
9495 | u32 bit; | |
9496 | u32 crc; | |
9497 | ||
9498 | for (i = 0, mclist = dev->mc_list; mclist && i < netdev_mc_count(dev); | |
9499 | i++, mclist = mclist->next) { | |
9500 | ||
9501 | crc = calc_crc (mclist->dmi_addr, ETH_ALEN); | |
9502 | bit = ~crc & 0x7f; | |
9503 | regidx = (bit & 0x60) >> 5; | |
9504 | bit &= 0x1f; | |
9505 | mc_filter[regidx] |= (1 << bit); | |
9506 | } | |
9507 | ||
9508 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9509 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9510 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9511 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9512 | } | |
9513 | ||
9514 | if (rx_mode != tp->rx_mode) { | |
9515 | tp->rx_mode = rx_mode; | |
9516 | tw32_f(MAC_RX_MODE, rx_mode); | |
9517 | udelay(10); | |
9518 | } | |
9519 | } | |
9520 | ||
9521 | static void tg3_set_rx_mode(struct net_device *dev) | |
9522 | { | |
9523 | struct tg3 *tp = netdev_priv(dev); | |
9524 | ||
9525 | if (!netif_running(dev)) | |
9526 | return; | |
9527 | ||
9528 | tg3_full_lock(tp, 0); | |
9529 | __tg3_set_rx_mode(dev); | |
9530 | tg3_full_unlock(tp); | |
9531 | } | |
9532 | ||
9533 | #define TG3_REGDUMP_LEN (32 * 1024) | |
9534 | ||
9535 | static int tg3_get_regs_len(struct net_device *dev) | |
9536 | { | |
9537 | return TG3_REGDUMP_LEN; | |
9538 | } | |
9539 | ||
9540 | static void tg3_get_regs(struct net_device *dev, | |
9541 | struct ethtool_regs *regs, void *_p) | |
9542 | { | |
9543 | u32 *p = _p; | |
9544 | struct tg3 *tp = netdev_priv(dev); | |
9545 | u8 *orig_p = _p; | |
9546 | int i; | |
9547 | ||
9548 | regs->version = 0; | |
9549 | ||
9550 | memset(p, 0, TG3_REGDUMP_LEN); | |
9551 | ||
9552 | if (tp->link_config.phy_is_low_power) | |
9553 | return; | |
9554 | ||
9555 | tg3_full_lock(tp, 0); | |
9556 | ||
9557 | #define __GET_REG32(reg) (*(p)++ = tr32(reg)) | |
9558 | #define GET_REG32_LOOP(base,len) \ | |
9559 | do { p = (u32 *)(orig_p + (base)); \ | |
9560 | for (i = 0; i < len; i += 4) \ | |
9561 | __GET_REG32((base) + i); \ | |
9562 | } while (0) | |
9563 | #define GET_REG32_1(reg) \ | |
9564 | do { p = (u32 *)(orig_p + (reg)); \ | |
9565 | __GET_REG32((reg)); \ | |
9566 | } while (0) | |
9567 | ||
9568 | GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0); | |
9569 | GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200); | |
9570 | GET_REG32_LOOP(MAC_MODE, 0x4f0); | |
9571 | GET_REG32_LOOP(SNDDATAI_MODE, 0xe0); | |
9572 | GET_REG32_1(SNDDATAC_MODE); | |
9573 | GET_REG32_LOOP(SNDBDS_MODE, 0x80); | |
9574 | GET_REG32_LOOP(SNDBDI_MODE, 0x48); | |
9575 | GET_REG32_1(SNDBDC_MODE); | |
9576 | GET_REG32_LOOP(RCVLPC_MODE, 0x20); | |
9577 | GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c); | |
9578 | GET_REG32_LOOP(RCVDBDI_MODE, 0x0c); | |
9579 | GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c); | |
9580 | GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44); | |
9581 | GET_REG32_1(RCVDCC_MODE); | |
9582 | GET_REG32_LOOP(RCVBDI_MODE, 0x20); | |
9583 | GET_REG32_LOOP(RCVCC_MODE, 0x14); | |
9584 | GET_REG32_LOOP(RCVLSC_MODE, 0x08); | |
9585 | GET_REG32_1(MBFREE_MODE); | |
9586 | GET_REG32_LOOP(HOSTCC_MODE, 0x100); | |
9587 | GET_REG32_LOOP(MEMARB_MODE, 0x10); | |
9588 | GET_REG32_LOOP(BUFMGR_MODE, 0x58); | |
9589 | GET_REG32_LOOP(RDMAC_MODE, 0x08); | |
9590 | GET_REG32_LOOP(WDMAC_MODE, 0x08); | |
9591 | GET_REG32_1(RX_CPU_MODE); | |
9592 | GET_REG32_1(RX_CPU_STATE); | |
9593 | GET_REG32_1(RX_CPU_PGMCTR); | |
9594 | GET_REG32_1(RX_CPU_HWBKPT); | |
9595 | GET_REG32_1(TX_CPU_MODE); | |
9596 | GET_REG32_1(TX_CPU_STATE); | |
9597 | GET_REG32_1(TX_CPU_PGMCTR); | |
9598 | GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110); | |
9599 | GET_REG32_LOOP(FTQ_RESET, 0x120); | |
9600 | GET_REG32_LOOP(MSGINT_MODE, 0x0c); | |
9601 | GET_REG32_1(DMAC_MODE); | |
9602 | GET_REG32_LOOP(GRC_MODE, 0x4c); | |
9603 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
9604 | GET_REG32_LOOP(NVRAM_CMD, 0x24); | |
9605 | ||
9606 | #undef __GET_REG32 | |
9607 | #undef GET_REG32_LOOP | |
9608 | #undef GET_REG32_1 | |
9609 | ||
9610 | tg3_full_unlock(tp); | |
9611 | } | |
9612 | ||
9613 | static int tg3_get_eeprom_len(struct net_device *dev) | |
9614 | { | |
9615 | struct tg3 *tp = netdev_priv(dev); | |
9616 | ||
9617 | return tp->nvram_size; | |
9618 | } | |
9619 | ||
9620 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9621 | { | |
9622 | struct tg3 *tp = netdev_priv(dev); | |
9623 | int ret; | |
9624 | u8 *pd; | |
9625 | u32 i, offset, len, b_offset, b_count; | |
9626 | __be32 val; | |
9627 | ||
9628 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) | |
9629 | return -EINVAL; | |
9630 | ||
9631 | if (tp->link_config.phy_is_low_power) | |
9632 | return -EAGAIN; | |
9633 | ||
9634 | offset = eeprom->offset; | |
9635 | len = eeprom->len; | |
9636 | eeprom->len = 0; | |
9637 | ||
9638 | eeprom->magic = TG3_EEPROM_MAGIC; | |
9639 | ||
9640 | if (offset & 3) { | |
9641 | /* adjustments to start on required 4 byte boundary */ | |
9642 | b_offset = offset & 3; | |
9643 | b_count = 4 - b_offset; | |
9644 | if (b_count > len) { | |
9645 | /* i.e. offset=1 len=2 */ | |
9646 | b_count = len; | |
9647 | } | |
9648 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); | |
9649 | if (ret) | |
9650 | return ret; | |
9651 | memcpy(data, ((char*)&val) + b_offset, b_count); | |
9652 | len -= b_count; | |
9653 | offset += b_count; | |
9654 | eeprom->len += b_count; | |
9655 | } | |
9656 | ||
9657 | /* read bytes upto the last 4 byte boundary */ | |
9658 | pd = &data[eeprom->len]; | |
9659 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
9660 | ret = tg3_nvram_read_be32(tp, offset + i, &val); | |
9661 | if (ret) { | |
9662 | eeprom->len += i; | |
9663 | return ret; | |
9664 | } | |
9665 | memcpy(pd + i, &val, 4); | |
9666 | } | |
9667 | eeprom->len += i; | |
9668 | ||
9669 | if (len & 3) { | |
9670 | /* read last bytes not ending on 4 byte boundary */ | |
9671 | pd = &data[eeprom->len]; | |
9672 | b_count = len & 3; | |
9673 | b_offset = offset + len - b_count; | |
9674 | ret = tg3_nvram_read_be32(tp, b_offset, &val); | |
9675 | if (ret) | |
9676 | return ret; | |
9677 | memcpy(pd, &val, b_count); | |
9678 | eeprom->len += b_count; | |
9679 | } | |
9680 | return 0; | |
9681 | } | |
9682 | ||
9683 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); | |
9684 | ||
9685 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9686 | { | |
9687 | struct tg3 *tp = netdev_priv(dev); | |
9688 | int ret; | |
9689 | u32 offset, len, b_offset, odd_len; | |
9690 | u8 *buf; | |
9691 | __be32 start, end; | |
9692 | ||
9693 | if (tp->link_config.phy_is_low_power) | |
9694 | return -EAGAIN; | |
9695 | ||
9696 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || | |
9697 | eeprom->magic != TG3_EEPROM_MAGIC) | |
9698 | return -EINVAL; | |
9699 | ||
9700 | offset = eeprom->offset; | |
9701 | len = eeprom->len; | |
9702 | ||
9703 | if ((b_offset = (offset & 3))) { | |
9704 | /* adjustments to start on required 4 byte boundary */ | |
9705 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); | |
9706 | if (ret) | |
9707 | return ret; | |
9708 | len += b_offset; | |
9709 | offset &= ~3; | |
9710 | if (len < 4) | |
9711 | len = 4; | |
9712 | } | |
9713 | ||
9714 | odd_len = 0; | |
9715 | if (len & 3) { | |
9716 | /* adjustments to end on required 4 byte boundary */ | |
9717 | odd_len = 1; | |
9718 | len = (len + 3) & ~3; | |
9719 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); | |
9720 | if (ret) | |
9721 | return ret; | |
9722 | } | |
9723 | ||
9724 | buf = data; | |
9725 | if (b_offset || odd_len) { | |
9726 | buf = kmalloc(len, GFP_KERNEL); | |
9727 | if (!buf) | |
9728 | return -ENOMEM; | |
9729 | if (b_offset) | |
9730 | memcpy(buf, &start, 4); | |
9731 | if (odd_len) | |
9732 | memcpy(buf+len-4, &end, 4); | |
9733 | memcpy(buf + b_offset, data, eeprom->len); | |
9734 | } | |
9735 | ||
9736 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
9737 | ||
9738 | if (buf != data) | |
9739 | kfree(buf); | |
9740 | ||
9741 | return ret; | |
9742 | } | |
9743 | ||
9744 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9745 | { | |
9746 | struct tg3 *tp = netdev_priv(dev); | |
9747 | ||
9748 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
9749 | struct phy_device *phydev; | |
9750 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
9751 | return -EAGAIN; | |
9752 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
9753 | return phy_ethtool_gset(phydev, cmd); | |
9754 | } | |
9755 | ||
9756 | cmd->supported = (SUPPORTED_Autoneg); | |
9757 | ||
9758 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
9759 | cmd->supported |= (SUPPORTED_1000baseT_Half | | |
9760 | SUPPORTED_1000baseT_Full); | |
9761 | ||
9762 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { | |
9763 | cmd->supported |= (SUPPORTED_100baseT_Half | | |
9764 | SUPPORTED_100baseT_Full | | |
9765 | SUPPORTED_10baseT_Half | | |
9766 | SUPPORTED_10baseT_Full | | |
9767 | SUPPORTED_TP); | |
9768 | cmd->port = PORT_TP; | |
9769 | } else { | |
9770 | cmd->supported |= SUPPORTED_FIBRE; | |
9771 | cmd->port = PORT_FIBRE; | |
9772 | } | |
9773 | ||
9774 | cmd->advertising = tp->link_config.advertising; | |
9775 | if (netif_running(dev)) { | |
9776 | cmd->speed = tp->link_config.active_speed; | |
9777 | cmd->duplex = tp->link_config.active_duplex; | |
9778 | } | |
9779 | cmd->phy_address = tp->phy_addr; | |
9780 | cmd->transceiver = XCVR_INTERNAL; | |
9781 | cmd->autoneg = tp->link_config.autoneg; | |
9782 | cmd->maxtxpkt = 0; | |
9783 | cmd->maxrxpkt = 0; | |
9784 | return 0; | |
9785 | } | |
9786 | ||
9787 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9788 | { | |
9789 | struct tg3 *tp = netdev_priv(dev); | |
9790 | ||
9791 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
9792 | struct phy_device *phydev; | |
9793 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
9794 | return -EAGAIN; | |
9795 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
9796 | return phy_ethtool_sset(phydev, cmd); | |
9797 | } | |
9798 | ||
9799 | if (cmd->autoneg != AUTONEG_ENABLE && | |
9800 | cmd->autoneg != AUTONEG_DISABLE) | |
9801 | return -EINVAL; | |
9802 | ||
9803 | if (cmd->autoneg == AUTONEG_DISABLE && | |
9804 | cmd->duplex != DUPLEX_FULL && | |
9805 | cmd->duplex != DUPLEX_HALF) | |
9806 | return -EINVAL; | |
9807 | ||
9808 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
9809 | u32 mask = ADVERTISED_Autoneg | | |
9810 | ADVERTISED_Pause | | |
9811 | ADVERTISED_Asym_Pause; | |
9812 | ||
9813 | if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY)) | |
9814 | mask |= ADVERTISED_1000baseT_Half | | |
9815 | ADVERTISED_1000baseT_Full; | |
9816 | ||
9817 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
9818 | mask |= ADVERTISED_100baseT_Half | | |
9819 | ADVERTISED_100baseT_Full | | |
9820 | ADVERTISED_10baseT_Half | | |
9821 | ADVERTISED_10baseT_Full | | |
9822 | ADVERTISED_TP; | |
9823 | else | |
9824 | mask |= ADVERTISED_FIBRE; | |
9825 | ||
9826 | if (cmd->advertising & ~mask) | |
9827 | return -EINVAL; | |
9828 | ||
9829 | mask &= (ADVERTISED_1000baseT_Half | | |
9830 | ADVERTISED_1000baseT_Full | | |
9831 | ADVERTISED_100baseT_Half | | |
9832 | ADVERTISED_100baseT_Full | | |
9833 | ADVERTISED_10baseT_Half | | |
9834 | ADVERTISED_10baseT_Full); | |
9835 | ||
9836 | cmd->advertising &= mask; | |
9837 | } else { | |
9838 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { | |
9839 | if (cmd->speed != SPEED_1000) | |
9840 | return -EINVAL; | |
9841 | ||
9842 | if (cmd->duplex != DUPLEX_FULL) | |
9843 | return -EINVAL; | |
9844 | } else { | |
9845 | if (cmd->speed != SPEED_100 && | |
9846 | cmd->speed != SPEED_10) | |
9847 | return -EINVAL; | |
9848 | } | |
9849 | } | |
9850 | ||
9851 | tg3_full_lock(tp, 0); | |
9852 | ||
9853 | tp->link_config.autoneg = cmd->autoneg; | |
9854 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
9855 | tp->link_config.advertising = (cmd->advertising | | |
9856 | ADVERTISED_Autoneg); | |
9857 | tp->link_config.speed = SPEED_INVALID; | |
9858 | tp->link_config.duplex = DUPLEX_INVALID; | |
9859 | } else { | |
9860 | tp->link_config.advertising = 0; | |
9861 | tp->link_config.speed = cmd->speed; | |
9862 | tp->link_config.duplex = cmd->duplex; | |
9863 | } | |
9864 | ||
9865 | tp->link_config.orig_speed = tp->link_config.speed; | |
9866 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
9867 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
9868 | ||
9869 | if (netif_running(dev)) | |
9870 | tg3_setup_phy(tp, 1); | |
9871 | ||
9872 | tg3_full_unlock(tp); | |
9873 | ||
9874 | return 0; | |
9875 | } | |
9876 | ||
9877 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
9878 | { | |
9879 | struct tg3 *tp = netdev_priv(dev); | |
9880 | ||
9881 | strcpy(info->driver, DRV_MODULE_NAME); | |
9882 | strcpy(info->version, DRV_MODULE_VERSION); | |
9883 | strcpy(info->fw_version, tp->fw_ver); | |
9884 | strcpy(info->bus_info, pci_name(tp->pdev)); | |
9885 | } | |
9886 | ||
9887 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
9888 | { | |
9889 | struct tg3 *tp = netdev_priv(dev); | |
9890 | ||
9891 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && | |
9892 | device_can_wakeup(&tp->pdev->dev)) | |
9893 | wol->supported = WAKE_MAGIC; | |
9894 | else | |
9895 | wol->supported = 0; | |
9896 | wol->wolopts = 0; | |
9897 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && | |
9898 | device_can_wakeup(&tp->pdev->dev)) | |
9899 | wol->wolopts = WAKE_MAGIC; | |
9900 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
9901 | } | |
9902 | ||
9903 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
9904 | { | |
9905 | struct tg3 *tp = netdev_priv(dev); | |
9906 | struct device *dp = &tp->pdev->dev; | |
9907 | ||
9908 | if (wol->wolopts & ~WAKE_MAGIC) | |
9909 | return -EINVAL; | |
9910 | if ((wol->wolopts & WAKE_MAGIC) && | |
9911 | !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp))) | |
9912 | return -EINVAL; | |
9913 | ||
9914 | spin_lock_bh(&tp->lock); | |
9915 | if (wol->wolopts & WAKE_MAGIC) { | |
9916 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; | |
9917 | device_set_wakeup_enable(dp, true); | |
9918 | } else { | |
9919 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; | |
9920 | device_set_wakeup_enable(dp, false); | |
9921 | } | |
9922 | spin_unlock_bh(&tp->lock); | |
9923 | ||
9924 | return 0; | |
9925 | } | |
9926 | ||
9927 | static u32 tg3_get_msglevel(struct net_device *dev) | |
9928 | { | |
9929 | struct tg3 *tp = netdev_priv(dev); | |
9930 | return tp->msg_enable; | |
9931 | } | |
9932 | ||
9933 | static void tg3_set_msglevel(struct net_device *dev, u32 value) | |
9934 | { | |
9935 | struct tg3 *tp = netdev_priv(dev); | |
9936 | tp->msg_enable = value; | |
9937 | } | |
9938 | ||
9939 | static int tg3_set_tso(struct net_device *dev, u32 value) | |
9940 | { | |
9941 | struct tg3 *tp = netdev_priv(dev); | |
9942 | ||
9943 | if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
9944 | if (value) | |
9945 | return -EINVAL; | |
9946 | return 0; | |
9947 | } | |
9948 | if ((dev->features & NETIF_F_IPV6_CSUM) && | |
9949 | ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || | |
9950 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) { | |
9951 | if (value) { | |
9952 | dev->features |= NETIF_F_TSO6; | |
9953 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || | |
9954 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
9955 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
9956 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
9957 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
9958 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
9959 | dev->features |= NETIF_F_TSO_ECN; | |
9960 | } else | |
9961 | dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN); | |
9962 | } | |
9963 | return ethtool_op_set_tso(dev, value); | |
9964 | } | |
9965 | ||
9966 | static int tg3_nway_reset(struct net_device *dev) | |
9967 | { | |
9968 | struct tg3 *tp = netdev_priv(dev); | |
9969 | int r; | |
9970 | ||
9971 | if (!netif_running(dev)) | |
9972 | return -EAGAIN; | |
9973 | ||
9974 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
9975 | return -EINVAL; | |
9976 | ||
9977 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
9978 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
9979 | return -EAGAIN; | |
9980 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); | |
9981 | } else { | |
9982 | u32 bmcr; | |
9983 | ||
9984 | spin_lock_bh(&tp->lock); | |
9985 | r = -EINVAL; | |
9986 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
9987 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
9988 | ((bmcr & BMCR_ANENABLE) || | |
9989 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) { | |
9990 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | | |
9991 | BMCR_ANENABLE); | |
9992 | r = 0; | |
9993 | } | |
9994 | spin_unlock_bh(&tp->lock); | |
9995 | } | |
9996 | ||
9997 | return r; | |
9998 | } | |
9999 | ||
10000 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
10001 | { | |
10002 | struct tg3 *tp = netdev_priv(dev); | |
10003 | ||
10004 | ering->rx_max_pending = TG3_RX_RING_SIZE - 1; | |
10005 | ering->rx_mini_max_pending = 0; | |
10006 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) | |
10007 | ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1; | |
10008 | else | |
10009 | ering->rx_jumbo_max_pending = 0; | |
10010 | ||
10011 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
10012 | ||
10013 | ering->rx_pending = tp->rx_pending; | |
10014 | ering->rx_mini_pending = 0; | |
10015 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) | |
10016 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; | |
10017 | else | |
10018 | ering->rx_jumbo_pending = 0; | |
10019 | ||
10020 | ering->tx_pending = tp->napi[0].tx_pending; | |
10021 | } | |
10022 | ||
10023 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
10024 | { | |
10025 | struct tg3 *tp = netdev_priv(dev); | |
10026 | int i, irq_sync = 0, err = 0; | |
10027 | ||
10028 | if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) || | |
10029 | (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || | |
10030 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || | |
10031 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
10032 | ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) && | |
10033 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) | |
10034 | return -EINVAL; | |
10035 | ||
10036 | if (netif_running(dev)) { | |
10037 | tg3_phy_stop(tp); | |
10038 | tg3_netif_stop(tp); | |
10039 | irq_sync = 1; | |
10040 | } | |
10041 | ||
10042 | tg3_full_lock(tp, irq_sync); | |
10043 | ||
10044 | tp->rx_pending = ering->rx_pending; | |
10045 | ||
10046 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && | |
10047 | tp->rx_pending > 63) | |
10048 | tp->rx_pending = 63; | |
10049 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
10050 | ||
10051 | for (i = 0; i < TG3_IRQ_MAX_VECS; i++) | |
10052 | tp->napi[i].tx_pending = ering->tx_pending; | |
10053 | ||
10054 | if (netif_running(dev)) { | |
10055 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10056 | err = tg3_restart_hw(tp, 1); | |
10057 | if (!err) | |
10058 | tg3_netif_start(tp); | |
10059 | } | |
10060 | ||
10061 | tg3_full_unlock(tp); | |
10062 | ||
10063 | if (irq_sync && !err) | |
10064 | tg3_phy_start(tp); | |
10065 | ||
10066 | return err; | |
10067 | } | |
10068 | ||
10069 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
10070 | { | |
10071 | struct tg3 *tp = netdev_priv(dev); | |
10072 | ||
10073 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; | |
10074 | ||
10075 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) | |
10076 | epause->rx_pause = 1; | |
10077 | else | |
10078 | epause->rx_pause = 0; | |
10079 | ||
10080 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) | |
10081 | epause->tx_pause = 1; | |
10082 | else | |
10083 | epause->tx_pause = 0; | |
10084 | } | |
10085 | ||
10086 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
10087 | { | |
10088 | struct tg3 *tp = netdev_priv(dev); | |
10089 | int err = 0; | |
10090 | ||
10091 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
10092 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
10093 | return -EAGAIN; | |
10094 | ||
10095 | if (epause->autoneg) { | |
10096 | u32 newadv; | |
10097 | struct phy_device *phydev; | |
10098 | ||
10099 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
10100 | ||
10101 | if (epause->rx_pause) { | |
10102 | if (epause->tx_pause) | |
10103 | newadv = ADVERTISED_Pause; | |
10104 | else | |
10105 | newadv = ADVERTISED_Pause | | |
10106 | ADVERTISED_Asym_Pause; | |
10107 | } else if (epause->tx_pause) { | |
10108 | newadv = ADVERTISED_Asym_Pause; | |
10109 | } else | |
10110 | newadv = 0; | |
10111 | ||
10112 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
10113 | u32 oldadv = phydev->advertising & | |
10114 | (ADVERTISED_Pause | | |
10115 | ADVERTISED_Asym_Pause); | |
10116 | if (oldadv != newadv) { | |
10117 | phydev->advertising &= | |
10118 | ~(ADVERTISED_Pause | | |
10119 | ADVERTISED_Asym_Pause); | |
10120 | phydev->advertising |= newadv; | |
10121 | err = phy_start_aneg(phydev); | |
10122 | } | |
10123 | } else { | |
10124 | tp->link_config.advertising &= | |
10125 | ~(ADVERTISED_Pause | | |
10126 | ADVERTISED_Asym_Pause); | |
10127 | tp->link_config.advertising |= newadv; | |
10128 | } | |
10129 | } else { | |
10130 | if (epause->rx_pause) | |
10131 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10132 | else | |
10133 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; | |
10134 | ||
10135 | if (epause->tx_pause) | |
10136 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10137 | else | |
10138 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; | |
10139 | ||
10140 | if (netif_running(dev)) | |
10141 | tg3_setup_flow_control(tp, 0, 0); | |
10142 | } | |
10143 | } else { | |
10144 | int irq_sync = 0; | |
10145 | ||
10146 | if (netif_running(dev)) { | |
10147 | tg3_netif_stop(tp); | |
10148 | irq_sync = 1; | |
10149 | } | |
10150 | ||
10151 | tg3_full_lock(tp, irq_sync); | |
10152 | ||
10153 | if (epause->autoneg) | |
10154 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
10155 | else | |
10156 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
10157 | if (epause->rx_pause) | |
10158 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10159 | else | |
10160 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; | |
10161 | if (epause->tx_pause) | |
10162 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10163 | else | |
10164 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; | |
10165 | ||
10166 | if (netif_running(dev)) { | |
10167 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10168 | err = tg3_restart_hw(tp, 1); | |
10169 | if (!err) | |
10170 | tg3_netif_start(tp); | |
10171 | } | |
10172 | ||
10173 | tg3_full_unlock(tp); | |
10174 | } | |
10175 | ||
10176 | return err; | |
10177 | } | |
10178 | ||
10179 | static u32 tg3_get_rx_csum(struct net_device *dev) | |
10180 | { | |
10181 | struct tg3 *tp = netdev_priv(dev); | |
10182 | return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0; | |
10183 | } | |
10184 | ||
10185 | static int tg3_set_rx_csum(struct net_device *dev, u32 data) | |
10186 | { | |
10187 | struct tg3 *tp = netdev_priv(dev); | |
10188 | ||
10189 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { | |
10190 | if (data != 0) | |
10191 | return -EINVAL; | |
10192 | return 0; | |
10193 | } | |
10194 | ||
10195 | spin_lock_bh(&tp->lock); | |
10196 | if (data) | |
10197 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
10198 | else | |
10199 | tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; | |
10200 | spin_unlock_bh(&tp->lock); | |
10201 | ||
10202 | return 0; | |
10203 | } | |
10204 | ||
10205 | static int tg3_set_tx_csum(struct net_device *dev, u32 data) | |
10206 | { | |
10207 | struct tg3 *tp = netdev_priv(dev); | |
10208 | ||
10209 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { | |
10210 | if (data != 0) | |
10211 | return -EINVAL; | |
10212 | return 0; | |
10213 | } | |
10214 | ||
10215 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
10216 | ethtool_op_set_tx_ipv6_csum(dev, data); | |
10217 | else | |
10218 | ethtool_op_set_tx_csum(dev, data); | |
10219 | ||
10220 | return 0; | |
10221 | } | |
10222 | ||
10223 | static int tg3_get_sset_count (struct net_device *dev, int sset) | |
10224 | { | |
10225 | switch (sset) { | |
10226 | case ETH_SS_TEST: | |
10227 | return TG3_NUM_TEST; | |
10228 | case ETH_SS_STATS: | |
10229 | return TG3_NUM_STATS; | |
10230 | default: | |
10231 | return -EOPNOTSUPP; | |
10232 | } | |
10233 | } | |
10234 | ||
10235 | static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf) | |
10236 | { | |
10237 | switch (stringset) { | |
10238 | case ETH_SS_STATS: | |
10239 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10240 | break; | |
10241 | case ETH_SS_TEST: | |
10242 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10243 | break; | |
10244 | default: | |
10245 | WARN_ON(1); /* we need a WARN() */ | |
10246 | break; | |
10247 | } | |
10248 | } | |
10249 | ||
10250 | static int tg3_phys_id(struct net_device *dev, u32 data) | |
10251 | { | |
10252 | struct tg3 *tp = netdev_priv(dev); | |
10253 | int i; | |
10254 | ||
10255 | if (!netif_running(tp->dev)) | |
10256 | return -EAGAIN; | |
10257 | ||
10258 | if (data == 0) | |
10259 | data = UINT_MAX / 2; | |
10260 | ||
10261 | for (i = 0; i < (data * 2); i++) { | |
10262 | if ((i % 2) == 0) | |
10263 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10264 | LED_CTRL_1000MBPS_ON | | |
10265 | LED_CTRL_100MBPS_ON | | |
10266 | LED_CTRL_10MBPS_ON | | |
10267 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10268 | LED_CTRL_TRAFFIC_BLINK | | |
10269 | LED_CTRL_TRAFFIC_LED); | |
10270 | ||
10271 | else | |
10272 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10273 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10274 | ||
10275 | if (msleep_interruptible(500)) | |
10276 | break; | |
10277 | } | |
10278 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10279 | return 0; | |
10280 | } | |
10281 | ||
10282 | static void tg3_get_ethtool_stats (struct net_device *dev, | |
10283 | struct ethtool_stats *estats, u64 *tmp_stats) | |
10284 | { | |
10285 | struct tg3 *tp = netdev_priv(dev); | |
10286 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10287 | } | |
10288 | ||
10289 | #define NVRAM_TEST_SIZE 0x100 | |
10290 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 | |
10291 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10292 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
10293 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 | |
10294 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
10295 | ||
10296 | static int tg3_test_nvram(struct tg3 *tp) | |
10297 | { | |
10298 | u32 csum, magic; | |
10299 | __be32 *buf; | |
10300 | int i, j, k, err = 0, size; | |
10301 | ||
10302 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) | |
10303 | return 0; | |
10304 | ||
10305 | if (tg3_nvram_read(tp, 0, &magic) != 0) | |
10306 | return -EIO; | |
10307 | ||
10308 | if (magic == TG3_EEPROM_MAGIC) | |
10309 | size = NVRAM_TEST_SIZE; | |
10310 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { | |
10311 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == | |
10312 | TG3_EEPROM_SB_FORMAT_1) { | |
10313 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10314 | case TG3_EEPROM_SB_REVISION_0: | |
10315 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10316 | break; | |
10317 | case TG3_EEPROM_SB_REVISION_2: | |
10318 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10319 | break; | |
10320 | case TG3_EEPROM_SB_REVISION_3: | |
10321 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10322 | break; | |
10323 | default: | |
10324 | return 0; | |
10325 | } | |
10326 | } else | |
10327 | return 0; | |
10328 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) | |
10329 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10330 | else | |
10331 | return -EIO; | |
10332 | ||
10333 | buf = kmalloc(size, GFP_KERNEL); | |
10334 | if (buf == NULL) | |
10335 | return -ENOMEM; | |
10336 | ||
10337 | err = -EIO; | |
10338 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
10339 | err = tg3_nvram_read_be32(tp, i, &buf[j]); | |
10340 | if (err) | |
10341 | break; | |
10342 | } | |
10343 | if (i < size) | |
10344 | goto out; | |
10345 | ||
10346 | /* Selfboot format */ | |
10347 | magic = be32_to_cpu(buf[0]); | |
10348 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == | |
10349 | TG3_EEPROM_MAGIC_FW) { | |
10350 | u8 *buf8 = (u8 *) buf, csum8 = 0; | |
10351 | ||
10352 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == | |
10353 | TG3_EEPROM_SB_REVISION_2) { | |
10354 | /* For rev 2, the csum doesn't include the MBA. */ | |
10355 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10356 | csum8 += buf8[i]; | |
10357 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10358 | csum8 += buf8[i]; | |
10359 | } else { | |
10360 | for (i = 0; i < size; i++) | |
10361 | csum8 += buf8[i]; | |
10362 | } | |
10363 | ||
10364 | if (csum8 == 0) { | |
10365 | err = 0; | |
10366 | goto out; | |
10367 | } | |
10368 | ||
10369 | err = -EIO; | |
10370 | goto out; | |
10371 | } | |
10372 | ||
10373 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == | |
10374 | TG3_EEPROM_MAGIC_HW) { | |
10375 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
10376 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; | |
10377 | u8 *buf8 = (u8 *) buf; | |
10378 | ||
10379 | /* Separate the parity bits and the data bytes. */ | |
10380 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10381 | if ((i == 0) || (i == 8)) { | |
10382 | int l; | |
10383 | u8 msk; | |
10384 | ||
10385 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10386 | parity[k++] = buf8[i] & msk; | |
10387 | i++; | |
10388 | } | |
10389 | else if (i == 16) { | |
10390 | int l; | |
10391 | u8 msk; | |
10392 | ||
10393 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10394 | parity[k++] = buf8[i] & msk; | |
10395 | i++; | |
10396 | ||
10397 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10398 | parity[k++] = buf8[i] & msk; | |
10399 | i++; | |
10400 | } | |
10401 | data[j++] = buf8[i]; | |
10402 | } | |
10403 | ||
10404 | err = -EIO; | |
10405 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10406 | u8 hw8 = hweight8(data[i]); | |
10407 | ||
10408 | if ((hw8 & 0x1) && parity[i]) | |
10409 | goto out; | |
10410 | else if (!(hw8 & 0x1) && !parity[i]) | |
10411 | goto out; | |
10412 | } | |
10413 | err = 0; | |
10414 | goto out; | |
10415 | } | |
10416 | ||
10417 | /* Bootstrap checksum at offset 0x10 */ | |
10418 | csum = calc_crc((unsigned char *) buf, 0x10); | |
10419 | if (csum != be32_to_cpu(buf[0x10/4])) | |
10420 | goto out; | |
10421 | ||
10422 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10423 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
10424 | if (csum != be32_to_cpu(buf[0xfc/4])) | |
10425 | goto out; | |
10426 | ||
10427 | err = 0; | |
10428 | ||
10429 | out: | |
10430 | kfree(buf); | |
10431 | return err; | |
10432 | } | |
10433 | ||
10434 | #define TG3_SERDES_TIMEOUT_SEC 2 | |
10435 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10436 | ||
10437 | static int tg3_test_link(struct tg3 *tp) | |
10438 | { | |
10439 | int i, max; | |
10440 | ||
10441 | if (!netif_running(tp->dev)) | |
10442 | return -ENODEV; | |
10443 | ||
10444 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) | |
10445 | max = TG3_SERDES_TIMEOUT_SEC; | |
10446 | else | |
10447 | max = TG3_COPPER_TIMEOUT_SEC; | |
10448 | ||
10449 | for (i = 0; i < max; i++) { | |
10450 | if (netif_carrier_ok(tp->dev)) | |
10451 | return 0; | |
10452 | ||
10453 | if (msleep_interruptible(1000)) | |
10454 | break; | |
10455 | } | |
10456 | ||
10457 | return -EIO; | |
10458 | } | |
10459 | ||
10460 | /* Only test the commonly used registers */ | |
10461 | static int tg3_test_registers(struct tg3 *tp) | |
10462 | { | |
10463 | int i, is_5705, is_5750; | |
10464 | u32 offset, read_mask, write_mask, val, save_val, read_val; | |
10465 | static struct { | |
10466 | u16 offset; | |
10467 | u16 flags; | |
10468 | #define TG3_FL_5705 0x1 | |
10469 | #define TG3_FL_NOT_5705 0x2 | |
10470 | #define TG3_FL_NOT_5788 0x4 | |
10471 | #define TG3_FL_NOT_5750 0x8 | |
10472 | u32 read_mask; | |
10473 | u32 write_mask; | |
10474 | } reg_tbl[] = { | |
10475 | /* MAC Control Registers */ | |
10476 | { MAC_MODE, TG3_FL_NOT_5705, | |
10477 | 0x00000000, 0x00ef6f8c }, | |
10478 | { MAC_MODE, TG3_FL_5705, | |
10479 | 0x00000000, 0x01ef6b8c }, | |
10480 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10481 | 0x03800107, 0x00000000 }, | |
10482 | { MAC_STATUS, TG3_FL_5705, | |
10483 | 0x03800100, 0x00000000 }, | |
10484 | { MAC_ADDR_0_HIGH, 0x0000, | |
10485 | 0x00000000, 0x0000ffff }, | |
10486 | { MAC_ADDR_0_LOW, 0x0000, | |
10487 | 0x00000000, 0xffffffff }, | |
10488 | { MAC_RX_MTU_SIZE, 0x0000, | |
10489 | 0x00000000, 0x0000ffff }, | |
10490 | { MAC_TX_MODE, 0x0000, | |
10491 | 0x00000000, 0x00000070 }, | |
10492 | { MAC_TX_LENGTHS, 0x0000, | |
10493 | 0x00000000, 0x00003fff }, | |
10494 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10495 | 0x00000000, 0x000007fc }, | |
10496 | { MAC_RX_MODE, TG3_FL_5705, | |
10497 | 0x00000000, 0x000007dc }, | |
10498 | { MAC_HASH_REG_0, 0x0000, | |
10499 | 0x00000000, 0xffffffff }, | |
10500 | { MAC_HASH_REG_1, 0x0000, | |
10501 | 0x00000000, 0xffffffff }, | |
10502 | { MAC_HASH_REG_2, 0x0000, | |
10503 | 0x00000000, 0xffffffff }, | |
10504 | { MAC_HASH_REG_3, 0x0000, | |
10505 | 0x00000000, 0xffffffff }, | |
10506 | ||
10507 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10508 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10509 | 0x00000000, 0xffffffff }, | |
10510 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10511 | 0x00000000, 0xffffffff }, | |
10512 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10513 | 0x00000000, 0x00000003 }, | |
10514 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10515 | 0x00000000, 0xffffffff }, | |
10516 | { RCVDBDI_STD_BD+0, 0x0000, | |
10517 | 0x00000000, 0xffffffff }, | |
10518 | { RCVDBDI_STD_BD+4, 0x0000, | |
10519 | 0x00000000, 0xffffffff }, | |
10520 | { RCVDBDI_STD_BD+8, 0x0000, | |
10521 | 0x00000000, 0xffff0002 }, | |
10522 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10523 | 0x00000000, 0xffffffff }, | |
10524 | ||
10525 | /* Receive BD Initiator Control Registers. */ | |
10526 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10527 | 0x00000000, 0xffffffff }, | |
10528 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10529 | 0x00000000, 0x000003ff }, | |
10530 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
10531 | 0x00000000, 0xffffffff }, | |
10532 | ||
10533 | /* Host Coalescing Control Registers. */ | |
10534 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
10535 | 0x00000000, 0x00000004 }, | |
10536 | { HOSTCC_MODE, TG3_FL_5705, | |
10537 | 0x00000000, 0x000000f6 }, | |
10538 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
10539 | 0x00000000, 0xffffffff }, | |
10540 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
10541 | 0x00000000, 0x000003ff }, | |
10542 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
10543 | 0x00000000, 0xffffffff }, | |
10544 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
10545 | 0x00000000, 0x000003ff }, | |
10546 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
10547 | 0x00000000, 0xffffffff }, | |
10548 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10549 | 0x00000000, 0x000000ff }, | |
10550 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
10551 | 0x00000000, 0xffffffff }, | |
10552 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10553 | 0x00000000, 0x000000ff }, | |
10554 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10555 | 0x00000000, 0xffffffff }, | |
10556 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10557 | 0x00000000, 0xffffffff }, | |
10558 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10559 | 0x00000000, 0xffffffff }, | |
10560 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10561 | 0x00000000, 0x000000ff }, | |
10562 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10563 | 0x00000000, 0xffffffff }, | |
10564 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10565 | 0x00000000, 0x000000ff }, | |
10566 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
10567 | 0x00000000, 0xffffffff }, | |
10568 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
10569 | 0x00000000, 0xffffffff }, | |
10570 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
10571 | 0x00000000, 0xffffffff }, | |
10572 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
10573 | 0x00000000, 0xffffffff }, | |
10574 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
10575 | 0x00000000, 0xffffffff }, | |
10576 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
10577 | 0xffffffff, 0x00000000 }, | |
10578 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
10579 | 0xffffffff, 0x00000000 }, | |
10580 | ||
10581 | /* Buffer Manager Control Registers. */ | |
10582 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, | |
10583 | 0x00000000, 0x007fff80 }, | |
10584 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, | |
10585 | 0x00000000, 0x007fffff }, | |
10586 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
10587 | 0x00000000, 0x0000003f }, | |
10588 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
10589 | 0x00000000, 0x000001ff }, | |
10590 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
10591 | 0x00000000, 0x000001ff }, | |
10592 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
10593 | 0xffffffff, 0x00000000 }, | |
10594 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
10595 | 0xffffffff, 0x00000000 }, | |
10596 | ||
10597 | /* Mailbox Registers */ | |
10598 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
10599 | 0x00000000, 0x000001ff }, | |
10600 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
10601 | 0x00000000, 0x000001ff }, | |
10602 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
10603 | 0x00000000, 0x000007ff }, | |
10604 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
10605 | 0x00000000, 0x000001ff }, | |
10606 | ||
10607 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
10608 | }; | |
10609 | ||
10610 | is_5705 = is_5750 = 0; | |
10611 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
10612 | is_5705 = 1; | |
10613 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) | |
10614 | is_5750 = 1; | |
10615 | } | |
10616 | ||
10617 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
10618 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
10619 | continue; | |
10620 | ||
10621 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
10622 | continue; | |
10623 | ||
10624 | if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
10625 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) | |
10626 | continue; | |
10627 | ||
10628 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) | |
10629 | continue; | |
10630 | ||
10631 | offset = (u32) reg_tbl[i].offset; | |
10632 | read_mask = reg_tbl[i].read_mask; | |
10633 | write_mask = reg_tbl[i].write_mask; | |
10634 | ||
10635 | /* Save the original register content */ | |
10636 | save_val = tr32(offset); | |
10637 | ||
10638 | /* Determine the read-only value. */ | |
10639 | read_val = save_val & read_mask; | |
10640 | ||
10641 | /* Write zero to the register, then make sure the read-only bits | |
10642 | * are not changed and the read/write bits are all zeros. | |
10643 | */ | |
10644 | tw32(offset, 0); | |
10645 | ||
10646 | val = tr32(offset); | |
10647 | ||
10648 | /* Test the read-only and read/write bits. */ | |
10649 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
10650 | goto out; | |
10651 | ||
10652 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
10653 | * make sure the read-only bits are not changed and the | |
10654 | * read/write bits are all ones. | |
10655 | */ | |
10656 | tw32(offset, read_mask | write_mask); | |
10657 | ||
10658 | val = tr32(offset); | |
10659 | ||
10660 | /* Test the read-only bits. */ | |
10661 | if ((val & read_mask) != read_val) | |
10662 | goto out; | |
10663 | ||
10664 | /* Test the read/write bits. */ | |
10665 | if ((val & write_mask) != write_mask) | |
10666 | goto out; | |
10667 | ||
10668 | tw32(offset, save_val); | |
10669 | } | |
10670 | ||
10671 | return 0; | |
10672 | ||
10673 | out: | |
10674 | if (netif_msg_hw(tp)) | |
10675 | printk(KERN_ERR PFX "Register test failed at offset %x\n", | |
10676 | offset); | |
10677 | tw32(offset, save_val); | |
10678 | return -EIO; | |
10679 | } | |
10680 | ||
10681 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) | |
10682 | { | |
10683 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; | |
10684 | int i; | |
10685 | u32 j; | |
10686 | ||
10687 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { | |
10688 | for (j = 0; j < len; j += 4) { | |
10689 | u32 val; | |
10690 | ||
10691 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
10692 | tg3_read_mem(tp, offset + j, &val); | |
10693 | if (val != test_pattern[i]) | |
10694 | return -EIO; | |
10695 | } | |
10696 | } | |
10697 | return 0; | |
10698 | } | |
10699 | ||
10700 | static int tg3_test_memory(struct tg3 *tp) | |
10701 | { | |
10702 | static struct mem_entry { | |
10703 | u32 offset; | |
10704 | u32 len; | |
10705 | } mem_tbl_570x[] = { | |
10706 | { 0x00000000, 0x00b50}, | |
10707 | { 0x00002000, 0x1c000}, | |
10708 | { 0xffffffff, 0x00000} | |
10709 | }, mem_tbl_5705[] = { | |
10710 | { 0x00000100, 0x0000c}, | |
10711 | { 0x00000200, 0x00008}, | |
10712 | { 0x00004000, 0x00800}, | |
10713 | { 0x00006000, 0x01000}, | |
10714 | { 0x00008000, 0x02000}, | |
10715 | { 0x00010000, 0x0e000}, | |
10716 | { 0xffffffff, 0x00000} | |
10717 | }, mem_tbl_5755[] = { | |
10718 | { 0x00000200, 0x00008}, | |
10719 | { 0x00004000, 0x00800}, | |
10720 | { 0x00006000, 0x00800}, | |
10721 | { 0x00008000, 0x02000}, | |
10722 | { 0x00010000, 0x0c000}, | |
10723 | { 0xffffffff, 0x00000} | |
10724 | }, mem_tbl_5906[] = { | |
10725 | { 0x00000200, 0x00008}, | |
10726 | { 0x00004000, 0x00400}, | |
10727 | { 0x00006000, 0x00400}, | |
10728 | { 0x00008000, 0x01000}, | |
10729 | { 0x00010000, 0x01000}, | |
10730 | { 0xffffffff, 0x00000} | |
10731 | }, mem_tbl_5717[] = { | |
10732 | { 0x00000200, 0x00008}, | |
10733 | { 0x00010000, 0x0a000}, | |
10734 | { 0x00020000, 0x13c00}, | |
10735 | { 0xffffffff, 0x00000} | |
10736 | }, mem_tbl_57765[] = { | |
10737 | { 0x00000200, 0x00008}, | |
10738 | { 0x00004000, 0x00800}, | |
10739 | { 0x00006000, 0x09800}, | |
10740 | { 0x00010000, 0x0a000}, | |
10741 | { 0xffffffff, 0x00000} | |
10742 | }; | |
10743 | struct mem_entry *mem_tbl; | |
10744 | int err = 0; | |
10745 | int i; | |
10746 | ||
10747 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
10748 | mem_tbl = mem_tbl_5717; | |
10749 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
10750 | mem_tbl = mem_tbl_57765; | |
10751 | else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
10752 | mem_tbl = mem_tbl_5755; | |
10753 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
10754 | mem_tbl = mem_tbl_5906; | |
10755 | else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
10756 | mem_tbl = mem_tbl_5705; | |
10757 | else | |
10758 | mem_tbl = mem_tbl_570x; | |
10759 | ||
10760 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
10761 | if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset, | |
10762 | mem_tbl[i].len)) != 0) | |
10763 | break; | |
10764 | } | |
10765 | ||
10766 | return err; | |
10767 | } | |
10768 | ||
10769 | #define TG3_MAC_LOOPBACK 0 | |
10770 | #define TG3_PHY_LOOPBACK 1 | |
10771 | ||
10772 | static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |
10773 | { | |
10774 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; | |
10775 | u32 desc_idx, coal_now; | |
10776 | struct sk_buff *skb, *rx_skb; | |
10777 | u8 *tx_data; | |
10778 | dma_addr_t map; | |
10779 | int num_pkts, tx_len, rx_len, i, err; | |
10780 | struct tg3_rx_buffer_desc *desc; | |
10781 | struct tg3_napi *tnapi, *rnapi; | |
10782 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; | |
10783 | ||
10784 | if (tp->irq_cnt > 1) { | |
10785 | tnapi = &tp->napi[1]; | |
10786 | rnapi = &tp->napi[1]; | |
10787 | } else { | |
10788 | tnapi = &tp->napi[0]; | |
10789 | rnapi = &tp->napi[0]; | |
10790 | } | |
10791 | coal_now = tnapi->coal_now | rnapi->coal_now; | |
10792 | ||
10793 | if (loopback_mode == TG3_MAC_LOOPBACK) { | |
10794 | /* HW errata - mac loopback fails in some cases on 5780. | |
10795 | * Normal traffic and PHY loopback are not affected by | |
10796 | * errata. | |
10797 | */ | |
10798 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) | |
10799 | return 0; | |
10800 | ||
10801 | mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) | | |
10802 | MAC_MODE_PORT_INT_LPBACK; | |
10803 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
10804 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
10805 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) | |
10806 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
10807 | else | |
10808 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
10809 | tw32(MAC_MODE, mac_mode); | |
10810 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { | |
10811 | u32 val; | |
10812 | ||
10813 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { | |
10814 | tg3_phy_fet_toggle_apd(tp, false); | |
10815 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; | |
10816 | } else | |
10817 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
10818 | ||
10819 | tg3_phy_toggle_automdix(tp, 0); | |
10820 | ||
10821 | tg3_writephy(tp, MII_BMCR, val); | |
10822 | udelay(40); | |
10823 | ||
10824 | mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
10825 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { | |
10826 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
10827 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800); | |
10828 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
10829 | } else | |
10830 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
10831 | ||
10832 | /* reset to prevent losing 1st rx packet intermittently */ | |
10833 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
10834 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
10835 | udelay(10); | |
10836 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
10837 | } | |
10838 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
10839 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) | |
10840 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
10841 | else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) | |
10842 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
10843 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
10844 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
10845 | } | |
10846 | tw32(MAC_MODE, mac_mode); | |
10847 | } | |
10848 | else | |
10849 | return -EINVAL; | |
10850 | ||
10851 | err = -EIO; | |
10852 | ||
10853 | tx_len = 1514; | |
10854 | skb = netdev_alloc_skb(tp->dev, tx_len); | |
10855 | if (!skb) | |
10856 | return -ENOMEM; | |
10857 | ||
10858 | tx_data = skb_put(skb, tx_len); | |
10859 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
10860 | memset(tx_data + 6, 0x0, 8); | |
10861 | ||
10862 | tw32(MAC_RX_MTU_SIZE, tx_len + 4); | |
10863 | ||
10864 | for (i = 14; i < tx_len; i++) | |
10865 | tx_data[i] = (u8) (i & 0xff); | |
10866 | ||
10867 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); | |
10868 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
10869 | dev_kfree_skb(skb); | |
10870 | return -EIO; | |
10871 | } | |
10872 | ||
10873 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
10874 | rnapi->coal_now); | |
10875 | ||
10876 | udelay(10); | |
10877 | ||
10878 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; | |
10879 | ||
10880 | num_pkts = 0; | |
10881 | ||
10882 | tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1); | |
10883 | ||
10884 | tnapi->tx_prod++; | |
10885 | num_pkts++; | |
10886 | ||
10887 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); | |
10888 | tr32_mailbox(tnapi->prodmbox); | |
10889 | ||
10890 | udelay(10); | |
10891 | ||
10892 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ | |
10893 | for (i = 0; i < 35; i++) { | |
10894 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
10895 | coal_now); | |
10896 | ||
10897 | udelay(10); | |
10898 | ||
10899 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; | |
10900 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
10901 | if ((tx_idx == tnapi->tx_prod) && | |
10902 | (rx_idx == (rx_start_idx + num_pkts))) | |
10903 | break; | |
10904 | } | |
10905 | ||
10906 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); | |
10907 | dev_kfree_skb(skb); | |
10908 | ||
10909 | if (tx_idx != tnapi->tx_prod) | |
10910 | goto out; | |
10911 | ||
10912 | if (rx_idx != rx_start_idx + num_pkts) | |
10913 | goto out; | |
10914 | ||
10915 | desc = &rnapi->rx_rcb[rx_start_idx]; | |
10916 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
10917 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
10918 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
10919 | goto out; | |
10920 | ||
10921 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
10922 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
10923 | goto out; | |
10924 | ||
10925 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; | |
10926 | if (rx_len != tx_len) | |
10927 | goto out; | |
10928 | ||
10929 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; | |
10930 | ||
10931 | map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping); | |
10932 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE); | |
10933 | ||
10934 | for (i = 14; i < tx_len; i++) { | |
10935 | if (*(rx_skb->data + i) != (u8) (i & 0xff)) | |
10936 | goto out; | |
10937 | } | |
10938 | err = 0; | |
10939 | ||
10940 | /* tg3_free_rings will unmap and free the rx_skb */ | |
10941 | out: | |
10942 | return err; | |
10943 | } | |
10944 | ||
10945 | #define TG3_MAC_LOOPBACK_FAILED 1 | |
10946 | #define TG3_PHY_LOOPBACK_FAILED 2 | |
10947 | #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \ | |
10948 | TG3_PHY_LOOPBACK_FAILED) | |
10949 | ||
10950 | static int tg3_test_loopback(struct tg3 *tp) | |
10951 | { | |
10952 | int err = 0; | |
10953 | u32 cpmuctrl = 0; | |
10954 | ||
10955 | if (!netif_running(tp->dev)) | |
10956 | return TG3_LOOPBACK_FAILED; | |
10957 | ||
10958 | err = tg3_reset_hw(tp, 1); | |
10959 | if (err) | |
10960 | return TG3_LOOPBACK_FAILED; | |
10961 | ||
10962 | /* Turn off gphy autopowerdown. */ | |
10963 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
10964 | tg3_phy_toggle_apd(tp, false); | |
10965 | ||
10966 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { | |
10967 | int i; | |
10968 | u32 status; | |
10969 | ||
10970 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
10971 | ||
10972 | /* Wait for up to 40 microseconds to acquire lock. */ | |
10973 | for (i = 0; i < 4; i++) { | |
10974 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
10975 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
10976 | break; | |
10977 | udelay(10); | |
10978 | } | |
10979 | ||
10980 | if (status != CPMU_MUTEX_GNT_DRIVER) | |
10981 | return TG3_LOOPBACK_FAILED; | |
10982 | ||
10983 | /* Turn off link-based power management. */ | |
10984 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
10985 | tw32(TG3_CPMU_CTRL, | |
10986 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
10987 | CPMU_CTRL_LINK_AWARE_MODE)); | |
10988 | } | |
10989 | ||
10990 | if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) | |
10991 | err |= TG3_MAC_LOOPBACK_FAILED; | |
10992 | ||
10993 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { | |
10994 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
10995 | ||
10996 | /* Release the mutex */ | |
10997 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
10998 | } | |
10999 | ||
11000 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
11001 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { | |
11002 | if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) | |
11003 | err |= TG3_PHY_LOOPBACK_FAILED; | |
11004 | } | |
11005 | ||
11006 | /* Re-enable gphy autopowerdown. */ | |
11007 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
11008 | tg3_phy_toggle_apd(tp, true); | |
11009 | ||
11010 | return err; | |
11011 | } | |
11012 | ||
11013 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, | |
11014 | u64 *data) | |
11015 | { | |
11016 | struct tg3 *tp = netdev_priv(dev); | |
11017 | ||
11018 | if (tp->link_config.phy_is_low_power) | |
11019 | tg3_set_power_state(tp, PCI_D0); | |
11020 | ||
11021 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); | |
11022 | ||
11023 | if (tg3_test_nvram(tp) != 0) { | |
11024 | etest->flags |= ETH_TEST_FL_FAILED; | |
11025 | data[0] = 1; | |
11026 | } | |
11027 | if (tg3_test_link(tp) != 0) { | |
11028 | etest->flags |= ETH_TEST_FL_FAILED; | |
11029 | data[1] = 1; | |
11030 | } | |
11031 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | |
11032 | int err, err2 = 0, irq_sync = 0; | |
11033 | ||
11034 | if (netif_running(dev)) { | |
11035 | tg3_phy_stop(tp); | |
11036 | tg3_netif_stop(tp); | |
11037 | irq_sync = 1; | |
11038 | } | |
11039 | ||
11040 | tg3_full_lock(tp, irq_sync); | |
11041 | ||
11042 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
11043 | err = tg3_nvram_lock(tp); | |
11044 | tg3_halt_cpu(tp, RX_CPU_BASE); | |
11045 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
11046 | tg3_halt_cpu(tp, TX_CPU_BASE); | |
11047 | if (!err) | |
11048 | tg3_nvram_unlock(tp); | |
11049 | ||
11050 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) | |
11051 | tg3_phy_reset(tp); | |
11052 | ||
11053 | if (tg3_test_registers(tp) != 0) { | |
11054 | etest->flags |= ETH_TEST_FL_FAILED; | |
11055 | data[2] = 1; | |
11056 | } | |
11057 | if (tg3_test_memory(tp) != 0) { | |
11058 | etest->flags |= ETH_TEST_FL_FAILED; | |
11059 | data[3] = 1; | |
11060 | } | |
11061 | if ((data[4] = tg3_test_loopback(tp)) != 0) | |
11062 | etest->flags |= ETH_TEST_FL_FAILED; | |
11063 | ||
11064 | tg3_full_unlock(tp); | |
11065 | ||
11066 | if (tg3_test_interrupt(tp) != 0) { | |
11067 | etest->flags |= ETH_TEST_FL_FAILED; | |
11068 | data[5] = 1; | |
11069 | } | |
11070 | ||
11071 | tg3_full_lock(tp, 0); | |
11072 | ||
11073 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
11074 | if (netif_running(dev)) { | |
11075 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
11076 | err2 = tg3_restart_hw(tp, 1); | |
11077 | if (!err2) | |
11078 | tg3_netif_start(tp); | |
11079 | } | |
11080 | ||
11081 | tg3_full_unlock(tp); | |
11082 | ||
11083 | if (irq_sync && !err2) | |
11084 | tg3_phy_start(tp); | |
11085 | } | |
11086 | if (tp->link_config.phy_is_low_power) | |
11087 | tg3_set_power_state(tp, PCI_D3hot); | |
11088 | ||
11089 | } | |
11090 | ||
11091 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
11092 | { | |
11093 | struct mii_ioctl_data *data = if_mii(ifr); | |
11094 | struct tg3 *tp = netdev_priv(dev); | |
11095 | int err; | |
11096 | ||
11097 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
11098 | struct phy_device *phydev; | |
11099 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
11100 | return -EAGAIN; | |
11101 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
11102 | return phy_mii_ioctl(phydev, data, cmd); | |
11103 | } | |
11104 | ||
11105 | switch(cmd) { | |
11106 | case SIOCGMIIPHY: | |
11107 | data->phy_id = tp->phy_addr; | |
11108 | ||
11109 | /* fallthru */ | |
11110 | case SIOCGMIIREG: { | |
11111 | u32 mii_regval; | |
11112 | ||
11113 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
11114 | break; /* We have no PHY */ | |
11115 | ||
11116 | if (tp->link_config.phy_is_low_power) | |
11117 | return -EAGAIN; | |
11118 | ||
11119 | spin_lock_bh(&tp->lock); | |
11120 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); | |
11121 | spin_unlock_bh(&tp->lock); | |
11122 | ||
11123 | data->val_out = mii_regval; | |
11124 | ||
11125 | return err; | |
11126 | } | |
11127 | ||
11128 | case SIOCSMIIREG: | |
11129 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
11130 | break; /* We have no PHY */ | |
11131 | ||
11132 | if (tp->link_config.phy_is_low_power) | |
11133 | return -EAGAIN; | |
11134 | ||
11135 | spin_lock_bh(&tp->lock); | |
11136 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); | |
11137 | spin_unlock_bh(&tp->lock); | |
11138 | ||
11139 | return err; | |
11140 | ||
11141 | default: | |
11142 | /* do nothing */ | |
11143 | break; | |
11144 | } | |
11145 | return -EOPNOTSUPP; | |
11146 | } | |
11147 | ||
11148 | #if TG3_VLAN_TAG_USED | |
11149 | static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
11150 | { | |
11151 | struct tg3 *tp = netdev_priv(dev); | |
11152 | ||
11153 | if (!netif_running(dev)) { | |
11154 | tp->vlgrp = grp; | |
11155 | return; | |
11156 | } | |
11157 | ||
11158 | tg3_netif_stop(tp); | |
11159 | ||
11160 | tg3_full_lock(tp, 0); | |
11161 | ||
11162 | tp->vlgrp = grp; | |
11163 | ||
11164 | /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */ | |
11165 | __tg3_set_rx_mode(dev); | |
11166 | ||
11167 | tg3_netif_start(tp); | |
11168 | ||
11169 | tg3_full_unlock(tp); | |
11170 | } | |
11171 | #endif | |
11172 | ||
11173 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
11174 | { | |
11175 | struct tg3 *tp = netdev_priv(dev); | |
11176 | ||
11177 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11178 | return 0; | |
11179 | } | |
11180 | ||
11181 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
11182 | { | |
11183 | struct tg3 *tp = netdev_priv(dev); | |
11184 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11185 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11186 | ||
11187 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
11188 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; | |
11189 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11190 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11191 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11192 | } | |
11193 | ||
11194 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11195 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11196 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11197 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11198 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11199 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11200 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11201 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11202 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11203 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11204 | return -EINVAL; | |
11205 | ||
11206 | /* No rx interrupts will be generated if both are zero */ | |
11207 | if ((ec->rx_coalesce_usecs == 0) && | |
11208 | (ec->rx_max_coalesced_frames == 0)) | |
11209 | return -EINVAL; | |
11210 | ||
11211 | /* No tx interrupts will be generated if both are zero */ | |
11212 | if ((ec->tx_coalesce_usecs == 0) && | |
11213 | (ec->tx_max_coalesced_frames == 0)) | |
11214 | return -EINVAL; | |
11215 | ||
11216 | /* Only copy relevant parameters, ignore all others. */ | |
11217 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11218 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11219 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11220 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11221 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11222 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11223 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11224 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11225 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11226 | ||
11227 | if (netif_running(dev)) { | |
11228 | tg3_full_lock(tp, 0); | |
11229 | __tg3_set_coalesce(tp, &tp->coal); | |
11230 | tg3_full_unlock(tp); | |
11231 | } | |
11232 | return 0; | |
11233 | } | |
11234 | ||
11235 | static const struct ethtool_ops tg3_ethtool_ops = { | |
11236 | .get_settings = tg3_get_settings, | |
11237 | .set_settings = tg3_set_settings, | |
11238 | .get_drvinfo = tg3_get_drvinfo, | |
11239 | .get_regs_len = tg3_get_regs_len, | |
11240 | .get_regs = tg3_get_regs, | |
11241 | .get_wol = tg3_get_wol, | |
11242 | .set_wol = tg3_set_wol, | |
11243 | .get_msglevel = tg3_get_msglevel, | |
11244 | .set_msglevel = tg3_set_msglevel, | |
11245 | .nway_reset = tg3_nway_reset, | |
11246 | .get_link = ethtool_op_get_link, | |
11247 | .get_eeprom_len = tg3_get_eeprom_len, | |
11248 | .get_eeprom = tg3_get_eeprom, | |
11249 | .set_eeprom = tg3_set_eeprom, | |
11250 | .get_ringparam = tg3_get_ringparam, | |
11251 | .set_ringparam = tg3_set_ringparam, | |
11252 | .get_pauseparam = tg3_get_pauseparam, | |
11253 | .set_pauseparam = tg3_set_pauseparam, | |
11254 | .get_rx_csum = tg3_get_rx_csum, | |
11255 | .set_rx_csum = tg3_set_rx_csum, | |
11256 | .set_tx_csum = tg3_set_tx_csum, | |
11257 | .set_sg = ethtool_op_set_sg, | |
11258 | .set_tso = tg3_set_tso, | |
11259 | .self_test = tg3_self_test, | |
11260 | .get_strings = tg3_get_strings, | |
11261 | .phys_id = tg3_phys_id, | |
11262 | .get_ethtool_stats = tg3_get_ethtool_stats, | |
11263 | .get_coalesce = tg3_get_coalesce, | |
11264 | .set_coalesce = tg3_set_coalesce, | |
11265 | .get_sset_count = tg3_get_sset_count, | |
11266 | }; | |
11267 | ||
11268 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11269 | { | |
11270 | u32 cursize, val, magic; | |
11271 | ||
11272 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11273 | ||
11274 | if (tg3_nvram_read(tp, 0, &magic) != 0) | |
11275 | return; | |
11276 | ||
11277 | if ((magic != TG3_EEPROM_MAGIC) && | |
11278 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11279 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
11280 | return; | |
11281 | ||
11282 | /* | |
11283 | * Size the chip by reading offsets at increasing powers of two. | |
11284 | * When we encounter our validation signature, we know the addressing | |
11285 | * has wrapped around, and thus have our chip size. | |
11286 | */ | |
11287 | cursize = 0x10; | |
11288 | ||
11289 | while (cursize < tp->nvram_size) { | |
11290 | if (tg3_nvram_read(tp, cursize, &val) != 0) | |
11291 | return; | |
11292 | ||
11293 | if (val == magic) | |
11294 | break; | |
11295 | ||
11296 | cursize <<= 1; | |
11297 | } | |
11298 | ||
11299 | tp->nvram_size = cursize; | |
11300 | } | |
11301 | ||
11302 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) | |
11303 | { | |
11304 | u32 val; | |
11305 | ||
11306 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || | |
11307 | tg3_nvram_read(tp, 0, &val) != 0) | |
11308 | return; | |
11309 | ||
11310 | /* Selfboot format */ | |
11311 | if (val != TG3_EEPROM_MAGIC) { | |
11312 | tg3_get_eeprom_size(tp); | |
11313 | return; | |
11314 | } | |
11315 | ||
11316 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { | |
11317 | if (val != 0) { | |
11318 | /* This is confusing. We want to operate on the | |
11319 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11320 | * call will read from NVRAM and byteswap the data | |
11321 | * according to the byteswapping settings for all | |
11322 | * other register accesses. This ensures the data we | |
11323 | * want will always reside in the lower 16-bits. | |
11324 | * However, the data in NVRAM is in LE format, which | |
11325 | * means the data from the NVRAM read will always be | |
11326 | * opposite the endianness of the CPU. The 16-bit | |
11327 | * byteswap then brings the data to CPU endianness. | |
11328 | */ | |
11329 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
11330 | return; | |
11331 | } | |
11332 | } | |
11333 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11334 | } | |
11335 | ||
11336 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11337 | { | |
11338 | u32 nvcfg1; | |
11339 | ||
11340 | nvcfg1 = tr32(NVRAM_CFG1); | |
11341 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
11342 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11343 | } else { | |
11344 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11345 | tw32(NVRAM_CFG1, nvcfg1); | |
11346 | } | |
11347 | ||
11348 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || | |
11349 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
11350 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { | |
11351 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: | |
11352 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11353 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11354 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11355 | break; | |
11356 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
11357 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11358 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
11359 | break; | |
11360 | case FLASH_VENDOR_ATMEL_EEPROM: | |
11361 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11362 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11363 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11364 | break; | |
11365 | case FLASH_VENDOR_ST: | |
11366 | tp->nvram_jedecnum = JEDEC_ST; | |
11367 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
11368 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11369 | break; | |
11370 | case FLASH_VENDOR_SAIFUN: | |
11371 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
11372 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
11373 | break; | |
11374 | case FLASH_VENDOR_SST_SMALL: | |
11375 | case FLASH_VENDOR_SST_LARGE: | |
11376 | tp->nvram_jedecnum = JEDEC_SST; | |
11377 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
11378 | break; | |
11379 | } | |
11380 | } else { | |
11381 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11382 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11383 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11384 | } | |
11385 | } | |
11386 | ||
11387 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) | |
11388 | { | |
11389 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
11390 | case FLASH_5752PAGE_SIZE_256: | |
11391 | tp->nvram_pagesize = 256; | |
11392 | break; | |
11393 | case FLASH_5752PAGE_SIZE_512: | |
11394 | tp->nvram_pagesize = 512; | |
11395 | break; | |
11396 | case FLASH_5752PAGE_SIZE_1K: | |
11397 | tp->nvram_pagesize = 1024; | |
11398 | break; | |
11399 | case FLASH_5752PAGE_SIZE_2K: | |
11400 | tp->nvram_pagesize = 2048; | |
11401 | break; | |
11402 | case FLASH_5752PAGE_SIZE_4K: | |
11403 | tp->nvram_pagesize = 4096; | |
11404 | break; | |
11405 | case FLASH_5752PAGE_SIZE_264: | |
11406 | tp->nvram_pagesize = 264; | |
11407 | break; | |
11408 | case FLASH_5752PAGE_SIZE_528: | |
11409 | tp->nvram_pagesize = 528; | |
11410 | break; | |
11411 | } | |
11412 | } | |
11413 | ||
11414 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) | |
11415 | { | |
11416 | u32 nvcfg1; | |
11417 | ||
11418 | nvcfg1 = tr32(NVRAM_CFG1); | |
11419 | ||
11420 | /* NVRAM protection for TPM */ | |
11421 | if (nvcfg1 & (1 << 27)) | |
11422 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; | |
11423 | ||
11424 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11425 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: | |
11426 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
11427 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11428 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11429 | break; | |
11430 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11431 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11432 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11433 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11434 | break; | |
11435 | case FLASH_5752VENDOR_ST_M45PE10: | |
11436 | case FLASH_5752VENDOR_ST_M45PE20: | |
11437 | case FLASH_5752VENDOR_ST_M45PE40: | |
11438 | tp->nvram_jedecnum = JEDEC_ST; | |
11439 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11440 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11441 | break; | |
11442 | } | |
11443 | ||
11444 | if (tp->tg3_flags2 & TG3_FLG2_FLASH) { | |
11445 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
11446 | } else { | |
11447 | /* For eeprom, set pagesize to maximum eeprom size */ | |
11448 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11449 | ||
11450 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11451 | tw32(NVRAM_CFG1, nvcfg1); | |
11452 | } | |
11453 | } | |
11454 | ||
11455 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) | |
11456 | { | |
11457 | u32 nvcfg1, protect = 0; | |
11458 | ||
11459 | nvcfg1 = tr32(NVRAM_CFG1); | |
11460 | ||
11461 | /* NVRAM protection for TPM */ | |
11462 | if (nvcfg1 & (1 << 27)) { | |
11463 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; | |
11464 | protect = 1; | |
11465 | } | |
11466 | ||
11467 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11468 | switch (nvcfg1) { | |
11469 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11470 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11471 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11472 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
11473 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11474 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11475 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11476 | tp->nvram_pagesize = 264; | |
11477 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
11478 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
11479 | tp->nvram_size = (protect ? 0x3e200 : | |
11480 | TG3_NVRAM_SIZE_512KB); | |
11481 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
11482 | tp->nvram_size = (protect ? 0x1f200 : | |
11483 | TG3_NVRAM_SIZE_256KB); | |
11484 | else | |
11485 | tp->nvram_size = (protect ? 0x1f200 : | |
11486 | TG3_NVRAM_SIZE_128KB); | |
11487 | break; | |
11488 | case FLASH_5752VENDOR_ST_M45PE10: | |
11489 | case FLASH_5752VENDOR_ST_M45PE20: | |
11490 | case FLASH_5752VENDOR_ST_M45PE40: | |
11491 | tp->nvram_jedecnum = JEDEC_ST; | |
11492 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11493 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11494 | tp->nvram_pagesize = 256; | |
11495 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
11496 | tp->nvram_size = (protect ? | |
11497 | TG3_NVRAM_SIZE_64KB : | |
11498 | TG3_NVRAM_SIZE_128KB); | |
11499 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
11500 | tp->nvram_size = (protect ? | |
11501 | TG3_NVRAM_SIZE_64KB : | |
11502 | TG3_NVRAM_SIZE_256KB); | |
11503 | else | |
11504 | tp->nvram_size = (protect ? | |
11505 | TG3_NVRAM_SIZE_128KB : | |
11506 | TG3_NVRAM_SIZE_512KB); | |
11507 | break; | |
11508 | } | |
11509 | } | |
11510 | ||
11511 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) | |
11512 | { | |
11513 | u32 nvcfg1; | |
11514 | ||
11515 | nvcfg1 = tr32(NVRAM_CFG1); | |
11516 | ||
11517 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11518 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: | |
11519 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11520 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
11521 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11522 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11523 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11524 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11525 | ||
11526 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11527 | tw32(NVRAM_CFG1, nvcfg1); | |
11528 | break; | |
11529 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11530 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11531 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11532 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11533 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11534 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11535 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11536 | tp->nvram_pagesize = 264; | |
11537 | break; | |
11538 | case FLASH_5752VENDOR_ST_M45PE10: | |
11539 | case FLASH_5752VENDOR_ST_M45PE20: | |
11540 | case FLASH_5752VENDOR_ST_M45PE40: | |
11541 | tp->nvram_jedecnum = JEDEC_ST; | |
11542 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11543 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11544 | tp->nvram_pagesize = 256; | |
11545 | break; | |
11546 | } | |
11547 | } | |
11548 | ||
11549 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) | |
11550 | { | |
11551 | u32 nvcfg1, protect = 0; | |
11552 | ||
11553 | nvcfg1 = tr32(NVRAM_CFG1); | |
11554 | ||
11555 | /* NVRAM protection for TPM */ | |
11556 | if (nvcfg1 & (1 << 27)) { | |
11557 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; | |
11558 | protect = 1; | |
11559 | } | |
11560 | ||
11561 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11562 | switch (nvcfg1) { | |
11563 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
11564 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11565 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11566 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
11567 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11568 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11569 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11570 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11571 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11572 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11573 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11574 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
11575 | tp->nvram_pagesize = 256; | |
11576 | break; | |
11577 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11578 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11579 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11580 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11581 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11582 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11583 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11584 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11585 | tp->nvram_jedecnum = JEDEC_ST; | |
11586 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11587 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11588 | tp->nvram_pagesize = 256; | |
11589 | break; | |
11590 | } | |
11591 | ||
11592 | if (protect) { | |
11593 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
11594 | } else { | |
11595 | switch (nvcfg1) { | |
11596 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
11597 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11598 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11599 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11600 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
11601 | break; | |
11602 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11603 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11604 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11605 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11606 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
11607 | break; | |
11608 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11609 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11610 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11611 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11612 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11613 | break; | |
11614 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
11615 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11616 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11617 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11618 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11619 | break; | |
11620 | } | |
11621 | } | |
11622 | } | |
11623 | ||
11624 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) | |
11625 | { | |
11626 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11627 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11628 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11629 | } | |
11630 | ||
11631 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) | |
11632 | { | |
11633 | u32 nvcfg1; | |
11634 | ||
11635 | nvcfg1 = tr32(NVRAM_CFG1); | |
11636 | ||
11637 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11638 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11639 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11640 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11641 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11642 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11643 | ||
11644 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11645 | tw32(NVRAM_CFG1, nvcfg1); | |
11646 | return; | |
11647 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11648 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11649 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11650 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11651 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11652 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11653 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11654 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11655 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11656 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11657 | ||
11658 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11659 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11660 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11661 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11662 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11663 | break; | |
11664 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11665 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11666 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11667 | break; | |
11668 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11669 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11670 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11671 | break; | |
11672 | } | |
11673 | break; | |
11674 | case FLASH_5752VENDOR_ST_M45PE10: | |
11675 | case FLASH_5752VENDOR_ST_M45PE20: | |
11676 | case FLASH_5752VENDOR_ST_M45PE40: | |
11677 | tp->nvram_jedecnum = JEDEC_ST; | |
11678 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11679 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11680 | ||
11681 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11682 | case FLASH_5752VENDOR_ST_M45PE10: | |
11683 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11684 | break; | |
11685 | case FLASH_5752VENDOR_ST_M45PE20: | |
11686 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11687 | break; | |
11688 | case FLASH_5752VENDOR_ST_M45PE40: | |
11689 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11690 | break; | |
11691 | } | |
11692 | break; | |
11693 | default: | |
11694 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
11695 | return; | |
11696 | } | |
11697 | ||
11698 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
11699 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
11700 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
11701 | } | |
11702 | ||
11703 | ||
11704 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
11705 | { | |
11706 | u32 nvcfg1; | |
11707 | ||
11708 | nvcfg1 = tr32(NVRAM_CFG1); | |
11709 | ||
11710 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11711 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
11712 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
11713 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11714 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11715 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11716 | ||
11717 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11718 | tw32(NVRAM_CFG1, nvcfg1); | |
11719 | return; | |
11720 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
11721 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
11722 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
11723 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
11724 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
11725 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
11726 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
11727 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11728 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11729 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11730 | ||
11731 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11732 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
11733 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
11734 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
11735 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11736 | break; | |
11737 | default: | |
11738 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11739 | break; | |
11740 | } | |
11741 | break; | |
11742 | case FLASH_5717VENDOR_ST_M_M25PE10: | |
11743 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
11744 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
11745 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
11746 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
11747 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
11748 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
11749 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
11750 | case FLASH_5717VENDOR_ST_25USPT: | |
11751 | case FLASH_5717VENDOR_ST_45USPT: | |
11752 | tp->nvram_jedecnum = JEDEC_ST; | |
11753 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11754 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11755 | ||
11756 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11757 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
11758 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
11759 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
11760 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
11761 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11762 | break; | |
11763 | default: | |
11764 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11765 | break; | |
11766 | } | |
11767 | break; | |
11768 | default: | |
11769 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
11770 | return; | |
11771 | } | |
11772 | ||
11773 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
11774 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
11775 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
11776 | } | |
11777 | ||
11778 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ | |
11779 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
11780 | { | |
11781 | tw32_f(GRC_EEPROM_ADDR, | |
11782 | (EEPROM_ADDR_FSM_RESET | | |
11783 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
11784 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
11785 | ||
11786 | msleep(1); | |
11787 | ||
11788 | /* Enable seeprom accesses. */ | |
11789 | tw32_f(GRC_LOCAL_CTRL, | |
11790 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
11791 | udelay(100); | |
11792 | ||
11793 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
11794 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
11795 | tp->tg3_flags |= TG3_FLAG_NVRAM; | |
11796 | ||
11797 | if (tg3_nvram_lock(tp)) { | |
11798 | printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, " | |
11799 | "tg3_nvram_init failed.\n", tp->dev->name); | |
11800 | return; | |
11801 | } | |
11802 | tg3_enable_nvram_access(tp); | |
11803 | ||
11804 | tp->nvram_size = 0; | |
11805 | ||
11806 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
11807 | tg3_get_5752_nvram_info(tp); | |
11808 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
11809 | tg3_get_5755_nvram_info(tp); | |
11810 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
11811 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
11812 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
11813 | tg3_get_5787_nvram_info(tp); | |
11814 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
11815 | tg3_get_5761_nvram_info(tp); | |
11816 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11817 | tg3_get_5906_nvram_info(tp); | |
11818 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
11819 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
11820 | tg3_get_57780_nvram_info(tp); | |
11821 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
11822 | tg3_get_5717_nvram_info(tp); | |
11823 | else | |
11824 | tg3_get_nvram_info(tp); | |
11825 | ||
11826 | if (tp->nvram_size == 0) | |
11827 | tg3_get_nvram_size(tp); | |
11828 | ||
11829 | tg3_disable_nvram_access(tp); | |
11830 | tg3_nvram_unlock(tp); | |
11831 | ||
11832 | } else { | |
11833 | tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); | |
11834 | ||
11835 | tg3_get_eeprom_size(tp); | |
11836 | } | |
11837 | } | |
11838 | ||
11839 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, | |
11840 | u32 offset, u32 len, u8 *buf) | |
11841 | { | |
11842 | int i, j, rc = 0; | |
11843 | u32 val; | |
11844 | ||
11845 | for (i = 0; i < len; i += 4) { | |
11846 | u32 addr; | |
11847 | __be32 data; | |
11848 | ||
11849 | addr = offset + i; | |
11850 | ||
11851 | memcpy(&data, buf + i, 4); | |
11852 | ||
11853 | /* | |
11854 | * The SEEPROM interface expects the data to always be opposite | |
11855 | * the native endian format. We accomplish this by reversing | |
11856 | * all the operations that would have been performed on the | |
11857 | * data from a call to tg3_nvram_read_be32(). | |
11858 | */ | |
11859 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
11860 | ||
11861 | val = tr32(GRC_EEPROM_ADDR); | |
11862 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
11863 | ||
11864 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
11865 | EEPROM_ADDR_READ); | |
11866 | tw32(GRC_EEPROM_ADDR, val | | |
11867 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
11868 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
11869 | EEPROM_ADDR_START | | |
11870 | EEPROM_ADDR_WRITE); | |
11871 | ||
11872 | for (j = 0; j < 1000; j++) { | |
11873 | val = tr32(GRC_EEPROM_ADDR); | |
11874 | ||
11875 | if (val & EEPROM_ADDR_COMPLETE) | |
11876 | break; | |
11877 | msleep(1); | |
11878 | } | |
11879 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
11880 | rc = -EBUSY; | |
11881 | break; | |
11882 | } | |
11883 | } | |
11884 | ||
11885 | return rc; | |
11886 | } | |
11887 | ||
11888 | /* offset and length are dword aligned */ | |
11889 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
11890 | u8 *buf) | |
11891 | { | |
11892 | int ret = 0; | |
11893 | u32 pagesize = tp->nvram_pagesize; | |
11894 | u32 pagemask = pagesize - 1; | |
11895 | u32 nvram_cmd; | |
11896 | u8 *tmp; | |
11897 | ||
11898 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
11899 | if (tmp == NULL) | |
11900 | return -ENOMEM; | |
11901 | ||
11902 | while (len) { | |
11903 | int j; | |
11904 | u32 phy_addr, page_off, size; | |
11905 | ||
11906 | phy_addr = offset & ~pagemask; | |
11907 | ||
11908 | for (j = 0; j < pagesize; j += 4) { | |
11909 | ret = tg3_nvram_read_be32(tp, phy_addr + j, | |
11910 | (__be32 *) (tmp + j)); | |
11911 | if (ret) | |
11912 | break; | |
11913 | } | |
11914 | if (ret) | |
11915 | break; | |
11916 | ||
11917 | page_off = offset & pagemask; | |
11918 | size = pagesize; | |
11919 | if (len < size) | |
11920 | size = len; | |
11921 | ||
11922 | len -= size; | |
11923 | ||
11924 | memcpy(tmp + page_off, buf, size); | |
11925 | ||
11926 | offset = offset + (pagesize - page_off); | |
11927 | ||
11928 | tg3_enable_nvram_access(tp); | |
11929 | ||
11930 | /* | |
11931 | * Before we can erase the flash page, we need | |
11932 | * to issue a special "write enable" command. | |
11933 | */ | |
11934 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11935 | ||
11936 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
11937 | break; | |
11938 | ||
11939 | /* Erase the target page */ | |
11940 | tw32(NVRAM_ADDR, phy_addr); | |
11941 | ||
11942 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
11943 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
11944 | ||
11945 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
11946 | break; | |
11947 | ||
11948 | /* Issue another write enable to start the write. */ | |
11949 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11950 | ||
11951 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
11952 | break; | |
11953 | ||
11954 | for (j = 0; j < pagesize; j += 4) { | |
11955 | __be32 data; | |
11956 | ||
11957 | data = *((__be32 *) (tmp + j)); | |
11958 | ||
11959 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
11960 | ||
11961 | tw32(NVRAM_ADDR, phy_addr + j); | |
11962 | ||
11963 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
11964 | NVRAM_CMD_WR; | |
11965 | ||
11966 | if (j == 0) | |
11967 | nvram_cmd |= NVRAM_CMD_FIRST; | |
11968 | else if (j == (pagesize - 4)) | |
11969 | nvram_cmd |= NVRAM_CMD_LAST; | |
11970 | ||
11971 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
11972 | break; | |
11973 | } | |
11974 | if (ret) | |
11975 | break; | |
11976 | } | |
11977 | ||
11978 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11979 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
11980 | ||
11981 | kfree(tmp); | |
11982 | ||
11983 | return ret; | |
11984 | } | |
11985 | ||
11986 | /* offset and length are dword aligned */ | |
11987 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
11988 | u8 *buf) | |
11989 | { | |
11990 | int i, ret = 0; | |
11991 | ||
11992 | for (i = 0; i < len; i += 4, offset += 4) { | |
11993 | u32 page_off, phy_addr, nvram_cmd; | |
11994 | __be32 data; | |
11995 | ||
11996 | memcpy(&data, buf + i, 4); | |
11997 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
11998 | ||
11999 | page_off = offset % tp->nvram_pagesize; | |
12000 | ||
12001 | phy_addr = tg3_nvram_phys_addr(tp, offset); | |
12002 | ||
12003 | tw32(NVRAM_ADDR, phy_addr); | |
12004 | ||
12005 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12006 | ||
12007 | if ((page_off == 0) || (i == 0)) | |
12008 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12009 | if (page_off == (tp->nvram_pagesize - 4)) | |
12010 | nvram_cmd |= NVRAM_CMD_LAST; | |
12011 | ||
12012 | if (i == (len - 4)) | |
12013 | nvram_cmd |= NVRAM_CMD_LAST; | |
12014 | ||
12015 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && | |
12016 | !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && | |
12017 | (tp->nvram_jedecnum == JEDEC_ST) && | |
12018 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
12019 | ||
12020 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12021 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12022 | NVRAM_CMD_DONE))) | |
12023 | ||
12024 | break; | |
12025 | } | |
12026 | if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
12027 | /* We always do complete word writes to eeprom. */ | |
12028 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12029 | } | |
12030 | ||
12031 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12032 | break; | |
12033 | } | |
12034 | return ret; | |
12035 | } | |
12036 | ||
12037 | /* offset and length are dword aligned */ | |
12038 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12039 | { | |
12040 | int ret; | |
12041 | ||
12042 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
12043 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & | |
12044 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
12045 | udelay(40); | |
12046 | } | |
12047 | ||
12048 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { | |
12049 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
12050 | } | |
12051 | else { | |
12052 | u32 grc_mode; | |
12053 | ||
12054 | ret = tg3_nvram_lock(tp); | |
12055 | if (ret) | |
12056 | return ret; | |
12057 | ||
12058 | tg3_enable_nvram_access(tp); | |
12059 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
12060 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) | |
12061 | tw32(NVRAM_WRITE1, 0x406); | |
12062 | ||
12063 | grc_mode = tr32(GRC_MODE); | |
12064 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12065 | ||
12066 | if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) || | |
12067 | !(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
12068 | ||
12069 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
12070 | buf); | |
12071 | } | |
12072 | else { | |
12073 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, | |
12074 | buf); | |
12075 | } | |
12076 | ||
12077 | grc_mode = tr32(GRC_MODE); | |
12078 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12079 | ||
12080 | tg3_disable_nvram_access(tp); | |
12081 | tg3_nvram_unlock(tp); | |
12082 | } | |
12083 | ||
12084 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
12085 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
12086 | udelay(40); | |
12087 | } | |
12088 | ||
12089 | return ret; | |
12090 | } | |
12091 | ||
12092 | struct subsys_tbl_ent { | |
12093 | u16 subsys_vendor, subsys_devid; | |
12094 | u32 phy_id; | |
12095 | }; | |
12096 | ||
12097 | static struct subsys_tbl_ent subsys_id_to_phy_id[] = { | |
12098 | /* Broadcom boards. */ | |
12099 | { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */ | |
12100 | { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */ | |
12101 | { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */ | |
12102 | { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */ | |
12103 | { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */ | |
12104 | { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */ | |
12105 | { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */ | |
12106 | { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */ | |
12107 | { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */ | |
12108 | { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */ | |
12109 | { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */ | |
12110 | ||
12111 | /* 3com boards. */ | |
12112 | { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */ | |
12113 | { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */ | |
12114 | { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */ | |
12115 | { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */ | |
12116 | { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */ | |
12117 | ||
12118 | /* DELL boards. */ | |
12119 | { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */ | |
12120 | { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */ | |
12121 | { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */ | |
12122 | { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */ | |
12123 | ||
12124 | /* Compaq boards. */ | |
12125 | { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */ | |
12126 | { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */ | |
12127 | { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */ | |
12128 | { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */ | |
12129 | { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */ | |
12130 | ||
12131 | /* IBM boards. */ | |
12132 | { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */ | |
12133 | }; | |
12134 | ||
12135 | static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp) | |
12136 | { | |
12137 | int i; | |
12138 | ||
12139 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12140 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12141 | tp->pdev->subsystem_vendor) && | |
12142 | (subsys_id_to_phy_id[i].subsys_devid == | |
12143 | tp->pdev->subsystem_device)) | |
12144 | return &subsys_id_to_phy_id[i]; | |
12145 | } | |
12146 | return NULL; | |
12147 | } | |
12148 | ||
12149 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) | |
12150 | { | |
12151 | u32 val; | |
12152 | u16 pmcsr; | |
12153 | ||
12154 | /* On some early chips the SRAM cannot be accessed in D3hot state, | |
12155 | * so need make sure we're in D0. | |
12156 | */ | |
12157 | pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
12158 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
12159 | pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); | |
12160 | msleep(1); | |
12161 | ||
12162 | /* Make sure register accesses (indirect or otherwise) | |
12163 | * will function correctly. | |
12164 | */ | |
12165 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12166 | tp->misc_host_ctrl); | |
12167 | ||
12168 | /* The memory arbiter has to be enabled in order for SRAM accesses | |
12169 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
12170 | * sure it is enabled, but other entities such as system netboot | |
12171 | * code might disable it. | |
12172 | */ | |
12173 | val = tr32(MEMARB_MODE); | |
12174 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
12175 | ||
12176 | tp->phy_id = PHY_ID_INVALID; | |
12177 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12178 | ||
12179 | /* Assume an onboard device and WOL capable by default. */ | |
12180 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; | |
12181 | ||
12182 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
12183 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { | |
12184 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
12185 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; | |
12186 | } | |
12187 | val = tr32(VCPU_CFGSHDW); | |
12188 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
12189 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
12190 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && | |
12191 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) | |
12192 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; | |
12193 | goto done; | |
12194 | } | |
12195 | ||
12196 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
12197 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12198 | u32 nic_cfg, led_cfg; | |
12199 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; | |
12200 | int eeprom_phy_serdes = 0; | |
12201 | ||
12202 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12203 | tp->nic_sram_data_cfg = nic_cfg; | |
12204 | ||
12205 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12206 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
12207 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && | |
12208 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && | |
12209 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) && | |
12210 | (ver > 0) && (ver < 0x100)) | |
12211 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12212 | ||
12213 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
12214 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12215 | ||
12216 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == | |
12217 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12218 | eeprom_phy_serdes = 1; | |
12219 | ||
12220 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12221 | if (nic_phy_id != 0) { | |
12222 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12223 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12224 | ||
12225 | eeprom_phy_id = (id1 >> 16) << 10; | |
12226 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
12227 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
12228 | } else | |
12229 | eeprom_phy_id = 0; | |
12230 | ||
12231 | tp->phy_id = eeprom_phy_id; | |
12232 | if (eeprom_phy_serdes) { | |
12233 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
12234 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
12235 | tp->tg3_flags2 |= TG3_FLG2_MII_SERDES; | |
12236 | else | |
12237 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
12238 | } | |
12239 | ||
12240 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) | |
12241 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | | |
12242 | SHASTA_EXT_LED_MODE_MASK); | |
12243 | else | |
12244 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; | |
12245 | ||
12246 | switch (led_cfg) { | |
12247 | default: | |
12248 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
12249 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12250 | break; | |
12251 | ||
12252 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
12253 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12254 | break; | |
12255 | ||
12256 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
12257 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
12258 | ||
12259 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
12260 | * read on some older 5700/5701 bootcode. | |
12261 | */ | |
12262 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12263 | ASIC_REV_5700 || | |
12264 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12265 | ASIC_REV_5701) | |
12266 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12267 | ||
12268 | break; | |
12269 | ||
12270 | case SHASTA_EXT_LED_SHARED: | |
12271 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
12272 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
12273 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
12274 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12275 | LED_CTRL_MODE_PHY_2); | |
12276 | break; | |
12277 | ||
12278 | case SHASTA_EXT_LED_MAC: | |
12279 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
12280 | break; | |
12281 | ||
12282 | case SHASTA_EXT_LED_COMBO: | |
12283 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
12284 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
12285 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12286 | LED_CTRL_MODE_PHY_2); | |
12287 | break; | |
12288 | ||
12289 | } | |
12290 | ||
12291 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12292 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
12293 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
12294 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12295 | ||
12296 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) | |
12297 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12298 | ||
12299 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { | |
12300 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; | |
12301 | if ((tp->pdev->subsystem_vendor == | |
12302 | PCI_VENDOR_ID_ARIMA) && | |
12303 | (tp->pdev->subsystem_device == 0x205a || | |
12304 | tp->pdev->subsystem_device == 0x2063)) | |
12305 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
12306 | } else { | |
12307 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
12308 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; | |
12309 | } | |
12310 | ||
12311 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
12312 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
12313 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) | |
12314 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; | |
12315 | } | |
12316 | ||
12317 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
12318 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
12319 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; | |
12320 | ||
12321 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES && | |
12322 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) | |
12323 | tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; | |
12324 | ||
12325 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && | |
12326 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) | |
12327 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; | |
12328 | ||
12329 | if (cfg2 & (1 << 17)) | |
12330 | tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING; | |
12331 | ||
12332 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
12333 | /* bootcode if bit 18 is set */ | |
12334 | if (cfg2 & (1 << 18)) | |
12335 | tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS; | |
12336 | ||
12337 | if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
12338 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
12339 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) | |
12340 | tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD; | |
12341 | ||
12342 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
12343 | u32 cfg3; | |
12344 | ||
12345 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
12346 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
12347 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
12348 | } | |
12349 | ||
12350 | if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE) | |
12351 | tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE; | |
12352 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) | |
12353 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN; | |
12354 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) | |
12355 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; | |
12356 | } | |
12357 | done: | |
12358 | device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP); | |
12359 | device_set_wakeup_enable(&tp->pdev->dev, | |
12360 | tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
12361 | } | |
12362 | ||
12363 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) | |
12364 | { | |
12365 | int i; | |
12366 | u32 val; | |
12367 | ||
12368 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
12369 | tw32(OTP_CTRL, cmd); | |
12370 | ||
12371 | /* Wait for up to 1 ms for command to execute. */ | |
12372 | for (i = 0; i < 100; i++) { | |
12373 | val = tr32(OTP_STATUS); | |
12374 | if (val & OTP_STATUS_CMD_DONE) | |
12375 | break; | |
12376 | udelay(10); | |
12377 | } | |
12378 | ||
12379 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
12380 | } | |
12381 | ||
12382 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
12383 | * configuration is a 32-bit value that straddles the alignment boundary. | |
12384 | * We do two 32-bit reads and then shift and merge the results. | |
12385 | */ | |
12386 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
12387 | { | |
12388 | u32 bhalf_otp, thalf_otp; | |
12389 | ||
12390 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
12391 | ||
12392 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
12393 | return 0; | |
12394 | ||
12395 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
12396 | ||
12397 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12398 | return 0; | |
12399 | ||
12400 | thalf_otp = tr32(OTP_READ_DATA); | |
12401 | ||
12402 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
12403 | ||
12404 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12405 | return 0; | |
12406 | ||
12407 | bhalf_otp = tr32(OTP_READ_DATA); | |
12408 | ||
12409 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
12410 | } | |
12411 | ||
12412 | static int __devinit tg3_phy_probe(struct tg3 *tp) | |
12413 | { | |
12414 | u32 hw_phy_id_1, hw_phy_id_2; | |
12415 | u32 hw_phy_id, hw_phy_id_masked; | |
12416 | int err; | |
12417 | ||
12418 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) | |
12419 | return tg3_phy_init(tp); | |
12420 | ||
12421 | /* Reading the PHY ID register can conflict with ASF | |
12422 | * firmware access to the PHY hardware. | |
12423 | */ | |
12424 | err = 0; | |
12425 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
12426 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
12427 | hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID; | |
12428 | } else { | |
12429 | /* Now read the physical PHY_ID from the chip and verify | |
12430 | * that it is sane. If it doesn't look good, we fall back | |
12431 | * to either the hard-coded table based PHY_ID and failing | |
12432 | * that the value found in the eeprom area. | |
12433 | */ | |
12434 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
12435 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
12436 | ||
12437 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
12438 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
12439 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
12440 | ||
12441 | hw_phy_id_masked = hw_phy_id & PHY_ID_MASK; | |
12442 | } | |
12443 | ||
12444 | if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) { | |
12445 | tp->phy_id = hw_phy_id; | |
12446 | if (hw_phy_id_masked == PHY_ID_BCM8002) | |
12447 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
12448 | else | |
12449 | tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES; | |
12450 | } else { | |
12451 | if (tp->phy_id != PHY_ID_INVALID) { | |
12452 | /* Do nothing, phy ID already set up in | |
12453 | * tg3_get_eeprom_hw_cfg(). | |
12454 | */ | |
12455 | } else { | |
12456 | struct subsys_tbl_ent *p; | |
12457 | ||
12458 | /* No eeprom signature? Try the hardcoded | |
12459 | * subsys device table. | |
12460 | */ | |
12461 | p = lookup_by_subsys(tp); | |
12462 | if (!p) | |
12463 | return -ENODEV; | |
12464 | ||
12465 | tp->phy_id = p->phy_id; | |
12466 | if (!tp->phy_id || | |
12467 | tp->phy_id == PHY_ID_BCM8002) | |
12468 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
12469 | } | |
12470 | } | |
12471 | ||
12472 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) && | |
12473 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) && | |
12474 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
12475 | u32 bmsr, adv_reg, tg3_ctrl, mask; | |
12476 | ||
12477 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
12478 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
12479 | (bmsr & BMSR_LSTATUS)) | |
12480 | goto skip_phy_reset; | |
12481 | ||
12482 | err = tg3_phy_reset(tp); | |
12483 | if (err) | |
12484 | return err; | |
12485 | ||
12486 | adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
12487 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
12488 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
12489 | tg3_ctrl = 0; | |
12490 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
12491 | tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF | | |
12492 | MII_TG3_CTRL_ADV_1000_FULL); | |
12493 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
12494 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
12495 | tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER | | |
12496 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
12497 | } | |
12498 | ||
12499 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
12500 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
12501 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
12502 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
12503 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
12504 | ||
12505 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
12506 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); | |
12507 | ||
12508 | tg3_writephy(tp, MII_BMCR, | |
12509 | BMCR_ANENABLE | BMCR_ANRESTART); | |
12510 | } | |
12511 | tg3_phy_set_wirespeed(tp); | |
12512 | ||
12513 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
12514 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
12515 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); | |
12516 | } | |
12517 | ||
12518 | skip_phy_reset: | |
12519 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
12520 | err = tg3_init_5401phy_dsp(tp); | |
12521 | if (err) | |
12522 | return err; | |
12523 | } | |
12524 | ||
12525 | if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) { | |
12526 | err = tg3_init_5401phy_dsp(tp); | |
12527 | } | |
12528 | ||
12529 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) | |
12530 | tp->link_config.advertising = | |
12531 | (ADVERTISED_1000baseT_Half | | |
12532 | ADVERTISED_1000baseT_Full | | |
12533 | ADVERTISED_Autoneg | | |
12534 | ADVERTISED_FIBRE); | |
12535 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) | |
12536 | tp->link_config.advertising &= | |
12537 | ~(ADVERTISED_1000baseT_Half | | |
12538 | ADVERTISED_1000baseT_Full); | |
12539 | ||
12540 | return err; | |
12541 | } | |
12542 | ||
12543 | static void __devinit tg3_read_partno(struct tg3 *tp) | |
12544 | { | |
12545 | unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */ | |
12546 | unsigned int i; | |
12547 | u32 magic; | |
12548 | ||
12549 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || | |
12550 | tg3_nvram_read(tp, 0x0, &magic)) | |
12551 | goto out_not_found; | |
12552 | ||
12553 | if (magic == TG3_EEPROM_MAGIC) { | |
12554 | for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) { | |
12555 | u32 tmp; | |
12556 | ||
12557 | /* The data is in little-endian format in NVRAM. | |
12558 | * Use the big-endian read routines to preserve | |
12559 | * the byte order as it exists in NVRAM. | |
12560 | */ | |
12561 | if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp)) | |
12562 | goto out_not_found; | |
12563 | ||
12564 | memcpy(&vpd_data[i], &tmp, sizeof(tmp)); | |
12565 | } | |
12566 | } else { | |
12567 | ssize_t cnt; | |
12568 | unsigned int pos = 0, i = 0; | |
12569 | ||
12570 | for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) { | |
12571 | cnt = pci_read_vpd(tp->pdev, pos, | |
12572 | TG3_NVM_VPD_LEN - pos, | |
12573 | &vpd_data[pos]); | |
12574 | if (cnt == -ETIMEDOUT || -EINTR) | |
12575 | cnt = 0; | |
12576 | else if (cnt < 0) | |
12577 | goto out_not_found; | |
12578 | } | |
12579 | if (pos != TG3_NVM_VPD_LEN) | |
12580 | goto out_not_found; | |
12581 | } | |
12582 | ||
12583 | /* Now parse and find the part number. */ | |
12584 | for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) { | |
12585 | unsigned char val = vpd_data[i]; | |
12586 | unsigned int block_end; | |
12587 | ||
12588 | if (val == 0x82 || val == 0x91) { | |
12589 | i = (i + 3 + | |
12590 | (vpd_data[i + 1] + | |
12591 | (vpd_data[i + 2] << 8))); | |
12592 | continue; | |
12593 | } | |
12594 | ||
12595 | if (val != 0x90) | |
12596 | goto out_not_found; | |
12597 | ||
12598 | block_end = (i + 3 + | |
12599 | (vpd_data[i + 1] + | |
12600 | (vpd_data[i + 2] << 8))); | |
12601 | i += 3; | |
12602 | ||
12603 | if (block_end > TG3_NVM_VPD_LEN) | |
12604 | goto out_not_found; | |
12605 | ||
12606 | while (i < (block_end - 2)) { | |
12607 | if (vpd_data[i + 0] == 'P' && | |
12608 | vpd_data[i + 1] == 'N') { | |
12609 | int partno_len = vpd_data[i + 2]; | |
12610 | ||
12611 | i += 3; | |
12612 | if (partno_len > TG3_BPN_SIZE || | |
12613 | (partno_len + i) > TG3_NVM_VPD_LEN) | |
12614 | goto out_not_found; | |
12615 | ||
12616 | memcpy(tp->board_part_number, | |
12617 | &vpd_data[i], partno_len); | |
12618 | ||
12619 | /* Success. */ | |
12620 | return; | |
12621 | } | |
12622 | i += 3 + vpd_data[i + 2]; | |
12623 | } | |
12624 | ||
12625 | /* Part number not found. */ | |
12626 | goto out_not_found; | |
12627 | } | |
12628 | ||
12629 | out_not_found: | |
12630 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
12631 | strcpy(tp->board_part_number, "BCM95906"); | |
12632 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && | |
12633 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
12634 | strcpy(tp->board_part_number, "BCM57780"); | |
12635 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && | |
12636 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
12637 | strcpy(tp->board_part_number, "BCM57760"); | |
12638 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && | |
12639 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
12640 | strcpy(tp->board_part_number, "BCM57790"); | |
12641 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && | |
12642 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
12643 | strcpy(tp->board_part_number, "BCM57788"); | |
12644 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
12645 | strcpy(tp->board_part_number, "BCM57765"); | |
12646 | else | |
12647 | strcpy(tp->board_part_number, "none"); | |
12648 | } | |
12649 | ||
12650 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) | |
12651 | { | |
12652 | u32 val; | |
12653 | ||
12654 | if (tg3_nvram_read(tp, offset, &val) || | |
12655 | (val & 0xfc000000) != 0x0c000000 || | |
12656 | tg3_nvram_read(tp, offset + 4, &val) || | |
12657 | val != 0) | |
12658 | return 0; | |
12659 | ||
12660 | return 1; | |
12661 | } | |
12662 | ||
12663 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) | |
12664 | { | |
12665 | u32 val, offset, start, ver_offset; | |
12666 | int i; | |
12667 | bool newver = false; | |
12668 | ||
12669 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
12670 | tg3_nvram_read(tp, 0x4, &start)) | |
12671 | return; | |
12672 | ||
12673 | offset = tg3_nvram_logical_addr(tp, offset); | |
12674 | ||
12675 | if (tg3_nvram_read(tp, offset, &val)) | |
12676 | return; | |
12677 | ||
12678 | if ((val & 0xfc000000) == 0x0c000000) { | |
12679 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
12680 | return; | |
12681 | ||
12682 | if (val == 0) | |
12683 | newver = true; | |
12684 | } | |
12685 | ||
12686 | if (newver) { | |
12687 | if (tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
12688 | return; | |
12689 | ||
12690 | offset = offset + ver_offset - start; | |
12691 | for (i = 0; i < 16; i += 4) { | |
12692 | __be32 v; | |
12693 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
12694 | return; | |
12695 | ||
12696 | memcpy(tp->fw_ver + i, &v, sizeof(v)); | |
12697 | } | |
12698 | } else { | |
12699 | u32 major, minor; | |
12700 | ||
12701 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
12702 | return; | |
12703 | ||
12704 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
12705 | TG3_NVM_BCVER_MAJSFT; | |
12706 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
12707 | snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor); | |
12708 | } | |
12709 | } | |
12710 | ||
12711 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) | |
12712 | { | |
12713 | u32 val, major, minor; | |
12714 | ||
12715 | /* Use native endian representation */ | |
12716 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
12717 | return; | |
12718 | ||
12719 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
12720 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
12721 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
12722 | TG3_NVM_HWSB_CFG1_MINSFT; | |
12723 | ||
12724 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
12725 | } | |
12726 | ||
12727 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) | |
12728 | { | |
12729 | u32 offset, major, minor, build; | |
12730 | ||
12731 | tp->fw_ver[0] = 's'; | |
12732 | tp->fw_ver[1] = 'b'; | |
12733 | tp->fw_ver[2] = '\0'; | |
12734 | ||
12735 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
12736 | return; | |
12737 | ||
12738 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
12739 | case TG3_EEPROM_SB_REVISION_0: | |
12740 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
12741 | break; | |
12742 | case TG3_EEPROM_SB_REVISION_2: | |
12743 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
12744 | break; | |
12745 | case TG3_EEPROM_SB_REVISION_3: | |
12746 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
12747 | break; | |
12748 | default: | |
12749 | return; | |
12750 | } | |
12751 | ||
12752 | if (tg3_nvram_read(tp, offset, &val)) | |
12753 | return; | |
12754 | ||
12755 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
12756 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
12757 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
12758 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
12759 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
12760 | ||
12761 | if (minor > 99 || build > 26) | |
12762 | return; | |
12763 | ||
12764 | snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor); | |
12765 | ||
12766 | if (build > 0) { | |
12767 | tp->fw_ver[8] = 'a' + build - 1; | |
12768 | tp->fw_ver[9] = '\0'; | |
12769 | } | |
12770 | } | |
12771 | ||
12772 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) | |
12773 | { | |
12774 | u32 val, offset, start; | |
12775 | int i, vlen; | |
12776 | ||
12777 | for (offset = TG3_NVM_DIR_START; | |
12778 | offset < TG3_NVM_DIR_END; | |
12779 | offset += TG3_NVM_DIRENT_SIZE) { | |
12780 | if (tg3_nvram_read(tp, offset, &val)) | |
12781 | return; | |
12782 | ||
12783 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) | |
12784 | break; | |
12785 | } | |
12786 | ||
12787 | if (offset == TG3_NVM_DIR_END) | |
12788 | return; | |
12789 | ||
12790 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
12791 | start = 0x08000000; | |
12792 | else if (tg3_nvram_read(tp, offset - 4, &start)) | |
12793 | return; | |
12794 | ||
12795 | if (tg3_nvram_read(tp, offset + 4, &offset) || | |
12796 | !tg3_fw_img_is_valid(tp, offset) || | |
12797 | tg3_nvram_read(tp, offset + 8, &val)) | |
12798 | return; | |
12799 | ||
12800 | offset += val - start; | |
12801 | ||
12802 | vlen = strlen(tp->fw_ver); | |
12803 | ||
12804 | tp->fw_ver[vlen++] = ','; | |
12805 | tp->fw_ver[vlen++] = ' '; | |
12806 | ||
12807 | for (i = 0; i < 4; i++) { | |
12808 | __be32 v; | |
12809 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
12810 | return; | |
12811 | ||
12812 | offset += sizeof(v); | |
12813 | ||
12814 | if (vlen > TG3_VER_SIZE - sizeof(v)) { | |
12815 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
12816 | break; | |
12817 | } | |
12818 | ||
12819 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); | |
12820 | vlen += sizeof(v); | |
12821 | } | |
12822 | } | |
12823 | ||
12824 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) | |
12825 | { | |
12826 | int vlen; | |
12827 | u32 apedata; | |
12828 | ||
12829 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || | |
12830 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
12831 | return; | |
12832 | ||
12833 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
12834 | if (apedata != APE_SEG_SIG_MAGIC) | |
12835 | return; | |
12836 | ||
12837 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
12838 | if (!(apedata & APE_FW_STATUS_READY)) | |
12839 | return; | |
12840 | ||
12841 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
12842 | ||
12843 | vlen = strlen(tp->fw_ver); | |
12844 | ||
12845 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d", | |
12846 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, | |
12847 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
12848 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
12849 | (apedata & APE_FW_VERSION_BLDMSK)); | |
12850 | } | |
12851 | ||
12852 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) | |
12853 | { | |
12854 | u32 val; | |
12855 | ||
12856 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { | |
12857 | tp->fw_ver[0] = 's'; | |
12858 | tp->fw_ver[1] = 'b'; | |
12859 | tp->fw_ver[2] = '\0'; | |
12860 | ||
12861 | return; | |
12862 | } | |
12863 | ||
12864 | if (tg3_nvram_read(tp, 0, &val)) | |
12865 | return; | |
12866 | ||
12867 | if (val == TG3_EEPROM_MAGIC) | |
12868 | tg3_read_bc_ver(tp); | |
12869 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
12870 | tg3_read_sb_ver(tp, val); | |
12871 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) | |
12872 | tg3_read_hwsb_ver(tp); | |
12873 | else | |
12874 | return; | |
12875 | ||
12876 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
12877 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
12878 | return; | |
12879 | ||
12880 | tg3_read_mgmtfw_ver(tp); | |
12881 | ||
12882 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; | |
12883 | } | |
12884 | ||
12885 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); | |
12886 | ||
12887 | static int __devinit tg3_get_invariants(struct tg3 *tp) | |
12888 | { | |
12889 | static struct pci_device_id write_reorder_chipsets[] = { | |
12890 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, | |
12891 | PCI_DEVICE_ID_AMD_FE_GATE_700C) }, | |
12892 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, | |
12893 | PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
12894 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, | |
12895 | PCI_DEVICE_ID_VIA_8385_0) }, | |
12896 | { }, | |
12897 | }; | |
12898 | u32 misc_ctrl_reg; | |
12899 | u32 pci_state_reg, grc_misc_cfg; | |
12900 | u32 val; | |
12901 | u16 pci_cmd; | |
12902 | int err; | |
12903 | ||
12904 | /* Force memory write invalidate off. If we leave it on, | |
12905 | * then on 5700_BX chips we have to enable a workaround. | |
12906 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
12907 | * to match the cacheline size. The Broadcom driver have this | |
12908 | * workaround but turns MWI off all the times so never uses | |
12909 | * it. This seems to suggest that the workaround is insufficient. | |
12910 | */ | |
12911 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
12912 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
12913 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
12914 | ||
12915 | /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL | |
12916 | * has the register indirect write enable bit set before | |
12917 | * we try to access any of the MMIO registers. It is also | |
12918 | * critical that the PCI-X hw workaround situation is decided | |
12919 | * before that as well. | |
12920 | */ | |
12921 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12922 | &misc_ctrl_reg); | |
12923 | ||
12924 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
12925 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
12926 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { | |
12927 | u32 prod_id_asic_rev; | |
12928 | ||
12929 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
12930 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
12931 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724) | |
12932 | pci_read_config_dword(tp->pdev, | |
12933 | TG3PCI_GEN2_PRODID_ASICREV, | |
12934 | &prod_id_asic_rev); | |
12935 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || | |
12936 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
12937 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
12938 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
12939 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
12940 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
12941 | pci_read_config_dword(tp->pdev, | |
12942 | TG3PCI_GEN15_PRODID_ASICREV, | |
12943 | &prod_id_asic_rev); | |
12944 | else | |
12945 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
12946 | &prod_id_asic_rev); | |
12947 | ||
12948 | tp->pci_chip_rev_id = prod_id_asic_rev; | |
12949 | } | |
12950 | ||
12951 | /* Wrong chip ID in 5752 A0. This code can be removed later | |
12952 | * as A0 is not in production. | |
12953 | */ | |
12954 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
12955 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
12956 | ||
12957 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, | |
12958 | * we need to disable memory and use config. cycles | |
12959 | * only to access all registers. The 5702/03 chips | |
12960 | * can mistakenly decode the special cycles from the | |
12961 | * ICH chipsets as memory write cycles, causing corruption | |
12962 | * of register and memory space. Only certain ICH bridges | |
12963 | * will drive special cycles with non-zero data during the | |
12964 | * address phase which can fall within the 5703's address | |
12965 | * range. This is not an ICH bug as the PCI spec allows | |
12966 | * non-zero address during special cycles. However, only | |
12967 | * these ICH bridges are known to drive non-zero addresses | |
12968 | * during special cycles. | |
12969 | * | |
12970 | * Since special cycles do not cross PCI bridges, we only | |
12971 | * enable this workaround if the 5703 is on the secondary | |
12972 | * bus of these ICH bridges. | |
12973 | */ | |
12974 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
12975 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
12976 | static struct tg3_dev_id { | |
12977 | u32 vendor; | |
12978 | u32 device; | |
12979 | u32 rev; | |
12980 | } ich_chipsets[] = { | |
12981 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
12982 | PCI_ANY_ID }, | |
12983 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
12984 | PCI_ANY_ID }, | |
12985 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
12986 | 0xa }, | |
12987 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
12988 | PCI_ANY_ID }, | |
12989 | { }, | |
12990 | }; | |
12991 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
12992 | struct pci_dev *bridge = NULL; | |
12993 | ||
12994 | while (pci_id->vendor != 0) { | |
12995 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
12996 | bridge); | |
12997 | if (!bridge) { | |
12998 | pci_id++; | |
12999 | continue; | |
13000 | } | |
13001 | if (pci_id->rev != PCI_ANY_ID) { | |
13002 | if (bridge->revision > pci_id->rev) | |
13003 | continue; | |
13004 | } | |
13005 | if (bridge->subordinate && | |
13006 | (bridge->subordinate->number == | |
13007 | tp->pdev->bus->number)) { | |
13008 | ||
13009 | tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND; | |
13010 | pci_dev_put(bridge); | |
13011 | break; | |
13012 | } | |
13013 | } | |
13014 | } | |
13015 | ||
13016 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
13017 | static struct tg3_dev_id { | |
13018 | u32 vendor; | |
13019 | u32 device; | |
13020 | } bridge_chipsets[] = { | |
13021 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13022 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13023 | { }, | |
13024 | }; | |
13025 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13026 | struct pci_dev *bridge = NULL; | |
13027 | ||
13028 | while (pci_id->vendor != 0) { | |
13029 | bridge = pci_get_device(pci_id->vendor, | |
13030 | pci_id->device, | |
13031 | bridge); | |
13032 | if (!bridge) { | |
13033 | pci_id++; | |
13034 | continue; | |
13035 | } | |
13036 | if (bridge->subordinate && | |
13037 | (bridge->subordinate->number <= | |
13038 | tp->pdev->bus->number) && | |
13039 | (bridge->subordinate->subordinate >= | |
13040 | tp->pdev->bus->number)) { | |
13041 | tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG; | |
13042 | pci_dev_put(bridge); | |
13043 | break; | |
13044 | } | |
13045 | } | |
13046 | } | |
13047 | ||
13048 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support | |
13049 | * DMA addresses > 40-bit. This bridge may have other additional | |
13050 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13051 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13052 | * DMA workaround. | |
13053 | */ | |
13054 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || | |
13055 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
13056 | tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; | |
13057 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
13058 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); | |
13059 | } | |
13060 | else { | |
13061 | struct pci_dev *bridge = NULL; | |
13062 | ||
13063 | do { | |
13064 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13065 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13066 | bridge); | |
13067 | if (bridge && bridge->subordinate && | |
13068 | (bridge->subordinate->number <= | |
13069 | tp->pdev->bus->number) && | |
13070 | (bridge->subordinate->subordinate >= | |
13071 | tp->pdev->bus->number)) { | |
13072 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
13073 | pci_dev_put(bridge); | |
13074 | break; | |
13075 | } | |
13076 | } while (bridge); | |
13077 | } | |
13078 | ||
13079 | /* Initialize misc host control in PCI block. */ | |
13080 | tp->misc_host_ctrl |= (misc_ctrl_reg & | |
13081 | MISC_HOST_CTRL_CHIPREV); | |
13082 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13083 | tp->misc_host_ctrl); | |
13084 | ||
13085 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
13086 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
13087 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
13088 | tp->pdev_peer = tg3_find_peer(tp); | |
13089 | ||
13090 | /* Intentionally exclude ASIC_REV_5906 */ | |
13091 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
13092 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
13093 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
13094 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
13095 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
13096 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
13097 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
13098 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
13099 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; | |
13100 | ||
13101 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13102 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
13103 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || | |
13104 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
13105 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
13106 | tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; | |
13107 | ||
13108 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || | |
13109 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
13110 | tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; | |
13111 | ||
13112 | /* 5700 B0 chips do not support checksumming correctly due | |
13113 | * to hardware bugs. | |
13114 | */ | |
13115 | if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0) | |
13116 | tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS; | |
13117 | else { | |
13118 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
13119 | tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; | |
13120 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
13121 | tp->dev->features |= NETIF_F_IPV6_CSUM; | |
13122 | } | |
13123 | ||
13124 | /* Determine TSO capabilities */ | |
13125 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
13126 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
13127 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; | |
13128 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
13129 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
13130 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; | |
13131 | else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
13132 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG; | |
13133 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && | |
13134 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
13135 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG; | |
13136 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13137 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13138 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
13139 | tp->tg3_flags2 |= TG3_FLG2_TSO_BUG; | |
13140 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) | |
13141 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13142 | else | |
13143 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13144 | } | |
13145 | ||
13146 | tp->irq_max = 1; | |
13147 | ||
13148 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
13149 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; | |
13150 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | |
13151 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13152 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13153 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13154 | tp->pdev_peer == tp->pdev)) | |
13155 | tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; | |
13156 | ||
13157 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
13158 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
13159 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; | |
13160 | } | |
13161 | ||
13162 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
13163 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13164 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX; | |
13165 | tp->irq_max = TG3_IRQ_MAX_VECS; | |
13166 | } | |
13167 | } | |
13168 | ||
13169 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
13170 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
13171 | tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG; | |
13172 | else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) { | |
13173 | tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG; | |
13174 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; | |
13175 | } | |
13176 | ||
13177 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
13178 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
13179 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; | |
13180 | ||
13181 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
13182 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
13183 | (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG)) | |
13184 | tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; | |
13185 | ||
13186 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
13187 | &pci_state_reg); | |
13188 | ||
13189 | tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); | |
13190 | if (tp->pcie_cap != 0) { | |
13191 | u16 lnkctl; | |
13192 | ||
13193 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; | |
13194 | ||
13195 | pcie_set_readrq(tp->pdev, 4096); | |
13196 | ||
13197 | pci_read_config_word(tp->pdev, | |
13198 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
13199 | &lnkctl); | |
13200 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
13201 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
13202 | tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; | |
13203 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
13204 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
13205 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || | |
13206 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
13207 | tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; | |
13208 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { | |
13209 | tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN; | |
13210 | } | |
13211 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
13212 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; | |
13213 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
13214 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
13215 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); | |
13216 | if (!tp->pcix_cap) { | |
13217 | printk(KERN_ERR PFX "Cannot find PCI-X " | |
13218 | "capability, aborting.\n"); | |
13219 | return -EIO; | |
13220 | } | |
13221 | ||
13222 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
13223 | tp->tg3_flags |= TG3_FLAG_PCIX_MODE; | |
13224 | } | |
13225 | ||
13226 | /* If we have an AMD 762 or VIA K8T800 chipset, write | |
13227 | * reordering to the mailbox registers done by the host | |
13228 | * controller can cause major troubles. We read back from | |
13229 | * every mailbox register write to force the writes to be | |
13230 | * posted to the chip in order. | |
13231 | */ | |
13232 | if (pci_dev_present(write_reorder_chipsets) && | |
13233 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
13234 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
13235 | ||
13236 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
13237 | &tp->pci_cacheline_sz); | |
13238 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13239 | &tp->pci_lat_timer); | |
13240 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
13241 | tp->pci_lat_timer < 64) { | |
13242 | tp->pci_lat_timer = 64; | |
13243 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13244 | tp->pci_lat_timer); | |
13245 | } | |
13246 | ||
13247 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { | |
13248 | /* 5700 BX chips need to have their TX producer index | |
13249 | * mailboxes written twice to workaround a bug. | |
13250 | */ | |
13251 | tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; | |
13252 | ||
13253 | /* If we are in PCI-X mode, enable register write workaround. | |
13254 | * | |
13255 | * The workaround is to use indirect register accesses | |
13256 | * for all chip writes not to mailbox registers. | |
13257 | */ | |
13258 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
13259 | u32 pm_reg; | |
13260 | ||
13261 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13262 | ||
13263 | /* The chip can have it's power management PCI config | |
13264 | * space registers clobbered due to this bug. | |
13265 | * So explicitly force the chip into D0 here. | |
13266 | */ | |
13267 | pci_read_config_dword(tp->pdev, | |
13268 | tp->pm_cap + PCI_PM_CTRL, | |
13269 | &pm_reg); | |
13270 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
13271 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
13272 | pci_write_config_dword(tp->pdev, | |
13273 | tp->pm_cap + PCI_PM_CTRL, | |
13274 | pm_reg); | |
13275 | ||
13276 | /* Also, force SERR#/PERR# in PCI command. */ | |
13277 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13278 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
13279 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13280 | } | |
13281 | } | |
13282 | ||
13283 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) | |
13284 | tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; | |
13285 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) | |
13286 | tp->tg3_flags |= TG3_FLAG_PCI_32BIT; | |
13287 | ||
13288 | /* Chip-specific fixup from Broadcom driver */ | |
13289 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
13290 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
13291 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
13292 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
13293 | } | |
13294 | ||
13295 | /* Default fast path register access methods */ | |
13296 | tp->read32 = tg3_read32; | |
13297 | tp->write32 = tg3_write32; | |
13298 | tp->read32_mbox = tg3_read32; | |
13299 | tp->write32_mbox = tg3_write32; | |
13300 | tp->write32_tx_mbox = tg3_write32; | |
13301 | tp->write32_rx_mbox = tg3_write32; | |
13302 | ||
13303 | /* Various workaround register access methods */ | |
13304 | if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) | |
13305 | tp->write32 = tg3_write_indirect_reg32; | |
13306 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || | |
13307 | ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
13308 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | |
13309 | /* | |
13310 | * Back to back register writes can cause problems on these | |
13311 | * chips, the workaround is to read back all reg writes | |
13312 | * except those to mailbox regs. | |
13313 | * | |
13314 | * See tg3_write_indirect_reg32(). | |
13315 | */ | |
13316 | tp->write32 = tg3_write_flush_reg32; | |
13317 | } | |
13318 | ||
13319 | if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || | |
13320 | (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { | |
13321 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
13322 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
13323 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
13324 | } | |
13325 | ||
13326 | if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) { | |
13327 | tp->read32 = tg3_read_indirect_reg32; | |
13328 | tp->write32 = tg3_write_indirect_reg32; | |
13329 | tp->read32_mbox = tg3_read_indirect_mbox; | |
13330 | tp->write32_mbox = tg3_write_indirect_mbox; | |
13331 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
13332 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
13333 | ||
13334 | iounmap(tp->regs); | |
13335 | tp->regs = NULL; | |
13336 | ||
13337 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13338 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
13339 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13340 | } | |
13341 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
13342 | tp->read32_mbox = tg3_read32_mbox_5906; | |
13343 | tp->write32_mbox = tg3_write32_mbox_5906; | |
13344 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
13345 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
13346 | } | |
13347 | ||
13348 | if (tp->write32 == tg3_write_indirect_reg32 || | |
13349 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
13350 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13351 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) | |
13352 | tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; | |
13353 | ||
13354 | /* Get eeprom hw config before calling tg3_set_power_state(). | |
13355 | * In particular, the TG3_FLG2_IS_NIC flag must be | |
13356 | * determined before calling tg3_set_power_state() so that | |
13357 | * we know whether or not to switch out of Vaux power. | |
13358 | * When the flag is set, it means that GPIO1 is used for eeprom | |
13359 | * write protect and also implies that it is a LOM where GPIOs | |
13360 | * are not used to switch power. | |
13361 | */ | |
13362 | tg3_get_eeprom_hw_cfg(tp); | |
13363 | ||
13364 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { | |
13365 | /* Allow reads and writes to the | |
13366 | * APE register and memory space. | |
13367 | */ | |
13368 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
13369 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
13370 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
13371 | pci_state_reg); | |
13372 | } | |
13373 | ||
13374 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
13375 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
13376 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
13377 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
13378 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
13379 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
13380 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; | |
13381 | ||
13382 | /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). | |
13383 | * GPIO1 driven high will bring 5700's external PHY out of reset. | |
13384 | * It is also used as eeprom write protect on LOMs. | |
13385 | */ | |
13386 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
13387 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13388 | (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) | |
13389 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
13390 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
13391 | /* Unused GPIO3 must be driven as output on 5752 because there | |
13392 | * are no pull-up resistors on unused GPIO pins. | |
13393 | */ | |
13394 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
13395 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
13396 | ||
13397 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
13398 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
13399 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
13400 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
13401 | ||
13402 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
13403 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
13404 | /* Turn off the debug UART. */ | |
13405 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
13406 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
13407 | /* Keep VMain power. */ | |
13408 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
13409 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
13410 | } | |
13411 | ||
13412 | /* Force the chip into D0. */ | |
13413 | err = tg3_set_power_state(tp, PCI_D0); | |
13414 | if (err) { | |
13415 | printk(KERN_ERR PFX "(%s) transition to D0 failed\n", | |
13416 | pci_name(tp->pdev)); | |
13417 | return err; | |
13418 | } | |
13419 | ||
13420 | /* Derive initial jumbo mode from MTU assigned in | |
13421 | * ether_setup() via the alloc_etherdev() call | |
13422 | */ | |
13423 | if (tp->dev->mtu > ETH_DATA_LEN && | |
13424 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
13425 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; | |
13426 | ||
13427 | /* Determine WakeOnLan speed to use. */ | |
13428 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13429 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
13430 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
13431 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
13432 | tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB); | |
13433 | } else { | |
13434 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; | |
13435 | } | |
13436 | ||
13437 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
13438 | tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; | |
13439 | ||
13440 | /* A few boards don't want Ethernet@WireSpeed phy feature */ | |
13441 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13442 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
13443 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | |
13444 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || | |
13445 | (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) || | |
13446 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
13447 | tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; | |
13448 | ||
13449 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
13450 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
13451 | tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG; | |
13452 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) | |
13453 | tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; | |
13454 | ||
13455 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
13456 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && | |
13457 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
13458 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && | |
13459 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
13460 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) { | |
13461 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
13462 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
13463 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
13464 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
13465 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && | |
13466 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
13467 | tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG; | |
13468 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) | |
13469 | tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM; | |
13470 | } else | |
13471 | tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; | |
13472 | } | |
13473 | ||
13474 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
13475 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
13476 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
13477 | if (tp->phy_otp == 0) | |
13478 | tp->phy_otp = TG3_OTP_DEFAULT; | |
13479 | } | |
13480 | ||
13481 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) | |
13482 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; | |
13483 | else | |
13484 | tp->mi_mode = MAC_MI_MODE_BASE; | |
13485 | ||
13486 | tp->coalesce_mode = 0; | |
13487 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && | |
13488 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
13489 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
13490 | ||
13491 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
13492 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
13493 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; | |
13494 | ||
13495 | err = tg3_mdio_init(tp); | |
13496 | if (err) | |
13497 | return err; | |
13498 | ||
13499 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | |
13500 | (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 || | |
13501 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) | |
13502 | return -ENOTSUPP; | |
13503 | ||
13504 | /* Initialize data/descriptor byte/word swapping. */ | |
13505 | val = tr32(GRC_MODE); | |
13506 | val &= GRC_MODE_HOST_STACKUP; | |
13507 | tw32(GRC_MODE, val | tp->grc_mode); | |
13508 | ||
13509 | tg3_switch_clocks(tp); | |
13510 | ||
13511 | /* Clear this out for sanity. */ | |
13512 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
13513 | ||
13514 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
13515 | &pci_state_reg); | |
13516 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
13517 | (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) { | |
13518 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); | |
13519 | ||
13520 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
13521 | chiprevid == CHIPREV_ID_5701_B0 || | |
13522 | chiprevid == CHIPREV_ID_5701_B2 || | |
13523 | chiprevid == CHIPREV_ID_5701_B5) { | |
13524 | void __iomem *sram_base; | |
13525 | ||
13526 | /* Write some dummy words into the SRAM status block | |
13527 | * area, see if it reads back correctly. If the return | |
13528 | * value is bad, force enable the PCIX workaround. | |
13529 | */ | |
13530 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
13531 | ||
13532 | writel(0x00000000, sram_base); | |
13533 | writel(0x00000000, sram_base + 4); | |
13534 | writel(0xffffffff, sram_base + 4); | |
13535 | if (readl(sram_base) != 0x00000000) | |
13536 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13537 | } | |
13538 | } | |
13539 | ||
13540 | udelay(50); | |
13541 | tg3_nvram_init(tp); | |
13542 | ||
13543 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
13544 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
13545 | ||
13546 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
13547 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
13548 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
13549 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; | |
13550 | ||
13551 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
13552 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) | |
13553 | tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; | |
13554 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
13555 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | |
13556 | HOSTCC_MODE_CLRTICK_TXBD); | |
13557 | ||
13558 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
13559 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13560 | tp->misc_host_ctrl); | |
13561 | } | |
13562 | ||
13563 | /* Preserve the APE MAC_MODE bits */ | |
13564 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
13565 | tp->mac_mode = tr32(MAC_MODE) | | |
13566 | MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
13567 | else | |
13568 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
13569 | ||
13570 | /* these are limited to 10/100 only */ | |
13571 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
13572 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
13573 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
13574 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
13575 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
13576 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
13577 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
13578 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
13579 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
13580 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || | |
13581 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
13582 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || | |
13583 | (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) | |
13584 | tp->tg3_flags |= TG3_FLAG_10_100_ONLY; | |
13585 | ||
13586 | err = tg3_phy_probe(tp); | |
13587 | if (err) { | |
13588 | printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n", | |
13589 | pci_name(tp->pdev), err); | |
13590 | /* ... but do not return immediately ... */ | |
13591 | tg3_mdio_fini(tp); | |
13592 | } | |
13593 | ||
13594 | tg3_read_partno(tp); | |
13595 | tg3_read_fw_ver(tp); | |
13596 | ||
13597 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
13598 | tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT; | |
13599 | } else { | |
13600 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
13601 | tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT; | |
13602 | else | |
13603 | tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT; | |
13604 | } | |
13605 | ||
13606 | /* 5700 {AX,BX} chips have a broken status block link | |
13607 | * change bit implementation, so we must use the | |
13608 | * status register in those cases. | |
13609 | */ | |
13610 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
13611 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
13612 | else | |
13613 | tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG; | |
13614 | ||
13615 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
13616 | * have to force the link status polling mechanism based | |
13617 | * upon subsystem IDs. | |
13618 | */ | |
13619 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
13620 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && | |
13621 | !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
13622 | tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT | | |
13623 | TG3_FLAG_USE_LINKCHG_REG); | |
13624 | } | |
13625 | ||
13626 | /* For all SERDES we poll the MAC status register. */ | |
13627 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
13628 | tp->tg3_flags |= TG3_FLAG_POLL_SERDES; | |
13629 | else | |
13630 | tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; | |
13631 | ||
13632 | tp->rx_offset = NET_IP_ALIGN; | |
13633 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && | |
13634 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) | |
13635 | tp->rx_offset = 0; | |
13636 | ||
13637 | tp->rx_std_max_post = TG3_RX_RING_SIZE; | |
13638 | ||
13639 | /* Increment the rx prod index on the rx std ring by at most | |
13640 | * 8 for these chips to workaround hw errata. | |
13641 | */ | |
13642 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13643 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
13644 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
13645 | tp->rx_std_max_post = 8; | |
13646 | ||
13647 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) | |
13648 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & | |
13649 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
13650 | ||
13651 | return err; | |
13652 | } | |
13653 | ||
13654 | #ifdef CONFIG_SPARC | |
13655 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) | |
13656 | { | |
13657 | struct net_device *dev = tp->dev; | |
13658 | struct pci_dev *pdev = tp->pdev; | |
13659 | struct device_node *dp = pci_device_to_OF_node(pdev); | |
13660 | const unsigned char *addr; | |
13661 | int len; | |
13662 | ||
13663 | addr = of_get_property(dp, "local-mac-address", &len); | |
13664 | if (addr && len == 6) { | |
13665 | memcpy(dev->dev_addr, addr, 6); | |
13666 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
13667 | return 0; | |
13668 | } | |
13669 | return -ENODEV; | |
13670 | } | |
13671 | ||
13672 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
13673 | { | |
13674 | struct net_device *dev = tp->dev; | |
13675 | ||
13676 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
13677 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); | |
13678 | return 0; | |
13679 | } | |
13680 | #endif | |
13681 | ||
13682 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
13683 | { | |
13684 | struct net_device *dev = tp->dev; | |
13685 | u32 hi, lo, mac_offset; | |
13686 | int addr_ok = 0; | |
13687 | ||
13688 | #ifdef CONFIG_SPARC | |
13689 | if (!tg3_get_macaddr_sparc(tp)) | |
13690 | return 0; | |
13691 | #endif | |
13692 | ||
13693 | mac_offset = 0x7c; | |
13694 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || | |
13695 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
13696 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
13697 | mac_offset = 0xcc; | |
13698 | if (tg3_nvram_lock(tp)) | |
13699 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
13700 | else | |
13701 | tg3_nvram_unlock(tp); | |
13702 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
13703 | if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC) | |
13704 | mac_offset = 0xcc; | |
13705 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
13706 | mac_offset = 0x10; | |
13707 | ||
13708 | /* First try to get it from MAC address mailbox. */ | |
13709 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
13710 | if ((hi >> 16) == 0x484b) { | |
13711 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
13712 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
13713 | ||
13714 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
13715 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
13716 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
13717 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
13718 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
13719 | ||
13720 | /* Some old bootcode may report a 0 MAC address in SRAM */ | |
13721 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
13722 | } | |
13723 | if (!addr_ok) { | |
13724 | /* Next, try NVRAM. */ | |
13725 | if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) && | |
13726 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && | |
13727 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { | |
13728 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); | |
13729 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
13730 | } | |
13731 | /* Finally just fetch it out of the MAC control regs. */ | |
13732 | else { | |
13733 | hi = tr32(MAC_ADDR_0_HIGH); | |
13734 | lo = tr32(MAC_ADDR_0_LOW); | |
13735 | ||
13736 | dev->dev_addr[5] = lo & 0xff; | |
13737 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
13738 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
13739 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
13740 | dev->dev_addr[1] = hi & 0xff; | |
13741 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
13742 | } | |
13743 | } | |
13744 | ||
13745 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
13746 | #ifdef CONFIG_SPARC | |
13747 | if (!tg3_get_default_macaddr_sparc(tp)) | |
13748 | return 0; | |
13749 | #endif | |
13750 | return -EINVAL; | |
13751 | } | |
13752 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
13753 | return 0; | |
13754 | } | |
13755 | ||
13756 | #define BOUNDARY_SINGLE_CACHELINE 1 | |
13757 | #define BOUNDARY_MULTI_CACHELINE 2 | |
13758 | ||
13759 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
13760 | { | |
13761 | int cacheline_size; | |
13762 | u8 byte; | |
13763 | int goal; | |
13764 | ||
13765 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
13766 | if (byte == 0) | |
13767 | cacheline_size = 1024; | |
13768 | else | |
13769 | cacheline_size = (int) byte * 4; | |
13770 | ||
13771 | /* On 5703 and later chips, the boundary bits have no | |
13772 | * effect. | |
13773 | */ | |
13774 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13775 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13776 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
13777 | goto out; | |
13778 | ||
13779 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
13780 | goal = BOUNDARY_MULTI_CACHELINE; | |
13781 | #else | |
13782 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
13783 | goal = BOUNDARY_SINGLE_CACHELINE; | |
13784 | #else | |
13785 | goal = 0; | |
13786 | #endif | |
13787 | #endif | |
13788 | ||
13789 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
13790 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13791 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
13792 | goto out; | |
13793 | } | |
13794 | ||
13795 | if (!goal) | |
13796 | goto out; | |
13797 | ||
13798 | /* PCI controllers on most RISC systems tend to disconnect | |
13799 | * when a device tries to burst across a cache-line boundary. | |
13800 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
13801 | * | |
13802 | * Unfortunately, for PCI-E there are only limited | |
13803 | * write-side controls for this, and thus for reads | |
13804 | * we will still get the disconnects. We'll also waste | |
13805 | * these PCI cycles for both read and write for chips | |
13806 | * other than 5700 and 5701 which do not implement the | |
13807 | * boundary bits. | |
13808 | */ | |
13809 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
13810 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
13811 | switch (cacheline_size) { | |
13812 | case 16: | |
13813 | case 32: | |
13814 | case 64: | |
13815 | case 128: | |
13816 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13817 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
13818 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
13819 | } else { | |
13820 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
13821 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
13822 | } | |
13823 | break; | |
13824 | ||
13825 | case 256: | |
13826 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
13827 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
13828 | break; | |
13829 | ||
13830 | default: | |
13831 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
13832 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
13833 | break; | |
13834 | } | |
13835 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
13836 | switch (cacheline_size) { | |
13837 | case 16: | |
13838 | case 32: | |
13839 | case 64: | |
13840 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13841 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
13842 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
13843 | break; | |
13844 | } | |
13845 | /* fallthrough */ | |
13846 | case 128: | |
13847 | default: | |
13848 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
13849 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
13850 | break; | |
13851 | } | |
13852 | } else { | |
13853 | switch (cacheline_size) { | |
13854 | case 16: | |
13855 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13856 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
13857 | DMA_RWCTRL_WRITE_BNDRY_16); | |
13858 | break; | |
13859 | } | |
13860 | /* fallthrough */ | |
13861 | case 32: | |
13862 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13863 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
13864 | DMA_RWCTRL_WRITE_BNDRY_32); | |
13865 | break; | |
13866 | } | |
13867 | /* fallthrough */ | |
13868 | case 64: | |
13869 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13870 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
13871 | DMA_RWCTRL_WRITE_BNDRY_64); | |
13872 | break; | |
13873 | } | |
13874 | /* fallthrough */ | |
13875 | case 128: | |
13876 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13877 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
13878 | DMA_RWCTRL_WRITE_BNDRY_128); | |
13879 | break; | |
13880 | } | |
13881 | /* fallthrough */ | |
13882 | case 256: | |
13883 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
13884 | DMA_RWCTRL_WRITE_BNDRY_256); | |
13885 | break; | |
13886 | case 512: | |
13887 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
13888 | DMA_RWCTRL_WRITE_BNDRY_512); | |
13889 | break; | |
13890 | case 1024: | |
13891 | default: | |
13892 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
13893 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
13894 | break; | |
13895 | } | |
13896 | } | |
13897 | ||
13898 | out: | |
13899 | return val; | |
13900 | } | |
13901 | ||
13902 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) | |
13903 | { | |
13904 | struct tg3_internal_buffer_desc test_desc; | |
13905 | u32 sram_dma_descs; | |
13906 | int i, ret; | |
13907 | ||
13908 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
13909 | ||
13910 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
13911 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
13912 | tw32(RDMAC_STATUS, 0); | |
13913 | tw32(WDMAC_STATUS, 0); | |
13914 | ||
13915 | tw32(BUFMGR_MODE, 0); | |
13916 | tw32(FTQ_RESET, 0); | |
13917 | ||
13918 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
13919 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
13920 | test_desc.nic_mbuf = 0x00002100; | |
13921 | test_desc.len = size; | |
13922 | ||
13923 | /* | |
13924 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
13925 | * the *second* time the tg3 driver was getting loaded after an | |
13926 | * initial scan. | |
13927 | * | |
13928 | * Broadcom tells me: | |
13929 | * ...the DMA engine is connected to the GRC block and a DMA | |
13930 | * reset may affect the GRC block in some unpredictable way... | |
13931 | * The behavior of resets to individual blocks has not been tested. | |
13932 | * | |
13933 | * Broadcom noted the GRC reset will also reset all sub-components. | |
13934 | */ | |
13935 | if (to_device) { | |
13936 | test_desc.cqid_sqid = (13 << 8) | 2; | |
13937 | ||
13938 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
13939 | udelay(40); | |
13940 | } else { | |
13941 | test_desc.cqid_sqid = (16 << 8) | 7; | |
13942 | ||
13943 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
13944 | udelay(40); | |
13945 | } | |
13946 | test_desc.flags = 0x00000005; | |
13947 | ||
13948 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
13949 | u32 val; | |
13950 | ||
13951 | val = *(((u32 *)&test_desc) + i); | |
13952 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
13953 | sram_dma_descs + (i * sizeof(u32))); | |
13954 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
13955 | } | |
13956 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
13957 | ||
13958 | if (to_device) { | |
13959 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); | |
13960 | } else { | |
13961 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); | |
13962 | } | |
13963 | ||
13964 | ret = -ENODEV; | |
13965 | for (i = 0; i < 40; i++) { | |
13966 | u32 val; | |
13967 | ||
13968 | if (to_device) | |
13969 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
13970 | else | |
13971 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
13972 | if ((val & 0xffff) == sram_dma_descs) { | |
13973 | ret = 0; | |
13974 | break; | |
13975 | } | |
13976 | ||
13977 | udelay(100); | |
13978 | } | |
13979 | ||
13980 | return ret; | |
13981 | } | |
13982 | ||
13983 | #define TEST_BUFFER_SIZE 0x2000 | |
13984 | ||
13985 | static int __devinit tg3_test_dma(struct tg3 *tp) | |
13986 | { | |
13987 | dma_addr_t buf_dma; | |
13988 | u32 *buf, saved_dma_rwctrl; | |
13989 | int ret = 0; | |
13990 | ||
13991 | buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma); | |
13992 | if (!buf) { | |
13993 | ret = -ENOMEM; | |
13994 | goto out_nofree; | |
13995 | } | |
13996 | ||
13997 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
13998 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
13999 | ||
14000 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); | |
14001 | ||
14002 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14003 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
14004 | goto out; | |
14005 | ||
14006 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
14007 | /* DMA read watermark not used on PCIE */ | |
14008 | tp->dma_rwctrl |= 0x00180000; | |
14009 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
14010 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || | |
14011 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
14012 | tp->dma_rwctrl |= 0x003f0000; | |
14013 | else | |
14014 | tp->dma_rwctrl |= 0x003f000f; | |
14015 | } else { | |
14016 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14017 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14018 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
14019 | u32 read_water = 0x7; | |
14020 | ||
14021 | /* If the 5704 is behind the EPB bridge, we can | |
14022 | * do the less restrictive ONE_DMA workaround for | |
14023 | * better performance. | |
14024 | */ | |
14025 | if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) && | |
14026 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14027 | tp->dma_rwctrl |= 0x8000; | |
14028 | else if (ccval == 0x6 || ccval == 0x7) | |
14029 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; | |
14030 | ||
14031 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) | |
14032 | read_water = 4; | |
14033 | /* Set bit 23 to enable PCIX hw bug fix */ | |
14034 | tp->dma_rwctrl |= | |
14035 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
14036 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
14037 | (1 << 23); | |
14038 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { | |
14039 | /* 5780 always in PCIX mode */ | |
14040 | tp->dma_rwctrl |= 0x00144000; | |
14041 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
14042 | /* 5714 always in PCIX mode */ | |
14043 | tp->dma_rwctrl |= 0x00148000; | |
14044 | } else { | |
14045 | tp->dma_rwctrl |= 0x001b000f; | |
14046 | } | |
14047 | } | |
14048 | ||
14049 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14050 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14051 | tp->dma_rwctrl &= 0xfffffff0; | |
14052 | ||
14053 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14054 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
14055 | /* Remove this if it causes problems for some boards. */ | |
14056 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
14057 | ||
14058 | /* On 5700/5701 chips, we need to set this bit. | |
14059 | * Otherwise the chip will issue cacheline transactions | |
14060 | * to streamable DMA memory with not all the byte | |
14061 | * enables turned on. This is an error on several | |
14062 | * RISC PCI controllers, in particular sparc64. | |
14063 | * | |
14064 | * On 5703/5704 chips, this bit has been reassigned | |
14065 | * a different meaning. In particular, it is used | |
14066 | * on those chips to enable a PCI-X workaround. | |
14067 | */ | |
14068 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
14069 | } | |
14070 | ||
14071 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14072 | ||
14073 | #if 0 | |
14074 | /* Unneeded, already done by tg3_get_invariants. */ | |
14075 | tg3_switch_clocks(tp); | |
14076 | #endif | |
14077 | ||
14078 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14079 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
14080 | goto out; | |
14081 | ||
14082 | /* It is best to perform DMA test with maximum write burst size | |
14083 | * to expose the 5700/5701 write DMA bug. | |
14084 | */ | |
14085 | saved_dma_rwctrl = tp->dma_rwctrl; | |
14086 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14087 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14088 | ||
14089 | while (1) { | |
14090 | u32 *p = buf, i; | |
14091 | ||
14092 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
14093 | p[i] = i; | |
14094 | ||
14095 | /* Send the buffer to the chip. */ | |
14096 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
14097 | if (ret) { | |
14098 | printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret); | |
14099 | break; | |
14100 | } | |
14101 | ||
14102 | #if 0 | |
14103 | /* validate data reached card RAM correctly. */ | |
14104 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14105 | u32 val; | |
14106 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
14107 | if (le32_to_cpu(val) != p[i]) { | |
14108 | printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i); | |
14109 | /* ret = -ENODEV here? */ | |
14110 | } | |
14111 | p[i] = 0; | |
14112 | } | |
14113 | #endif | |
14114 | /* Now read it back. */ | |
14115 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
14116 | if (ret) { | |
14117 | printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret); | |
14118 | ||
14119 | break; | |
14120 | } | |
14121 | ||
14122 | /* Verify it. */ | |
14123 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14124 | if (p[i] == i) | |
14125 | continue; | |
14126 | ||
14127 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != | |
14128 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14129 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14130 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
14131 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14132 | break; | |
14133 | } else { | |
14134 | printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i); | |
14135 | ret = -ENODEV; | |
14136 | goto out; | |
14137 | } | |
14138 | } | |
14139 | ||
14140 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
14141 | /* Success. */ | |
14142 | ret = 0; | |
14143 | break; | |
14144 | } | |
14145 | } | |
14146 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != | |
14147 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14148 | static struct pci_device_id dma_wait_state_chipsets[] = { | |
14149 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, | |
14150 | PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, | |
14151 | { }, | |
14152 | }; | |
14153 | ||
14154 | /* DMA test passed without adjusting DMA boundary, | |
14155 | * now look for chipsets that are known to expose the | |
14156 | * DMA bug without failing the test. | |
14157 | */ | |
14158 | if (pci_dev_present(dma_wait_state_chipsets)) { | |
14159 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14160 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
14161 | } | |
14162 | else | |
14163 | /* Safe to use the calculated DMA boundary. */ | |
14164 | tp->dma_rwctrl = saved_dma_rwctrl; | |
14165 | ||
14166 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14167 | } | |
14168 | ||
14169 | out: | |
14170 | pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma); | |
14171 | out_nofree: | |
14172 | return ret; | |
14173 | } | |
14174 | ||
14175 | static void __devinit tg3_init_link_config(struct tg3 *tp) | |
14176 | { | |
14177 | tp->link_config.advertising = | |
14178 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
14179 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
14180 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | | |
14181 | ADVERTISED_Autoneg | ADVERTISED_MII); | |
14182 | tp->link_config.speed = SPEED_INVALID; | |
14183 | tp->link_config.duplex = DUPLEX_INVALID; | |
14184 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
14185 | tp->link_config.active_speed = SPEED_INVALID; | |
14186 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
14187 | tp->link_config.phy_is_low_power = 0; | |
14188 | tp->link_config.orig_speed = SPEED_INVALID; | |
14189 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
14190 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
14191 | } | |
14192 | ||
14193 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) | |
14194 | { | |
14195 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14196 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
14197 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14198 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14199 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14200 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
14201 | tp->bufmgr_config.mbuf_high_water = | |
14202 | DEFAULT_MB_HIGH_WATER_57765; | |
14203 | ||
14204 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14205 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14206 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14207 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
14208 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14209 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
14210 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
14211 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14212 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14213 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14214 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
14215 | tp->bufmgr_config.mbuf_high_water = | |
14216 | DEFAULT_MB_HIGH_WATER_5705; | |
14217 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
14218 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14219 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
14220 | tp->bufmgr_config.mbuf_high_water = | |
14221 | DEFAULT_MB_HIGH_WATER_5906; | |
14222 | } | |
14223 | ||
14224 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14225 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
14226 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14227 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
14228 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14229 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
14230 | } else { | |
14231 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14232 | DEFAULT_MB_RDMA_LOW_WATER; | |
14233 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14234 | DEFAULT_MB_MACRX_LOW_WATER; | |
14235 | tp->bufmgr_config.mbuf_high_water = | |
14236 | DEFAULT_MB_HIGH_WATER; | |
14237 | ||
14238 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14239 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
14240 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14241 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
14242 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14243 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
14244 | } | |
14245 | ||
14246 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
14247 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
14248 | } | |
14249 | ||
14250 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
14251 | { | |
14252 | switch (tp->phy_id & PHY_ID_MASK) { | |
14253 | case PHY_ID_BCM5400: return "5400"; | |
14254 | case PHY_ID_BCM5401: return "5401"; | |
14255 | case PHY_ID_BCM5411: return "5411"; | |
14256 | case PHY_ID_BCM5701: return "5701"; | |
14257 | case PHY_ID_BCM5703: return "5703"; | |
14258 | case PHY_ID_BCM5704: return "5704"; | |
14259 | case PHY_ID_BCM5705: return "5705"; | |
14260 | case PHY_ID_BCM5750: return "5750"; | |
14261 | case PHY_ID_BCM5752: return "5752"; | |
14262 | case PHY_ID_BCM5714: return "5714"; | |
14263 | case PHY_ID_BCM5780: return "5780"; | |
14264 | case PHY_ID_BCM5755: return "5755"; | |
14265 | case PHY_ID_BCM5787: return "5787"; | |
14266 | case PHY_ID_BCM5784: return "5784"; | |
14267 | case PHY_ID_BCM5756: return "5722/5756"; | |
14268 | case PHY_ID_BCM5906: return "5906"; | |
14269 | case PHY_ID_BCM5761: return "5761"; | |
14270 | case PHY_ID_BCM5718C: return "5718C"; | |
14271 | case PHY_ID_BCM5718S: return "5718S"; | |
14272 | case PHY_ID_BCM57765: return "57765"; | |
14273 | case PHY_ID_BCM8002: return "8002/serdes"; | |
14274 | case 0: return "serdes"; | |
14275 | default: return "unknown"; | |
14276 | } | |
14277 | } | |
14278 | ||
14279 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) | |
14280 | { | |
14281 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
14282 | strcpy(str, "PCI Express"); | |
14283 | return str; | |
14284 | } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
14285 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; | |
14286 | ||
14287 | strcpy(str, "PCIX:"); | |
14288 | ||
14289 | if ((clock_ctrl == 7) || | |
14290 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
14291 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
14292 | strcat(str, "133MHz"); | |
14293 | else if (clock_ctrl == 0) | |
14294 | strcat(str, "33MHz"); | |
14295 | else if (clock_ctrl == 2) | |
14296 | strcat(str, "50MHz"); | |
14297 | else if (clock_ctrl == 4) | |
14298 | strcat(str, "66MHz"); | |
14299 | else if (clock_ctrl == 6) | |
14300 | strcat(str, "100MHz"); | |
14301 | } else { | |
14302 | strcpy(str, "PCI:"); | |
14303 | if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) | |
14304 | strcat(str, "66MHz"); | |
14305 | else | |
14306 | strcat(str, "33MHz"); | |
14307 | } | |
14308 | if (tp->tg3_flags & TG3_FLAG_PCI_32BIT) | |
14309 | strcat(str, ":32-bit"); | |
14310 | else | |
14311 | strcat(str, ":64-bit"); | |
14312 | return str; | |
14313 | } | |
14314 | ||
14315 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) | |
14316 | { | |
14317 | struct pci_dev *peer; | |
14318 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
14319 | ||
14320 | for (func = 0; func < 8; func++) { | |
14321 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
14322 | if (peer && peer != tp->pdev) | |
14323 | break; | |
14324 | pci_dev_put(peer); | |
14325 | } | |
14326 | /* 5704 can be configured in single-port mode, set peer to | |
14327 | * tp->pdev in that case. | |
14328 | */ | |
14329 | if (!peer) { | |
14330 | peer = tp->pdev; | |
14331 | return peer; | |
14332 | } | |
14333 | ||
14334 | /* | |
14335 | * We don't need to keep the refcount elevated; there's no way | |
14336 | * to remove one half of this device without removing the other | |
14337 | */ | |
14338 | pci_dev_put(peer); | |
14339 | ||
14340 | return peer; | |
14341 | } | |
14342 | ||
14343 | static void __devinit tg3_init_coal(struct tg3 *tp) | |
14344 | { | |
14345 | struct ethtool_coalesce *ec = &tp->coal; | |
14346 | ||
14347 | memset(ec, 0, sizeof(*ec)); | |
14348 | ec->cmd = ETHTOOL_GCOALESCE; | |
14349 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
14350 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
14351 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
14352 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
14353 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
14354 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
14355 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
14356 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
14357 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
14358 | ||
14359 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
14360 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
14361 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
14362 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
14363 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
14364 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
14365 | } | |
14366 | ||
14367 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
14368 | ec->rx_coalesce_usecs_irq = 0; | |
14369 | ec->tx_coalesce_usecs_irq = 0; | |
14370 | ec->stats_block_coalesce_usecs = 0; | |
14371 | } | |
14372 | } | |
14373 | ||
14374 | static const struct net_device_ops tg3_netdev_ops = { | |
14375 | .ndo_open = tg3_open, | |
14376 | .ndo_stop = tg3_close, | |
14377 | .ndo_start_xmit = tg3_start_xmit, | |
14378 | .ndo_get_stats = tg3_get_stats, | |
14379 | .ndo_validate_addr = eth_validate_addr, | |
14380 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14381 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14382 | .ndo_do_ioctl = tg3_ioctl, | |
14383 | .ndo_tx_timeout = tg3_tx_timeout, | |
14384 | .ndo_change_mtu = tg3_change_mtu, | |
14385 | #if TG3_VLAN_TAG_USED | |
14386 | .ndo_vlan_rx_register = tg3_vlan_rx_register, | |
14387 | #endif | |
14388 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
14389 | .ndo_poll_controller = tg3_poll_controller, | |
14390 | #endif | |
14391 | }; | |
14392 | ||
14393 | static const struct net_device_ops tg3_netdev_ops_dma_bug = { | |
14394 | .ndo_open = tg3_open, | |
14395 | .ndo_stop = tg3_close, | |
14396 | .ndo_start_xmit = tg3_start_xmit_dma_bug, | |
14397 | .ndo_get_stats = tg3_get_stats, | |
14398 | .ndo_validate_addr = eth_validate_addr, | |
14399 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14400 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14401 | .ndo_do_ioctl = tg3_ioctl, | |
14402 | .ndo_tx_timeout = tg3_tx_timeout, | |
14403 | .ndo_change_mtu = tg3_change_mtu, | |
14404 | #if TG3_VLAN_TAG_USED | |
14405 | .ndo_vlan_rx_register = tg3_vlan_rx_register, | |
14406 | #endif | |
14407 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
14408 | .ndo_poll_controller = tg3_poll_controller, | |
14409 | #endif | |
14410 | }; | |
14411 | ||
14412 | static int __devinit tg3_init_one(struct pci_dev *pdev, | |
14413 | const struct pci_device_id *ent) | |
14414 | { | |
14415 | static int tg3_version_printed = 0; | |
14416 | struct net_device *dev; | |
14417 | struct tg3 *tp; | |
14418 | int i, err, pm_cap; | |
14419 | u32 sndmbx, rcvmbx, intmbx; | |
14420 | char str[40]; | |
14421 | u64 dma_mask, persist_dma_mask; | |
14422 | ||
14423 | if (tg3_version_printed++ == 0) | |
14424 | printk(KERN_INFO "%s", version); | |
14425 | ||
14426 | err = pci_enable_device(pdev); | |
14427 | if (err) { | |
14428 | printk(KERN_ERR PFX "Cannot enable PCI device, " | |
14429 | "aborting.\n"); | |
14430 | return err; | |
14431 | } | |
14432 | ||
14433 | err = pci_request_regions(pdev, DRV_MODULE_NAME); | |
14434 | if (err) { | |
14435 | printk(KERN_ERR PFX "Cannot obtain PCI resources, " | |
14436 | "aborting.\n"); | |
14437 | goto err_out_disable_pdev; | |
14438 | } | |
14439 | ||
14440 | pci_set_master(pdev); | |
14441 | ||
14442 | /* Find power-management capability. */ | |
14443 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
14444 | if (pm_cap == 0) { | |
14445 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
14446 | "aborting.\n"); | |
14447 | err = -EIO; | |
14448 | goto err_out_free_res; | |
14449 | } | |
14450 | ||
14451 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); | |
14452 | if (!dev) { | |
14453 | printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n"); | |
14454 | err = -ENOMEM; | |
14455 | goto err_out_free_res; | |
14456 | } | |
14457 | ||
14458 | SET_NETDEV_DEV(dev, &pdev->dev); | |
14459 | ||
14460 | #if TG3_VLAN_TAG_USED | |
14461 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
14462 | #endif | |
14463 | ||
14464 | tp = netdev_priv(dev); | |
14465 | tp->pdev = pdev; | |
14466 | tp->dev = dev; | |
14467 | tp->pm_cap = pm_cap; | |
14468 | tp->rx_mode = TG3_DEF_RX_MODE; | |
14469 | tp->tx_mode = TG3_DEF_TX_MODE; | |
14470 | ||
14471 | if (tg3_debug > 0) | |
14472 | tp->msg_enable = tg3_debug; | |
14473 | else | |
14474 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
14475 | ||
14476 | /* The word/byte swap controls here control register access byte | |
14477 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
14478 | * setting below. | |
14479 | */ | |
14480 | tp->misc_host_ctrl = | |
14481 | MISC_HOST_CTRL_MASK_PCI_INT | | |
14482 | MISC_HOST_CTRL_WORD_SWAP | | |
14483 | MISC_HOST_CTRL_INDIR_ACCESS | | |
14484 | MISC_HOST_CTRL_PCISTATE_RW; | |
14485 | ||
14486 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
14487 | * on descriptor entries, anything which isn't packet data. | |
14488 | * | |
14489 | * The StrongARM chips on the board (one for tx, one for rx) | |
14490 | * are running in big-endian mode. | |
14491 | */ | |
14492 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
14493 | GRC_MODE_WSWAP_NONFRM_DATA); | |
14494 | #ifdef __BIG_ENDIAN | |
14495 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
14496 | #endif | |
14497 | spin_lock_init(&tp->lock); | |
14498 | spin_lock_init(&tp->indirect_lock); | |
14499 | INIT_WORK(&tp->reset_task, tg3_reset_task); | |
14500 | ||
14501 | tp->regs = pci_ioremap_bar(pdev, BAR_0); | |
14502 | if (!tp->regs) { | |
14503 | printk(KERN_ERR PFX "Cannot map device registers, " | |
14504 | "aborting.\n"); | |
14505 | err = -ENOMEM; | |
14506 | goto err_out_free_dev; | |
14507 | } | |
14508 | ||
14509 | tg3_init_link_config(tp); | |
14510 | ||
14511 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; | |
14512 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
14513 | ||
14514 | dev->ethtool_ops = &tg3_ethtool_ops; | |
14515 | dev->watchdog_timeo = TG3_TX_TIMEOUT; | |
14516 | dev->irq = pdev->irq; | |
14517 | ||
14518 | err = tg3_get_invariants(tp); | |
14519 | if (err) { | |
14520 | printk(KERN_ERR PFX "Problem fetching invariants of chip, " | |
14521 | "aborting.\n"); | |
14522 | goto err_out_iounmap; | |
14523 | } | |
14524 | ||
14525 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && | |
14526 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) | |
14527 | dev->netdev_ops = &tg3_netdev_ops; | |
14528 | else | |
14529 | dev->netdev_ops = &tg3_netdev_ops_dma_bug; | |
14530 | ||
14531 | ||
14532 | /* The EPB bridge inside 5714, 5715, and 5780 and any | |
14533 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
14534 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. | |
14535 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
14536 | * do DMA address check in tg3_start_xmit(). | |
14537 | */ | |
14538 | if (tp->tg3_flags2 & TG3_FLG2_IS_5788) | |
14539 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); | |
14540 | else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { | |
14541 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); | |
14542 | #ifdef CONFIG_HIGHMEM | |
14543 | dma_mask = DMA_BIT_MASK(64); | |
14544 | #endif | |
14545 | } else | |
14546 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); | |
14547 | ||
14548 | /* Configure DMA attributes. */ | |
14549 | if (dma_mask > DMA_BIT_MASK(32)) { | |
14550 | err = pci_set_dma_mask(pdev, dma_mask); | |
14551 | if (!err) { | |
14552 | dev->features |= NETIF_F_HIGHDMA; | |
14553 | err = pci_set_consistent_dma_mask(pdev, | |
14554 | persist_dma_mask); | |
14555 | if (err < 0) { | |
14556 | printk(KERN_ERR PFX "Unable to obtain 64 bit " | |
14557 | "DMA for consistent allocations\n"); | |
14558 | goto err_out_iounmap; | |
14559 | } | |
14560 | } | |
14561 | } | |
14562 | if (err || dma_mask == DMA_BIT_MASK(32)) { | |
14563 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
14564 | if (err) { | |
14565 | printk(KERN_ERR PFX "No usable DMA configuration, " | |
14566 | "aborting.\n"); | |
14567 | goto err_out_iounmap; | |
14568 | } | |
14569 | } | |
14570 | ||
14571 | tg3_init_bufmgr_config(tp); | |
14572 | ||
14573 | /* Selectively allow TSO based on operating conditions */ | |
14574 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) || | |
14575 | (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) | |
14576 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; | |
14577 | else { | |
14578 | tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG); | |
14579 | tp->fw_needed = NULL; | |
14580 | } | |
14581 | ||
14582 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
14583 | tp->fw_needed = FIRMWARE_TG3; | |
14584 | ||
14585 | /* TSO is on by default on chips that support hardware TSO. | |
14586 | * Firmware TSO on older chips gives lower performance, so it | |
14587 | * is off by default, but can be enabled using ethtool. | |
14588 | */ | |
14589 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) && | |
14590 | (dev->features & NETIF_F_IP_CSUM)) | |
14591 | dev->features |= NETIF_F_TSO; | |
14592 | ||
14593 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || | |
14594 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) { | |
14595 | if (dev->features & NETIF_F_IPV6_CSUM) | |
14596 | dev->features |= NETIF_F_TSO6; | |
14597 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || | |
14598 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
14599 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
14600 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
14601 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
14602 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
14603 | dev->features |= NETIF_F_TSO_ECN; | |
14604 | } | |
14605 | ||
14606 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && | |
14607 | !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && | |
14608 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | |
14609 | tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64; | |
14610 | tp->rx_pending = 63; | |
14611 | } | |
14612 | ||
14613 | err = tg3_get_device_address(tp); | |
14614 | if (err) { | |
14615 | printk(KERN_ERR PFX "Could not obtain valid ethernet address, " | |
14616 | "aborting.\n"); | |
14617 | goto err_out_iounmap; | |
14618 | } | |
14619 | ||
14620 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { | |
14621 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
14622 | if (!tp->aperegs) { | |
14623 | printk(KERN_ERR PFX "Cannot map APE registers, " | |
14624 | "aborting.\n"); | |
14625 | err = -ENOMEM; | |
14626 | goto err_out_iounmap; | |
14627 | } | |
14628 | ||
14629 | tg3_ape_lock_init(tp); | |
14630 | ||
14631 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
14632 | tg3_read_dash_ver(tp); | |
14633 | } | |
14634 | ||
14635 | /* | |
14636 | * Reset chip in case UNDI or EFI driver did not shutdown | |
14637 | * DMA self test will enable WDMAC and we'll see (spurious) | |
14638 | * pending DMA on the PCI bus at that point. | |
14639 | */ | |
14640 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
14641 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
14642 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); | |
14643 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
14644 | } | |
14645 | ||
14646 | err = tg3_test_dma(tp); | |
14647 | if (err) { | |
14648 | printk(KERN_ERR PFX "DMA engine test failed, aborting.\n"); | |
14649 | goto err_out_apeunmap; | |
14650 | } | |
14651 | ||
14652 | /* flow control autonegotiation is default behavior */ | |
14653 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
14654 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
14655 | ||
14656 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; | |
14657 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
14658 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
14659 | for (i = 0; i < TG3_IRQ_MAX_VECS; i++) { | |
14660 | struct tg3_napi *tnapi = &tp->napi[i]; | |
14661 | ||
14662 | tnapi->tp = tp; | |
14663 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
14664 | ||
14665 | tnapi->int_mbox = intmbx; | |
14666 | if (i < 4) | |
14667 | intmbx += 0x8; | |
14668 | else | |
14669 | intmbx += 0x4; | |
14670 | ||
14671 | tnapi->consmbox = rcvmbx; | |
14672 | tnapi->prodmbox = sndmbx; | |
14673 | ||
14674 | if (i) { | |
14675 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); | |
14676 | netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64); | |
14677 | } else { | |
14678 | tnapi->coal_now = HOSTCC_MODE_NOW; | |
14679 | netif_napi_add(dev, &tnapi->napi, tg3_poll, 64); | |
14680 | } | |
14681 | ||
14682 | if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)) | |
14683 | break; | |
14684 | ||
14685 | /* | |
14686 | * If we support MSIX, we'll be using RSS. If we're using | |
14687 | * RSS, the first vector only handles link interrupts and the | |
14688 | * remaining vectors handle rx and tx interrupts. Reuse the | |
14689 | * mailbox values for the next iteration. The values we setup | |
14690 | * above are still useful for the single vectored mode. | |
14691 | */ | |
14692 | if (!i) | |
14693 | continue; | |
14694 | ||
14695 | rcvmbx += 0x8; | |
14696 | ||
14697 | if (sndmbx & 0x4) | |
14698 | sndmbx -= 0x4; | |
14699 | else | |
14700 | sndmbx += 0xc; | |
14701 | } | |
14702 | ||
14703 | tg3_init_coal(tp); | |
14704 | ||
14705 | pci_set_drvdata(pdev, dev); | |
14706 | ||
14707 | err = register_netdev(dev); | |
14708 | if (err) { | |
14709 | printk(KERN_ERR PFX "Cannot register net device, " | |
14710 | "aborting.\n"); | |
14711 | goto err_out_apeunmap; | |
14712 | } | |
14713 | ||
14714 | printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", | |
14715 | dev->name, | |
14716 | tp->board_part_number, | |
14717 | tp->pci_chip_rev_id, | |
14718 | tg3_bus_string(tp, str), | |
14719 | dev->dev_addr); | |
14720 | ||
14721 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
14722 | struct phy_device *phydev; | |
14723 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
14724 | printk(KERN_INFO | |
14725 | "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
14726 | tp->dev->name, phydev->drv->name, | |
14727 | dev_name(&phydev->dev)); | |
14728 | } else | |
14729 | printk(KERN_INFO | |
14730 | "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n", | |
14731 | tp->dev->name, tg3_phy_string(tp), | |
14732 | ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" : | |
14733 | ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" : | |
14734 | "10/100/1000Base-T")), | |
14735 | (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0); | |
14736 | ||
14737 | printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
14738 | dev->name, | |
14739 | (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0, | |
14740 | (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, | |
14741 | (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0, | |
14742 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, | |
14743 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); | |
14744 | printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n", | |
14745 | dev->name, tp->dma_rwctrl, | |
14746 | (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 : | |
14747 | (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64)); | |
14748 | ||
14749 | return 0; | |
14750 | ||
14751 | err_out_apeunmap: | |
14752 | if (tp->aperegs) { | |
14753 | iounmap(tp->aperegs); | |
14754 | tp->aperegs = NULL; | |
14755 | } | |
14756 | ||
14757 | err_out_iounmap: | |
14758 | if (tp->regs) { | |
14759 | iounmap(tp->regs); | |
14760 | tp->regs = NULL; | |
14761 | } | |
14762 | ||
14763 | err_out_free_dev: | |
14764 | free_netdev(dev); | |
14765 | ||
14766 | err_out_free_res: | |
14767 | pci_release_regions(pdev); | |
14768 | ||
14769 | err_out_disable_pdev: | |
14770 | pci_disable_device(pdev); | |
14771 | pci_set_drvdata(pdev, NULL); | |
14772 | return err; | |
14773 | } | |
14774 | ||
14775 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
14776 | { | |
14777 | struct net_device *dev = pci_get_drvdata(pdev); | |
14778 | ||
14779 | if (dev) { | |
14780 | struct tg3 *tp = netdev_priv(dev); | |
14781 | ||
14782 | if (tp->fw) | |
14783 | release_firmware(tp->fw); | |
14784 | ||
14785 | flush_scheduled_work(); | |
14786 | ||
14787 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
14788 | tg3_phy_fini(tp); | |
14789 | tg3_mdio_fini(tp); | |
14790 | } | |
14791 | ||
14792 | unregister_netdev(dev); | |
14793 | if (tp->aperegs) { | |
14794 | iounmap(tp->aperegs); | |
14795 | tp->aperegs = NULL; | |
14796 | } | |
14797 | if (tp->regs) { | |
14798 | iounmap(tp->regs); | |
14799 | tp->regs = NULL; | |
14800 | } | |
14801 | free_netdev(dev); | |
14802 | pci_release_regions(pdev); | |
14803 | pci_disable_device(pdev); | |
14804 | pci_set_drvdata(pdev, NULL); | |
14805 | } | |
14806 | } | |
14807 | ||
14808 | static int tg3_suspend(struct pci_dev *pdev, pm_message_t state) | |
14809 | { | |
14810 | struct net_device *dev = pci_get_drvdata(pdev); | |
14811 | struct tg3 *tp = netdev_priv(dev); | |
14812 | pci_power_t target_state; | |
14813 | int err; | |
14814 | ||
14815 | /* PCI register 4 needs to be saved whether netif_running() or not. | |
14816 | * MSI address and data need to be saved if using MSI and | |
14817 | * netif_running(). | |
14818 | */ | |
14819 | pci_save_state(pdev); | |
14820 | ||
14821 | if (!netif_running(dev)) | |
14822 | return 0; | |
14823 | ||
14824 | flush_scheduled_work(); | |
14825 | tg3_phy_stop(tp); | |
14826 | tg3_netif_stop(tp); | |
14827 | ||
14828 | del_timer_sync(&tp->timer); | |
14829 | ||
14830 | tg3_full_lock(tp, 1); | |
14831 | tg3_disable_ints(tp); | |
14832 | tg3_full_unlock(tp); | |
14833 | ||
14834 | netif_device_detach(dev); | |
14835 | ||
14836 | tg3_full_lock(tp, 0); | |
14837 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
14838 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
14839 | tg3_full_unlock(tp); | |
14840 | ||
14841 | target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot; | |
14842 | ||
14843 | err = tg3_set_power_state(tp, target_state); | |
14844 | if (err) { | |
14845 | int err2; | |
14846 | ||
14847 | tg3_full_lock(tp, 0); | |
14848 | ||
14849 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
14850 | err2 = tg3_restart_hw(tp, 1); | |
14851 | if (err2) | |
14852 | goto out; | |
14853 | ||
14854 | tp->timer.expires = jiffies + tp->timer_offset; | |
14855 | add_timer(&tp->timer); | |
14856 | ||
14857 | netif_device_attach(dev); | |
14858 | tg3_netif_start(tp); | |
14859 | ||
14860 | out: | |
14861 | tg3_full_unlock(tp); | |
14862 | ||
14863 | if (!err2) | |
14864 | tg3_phy_start(tp); | |
14865 | } | |
14866 | ||
14867 | return err; | |
14868 | } | |
14869 | ||
14870 | static int tg3_resume(struct pci_dev *pdev) | |
14871 | { | |
14872 | struct net_device *dev = pci_get_drvdata(pdev); | |
14873 | struct tg3 *tp = netdev_priv(dev); | |
14874 | int err; | |
14875 | ||
14876 | pci_restore_state(tp->pdev); | |
14877 | ||
14878 | if (!netif_running(dev)) | |
14879 | return 0; | |
14880 | ||
14881 | err = tg3_set_power_state(tp, PCI_D0); | |
14882 | if (err) | |
14883 | return err; | |
14884 | ||
14885 | netif_device_attach(dev); | |
14886 | ||
14887 | tg3_full_lock(tp, 0); | |
14888 | ||
14889 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
14890 | err = tg3_restart_hw(tp, 1); | |
14891 | if (err) | |
14892 | goto out; | |
14893 | ||
14894 | tp->timer.expires = jiffies + tp->timer_offset; | |
14895 | add_timer(&tp->timer); | |
14896 | ||
14897 | tg3_netif_start(tp); | |
14898 | ||
14899 | out: | |
14900 | tg3_full_unlock(tp); | |
14901 | ||
14902 | if (!err) | |
14903 | tg3_phy_start(tp); | |
14904 | ||
14905 | return err; | |
14906 | } | |
14907 | ||
14908 | static struct pci_driver tg3_driver = { | |
14909 | .name = DRV_MODULE_NAME, | |
14910 | .id_table = tg3_pci_tbl, | |
14911 | .probe = tg3_init_one, | |
14912 | .remove = __devexit_p(tg3_remove_one), | |
14913 | .suspend = tg3_suspend, | |
14914 | .resume = tg3_resume | |
14915 | }; | |
14916 | ||
14917 | static int __init tg3_init(void) | |
14918 | { | |
14919 | return pci_register_driver(&tg3_driver); | |
14920 | } | |
14921 | ||
14922 | static void __exit tg3_cleanup(void) | |
14923 | { | |
14924 | pci_unregister_driver(&tg3_driver); | |
14925 | } | |
14926 | ||
14927 | module_init(tg3_init); | |
14928 | module_exit(tg3_cleanup); |