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tg3: Cleanup IPV6 LSO
[net-next-2.6.git] / drivers / net / tg3.c
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1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
26#include <linux/in.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/phy.h>
36#include <linux/brcmphy.h>
37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
41#include <linux/prefetch.h>
42#include <linux/dma-mapping.h>
43
44#include <net/checksum.h>
45#include <net/ip.h>
46
47#include <asm/system.h>
48#include <asm/io.h>
49#include <asm/byteorder.h>
50#include <asm/uaccess.h>
51
52#ifdef CONFIG_SPARC
53#include <asm/idprom.h>
54#include <asm/prom.h>
55#endif
56
57#define BAR_0 0
58#define BAR_2 2
59
60#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
61#define TG3_VLAN_TAG_USED 1
62#else
63#define TG3_VLAN_TAG_USED 0
64#endif
65
66#define TG3_TSO_SUPPORT 1
67
68#include "tg3.h"
69
70#define DRV_MODULE_NAME "tg3"
71#define PFX DRV_MODULE_NAME ": "
72#define DRV_MODULE_VERSION "3.96"
73#define DRV_MODULE_RELDATE "November 21, 2008"
74
75#define TG3_DEF_MAC_MODE 0
76#define TG3_DEF_RX_MODE 0
77#define TG3_DEF_TX_MODE 0
78#define TG3_DEF_MSG_ENABLE \
79 (NETIF_MSG_DRV | \
80 NETIF_MSG_PROBE | \
81 NETIF_MSG_LINK | \
82 NETIF_MSG_TIMER | \
83 NETIF_MSG_IFDOWN | \
84 NETIF_MSG_IFUP | \
85 NETIF_MSG_RX_ERR | \
86 NETIF_MSG_TX_ERR)
87
88/* length of time before we decide the hardware is borked,
89 * and dev->tx_timeout() should be called to fix the problem
90 */
91#define TG3_TX_TIMEOUT (5 * HZ)
92
93/* hardware minimum and maximum for a single frame's data payload */
94#define TG3_MIN_MTU 60
95#define TG3_MAX_MTU(tp) \
96 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
97
98/* These numbers seem to be hard coded in the NIC firmware somehow.
99 * You can't change the ring sizes, but you can change where you place
100 * them in the NIC onboard memory.
101 */
102#define TG3_RX_RING_SIZE 512
103#define TG3_DEF_RX_RING_PENDING 200
104#define TG3_RX_JUMBO_RING_SIZE 256
105#define TG3_DEF_RX_JUMBO_RING_PENDING 100
106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
114 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115
116#define TG3_TX_RING_SIZE 512
117#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118
119#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_RING_SIZE)
121#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
123#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RCB_RING_SIZE(tp))
125#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 TG3_TX_RING_SIZE)
127#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
129#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
130#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
131
132/* minimum number of free TX descriptors required to wake up TX process */
133#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
134
135#define TG3_RAW_IP_ALIGN 2
136
137/* number of ETHTOOL_GSTATS u64's */
138#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
139
140#define TG3_NUM_TEST 6
141
142static char version[] __devinitdata =
143 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
144
145MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
146MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
147MODULE_LICENSE("GPL");
148MODULE_VERSION(DRV_MODULE_VERSION);
149
150static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
151module_param(tg3_debug, int, 0);
152MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
153
154static struct pci_device_id tg3_pci_tbl[] = {
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
220 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
221 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
222 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
223 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
224 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
225 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
226 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
227 {}
228};
229
230MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
231
232static const struct {
233 const char string[ETH_GSTRING_LEN];
234} ethtool_stats_keys[TG3_NUM_STATS] = {
235 { "rx_octets" },
236 { "rx_fragments" },
237 { "rx_ucast_packets" },
238 { "rx_mcast_packets" },
239 { "rx_bcast_packets" },
240 { "rx_fcs_errors" },
241 { "rx_align_errors" },
242 { "rx_xon_pause_rcvd" },
243 { "rx_xoff_pause_rcvd" },
244 { "rx_mac_ctrl_rcvd" },
245 { "rx_xoff_entered" },
246 { "rx_frame_too_long_errors" },
247 { "rx_jabbers" },
248 { "rx_undersize_packets" },
249 { "rx_in_length_errors" },
250 { "rx_out_length_errors" },
251 { "rx_64_or_less_octet_packets" },
252 { "rx_65_to_127_octet_packets" },
253 { "rx_128_to_255_octet_packets" },
254 { "rx_256_to_511_octet_packets" },
255 { "rx_512_to_1023_octet_packets" },
256 { "rx_1024_to_1522_octet_packets" },
257 { "rx_1523_to_2047_octet_packets" },
258 { "rx_2048_to_4095_octet_packets" },
259 { "rx_4096_to_8191_octet_packets" },
260 { "rx_8192_to_9022_octet_packets" },
261
262 { "tx_octets" },
263 { "tx_collisions" },
264
265 { "tx_xon_sent" },
266 { "tx_xoff_sent" },
267 { "tx_flow_control" },
268 { "tx_mac_errors" },
269 { "tx_single_collisions" },
270 { "tx_mult_collisions" },
271 { "tx_deferred" },
272 { "tx_excessive_collisions" },
273 { "tx_late_collisions" },
274 { "tx_collide_2times" },
275 { "tx_collide_3times" },
276 { "tx_collide_4times" },
277 { "tx_collide_5times" },
278 { "tx_collide_6times" },
279 { "tx_collide_7times" },
280 { "tx_collide_8times" },
281 { "tx_collide_9times" },
282 { "tx_collide_10times" },
283 { "tx_collide_11times" },
284 { "tx_collide_12times" },
285 { "tx_collide_13times" },
286 { "tx_collide_14times" },
287 { "tx_collide_15times" },
288 { "tx_ucast_packets" },
289 { "tx_mcast_packets" },
290 { "tx_bcast_packets" },
291 { "tx_carrier_sense_errors" },
292 { "tx_discards" },
293 { "tx_errors" },
294
295 { "dma_writeq_full" },
296 { "dma_write_prioq_full" },
297 { "rxbds_empty" },
298 { "rx_discards" },
299 { "rx_errors" },
300 { "rx_threshold_hit" },
301
302 { "dma_readq_full" },
303 { "dma_read_prioq_full" },
304 { "tx_comp_queue_full" },
305
306 { "ring_set_send_prod_index" },
307 { "ring_status_update" },
308 { "nic_irqs" },
309 { "nic_avoided_irqs" },
310 { "nic_tx_threshold_hit" }
311};
312
313static const struct {
314 const char string[ETH_GSTRING_LEN];
315} ethtool_test_keys[TG3_NUM_TEST] = {
316 { "nvram test (online) " },
317 { "link test (online) " },
318 { "register test (offline)" },
319 { "memory test (offline)" },
320 { "loopback test (offline)" },
321 { "interrupt test (offline)" },
322};
323
324static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
325{
326 writel(val, tp->regs + off);
327}
328
329static u32 tg3_read32(struct tg3 *tp, u32 off)
330{
331 return (readl(tp->regs + off));
332}
333
334static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
335{
336 writel(val, tp->aperegs + off);
337}
338
339static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
340{
341 return (readl(tp->aperegs + off));
342}
343
344static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
345{
346 unsigned long flags;
347
348 spin_lock_irqsave(&tp->indirect_lock, flags);
349 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
350 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
351 spin_unlock_irqrestore(&tp->indirect_lock, flags);
352}
353
354static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
355{
356 writel(val, tp->regs + off);
357 readl(tp->regs + off);
358}
359
360static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
361{
362 unsigned long flags;
363 u32 val;
364
365 spin_lock_irqsave(&tp->indirect_lock, flags);
366 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
367 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
368 spin_unlock_irqrestore(&tp->indirect_lock, flags);
369 return val;
370}
371
372static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
373{
374 unsigned long flags;
375
376 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
377 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
378 TG3_64BIT_REG_LOW, val);
379 return;
380 }
381 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
382 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
383 TG3_64BIT_REG_LOW, val);
384 return;
385 }
386
387 spin_lock_irqsave(&tp->indirect_lock, flags);
388 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
389 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
390 spin_unlock_irqrestore(&tp->indirect_lock, flags);
391
392 /* In indirect mode when disabling interrupts, we also need
393 * to clear the interrupt bit in the GRC local ctrl register.
394 */
395 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
396 (val == 0x1)) {
397 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
398 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
399 }
400}
401
402static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
403{
404 unsigned long flags;
405 u32 val;
406
407 spin_lock_irqsave(&tp->indirect_lock, flags);
408 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
409 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
410 spin_unlock_irqrestore(&tp->indirect_lock, flags);
411 return val;
412}
413
414/* usec_wait specifies the wait time in usec when writing to certain registers
415 * where it is unsafe to read back the register without some delay.
416 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
417 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
418 */
419static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
420{
421 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
422 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
423 /* Non-posted methods */
424 tp->write32(tp, off, val);
425 else {
426 /* Posted method */
427 tg3_write32(tp, off, val);
428 if (usec_wait)
429 udelay(usec_wait);
430 tp->read32(tp, off);
431 }
432 /* Wait again after the read for the posted method to guarantee that
433 * the wait time is met.
434 */
435 if (usec_wait)
436 udelay(usec_wait);
437}
438
439static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
440{
441 tp->write32_mbox(tp, off, val);
442 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
443 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
444 tp->read32_mbox(tp, off);
445}
446
447static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
448{
449 void __iomem *mbox = tp->regs + off;
450 writel(val, mbox);
451 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
452 writel(val, mbox);
453 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
454 readl(mbox);
455}
456
457static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
458{
459 return (readl(tp->regs + off + GRCMBOX_BASE));
460}
461
462static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
463{
464 writel(val, tp->regs + off + GRCMBOX_BASE);
465}
466
467#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
468#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
469#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
470#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
471#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
472
473#define tw32(reg,val) tp->write32(tp, reg, val)
474#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
475#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
476#define tr32(reg) tp->read32(tp, reg)
477
478static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
479{
480 unsigned long flags;
481
482 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
483 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
484 return;
485
486 spin_lock_irqsave(&tp->indirect_lock, flags);
487 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
488 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
489 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
490
491 /* Always leave this as zero. */
492 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
493 } else {
494 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
495 tw32_f(TG3PCI_MEM_WIN_DATA, val);
496
497 /* Always leave this as zero. */
498 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
499 }
500 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501}
502
503static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
504{
505 unsigned long flags;
506
507 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
508 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
509 *val = 0;
510 return;
511 }
512
513 spin_lock_irqsave(&tp->indirect_lock, flags);
514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
517
518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
520 } else {
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 *val = tr32(TG3PCI_MEM_WIN_DATA);
523
524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 }
527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
528}
529
530static void tg3_ape_lock_init(struct tg3 *tp)
531{
532 int i;
533
534 /* Make sure the driver hasn't any stale locks. */
535 for (i = 0; i < 8; i++)
536 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
537 APE_LOCK_GRANT_DRIVER);
538}
539
540static int tg3_ape_lock(struct tg3 *tp, int locknum)
541{
542 int i, off;
543 int ret = 0;
544 u32 status;
545
546 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
547 return 0;
548
549 switch (locknum) {
550 case TG3_APE_LOCK_GRC:
551 case TG3_APE_LOCK_MEM:
552 break;
553 default:
554 return -EINVAL;
555 }
556
557 off = 4 * locknum;
558
559 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
560
561 /* Wait for up to 1 millisecond to acquire lock. */
562 for (i = 0; i < 100; i++) {
563 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
564 if (status == APE_LOCK_GRANT_DRIVER)
565 break;
566 udelay(10);
567 }
568
569 if (status != APE_LOCK_GRANT_DRIVER) {
570 /* Revoke the lock request. */
571 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
572 APE_LOCK_GRANT_DRIVER);
573
574 ret = -EBUSY;
575 }
576
577 return ret;
578}
579
580static void tg3_ape_unlock(struct tg3 *tp, int locknum)
581{
582 int off;
583
584 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
585 return;
586
587 switch (locknum) {
588 case TG3_APE_LOCK_GRC:
589 case TG3_APE_LOCK_MEM:
590 break;
591 default:
592 return;
593 }
594
595 off = 4 * locknum;
596 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
597}
598
599static void tg3_disable_ints(struct tg3 *tp)
600{
601 tw32(TG3PCI_MISC_HOST_CTRL,
602 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
603 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
604}
605
606static inline void tg3_cond_int(struct tg3 *tp)
607{
608 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
609 (tp->hw_status->status & SD_STATUS_UPDATED))
610 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
611 else
612 tw32(HOSTCC_MODE, tp->coalesce_mode |
613 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
614}
615
616static void tg3_enable_ints(struct tg3 *tp)
617{
618 tp->irq_sync = 0;
619 wmb();
620
621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
623 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
624 (tp->last_tag << 24));
625 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
626 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
627 (tp->last_tag << 24));
628 tg3_cond_int(tp);
629}
630
631static inline unsigned int tg3_has_work(struct tg3 *tp)
632{
633 struct tg3_hw_status *sblk = tp->hw_status;
634 unsigned int work_exists = 0;
635
636 /* check for phy events */
637 if (!(tp->tg3_flags &
638 (TG3_FLAG_USE_LINKCHG_REG |
639 TG3_FLAG_POLL_SERDES))) {
640 if (sblk->status & SD_STATUS_LINK_CHG)
641 work_exists = 1;
642 }
643 /* check for RX/TX work to do */
644 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
645 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
646 work_exists = 1;
647
648 return work_exists;
649}
650
651/* tg3_restart_ints
652 * similar to tg3_enable_ints, but it accurately determines whether there
653 * is new work pending and can return without flushing the PIO write
654 * which reenables interrupts
655 */
656static void tg3_restart_ints(struct tg3 *tp)
657{
658 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
659 tp->last_tag << 24);
660 mmiowb();
661
662 /* When doing tagged status, this work check is unnecessary.
663 * The last_tag we write above tells the chip which piece of
664 * work we've completed.
665 */
666 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
667 tg3_has_work(tp))
668 tw32(HOSTCC_MODE, tp->coalesce_mode |
669 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
670}
671
672static inline void tg3_netif_stop(struct tg3 *tp)
673{
674 tp->dev->trans_start = jiffies; /* prevent tx timeout */
675 napi_disable(&tp->napi);
676 netif_tx_disable(tp->dev);
677}
678
679static inline void tg3_netif_start(struct tg3 *tp)
680{
681 netif_wake_queue(tp->dev);
682 /* NOTE: unconditional netif_wake_queue is only appropriate
683 * so long as all callers are assured to have free tx slots
684 * (such as after tg3_init_hw)
685 */
686 napi_enable(&tp->napi);
687 tp->hw_status->status |= SD_STATUS_UPDATED;
688 tg3_enable_ints(tp);
689}
690
691static void tg3_switch_clocks(struct tg3 *tp)
692{
693 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
694 u32 orig_clock_ctrl;
695
696 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
697 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
698 return;
699
700 orig_clock_ctrl = clock_ctrl;
701 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
702 CLOCK_CTRL_CLKRUN_OENABLE |
703 0x1f);
704 tp->pci_clock_ctrl = clock_ctrl;
705
706 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
707 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
708 tw32_wait_f(TG3PCI_CLOCK_CTRL,
709 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
710 }
711 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
712 tw32_wait_f(TG3PCI_CLOCK_CTRL,
713 clock_ctrl |
714 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
715 40);
716 tw32_wait_f(TG3PCI_CLOCK_CTRL,
717 clock_ctrl | (CLOCK_CTRL_ALTCLK),
718 40);
719 }
720 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
721}
722
723#define PHY_BUSY_LOOPS 5000
724
725static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
726{
727 u32 frame_val;
728 unsigned int loops;
729 int ret;
730
731 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
732 tw32_f(MAC_MI_MODE,
733 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
734 udelay(80);
735 }
736
737 *val = 0x0;
738
739 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
740 MI_COM_PHY_ADDR_MASK);
741 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
742 MI_COM_REG_ADDR_MASK);
743 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
744
745 tw32_f(MAC_MI_COM, frame_val);
746
747 loops = PHY_BUSY_LOOPS;
748 while (loops != 0) {
749 udelay(10);
750 frame_val = tr32(MAC_MI_COM);
751
752 if ((frame_val & MI_COM_BUSY) == 0) {
753 udelay(5);
754 frame_val = tr32(MAC_MI_COM);
755 break;
756 }
757 loops -= 1;
758 }
759
760 ret = -EBUSY;
761 if (loops != 0) {
762 *val = frame_val & MI_COM_DATA_MASK;
763 ret = 0;
764 }
765
766 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
767 tw32_f(MAC_MI_MODE, tp->mi_mode);
768 udelay(80);
769 }
770
771 return ret;
772}
773
774static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
775{
776 u32 frame_val;
777 unsigned int loops;
778 int ret;
779
780 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
781 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
782 return 0;
783
784 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
785 tw32_f(MAC_MI_MODE,
786 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
787 udelay(80);
788 }
789
790 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
791 MI_COM_PHY_ADDR_MASK);
792 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
793 MI_COM_REG_ADDR_MASK);
794 frame_val |= (val & MI_COM_DATA_MASK);
795 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
796
797 tw32_f(MAC_MI_COM, frame_val);
798
799 loops = PHY_BUSY_LOOPS;
800 while (loops != 0) {
801 udelay(10);
802 frame_val = tr32(MAC_MI_COM);
803 if ((frame_val & MI_COM_BUSY) == 0) {
804 udelay(5);
805 frame_val = tr32(MAC_MI_COM);
806 break;
807 }
808 loops -= 1;
809 }
810
811 ret = -EBUSY;
812 if (loops != 0)
813 ret = 0;
814
815 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
816 tw32_f(MAC_MI_MODE, tp->mi_mode);
817 udelay(80);
818 }
819
820 return ret;
821}
822
823static int tg3_bmcr_reset(struct tg3 *tp)
824{
825 u32 phy_control;
826 int limit, err;
827
828 /* OK, reset it, and poll the BMCR_RESET bit until it
829 * clears or we time out.
830 */
831 phy_control = BMCR_RESET;
832 err = tg3_writephy(tp, MII_BMCR, phy_control);
833 if (err != 0)
834 return -EBUSY;
835
836 limit = 5000;
837 while (limit--) {
838 err = tg3_readphy(tp, MII_BMCR, &phy_control);
839 if (err != 0)
840 return -EBUSY;
841
842 if ((phy_control & BMCR_RESET) == 0) {
843 udelay(40);
844 break;
845 }
846 udelay(10);
847 }
848 if (limit <= 0)
849 return -EBUSY;
850
851 return 0;
852}
853
854static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
855{
856 struct tg3 *tp = (struct tg3 *)bp->priv;
857 u32 val;
858
859 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
860 return -EAGAIN;
861
862 if (tg3_readphy(tp, reg, &val))
863 return -EIO;
864
865 return val;
866}
867
868static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
869{
870 struct tg3 *tp = (struct tg3 *)bp->priv;
871
872 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
873 return -EAGAIN;
874
875 if (tg3_writephy(tp, reg, val))
876 return -EIO;
877
878 return 0;
879}
880
881static int tg3_mdio_reset(struct mii_bus *bp)
882{
883 return 0;
884}
885
886static void tg3_mdio_config_5785(struct tg3 *tp)
887{
888 u32 val;
889 struct phy_device *phydev;
890
891 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
892 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
893 case TG3_PHY_ID_BCM50610:
894 val = MAC_PHYCFG2_50610_LED_MODES;
895 break;
896 case TG3_PHY_ID_BCMAC131:
897 val = MAC_PHYCFG2_AC131_LED_MODES;
898 break;
899 case TG3_PHY_ID_RTL8211C:
900 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
901 break;
902 case TG3_PHY_ID_RTL8201E:
903 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
904 break;
905 default:
906 return;
907 }
908
909 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
910 tw32(MAC_PHYCFG2, val);
911
912 val = tr32(MAC_PHYCFG1);
913 val &= ~MAC_PHYCFG1_RGMII_INT;
914 tw32(MAC_PHYCFG1, val);
915
916 return;
917 }
918
919 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
920 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
921 MAC_PHYCFG2_FMODE_MASK_MASK |
922 MAC_PHYCFG2_GMODE_MASK_MASK |
923 MAC_PHYCFG2_ACT_MASK_MASK |
924 MAC_PHYCFG2_QUAL_MASK_MASK |
925 MAC_PHYCFG2_INBAND_ENABLE;
926
927 tw32(MAC_PHYCFG2, val);
928
929 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
930 MAC_PHYCFG1_RGMII_SND_STAT_EN);
931 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
932 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
933 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
934 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
935 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
936 }
937 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
938
939 val = tr32(MAC_EXT_RGMII_MODE);
940 val &= ~(MAC_RGMII_MODE_RX_INT_B |
941 MAC_RGMII_MODE_RX_QUALITY |
942 MAC_RGMII_MODE_RX_ACTIVITY |
943 MAC_RGMII_MODE_RX_ENG_DET |
944 MAC_RGMII_MODE_TX_ENABLE |
945 MAC_RGMII_MODE_TX_LOWPWR |
946 MAC_RGMII_MODE_TX_RESET);
947 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
948 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
949 val |= MAC_RGMII_MODE_RX_INT_B |
950 MAC_RGMII_MODE_RX_QUALITY |
951 MAC_RGMII_MODE_RX_ACTIVITY |
952 MAC_RGMII_MODE_RX_ENG_DET;
953 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
954 val |= MAC_RGMII_MODE_TX_ENABLE |
955 MAC_RGMII_MODE_TX_LOWPWR |
956 MAC_RGMII_MODE_TX_RESET;
957 }
958 tw32(MAC_EXT_RGMII_MODE, val);
959}
960
961static void tg3_mdio_start(struct tg3 *tp)
962{
963 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
964 mutex_lock(&tp->mdio_bus->mdio_lock);
965 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
966 mutex_unlock(&tp->mdio_bus->mdio_lock);
967 }
968
969 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
970 tw32_f(MAC_MI_MODE, tp->mi_mode);
971 udelay(80);
972
973 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
974 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
975 tg3_mdio_config_5785(tp);
976}
977
978static void tg3_mdio_stop(struct tg3 *tp)
979{
980 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
981 mutex_lock(&tp->mdio_bus->mdio_lock);
982 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
983 mutex_unlock(&tp->mdio_bus->mdio_lock);
984 }
985}
986
987static int tg3_mdio_init(struct tg3 *tp)
988{
989 int i;
990 u32 reg;
991 struct phy_device *phydev;
992
993 tg3_mdio_start(tp);
994
995 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
996 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
997 return 0;
998
999 tp->mdio_bus = mdiobus_alloc();
1000 if (tp->mdio_bus == NULL)
1001 return -ENOMEM;
1002
1003 tp->mdio_bus->name = "tg3 mdio bus";
1004 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1005 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1006 tp->mdio_bus->priv = tp;
1007 tp->mdio_bus->parent = &tp->pdev->dev;
1008 tp->mdio_bus->read = &tg3_mdio_read;
1009 tp->mdio_bus->write = &tg3_mdio_write;
1010 tp->mdio_bus->reset = &tg3_mdio_reset;
1011 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1012 tp->mdio_bus->irq = &tp->mdio_irq[0];
1013
1014 for (i = 0; i < PHY_MAX_ADDR; i++)
1015 tp->mdio_bus->irq[i] = PHY_POLL;
1016
1017 /* The bus registration will look for all the PHYs on the mdio bus.
1018 * Unfortunately, it does not ensure the PHY is powered up before
1019 * accessing the PHY ID registers. A chip reset is the
1020 * quickest way to bring the device back to an operational state..
1021 */
1022 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1023 tg3_bmcr_reset(tp);
1024
1025 i = mdiobus_register(tp->mdio_bus);
1026 if (i) {
1027 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1028 tp->dev->name, i);
1029 mdiobus_free(tp->mdio_bus);
1030 return i;
1031 }
1032
1033 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1034
1035 if (!phydev || !phydev->drv) {
1036 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1037 mdiobus_unregister(tp->mdio_bus);
1038 mdiobus_free(tp->mdio_bus);
1039 return -ENODEV;
1040 }
1041
1042 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1043 case TG3_PHY_ID_BCM57780:
1044 phydev->interface = PHY_INTERFACE_MODE_GMII;
1045 break;
1046 case TG3_PHY_ID_BCM50610:
1047 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1048 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1049 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1050 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1051 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1052 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1053 /* fallthru */
1054 case TG3_PHY_ID_RTL8211C:
1055 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1056 break;
1057 case TG3_PHY_ID_RTL8201E:
1058 case TG3_PHY_ID_BCMAC131:
1059 phydev->interface = PHY_INTERFACE_MODE_MII;
1060 break;
1061 }
1062
1063 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1064
1065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1066 tg3_mdio_config_5785(tp);
1067
1068 return 0;
1069}
1070
1071static void tg3_mdio_fini(struct tg3 *tp)
1072{
1073 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1074 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1075 mdiobus_unregister(tp->mdio_bus);
1076 mdiobus_free(tp->mdio_bus);
1077 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1078 }
1079}
1080
1081/* tp->lock is held. */
1082static inline void tg3_generate_fw_event(struct tg3 *tp)
1083{
1084 u32 val;
1085
1086 val = tr32(GRC_RX_CPU_EVENT);
1087 val |= GRC_RX_CPU_DRIVER_EVENT;
1088 tw32_f(GRC_RX_CPU_EVENT, val);
1089
1090 tp->last_event_jiffies = jiffies;
1091}
1092
1093#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1094
1095/* tp->lock is held. */
1096static void tg3_wait_for_event_ack(struct tg3 *tp)
1097{
1098 int i;
1099 unsigned int delay_cnt;
1100 long time_remain;
1101
1102 /* If enough time has passed, no wait is necessary. */
1103 time_remain = (long)(tp->last_event_jiffies + 1 +
1104 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1105 (long)jiffies;
1106 if (time_remain < 0)
1107 return;
1108
1109 /* Check if we can shorten the wait time. */
1110 delay_cnt = jiffies_to_usecs(time_remain);
1111 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1112 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1113 delay_cnt = (delay_cnt >> 3) + 1;
1114
1115 for (i = 0; i < delay_cnt; i++) {
1116 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1117 break;
1118 udelay(8);
1119 }
1120}
1121
1122/* tp->lock is held. */
1123static void tg3_ump_link_report(struct tg3 *tp)
1124{
1125 u32 reg;
1126 u32 val;
1127
1128 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1129 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1130 return;
1131
1132 tg3_wait_for_event_ack(tp);
1133
1134 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1135
1136 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1137
1138 val = 0;
1139 if (!tg3_readphy(tp, MII_BMCR, &reg))
1140 val = reg << 16;
1141 if (!tg3_readphy(tp, MII_BMSR, &reg))
1142 val |= (reg & 0xffff);
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_LPA, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1151
1152 val = 0;
1153 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1154 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1155 val = reg << 16;
1156 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1157 val |= (reg & 0xffff);
1158 }
1159 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1160
1161 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1162 val = reg << 16;
1163 else
1164 val = 0;
1165 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1166
1167 tg3_generate_fw_event(tp);
1168}
1169
1170static void tg3_link_report(struct tg3 *tp)
1171{
1172 if (!netif_carrier_ok(tp->dev)) {
1173 if (netif_msg_link(tp))
1174 printk(KERN_INFO PFX "%s: Link is down.\n",
1175 tp->dev->name);
1176 tg3_ump_link_report(tp);
1177 } else if (netif_msg_link(tp)) {
1178 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1179 tp->dev->name,
1180 (tp->link_config.active_speed == SPEED_1000 ?
1181 1000 :
1182 (tp->link_config.active_speed == SPEED_100 ?
1183 100 : 10)),
1184 (tp->link_config.active_duplex == DUPLEX_FULL ?
1185 "full" : "half"));
1186
1187 printk(KERN_INFO PFX
1188 "%s: Flow control is %s for TX and %s for RX.\n",
1189 tp->dev->name,
1190 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1191 "on" : "off",
1192 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1193 "on" : "off");
1194 tg3_ump_link_report(tp);
1195 }
1196}
1197
1198static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1199{
1200 u16 miireg;
1201
1202 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1203 miireg = ADVERTISE_PAUSE_CAP;
1204 else if (flow_ctrl & FLOW_CTRL_TX)
1205 miireg = ADVERTISE_PAUSE_ASYM;
1206 else if (flow_ctrl & FLOW_CTRL_RX)
1207 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1208 else
1209 miireg = 0;
1210
1211 return miireg;
1212}
1213
1214static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1215{
1216 u16 miireg;
1217
1218 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1219 miireg = ADVERTISE_1000XPAUSE;
1220 else if (flow_ctrl & FLOW_CTRL_TX)
1221 miireg = ADVERTISE_1000XPSE_ASYM;
1222 else if (flow_ctrl & FLOW_CTRL_RX)
1223 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1224 else
1225 miireg = 0;
1226
1227 return miireg;
1228}
1229
1230static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1231{
1232 u8 cap = 0;
1233
1234 if (lcladv & ADVERTISE_1000XPAUSE) {
1235 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1236 if (rmtadv & LPA_1000XPAUSE)
1237 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1238 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1239 cap = FLOW_CTRL_RX;
1240 } else {
1241 if (rmtadv & LPA_1000XPAUSE)
1242 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1243 }
1244 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1245 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1246 cap = FLOW_CTRL_TX;
1247 }
1248
1249 return cap;
1250}
1251
1252static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1253{
1254 u8 autoneg;
1255 u8 flowctrl = 0;
1256 u32 old_rx_mode = tp->rx_mode;
1257 u32 old_tx_mode = tp->tx_mode;
1258
1259 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1260 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1261 else
1262 autoneg = tp->link_config.autoneg;
1263
1264 if (autoneg == AUTONEG_ENABLE &&
1265 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1266 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1267 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1268 else
1269 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1270 } else
1271 flowctrl = tp->link_config.flowctrl;
1272
1273 tp->link_config.active_flowctrl = flowctrl;
1274
1275 if (flowctrl & FLOW_CTRL_RX)
1276 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1277 else
1278 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1279
1280 if (old_rx_mode != tp->rx_mode)
1281 tw32_f(MAC_RX_MODE, tp->rx_mode);
1282
1283 if (flowctrl & FLOW_CTRL_TX)
1284 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1285 else
1286 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1287
1288 if (old_tx_mode != tp->tx_mode)
1289 tw32_f(MAC_TX_MODE, tp->tx_mode);
1290}
1291
1292static void tg3_adjust_link(struct net_device *dev)
1293{
1294 u8 oldflowctrl, linkmesg = 0;
1295 u32 mac_mode, lcl_adv, rmt_adv;
1296 struct tg3 *tp = netdev_priv(dev);
1297 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1298
1299 spin_lock(&tp->lock);
1300
1301 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1302 MAC_MODE_HALF_DUPLEX);
1303
1304 oldflowctrl = tp->link_config.active_flowctrl;
1305
1306 if (phydev->link) {
1307 lcl_adv = 0;
1308 rmt_adv = 0;
1309
1310 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1311 mac_mode |= MAC_MODE_PORT_MODE_MII;
1312 else
1313 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1314
1315 if (phydev->duplex == DUPLEX_HALF)
1316 mac_mode |= MAC_MODE_HALF_DUPLEX;
1317 else {
1318 lcl_adv = tg3_advert_flowctrl_1000T(
1319 tp->link_config.flowctrl);
1320
1321 if (phydev->pause)
1322 rmt_adv = LPA_PAUSE_CAP;
1323 if (phydev->asym_pause)
1324 rmt_adv |= LPA_PAUSE_ASYM;
1325 }
1326
1327 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1328 } else
1329 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1330
1331 if (mac_mode != tp->mac_mode) {
1332 tp->mac_mode = mac_mode;
1333 tw32_f(MAC_MODE, tp->mac_mode);
1334 udelay(40);
1335 }
1336
1337 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1338 if (phydev->speed == SPEED_10)
1339 tw32(MAC_MI_STAT,
1340 MAC_MI_STAT_10MBPS_MODE |
1341 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1342 else
1343 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1344 }
1345
1346 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1347 tw32(MAC_TX_LENGTHS,
1348 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1349 (6 << TX_LENGTHS_IPG_SHIFT) |
1350 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1351 else
1352 tw32(MAC_TX_LENGTHS,
1353 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1354 (6 << TX_LENGTHS_IPG_SHIFT) |
1355 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1356
1357 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1358 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1359 phydev->speed != tp->link_config.active_speed ||
1360 phydev->duplex != tp->link_config.active_duplex ||
1361 oldflowctrl != tp->link_config.active_flowctrl)
1362 linkmesg = 1;
1363
1364 tp->link_config.active_speed = phydev->speed;
1365 tp->link_config.active_duplex = phydev->duplex;
1366
1367 spin_unlock(&tp->lock);
1368
1369 if (linkmesg)
1370 tg3_link_report(tp);
1371}
1372
1373static int tg3_phy_init(struct tg3 *tp)
1374{
1375 struct phy_device *phydev;
1376
1377 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1378 return 0;
1379
1380 /* Bring the PHY back to a known state. */
1381 tg3_bmcr_reset(tp);
1382
1383 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1384
1385 /* Attach the MAC to the PHY. */
1386 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1387 phydev->dev_flags, phydev->interface);
1388 if (IS_ERR(phydev)) {
1389 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1390 return PTR_ERR(phydev);
1391 }
1392
1393 /* Mask with MAC supported features. */
1394 switch (phydev->interface) {
1395 case PHY_INTERFACE_MODE_GMII:
1396 case PHY_INTERFACE_MODE_RGMII:
1397 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1398 phydev->supported &= (PHY_GBIT_FEATURES |
1399 SUPPORTED_Pause |
1400 SUPPORTED_Asym_Pause);
1401 break;
1402 }
1403 /* fallthru */
1404 case PHY_INTERFACE_MODE_MII:
1405 phydev->supported &= (PHY_BASIC_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 default:
1410 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1411 return -EINVAL;
1412 }
1413
1414 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1415
1416 phydev->advertising = phydev->supported;
1417
1418 return 0;
1419}
1420
1421static void tg3_phy_start(struct tg3 *tp)
1422{
1423 struct phy_device *phydev;
1424
1425 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1426 return;
1427
1428 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1429
1430 if (tp->link_config.phy_is_low_power) {
1431 tp->link_config.phy_is_low_power = 0;
1432 phydev->speed = tp->link_config.orig_speed;
1433 phydev->duplex = tp->link_config.orig_duplex;
1434 phydev->autoneg = tp->link_config.orig_autoneg;
1435 phydev->advertising = tp->link_config.orig_advertising;
1436 }
1437
1438 phy_start(phydev);
1439
1440 phy_start_aneg(phydev);
1441}
1442
1443static void tg3_phy_stop(struct tg3 *tp)
1444{
1445 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1446 return;
1447
1448 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1449}
1450
1451static void tg3_phy_fini(struct tg3 *tp)
1452{
1453 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1454 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1455 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1456 }
1457}
1458
1459static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1460{
1461 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1462 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1463}
1464
1465static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1466{
1467 u32 reg;
1468
1469 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1470 return;
1471
1472 reg = MII_TG3_MISC_SHDW_WREN |
1473 MII_TG3_MISC_SHDW_SCR5_SEL |
1474 MII_TG3_MISC_SHDW_SCR5_LPED |
1475 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1476 MII_TG3_MISC_SHDW_SCR5_SDTL |
1477 MII_TG3_MISC_SHDW_SCR5_C125OE;
1478 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1479 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1480
1481 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1482
1483
1484 reg = MII_TG3_MISC_SHDW_WREN |
1485 MII_TG3_MISC_SHDW_APD_SEL |
1486 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1487 if (enable)
1488 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1489
1490 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1491}
1492
1493static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1494{
1495 u32 phy;
1496
1497 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1498 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1499 return;
1500
1501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1502 u32 ephy;
1503
1504 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1505 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1506 ephy | MII_TG3_EPHY_SHADOW_EN);
1507 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1508 if (enable)
1509 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1510 else
1511 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1512 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1513 }
1514 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1515 }
1516 } else {
1517 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1518 MII_TG3_AUXCTL_SHDWSEL_MISC;
1519 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1520 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1521 if (enable)
1522 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1523 else
1524 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1525 phy |= MII_TG3_AUXCTL_MISC_WREN;
1526 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1527 }
1528 }
1529}
1530
1531static void tg3_phy_set_wirespeed(struct tg3 *tp)
1532{
1533 u32 val;
1534
1535 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1536 return;
1537
1538 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1539 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1540 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1541 (val | (1 << 15) | (1 << 4)));
1542}
1543
1544static void tg3_phy_apply_otp(struct tg3 *tp)
1545{
1546 u32 otp, phy;
1547
1548 if (!tp->phy_otp)
1549 return;
1550
1551 otp = tp->phy_otp;
1552
1553 /* Enable SM_DSP clock and tx 6dB coding. */
1554 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1555 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1556 MII_TG3_AUXCTL_ACTL_TX_6DB;
1557 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1558
1559 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1560 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1561 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1562
1563 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1564 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1565 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1566
1567 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1568 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1569 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1570
1571 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1572 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1573
1574 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1575 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1576
1577 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1578 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1579 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1580
1581 /* Turn off SM_DSP clock. */
1582 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1583 MII_TG3_AUXCTL_ACTL_TX_6DB;
1584 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1585}
1586
1587static int tg3_wait_macro_done(struct tg3 *tp)
1588{
1589 int limit = 100;
1590
1591 while (limit--) {
1592 u32 tmp32;
1593
1594 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1595 if ((tmp32 & 0x1000) == 0)
1596 break;
1597 }
1598 }
1599 if (limit <= 0)
1600 return -EBUSY;
1601
1602 return 0;
1603}
1604
1605static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1606{
1607 static const u32 test_pat[4][6] = {
1608 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1609 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1610 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1611 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1612 };
1613 int chan;
1614
1615 for (chan = 0; chan < 4; chan++) {
1616 int i;
1617
1618 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1619 (chan * 0x2000) | 0x0200);
1620 tg3_writephy(tp, 0x16, 0x0002);
1621
1622 for (i = 0; i < 6; i++)
1623 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1624 test_pat[chan][i]);
1625
1626 tg3_writephy(tp, 0x16, 0x0202);
1627 if (tg3_wait_macro_done(tp)) {
1628 *resetp = 1;
1629 return -EBUSY;
1630 }
1631
1632 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1633 (chan * 0x2000) | 0x0200);
1634 tg3_writephy(tp, 0x16, 0x0082);
1635 if (tg3_wait_macro_done(tp)) {
1636 *resetp = 1;
1637 return -EBUSY;
1638 }
1639
1640 tg3_writephy(tp, 0x16, 0x0802);
1641 if (tg3_wait_macro_done(tp)) {
1642 *resetp = 1;
1643 return -EBUSY;
1644 }
1645
1646 for (i = 0; i < 6; i += 2) {
1647 u32 low, high;
1648
1649 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1650 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1651 tg3_wait_macro_done(tp)) {
1652 *resetp = 1;
1653 return -EBUSY;
1654 }
1655 low &= 0x7fff;
1656 high &= 0x000f;
1657 if (low != test_pat[chan][i] ||
1658 high != test_pat[chan][i+1]) {
1659 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1660 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1661 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1662
1663 return -EBUSY;
1664 }
1665 }
1666 }
1667
1668 return 0;
1669}
1670
1671static int tg3_phy_reset_chanpat(struct tg3 *tp)
1672{
1673 int chan;
1674
1675 for (chan = 0; chan < 4; chan++) {
1676 int i;
1677
1678 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1679 (chan * 0x2000) | 0x0200);
1680 tg3_writephy(tp, 0x16, 0x0002);
1681 for (i = 0; i < 6; i++)
1682 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1683 tg3_writephy(tp, 0x16, 0x0202);
1684 if (tg3_wait_macro_done(tp))
1685 return -EBUSY;
1686 }
1687
1688 return 0;
1689}
1690
1691static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1692{
1693 u32 reg32, phy9_orig;
1694 int retries, do_phy_reset, err;
1695
1696 retries = 10;
1697 do_phy_reset = 1;
1698 do {
1699 if (do_phy_reset) {
1700 err = tg3_bmcr_reset(tp);
1701 if (err)
1702 return err;
1703 do_phy_reset = 0;
1704 }
1705
1706 /* Disable transmitter and interrupt. */
1707 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1708 continue;
1709
1710 reg32 |= 0x3000;
1711 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1712
1713 /* Set full-duplex, 1000 mbps. */
1714 tg3_writephy(tp, MII_BMCR,
1715 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1716
1717 /* Set to master mode. */
1718 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1719 continue;
1720
1721 tg3_writephy(tp, MII_TG3_CTRL,
1722 (MII_TG3_CTRL_AS_MASTER |
1723 MII_TG3_CTRL_ENABLE_AS_MASTER));
1724
1725 /* Enable SM_DSP_CLOCK and 6dB. */
1726 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1727
1728 /* Block the PHY control access. */
1729 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1730 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1731
1732 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1733 if (!err)
1734 break;
1735 } while (--retries);
1736
1737 err = tg3_phy_reset_chanpat(tp);
1738 if (err)
1739 return err;
1740
1741 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1742 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1743
1744 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1745 tg3_writephy(tp, 0x16, 0x0000);
1746
1747 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1748 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1749 /* Set Extended packet length bit for jumbo frames */
1750 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1751 }
1752 else {
1753 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1754 }
1755
1756 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1757
1758 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1759 reg32 &= ~0x3000;
1760 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1761 } else if (!err)
1762 err = -EBUSY;
1763
1764 return err;
1765}
1766
1767/* This will reset the tigon3 PHY if there is no valid
1768 * link unless the FORCE argument is non-zero.
1769 */
1770static int tg3_phy_reset(struct tg3 *tp)
1771{
1772 u32 cpmuctrl;
1773 u32 phy_status;
1774 int err;
1775
1776 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1777 u32 val;
1778
1779 val = tr32(GRC_MISC_CFG);
1780 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1781 udelay(40);
1782 }
1783 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1784 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1785 if (err != 0)
1786 return -EBUSY;
1787
1788 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1789 netif_carrier_off(tp->dev);
1790 tg3_link_report(tp);
1791 }
1792
1793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1794 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1795 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1796 err = tg3_phy_reset_5703_4_5(tp);
1797 if (err)
1798 return err;
1799 goto out;
1800 }
1801
1802 cpmuctrl = 0;
1803 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1804 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1805 cpmuctrl = tr32(TG3_CPMU_CTRL);
1806 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1807 tw32(TG3_CPMU_CTRL,
1808 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1809 }
1810
1811 err = tg3_bmcr_reset(tp);
1812 if (err)
1813 return err;
1814
1815 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1816 u32 phy;
1817
1818 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1819 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1820
1821 tw32(TG3_CPMU_CTRL, cpmuctrl);
1822 }
1823
1824 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1825 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1826 u32 val;
1827
1828 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1829 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1830 CPMU_LSPD_1000MB_MACCLK_12_5) {
1831 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1832 udelay(40);
1833 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1834 }
1835 }
1836
1837 tg3_phy_apply_otp(tp);
1838
1839 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1840 tg3_phy_toggle_apd(tp, true);
1841 else
1842 tg3_phy_toggle_apd(tp, false);
1843
1844out:
1845 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1846 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1847 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1848 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1849 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1850 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1851 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1852 }
1853 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1854 tg3_writephy(tp, 0x1c, 0x8d68);
1855 tg3_writephy(tp, 0x1c, 0x8d68);
1856 }
1857 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1858 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1859 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1860 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1861 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1862 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1863 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1864 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1865 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1866 }
1867 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1868 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1870 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1871 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1872 tg3_writephy(tp, MII_TG3_TEST1,
1873 MII_TG3_TEST1_TRIM_EN | 0x4);
1874 } else
1875 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1877 }
1878 /* Set Extended packet length bit (bit 14) on all chips that */
1879 /* support jumbo frames */
1880 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1881 /* Cannot do read-modify-write on 5401 */
1882 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1883 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1884 u32 phy_reg;
1885
1886 /* Set bit 14 with read-modify-write to preserve other bits */
1887 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1888 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1889 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1890 }
1891
1892 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1893 * jumbo frames transmission.
1894 */
1895 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1896 u32 phy_reg;
1897
1898 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1899 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1900 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1901 }
1902
1903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1904 /* adjust output voltage */
1905 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1906 }
1907
1908 tg3_phy_toggle_automdix(tp, 1);
1909 tg3_phy_set_wirespeed(tp);
1910 return 0;
1911}
1912
1913static void tg3_frob_aux_power(struct tg3 *tp)
1914{
1915 struct tg3 *tp_peer = tp;
1916
1917 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1918 return;
1919
1920 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1921 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1922 struct net_device *dev_peer;
1923
1924 dev_peer = pci_get_drvdata(tp->pdev_peer);
1925 /* remove_one() may have been run on the peer. */
1926 if (!dev_peer)
1927 tp_peer = tp;
1928 else
1929 tp_peer = netdev_priv(dev_peer);
1930 }
1931
1932 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1933 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1934 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1935 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1936 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1938 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1939 (GRC_LCLCTRL_GPIO_OE0 |
1940 GRC_LCLCTRL_GPIO_OE1 |
1941 GRC_LCLCTRL_GPIO_OE2 |
1942 GRC_LCLCTRL_GPIO_OUTPUT0 |
1943 GRC_LCLCTRL_GPIO_OUTPUT1),
1944 100);
1945 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1946 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1947 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1948 GRC_LCLCTRL_GPIO_OE1 |
1949 GRC_LCLCTRL_GPIO_OE2 |
1950 GRC_LCLCTRL_GPIO_OUTPUT0 |
1951 GRC_LCLCTRL_GPIO_OUTPUT1 |
1952 tp->grc_local_ctrl;
1953 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1954
1955 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1956 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1957
1958 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1959 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1960 } else {
1961 u32 no_gpio2;
1962 u32 grc_local_ctrl = 0;
1963
1964 if (tp_peer != tp &&
1965 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1966 return;
1967
1968 /* Workaround to prevent overdrawing Amps. */
1969 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1970 ASIC_REV_5714) {
1971 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1972 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1973 grc_local_ctrl, 100);
1974 }
1975
1976 /* On 5753 and variants, GPIO2 cannot be used. */
1977 no_gpio2 = tp->nic_sram_data_cfg &
1978 NIC_SRAM_DATA_CFG_NO_GPIO2;
1979
1980 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1981 GRC_LCLCTRL_GPIO_OE1 |
1982 GRC_LCLCTRL_GPIO_OE2 |
1983 GRC_LCLCTRL_GPIO_OUTPUT1 |
1984 GRC_LCLCTRL_GPIO_OUTPUT2;
1985 if (no_gpio2) {
1986 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1987 GRC_LCLCTRL_GPIO_OUTPUT2);
1988 }
1989 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1990 grc_local_ctrl, 100);
1991
1992 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1993
1994 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1995 grc_local_ctrl, 100);
1996
1997 if (!no_gpio2) {
1998 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1999 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2000 grc_local_ctrl, 100);
2001 }
2002 }
2003 } else {
2004 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2005 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2006 if (tp_peer != tp &&
2007 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2008 return;
2009
2010 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2011 (GRC_LCLCTRL_GPIO_OE1 |
2012 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2013
2014 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2015 GRC_LCLCTRL_GPIO_OE1, 100);
2016
2017 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2018 (GRC_LCLCTRL_GPIO_OE1 |
2019 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2020 }
2021 }
2022}
2023
2024static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2025{
2026 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2027 return 1;
2028 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2029 if (speed != SPEED_10)
2030 return 1;
2031 } else if (speed == SPEED_10)
2032 return 1;
2033
2034 return 0;
2035}
2036
2037static int tg3_setup_phy(struct tg3 *, int);
2038
2039#define RESET_KIND_SHUTDOWN 0
2040#define RESET_KIND_INIT 1
2041#define RESET_KIND_SUSPEND 2
2042
2043static void tg3_write_sig_post_reset(struct tg3 *, int);
2044static int tg3_halt_cpu(struct tg3 *, u32);
2045static int tg3_nvram_lock(struct tg3 *);
2046static void tg3_nvram_unlock(struct tg3 *);
2047
2048static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2049{
2050 u32 val;
2051
2052 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2054 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2055 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2056
2057 sg_dig_ctrl |=
2058 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2059 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2060 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2061 }
2062 return;
2063 }
2064
2065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2066 tg3_bmcr_reset(tp);
2067 val = tr32(GRC_MISC_CFG);
2068 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2069 udelay(40);
2070 return;
2071 } else if (do_low_power) {
2072 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2073 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2074
2075 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2076 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2077 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2078 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2079 MII_TG3_AUXCTL_PCTL_VREG_11V);
2080 }
2081
2082 /* The PHY should not be powered down on some chips because
2083 * of bugs.
2084 */
2085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2087 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2088 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2089 return;
2090
2091 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2092 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2093 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2094 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2095 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2096 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2097 }
2098
2099 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2100}
2101
2102/* tp->lock is held. */
2103static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2104{
2105 u32 addr_high, addr_low;
2106 int i;
2107
2108 addr_high = ((tp->dev->dev_addr[0] << 8) |
2109 tp->dev->dev_addr[1]);
2110 addr_low = ((tp->dev->dev_addr[2] << 24) |
2111 (tp->dev->dev_addr[3] << 16) |
2112 (tp->dev->dev_addr[4] << 8) |
2113 (tp->dev->dev_addr[5] << 0));
2114 for (i = 0; i < 4; i++) {
2115 if (i == 1 && skip_mac_1)
2116 continue;
2117 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2118 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2119 }
2120
2121 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2122 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2123 for (i = 0; i < 12; i++) {
2124 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2125 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2126 }
2127 }
2128
2129 addr_high = (tp->dev->dev_addr[0] +
2130 tp->dev->dev_addr[1] +
2131 tp->dev->dev_addr[2] +
2132 tp->dev->dev_addr[3] +
2133 tp->dev->dev_addr[4] +
2134 tp->dev->dev_addr[5]) &
2135 TX_BACKOFF_SEED_MASK;
2136 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2137}
2138
2139static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2140{
2141 u32 misc_host_ctrl;
2142 bool device_should_wake, do_low_power;
2143
2144 /* Make sure register accesses (indirect or otherwise)
2145 * will function correctly.
2146 */
2147 pci_write_config_dword(tp->pdev,
2148 TG3PCI_MISC_HOST_CTRL,
2149 tp->misc_host_ctrl);
2150
2151 switch (state) {
2152 case PCI_D0:
2153 pci_enable_wake(tp->pdev, state, false);
2154 pci_set_power_state(tp->pdev, PCI_D0);
2155
2156 /* Switch out of Vaux if it is a NIC */
2157 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2158 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2159
2160 return 0;
2161
2162 case PCI_D1:
2163 case PCI_D2:
2164 case PCI_D3hot:
2165 break;
2166
2167 default:
2168 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2169 tp->dev->name, state);
2170 return -EINVAL;
2171 }
2172
2173 /* Restore the CLKREQ setting. */
2174 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2175 u16 lnkctl;
2176
2177 pci_read_config_word(tp->pdev,
2178 tp->pcie_cap + PCI_EXP_LNKCTL,
2179 &lnkctl);
2180 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2181 pci_write_config_word(tp->pdev,
2182 tp->pcie_cap + PCI_EXP_LNKCTL,
2183 lnkctl);
2184 }
2185
2186 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2187 tw32(TG3PCI_MISC_HOST_CTRL,
2188 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2189
2190 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2191 device_may_wakeup(&tp->pdev->dev) &&
2192 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2193
2194 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2195 do_low_power = false;
2196 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2197 !tp->link_config.phy_is_low_power) {
2198 struct phy_device *phydev;
2199 u32 phyid, advertising;
2200
2201 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2202
2203 tp->link_config.phy_is_low_power = 1;
2204
2205 tp->link_config.orig_speed = phydev->speed;
2206 tp->link_config.orig_duplex = phydev->duplex;
2207 tp->link_config.orig_autoneg = phydev->autoneg;
2208 tp->link_config.orig_advertising = phydev->advertising;
2209
2210 advertising = ADVERTISED_TP |
2211 ADVERTISED_Pause |
2212 ADVERTISED_Autoneg |
2213 ADVERTISED_10baseT_Half;
2214
2215 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2216 device_should_wake) {
2217 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2218 advertising |=
2219 ADVERTISED_100baseT_Half |
2220 ADVERTISED_100baseT_Full |
2221 ADVERTISED_10baseT_Full;
2222 else
2223 advertising |= ADVERTISED_10baseT_Full;
2224 }
2225
2226 phydev->advertising = advertising;
2227
2228 phy_start_aneg(phydev);
2229
2230 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2231 if (phyid != TG3_PHY_ID_BCMAC131) {
2232 phyid &= TG3_PHY_OUI_MASK;
2233 if (phyid == TG3_PHY_OUI_1 &&
2234 phyid == TG3_PHY_OUI_2 &&
2235 phyid == TG3_PHY_OUI_3)
2236 do_low_power = true;
2237 }
2238 }
2239 } else {
2240 do_low_power = true;
2241
2242 if (tp->link_config.phy_is_low_power == 0) {
2243 tp->link_config.phy_is_low_power = 1;
2244 tp->link_config.orig_speed = tp->link_config.speed;
2245 tp->link_config.orig_duplex = tp->link_config.duplex;
2246 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2247 }
2248
2249 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2250 tp->link_config.speed = SPEED_10;
2251 tp->link_config.duplex = DUPLEX_HALF;
2252 tp->link_config.autoneg = AUTONEG_ENABLE;
2253 tg3_setup_phy(tp, 0);
2254 }
2255 }
2256
2257 __tg3_set_mac_addr(tp, 0);
2258
2259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2260 u32 val;
2261
2262 val = tr32(GRC_VCPU_EXT_CTRL);
2263 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2264 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2265 int i;
2266 u32 val;
2267
2268 for (i = 0; i < 200; i++) {
2269 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2270 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2271 break;
2272 msleep(1);
2273 }
2274 }
2275 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2276 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2277 WOL_DRV_STATE_SHUTDOWN |
2278 WOL_DRV_WOL |
2279 WOL_SET_MAGIC_PKT);
2280
2281 if (device_should_wake) {
2282 u32 mac_mode;
2283
2284 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2285 if (do_low_power) {
2286 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2287 udelay(40);
2288 }
2289
2290 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2291 mac_mode = MAC_MODE_PORT_MODE_GMII;
2292 else
2293 mac_mode = MAC_MODE_PORT_MODE_MII;
2294
2295 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2296 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2297 ASIC_REV_5700) {
2298 u32 speed = (tp->tg3_flags &
2299 TG3_FLAG_WOL_SPEED_100MB) ?
2300 SPEED_100 : SPEED_10;
2301 if (tg3_5700_link_polarity(tp, speed))
2302 mac_mode |= MAC_MODE_LINK_POLARITY;
2303 else
2304 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2305 }
2306 } else {
2307 mac_mode = MAC_MODE_PORT_MODE_TBI;
2308 }
2309
2310 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2311 tw32(MAC_LED_CTRL, tp->led_ctrl);
2312
2313 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2314 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2315 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2316 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2317 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2318 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2319
2320 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2321 mac_mode |= tp->mac_mode &
2322 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2323 if (mac_mode & MAC_MODE_APE_TX_EN)
2324 mac_mode |= MAC_MODE_TDE_ENABLE;
2325 }
2326
2327 tw32_f(MAC_MODE, mac_mode);
2328 udelay(100);
2329
2330 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2331 udelay(10);
2332 }
2333
2334 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2335 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2336 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2337 u32 base_val;
2338
2339 base_val = tp->pci_clock_ctrl;
2340 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2341 CLOCK_CTRL_TXCLK_DISABLE);
2342
2343 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2344 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2345 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2346 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2347 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2348 /* do nothing */
2349 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2350 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2351 u32 newbits1, newbits2;
2352
2353 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2355 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2356 CLOCK_CTRL_TXCLK_DISABLE |
2357 CLOCK_CTRL_ALTCLK);
2358 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2359 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2360 newbits1 = CLOCK_CTRL_625_CORE;
2361 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2362 } else {
2363 newbits1 = CLOCK_CTRL_ALTCLK;
2364 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2365 }
2366
2367 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2368 40);
2369
2370 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2371 40);
2372
2373 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2374 u32 newbits3;
2375
2376 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2377 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2378 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2379 CLOCK_CTRL_TXCLK_DISABLE |
2380 CLOCK_CTRL_44MHZ_CORE);
2381 } else {
2382 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2383 }
2384
2385 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2386 tp->pci_clock_ctrl | newbits3, 40);
2387 }
2388 }
2389
2390 if (!(device_should_wake) &&
2391 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2392 tg3_power_down_phy(tp, do_low_power);
2393
2394 tg3_frob_aux_power(tp);
2395
2396 /* Workaround for unstable PLL clock */
2397 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2398 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2399 u32 val = tr32(0x7d00);
2400
2401 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2402 tw32(0x7d00, val);
2403 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2404 int err;
2405
2406 err = tg3_nvram_lock(tp);
2407 tg3_halt_cpu(tp, RX_CPU_BASE);
2408 if (!err)
2409 tg3_nvram_unlock(tp);
2410 }
2411 }
2412
2413 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2414
2415 if (device_should_wake)
2416 pci_enable_wake(tp->pdev, state, true);
2417
2418 /* Finally, set the new power state. */
2419 pci_set_power_state(tp->pdev, state);
2420
2421 return 0;
2422}
2423
2424static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2425{
2426 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2427 case MII_TG3_AUX_STAT_10HALF:
2428 *speed = SPEED_10;
2429 *duplex = DUPLEX_HALF;
2430 break;
2431
2432 case MII_TG3_AUX_STAT_10FULL:
2433 *speed = SPEED_10;
2434 *duplex = DUPLEX_FULL;
2435 break;
2436
2437 case MII_TG3_AUX_STAT_100HALF:
2438 *speed = SPEED_100;
2439 *duplex = DUPLEX_HALF;
2440 break;
2441
2442 case MII_TG3_AUX_STAT_100FULL:
2443 *speed = SPEED_100;
2444 *duplex = DUPLEX_FULL;
2445 break;
2446
2447 case MII_TG3_AUX_STAT_1000HALF:
2448 *speed = SPEED_1000;
2449 *duplex = DUPLEX_HALF;
2450 break;
2451
2452 case MII_TG3_AUX_STAT_1000FULL:
2453 *speed = SPEED_1000;
2454 *duplex = DUPLEX_FULL;
2455 break;
2456
2457 default:
2458 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2459 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2460 SPEED_10;
2461 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2462 DUPLEX_HALF;
2463 break;
2464 }
2465 *speed = SPEED_INVALID;
2466 *duplex = DUPLEX_INVALID;
2467 break;
2468 }
2469}
2470
2471static void tg3_phy_copper_begin(struct tg3 *tp)
2472{
2473 u32 new_adv;
2474 int i;
2475
2476 if (tp->link_config.phy_is_low_power) {
2477 /* Entering low power mode. Disable gigabit and
2478 * 100baseT advertisements.
2479 */
2480 tg3_writephy(tp, MII_TG3_CTRL, 0);
2481
2482 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2483 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2484 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2485 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2486
2487 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2488 } else if (tp->link_config.speed == SPEED_INVALID) {
2489 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2490 tp->link_config.advertising &=
2491 ~(ADVERTISED_1000baseT_Half |
2492 ADVERTISED_1000baseT_Full);
2493
2494 new_adv = ADVERTISE_CSMA;
2495 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2496 new_adv |= ADVERTISE_10HALF;
2497 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2498 new_adv |= ADVERTISE_10FULL;
2499 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2500 new_adv |= ADVERTISE_100HALF;
2501 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2502 new_adv |= ADVERTISE_100FULL;
2503
2504 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2505
2506 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2507
2508 if (tp->link_config.advertising &
2509 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2510 new_adv = 0;
2511 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2512 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2513 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2514 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2515 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2516 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2517 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2518 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2519 MII_TG3_CTRL_ENABLE_AS_MASTER);
2520 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2521 } else {
2522 tg3_writephy(tp, MII_TG3_CTRL, 0);
2523 }
2524 } else {
2525 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2526 new_adv |= ADVERTISE_CSMA;
2527
2528 /* Asking for a specific link mode. */
2529 if (tp->link_config.speed == SPEED_1000) {
2530 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2531
2532 if (tp->link_config.duplex == DUPLEX_FULL)
2533 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2534 else
2535 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2536 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2537 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2538 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2539 MII_TG3_CTRL_ENABLE_AS_MASTER);
2540 } else {
2541 if (tp->link_config.speed == SPEED_100) {
2542 if (tp->link_config.duplex == DUPLEX_FULL)
2543 new_adv |= ADVERTISE_100FULL;
2544 else
2545 new_adv |= ADVERTISE_100HALF;
2546 } else {
2547 if (tp->link_config.duplex == DUPLEX_FULL)
2548 new_adv |= ADVERTISE_10FULL;
2549 else
2550 new_adv |= ADVERTISE_10HALF;
2551 }
2552 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2553
2554 new_adv = 0;
2555 }
2556
2557 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2558 }
2559
2560 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2561 tp->link_config.speed != SPEED_INVALID) {
2562 u32 bmcr, orig_bmcr;
2563
2564 tp->link_config.active_speed = tp->link_config.speed;
2565 tp->link_config.active_duplex = tp->link_config.duplex;
2566
2567 bmcr = 0;
2568 switch (tp->link_config.speed) {
2569 default:
2570 case SPEED_10:
2571 break;
2572
2573 case SPEED_100:
2574 bmcr |= BMCR_SPEED100;
2575 break;
2576
2577 case SPEED_1000:
2578 bmcr |= TG3_BMCR_SPEED1000;
2579 break;
2580 }
2581
2582 if (tp->link_config.duplex == DUPLEX_FULL)
2583 bmcr |= BMCR_FULLDPLX;
2584
2585 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2586 (bmcr != orig_bmcr)) {
2587 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2588 for (i = 0; i < 1500; i++) {
2589 u32 tmp;
2590
2591 udelay(10);
2592 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2593 tg3_readphy(tp, MII_BMSR, &tmp))
2594 continue;
2595 if (!(tmp & BMSR_LSTATUS)) {
2596 udelay(40);
2597 break;
2598 }
2599 }
2600 tg3_writephy(tp, MII_BMCR, bmcr);
2601 udelay(40);
2602 }
2603 } else {
2604 tg3_writephy(tp, MII_BMCR,
2605 BMCR_ANENABLE | BMCR_ANRESTART);
2606 }
2607}
2608
2609static int tg3_init_5401phy_dsp(struct tg3 *tp)
2610{
2611 int err;
2612
2613 /* Turn off tap power management. */
2614 /* Set Extended packet length bit */
2615 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2616
2617 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2618 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2619
2620 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2621 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2622
2623 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2624 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2625
2626 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2627 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2628
2629 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2630 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2631
2632 udelay(40);
2633
2634 return err;
2635}
2636
2637static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2638{
2639 u32 adv_reg, all_mask = 0;
2640
2641 if (mask & ADVERTISED_10baseT_Half)
2642 all_mask |= ADVERTISE_10HALF;
2643 if (mask & ADVERTISED_10baseT_Full)
2644 all_mask |= ADVERTISE_10FULL;
2645 if (mask & ADVERTISED_100baseT_Half)
2646 all_mask |= ADVERTISE_100HALF;
2647 if (mask & ADVERTISED_100baseT_Full)
2648 all_mask |= ADVERTISE_100FULL;
2649
2650 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2651 return 0;
2652
2653 if ((adv_reg & all_mask) != all_mask)
2654 return 0;
2655 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2656 u32 tg3_ctrl;
2657
2658 all_mask = 0;
2659 if (mask & ADVERTISED_1000baseT_Half)
2660 all_mask |= ADVERTISE_1000HALF;
2661 if (mask & ADVERTISED_1000baseT_Full)
2662 all_mask |= ADVERTISE_1000FULL;
2663
2664 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2665 return 0;
2666
2667 if ((tg3_ctrl & all_mask) != all_mask)
2668 return 0;
2669 }
2670 return 1;
2671}
2672
2673static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2674{
2675 u32 curadv, reqadv;
2676
2677 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2678 return 1;
2679
2680 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2681 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2682
2683 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2684 if (curadv != reqadv)
2685 return 0;
2686
2687 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2688 tg3_readphy(tp, MII_LPA, rmtadv);
2689 } else {
2690 /* Reprogram the advertisement register, even if it
2691 * does not affect the current link. If the link
2692 * gets renegotiated in the future, we can save an
2693 * additional renegotiation cycle by advertising
2694 * it correctly in the first place.
2695 */
2696 if (curadv != reqadv) {
2697 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2698 ADVERTISE_PAUSE_ASYM);
2699 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2700 }
2701 }
2702
2703 return 1;
2704}
2705
2706static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2707{
2708 int current_link_up;
2709 u32 bmsr, dummy;
2710 u32 lcl_adv, rmt_adv;
2711 u16 current_speed;
2712 u8 current_duplex;
2713 int i, err;
2714
2715 tw32(MAC_EVENT, 0);
2716
2717 tw32_f(MAC_STATUS,
2718 (MAC_STATUS_SYNC_CHANGED |
2719 MAC_STATUS_CFG_CHANGED |
2720 MAC_STATUS_MI_COMPLETION |
2721 MAC_STATUS_LNKSTATE_CHANGED));
2722 udelay(40);
2723
2724 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2725 tw32_f(MAC_MI_MODE,
2726 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2727 udelay(80);
2728 }
2729
2730 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2731
2732 /* Some third-party PHYs need to be reset on link going
2733 * down.
2734 */
2735 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2736 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2737 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2738 netif_carrier_ok(tp->dev)) {
2739 tg3_readphy(tp, MII_BMSR, &bmsr);
2740 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2741 !(bmsr & BMSR_LSTATUS))
2742 force_reset = 1;
2743 }
2744 if (force_reset)
2745 tg3_phy_reset(tp);
2746
2747 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2748 tg3_readphy(tp, MII_BMSR, &bmsr);
2749 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2750 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2751 bmsr = 0;
2752
2753 if (!(bmsr & BMSR_LSTATUS)) {
2754 err = tg3_init_5401phy_dsp(tp);
2755 if (err)
2756 return err;
2757
2758 tg3_readphy(tp, MII_BMSR, &bmsr);
2759 for (i = 0; i < 1000; i++) {
2760 udelay(10);
2761 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2762 (bmsr & BMSR_LSTATUS)) {
2763 udelay(40);
2764 break;
2765 }
2766 }
2767
2768 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2769 !(bmsr & BMSR_LSTATUS) &&
2770 tp->link_config.active_speed == SPEED_1000) {
2771 err = tg3_phy_reset(tp);
2772 if (!err)
2773 err = tg3_init_5401phy_dsp(tp);
2774 if (err)
2775 return err;
2776 }
2777 }
2778 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2779 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2780 /* 5701 {A0,B0} CRC bug workaround */
2781 tg3_writephy(tp, 0x15, 0x0a75);
2782 tg3_writephy(tp, 0x1c, 0x8c68);
2783 tg3_writephy(tp, 0x1c, 0x8d68);
2784 tg3_writephy(tp, 0x1c, 0x8c68);
2785 }
2786
2787 /* Clear pending interrupts... */
2788 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2789 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2790
2791 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2792 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2793 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2794 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2795
2796 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2797 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2798 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2799 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2800 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2801 else
2802 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2803 }
2804
2805 current_link_up = 0;
2806 current_speed = SPEED_INVALID;
2807 current_duplex = DUPLEX_INVALID;
2808
2809 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2810 u32 val;
2811
2812 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2813 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2814 if (!(val & (1 << 10))) {
2815 val |= (1 << 10);
2816 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2817 goto relink;
2818 }
2819 }
2820
2821 bmsr = 0;
2822 for (i = 0; i < 100; i++) {
2823 tg3_readphy(tp, MII_BMSR, &bmsr);
2824 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2825 (bmsr & BMSR_LSTATUS))
2826 break;
2827 udelay(40);
2828 }
2829
2830 if (bmsr & BMSR_LSTATUS) {
2831 u32 aux_stat, bmcr;
2832
2833 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2834 for (i = 0; i < 2000; i++) {
2835 udelay(10);
2836 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2837 aux_stat)
2838 break;
2839 }
2840
2841 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2842 &current_speed,
2843 &current_duplex);
2844
2845 bmcr = 0;
2846 for (i = 0; i < 200; i++) {
2847 tg3_readphy(tp, MII_BMCR, &bmcr);
2848 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2849 continue;
2850 if (bmcr && bmcr != 0x7fff)
2851 break;
2852 udelay(10);
2853 }
2854
2855 lcl_adv = 0;
2856 rmt_adv = 0;
2857
2858 tp->link_config.active_speed = current_speed;
2859 tp->link_config.active_duplex = current_duplex;
2860
2861 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2862 if ((bmcr & BMCR_ANENABLE) &&
2863 tg3_copper_is_advertising_all(tp,
2864 tp->link_config.advertising)) {
2865 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2866 &rmt_adv))
2867 current_link_up = 1;
2868 }
2869 } else {
2870 if (!(bmcr & BMCR_ANENABLE) &&
2871 tp->link_config.speed == current_speed &&
2872 tp->link_config.duplex == current_duplex &&
2873 tp->link_config.flowctrl ==
2874 tp->link_config.active_flowctrl) {
2875 current_link_up = 1;
2876 }
2877 }
2878
2879 if (current_link_up == 1 &&
2880 tp->link_config.active_duplex == DUPLEX_FULL)
2881 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2882 }
2883
2884relink:
2885 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2886 u32 tmp;
2887
2888 tg3_phy_copper_begin(tp);
2889
2890 tg3_readphy(tp, MII_BMSR, &tmp);
2891 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2892 (tmp & BMSR_LSTATUS))
2893 current_link_up = 1;
2894 }
2895
2896 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2897 if (current_link_up == 1) {
2898 if (tp->link_config.active_speed == SPEED_100 ||
2899 tp->link_config.active_speed == SPEED_10)
2900 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2901 else
2902 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2903 } else
2904 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2905
2906 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2907 if (tp->link_config.active_duplex == DUPLEX_HALF)
2908 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2909
2910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2911 if (current_link_up == 1 &&
2912 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2913 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2914 else
2915 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2916 }
2917
2918 /* ??? Without this setting Netgear GA302T PHY does not
2919 * ??? send/receive packets...
2920 */
2921 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2922 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2923 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2924 tw32_f(MAC_MI_MODE, tp->mi_mode);
2925 udelay(80);
2926 }
2927
2928 tw32_f(MAC_MODE, tp->mac_mode);
2929 udelay(40);
2930
2931 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2932 /* Polled via timer. */
2933 tw32_f(MAC_EVENT, 0);
2934 } else {
2935 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2936 }
2937 udelay(40);
2938
2939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2940 current_link_up == 1 &&
2941 tp->link_config.active_speed == SPEED_1000 &&
2942 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2943 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2944 udelay(120);
2945 tw32_f(MAC_STATUS,
2946 (MAC_STATUS_SYNC_CHANGED |
2947 MAC_STATUS_CFG_CHANGED));
2948 udelay(40);
2949 tg3_write_mem(tp,
2950 NIC_SRAM_FIRMWARE_MBOX,
2951 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2952 }
2953
2954 /* Prevent send BD corruption. */
2955 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2956 u16 oldlnkctl, newlnkctl;
2957
2958 pci_read_config_word(tp->pdev,
2959 tp->pcie_cap + PCI_EXP_LNKCTL,
2960 &oldlnkctl);
2961 if (tp->link_config.active_speed == SPEED_100 ||
2962 tp->link_config.active_speed == SPEED_10)
2963 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
2964 else
2965 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
2966 if (newlnkctl != oldlnkctl)
2967 pci_write_config_word(tp->pdev,
2968 tp->pcie_cap + PCI_EXP_LNKCTL,
2969 newlnkctl);
2970 }
2971
2972 if (current_link_up != netif_carrier_ok(tp->dev)) {
2973 if (current_link_up)
2974 netif_carrier_on(tp->dev);
2975 else
2976 netif_carrier_off(tp->dev);
2977 tg3_link_report(tp);
2978 }
2979
2980 return 0;
2981}
2982
2983struct tg3_fiber_aneginfo {
2984 int state;
2985#define ANEG_STATE_UNKNOWN 0
2986#define ANEG_STATE_AN_ENABLE 1
2987#define ANEG_STATE_RESTART_INIT 2
2988#define ANEG_STATE_RESTART 3
2989#define ANEG_STATE_DISABLE_LINK_OK 4
2990#define ANEG_STATE_ABILITY_DETECT_INIT 5
2991#define ANEG_STATE_ABILITY_DETECT 6
2992#define ANEG_STATE_ACK_DETECT_INIT 7
2993#define ANEG_STATE_ACK_DETECT 8
2994#define ANEG_STATE_COMPLETE_ACK_INIT 9
2995#define ANEG_STATE_COMPLETE_ACK 10
2996#define ANEG_STATE_IDLE_DETECT_INIT 11
2997#define ANEG_STATE_IDLE_DETECT 12
2998#define ANEG_STATE_LINK_OK 13
2999#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3000#define ANEG_STATE_NEXT_PAGE_WAIT 15
3001
3002 u32 flags;
3003#define MR_AN_ENABLE 0x00000001
3004#define MR_RESTART_AN 0x00000002
3005#define MR_AN_COMPLETE 0x00000004
3006#define MR_PAGE_RX 0x00000008
3007#define MR_NP_LOADED 0x00000010
3008#define MR_TOGGLE_TX 0x00000020
3009#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3010#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3011#define MR_LP_ADV_SYM_PAUSE 0x00000100
3012#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3013#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3014#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3015#define MR_LP_ADV_NEXT_PAGE 0x00001000
3016#define MR_TOGGLE_RX 0x00002000
3017#define MR_NP_RX 0x00004000
3018
3019#define MR_LINK_OK 0x80000000
3020
3021 unsigned long link_time, cur_time;
3022
3023 u32 ability_match_cfg;
3024 int ability_match_count;
3025
3026 char ability_match, idle_match, ack_match;
3027
3028 u32 txconfig, rxconfig;
3029#define ANEG_CFG_NP 0x00000080
3030#define ANEG_CFG_ACK 0x00000040
3031#define ANEG_CFG_RF2 0x00000020
3032#define ANEG_CFG_RF1 0x00000010
3033#define ANEG_CFG_PS2 0x00000001
3034#define ANEG_CFG_PS1 0x00008000
3035#define ANEG_CFG_HD 0x00004000
3036#define ANEG_CFG_FD 0x00002000
3037#define ANEG_CFG_INVAL 0x00001f06
3038
3039};
3040#define ANEG_OK 0
3041#define ANEG_DONE 1
3042#define ANEG_TIMER_ENAB 2
3043#define ANEG_FAILED -1
3044
3045#define ANEG_STATE_SETTLE_TIME 10000
3046
3047static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3048 struct tg3_fiber_aneginfo *ap)
3049{
3050 u16 flowctrl;
3051 unsigned long delta;
3052 u32 rx_cfg_reg;
3053 int ret;
3054
3055 if (ap->state == ANEG_STATE_UNKNOWN) {
3056 ap->rxconfig = 0;
3057 ap->link_time = 0;
3058 ap->cur_time = 0;
3059 ap->ability_match_cfg = 0;
3060 ap->ability_match_count = 0;
3061 ap->ability_match = 0;
3062 ap->idle_match = 0;
3063 ap->ack_match = 0;
3064 }
3065 ap->cur_time++;
3066
3067 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3068 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3069
3070 if (rx_cfg_reg != ap->ability_match_cfg) {
3071 ap->ability_match_cfg = rx_cfg_reg;
3072 ap->ability_match = 0;
3073 ap->ability_match_count = 0;
3074 } else {
3075 if (++ap->ability_match_count > 1) {
3076 ap->ability_match = 1;
3077 ap->ability_match_cfg = rx_cfg_reg;
3078 }
3079 }
3080 if (rx_cfg_reg & ANEG_CFG_ACK)
3081 ap->ack_match = 1;
3082 else
3083 ap->ack_match = 0;
3084
3085 ap->idle_match = 0;
3086 } else {
3087 ap->idle_match = 1;
3088 ap->ability_match_cfg = 0;
3089 ap->ability_match_count = 0;
3090 ap->ability_match = 0;
3091 ap->ack_match = 0;
3092
3093 rx_cfg_reg = 0;
3094 }
3095
3096 ap->rxconfig = rx_cfg_reg;
3097 ret = ANEG_OK;
3098
3099 switch(ap->state) {
3100 case ANEG_STATE_UNKNOWN:
3101 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3102 ap->state = ANEG_STATE_AN_ENABLE;
3103
3104 /* fallthru */
3105 case ANEG_STATE_AN_ENABLE:
3106 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3107 if (ap->flags & MR_AN_ENABLE) {
3108 ap->link_time = 0;
3109 ap->cur_time = 0;
3110 ap->ability_match_cfg = 0;
3111 ap->ability_match_count = 0;
3112 ap->ability_match = 0;
3113 ap->idle_match = 0;
3114 ap->ack_match = 0;
3115
3116 ap->state = ANEG_STATE_RESTART_INIT;
3117 } else {
3118 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3119 }
3120 break;
3121
3122 case ANEG_STATE_RESTART_INIT:
3123 ap->link_time = ap->cur_time;
3124 ap->flags &= ~(MR_NP_LOADED);
3125 ap->txconfig = 0;
3126 tw32(MAC_TX_AUTO_NEG, 0);
3127 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3128 tw32_f(MAC_MODE, tp->mac_mode);
3129 udelay(40);
3130
3131 ret = ANEG_TIMER_ENAB;
3132 ap->state = ANEG_STATE_RESTART;
3133
3134 /* fallthru */
3135 case ANEG_STATE_RESTART:
3136 delta = ap->cur_time - ap->link_time;
3137 if (delta > ANEG_STATE_SETTLE_TIME) {
3138 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3139 } else {
3140 ret = ANEG_TIMER_ENAB;
3141 }
3142 break;
3143
3144 case ANEG_STATE_DISABLE_LINK_OK:
3145 ret = ANEG_DONE;
3146 break;
3147
3148 case ANEG_STATE_ABILITY_DETECT_INIT:
3149 ap->flags &= ~(MR_TOGGLE_TX);
3150 ap->txconfig = ANEG_CFG_FD;
3151 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3152 if (flowctrl & ADVERTISE_1000XPAUSE)
3153 ap->txconfig |= ANEG_CFG_PS1;
3154 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3155 ap->txconfig |= ANEG_CFG_PS2;
3156 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3157 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3158 tw32_f(MAC_MODE, tp->mac_mode);
3159 udelay(40);
3160
3161 ap->state = ANEG_STATE_ABILITY_DETECT;
3162 break;
3163
3164 case ANEG_STATE_ABILITY_DETECT:
3165 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3166 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3167 }
3168 break;
3169
3170 case ANEG_STATE_ACK_DETECT_INIT:
3171 ap->txconfig |= ANEG_CFG_ACK;
3172 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3173 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3174 tw32_f(MAC_MODE, tp->mac_mode);
3175 udelay(40);
3176
3177 ap->state = ANEG_STATE_ACK_DETECT;
3178
3179 /* fallthru */
3180 case ANEG_STATE_ACK_DETECT:
3181 if (ap->ack_match != 0) {
3182 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3183 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3184 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3185 } else {
3186 ap->state = ANEG_STATE_AN_ENABLE;
3187 }
3188 } else if (ap->ability_match != 0 &&
3189 ap->rxconfig == 0) {
3190 ap->state = ANEG_STATE_AN_ENABLE;
3191 }
3192 break;
3193
3194 case ANEG_STATE_COMPLETE_ACK_INIT:
3195 if (ap->rxconfig & ANEG_CFG_INVAL) {
3196 ret = ANEG_FAILED;
3197 break;
3198 }
3199 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3200 MR_LP_ADV_HALF_DUPLEX |
3201 MR_LP_ADV_SYM_PAUSE |
3202 MR_LP_ADV_ASYM_PAUSE |
3203 MR_LP_ADV_REMOTE_FAULT1 |
3204 MR_LP_ADV_REMOTE_FAULT2 |
3205 MR_LP_ADV_NEXT_PAGE |
3206 MR_TOGGLE_RX |
3207 MR_NP_RX);
3208 if (ap->rxconfig & ANEG_CFG_FD)
3209 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3210 if (ap->rxconfig & ANEG_CFG_HD)
3211 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3212 if (ap->rxconfig & ANEG_CFG_PS1)
3213 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3214 if (ap->rxconfig & ANEG_CFG_PS2)
3215 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3216 if (ap->rxconfig & ANEG_CFG_RF1)
3217 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3218 if (ap->rxconfig & ANEG_CFG_RF2)
3219 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3220 if (ap->rxconfig & ANEG_CFG_NP)
3221 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3222
3223 ap->link_time = ap->cur_time;
3224
3225 ap->flags ^= (MR_TOGGLE_TX);
3226 if (ap->rxconfig & 0x0008)
3227 ap->flags |= MR_TOGGLE_RX;
3228 if (ap->rxconfig & ANEG_CFG_NP)
3229 ap->flags |= MR_NP_RX;
3230 ap->flags |= MR_PAGE_RX;
3231
3232 ap->state = ANEG_STATE_COMPLETE_ACK;
3233 ret = ANEG_TIMER_ENAB;
3234 break;
3235
3236 case ANEG_STATE_COMPLETE_ACK:
3237 if (ap->ability_match != 0 &&
3238 ap->rxconfig == 0) {
3239 ap->state = ANEG_STATE_AN_ENABLE;
3240 break;
3241 }
3242 delta = ap->cur_time - ap->link_time;
3243 if (delta > ANEG_STATE_SETTLE_TIME) {
3244 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3245 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3246 } else {
3247 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3248 !(ap->flags & MR_NP_RX)) {
3249 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3250 } else {
3251 ret = ANEG_FAILED;
3252 }
3253 }
3254 }
3255 break;
3256
3257 case ANEG_STATE_IDLE_DETECT_INIT:
3258 ap->link_time = ap->cur_time;
3259 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3260 tw32_f(MAC_MODE, tp->mac_mode);
3261 udelay(40);
3262
3263 ap->state = ANEG_STATE_IDLE_DETECT;
3264 ret = ANEG_TIMER_ENAB;
3265 break;
3266
3267 case ANEG_STATE_IDLE_DETECT:
3268 if (ap->ability_match != 0 &&
3269 ap->rxconfig == 0) {
3270 ap->state = ANEG_STATE_AN_ENABLE;
3271 break;
3272 }
3273 delta = ap->cur_time - ap->link_time;
3274 if (delta > ANEG_STATE_SETTLE_TIME) {
3275 /* XXX another gem from the Broadcom driver :( */
3276 ap->state = ANEG_STATE_LINK_OK;
3277 }
3278 break;
3279
3280 case ANEG_STATE_LINK_OK:
3281 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3282 ret = ANEG_DONE;
3283 break;
3284
3285 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3286 /* ??? unimplemented */
3287 break;
3288
3289 case ANEG_STATE_NEXT_PAGE_WAIT:
3290 /* ??? unimplemented */
3291 break;
3292
3293 default:
3294 ret = ANEG_FAILED;
3295 break;
3296 }
3297
3298 return ret;
3299}
3300
3301static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3302{
3303 int res = 0;
3304 struct tg3_fiber_aneginfo aninfo;
3305 int status = ANEG_FAILED;
3306 unsigned int tick;
3307 u32 tmp;
3308
3309 tw32_f(MAC_TX_AUTO_NEG, 0);
3310
3311 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3312 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3313 udelay(40);
3314
3315 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3316 udelay(40);
3317
3318 memset(&aninfo, 0, sizeof(aninfo));
3319 aninfo.flags |= MR_AN_ENABLE;
3320 aninfo.state = ANEG_STATE_UNKNOWN;
3321 aninfo.cur_time = 0;
3322 tick = 0;
3323 while (++tick < 195000) {
3324 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3325 if (status == ANEG_DONE || status == ANEG_FAILED)
3326 break;
3327
3328 udelay(1);
3329 }
3330
3331 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3332 tw32_f(MAC_MODE, tp->mac_mode);
3333 udelay(40);
3334
3335 *txflags = aninfo.txconfig;
3336 *rxflags = aninfo.flags;
3337
3338 if (status == ANEG_DONE &&
3339 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3340 MR_LP_ADV_FULL_DUPLEX)))
3341 res = 1;
3342
3343 return res;
3344}
3345
3346static void tg3_init_bcm8002(struct tg3 *tp)
3347{
3348 u32 mac_status = tr32(MAC_STATUS);
3349 int i;
3350
3351 /* Reset when initting first time or we have a link. */
3352 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3353 !(mac_status & MAC_STATUS_PCS_SYNCED))
3354 return;
3355
3356 /* Set PLL lock range. */
3357 tg3_writephy(tp, 0x16, 0x8007);
3358
3359 /* SW reset */
3360 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3361
3362 /* Wait for reset to complete. */
3363 /* XXX schedule_timeout() ... */
3364 for (i = 0; i < 500; i++)
3365 udelay(10);
3366
3367 /* Config mode; select PMA/Ch 1 regs. */
3368 tg3_writephy(tp, 0x10, 0x8411);
3369
3370 /* Enable auto-lock and comdet, select txclk for tx. */
3371 tg3_writephy(tp, 0x11, 0x0a10);
3372
3373 tg3_writephy(tp, 0x18, 0x00a0);
3374 tg3_writephy(tp, 0x16, 0x41ff);
3375
3376 /* Assert and deassert POR. */
3377 tg3_writephy(tp, 0x13, 0x0400);
3378 udelay(40);
3379 tg3_writephy(tp, 0x13, 0x0000);
3380
3381 tg3_writephy(tp, 0x11, 0x0a50);
3382 udelay(40);
3383 tg3_writephy(tp, 0x11, 0x0a10);
3384
3385 /* Wait for signal to stabilize */
3386 /* XXX schedule_timeout() ... */
3387 for (i = 0; i < 15000; i++)
3388 udelay(10);
3389
3390 /* Deselect the channel register so we can read the PHYID
3391 * later.
3392 */
3393 tg3_writephy(tp, 0x10, 0x8011);
3394}
3395
3396static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3397{
3398 u16 flowctrl;
3399 u32 sg_dig_ctrl, sg_dig_status;
3400 u32 serdes_cfg, expected_sg_dig_ctrl;
3401 int workaround, port_a;
3402 int current_link_up;
3403
3404 serdes_cfg = 0;
3405 expected_sg_dig_ctrl = 0;
3406 workaround = 0;
3407 port_a = 1;
3408 current_link_up = 0;
3409
3410 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3411 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3412 workaround = 1;
3413 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3414 port_a = 0;
3415
3416 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3417 /* preserve bits 20-23 for voltage regulator */
3418 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3419 }
3420
3421 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3422
3423 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3424 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3425 if (workaround) {
3426 u32 val = serdes_cfg;
3427
3428 if (port_a)
3429 val |= 0xc010000;
3430 else
3431 val |= 0x4010000;
3432 tw32_f(MAC_SERDES_CFG, val);
3433 }
3434
3435 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3436 }
3437 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3438 tg3_setup_flow_control(tp, 0, 0);
3439 current_link_up = 1;
3440 }
3441 goto out;
3442 }
3443
3444 /* Want auto-negotiation. */
3445 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3446
3447 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3448 if (flowctrl & ADVERTISE_1000XPAUSE)
3449 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3450 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3451 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3452
3453 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3454 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3455 tp->serdes_counter &&
3456 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3457 MAC_STATUS_RCVD_CFG)) ==
3458 MAC_STATUS_PCS_SYNCED)) {
3459 tp->serdes_counter--;
3460 current_link_up = 1;
3461 goto out;
3462 }
3463restart_autoneg:
3464 if (workaround)
3465 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3466 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3467 udelay(5);
3468 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3469
3470 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3471 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3472 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3473 MAC_STATUS_SIGNAL_DET)) {
3474 sg_dig_status = tr32(SG_DIG_STATUS);
3475 mac_status = tr32(MAC_STATUS);
3476
3477 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3478 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3479 u32 local_adv = 0, remote_adv = 0;
3480
3481 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3482 local_adv |= ADVERTISE_1000XPAUSE;
3483 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3484 local_adv |= ADVERTISE_1000XPSE_ASYM;
3485
3486 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3487 remote_adv |= LPA_1000XPAUSE;
3488 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3489 remote_adv |= LPA_1000XPAUSE_ASYM;
3490
3491 tg3_setup_flow_control(tp, local_adv, remote_adv);
3492 current_link_up = 1;
3493 tp->serdes_counter = 0;
3494 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3495 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3496 if (tp->serdes_counter)
3497 tp->serdes_counter--;
3498 else {
3499 if (workaround) {
3500 u32 val = serdes_cfg;
3501
3502 if (port_a)
3503 val |= 0xc010000;
3504 else
3505 val |= 0x4010000;
3506
3507 tw32_f(MAC_SERDES_CFG, val);
3508 }
3509
3510 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3511 udelay(40);
3512
3513 /* Link parallel detection - link is up */
3514 /* only if we have PCS_SYNC and not */
3515 /* receiving config code words */
3516 mac_status = tr32(MAC_STATUS);
3517 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3518 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3519 tg3_setup_flow_control(tp, 0, 0);
3520 current_link_up = 1;
3521 tp->tg3_flags2 |=
3522 TG3_FLG2_PARALLEL_DETECT;
3523 tp->serdes_counter =
3524 SERDES_PARALLEL_DET_TIMEOUT;
3525 } else
3526 goto restart_autoneg;
3527 }
3528 }
3529 } else {
3530 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3531 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3532 }
3533
3534out:
3535 return current_link_up;
3536}
3537
3538static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3539{
3540 int current_link_up = 0;
3541
3542 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3543 goto out;
3544
3545 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3546 u32 txflags, rxflags;
3547 int i;
3548
3549 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3550 u32 local_adv = 0, remote_adv = 0;
3551
3552 if (txflags & ANEG_CFG_PS1)
3553 local_adv |= ADVERTISE_1000XPAUSE;
3554 if (txflags & ANEG_CFG_PS2)
3555 local_adv |= ADVERTISE_1000XPSE_ASYM;
3556
3557 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3558 remote_adv |= LPA_1000XPAUSE;
3559 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3560 remote_adv |= LPA_1000XPAUSE_ASYM;
3561
3562 tg3_setup_flow_control(tp, local_adv, remote_adv);
3563
3564 current_link_up = 1;
3565 }
3566 for (i = 0; i < 30; i++) {
3567 udelay(20);
3568 tw32_f(MAC_STATUS,
3569 (MAC_STATUS_SYNC_CHANGED |
3570 MAC_STATUS_CFG_CHANGED));
3571 udelay(40);
3572 if ((tr32(MAC_STATUS) &
3573 (MAC_STATUS_SYNC_CHANGED |
3574 MAC_STATUS_CFG_CHANGED)) == 0)
3575 break;
3576 }
3577
3578 mac_status = tr32(MAC_STATUS);
3579 if (current_link_up == 0 &&
3580 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3581 !(mac_status & MAC_STATUS_RCVD_CFG))
3582 current_link_up = 1;
3583 } else {
3584 tg3_setup_flow_control(tp, 0, 0);
3585
3586 /* Forcing 1000FD link up. */
3587 current_link_up = 1;
3588
3589 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3590 udelay(40);
3591
3592 tw32_f(MAC_MODE, tp->mac_mode);
3593 udelay(40);
3594 }
3595
3596out:
3597 return current_link_up;
3598}
3599
3600static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3601{
3602 u32 orig_pause_cfg;
3603 u16 orig_active_speed;
3604 u8 orig_active_duplex;
3605 u32 mac_status;
3606 int current_link_up;
3607 int i;
3608
3609 orig_pause_cfg = tp->link_config.active_flowctrl;
3610 orig_active_speed = tp->link_config.active_speed;
3611 orig_active_duplex = tp->link_config.active_duplex;
3612
3613 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3614 netif_carrier_ok(tp->dev) &&
3615 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3616 mac_status = tr32(MAC_STATUS);
3617 mac_status &= (MAC_STATUS_PCS_SYNCED |
3618 MAC_STATUS_SIGNAL_DET |
3619 MAC_STATUS_CFG_CHANGED |
3620 MAC_STATUS_RCVD_CFG);
3621 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3622 MAC_STATUS_SIGNAL_DET)) {
3623 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3624 MAC_STATUS_CFG_CHANGED));
3625 return 0;
3626 }
3627 }
3628
3629 tw32_f(MAC_TX_AUTO_NEG, 0);
3630
3631 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3632 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3633 tw32_f(MAC_MODE, tp->mac_mode);
3634 udelay(40);
3635
3636 if (tp->phy_id == PHY_ID_BCM8002)
3637 tg3_init_bcm8002(tp);
3638
3639 /* Enable link change event even when serdes polling. */
3640 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3641 udelay(40);
3642
3643 current_link_up = 0;
3644 mac_status = tr32(MAC_STATUS);
3645
3646 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3647 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3648 else
3649 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3650
3651 tp->hw_status->status =
3652 (SD_STATUS_UPDATED |
3653 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3654
3655 for (i = 0; i < 100; i++) {
3656 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3657 MAC_STATUS_CFG_CHANGED));
3658 udelay(5);
3659 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3660 MAC_STATUS_CFG_CHANGED |
3661 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3662 break;
3663 }
3664
3665 mac_status = tr32(MAC_STATUS);
3666 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3667 current_link_up = 0;
3668 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3669 tp->serdes_counter == 0) {
3670 tw32_f(MAC_MODE, (tp->mac_mode |
3671 MAC_MODE_SEND_CONFIGS));
3672 udelay(1);
3673 tw32_f(MAC_MODE, tp->mac_mode);
3674 }
3675 }
3676
3677 if (current_link_up == 1) {
3678 tp->link_config.active_speed = SPEED_1000;
3679 tp->link_config.active_duplex = DUPLEX_FULL;
3680 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3681 LED_CTRL_LNKLED_OVERRIDE |
3682 LED_CTRL_1000MBPS_ON));
3683 } else {
3684 tp->link_config.active_speed = SPEED_INVALID;
3685 tp->link_config.active_duplex = DUPLEX_INVALID;
3686 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3687 LED_CTRL_LNKLED_OVERRIDE |
3688 LED_CTRL_TRAFFIC_OVERRIDE));
3689 }
3690
3691 if (current_link_up != netif_carrier_ok(tp->dev)) {
3692 if (current_link_up)
3693 netif_carrier_on(tp->dev);
3694 else
3695 netif_carrier_off(tp->dev);
3696 tg3_link_report(tp);
3697 } else {
3698 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3699 if (orig_pause_cfg != now_pause_cfg ||
3700 orig_active_speed != tp->link_config.active_speed ||
3701 orig_active_duplex != tp->link_config.active_duplex)
3702 tg3_link_report(tp);
3703 }
3704
3705 return 0;
3706}
3707
3708static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3709{
3710 int current_link_up, err = 0;
3711 u32 bmsr, bmcr;
3712 u16 current_speed;
3713 u8 current_duplex;
3714 u32 local_adv, remote_adv;
3715
3716 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3717 tw32_f(MAC_MODE, tp->mac_mode);
3718 udelay(40);
3719
3720 tw32(MAC_EVENT, 0);
3721
3722 tw32_f(MAC_STATUS,
3723 (MAC_STATUS_SYNC_CHANGED |
3724 MAC_STATUS_CFG_CHANGED |
3725 MAC_STATUS_MI_COMPLETION |
3726 MAC_STATUS_LNKSTATE_CHANGED));
3727 udelay(40);
3728
3729 if (force_reset)
3730 tg3_phy_reset(tp);
3731
3732 current_link_up = 0;
3733 current_speed = SPEED_INVALID;
3734 current_duplex = DUPLEX_INVALID;
3735
3736 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3737 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3738 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3739 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3740 bmsr |= BMSR_LSTATUS;
3741 else
3742 bmsr &= ~BMSR_LSTATUS;
3743 }
3744
3745 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3746
3747 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3748 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3749 /* do nothing, just check for link up at the end */
3750 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3751 u32 adv, new_adv;
3752
3753 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3754 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3755 ADVERTISE_1000XPAUSE |
3756 ADVERTISE_1000XPSE_ASYM |
3757 ADVERTISE_SLCT);
3758
3759 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3760
3761 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3762 new_adv |= ADVERTISE_1000XHALF;
3763 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3764 new_adv |= ADVERTISE_1000XFULL;
3765
3766 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3767 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3768 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3769 tg3_writephy(tp, MII_BMCR, bmcr);
3770
3771 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3772 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3773 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3774
3775 return err;
3776 }
3777 } else {
3778 u32 new_bmcr;
3779
3780 bmcr &= ~BMCR_SPEED1000;
3781 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3782
3783 if (tp->link_config.duplex == DUPLEX_FULL)
3784 new_bmcr |= BMCR_FULLDPLX;
3785
3786 if (new_bmcr != bmcr) {
3787 /* BMCR_SPEED1000 is a reserved bit that needs
3788 * to be set on write.
3789 */
3790 new_bmcr |= BMCR_SPEED1000;
3791
3792 /* Force a linkdown */
3793 if (netif_carrier_ok(tp->dev)) {
3794 u32 adv;
3795
3796 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3797 adv &= ~(ADVERTISE_1000XFULL |
3798 ADVERTISE_1000XHALF |
3799 ADVERTISE_SLCT);
3800 tg3_writephy(tp, MII_ADVERTISE, adv);
3801 tg3_writephy(tp, MII_BMCR, bmcr |
3802 BMCR_ANRESTART |
3803 BMCR_ANENABLE);
3804 udelay(10);
3805 netif_carrier_off(tp->dev);
3806 }
3807 tg3_writephy(tp, MII_BMCR, new_bmcr);
3808 bmcr = new_bmcr;
3809 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3810 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3811 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3812 ASIC_REV_5714) {
3813 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3814 bmsr |= BMSR_LSTATUS;
3815 else
3816 bmsr &= ~BMSR_LSTATUS;
3817 }
3818 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3819 }
3820 }
3821
3822 if (bmsr & BMSR_LSTATUS) {
3823 current_speed = SPEED_1000;
3824 current_link_up = 1;
3825 if (bmcr & BMCR_FULLDPLX)
3826 current_duplex = DUPLEX_FULL;
3827 else
3828 current_duplex = DUPLEX_HALF;
3829
3830 local_adv = 0;
3831 remote_adv = 0;
3832
3833 if (bmcr & BMCR_ANENABLE) {
3834 u32 common;
3835
3836 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3837 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3838 common = local_adv & remote_adv;
3839 if (common & (ADVERTISE_1000XHALF |
3840 ADVERTISE_1000XFULL)) {
3841 if (common & ADVERTISE_1000XFULL)
3842 current_duplex = DUPLEX_FULL;
3843 else
3844 current_duplex = DUPLEX_HALF;
3845 }
3846 else
3847 current_link_up = 0;
3848 }
3849 }
3850
3851 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3852 tg3_setup_flow_control(tp, local_adv, remote_adv);
3853
3854 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3855 if (tp->link_config.active_duplex == DUPLEX_HALF)
3856 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3857
3858 tw32_f(MAC_MODE, tp->mac_mode);
3859 udelay(40);
3860
3861 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3862
3863 tp->link_config.active_speed = current_speed;
3864 tp->link_config.active_duplex = current_duplex;
3865
3866 if (current_link_up != netif_carrier_ok(tp->dev)) {
3867 if (current_link_up)
3868 netif_carrier_on(tp->dev);
3869 else {
3870 netif_carrier_off(tp->dev);
3871 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3872 }
3873 tg3_link_report(tp);
3874 }
3875 return err;
3876}
3877
3878static void tg3_serdes_parallel_detect(struct tg3 *tp)
3879{
3880 if (tp->serdes_counter) {
3881 /* Give autoneg time to complete. */
3882 tp->serdes_counter--;
3883 return;
3884 }
3885 if (!netif_carrier_ok(tp->dev) &&
3886 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3887 u32 bmcr;
3888
3889 tg3_readphy(tp, MII_BMCR, &bmcr);
3890 if (bmcr & BMCR_ANENABLE) {
3891 u32 phy1, phy2;
3892
3893 /* Select shadow register 0x1f */
3894 tg3_writephy(tp, 0x1c, 0x7c00);
3895 tg3_readphy(tp, 0x1c, &phy1);
3896
3897 /* Select expansion interrupt status register */
3898 tg3_writephy(tp, 0x17, 0x0f01);
3899 tg3_readphy(tp, 0x15, &phy2);
3900 tg3_readphy(tp, 0x15, &phy2);
3901
3902 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3903 /* We have signal detect and not receiving
3904 * config code words, link is up by parallel
3905 * detection.
3906 */
3907
3908 bmcr &= ~BMCR_ANENABLE;
3909 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3910 tg3_writephy(tp, MII_BMCR, bmcr);
3911 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3912 }
3913 }
3914 }
3915 else if (netif_carrier_ok(tp->dev) &&
3916 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3917 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3918 u32 phy2;
3919
3920 /* Select expansion interrupt status register */
3921 tg3_writephy(tp, 0x17, 0x0f01);
3922 tg3_readphy(tp, 0x15, &phy2);
3923 if (phy2 & 0x20) {
3924 u32 bmcr;
3925
3926 /* Config code words received, turn on autoneg. */
3927 tg3_readphy(tp, MII_BMCR, &bmcr);
3928 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3929
3930 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3931
3932 }
3933 }
3934}
3935
3936static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3937{
3938 int err;
3939
3940 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3941 err = tg3_setup_fiber_phy(tp, force_reset);
3942 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3943 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3944 } else {
3945 err = tg3_setup_copper_phy(tp, force_reset);
3946 }
3947
3948 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
3949 u32 val, scale;
3950
3951 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3952 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3953 scale = 65;
3954 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3955 scale = 6;
3956 else
3957 scale = 12;
3958
3959 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3960 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3961 tw32(GRC_MISC_CFG, val);
3962 }
3963
3964 if (tp->link_config.active_speed == SPEED_1000 &&
3965 tp->link_config.active_duplex == DUPLEX_HALF)
3966 tw32(MAC_TX_LENGTHS,
3967 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3968 (6 << TX_LENGTHS_IPG_SHIFT) |
3969 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3970 else
3971 tw32(MAC_TX_LENGTHS,
3972 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3973 (6 << TX_LENGTHS_IPG_SHIFT) |
3974 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3975
3976 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3977 if (netif_carrier_ok(tp->dev)) {
3978 tw32(HOSTCC_STAT_COAL_TICKS,
3979 tp->coal.stats_block_coalesce_usecs);
3980 } else {
3981 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3982 }
3983 }
3984
3985 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3986 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3987 if (!netif_carrier_ok(tp->dev))
3988 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3989 tp->pwrmgmt_thresh;
3990 else
3991 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3992 tw32(PCIE_PWR_MGMT_THRESH, val);
3993 }
3994
3995 return err;
3996}
3997
3998/* This is called whenever we suspect that the system chipset is re-
3999 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4000 * is bogus tx completions. We try to recover by setting the
4001 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4002 * in the workqueue.
4003 */
4004static void tg3_tx_recover(struct tg3 *tp)
4005{
4006 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4007 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4008
4009 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4010 "mapped I/O cycles to the network device, attempting to "
4011 "recover. Please report the problem to the driver maintainer "
4012 "and include system chipset information.\n", tp->dev->name);
4013
4014 spin_lock(&tp->lock);
4015 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4016 spin_unlock(&tp->lock);
4017}
4018
4019static inline u32 tg3_tx_avail(struct tg3 *tp)
4020{
4021 smp_mb();
4022 return (tp->tx_pending -
4023 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4024}
4025
4026/* Tigon3 never reports partial packet sends. So we do not
4027 * need special logic to handle SKBs that have not had all
4028 * of their frags sent yet, like SunGEM does.
4029 */
4030static void tg3_tx(struct tg3 *tp)
4031{
4032 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4033 u32 sw_idx = tp->tx_cons;
4034
4035 while (sw_idx != hw_idx) {
4036 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4037 struct sk_buff *skb = ri->skb;
4038 int i, tx_bug = 0;
4039
4040 if (unlikely(skb == NULL)) {
4041 tg3_tx_recover(tp);
4042 return;
4043 }
4044
4045 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4046
4047 ri->skb = NULL;
4048
4049 sw_idx = NEXT_TX(sw_idx);
4050
4051 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4052 ri = &tp->tx_buffers[sw_idx];
4053 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4054 tx_bug = 1;
4055 sw_idx = NEXT_TX(sw_idx);
4056 }
4057
4058 dev_kfree_skb(skb);
4059
4060 if (unlikely(tx_bug)) {
4061 tg3_tx_recover(tp);
4062 return;
4063 }
4064 }
4065
4066 tp->tx_cons = sw_idx;
4067
4068 /* Need to make the tx_cons update visible to tg3_start_xmit()
4069 * before checking for netif_queue_stopped(). Without the
4070 * memory barrier, there is a small possibility that tg3_start_xmit()
4071 * will miss it and cause the queue to be stopped forever.
4072 */
4073 smp_mb();
4074
4075 if (unlikely(netif_queue_stopped(tp->dev) &&
4076 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4077 netif_tx_lock(tp->dev);
4078 if (netif_queue_stopped(tp->dev) &&
4079 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4080 netif_wake_queue(tp->dev);
4081 netif_tx_unlock(tp->dev);
4082 }
4083}
4084
4085/* Returns size of skb allocated or < 0 on error.
4086 *
4087 * We only need to fill in the address because the other members
4088 * of the RX descriptor are invariant, see tg3_init_rings.
4089 *
4090 * Note the purposeful assymetry of cpu vs. chip accesses. For
4091 * posting buffers we only dirty the first cache line of the RX
4092 * descriptor (containing the address). Whereas for the RX status
4093 * buffers the cpu only reads the last cacheline of the RX descriptor
4094 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4095 */
4096static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4097 int src_idx, u32 dest_idx_unmasked)
4098{
4099 struct tg3_rx_buffer_desc *desc;
4100 struct ring_info *map, *src_map;
4101 struct sk_buff *skb;
4102 dma_addr_t mapping;
4103 int skb_size, dest_idx;
4104
4105 src_map = NULL;
4106 switch (opaque_key) {
4107 case RXD_OPAQUE_RING_STD:
4108 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4109 desc = &tp->rx_std[dest_idx];
4110 map = &tp->rx_std_buffers[dest_idx];
4111 if (src_idx >= 0)
4112 src_map = &tp->rx_std_buffers[src_idx];
4113 skb_size = tp->rx_pkt_buf_sz;
4114 break;
4115
4116 case RXD_OPAQUE_RING_JUMBO:
4117 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4118 desc = &tp->rx_jumbo[dest_idx];
4119 map = &tp->rx_jumbo_buffers[dest_idx];
4120 if (src_idx >= 0)
4121 src_map = &tp->rx_jumbo_buffers[src_idx];
4122 skb_size = RX_JUMBO_PKT_BUF_SZ;
4123 break;
4124
4125 default:
4126 return -EINVAL;
4127 }
4128
4129 /* Do not overwrite any of the map or rp information
4130 * until we are sure we can commit to a new buffer.
4131 *
4132 * Callers depend upon this behavior and assume that
4133 * we leave everything unchanged if we fail.
4134 */
4135 skb = netdev_alloc_skb(tp->dev, skb_size);
4136 if (skb == NULL)
4137 return -ENOMEM;
4138
4139 skb_reserve(skb, tp->rx_offset);
4140
4141 mapping = pci_map_single(tp->pdev, skb->data,
4142 skb_size - tp->rx_offset,
4143 PCI_DMA_FROMDEVICE);
4144
4145 map->skb = skb;
4146 pci_unmap_addr_set(map, mapping, mapping);
4147
4148 if (src_map != NULL)
4149 src_map->skb = NULL;
4150
4151 desc->addr_hi = ((u64)mapping >> 32);
4152 desc->addr_lo = ((u64)mapping & 0xffffffff);
4153
4154 return skb_size;
4155}
4156
4157/* We only need to move over in the address because the other
4158 * members of the RX descriptor are invariant. See notes above
4159 * tg3_alloc_rx_skb for full details.
4160 */
4161static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4162 int src_idx, u32 dest_idx_unmasked)
4163{
4164 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4165 struct ring_info *src_map, *dest_map;
4166 int dest_idx;
4167
4168 switch (opaque_key) {
4169 case RXD_OPAQUE_RING_STD:
4170 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4171 dest_desc = &tp->rx_std[dest_idx];
4172 dest_map = &tp->rx_std_buffers[dest_idx];
4173 src_desc = &tp->rx_std[src_idx];
4174 src_map = &tp->rx_std_buffers[src_idx];
4175 break;
4176
4177 case RXD_OPAQUE_RING_JUMBO:
4178 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4179 dest_desc = &tp->rx_jumbo[dest_idx];
4180 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4181 src_desc = &tp->rx_jumbo[src_idx];
4182 src_map = &tp->rx_jumbo_buffers[src_idx];
4183 break;
4184
4185 default:
4186 return;
4187 }
4188
4189 dest_map->skb = src_map->skb;
4190 pci_unmap_addr_set(dest_map, mapping,
4191 pci_unmap_addr(src_map, mapping));
4192 dest_desc->addr_hi = src_desc->addr_hi;
4193 dest_desc->addr_lo = src_desc->addr_lo;
4194
4195 src_map->skb = NULL;
4196}
4197
4198#if TG3_VLAN_TAG_USED
4199static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4200{
4201 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4202}
4203#endif
4204
4205/* The RX ring scheme is composed of multiple rings which post fresh
4206 * buffers to the chip, and one special ring the chip uses to report
4207 * status back to the host.
4208 *
4209 * The special ring reports the status of received packets to the
4210 * host. The chip does not write into the original descriptor the
4211 * RX buffer was obtained from. The chip simply takes the original
4212 * descriptor as provided by the host, updates the status and length
4213 * field, then writes this into the next status ring entry.
4214 *
4215 * Each ring the host uses to post buffers to the chip is described
4216 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4217 * it is first placed into the on-chip ram. When the packet's length
4218 * is known, it walks down the TG3_BDINFO entries to select the ring.
4219 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4220 * which is within the range of the new packet's length is chosen.
4221 *
4222 * The "separate ring for rx status" scheme may sound queer, but it makes
4223 * sense from a cache coherency perspective. If only the host writes
4224 * to the buffer post rings, and only the chip writes to the rx status
4225 * rings, then cache lines never move beyond shared-modified state.
4226 * If both the host and chip were to write into the same ring, cache line
4227 * eviction could occur since both entities want it in an exclusive state.
4228 */
4229static int tg3_rx(struct tg3 *tp, int budget)
4230{
4231 u32 work_mask, rx_std_posted = 0;
4232 u32 sw_idx = tp->rx_rcb_ptr;
4233 u16 hw_idx;
4234 int received;
4235
4236 hw_idx = tp->hw_status->idx[0].rx_producer;
4237 /*
4238 * We need to order the read of hw_idx and the read of
4239 * the opaque cookie.
4240 */
4241 rmb();
4242 work_mask = 0;
4243 received = 0;
4244 while (sw_idx != hw_idx && budget > 0) {
4245 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4246 unsigned int len;
4247 struct sk_buff *skb;
4248 dma_addr_t dma_addr;
4249 u32 opaque_key, desc_idx, *post_ptr;
4250
4251 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4252 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4253 if (opaque_key == RXD_OPAQUE_RING_STD) {
4254 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4255 mapping);
4256 skb = tp->rx_std_buffers[desc_idx].skb;
4257 post_ptr = &tp->rx_std_ptr;
4258 rx_std_posted++;
4259 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4260 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4261 mapping);
4262 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4263 post_ptr = &tp->rx_jumbo_ptr;
4264 }
4265 else {
4266 goto next_pkt_nopost;
4267 }
4268
4269 work_mask |= opaque_key;
4270
4271 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4272 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4273 drop_it:
4274 tg3_recycle_rx(tp, opaque_key,
4275 desc_idx, *post_ptr);
4276 drop_it_no_recycle:
4277 /* Other statistics kept track of by card. */
4278 tp->net_stats.rx_dropped++;
4279 goto next_pkt;
4280 }
4281
4282 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4283 ETH_FCS_LEN;
4284
4285 if (len > RX_COPY_THRESHOLD
4286 && tp->rx_offset == NET_IP_ALIGN
4287 /* rx_offset will likely not equal NET_IP_ALIGN
4288 * if this is a 5701 card running in PCI-X mode
4289 * [see tg3_get_invariants()]
4290 */
4291 ) {
4292 int skb_size;
4293
4294 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4295 desc_idx, *post_ptr);
4296 if (skb_size < 0)
4297 goto drop_it;
4298
4299 pci_unmap_single(tp->pdev, dma_addr,
4300 skb_size - tp->rx_offset,
4301 PCI_DMA_FROMDEVICE);
4302
4303 skb_put(skb, len);
4304 } else {
4305 struct sk_buff *copy_skb;
4306
4307 tg3_recycle_rx(tp, opaque_key,
4308 desc_idx, *post_ptr);
4309
4310 copy_skb = netdev_alloc_skb(tp->dev,
4311 len + TG3_RAW_IP_ALIGN);
4312 if (copy_skb == NULL)
4313 goto drop_it_no_recycle;
4314
4315 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4316 skb_put(copy_skb, len);
4317 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4318 skb_copy_from_linear_data(skb, copy_skb->data, len);
4319 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4320
4321 /* We'll reuse the original ring buffer. */
4322 skb = copy_skb;
4323 }
4324
4325 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4326 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4327 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4328 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4329 skb->ip_summed = CHECKSUM_UNNECESSARY;
4330 else
4331 skb->ip_summed = CHECKSUM_NONE;
4332
4333 skb->protocol = eth_type_trans(skb, tp->dev);
4334#if TG3_VLAN_TAG_USED
4335 if (tp->vlgrp != NULL &&
4336 desc->type_flags & RXD_FLAG_VLAN) {
4337 tg3_vlan_rx(tp, skb,
4338 desc->err_vlan & RXD_VLAN_MASK);
4339 } else
4340#endif
4341 netif_receive_skb(skb);
4342
4343 received++;
4344 budget--;
4345
4346next_pkt:
4347 (*post_ptr)++;
4348
4349 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4350 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4351
4352 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4353 TG3_64BIT_REG_LOW, idx);
4354 work_mask &= ~RXD_OPAQUE_RING_STD;
4355 rx_std_posted = 0;
4356 }
4357next_pkt_nopost:
4358 sw_idx++;
4359 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4360
4361 /* Refresh hw_idx to see if there is new work */
4362 if (sw_idx == hw_idx) {
4363 hw_idx = tp->hw_status->idx[0].rx_producer;
4364 rmb();
4365 }
4366 }
4367
4368 /* ACK the status ring. */
4369 tp->rx_rcb_ptr = sw_idx;
4370 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4371
4372 /* Refill RX ring(s). */
4373 if (work_mask & RXD_OPAQUE_RING_STD) {
4374 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4375 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4376 sw_idx);
4377 }
4378 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4379 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4380 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4381 sw_idx);
4382 }
4383 mmiowb();
4384
4385 return received;
4386}
4387
4388static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4389{
4390 struct tg3_hw_status *sblk = tp->hw_status;
4391
4392 /* handle link change and other phy events */
4393 if (!(tp->tg3_flags &
4394 (TG3_FLAG_USE_LINKCHG_REG |
4395 TG3_FLAG_POLL_SERDES))) {
4396 if (sblk->status & SD_STATUS_LINK_CHG) {
4397 sblk->status = SD_STATUS_UPDATED |
4398 (sblk->status & ~SD_STATUS_LINK_CHG);
4399 spin_lock(&tp->lock);
4400 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4401 tw32_f(MAC_STATUS,
4402 (MAC_STATUS_SYNC_CHANGED |
4403 MAC_STATUS_CFG_CHANGED |
4404 MAC_STATUS_MI_COMPLETION |
4405 MAC_STATUS_LNKSTATE_CHANGED));
4406 udelay(40);
4407 } else
4408 tg3_setup_phy(tp, 0);
4409 spin_unlock(&tp->lock);
4410 }
4411 }
4412
4413 /* run TX completion thread */
4414 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4415 tg3_tx(tp);
4416 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4417 return work_done;
4418 }
4419
4420 /* run RX thread, within the bounds set by NAPI.
4421 * All RX "locking" is done by ensuring outside
4422 * code synchronizes with tg3->napi.poll()
4423 */
4424 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4425 work_done += tg3_rx(tp, budget - work_done);
4426
4427 return work_done;
4428}
4429
4430static int tg3_poll(struct napi_struct *napi, int budget)
4431{
4432 struct tg3 *tp = container_of(napi, struct tg3, napi);
4433 int work_done = 0;
4434 struct tg3_hw_status *sblk = tp->hw_status;
4435
4436 while (1) {
4437 work_done = tg3_poll_work(tp, work_done, budget);
4438
4439 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4440 goto tx_recovery;
4441
4442 if (unlikely(work_done >= budget))
4443 break;
4444
4445 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4446 /* tp->last_tag is used in tg3_restart_ints() below
4447 * to tell the hw how much work has been processed,
4448 * so we must read it before checking for more work.
4449 */
4450 tp->last_tag = sblk->status_tag;
4451 rmb();
4452 } else
4453 sblk->status &= ~SD_STATUS_UPDATED;
4454
4455 if (likely(!tg3_has_work(tp))) {
4456 netif_rx_complete(tp->dev, napi);
4457 tg3_restart_ints(tp);
4458 break;
4459 }
4460 }
4461
4462 return work_done;
4463
4464tx_recovery:
4465 /* work_done is guaranteed to be less than budget. */
4466 netif_rx_complete(tp->dev, napi);
4467 schedule_work(&tp->reset_task);
4468 return work_done;
4469}
4470
4471static void tg3_irq_quiesce(struct tg3 *tp)
4472{
4473 BUG_ON(tp->irq_sync);
4474
4475 tp->irq_sync = 1;
4476 smp_mb();
4477
4478 synchronize_irq(tp->pdev->irq);
4479}
4480
4481static inline int tg3_irq_sync(struct tg3 *tp)
4482{
4483 return tp->irq_sync;
4484}
4485
4486/* Fully shutdown all tg3 driver activity elsewhere in the system.
4487 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4488 * with as well. Most of the time, this is not necessary except when
4489 * shutting down the device.
4490 */
4491static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4492{
4493 spin_lock_bh(&tp->lock);
4494 if (irq_sync)
4495 tg3_irq_quiesce(tp);
4496}
4497
4498static inline void tg3_full_unlock(struct tg3 *tp)
4499{
4500 spin_unlock_bh(&tp->lock);
4501}
4502
4503/* One-shot MSI handler - Chip automatically disables interrupt
4504 * after sending MSI so driver doesn't have to do it.
4505 */
4506static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4507{
4508 struct net_device *dev = dev_id;
4509 struct tg3 *tp = netdev_priv(dev);
4510
4511 prefetch(tp->hw_status);
4512 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4513
4514 if (likely(!tg3_irq_sync(tp)))
4515 netif_rx_schedule(dev, &tp->napi);
4516
4517 return IRQ_HANDLED;
4518}
4519
4520/* MSI ISR - No need to check for interrupt sharing and no need to
4521 * flush status block and interrupt mailbox. PCI ordering rules
4522 * guarantee that MSI will arrive after the status block.
4523 */
4524static irqreturn_t tg3_msi(int irq, void *dev_id)
4525{
4526 struct net_device *dev = dev_id;
4527 struct tg3 *tp = netdev_priv(dev);
4528
4529 prefetch(tp->hw_status);
4530 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4531 /*
4532 * Writing any value to intr-mbox-0 clears PCI INTA# and
4533 * chip-internal interrupt pending events.
4534 * Writing non-zero to intr-mbox-0 additional tells the
4535 * NIC to stop sending us irqs, engaging "in-intr-handler"
4536 * event coalescing.
4537 */
4538 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4539 if (likely(!tg3_irq_sync(tp)))
4540 netif_rx_schedule(dev, &tp->napi);
4541
4542 return IRQ_RETVAL(1);
4543}
4544
4545static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4546{
4547 struct net_device *dev = dev_id;
4548 struct tg3 *tp = netdev_priv(dev);
4549 struct tg3_hw_status *sblk = tp->hw_status;
4550 unsigned int handled = 1;
4551
4552 /* In INTx mode, it is possible for the interrupt to arrive at
4553 * the CPU before the status block posted prior to the interrupt.
4554 * Reading the PCI State register will confirm whether the
4555 * interrupt is ours and will flush the status block.
4556 */
4557 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4558 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4559 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4560 handled = 0;
4561 goto out;
4562 }
4563 }
4564
4565 /*
4566 * Writing any value to intr-mbox-0 clears PCI INTA# and
4567 * chip-internal interrupt pending events.
4568 * Writing non-zero to intr-mbox-0 additional tells the
4569 * NIC to stop sending us irqs, engaging "in-intr-handler"
4570 * event coalescing.
4571 *
4572 * Flush the mailbox to de-assert the IRQ immediately to prevent
4573 * spurious interrupts. The flush impacts performance but
4574 * excessive spurious interrupts can be worse in some cases.
4575 */
4576 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4577 if (tg3_irq_sync(tp))
4578 goto out;
4579 sblk->status &= ~SD_STATUS_UPDATED;
4580 if (likely(tg3_has_work(tp))) {
4581 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4582 netif_rx_schedule(dev, &tp->napi);
4583 } else {
4584 /* No work, shared interrupt perhaps? re-enable
4585 * interrupts, and flush that PCI write
4586 */
4587 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4588 0x00000000);
4589 }
4590out:
4591 return IRQ_RETVAL(handled);
4592}
4593
4594static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4595{
4596 struct net_device *dev = dev_id;
4597 struct tg3 *tp = netdev_priv(dev);
4598 struct tg3_hw_status *sblk = tp->hw_status;
4599 unsigned int handled = 1;
4600
4601 /* In INTx mode, it is possible for the interrupt to arrive at
4602 * the CPU before the status block posted prior to the interrupt.
4603 * Reading the PCI State register will confirm whether the
4604 * interrupt is ours and will flush the status block.
4605 */
4606 if (unlikely(sblk->status_tag == tp->last_tag)) {
4607 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4608 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4609 handled = 0;
4610 goto out;
4611 }
4612 }
4613
4614 /*
4615 * writing any value to intr-mbox-0 clears PCI INTA# and
4616 * chip-internal interrupt pending events.
4617 * writing non-zero to intr-mbox-0 additional tells the
4618 * NIC to stop sending us irqs, engaging "in-intr-handler"
4619 * event coalescing.
4620 *
4621 * Flush the mailbox to de-assert the IRQ immediately to prevent
4622 * spurious interrupts. The flush impacts performance but
4623 * excessive spurious interrupts can be worse in some cases.
4624 */
4625 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4626 if (tg3_irq_sync(tp))
4627 goto out;
4628 if (netif_rx_schedule_prep(dev, &tp->napi)) {
4629 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4630 /* Update last_tag to mark that this status has been
4631 * seen. Because interrupt may be shared, we may be
4632 * racing with tg3_poll(), so only update last_tag
4633 * if tg3_poll() is not scheduled.
4634 */
4635 tp->last_tag = sblk->status_tag;
4636 __netif_rx_schedule(dev, &tp->napi);
4637 }
4638out:
4639 return IRQ_RETVAL(handled);
4640}
4641
4642/* ISR for interrupt test */
4643static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4644{
4645 struct net_device *dev = dev_id;
4646 struct tg3 *tp = netdev_priv(dev);
4647 struct tg3_hw_status *sblk = tp->hw_status;
4648
4649 if ((sblk->status & SD_STATUS_UPDATED) ||
4650 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4651 tg3_disable_ints(tp);
4652 return IRQ_RETVAL(1);
4653 }
4654 return IRQ_RETVAL(0);
4655}
4656
4657static int tg3_init_hw(struct tg3 *, int);
4658static int tg3_halt(struct tg3 *, int, int);
4659
4660/* Restart hardware after configuration changes, self-test, etc.
4661 * Invoked with tp->lock held.
4662 */
4663static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4664 __releases(tp->lock)
4665 __acquires(tp->lock)
4666{
4667 int err;
4668
4669 err = tg3_init_hw(tp, reset_phy);
4670 if (err) {
4671 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4672 "aborting.\n", tp->dev->name);
4673 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4674 tg3_full_unlock(tp);
4675 del_timer_sync(&tp->timer);
4676 tp->irq_sync = 0;
4677 napi_enable(&tp->napi);
4678 dev_close(tp->dev);
4679 tg3_full_lock(tp, 0);
4680 }
4681 return err;
4682}
4683
4684#ifdef CONFIG_NET_POLL_CONTROLLER
4685static void tg3_poll_controller(struct net_device *dev)
4686{
4687 struct tg3 *tp = netdev_priv(dev);
4688
4689 tg3_interrupt(tp->pdev->irq, dev);
4690}
4691#endif
4692
4693static void tg3_reset_task(struct work_struct *work)
4694{
4695 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4696 int err;
4697 unsigned int restart_timer;
4698
4699 tg3_full_lock(tp, 0);
4700
4701 if (!netif_running(tp->dev)) {
4702 tg3_full_unlock(tp);
4703 return;
4704 }
4705
4706 tg3_full_unlock(tp);
4707
4708 tg3_phy_stop(tp);
4709
4710 tg3_netif_stop(tp);
4711
4712 tg3_full_lock(tp, 1);
4713
4714 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4715 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4716
4717 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4718 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4719 tp->write32_rx_mbox = tg3_write_flush_reg32;
4720 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4721 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4722 }
4723
4724 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4725 err = tg3_init_hw(tp, 1);
4726 if (err)
4727 goto out;
4728
4729 tg3_netif_start(tp);
4730
4731 if (restart_timer)
4732 mod_timer(&tp->timer, jiffies + 1);
4733
4734out:
4735 tg3_full_unlock(tp);
4736
4737 if (!err)
4738 tg3_phy_start(tp);
4739}
4740
4741static void tg3_dump_short_state(struct tg3 *tp)
4742{
4743 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4744 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4745 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4746 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4747}
4748
4749static void tg3_tx_timeout(struct net_device *dev)
4750{
4751 struct tg3 *tp = netdev_priv(dev);
4752
4753 if (netif_msg_tx_err(tp)) {
4754 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4755 dev->name);
4756 tg3_dump_short_state(tp);
4757 }
4758
4759 schedule_work(&tp->reset_task);
4760}
4761
4762/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4763static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4764{
4765 u32 base = (u32) mapping & 0xffffffff;
4766
4767 return ((base > 0xffffdcc0) &&
4768 (base + len + 8 < base));
4769}
4770
4771/* Test for DMA addresses > 40-bit */
4772static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4773 int len)
4774{
4775#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4776 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4777 return (((u64) mapping + len) > DMA_40BIT_MASK);
4778 return 0;
4779#else
4780 return 0;
4781#endif
4782}
4783
4784static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4785
4786/* Workaround 4GB and 40-bit hardware DMA bugs. */
4787static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4788 u32 last_plus_one, u32 *start,
4789 u32 base_flags, u32 mss)
4790{
4791 struct sk_buff *new_skb;
4792 dma_addr_t new_addr = 0;
4793 u32 entry = *start;
4794 int i, ret = 0;
4795
4796 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4797 new_skb = skb_copy(skb, GFP_ATOMIC);
4798 else {
4799 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4800
4801 new_skb = skb_copy_expand(skb,
4802 skb_headroom(skb) + more_headroom,
4803 skb_tailroom(skb), GFP_ATOMIC);
4804 }
4805
4806 if (!new_skb) {
4807 ret = -1;
4808 } else {
4809 /* New SKB is guaranteed to be linear. */
4810 entry = *start;
4811 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
4812 new_addr = skb_shinfo(new_skb)->dma_maps[0];
4813
4814 /* Make sure new skb does not cross any 4G boundaries.
4815 * Drop the packet if it does.
4816 */
4817 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
4818 if (!ret)
4819 skb_dma_unmap(&tp->pdev->dev, new_skb,
4820 DMA_TO_DEVICE);
4821 ret = -1;
4822 dev_kfree_skb(new_skb);
4823 new_skb = NULL;
4824 } else {
4825 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4826 base_flags, 1 | (mss << 1));
4827 *start = NEXT_TX(entry);
4828 }
4829 }
4830
4831 /* Now clean up the sw ring entries. */
4832 i = 0;
4833 while (entry != last_plus_one) {
4834 if (i == 0) {
4835 tp->tx_buffers[entry].skb = new_skb;
4836 } else {
4837 tp->tx_buffers[entry].skb = NULL;
4838 }
4839 entry = NEXT_TX(entry);
4840 i++;
4841 }
4842
4843 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4844 dev_kfree_skb(skb);
4845
4846 return ret;
4847}
4848
4849static void tg3_set_txd(struct tg3 *tp, int entry,
4850 dma_addr_t mapping, int len, u32 flags,
4851 u32 mss_and_is_end)
4852{
4853 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4854 int is_end = (mss_and_is_end & 0x1);
4855 u32 mss = (mss_and_is_end >> 1);
4856 u32 vlan_tag = 0;
4857
4858 if (is_end)
4859 flags |= TXD_FLAG_END;
4860 if (flags & TXD_FLAG_VLAN) {
4861 vlan_tag = flags >> 16;
4862 flags &= 0xffff;
4863 }
4864 vlan_tag |= (mss << TXD_MSS_SHIFT);
4865
4866 txd->addr_hi = ((u64) mapping >> 32);
4867 txd->addr_lo = ((u64) mapping & 0xffffffff);
4868 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4869 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4870}
4871
4872/* hard_start_xmit for devices that don't have any bugs and
4873 * support TG3_FLG2_HW_TSO_2 only.
4874 */
4875static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4876{
4877 struct tg3 *tp = netdev_priv(dev);
4878 u32 len, entry, base_flags, mss;
4879 struct skb_shared_info *sp;
4880 dma_addr_t mapping;
4881
4882 len = skb_headlen(skb);
4883
4884 /* We are running in BH disabled context with netif_tx_lock
4885 * and TX reclaim runs via tp->napi.poll inside of a software
4886 * interrupt. Furthermore, IRQ processing runs lockless so we have
4887 * no IRQ context deadlocks to worry about either. Rejoice!
4888 */
4889 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4890 if (!netif_queue_stopped(dev)) {
4891 netif_stop_queue(dev);
4892
4893 /* This is a hard error, log it. */
4894 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4895 "queue awake!\n", dev->name);
4896 }
4897 return NETDEV_TX_BUSY;
4898 }
4899
4900 entry = tp->tx_prod;
4901 base_flags = 0;
4902 mss = 0;
4903 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4904 int tcp_opt_len, ip_tcp_len;
4905
4906 if (skb_header_cloned(skb) &&
4907 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4908 dev_kfree_skb(skb);
4909 goto out_unlock;
4910 }
4911
4912 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4913 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4914 else {
4915 struct iphdr *iph = ip_hdr(skb);
4916
4917 tcp_opt_len = tcp_optlen(skb);
4918 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4919
4920 iph->check = 0;
4921 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4922 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4923 }
4924
4925 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4926 TXD_FLAG_CPU_POST_DMA);
4927
4928 tcp_hdr(skb)->check = 0;
4929
4930 }
4931 else if (skb->ip_summed == CHECKSUM_PARTIAL)
4932 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4933#if TG3_VLAN_TAG_USED
4934 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4935 base_flags |= (TXD_FLAG_VLAN |
4936 (vlan_tx_tag_get(skb) << 16));
4937#endif
4938
4939 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
4940 dev_kfree_skb(skb);
4941 goto out_unlock;
4942 }
4943
4944 sp = skb_shinfo(skb);
4945
4946 mapping = sp->dma_maps[0];
4947
4948 tp->tx_buffers[entry].skb = skb;
4949
4950 tg3_set_txd(tp, entry, mapping, len, base_flags,
4951 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4952
4953 entry = NEXT_TX(entry);
4954
4955 /* Now loop through additional data fragments, and queue them. */
4956 if (skb_shinfo(skb)->nr_frags > 0) {
4957 unsigned int i, last;
4958
4959 last = skb_shinfo(skb)->nr_frags - 1;
4960 for (i = 0; i <= last; i++) {
4961 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4962
4963 len = frag->size;
4964 mapping = sp->dma_maps[i + 1];
4965 tp->tx_buffers[entry].skb = NULL;
4966
4967 tg3_set_txd(tp, entry, mapping, len,
4968 base_flags, (i == last) | (mss << 1));
4969
4970 entry = NEXT_TX(entry);
4971 }
4972 }
4973
4974 /* Packets are ready, update Tx producer idx local and on card. */
4975 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4976
4977 tp->tx_prod = entry;
4978 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4979 netif_stop_queue(dev);
4980 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4981 netif_wake_queue(tp->dev);
4982 }
4983
4984out_unlock:
4985 mmiowb();
4986
4987 dev->trans_start = jiffies;
4988
4989 return NETDEV_TX_OK;
4990}
4991
4992static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4993
4994/* Use GSO to workaround a rare TSO bug that may be triggered when the
4995 * TSO header is greater than 80 bytes.
4996 */
4997static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4998{
4999 struct sk_buff *segs, *nskb;
5000
5001 /* Estimate the number of fragments in the worst case */
5002 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5003 netif_stop_queue(tp->dev);
5004 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5005 return NETDEV_TX_BUSY;
5006
5007 netif_wake_queue(tp->dev);
5008 }
5009
5010 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5011 if (IS_ERR(segs))
5012 goto tg3_tso_bug_end;
5013
5014 do {
5015 nskb = segs;
5016 segs = segs->next;
5017 nskb->next = NULL;
5018 tg3_start_xmit_dma_bug(nskb, tp->dev);
5019 } while (segs);
5020
5021tg3_tso_bug_end:
5022 dev_kfree_skb(skb);
5023
5024 return NETDEV_TX_OK;
5025}
5026
5027/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5028 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5029 */
5030static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5031{
5032 struct tg3 *tp = netdev_priv(dev);
5033 u32 len, entry, base_flags, mss;
5034 struct skb_shared_info *sp;
5035 int would_hit_hwbug;
5036 dma_addr_t mapping;
5037
5038 len = skb_headlen(skb);
5039
5040 /* We are running in BH disabled context with netif_tx_lock
5041 * and TX reclaim runs via tp->napi.poll inside of a software
5042 * interrupt. Furthermore, IRQ processing runs lockless so we have
5043 * no IRQ context deadlocks to worry about either. Rejoice!
5044 */
5045 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5046 if (!netif_queue_stopped(dev)) {
5047 netif_stop_queue(dev);
5048
5049 /* This is a hard error, log it. */
5050 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5051 "queue awake!\n", dev->name);
5052 }
5053 return NETDEV_TX_BUSY;
5054 }
5055
5056 entry = tp->tx_prod;
5057 base_flags = 0;
5058 if (skb->ip_summed == CHECKSUM_PARTIAL)
5059 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5060 mss = 0;
5061 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5062 struct iphdr *iph;
5063 int tcp_opt_len, ip_tcp_len, hdr_len;
5064
5065 if (skb_header_cloned(skb) &&
5066 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5067 dev_kfree_skb(skb);
5068 goto out_unlock;
5069 }
5070
5071 tcp_opt_len = tcp_optlen(skb);
5072 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5073
5074 hdr_len = ip_tcp_len + tcp_opt_len;
5075 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5076 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5077 return (tg3_tso_bug(tp, skb));
5078
5079 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5080 TXD_FLAG_CPU_POST_DMA);
5081
5082 iph = ip_hdr(skb);
5083 iph->check = 0;
5084 iph->tot_len = htons(mss + hdr_len);
5085 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5086 tcp_hdr(skb)->check = 0;
5087 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5088 } else
5089 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5090 iph->daddr, 0,
5091 IPPROTO_TCP,
5092 0);
5093
5094 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5095 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5096 if (tcp_opt_len || iph->ihl > 5) {
5097 int tsflags;
5098
5099 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5100 mss |= (tsflags << 11);
5101 }
5102 } else {
5103 if (tcp_opt_len || iph->ihl > 5) {
5104 int tsflags;
5105
5106 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5107 base_flags |= tsflags << 12;
5108 }
5109 }
5110 }
5111#if TG3_VLAN_TAG_USED
5112 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5113 base_flags |= (TXD_FLAG_VLAN |
5114 (vlan_tx_tag_get(skb) << 16));
5115#endif
5116
5117 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5118 dev_kfree_skb(skb);
5119 goto out_unlock;
5120 }
5121
5122 sp = skb_shinfo(skb);
5123
5124 mapping = sp->dma_maps[0];
5125
5126 tp->tx_buffers[entry].skb = skb;
5127
5128 would_hit_hwbug = 0;
5129
5130 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5131 would_hit_hwbug = 1;
5132 else if (tg3_4g_overflow_test(mapping, len))
5133 would_hit_hwbug = 1;
5134
5135 tg3_set_txd(tp, entry, mapping, len, base_flags,
5136 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5137
5138 entry = NEXT_TX(entry);
5139
5140 /* Now loop through additional data fragments, and queue them. */
5141 if (skb_shinfo(skb)->nr_frags > 0) {
5142 unsigned int i, last;
5143
5144 last = skb_shinfo(skb)->nr_frags - 1;
5145 for (i = 0; i <= last; i++) {
5146 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5147
5148 len = frag->size;
5149 mapping = sp->dma_maps[i + 1];
5150
5151 tp->tx_buffers[entry].skb = NULL;
5152
5153 if (tg3_4g_overflow_test(mapping, len))
5154 would_hit_hwbug = 1;
5155
5156 if (tg3_40bit_overflow_test(tp, mapping, len))
5157 would_hit_hwbug = 1;
5158
5159 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5160 tg3_set_txd(tp, entry, mapping, len,
5161 base_flags, (i == last)|(mss << 1));
5162 else
5163 tg3_set_txd(tp, entry, mapping, len,
5164 base_flags, (i == last));
5165
5166 entry = NEXT_TX(entry);
5167 }
5168 }
5169
5170 if (would_hit_hwbug) {
5171 u32 last_plus_one = entry;
5172 u32 start;
5173
5174 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5175 start &= (TG3_TX_RING_SIZE - 1);
5176
5177 /* If the workaround fails due to memory/mapping
5178 * failure, silently drop this packet.
5179 */
5180 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5181 &start, base_flags, mss))
5182 goto out_unlock;
5183
5184 entry = start;
5185 }
5186
5187 /* Packets are ready, update Tx producer idx local and on card. */
5188 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5189
5190 tp->tx_prod = entry;
5191 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5192 netif_stop_queue(dev);
5193 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5194 netif_wake_queue(tp->dev);
5195 }
5196
5197out_unlock:
5198 mmiowb();
5199
5200 dev->trans_start = jiffies;
5201
5202 return NETDEV_TX_OK;
5203}
5204
5205static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5206 int new_mtu)
5207{
5208 dev->mtu = new_mtu;
5209
5210 if (new_mtu > ETH_DATA_LEN) {
5211 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5212 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5213 ethtool_op_set_tso(dev, 0);
5214 }
5215 else
5216 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5217 } else {
5218 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5219 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5220 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5221 }
5222}
5223
5224static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5225{
5226 struct tg3 *tp = netdev_priv(dev);
5227 int err;
5228
5229 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5230 return -EINVAL;
5231
5232 if (!netif_running(dev)) {
5233 /* We'll just catch it later when the
5234 * device is up'd.
5235 */
5236 tg3_set_mtu(dev, tp, new_mtu);
5237 return 0;
5238 }
5239
5240 tg3_phy_stop(tp);
5241
5242 tg3_netif_stop(tp);
5243
5244 tg3_full_lock(tp, 1);
5245
5246 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5247
5248 tg3_set_mtu(dev, tp, new_mtu);
5249
5250 err = tg3_restart_hw(tp, 0);
5251
5252 if (!err)
5253 tg3_netif_start(tp);
5254
5255 tg3_full_unlock(tp);
5256
5257 if (!err)
5258 tg3_phy_start(tp);
5259
5260 return err;
5261}
5262
5263/* Free up pending packets in all rx/tx rings.
5264 *
5265 * The chip has been shut down and the driver detached from
5266 * the networking, so no interrupts or new tx packets will
5267 * end up in the driver. tp->{tx,}lock is not held and we are not
5268 * in an interrupt context and thus may sleep.
5269 */
5270static void tg3_free_rings(struct tg3 *tp)
5271{
5272 struct ring_info *rxp;
5273 int i;
5274
5275 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5276 rxp = &tp->rx_std_buffers[i];
5277
5278 if (rxp->skb == NULL)
5279 continue;
5280 pci_unmap_single(tp->pdev,
5281 pci_unmap_addr(rxp, mapping),
5282 tp->rx_pkt_buf_sz - tp->rx_offset,
5283 PCI_DMA_FROMDEVICE);
5284 dev_kfree_skb_any(rxp->skb);
5285 rxp->skb = NULL;
5286 }
5287
5288 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5289 rxp = &tp->rx_jumbo_buffers[i];
5290
5291 if (rxp->skb == NULL)
5292 continue;
5293 pci_unmap_single(tp->pdev,
5294 pci_unmap_addr(rxp, mapping),
5295 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5296 PCI_DMA_FROMDEVICE);
5297 dev_kfree_skb_any(rxp->skb);
5298 rxp->skb = NULL;
5299 }
5300
5301 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5302 struct tx_ring_info *txp;
5303 struct sk_buff *skb;
5304
5305 txp = &tp->tx_buffers[i];
5306 skb = txp->skb;
5307
5308 if (skb == NULL) {
5309 i++;
5310 continue;
5311 }
5312
5313 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5314
5315 txp->skb = NULL;
5316
5317 i += skb_shinfo(skb)->nr_frags + 1;
5318
5319 dev_kfree_skb_any(skb);
5320 }
5321}
5322
5323/* Initialize tx/rx rings for packet processing.
5324 *
5325 * The chip has been shut down and the driver detached from
5326 * the networking, so no interrupts or new tx packets will
5327 * end up in the driver. tp->{tx,}lock are held and thus
5328 * we may not sleep.
5329 */
5330static int tg3_init_rings(struct tg3 *tp)
5331{
5332 u32 i;
5333
5334 /* Free up all the SKBs. */
5335 tg3_free_rings(tp);
5336
5337 /* Zero out all descriptors. */
5338 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5339 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5340 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5341 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5342
5343 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5344 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5345 (tp->dev->mtu > ETH_DATA_LEN))
5346 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5347
5348 /* Initialize invariants of the rings, we only set this
5349 * stuff once. This works because the card does not
5350 * write into the rx buffer posting rings.
5351 */
5352 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5353 struct tg3_rx_buffer_desc *rxd;
5354
5355 rxd = &tp->rx_std[i];
5356 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5357 << RXD_LEN_SHIFT;
5358 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5359 rxd->opaque = (RXD_OPAQUE_RING_STD |
5360 (i << RXD_OPAQUE_INDEX_SHIFT));
5361 }
5362
5363 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5364 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5365 struct tg3_rx_buffer_desc *rxd;
5366
5367 rxd = &tp->rx_jumbo[i];
5368 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5369 << RXD_LEN_SHIFT;
5370 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5371 RXD_FLAG_JUMBO;
5372 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5373 (i << RXD_OPAQUE_INDEX_SHIFT));
5374 }
5375 }
5376
5377 /* Now allocate fresh SKBs for each rx ring. */
5378 for (i = 0; i < tp->rx_pending; i++) {
5379 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5380 printk(KERN_WARNING PFX
5381 "%s: Using a smaller RX standard ring, "
5382 "only %d out of %d buffers were allocated "
5383 "successfully.\n",
5384 tp->dev->name, i, tp->rx_pending);
5385 if (i == 0)
5386 return -ENOMEM;
5387 tp->rx_pending = i;
5388 break;
5389 }
5390 }
5391
5392 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5393 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5394 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5395 -1, i) < 0) {
5396 printk(KERN_WARNING PFX
5397 "%s: Using a smaller RX jumbo ring, "
5398 "only %d out of %d buffers were "
5399 "allocated successfully.\n",
5400 tp->dev->name, i, tp->rx_jumbo_pending);
5401 if (i == 0) {
5402 tg3_free_rings(tp);
5403 return -ENOMEM;
5404 }
5405 tp->rx_jumbo_pending = i;
5406 break;
5407 }
5408 }
5409 }
5410 return 0;
5411}
5412
5413/*
5414 * Must not be invoked with interrupt sources disabled and
5415 * the hardware shutdown down.
5416 */
5417static void tg3_free_consistent(struct tg3 *tp)
5418{
5419 kfree(tp->rx_std_buffers);
5420 tp->rx_std_buffers = NULL;
5421 if (tp->rx_std) {
5422 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5423 tp->rx_std, tp->rx_std_mapping);
5424 tp->rx_std = NULL;
5425 }
5426 if (tp->rx_jumbo) {
5427 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5428 tp->rx_jumbo, tp->rx_jumbo_mapping);
5429 tp->rx_jumbo = NULL;
5430 }
5431 if (tp->rx_rcb) {
5432 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5433 tp->rx_rcb, tp->rx_rcb_mapping);
5434 tp->rx_rcb = NULL;
5435 }
5436 if (tp->tx_ring) {
5437 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5438 tp->tx_ring, tp->tx_desc_mapping);
5439 tp->tx_ring = NULL;
5440 }
5441 if (tp->hw_status) {
5442 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5443 tp->hw_status, tp->status_mapping);
5444 tp->hw_status = NULL;
5445 }
5446 if (tp->hw_stats) {
5447 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5448 tp->hw_stats, tp->stats_mapping);
5449 tp->hw_stats = NULL;
5450 }
5451}
5452
5453/*
5454 * Must not be invoked with interrupt sources disabled and
5455 * the hardware shutdown down. Can sleep.
5456 */
5457static int tg3_alloc_consistent(struct tg3 *tp)
5458{
5459 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5460 (TG3_RX_RING_SIZE +
5461 TG3_RX_JUMBO_RING_SIZE)) +
5462 (sizeof(struct tx_ring_info) *
5463 TG3_TX_RING_SIZE),
5464 GFP_KERNEL);
5465 if (!tp->rx_std_buffers)
5466 return -ENOMEM;
5467
5468 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5469 tp->tx_buffers = (struct tx_ring_info *)
5470 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5471
5472 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5473 &tp->rx_std_mapping);
5474 if (!tp->rx_std)
5475 goto err_out;
5476
5477 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5478 &tp->rx_jumbo_mapping);
5479
5480 if (!tp->rx_jumbo)
5481 goto err_out;
5482
5483 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5484 &tp->rx_rcb_mapping);
5485 if (!tp->rx_rcb)
5486 goto err_out;
5487
5488 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5489 &tp->tx_desc_mapping);
5490 if (!tp->tx_ring)
5491 goto err_out;
5492
5493 tp->hw_status = pci_alloc_consistent(tp->pdev,
5494 TG3_HW_STATUS_SIZE,
5495 &tp->status_mapping);
5496 if (!tp->hw_status)
5497 goto err_out;
5498
5499 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5500 sizeof(struct tg3_hw_stats),
5501 &tp->stats_mapping);
5502 if (!tp->hw_stats)
5503 goto err_out;
5504
5505 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5506 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5507
5508 return 0;
5509
5510err_out:
5511 tg3_free_consistent(tp);
5512 return -ENOMEM;
5513}
5514
5515#define MAX_WAIT_CNT 1000
5516
5517/* To stop a block, clear the enable bit and poll till it
5518 * clears. tp->lock is held.
5519 */
5520static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5521{
5522 unsigned int i;
5523 u32 val;
5524
5525 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5526 switch (ofs) {
5527 case RCVLSC_MODE:
5528 case DMAC_MODE:
5529 case MBFREE_MODE:
5530 case BUFMGR_MODE:
5531 case MEMARB_MODE:
5532 /* We can't enable/disable these bits of the
5533 * 5705/5750, just say success.
5534 */
5535 return 0;
5536
5537 default:
5538 break;
5539 }
5540 }
5541
5542 val = tr32(ofs);
5543 val &= ~enable_bit;
5544 tw32_f(ofs, val);
5545
5546 for (i = 0; i < MAX_WAIT_CNT; i++) {
5547 udelay(100);
5548 val = tr32(ofs);
5549 if ((val & enable_bit) == 0)
5550 break;
5551 }
5552
5553 if (i == MAX_WAIT_CNT && !silent) {
5554 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5555 "ofs=%lx enable_bit=%x\n",
5556 ofs, enable_bit);
5557 return -ENODEV;
5558 }
5559
5560 return 0;
5561}
5562
5563/* tp->lock is held. */
5564static int tg3_abort_hw(struct tg3 *tp, int silent)
5565{
5566 int i, err;
5567
5568 tg3_disable_ints(tp);
5569
5570 tp->rx_mode &= ~RX_MODE_ENABLE;
5571 tw32_f(MAC_RX_MODE, tp->rx_mode);
5572 udelay(10);
5573
5574 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5575 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5576 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5577 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5578 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5579 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5580
5581 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5582 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5583 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5584 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5585 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5586 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5587 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5588
5589 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5590 tw32_f(MAC_MODE, tp->mac_mode);
5591 udelay(40);
5592
5593 tp->tx_mode &= ~TX_MODE_ENABLE;
5594 tw32_f(MAC_TX_MODE, tp->tx_mode);
5595
5596 for (i = 0; i < MAX_WAIT_CNT; i++) {
5597 udelay(100);
5598 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5599 break;
5600 }
5601 if (i >= MAX_WAIT_CNT) {
5602 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5603 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5604 tp->dev->name, tr32(MAC_TX_MODE));
5605 err |= -ENODEV;
5606 }
5607
5608 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5609 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5610 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5611
5612 tw32(FTQ_RESET, 0xffffffff);
5613 tw32(FTQ_RESET, 0x00000000);
5614
5615 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5616 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5617
5618 if (tp->hw_status)
5619 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5620 if (tp->hw_stats)
5621 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5622
5623 return err;
5624}
5625
5626/* tp->lock is held. */
5627static int tg3_nvram_lock(struct tg3 *tp)
5628{
5629 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5630 int i;
5631
5632 if (tp->nvram_lock_cnt == 0) {
5633 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5634 for (i = 0; i < 8000; i++) {
5635 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5636 break;
5637 udelay(20);
5638 }
5639 if (i == 8000) {
5640 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5641 return -ENODEV;
5642 }
5643 }
5644 tp->nvram_lock_cnt++;
5645 }
5646 return 0;
5647}
5648
5649/* tp->lock is held. */
5650static void tg3_nvram_unlock(struct tg3 *tp)
5651{
5652 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5653 if (tp->nvram_lock_cnt > 0)
5654 tp->nvram_lock_cnt--;
5655 if (tp->nvram_lock_cnt == 0)
5656 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5657 }
5658}
5659
5660/* tp->lock is held. */
5661static void tg3_enable_nvram_access(struct tg3 *tp)
5662{
5663 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5664 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5665 u32 nvaccess = tr32(NVRAM_ACCESS);
5666
5667 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5668 }
5669}
5670
5671/* tp->lock is held. */
5672static void tg3_disable_nvram_access(struct tg3 *tp)
5673{
5674 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5675 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5676 u32 nvaccess = tr32(NVRAM_ACCESS);
5677
5678 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5679 }
5680}
5681
5682static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5683{
5684 int i;
5685 u32 apedata;
5686
5687 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5688 if (apedata != APE_SEG_SIG_MAGIC)
5689 return;
5690
5691 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5692 if (!(apedata & APE_FW_STATUS_READY))
5693 return;
5694
5695 /* Wait for up to 1 millisecond for APE to service previous event. */
5696 for (i = 0; i < 10; i++) {
5697 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5698 return;
5699
5700 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5701
5702 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5703 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5704 event | APE_EVENT_STATUS_EVENT_PENDING);
5705
5706 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5707
5708 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5709 break;
5710
5711 udelay(100);
5712 }
5713
5714 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5715 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5716}
5717
5718static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5719{
5720 u32 event;
5721 u32 apedata;
5722
5723 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5724 return;
5725
5726 switch (kind) {
5727 case RESET_KIND_INIT:
5728 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5729 APE_HOST_SEG_SIG_MAGIC);
5730 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5731 APE_HOST_SEG_LEN_MAGIC);
5732 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5733 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5734 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5735 APE_HOST_DRIVER_ID_MAGIC);
5736 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5737 APE_HOST_BEHAV_NO_PHYLOCK);
5738
5739 event = APE_EVENT_STATUS_STATE_START;
5740 break;
5741 case RESET_KIND_SHUTDOWN:
5742 /* With the interface we are currently using,
5743 * APE does not track driver state. Wiping
5744 * out the HOST SEGMENT SIGNATURE forces
5745 * the APE to assume OS absent status.
5746 */
5747 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5748
5749 event = APE_EVENT_STATUS_STATE_UNLOAD;
5750 break;
5751 case RESET_KIND_SUSPEND:
5752 event = APE_EVENT_STATUS_STATE_SUSPEND;
5753 break;
5754 default:
5755 return;
5756 }
5757
5758 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5759
5760 tg3_ape_send_event(tp, event);
5761}
5762
5763/* tp->lock is held. */
5764static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5765{
5766 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5767 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5768
5769 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5770 switch (kind) {
5771 case RESET_KIND_INIT:
5772 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5773 DRV_STATE_START);
5774 break;
5775
5776 case RESET_KIND_SHUTDOWN:
5777 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5778 DRV_STATE_UNLOAD);
5779 break;
5780
5781 case RESET_KIND_SUSPEND:
5782 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5783 DRV_STATE_SUSPEND);
5784 break;
5785
5786 default:
5787 break;
5788 }
5789 }
5790
5791 if (kind == RESET_KIND_INIT ||
5792 kind == RESET_KIND_SUSPEND)
5793 tg3_ape_driver_state_change(tp, kind);
5794}
5795
5796/* tp->lock is held. */
5797static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5798{
5799 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5800 switch (kind) {
5801 case RESET_KIND_INIT:
5802 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5803 DRV_STATE_START_DONE);
5804 break;
5805
5806 case RESET_KIND_SHUTDOWN:
5807 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5808 DRV_STATE_UNLOAD_DONE);
5809 break;
5810
5811 default:
5812 break;
5813 }
5814 }
5815
5816 if (kind == RESET_KIND_SHUTDOWN)
5817 tg3_ape_driver_state_change(tp, kind);
5818}
5819
5820/* tp->lock is held. */
5821static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5822{
5823 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5824 switch (kind) {
5825 case RESET_KIND_INIT:
5826 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5827 DRV_STATE_START);
5828 break;
5829
5830 case RESET_KIND_SHUTDOWN:
5831 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5832 DRV_STATE_UNLOAD);
5833 break;
5834
5835 case RESET_KIND_SUSPEND:
5836 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5837 DRV_STATE_SUSPEND);
5838 break;
5839
5840 default:
5841 break;
5842 }
5843 }
5844}
5845
5846static int tg3_poll_fw(struct tg3 *tp)
5847{
5848 int i;
5849 u32 val;
5850
5851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5852 /* Wait up to 20ms for init done. */
5853 for (i = 0; i < 200; i++) {
5854 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5855 return 0;
5856 udelay(100);
5857 }
5858 return -ENODEV;
5859 }
5860
5861 /* Wait for firmware initialization to complete. */
5862 for (i = 0; i < 100000; i++) {
5863 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5864 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5865 break;
5866 udelay(10);
5867 }
5868
5869 /* Chip might not be fitted with firmware. Some Sun onboard
5870 * parts are configured like that. So don't signal the timeout
5871 * of the above loop as an error, but do report the lack of
5872 * running firmware once.
5873 */
5874 if (i >= 100000 &&
5875 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5876 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5877
5878 printk(KERN_INFO PFX "%s: No firmware running.\n",
5879 tp->dev->name);
5880 }
5881
5882 return 0;
5883}
5884
5885/* Save PCI command register before chip reset */
5886static void tg3_save_pci_state(struct tg3 *tp)
5887{
5888 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5889}
5890
5891/* Restore PCI state after chip reset */
5892static void tg3_restore_pci_state(struct tg3 *tp)
5893{
5894 u32 val;
5895
5896 /* Re-enable indirect register accesses. */
5897 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5898 tp->misc_host_ctrl);
5899
5900 /* Set MAX PCI retry to zero. */
5901 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5902 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5903 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5904 val |= PCISTATE_RETRY_SAME_DMA;
5905 /* Allow reads and writes to the APE register and memory space. */
5906 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5907 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5908 PCISTATE_ALLOW_APE_SHMEM_WR;
5909 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5910
5911 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5912
5913 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
5914 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5915 pcie_set_readrq(tp->pdev, 4096);
5916 else {
5917 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5918 tp->pci_cacheline_sz);
5919 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5920 tp->pci_lat_timer);
5921 }
5922 }
5923
5924 /* Make sure PCI-X relaxed ordering bit is clear. */
5925 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
5926 u16 pcix_cmd;
5927
5928 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5929 &pcix_cmd);
5930 pcix_cmd &= ~PCI_X_CMD_ERO;
5931 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5932 pcix_cmd);
5933 }
5934
5935 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5936
5937 /* Chip reset on 5780 will reset MSI enable bit,
5938 * so need to restore it.
5939 */
5940 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5941 u16 ctrl;
5942
5943 pci_read_config_word(tp->pdev,
5944 tp->msi_cap + PCI_MSI_FLAGS,
5945 &ctrl);
5946 pci_write_config_word(tp->pdev,
5947 tp->msi_cap + PCI_MSI_FLAGS,
5948 ctrl | PCI_MSI_FLAGS_ENABLE);
5949 val = tr32(MSGINT_MODE);
5950 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5951 }
5952 }
5953}
5954
5955static void tg3_stop_fw(struct tg3 *);
5956
5957/* tp->lock is held. */
5958static int tg3_chip_reset(struct tg3 *tp)
5959{
5960 u32 val;
5961 void (*write_op)(struct tg3 *, u32, u32);
5962 int err;
5963
5964 tg3_nvram_lock(tp);
5965
5966 tg3_mdio_stop(tp);
5967
5968 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
5969
5970 /* No matching tg3_nvram_unlock() after this because
5971 * chip reset below will undo the nvram lock.
5972 */
5973 tp->nvram_lock_cnt = 0;
5974
5975 /* GRC_MISC_CFG core clock reset will clear the memory
5976 * enable bit in PCI register 4 and the MSI enable bit
5977 * on some chips, so we save relevant registers here.
5978 */
5979 tg3_save_pci_state(tp);
5980
5981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5982 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
5983 tw32(GRC_FASTBOOT_PC, 0);
5984
5985 /*
5986 * We must avoid the readl() that normally takes place.
5987 * It locks machines, causes machine checks, and other
5988 * fun things. So, temporarily disable the 5701
5989 * hardware workaround, while we do the reset.
5990 */
5991 write_op = tp->write32;
5992 if (write_op == tg3_write_flush_reg32)
5993 tp->write32 = tg3_write32;
5994
5995 /* Prevent the irq handler from reading or writing PCI registers
5996 * during chip reset when the memory enable bit in the PCI command
5997 * register may be cleared. The chip does not generate interrupt
5998 * at this time, but the irq handler may still be called due to irq
5999 * sharing or irqpoll.
6000 */
6001 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6002 if (tp->hw_status) {
6003 tp->hw_status->status = 0;
6004 tp->hw_status->status_tag = 0;
6005 }
6006 tp->last_tag = 0;
6007 smp_mb();
6008 synchronize_irq(tp->pdev->irq);
6009
6010 /* do the reset */
6011 val = GRC_MISC_CFG_CORECLK_RESET;
6012
6013 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6014 if (tr32(0x7e2c) == 0x60) {
6015 tw32(0x7e2c, 0x20);
6016 }
6017 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6018 tw32(GRC_MISC_CFG, (1 << 29));
6019 val |= (1 << 29);
6020 }
6021 }
6022
6023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6024 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6025 tw32(GRC_VCPU_EXT_CTRL,
6026 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6027 }
6028
6029 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6030 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6031 tw32(GRC_MISC_CFG, val);
6032
6033 /* restore 5701 hardware bug workaround write method */
6034 tp->write32 = write_op;
6035
6036 /* Unfortunately, we have to delay before the PCI read back.
6037 * Some 575X chips even will not respond to a PCI cfg access
6038 * when the reset command is given to the chip.
6039 *
6040 * How do these hardware designers expect things to work
6041 * properly if the PCI write is posted for a long period
6042 * of time? It is always necessary to have some method by
6043 * which a register read back can occur to push the write
6044 * out which does the reset.
6045 *
6046 * For most tg3 variants the trick below was working.
6047 * Ho hum...
6048 */
6049 udelay(120);
6050
6051 /* Flush PCI posted writes. The normal MMIO registers
6052 * are inaccessible at this time so this is the only
6053 * way to make this reliably (actually, this is no longer
6054 * the case, see above). I tried to use indirect
6055 * register read/write but this upset some 5701 variants.
6056 */
6057 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6058
6059 udelay(120);
6060
6061 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6062 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6063 int i;
6064 u32 cfg_val;
6065
6066 /* Wait for link training to complete. */
6067 for (i = 0; i < 5000; i++)
6068 udelay(100);
6069
6070 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6071 pci_write_config_dword(tp->pdev, 0xc4,
6072 cfg_val | (1 << 15));
6073 }
6074
6075 /* Set PCIE max payload size to 128 bytes and
6076 * clear the "no snoop" and "relaxed ordering" bits.
6077 */
6078 pci_write_config_word(tp->pdev,
6079 tp->pcie_cap + PCI_EXP_DEVCTL,
6080 0);
6081
6082 pcie_set_readrq(tp->pdev, 4096);
6083
6084 /* Clear error status */
6085 pci_write_config_word(tp->pdev,
6086 tp->pcie_cap + PCI_EXP_DEVSTA,
6087 PCI_EXP_DEVSTA_CED |
6088 PCI_EXP_DEVSTA_NFED |
6089 PCI_EXP_DEVSTA_FED |
6090 PCI_EXP_DEVSTA_URD);
6091 }
6092
6093 tg3_restore_pci_state(tp);
6094
6095 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6096
6097 val = 0;
6098 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6099 val = tr32(MEMARB_MODE);
6100 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6101
6102 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6103 tg3_stop_fw(tp);
6104 tw32(0x5000, 0x400);
6105 }
6106
6107 tw32(GRC_MODE, tp->grc_mode);
6108
6109 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6110 val = tr32(0xc4);
6111
6112 tw32(0xc4, val | (1 << 15));
6113 }
6114
6115 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6116 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6117 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6118 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6119 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6120 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6121 }
6122
6123 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6124 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6125 tw32_f(MAC_MODE, tp->mac_mode);
6126 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6127 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6128 tw32_f(MAC_MODE, tp->mac_mode);
6129 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6130 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6131 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6132 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6133 tw32_f(MAC_MODE, tp->mac_mode);
6134 } else
6135 tw32_f(MAC_MODE, 0);
6136 udelay(40);
6137
6138 tg3_mdio_start(tp);
6139
6140 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6141
6142 err = tg3_poll_fw(tp);
6143 if (err)
6144 return err;
6145
6146 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6147 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6148 val = tr32(0x7c00);
6149
6150 tw32(0x7c00, val | (1 << 25));
6151 }
6152
6153 /* Reprobe ASF enable state. */
6154 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6155 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6156 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6157 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6158 u32 nic_cfg;
6159
6160 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6161 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6162 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6163 tp->last_event_jiffies = jiffies;
6164 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6165 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6166 }
6167 }
6168
6169 return 0;
6170}
6171
6172/* tp->lock is held. */
6173static void tg3_stop_fw(struct tg3 *tp)
6174{
6175 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6176 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6177 /* Wait for RX cpu to ACK the previous event. */
6178 tg3_wait_for_event_ack(tp);
6179
6180 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6181
6182 tg3_generate_fw_event(tp);
6183
6184 /* Wait for RX cpu to ACK this event. */
6185 tg3_wait_for_event_ack(tp);
6186 }
6187}
6188
6189/* tp->lock is held. */
6190static int tg3_halt(struct tg3 *tp, int kind, int silent)
6191{
6192 int err;
6193
6194 tg3_stop_fw(tp);
6195
6196 tg3_write_sig_pre_reset(tp, kind);
6197
6198 tg3_abort_hw(tp, silent);
6199 err = tg3_chip_reset(tp);
6200
6201 tg3_write_sig_legacy(tp, kind);
6202 tg3_write_sig_post_reset(tp, kind);
6203
6204 if (err)
6205 return err;
6206
6207 return 0;
6208}
6209
6210#define TG3_FW_RELEASE_MAJOR 0x0
6211#define TG3_FW_RELASE_MINOR 0x0
6212#define TG3_FW_RELEASE_FIX 0x0
6213#define TG3_FW_START_ADDR 0x08000000
6214#define TG3_FW_TEXT_ADDR 0x08000000
6215#define TG3_FW_TEXT_LEN 0x9c0
6216#define TG3_FW_RODATA_ADDR 0x080009c0
6217#define TG3_FW_RODATA_LEN 0x60
6218#define TG3_FW_DATA_ADDR 0x08000a40
6219#define TG3_FW_DATA_LEN 0x20
6220#define TG3_FW_SBSS_ADDR 0x08000a60
6221#define TG3_FW_SBSS_LEN 0xc
6222#define TG3_FW_BSS_ADDR 0x08000a70
6223#define TG3_FW_BSS_LEN 0x10
6224
6225static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
6226 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
6227 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
6228 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
6229 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
6230 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
6231 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
6232 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
6233 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
6234 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
6235 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
6236 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
6237 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
6238 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
6239 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
6240 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
6241 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6242 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
6243 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
6244 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
6245 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6246 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
6247 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
6248 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6250 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6251 0, 0, 0, 0, 0, 0,
6252 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
6253 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6254 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6255 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6256 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
6257 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
6258 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
6259 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
6260 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6261 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6262 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
6263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6266 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
6267 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
6268 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
6269 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
6270 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
6271 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
6272 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
6273 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
6274 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
6275 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
6276 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
6277 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
6278 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
6279 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
6280 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
6281 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
6282 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
6283 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
6284 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
6285 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
6286 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
6287 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
6288 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
6289 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
6290 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
6291 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
6292 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
6293 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
6294 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
6295 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
6296 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
6297 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
6298 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
6299 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
6300 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
6301 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
6302 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
6303 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
6304 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
6305 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
6306 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
6307 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
6308 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
6309 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
6310 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
6311 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
6312 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
6313 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
6314 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
6315 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
6316 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
6317};
6318
6319static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
6320 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
6321 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
6322 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6323 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
6324 0x00000000
6325};
6326
6327#if 0 /* All zeros, don't eat up space with it. */
6328u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
6329 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6330 0x00000000, 0x00000000, 0x00000000, 0x00000000
6331};
6332#endif
6333
6334#define RX_CPU_SCRATCH_BASE 0x30000
6335#define RX_CPU_SCRATCH_SIZE 0x04000
6336#define TX_CPU_SCRATCH_BASE 0x34000
6337#define TX_CPU_SCRATCH_SIZE 0x04000
6338
6339/* tp->lock is held. */
6340static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6341{
6342 int i;
6343
6344 BUG_ON(offset == TX_CPU_BASE &&
6345 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6346
6347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6348 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6349
6350 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6351 return 0;
6352 }
6353 if (offset == RX_CPU_BASE) {
6354 for (i = 0; i < 10000; i++) {
6355 tw32(offset + CPU_STATE, 0xffffffff);
6356 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6357 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6358 break;
6359 }
6360
6361 tw32(offset + CPU_STATE, 0xffffffff);
6362 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6363 udelay(10);
6364 } else {
6365 for (i = 0; i < 10000; i++) {
6366 tw32(offset + CPU_STATE, 0xffffffff);
6367 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6368 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6369 break;
6370 }
6371 }
6372
6373 if (i >= 10000) {
6374 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6375 "and %s CPU\n",
6376 tp->dev->name,
6377 (offset == RX_CPU_BASE ? "RX" : "TX"));
6378 return -ENODEV;
6379 }
6380
6381 /* Clear firmware's nvram arbitration. */
6382 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6383 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6384 return 0;
6385}
6386
6387struct fw_info {
6388 unsigned int text_base;
6389 unsigned int text_len;
6390 const u32 *text_data;
6391 unsigned int rodata_base;
6392 unsigned int rodata_len;
6393 const u32 *rodata_data;
6394 unsigned int data_base;
6395 unsigned int data_len;
6396 const u32 *data_data;
6397};
6398
6399/* tp->lock is held. */
6400static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6401 int cpu_scratch_size, struct fw_info *info)
6402{
6403 int err, lock_err, i;
6404 void (*write_op)(struct tg3 *, u32, u32);
6405
6406 if (cpu_base == TX_CPU_BASE &&
6407 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6408 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6409 "TX cpu firmware on %s which is 5705.\n",
6410 tp->dev->name);
6411 return -EINVAL;
6412 }
6413
6414 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6415 write_op = tg3_write_mem;
6416 else
6417 write_op = tg3_write_indirect_reg32;
6418
6419 /* It is possible that bootcode is still loading at this point.
6420 * Get the nvram lock first before halting the cpu.
6421 */
6422 lock_err = tg3_nvram_lock(tp);
6423 err = tg3_halt_cpu(tp, cpu_base);
6424 if (!lock_err)
6425 tg3_nvram_unlock(tp);
6426 if (err)
6427 goto out;
6428
6429 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6430 write_op(tp, cpu_scratch_base + i, 0);
6431 tw32(cpu_base + CPU_STATE, 0xffffffff);
6432 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6433 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
6434 write_op(tp, (cpu_scratch_base +
6435 (info->text_base & 0xffff) +
6436 (i * sizeof(u32))),
6437 (info->text_data ?
6438 info->text_data[i] : 0));
6439 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
6440 write_op(tp, (cpu_scratch_base +
6441 (info->rodata_base & 0xffff) +
6442 (i * sizeof(u32))),
6443 (info->rodata_data ?
6444 info->rodata_data[i] : 0));
6445 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
6446 write_op(tp, (cpu_scratch_base +
6447 (info->data_base & 0xffff) +
6448 (i * sizeof(u32))),
6449 (info->data_data ?
6450 info->data_data[i] : 0));
6451
6452 err = 0;
6453
6454out:
6455 return err;
6456}
6457
6458/* tp->lock is held. */
6459static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6460{
6461 struct fw_info info;
6462 int err, i;
6463
6464 info.text_base = TG3_FW_TEXT_ADDR;
6465 info.text_len = TG3_FW_TEXT_LEN;
6466 info.text_data = &tg3FwText[0];
6467 info.rodata_base = TG3_FW_RODATA_ADDR;
6468 info.rodata_len = TG3_FW_RODATA_LEN;
6469 info.rodata_data = &tg3FwRodata[0];
6470 info.data_base = TG3_FW_DATA_ADDR;
6471 info.data_len = TG3_FW_DATA_LEN;
6472 info.data_data = NULL;
6473
6474 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6475 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6476 &info);
6477 if (err)
6478 return err;
6479
6480 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6481 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6482 &info);
6483 if (err)
6484 return err;
6485
6486 /* Now startup only the RX cpu. */
6487 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6488 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
6489
6490 for (i = 0; i < 5; i++) {
6491 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
6492 break;
6493 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6494 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6495 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
6496 udelay(1000);
6497 }
6498 if (i >= 5) {
6499 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6500 "to set RX CPU PC, is %08x should be %08x\n",
6501 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6502 TG3_FW_TEXT_ADDR);
6503 return -ENODEV;
6504 }
6505 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6506 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6507
6508 return 0;
6509}
6510
6511
6512#define TG3_TSO_FW_RELEASE_MAJOR 0x1
6513#define TG3_TSO_FW_RELASE_MINOR 0x6
6514#define TG3_TSO_FW_RELEASE_FIX 0x0
6515#define TG3_TSO_FW_START_ADDR 0x08000000
6516#define TG3_TSO_FW_TEXT_ADDR 0x08000000
6517#define TG3_TSO_FW_TEXT_LEN 0x1aa0
6518#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
6519#define TG3_TSO_FW_RODATA_LEN 0x60
6520#define TG3_TSO_FW_DATA_ADDR 0x08001b20
6521#define TG3_TSO_FW_DATA_LEN 0x30
6522#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
6523#define TG3_TSO_FW_SBSS_LEN 0x2c
6524#define TG3_TSO_FW_BSS_ADDR 0x08001b80
6525#define TG3_TSO_FW_BSS_LEN 0x894
6526
6527static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
6528 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
6529 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
6530 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6531 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
6532 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
6533 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
6534 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
6535 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
6536 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
6537 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
6538 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
6539 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
6540 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
6541 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
6542 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
6543 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
6544 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
6545 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
6546 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6547 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
6548 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
6549 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
6550 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
6551 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
6552 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
6553 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
6554 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
6555 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
6556 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
6557 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6558 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
6559 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
6560 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
6561 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
6562 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
6563 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
6564 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
6565 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
6566 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6567 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
6568 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
6569 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
6570 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
6571 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
6572 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
6573 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
6574 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
6575 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6576 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
6577 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6578 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
6579 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
6580 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
6581 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
6582 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
6583 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
6584 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
6585 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
6586 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
6587 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
6588 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
6589 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
6590 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
6591 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
6592 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
6593 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
6594 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
6595 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
6596 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
6597 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
6598 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
6599 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
6600 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
6601 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
6602 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
6603 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
6604 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
6605 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
6606 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
6607 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6608 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6609 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6610 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6611 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6612 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6613 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6614 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6615 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6616 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6617 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6618 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6619 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6620 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6621 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6622 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6623 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6624 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6625 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6626 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6627 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6628 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6629 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6630 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6631 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6632 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6633 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6634 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6635 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6636 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6637 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6638 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6639 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6640 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6641 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6642 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6643 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6644 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6645 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6646 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6647 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6648 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6649 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6650 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6651 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6652 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6653 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6654 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6655 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6656 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6657 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6658 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6659 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6660 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6661 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6662 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6663 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6664 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6665 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6666 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6667 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6668 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6669 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6670 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6671 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6672 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6673 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6674 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6675 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6676 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6677 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6678 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6679 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6680 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6681 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6682 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6683 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6684 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6685 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6686 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6687 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6688 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6689 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6690 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6691 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6692 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6693 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6694 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6695 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6696 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6697 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6698 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6699 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6700 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6701 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6702 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6703 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6704 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6705 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6706 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6707 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6708 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6709 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6710 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6711 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6712 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6713 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6714 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6715 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6716 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6717 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6718 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6719 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6720 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6721 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6722 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6723 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6724 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6725 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6726 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6727 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6728 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6729 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6730 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6731 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6732 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6733 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6734 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6735 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6736 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6737 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6738 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6739 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6740 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6741 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6742 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6743 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6744 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6745 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6746 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6747 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6748 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6749 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6750 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6751 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6752 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6753 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6754 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6755 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6756 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6757 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6758 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6759 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6760 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6761 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6762 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6763 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6764 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6765 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6766 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6767 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6768 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6769 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6770 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6771 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6772 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6773 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6774 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6775 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6776 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6777 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6778 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6779 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6780 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6781 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6782 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6783 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6784 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6785 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6786 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6787 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6788 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6789 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6790 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6791 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6792 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6793 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6794 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6795 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6796 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6797 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6798 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6799 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6800 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6801 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6802 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6803 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6804 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6805 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6806 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6807 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6808 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6809 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6810 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6811 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6812};
6813
6814static const u32 tg3TsoFwRodata[] = {
6815 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6816 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6817 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6818 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6819 0x00000000,
6820};
6821
6822static const u32 tg3TsoFwData[] = {
6823 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6824 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6825 0x00000000,
6826};
6827
6828/* 5705 needs a special version of the TSO firmware. */
6829#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
6830#define TG3_TSO5_FW_RELASE_MINOR 0x2
6831#define TG3_TSO5_FW_RELEASE_FIX 0x0
6832#define TG3_TSO5_FW_START_ADDR 0x00010000
6833#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
6834#define TG3_TSO5_FW_TEXT_LEN 0xe90
6835#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
6836#define TG3_TSO5_FW_RODATA_LEN 0x50
6837#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
6838#define TG3_TSO5_FW_DATA_LEN 0x20
6839#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
6840#define TG3_TSO5_FW_SBSS_LEN 0x28
6841#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
6842#define TG3_TSO5_FW_BSS_LEN 0x88
6843
6844static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6845 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6846 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6847 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6848 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6849 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6850 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6851 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6852 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6853 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6854 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6855 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6856 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6857 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6858 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6859 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6860 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6861 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6862 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6863 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6864 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6865 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6866 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6867 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6868 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6869 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6870 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6871 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6872 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6873 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6874 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6875 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6876 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6877 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6878 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6879 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6880 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6881 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6882 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6883 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6884 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6885 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6886 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6887 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6888 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6889 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6890 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6891 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6892 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6893 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6894 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6895 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6896 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6897 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6898 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6899 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6900 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6901 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6902 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6903 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6904 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6905 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6906 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6907 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6908 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6909 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6910 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6911 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6912 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6913 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6914 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6915 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6916 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6917 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6918 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6919 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6920 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6921 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6922 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6923 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6924 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6925 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6926 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6927 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6928 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6929 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6930 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6931 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6932 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6933 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6934 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6935 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6936 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6937 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6938 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6939 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6940 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6941 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6942 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6943 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6944 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6945 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6946 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6947 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6948 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6949 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6950 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6951 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6952 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6953 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6954 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6955 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6956 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6957 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6958 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6959 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6960 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6961 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6962 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6963 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6964 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6965 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6966 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6967 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6968 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6969 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6970 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6971 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6972 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6973 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6974 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6975 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6976 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6977 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6978 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6979 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6980 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6981 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6982 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6983 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6984 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6985 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6986 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6987 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6988 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6989 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6990 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6991 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6992 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6993 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6994 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6995 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6996 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6997 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6998 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6999 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
7000 0x00000000, 0x00000000, 0x00000000,
7001};
7002
7003static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
7004 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
7005 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
7006 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
7007 0x00000000, 0x00000000, 0x00000000,
7008};
7009
7010static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
7011 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
7012 0x00000000, 0x00000000, 0x00000000,
7013};
7014
7015/* tp->lock is held. */
7016static int tg3_load_tso_firmware(struct tg3 *tp)
7017{
7018 struct fw_info info;
7019 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7020 int err, i;
7021
7022 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7023 return 0;
7024
7025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7026 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
7027 info.text_len = TG3_TSO5_FW_TEXT_LEN;
7028 info.text_data = &tg3Tso5FwText[0];
7029 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
7030 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
7031 info.rodata_data = &tg3Tso5FwRodata[0];
7032 info.data_base = TG3_TSO5_FW_DATA_ADDR;
7033 info.data_len = TG3_TSO5_FW_DATA_LEN;
7034 info.data_data = &tg3Tso5FwData[0];
7035 cpu_base = RX_CPU_BASE;
7036 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7037 cpu_scratch_size = (info.text_len +
7038 info.rodata_len +
7039 info.data_len +
7040 TG3_TSO5_FW_SBSS_LEN +
7041 TG3_TSO5_FW_BSS_LEN);
7042 } else {
7043 info.text_base = TG3_TSO_FW_TEXT_ADDR;
7044 info.text_len = TG3_TSO_FW_TEXT_LEN;
7045 info.text_data = &tg3TsoFwText[0];
7046 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
7047 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
7048 info.rodata_data = &tg3TsoFwRodata[0];
7049 info.data_base = TG3_TSO_FW_DATA_ADDR;
7050 info.data_len = TG3_TSO_FW_DATA_LEN;
7051 info.data_data = &tg3TsoFwData[0];
7052 cpu_base = TX_CPU_BASE;
7053 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7054 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7055 }
7056
7057 err = tg3_load_firmware_cpu(tp, cpu_base,
7058 cpu_scratch_base, cpu_scratch_size,
7059 &info);
7060 if (err)
7061 return err;
7062
7063 /* Now startup the cpu. */
7064 tw32(cpu_base + CPU_STATE, 0xffffffff);
7065 tw32_f(cpu_base + CPU_PC, info.text_base);
7066
7067 for (i = 0; i < 5; i++) {
7068 if (tr32(cpu_base + CPU_PC) == info.text_base)
7069 break;
7070 tw32(cpu_base + CPU_STATE, 0xffffffff);
7071 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7072 tw32_f(cpu_base + CPU_PC, info.text_base);
7073 udelay(1000);
7074 }
7075 if (i >= 5) {
7076 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7077 "to set CPU PC, is %08x should be %08x\n",
7078 tp->dev->name, tr32(cpu_base + CPU_PC),
7079 info.text_base);
7080 return -ENODEV;
7081 }
7082 tw32(cpu_base + CPU_STATE, 0xffffffff);
7083 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7084 return 0;
7085}
7086
7087
7088static int tg3_set_mac_addr(struct net_device *dev, void *p)
7089{
7090 struct tg3 *tp = netdev_priv(dev);
7091 struct sockaddr *addr = p;
7092 int err = 0, skip_mac_1 = 0;
7093
7094 if (!is_valid_ether_addr(addr->sa_data))
7095 return -EINVAL;
7096
7097 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7098
7099 if (!netif_running(dev))
7100 return 0;
7101
7102 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7103 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7104
7105 addr0_high = tr32(MAC_ADDR_0_HIGH);
7106 addr0_low = tr32(MAC_ADDR_0_LOW);
7107 addr1_high = tr32(MAC_ADDR_1_HIGH);
7108 addr1_low = tr32(MAC_ADDR_1_LOW);
7109
7110 /* Skip MAC addr 1 if ASF is using it. */
7111 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7112 !(addr1_high == 0 && addr1_low == 0))
7113 skip_mac_1 = 1;
7114 }
7115 spin_lock_bh(&tp->lock);
7116 __tg3_set_mac_addr(tp, skip_mac_1);
7117 spin_unlock_bh(&tp->lock);
7118
7119 return err;
7120}
7121
7122/* tp->lock is held. */
7123static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7124 dma_addr_t mapping, u32 maxlen_flags,
7125 u32 nic_addr)
7126{
7127 tg3_write_mem(tp,
7128 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7129 ((u64) mapping >> 32));
7130 tg3_write_mem(tp,
7131 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7132 ((u64) mapping & 0xffffffff));
7133 tg3_write_mem(tp,
7134 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7135 maxlen_flags);
7136
7137 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7138 tg3_write_mem(tp,
7139 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7140 nic_addr);
7141}
7142
7143static void __tg3_set_rx_mode(struct net_device *);
7144static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7145{
7146 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7147 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7148 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7149 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7150 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7151 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7152 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7153 }
7154 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7155 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7156 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7157 u32 val = ec->stats_block_coalesce_usecs;
7158
7159 if (!netif_carrier_ok(tp->dev))
7160 val = 0;
7161
7162 tw32(HOSTCC_STAT_COAL_TICKS, val);
7163 }
7164}
7165
7166/* tp->lock is held. */
7167static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7168{
7169 u32 val, rdmac_mode;
7170 int i, err, limit;
7171
7172 tg3_disable_ints(tp);
7173
7174 tg3_stop_fw(tp);
7175
7176 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7177
7178 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7179 tg3_abort_hw(tp, 1);
7180 }
7181
7182 if (reset_phy &&
7183 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7184 tg3_phy_reset(tp);
7185
7186 err = tg3_chip_reset(tp);
7187 if (err)
7188 return err;
7189
7190 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7191
7192 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7193 val = tr32(TG3_CPMU_CTRL);
7194 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7195 tw32(TG3_CPMU_CTRL, val);
7196
7197 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7198 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7199 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7200 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7201
7202 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7203 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7204 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7205 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7206
7207 val = tr32(TG3_CPMU_HST_ACC);
7208 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7209 val |= CPMU_HST_ACC_MACCLK_6_25;
7210 tw32(TG3_CPMU_HST_ACC, val);
7211 }
7212
7213 /* This works around an issue with Athlon chipsets on
7214 * B3 tigon3 silicon. This bit has no effect on any
7215 * other revision. But do not set this on PCI Express
7216 * chips and don't even touch the clocks if the CPMU is present.
7217 */
7218 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7219 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7220 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7221 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7222 }
7223
7224 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7225 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7226 val = tr32(TG3PCI_PCISTATE);
7227 val |= PCISTATE_RETRY_SAME_DMA;
7228 tw32(TG3PCI_PCISTATE, val);
7229 }
7230
7231 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7232 /* Allow reads and writes to the
7233 * APE register and memory space.
7234 */
7235 val = tr32(TG3PCI_PCISTATE);
7236 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7237 PCISTATE_ALLOW_APE_SHMEM_WR;
7238 tw32(TG3PCI_PCISTATE, val);
7239 }
7240
7241 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7242 /* Enable some hw fixes. */
7243 val = tr32(TG3PCI_MSI_DATA);
7244 val |= (1 << 26) | (1 << 28) | (1 << 29);
7245 tw32(TG3PCI_MSI_DATA, val);
7246 }
7247
7248 /* Descriptor ring init may make accesses to the
7249 * NIC SRAM area to setup the TX descriptors, so we
7250 * can only do this after the hardware has been
7251 * successfully reset.
7252 */
7253 err = tg3_init_rings(tp);
7254 if (err)
7255 return err;
7256
7257 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7258 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7259 /* This value is determined during the probe time DMA
7260 * engine test, tg3_test_dma.
7261 */
7262 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7263 }
7264
7265 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7266 GRC_MODE_4X_NIC_SEND_RINGS |
7267 GRC_MODE_NO_TX_PHDR_CSUM |
7268 GRC_MODE_NO_RX_PHDR_CSUM);
7269 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7270
7271 /* Pseudo-header checksum is done by hardware logic and not
7272 * the offload processers, so make the chip do the pseudo-
7273 * header checksums on receive. For transmit it is more
7274 * convenient to do the pseudo-header checksum in software
7275 * as Linux does that on transmit for us in all cases.
7276 */
7277 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7278
7279 tw32(GRC_MODE,
7280 tp->grc_mode |
7281 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7282
7283 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7284 val = tr32(GRC_MISC_CFG);
7285 val &= ~0xff;
7286 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7287 tw32(GRC_MISC_CFG, val);
7288
7289 /* Initialize MBUF/DESC pool. */
7290 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7291 /* Do nothing. */
7292 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7293 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7294 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7295 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7296 else
7297 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7298 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7299 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7300 }
7301 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7302 int fw_len;
7303
7304 fw_len = (TG3_TSO5_FW_TEXT_LEN +
7305 TG3_TSO5_FW_RODATA_LEN +
7306 TG3_TSO5_FW_DATA_LEN +
7307 TG3_TSO5_FW_SBSS_LEN +
7308 TG3_TSO5_FW_BSS_LEN);
7309 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7310 tw32(BUFMGR_MB_POOL_ADDR,
7311 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7312 tw32(BUFMGR_MB_POOL_SIZE,
7313 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7314 }
7315
7316 if (tp->dev->mtu <= ETH_DATA_LEN) {
7317 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7318 tp->bufmgr_config.mbuf_read_dma_low_water);
7319 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7320 tp->bufmgr_config.mbuf_mac_rx_low_water);
7321 tw32(BUFMGR_MB_HIGH_WATER,
7322 tp->bufmgr_config.mbuf_high_water);
7323 } else {
7324 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7325 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7326 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7327 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7328 tw32(BUFMGR_MB_HIGH_WATER,
7329 tp->bufmgr_config.mbuf_high_water_jumbo);
7330 }
7331 tw32(BUFMGR_DMA_LOW_WATER,
7332 tp->bufmgr_config.dma_low_water);
7333 tw32(BUFMGR_DMA_HIGH_WATER,
7334 tp->bufmgr_config.dma_high_water);
7335
7336 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7337 for (i = 0; i < 2000; i++) {
7338 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7339 break;
7340 udelay(10);
7341 }
7342 if (i >= 2000) {
7343 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7344 tp->dev->name);
7345 return -ENODEV;
7346 }
7347
7348 /* Setup replenish threshold. */
7349 val = tp->rx_pending / 8;
7350 if (val == 0)
7351 val = 1;
7352 else if (val > tp->rx_std_max_post)
7353 val = tp->rx_std_max_post;
7354 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7355 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7356 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7357
7358 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7359 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7360 }
7361
7362 tw32(RCVBDI_STD_THRESH, val);
7363
7364 /* Initialize TG3_BDINFO's at:
7365 * RCVDBDI_STD_BD: standard eth size rx ring
7366 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7367 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7368 *
7369 * like so:
7370 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7371 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7372 * ring attribute flags
7373 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7374 *
7375 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7376 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7377 *
7378 * The size of each ring is fixed in the firmware, but the location is
7379 * configurable.
7380 */
7381 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7382 ((u64) tp->rx_std_mapping >> 32));
7383 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7384 ((u64) tp->rx_std_mapping & 0xffffffff));
7385 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7386 NIC_SRAM_RX_BUFFER_DESC);
7387
7388 /* Don't even try to program the JUMBO/MINI buffer descriptor
7389 * configs on 5705.
7390 */
7391 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7392 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7393 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
7394 } else {
7395 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7396 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7397
7398 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7399 BDINFO_FLAGS_DISABLED);
7400
7401 /* Setup replenish threshold. */
7402 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7403
7404 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7405 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7406 ((u64) tp->rx_jumbo_mapping >> 32));
7407 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7408 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
7409 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7410 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7411 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7412 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7413 } else {
7414 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7415 BDINFO_FLAGS_DISABLED);
7416 }
7417
7418 }
7419
7420 /* There is only one send ring on 5705/5750, no need to explicitly
7421 * disable the others.
7422 */
7423 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7424 /* Clear out send RCB ring in SRAM. */
7425 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7426 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7427 BDINFO_FLAGS_DISABLED);
7428 }
7429
7430 tp->tx_prod = 0;
7431 tp->tx_cons = 0;
7432 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7433 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7434
7435 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7436 tp->tx_desc_mapping,
7437 (TG3_TX_RING_SIZE <<
7438 BDINFO_FLAGS_MAXLEN_SHIFT),
7439 NIC_SRAM_TX_BUFFER_DESC);
7440
7441 /* There is only one receive return ring on 5705/5750, no need
7442 * to explicitly disable the others.
7443 */
7444 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7445 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7446 i += TG3_BDINFO_SIZE) {
7447 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7448 BDINFO_FLAGS_DISABLED);
7449 }
7450 }
7451
7452 tp->rx_rcb_ptr = 0;
7453 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7454
7455 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7456 tp->rx_rcb_mapping,
7457 (TG3_RX_RCB_RING_SIZE(tp) <<
7458 BDINFO_FLAGS_MAXLEN_SHIFT),
7459 0);
7460
7461 tp->rx_std_ptr = tp->rx_pending;
7462 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7463 tp->rx_std_ptr);
7464
7465 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7466 tp->rx_jumbo_pending : 0;
7467 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7468 tp->rx_jumbo_ptr);
7469
7470 /* Initialize MAC address and backoff seed. */
7471 __tg3_set_mac_addr(tp, 0);
7472
7473 /* MTU + ethernet header + FCS + optional VLAN tag */
7474 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
7475
7476 /* The slot time is changed by tg3_setup_phy if we
7477 * run at gigabit with half duplex.
7478 */
7479 tw32(MAC_TX_LENGTHS,
7480 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7481 (6 << TX_LENGTHS_IPG_SHIFT) |
7482 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7483
7484 /* Receive rules. */
7485 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7486 tw32(RCVLPC_CONFIG, 0x0181);
7487
7488 /* Calculate RDMAC_MODE setting early, we need it to determine
7489 * the RCVLPC_STATE_ENABLE mask.
7490 */
7491 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7492 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7493 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7494 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7495 RDMAC_MODE_LNGREAD_ENAB);
7496
7497 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7498 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7499 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7500 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7501 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7502 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7503
7504 /* If statement applies to 5705 and 5750 PCI devices only */
7505 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7506 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7507 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7508 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7509 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7510 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7511 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7512 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7513 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7514 }
7515 }
7516
7517 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7518 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7519
7520 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7521 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7522
7523 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7524 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7525 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7526
7527 /* Receive/send statistics. */
7528 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7529 val = tr32(RCVLPC_STATS_ENABLE);
7530 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7531 tw32(RCVLPC_STATS_ENABLE, val);
7532 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7533 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7534 val = tr32(RCVLPC_STATS_ENABLE);
7535 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7536 tw32(RCVLPC_STATS_ENABLE, val);
7537 } else {
7538 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7539 }
7540 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7541 tw32(SNDDATAI_STATSENAB, 0xffffff);
7542 tw32(SNDDATAI_STATSCTRL,
7543 (SNDDATAI_SCTRL_ENABLE |
7544 SNDDATAI_SCTRL_FASTUPD));
7545
7546 /* Setup host coalescing engine. */
7547 tw32(HOSTCC_MODE, 0);
7548 for (i = 0; i < 2000; i++) {
7549 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7550 break;
7551 udelay(10);
7552 }
7553
7554 __tg3_set_coalesce(tp, &tp->coal);
7555
7556 /* set status block DMA address */
7557 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7558 ((u64) tp->status_mapping >> 32));
7559 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7560 ((u64) tp->status_mapping & 0xffffffff));
7561
7562 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7563 /* Status/statistics block address. See tg3_timer,
7564 * the tg3_periodic_fetch_stats call there, and
7565 * tg3_get_stats to see how this works for 5705/5750 chips.
7566 */
7567 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7568 ((u64) tp->stats_mapping >> 32));
7569 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7570 ((u64) tp->stats_mapping & 0xffffffff));
7571 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7572 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7573 }
7574
7575 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7576
7577 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7578 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7579 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7580 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7581
7582 /* Clear statistics/status block in chip, and status block in ram. */
7583 for (i = NIC_SRAM_STATS_BLK;
7584 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7585 i += sizeof(u32)) {
7586 tg3_write_mem(tp, i, 0);
7587 udelay(40);
7588 }
7589 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7590
7591 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7592 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7593 /* reset to prevent losing 1st rx packet intermittently */
7594 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7595 udelay(10);
7596 }
7597
7598 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7599 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7600 else
7601 tp->mac_mode = 0;
7602 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7603 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7604 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7605 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7606 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7607 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7608 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7609 udelay(40);
7610
7611 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7612 * If TG3_FLG2_IS_NIC is zero, we should read the
7613 * register to preserve the GPIO settings for LOMs. The GPIOs,
7614 * whether used as inputs or outputs, are set by boot code after
7615 * reset.
7616 */
7617 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7618 u32 gpio_mask;
7619
7620 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7621 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7622 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7623
7624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7625 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7626 GRC_LCLCTRL_GPIO_OUTPUT3;
7627
7628 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7629 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7630
7631 tp->grc_local_ctrl &= ~gpio_mask;
7632 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7633
7634 /* GPIO1 must be driven high for eeprom write protect */
7635 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7636 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7637 GRC_LCLCTRL_GPIO_OUTPUT1);
7638 }
7639 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7640 udelay(100);
7641
7642 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7643 tp->last_tag = 0;
7644
7645 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7646 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7647 udelay(40);
7648 }
7649
7650 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7651 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7652 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7653 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7654 WDMAC_MODE_LNGREAD_ENAB);
7655
7656 /* If statement applies to 5705 and 5750 PCI devices only */
7657 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7658 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7659 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7660 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7661 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7662 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7663 /* nothing */
7664 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7665 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7666 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7667 val |= WDMAC_MODE_RX_ACCEL;
7668 }
7669 }
7670
7671 /* Enable host coalescing bug fix */
7672 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7673 val |= WDMAC_MODE_STATUS_TAG_FIX;
7674
7675 tw32_f(WDMAC_MODE, val);
7676 udelay(40);
7677
7678 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7679 u16 pcix_cmd;
7680
7681 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7682 &pcix_cmd);
7683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7684 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7685 pcix_cmd |= PCI_X_CMD_READ_2K;
7686 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7687 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7688 pcix_cmd |= PCI_X_CMD_READ_2K;
7689 }
7690 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7691 pcix_cmd);
7692 }
7693
7694 tw32_f(RDMAC_MODE, rdmac_mode);
7695 udelay(40);
7696
7697 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7698 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7699 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7700
7701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7702 tw32(SNDDATAC_MODE,
7703 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7704 else
7705 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7706
7707 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7708 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7709 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7710 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7711 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7712 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7713 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7714 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7715
7716 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7717 err = tg3_load_5701_a0_firmware_fix(tp);
7718 if (err)
7719 return err;
7720 }
7721
7722 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7723 err = tg3_load_tso_firmware(tp);
7724 if (err)
7725 return err;
7726 }
7727
7728 tp->tx_mode = TX_MODE_ENABLE;
7729 tw32_f(MAC_TX_MODE, tp->tx_mode);
7730 udelay(100);
7731
7732 tp->rx_mode = RX_MODE_ENABLE;
7733 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7734 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7735
7736 tw32_f(MAC_RX_MODE, tp->rx_mode);
7737 udelay(10);
7738
7739 tw32(MAC_LED_CTRL, tp->led_ctrl);
7740
7741 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7742 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7743 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7744 udelay(10);
7745 }
7746 tw32_f(MAC_RX_MODE, tp->rx_mode);
7747 udelay(10);
7748
7749 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7750 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7751 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7752 /* Set drive transmission level to 1.2V */
7753 /* only if the signal pre-emphasis bit is not set */
7754 val = tr32(MAC_SERDES_CFG);
7755 val &= 0xfffff000;
7756 val |= 0x880;
7757 tw32(MAC_SERDES_CFG, val);
7758 }
7759 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7760 tw32(MAC_SERDES_CFG, 0x616000);
7761 }
7762
7763 /* Prevent chip from dropping frames when flow control
7764 * is enabled.
7765 */
7766 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7767
7768 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7769 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7770 /* Use hardware link auto-negotiation */
7771 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7772 }
7773
7774 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7775 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7776 u32 tmp;
7777
7778 tmp = tr32(SERDES_RX_CTRL);
7779 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7780 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7781 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7782 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7783 }
7784
7785 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7786 if (tp->link_config.phy_is_low_power) {
7787 tp->link_config.phy_is_low_power = 0;
7788 tp->link_config.speed = tp->link_config.orig_speed;
7789 tp->link_config.duplex = tp->link_config.orig_duplex;
7790 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7791 }
7792
7793 err = tg3_setup_phy(tp, 0);
7794 if (err)
7795 return err;
7796
7797 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7798 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7799 u32 tmp;
7800
7801 /* Clear CRC stats. */
7802 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7803 tg3_writephy(tp, MII_TG3_TEST1,
7804 tmp | MII_TG3_TEST1_CRC_EN);
7805 tg3_readphy(tp, 0x14, &tmp);
7806 }
7807 }
7808 }
7809
7810 __tg3_set_rx_mode(tp->dev);
7811
7812 /* Initialize receive rules. */
7813 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7814 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7815 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7816 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7817
7818 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7819 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7820 limit = 8;
7821 else
7822 limit = 16;
7823 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7824 limit -= 4;
7825 switch (limit) {
7826 case 16:
7827 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7828 case 15:
7829 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7830 case 14:
7831 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7832 case 13:
7833 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7834 case 12:
7835 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7836 case 11:
7837 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7838 case 10:
7839 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7840 case 9:
7841 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7842 case 8:
7843 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7844 case 7:
7845 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7846 case 6:
7847 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7848 case 5:
7849 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7850 case 4:
7851 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7852 case 3:
7853 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7854 case 2:
7855 case 1:
7856
7857 default:
7858 break;
7859 }
7860
7861 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7862 /* Write our heartbeat update interval to APE. */
7863 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7864 APE_HOST_HEARTBEAT_INT_DISABLE);
7865
7866 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7867
7868 return 0;
7869}
7870
7871/* Called at device open time to get the chip ready for
7872 * packet processing. Invoked with tp->lock held.
7873 */
7874static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7875{
7876 tg3_switch_clocks(tp);
7877
7878 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7879
7880 return tg3_reset_hw(tp, reset_phy);
7881}
7882
7883#define TG3_STAT_ADD32(PSTAT, REG) \
7884do { u32 __val = tr32(REG); \
7885 (PSTAT)->low += __val; \
7886 if ((PSTAT)->low < __val) \
7887 (PSTAT)->high += 1; \
7888} while (0)
7889
7890static void tg3_periodic_fetch_stats(struct tg3 *tp)
7891{
7892 struct tg3_hw_stats *sp = tp->hw_stats;
7893
7894 if (!netif_carrier_ok(tp->dev))
7895 return;
7896
7897 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7898 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7899 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7900 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7901 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7902 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7903 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7904 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7905 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7906 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7907 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7908 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7909 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7910
7911 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7912 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7913 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7914 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7915 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7916 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7917 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7918 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7919 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7920 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7921 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7922 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7923 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7924 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7925
7926 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7927 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7928 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7929}
7930
7931static void tg3_timer(unsigned long __opaque)
7932{
7933 struct tg3 *tp = (struct tg3 *) __opaque;
7934
7935 if (tp->irq_sync)
7936 goto restart_timer;
7937
7938 spin_lock(&tp->lock);
7939
7940 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7941 /* All of this garbage is because when using non-tagged
7942 * IRQ status the mailbox/status_block protocol the chip
7943 * uses with the cpu is race prone.
7944 */
7945 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7946 tw32(GRC_LOCAL_CTRL,
7947 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7948 } else {
7949 tw32(HOSTCC_MODE, tp->coalesce_mode |
7950 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7951 }
7952
7953 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7954 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7955 spin_unlock(&tp->lock);
7956 schedule_work(&tp->reset_task);
7957 return;
7958 }
7959 }
7960
7961 /* This part only runs once per second. */
7962 if (!--tp->timer_counter) {
7963 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7964 tg3_periodic_fetch_stats(tp);
7965
7966 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7967 u32 mac_stat;
7968 int phy_event;
7969
7970 mac_stat = tr32(MAC_STATUS);
7971
7972 phy_event = 0;
7973 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7974 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7975 phy_event = 1;
7976 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7977 phy_event = 1;
7978
7979 if (phy_event)
7980 tg3_setup_phy(tp, 0);
7981 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7982 u32 mac_stat = tr32(MAC_STATUS);
7983 int need_setup = 0;
7984
7985 if (netif_carrier_ok(tp->dev) &&
7986 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7987 need_setup = 1;
7988 }
7989 if (! netif_carrier_ok(tp->dev) &&
7990 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7991 MAC_STATUS_SIGNAL_DET))) {
7992 need_setup = 1;
7993 }
7994 if (need_setup) {
7995 if (!tp->serdes_counter) {
7996 tw32_f(MAC_MODE,
7997 (tp->mac_mode &
7998 ~MAC_MODE_PORT_MODE_MASK));
7999 udelay(40);
8000 tw32_f(MAC_MODE, tp->mac_mode);
8001 udelay(40);
8002 }
8003 tg3_setup_phy(tp, 0);
8004 }
8005 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8006 tg3_serdes_parallel_detect(tp);
8007
8008 tp->timer_counter = tp->timer_multiplier;
8009 }
8010
8011 /* Heartbeat is only sent once every 2 seconds.
8012 *
8013 * The heartbeat is to tell the ASF firmware that the host
8014 * driver is still alive. In the event that the OS crashes,
8015 * ASF needs to reset the hardware to free up the FIFO space
8016 * that may be filled with rx packets destined for the host.
8017 * If the FIFO is full, ASF will no longer function properly.
8018 *
8019 * Unintended resets have been reported on real time kernels
8020 * where the timer doesn't run on time. Netpoll will also have
8021 * same problem.
8022 *
8023 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8024 * to check the ring condition when the heartbeat is expiring
8025 * before doing the reset. This will prevent most unintended
8026 * resets.
8027 */
8028 if (!--tp->asf_counter) {
8029 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8030 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8031 tg3_wait_for_event_ack(tp);
8032
8033 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8034 FWCMD_NICDRV_ALIVE3);
8035 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8036 /* 5 seconds timeout */
8037 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8038
8039 tg3_generate_fw_event(tp);
8040 }
8041 tp->asf_counter = tp->asf_multiplier;
8042 }
8043
8044 spin_unlock(&tp->lock);
8045
8046restart_timer:
8047 tp->timer.expires = jiffies + tp->timer_offset;
8048 add_timer(&tp->timer);
8049}
8050
8051static int tg3_request_irq(struct tg3 *tp)
8052{
8053 irq_handler_t fn;
8054 unsigned long flags;
8055 struct net_device *dev = tp->dev;
8056
8057 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8058 fn = tg3_msi;
8059 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8060 fn = tg3_msi_1shot;
8061 flags = IRQF_SAMPLE_RANDOM;
8062 } else {
8063 fn = tg3_interrupt;
8064 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8065 fn = tg3_interrupt_tagged;
8066 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8067 }
8068 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
8069}
8070
8071static int tg3_test_interrupt(struct tg3 *tp)
8072{
8073 struct net_device *dev = tp->dev;
8074 int err, i, intr_ok = 0;
8075
8076 if (!netif_running(dev))
8077 return -ENODEV;
8078
8079 tg3_disable_ints(tp);
8080
8081 free_irq(tp->pdev->irq, dev);
8082
8083 err = request_irq(tp->pdev->irq, tg3_test_isr,
8084 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
8085 if (err)
8086 return err;
8087
8088 tp->hw_status->status &= ~SD_STATUS_UPDATED;
8089 tg3_enable_ints(tp);
8090
8091 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8092 HOSTCC_MODE_NOW);
8093
8094 for (i = 0; i < 5; i++) {
8095 u32 int_mbox, misc_host_ctrl;
8096
8097 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
8098 TG3_64BIT_REG_LOW);
8099 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8100
8101 if ((int_mbox != 0) ||
8102 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8103 intr_ok = 1;
8104 break;
8105 }
8106
8107 msleep(10);
8108 }
8109
8110 tg3_disable_ints(tp);
8111
8112 free_irq(tp->pdev->irq, dev);
8113
8114 err = tg3_request_irq(tp);
8115
8116 if (err)
8117 return err;
8118
8119 if (intr_ok)
8120 return 0;
8121
8122 return -EIO;
8123}
8124
8125/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8126 * successfully restored
8127 */
8128static int tg3_test_msi(struct tg3 *tp)
8129{
8130 struct net_device *dev = tp->dev;
8131 int err;
8132 u16 pci_cmd;
8133
8134 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8135 return 0;
8136
8137 /* Turn off SERR reporting in case MSI terminates with Master
8138 * Abort.
8139 */
8140 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8141 pci_write_config_word(tp->pdev, PCI_COMMAND,
8142 pci_cmd & ~PCI_COMMAND_SERR);
8143
8144 err = tg3_test_interrupt(tp);
8145
8146 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8147
8148 if (!err)
8149 return 0;
8150
8151 /* other failures */
8152 if (err != -EIO)
8153 return err;
8154
8155 /* MSI test failed, go back to INTx mode */
8156 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8157 "switching to INTx mode. Please report this failure to "
8158 "the PCI maintainer and include system chipset information.\n",
8159 tp->dev->name);
8160
8161 free_irq(tp->pdev->irq, dev);
8162 pci_disable_msi(tp->pdev);
8163
8164 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8165
8166 err = tg3_request_irq(tp);
8167 if (err)
8168 return err;
8169
8170 /* Need to reset the chip because the MSI cycle may have terminated
8171 * with Master Abort.
8172 */
8173 tg3_full_lock(tp, 1);
8174
8175 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8176 err = tg3_init_hw(tp, 1);
8177
8178 tg3_full_unlock(tp);
8179
8180 if (err)
8181 free_irq(tp->pdev->irq, dev);
8182
8183 return err;
8184}
8185
8186static int tg3_open(struct net_device *dev)
8187{
8188 struct tg3 *tp = netdev_priv(dev);
8189 int err;
8190
8191 netif_carrier_off(tp->dev);
8192
8193 err = tg3_set_power_state(tp, PCI_D0);
8194 if (err)
8195 return err;
8196
8197 tg3_full_lock(tp, 0);
8198
8199 tg3_disable_ints(tp);
8200 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8201
8202 tg3_full_unlock(tp);
8203
8204 /* The placement of this call is tied
8205 * to the setup and use of Host TX descriptors.
8206 */
8207 err = tg3_alloc_consistent(tp);
8208 if (err)
8209 return err;
8210
8211 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
8212 /* All MSI supporting chips should support tagged
8213 * status. Assert that this is the case.
8214 */
8215 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8216 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8217 "Not using MSI.\n", tp->dev->name);
8218 } else if (pci_enable_msi(tp->pdev) == 0) {
8219 u32 msi_mode;
8220
8221 msi_mode = tr32(MSGINT_MODE);
8222 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8223 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8224 }
8225 }
8226 err = tg3_request_irq(tp);
8227
8228 if (err) {
8229 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8230 pci_disable_msi(tp->pdev);
8231 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8232 }
8233 tg3_free_consistent(tp);
8234 return err;
8235 }
8236
8237 napi_enable(&tp->napi);
8238
8239 tg3_full_lock(tp, 0);
8240
8241 err = tg3_init_hw(tp, 1);
8242 if (err) {
8243 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8244 tg3_free_rings(tp);
8245 } else {
8246 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8247 tp->timer_offset = HZ;
8248 else
8249 tp->timer_offset = HZ / 10;
8250
8251 BUG_ON(tp->timer_offset > HZ);
8252 tp->timer_counter = tp->timer_multiplier =
8253 (HZ / tp->timer_offset);
8254 tp->asf_counter = tp->asf_multiplier =
8255 ((HZ / tp->timer_offset) * 2);
8256
8257 init_timer(&tp->timer);
8258 tp->timer.expires = jiffies + tp->timer_offset;
8259 tp->timer.data = (unsigned long) tp;
8260 tp->timer.function = tg3_timer;
8261 }
8262
8263 tg3_full_unlock(tp);
8264
8265 if (err) {
8266 napi_disable(&tp->napi);
8267 free_irq(tp->pdev->irq, dev);
8268 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8269 pci_disable_msi(tp->pdev);
8270 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8271 }
8272 tg3_free_consistent(tp);
8273 return err;
8274 }
8275
8276 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8277 err = tg3_test_msi(tp);
8278
8279 if (err) {
8280 tg3_full_lock(tp, 0);
8281
8282 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8283 pci_disable_msi(tp->pdev);
8284 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8285 }
8286 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8287 tg3_free_rings(tp);
8288 tg3_free_consistent(tp);
8289
8290 tg3_full_unlock(tp);
8291
8292 napi_disable(&tp->napi);
8293
8294 return err;
8295 }
8296
8297 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8298 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8299 u32 val = tr32(PCIE_TRANSACTION_CFG);
8300
8301 tw32(PCIE_TRANSACTION_CFG,
8302 val | PCIE_TRANS_CFG_1SHOT_MSI);
8303 }
8304 }
8305 }
8306
8307 tg3_phy_start(tp);
8308
8309 tg3_full_lock(tp, 0);
8310
8311 add_timer(&tp->timer);
8312 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8313 tg3_enable_ints(tp);
8314
8315 tg3_full_unlock(tp);
8316
8317 netif_start_queue(dev);
8318
8319 return 0;
8320}
8321
8322#if 0
8323/*static*/ void tg3_dump_state(struct tg3 *tp)
8324{
8325 u32 val32, val32_2, val32_3, val32_4, val32_5;
8326 u16 val16;
8327 int i;
8328
8329 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8330 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8331 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8332 val16, val32);
8333
8334 /* MAC block */
8335 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8336 tr32(MAC_MODE), tr32(MAC_STATUS));
8337 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8338 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8339 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8340 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8341 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8342 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8343
8344 /* Send data initiator control block */
8345 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8346 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8347 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8348 tr32(SNDDATAI_STATSCTRL));
8349
8350 /* Send data completion control block */
8351 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8352
8353 /* Send BD ring selector block */
8354 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8355 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8356
8357 /* Send BD initiator control block */
8358 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8359 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8360
8361 /* Send BD completion control block */
8362 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8363
8364 /* Receive list placement control block */
8365 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8366 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8367 printk(" RCVLPC_STATSCTRL[%08x]\n",
8368 tr32(RCVLPC_STATSCTRL));
8369
8370 /* Receive data and receive BD initiator control block */
8371 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8372 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8373
8374 /* Receive data completion control block */
8375 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8376 tr32(RCVDCC_MODE));
8377
8378 /* Receive BD initiator control block */
8379 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8380 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8381
8382 /* Receive BD completion control block */
8383 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8384 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8385
8386 /* Receive list selector control block */
8387 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8388 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8389
8390 /* Mbuf cluster free block */
8391 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8392 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8393
8394 /* Host coalescing control block */
8395 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8396 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8397 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8398 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8399 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8400 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8401 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8402 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8403 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8404 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8405 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8406 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8407
8408 /* Memory arbiter control block */
8409 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8410 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8411
8412 /* Buffer manager control block */
8413 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8414 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8415 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8416 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8417 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8418 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8419 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8420 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8421
8422 /* Read DMA control block */
8423 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8424 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8425
8426 /* Write DMA control block */
8427 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8428 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8429
8430 /* DMA completion block */
8431 printk("DEBUG: DMAC_MODE[%08x]\n",
8432 tr32(DMAC_MODE));
8433
8434 /* GRC block */
8435 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8436 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8437 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8438 tr32(GRC_LOCAL_CTRL));
8439
8440 /* TG3_BDINFOs */
8441 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8442 tr32(RCVDBDI_JUMBO_BD + 0x0),
8443 tr32(RCVDBDI_JUMBO_BD + 0x4),
8444 tr32(RCVDBDI_JUMBO_BD + 0x8),
8445 tr32(RCVDBDI_JUMBO_BD + 0xc));
8446 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8447 tr32(RCVDBDI_STD_BD + 0x0),
8448 tr32(RCVDBDI_STD_BD + 0x4),
8449 tr32(RCVDBDI_STD_BD + 0x8),
8450 tr32(RCVDBDI_STD_BD + 0xc));
8451 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8452 tr32(RCVDBDI_MINI_BD + 0x0),
8453 tr32(RCVDBDI_MINI_BD + 0x4),
8454 tr32(RCVDBDI_MINI_BD + 0x8),
8455 tr32(RCVDBDI_MINI_BD + 0xc));
8456
8457 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8458 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8459 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8460 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8461 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8462 val32, val32_2, val32_3, val32_4);
8463
8464 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8465 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8466 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8467 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8468 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8469 val32, val32_2, val32_3, val32_4);
8470
8471 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8472 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8473 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8474 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8475 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8476 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8477 val32, val32_2, val32_3, val32_4, val32_5);
8478
8479 /* SW status block */
8480 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8481 tp->hw_status->status,
8482 tp->hw_status->status_tag,
8483 tp->hw_status->rx_jumbo_consumer,
8484 tp->hw_status->rx_consumer,
8485 tp->hw_status->rx_mini_consumer,
8486 tp->hw_status->idx[0].rx_producer,
8487 tp->hw_status->idx[0].tx_consumer);
8488
8489 /* SW statistics block */
8490 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8491 ((u32 *)tp->hw_stats)[0],
8492 ((u32 *)tp->hw_stats)[1],
8493 ((u32 *)tp->hw_stats)[2],
8494 ((u32 *)tp->hw_stats)[3]);
8495
8496 /* Mailboxes */
8497 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8498 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8499 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8500 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8501 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8502
8503 /* NIC side send descriptors. */
8504 for (i = 0; i < 6; i++) {
8505 unsigned long txd;
8506
8507 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8508 + (i * sizeof(struct tg3_tx_buffer_desc));
8509 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8510 i,
8511 readl(txd + 0x0), readl(txd + 0x4),
8512 readl(txd + 0x8), readl(txd + 0xc));
8513 }
8514
8515 /* NIC side RX descriptors. */
8516 for (i = 0; i < 6; i++) {
8517 unsigned long rxd;
8518
8519 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8520 + (i * sizeof(struct tg3_rx_buffer_desc));
8521 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8522 i,
8523 readl(rxd + 0x0), readl(rxd + 0x4),
8524 readl(rxd + 0x8), readl(rxd + 0xc));
8525 rxd += (4 * sizeof(u32));
8526 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8527 i,
8528 readl(rxd + 0x0), readl(rxd + 0x4),
8529 readl(rxd + 0x8), readl(rxd + 0xc));
8530 }
8531
8532 for (i = 0; i < 6; i++) {
8533 unsigned long rxd;
8534
8535 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8536 + (i * sizeof(struct tg3_rx_buffer_desc));
8537 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8538 i,
8539 readl(rxd + 0x0), readl(rxd + 0x4),
8540 readl(rxd + 0x8), readl(rxd + 0xc));
8541 rxd += (4 * sizeof(u32));
8542 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8543 i,
8544 readl(rxd + 0x0), readl(rxd + 0x4),
8545 readl(rxd + 0x8), readl(rxd + 0xc));
8546 }
8547}
8548#endif
8549
8550static struct net_device_stats *tg3_get_stats(struct net_device *);
8551static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8552
8553static int tg3_close(struct net_device *dev)
8554{
8555 struct tg3 *tp = netdev_priv(dev);
8556
8557 napi_disable(&tp->napi);
8558 cancel_work_sync(&tp->reset_task);
8559
8560 netif_stop_queue(dev);
8561
8562 del_timer_sync(&tp->timer);
8563
8564 tg3_full_lock(tp, 1);
8565#if 0
8566 tg3_dump_state(tp);
8567#endif
8568
8569 tg3_disable_ints(tp);
8570
8571 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8572 tg3_free_rings(tp);
8573 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8574
8575 tg3_full_unlock(tp);
8576
8577 free_irq(tp->pdev->irq, dev);
8578 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8579 pci_disable_msi(tp->pdev);
8580 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8581 }
8582
8583 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8584 sizeof(tp->net_stats_prev));
8585 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8586 sizeof(tp->estats_prev));
8587
8588 tg3_free_consistent(tp);
8589
8590 tg3_set_power_state(tp, PCI_D3hot);
8591
8592 netif_carrier_off(tp->dev);
8593
8594 return 0;
8595}
8596
8597static inline unsigned long get_stat64(tg3_stat64_t *val)
8598{
8599 unsigned long ret;
8600
8601#if (BITS_PER_LONG == 32)
8602 ret = val->low;
8603#else
8604 ret = ((u64)val->high << 32) | ((u64)val->low);
8605#endif
8606 return ret;
8607}
8608
8609static inline u64 get_estat64(tg3_stat64_t *val)
8610{
8611 return ((u64)val->high << 32) | ((u64)val->low);
8612}
8613
8614static unsigned long calc_crc_errors(struct tg3 *tp)
8615{
8616 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8617
8618 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8619 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8620 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8621 u32 val;
8622
8623 spin_lock_bh(&tp->lock);
8624 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8625 tg3_writephy(tp, MII_TG3_TEST1,
8626 val | MII_TG3_TEST1_CRC_EN);
8627 tg3_readphy(tp, 0x14, &val);
8628 } else
8629 val = 0;
8630 spin_unlock_bh(&tp->lock);
8631
8632 tp->phy_crc_errors += val;
8633
8634 return tp->phy_crc_errors;
8635 }
8636
8637 return get_stat64(&hw_stats->rx_fcs_errors);
8638}
8639
8640#define ESTAT_ADD(member) \
8641 estats->member = old_estats->member + \
8642 get_estat64(&hw_stats->member)
8643
8644static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8645{
8646 struct tg3_ethtool_stats *estats = &tp->estats;
8647 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8648 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8649
8650 if (!hw_stats)
8651 return old_estats;
8652
8653 ESTAT_ADD(rx_octets);
8654 ESTAT_ADD(rx_fragments);
8655 ESTAT_ADD(rx_ucast_packets);
8656 ESTAT_ADD(rx_mcast_packets);
8657 ESTAT_ADD(rx_bcast_packets);
8658 ESTAT_ADD(rx_fcs_errors);
8659 ESTAT_ADD(rx_align_errors);
8660 ESTAT_ADD(rx_xon_pause_rcvd);
8661 ESTAT_ADD(rx_xoff_pause_rcvd);
8662 ESTAT_ADD(rx_mac_ctrl_rcvd);
8663 ESTAT_ADD(rx_xoff_entered);
8664 ESTAT_ADD(rx_frame_too_long_errors);
8665 ESTAT_ADD(rx_jabbers);
8666 ESTAT_ADD(rx_undersize_packets);
8667 ESTAT_ADD(rx_in_length_errors);
8668 ESTAT_ADD(rx_out_length_errors);
8669 ESTAT_ADD(rx_64_or_less_octet_packets);
8670 ESTAT_ADD(rx_65_to_127_octet_packets);
8671 ESTAT_ADD(rx_128_to_255_octet_packets);
8672 ESTAT_ADD(rx_256_to_511_octet_packets);
8673 ESTAT_ADD(rx_512_to_1023_octet_packets);
8674 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8675 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8676 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8677 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8678 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8679
8680 ESTAT_ADD(tx_octets);
8681 ESTAT_ADD(tx_collisions);
8682 ESTAT_ADD(tx_xon_sent);
8683 ESTAT_ADD(tx_xoff_sent);
8684 ESTAT_ADD(tx_flow_control);
8685 ESTAT_ADD(tx_mac_errors);
8686 ESTAT_ADD(tx_single_collisions);
8687 ESTAT_ADD(tx_mult_collisions);
8688 ESTAT_ADD(tx_deferred);
8689 ESTAT_ADD(tx_excessive_collisions);
8690 ESTAT_ADD(tx_late_collisions);
8691 ESTAT_ADD(tx_collide_2times);
8692 ESTAT_ADD(tx_collide_3times);
8693 ESTAT_ADD(tx_collide_4times);
8694 ESTAT_ADD(tx_collide_5times);
8695 ESTAT_ADD(tx_collide_6times);
8696 ESTAT_ADD(tx_collide_7times);
8697 ESTAT_ADD(tx_collide_8times);
8698 ESTAT_ADD(tx_collide_9times);
8699 ESTAT_ADD(tx_collide_10times);
8700 ESTAT_ADD(tx_collide_11times);
8701 ESTAT_ADD(tx_collide_12times);
8702 ESTAT_ADD(tx_collide_13times);
8703 ESTAT_ADD(tx_collide_14times);
8704 ESTAT_ADD(tx_collide_15times);
8705 ESTAT_ADD(tx_ucast_packets);
8706 ESTAT_ADD(tx_mcast_packets);
8707 ESTAT_ADD(tx_bcast_packets);
8708 ESTAT_ADD(tx_carrier_sense_errors);
8709 ESTAT_ADD(tx_discards);
8710 ESTAT_ADD(tx_errors);
8711
8712 ESTAT_ADD(dma_writeq_full);
8713 ESTAT_ADD(dma_write_prioq_full);
8714 ESTAT_ADD(rxbds_empty);
8715 ESTAT_ADD(rx_discards);
8716 ESTAT_ADD(rx_errors);
8717 ESTAT_ADD(rx_threshold_hit);
8718
8719 ESTAT_ADD(dma_readq_full);
8720 ESTAT_ADD(dma_read_prioq_full);
8721 ESTAT_ADD(tx_comp_queue_full);
8722
8723 ESTAT_ADD(ring_set_send_prod_index);
8724 ESTAT_ADD(ring_status_update);
8725 ESTAT_ADD(nic_irqs);
8726 ESTAT_ADD(nic_avoided_irqs);
8727 ESTAT_ADD(nic_tx_threshold_hit);
8728
8729 return estats;
8730}
8731
8732static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8733{
8734 struct tg3 *tp = netdev_priv(dev);
8735 struct net_device_stats *stats = &tp->net_stats;
8736 struct net_device_stats *old_stats = &tp->net_stats_prev;
8737 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8738
8739 if (!hw_stats)
8740 return old_stats;
8741
8742 stats->rx_packets = old_stats->rx_packets +
8743 get_stat64(&hw_stats->rx_ucast_packets) +
8744 get_stat64(&hw_stats->rx_mcast_packets) +
8745 get_stat64(&hw_stats->rx_bcast_packets);
8746
8747 stats->tx_packets = old_stats->tx_packets +
8748 get_stat64(&hw_stats->tx_ucast_packets) +
8749 get_stat64(&hw_stats->tx_mcast_packets) +
8750 get_stat64(&hw_stats->tx_bcast_packets);
8751
8752 stats->rx_bytes = old_stats->rx_bytes +
8753 get_stat64(&hw_stats->rx_octets);
8754 stats->tx_bytes = old_stats->tx_bytes +
8755 get_stat64(&hw_stats->tx_octets);
8756
8757 stats->rx_errors = old_stats->rx_errors +
8758 get_stat64(&hw_stats->rx_errors);
8759 stats->tx_errors = old_stats->tx_errors +
8760 get_stat64(&hw_stats->tx_errors) +
8761 get_stat64(&hw_stats->tx_mac_errors) +
8762 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8763 get_stat64(&hw_stats->tx_discards);
8764
8765 stats->multicast = old_stats->multicast +
8766 get_stat64(&hw_stats->rx_mcast_packets);
8767 stats->collisions = old_stats->collisions +
8768 get_stat64(&hw_stats->tx_collisions);
8769
8770 stats->rx_length_errors = old_stats->rx_length_errors +
8771 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8772 get_stat64(&hw_stats->rx_undersize_packets);
8773
8774 stats->rx_over_errors = old_stats->rx_over_errors +
8775 get_stat64(&hw_stats->rxbds_empty);
8776 stats->rx_frame_errors = old_stats->rx_frame_errors +
8777 get_stat64(&hw_stats->rx_align_errors);
8778 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8779 get_stat64(&hw_stats->tx_discards);
8780 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8781 get_stat64(&hw_stats->tx_carrier_sense_errors);
8782
8783 stats->rx_crc_errors = old_stats->rx_crc_errors +
8784 calc_crc_errors(tp);
8785
8786 stats->rx_missed_errors = old_stats->rx_missed_errors +
8787 get_stat64(&hw_stats->rx_discards);
8788
8789 return stats;
8790}
8791
8792static inline u32 calc_crc(unsigned char *buf, int len)
8793{
8794 u32 reg;
8795 u32 tmp;
8796 int j, k;
8797
8798 reg = 0xffffffff;
8799
8800 for (j = 0; j < len; j++) {
8801 reg ^= buf[j];
8802
8803 for (k = 0; k < 8; k++) {
8804 tmp = reg & 0x01;
8805
8806 reg >>= 1;
8807
8808 if (tmp) {
8809 reg ^= 0xedb88320;
8810 }
8811 }
8812 }
8813
8814 return ~reg;
8815}
8816
8817static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8818{
8819 /* accept or reject all multicast frames */
8820 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8821 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8822 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8823 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8824}
8825
8826static void __tg3_set_rx_mode(struct net_device *dev)
8827{
8828 struct tg3 *tp = netdev_priv(dev);
8829 u32 rx_mode;
8830
8831 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8832 RX_MODE_KEEP_VLAN_TAG);
8833
8834 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8835 * flag clear.
8836 */
8837#if TG3_VLAN_TAG_USED
8838 if (!tp->vlgrp &&
8839 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8840 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8841#else
8842 /* By definition, VLAN is disabled always in this
8843 * case.
8844 */
8845 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8846 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8847#endif
8848
8849 if (dev->flags & IFF_PROMISC) {
8850 /* Promiscuous mode. */
8851 rx_mode |= RX_MODE_PROMISC;
8852 } else if (dev->flags & IFF_ALLMULTI) {
8853 /* Accept all multicast. */
8854 tg3_set_multi (tp, 1);
8855 } else if (dev->mc_count < 1) {
8856 /* Reject all multicast. */
8857 tg3_set_multi (tp, 0);
8858 } else {
8859 /* Accept one or more multicast(s). */
8860 struct dev_mc_list *mclist;
8861 unsigned int i;
8862 u32 mc_filter[4] = { 0, };
8863 u32 regidx;
8864 u32 bit;
8865 u32 crc;
8866
8867 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8868 i++, mclist = mclist->next) {
8869
8870 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8871 bit = ~crc & 0x7f;
8872 regidx = (bit & 0x60) >> 5;
8873 bit &= 0x1f;
8874 mc_filter[regidx] |= (1 << bit);
8875 }
8876
8877 tw32(MAC_HASH_REG_0, mc_filter[0]);
8878 tw32(MAC_HASH_REG_1, mc_filter[1]);
8879 tw32(MAC_HASH_REG_2, mc_filter[2]);
8880 tw32(MAC_HASH_REG_3, mc_filter[3]);
8881 }
8882
8883 if (rx_mode != tp->rx_mode) {
8884 tp->rx_mode = rx_mode;
8885 tw32_f(MAC_RX_MODE, rx_mode);
8886 udelay(10);
8887 }
8888}
8889
8890static void tg3_set_rx_mode(struct net_device *dev)
8891{
8892 struct tg3 *tp = netdev_priv(dev);
8893
8894 if (!netif_running(dev))
8895 return;
8896
8897 tg3_full_lock(tp, 0);
8898 __tg3_set_rx_mode(dev);
8899 tg3_full_unlock(tp);
8900}
8901
8902#define TG3_REGDUMP_LEN (32 * 1024)
8903
8904static int tg3_get_regs_len(struct net_device *dev)
8905{
8906 return TG3_REGDUMP_LEN;
8907}
8908
8909static void tg3_get_regs(struct net_device *dev,
8910 struct ethtool_regs *regs, void *_p)
8911{
8912 u32 *p = _p;
8913 struct tg3 *tp = netdev_priv(dev);
8914 u8 *orig_p = _p;
8915 int i;
8916
8917 regs->version = 0;
8918
8919 memset(p, 0, TG3_REGDUMP_LEN);
8920
8921 if (tp->link_config.phy_is_low_power)
8922 return;
8923
8924 tg3_full_lock(tp, 0);
8925
8926#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8927#define GET_REG32_LOOP(base,len) \
8928do { p = (u32 *)(orig_p + (base)); \
8929 for (i = 0; i < len; i += 4) \
8930 __GET_REG32((base) + i); \
8931} while (0)
8932#define GET_REG32_1(reg) \
8933do { p = (u32 *)(orig_p + (reg)); \
8934 __GET_REG32((reg)); \
8935} while (0)
8936
8937 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8938 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8939 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8940 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8941 GET_REG32_1(SNDDATAC_MODE);
8942 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8943 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8944 GET_REG32_1(SNDBDC_MODE);
8945 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8946 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8947 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8948 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8949 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8950 GET_REG32_1(RCVDCC_MODE);
8951 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8952 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8953 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8954 GET_REG32_1(MBFREE_MODE);
8955 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8956 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8957 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8958 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8959 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8960 GET_REG32_1(RX_CPU_MODE);
8961 GET_REG32_1(RX_CPU_STATE);
8962 GET_REG32_1(RX_CPU_PGMCTR);
8963 GET_REG32_1(RX_CPU_HWBKPT);
8964 GET_REG32_1(TX_CPU_MODE);
8965 GET_REG32_1(TX_CPU_STATE);
8966 GET_REG32_1(TX_CPU_PGMCTR);
8967 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8968 GET_REG32_LOOP(FTQ_RESET, 0x120);
8969 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8970 GET_REG32_1(DMAC_MODE);
8971 GET_REG32_LOOP(GRC_MODE, 0x4c);
8972 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8973 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8974
8975#undef __GET_REG32
8976#undef GET_REG32_LOOP
8977#undef GET_REG32_1
8978
8979 tg3_full_unlock(tp);
8980}
8981
8982static int tg3_get_eeprom_len(struct net_device *dev)
8983{
8984 struct tg3 *tp = netdev_priv(dev);
8985
8986 return tp->nvram_size;
8987}
8988
8989static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8990static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8991static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8992
8993static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8994{
8995 struct tg3 *tp = netdev_priv(dev);
8996 int ret;
8997 u8 *pd;
8998 u32 i, offset, len, b_offset, b_count;
8999 __le32 val;
9000
9001 if (tp->link_config.phy_is_low_power)
9002 return -EAGAIN;
9003
9004 offset = eeprom->offset;
9005 len = eeprom->len;
9006 eeprom->len = 0;
9007
9008 eeprom->magic = TG3_EEPROM_MAGIC;
9009
9010 if (offset & 3) {
9011 /* adjustments to start on required 4 byte boundary */
9012 b_offset = offset & 3;
9013 b_count = 4 - b_offset;
9014 if (b_count > len) {
9015 /* i.e. offset=1 len=2 */
9016 b_count = len;
9017 }
9018 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
9019 if (ret)
9020 return ret;
9021 memcpy(data, ((char*)&val) + b_offset, b_count);
9022 len -= b_count;
9023 offset += b_count;
9024 eeprom->len += b_count;
9025 }
9026
9027 /* read bytes upto the last 4 byte boundary */
9028 pd = &data[eeprom->len];
9029 for (i = 0; i < (len - (len & 3)); i += 4) {
9030 ret = tg3_nvram_read_le(tp, offset + i, &val);
9031 if (ret) {
9032 eeprom->len += i;
9033 return ret;
9034 }
9035 memcpy(pd + i, &val, 4);
9036 }
9037 eeprom->len += i;
9038
9039 if (len & 3) {
9040 /* read last bytes not ending on 4 byte boundary */
9041 pd = &data[eeprom->len];
9042 b_count = len & 3;
9043 b_offset = offset + len - b_count;
9044 ret = tg3_nvram_read_le(tp, b_offset, &val);
9045 if (ret)
9046 return ret;
9047 memcpy(pd, &val, b_count);
9048 eeprom->len += b_count;
9049 }
9050 return 0;
9051}
9052
9053static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9054
9055static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9056{
9057 struct tg3 *tp = netdev_priv(dev);
9058 int ret;
9059 u32 offset, len, b_offset, odd_len;
9060 u8 *buf;
9061 __le32 start, end;
9062
9063 if (tp->link_config.phy_is_low_power)
9064 return -EAGAIN;
9065
9066 if (eeprom->magic != TG3_EEPROM_MAGIC)
9067 return -EINVAL;
9068
9069 offset = eeprom->offset;
9070 len = eeprom->len;
9071
9072 if ((b_offset = (offset & 3))) {
9073 /* adjustments to start on required 4 byte boundary */
9074 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
9075 if (ret)
9076 return ret;
9077 len += b_offset;
9078 offset &= ~3;
9079 if (len < 4)
9080 len = 4;
9081 }
9082
9083 odd_len = 0;
9084 if (len & 3) {
9085 /* adjustments to end on required 4 byte boundary */
9086 odd_len = 1;
9087 len = (len + 3) & ~3;
9088 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
9089 if (ret)
9090 return ret;
9091 }
9092
9093 buf = data;
9094 if (b_offset || odd_len) {
9095 buf = kmalloc(len, GFP_KERNEL);
9096 if (!buf)
9097 return -ENOMEM;
9098 if (b_offset)
9099 memcpy(buf, &start, 4);
9100 if (odd_len)
9101 memcpy(buf+len-4, &end, 4);
9102 memcpy(buf + b_offset, data, eeprom->len);
9103 }
9104
9105 ret = tg3_nvram_write_block(tp, offset, len, buf);
9106
9107 if (buf != data)
9108 kfree(buf);
9109
9110 return ret;
9111}
9112
9113static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9114{
9115 struct tg3 *tp = netdev_priv(dev);
9116
9117 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9118 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9119 return -EAGAIN;
9120 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9121 }
9122
9123 cmd->supported = (SUPPORTED_Autoneg);
9124
9125 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9126 cmd->supported |= (SUPPORTED_1000baseT_Half |
9127 SUPPORTED_1000baseT_Full);
9128
9129 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9130 cmd->supported |= (SUPPORTED_100baseT_Half |
9131 SUPPORTED_100baseT_Full |
9132 SUPPORTED_10baseT_Half |
9133 SUPPORTED_10baseT_Full |
9134 SUPPORTED_TP);
9135 cmd->port = PORT_TP;
9136 } else {
9137 cmd->supported |= SUPPORTED_FIBRE;
9138 cmd->port = PORT_FIBRE;
9139 }
9140
9141 cmd->advertising = tp->link_config.advertising;
9142 if (netif_running(dev)) {
9143 cmd->speed = tp->link_config.active_speed;
9144 cmd->duplex = tp->link_config.active_duplex;
9145 }
9146 cmd->phy_address = PHY_ADDR;
9147 cmd->transceiver = 0;
9148 cmd->autoneg = tp->link_config.autoneg;
9149 cmd->maxtxpkt = 0;
9150 cmd->maxrxpkt = 0;
9151 return 0;
9152}
9153
9154static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9155{
9156 struct tg3 *tp = netdev_priv(dev);
9157
9158 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9159 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9160 return -EAGAIN;
9161 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9162 }
9163
9164 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9165 /* These are the only valid advertisement bits allowed. */
9166 if (cmd->autoneg == AUTONEG_ENABLE &&
9167 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
9168 ADVERTISED_1000baseT_Full |
9169 ADVERTISED_Autoneg |
9170 ADVERTISED_FIBRE)))
9171 return -EINVAL;
9172 /* Fiber can only do SPEED_1000. */
9173 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9174 (cmd->speed != SPEED_1000))
9175 return -EINVAL;
9176 /* Copper cannot force SPEED_1000. */
9177 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9178 (cmd->speed == SPEED_1000))
9179 return -EINVAL;
9180 else if ((cmd->speed == SPEED_1000) &&
9181 (tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9182 return -EINVAL;
9183
9184 tg3_full_lock(tp, 0);
9185
9186 tp->link_config.autoneg = cmd->autoneg;
9187 if (cmd->autoneg == AUTONEG_ENABLE) {
9188 tp->link_config.advertising = (cmd->advertising |
9189 ADVERTISED_Autoneg);
9190 tp->link_config.speed = SPEED_INVALID;
9191 tp->link_config.duplex = DUPLEX_INVALID;
9192 } else {
9193 tp->link_config.advertising = 0;
9194 tp->link_config.speed = cmd->speed;
9195 tp->link_config.duplex = cmd->duplex;
9196 }
9197
9198 tp->link_config.orig_speed = tp->link_config.speed;
9199 tp->link_config.orig_duplex = tp->link_config.duplex;
9200 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9201
9202 if (netif_running(dev))
9203 tg3_setup_phy(tp, 1);
9204
9205 tg3_full_unlock(tp);
9206
9207 return 0;
9208}
9209
9210static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9211{
9212 struct tg3 *tp = netdev_priv(dev);
9213
9214 strcpy(info->driver, DRV_MODULE_NAME);
9215 strcpy(info->version, DRV_MODULE_VERSION);
9216 strcpy(info->fw_version, tp->fw_ver);
9217 strcpy(info->bus_info, pci_name(tp->pdev));
9218}
9219
9220static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9221{
9222 struct tg3 *tp = netdev_priv(dev);
9223
9224 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9225 device_can_wakeup(&tp->pdev->dev))
9226 wol->supported = WAKE_MAGIC;
9227 else
9228 wol->supported = 0;
9229 wol->wolopts = 0;
9230 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9231 device_can_wakeup(&tp->pdev->dev))
9232 wol->wolopts = WAKE_MAGIC;
9233 memset(&wol->sopass, 0, sizeof(wol->sopass));
9234}
9235
9236static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9237{
9238 struct tg3 *tp = netdev_priv(dev);
9239 struct device *dp = &tp->pdev->dev;
9240
9241 if (wol->wolopts & ~WAKE_MAGIC)
9242 return -EINVAL;
9243 if ((wol->wolopts & WAKE_MAGIC) &&
9244 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9245 return -EINVAL;
9246
9247 spin_lock_bh(&tp->lock);
9248 if (wol->wolopts & WAKE_MAGIC) {
9249 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9250 device_set_wakeup_enable(dp, true);
9251 } else {
9252 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9253 device_set_wakeup_enable(dp, false);
9254 }
9255 spin_unlock_bh(&tp->lock);
9256
9257 return 0;
9258}
9259
9260static u32 tg3_get_msglevel(struct net_device *dev)
9261{
9262 struct tg3 *tp = netdev_priv(dev);
9263 return tp->msg_enable;
9264}
9265
9266static void tg3_set_msglevel(struct net_device *dev, u32 value)
9267{
9268 struct tg3 *tp = netdev_priv(dev);
9269 tp->msg_enable = value;
9270}
9271
9272static int tg3_set_tso(struct net_device *dev, u32 value)
9273{
9274 struct tg3 *tp = netdev_priv(dev);
9275
9276 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9277 if (value)
9278 return -EINVAL;
9279 return 0;
9280 }
9281 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9282 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9283 if (value) {
9284 dev->features |= NETIF_F_TSO6;
9285 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9286 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9287 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9288 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9289 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9290 dev->features |= NETIF_F_TSO_ECN;
9291 } else
9292 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9293 }
9294 return ethtool_op_set_tso(dev, value);
9295}
9296
9297static int tg3_nway_reset(struct net_device *dev)
9298{
9299 struct tg3 *tp = netdev_priv(dev);
9300 int r;
9301
9302 if (!netif_running(dev))
9303 return -EAGAIN;
9304
9305 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9306 return -EINVAL;
9307
9308 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9309 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9310 return -EAGAIN;
9311 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9312 } else {
9313 u32 bmcr;
9314
9315 spin_lock_bh(&tp->lock);
9316 r = -EINVAL;
9317 tg3_readphy(tp, MII_BMCR, &bmcr);
9318 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9319 ((bmcr & BMCR_ANENABLE) ||
9320 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9321 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9322 BMCR_ANENABLE);
9323 r = 0;
9324 }
9325 spin_unlock_bh(&tp->lock);
9326 }
9327
9328 return r;
9329}
9330
9331static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9332{
9333 struct tg3 *tp = netdev_priv(dev);
9334
9335 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9336 ering->rx_mini_max_pending = 0;
9337 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9338 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9339 else
9340 ering->rx_jumbo_max_pending = 0;
9341
9342 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9343
9344 ering->rx_pending = tp->rx_pending;
9345 ering->rx_mini_pending = 0;
9346 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9347 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9348 else
9349 ering->rx_jumbo_pending = 0;
9350
9351 ering->tx_pending = tp->tx_pending;
9352}
9353
9354static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9355{
9356 struct tg3 *tp = netdev_priv(dev);
9357 int irq_sync = 0, err = 0;
9358
9359 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9360 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9361 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9362 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9363 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9364 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9365 return -EINVAL;
9366
9367 if (netif_running(dev)) {
9368 tg3_phy_stop(tp);
9369 tg3_netif_stop(tp);
9370 irq_sync = 1;
9371 }
9372
9373 tg3_full_lock(tp, irq_sync);
9374
9375 tp->rx_pending = ering->rx_pending;
9376
9377 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9378 tp->rx_pending > 63)
9379 tp->rx_pending = 63;
9380 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9381 tp->tx_pending = ering->tx_pending;
9382
9383 if (netif_running(dev)) {
9384 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9385 err = tg3_restart_hw(tp, 1);
9386 if (!err)
9387 tg3_netif_start(tp);
9388 }
9389
9390 tg3_full_unlock(tp);
9391
9392 if (irq_sync && !err)
9393 tg3_phy_start(tp);
9394
9395 return err;
9396}
9397
9398static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9399{
9400 struct tg3 *tp = netdev_priv(dev);
9401
9402 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9403
9404 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9405 epause->rx_pause = 1;
9406 else
9407 epause->rx_pause = 0;
9408
9409 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9410 epause->tx_pause = 1;
9411 else
9412 epause->tx_pause = 0;
9413}
9414
9415static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9416{
9417 struct tg3 *tp = netdev_priv(dev);
9418 int err = 0;
9419
9420 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9421 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9422 return -EAGAIN;
9423
9424 if (epause->autoneg) {
9425 u32 newadv;
9426 struct phy_device *phydev;
9427
9428 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9429
9430 if (epause->rx_pause) {
9431 if (epause->tx_pause)
9432 newadv = ADVERTISED_Pause;
9433 else
9434 newadv = ADVERTISED_Pause |
9435 ADVERTISED_Asym_Pause;
9436 } else if (epause->tx_pause) {
9437 newadv = ADVERTISED_Asym_Pause;
9438 } else
9439 newadv = 0;
9440
9441 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9442 u32 oldadv = phydev->advertising &
9443 (ADVERTISED_Pause |
9444 ADVERTISED_Asym_Pause);
9445 if (oldadv != newadv) {
9446 phydev->advertising &=
9447 ~(ADVERTISED_Pause |
9448 ADVERTISED_Asym_Pause);
9449 phydev->advertising |= newadv;
9450 err = phy_start_aneg(phydev);
9451 }
9452 } else {
9453 tp->link_config.advertising &=
9454 ~(ADVERTISED_Pause |
9455 ADVERTISED_Asym_Pause);
9456 tp->link_config.advertising |= newadv;
9457 }
9458 } else {
9459 if (epause->rx_pause)
9460 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9461 else
9462 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9463
9464 if (epause->tx_pause)
9465 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9466 else
9467 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9468
9469 if (netif_running(dev))
9470 tg3_setup_flow_control(tp, 0, 0);
9471 }
9472 } else {
9473 int irq_sync = 0;
9474
9475 if (netif_running(dev)) {
9476 tg3_netif_stop(tp);
9477 irq_sync = 1;
9478 }
9479
9480 tg3_full_lock(tp, irq_sync);
9481
9482 if (epause->autoneg)
9483 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9484 else
9485 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9486 if (epause->rx_pause)
9487 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9488 else
9489 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9490 if (epause->tx_pause)
9491 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9492 else
9493 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9494
9495 if (netif_running(dev)) {
9496 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9497 err = tg3_restart_hw(tp, 1);
9498 if (!err)
9499 tg3_netif_start(tp);
9500 }
9501
9502 tg3_full_unlock(tp);
9503 }
9504
9505 return err;
9506}
9507
9508static u32 tg3_get_rx_csum(struct net_device *dev)
9509{
9510 struct tg3 *tp = netdev_priv(dev);
9511 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9512}
9513
9514static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9515{
9516 struct tg3 *tp = netdev_priv(dev);
9517
9518 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9519 if (data != 0)
9520 return -EINVAL;
9521 return 0;
9522 }
9523
9524 spin_lock_bh(&tp->lock);
9525 if (data)
9526 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9527 else
9528 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9529 spin_unlock_bh(&tp->lock);
9530
9531 return 0;
9532}
9533
9534static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9535{
9536 struct tg3 *tp = netdev_priv(dev);
9537
9538 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9539 if (data != 0)
9540 return -EINVAL;
9541 return 0;
9542 }
9543
9544 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9545 ethtool_op_set_tx_ipv6_csum(dev, data);
9546 else
9547 ethtool_op_set_tx_csum(dev, data);
9548
9549 return 0;
9550}
9551
9552static int tg3_get_sset_count (struct net_device *dev, int sset)
9553{
9554 switch (sset) {
9555 case ETH_SS_TEST:
9556 return TG3_NUM_TEST;
9557 case ETH_SS_STATS:
9558 return TG3_NUM_STATS;
9559 default:
9560 return -EOPNOTSUPP;
9561 }
9562}
9563
9564static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9565{
9566 switch (stringset) {
9567 case ETH_SS_STATS:
9568 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9569 break;
9570 case ETH_SS_TEST:
9571 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9572 break;
9573 default:
9574 WARN_ON(1); /* we need a WARN() */
9575 break;
9576 }
9577}
9578
9579static int tg3_phys_id(struct net_device *dev, u32 data)
9580{
9581 struct tg3 *tp = netdev_priv(dev);
9582 int i;
9583
9584 if (!netif_running(tp->dev))
9585 return -EAGAIN;
9586
9587 if (data == 0)
9588 data = UINT_MAX / 2;
9589
9590 for (i = 0; i < (data * 2); i++) {
9591 if ((i % 2) == 0)
9592 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9593 LED_CTRL_1000MBPS_ON |
9594 LED_CTRL_100MBPS_ON |
9595 LED_CTRL_10MBPS_ON |
9596 LED_CTRL_TRAFFIC_OVERRIDE |
9597 LED_CTRL_TRAFFIC_BLINK |
9598 LED_CTRL_TRAFFIC_LED);
9599
9600 else
9601 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9602 LED_CTRL_TRAFFIC_OVERRIDE);
9603
9604 if (msleep_interruptible(500))
9605 break;
9606 }
9607 tw32(MAC_LED_CTRL, tp->led_ctrl);
9608 return 0;
9609}
9610
9611static void tg3_get_ethtool_stats (struct net_device *dev,
9612 struct ethtool_stats *estats, u64 *tmp_stats)
9613{
9614 struct tg3 *tp = netdev_priv(dev);
9615 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9616}
9617
9618#define NVRAM_TEST_SIZE 0x100
9619#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9620#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9621#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9622#define NVRAM_SELFBOOT_HW_SIZE 0x20
9623#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9624
9625static int tg3_test_nvram(struct tg3 *tp)
9626{
9627 u32 csum, magic;
9628 __le32 *buf;
9629 int i, j, k, err = 0, size;
9630
9631 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9632 return -EIO;
9633
9634 if (magic == TG3_EEPROM_MAGIC)
9635 size = NVRAM_TEST_SIZE;
9636 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9637 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9638 TG3_EEPROM_SB_FORMAT_1) {
9639 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9640 case TG3_EEPROM_SB_REVISION_0:
9641 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9642 break;
9643 case TG3_EEPROM_SB_REVISION_2:
9644 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9645 break;
9646 case TG3_EEPROM_SB_REVISION_3:
9647 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9648 break;
9649 default:
9650 return 0;
9651 }
9652 } else
9653 return 0;
9654 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9655 size = NVRAM_SELFBOOT_HW_SIZE;
9656 else
9657 return -EIO;
9658
9659 buf = kmalloc(size, GFP_KERNEL);
9660 if (buf == NULL)
9661 return -ENOMEM;
9662
9663 err = -EIO;
9664 for (i = 0, j = 0; i < size; i += 4, j++) {
9665 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9666 break;
9667 }
9668 if (i < size)
9669 goto out;
9670
9671 /* Selfboot format */
9672 magic = swab32(le32_to_cpu(buf[0]));
9673 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9674 TG3_EEPROM_MAGIC_FW) {
9675 u8 *buf8 = (u8 *) buf, csum8 = 0;
9676
9677 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9678 TG3_EEPROM_SB_REVISION_2) {
9679 /* For rev 2, the csum doesn't include the MBA. */
9680 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9681 csum8 += buf8[i];
9682 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9683 csum8 += buf8[i];
9684 } else {
9685 for (i = 0; i < size; i++)
9686 csum8 += buf8[i];
9687 }
9688
9689 if (csum8 == 0) {
9690 err = 0;
9691 goto out;
9692 }
9693
9694 err = -EIO;
9695 goto out;
9696 }
9697
9698 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9699 TG3_EEPROM_MAGIC_HW) {
9700 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9701 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9702 u8 *buf8 = (u8 *) buf;
9703
9704 /* Separate the parity bits and the data bytes. */
9705 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9706 if ((i == 0) || (i == 8)) {
9707 int l;
9708 u8 msk;
9709
9710 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9711 parity[k++] = buf8[i] & msk;
9712 i++;
9713 }
9714 else if (i == 16) {
9715 int l;
9716 u8 msk;
9717
9718 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9719 parity[k++] = buf8[i] & msk;
9720 i++;
9721
9722 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9723 parity[k++] = buf8[i] & msk;
9724 i++;
9725 }
9726 data[j++] = buf8[i];
9727 }
9728
9729 err = -EIO;
9730 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9731 u8 hw8 = hweight8(data[i]);
9732
9733 if ((hw8 & 0x1) && parity[i])
9734 goto out;
9735 else if (!(hw8 & 0x1) && !parity[i])
9736 goto out;
9737 }
9738 err = 0;
9739 goto out;
9740 }
9741
9742 /* Bootstrap checksum at offset 0x10 */
9743 csum = calc_crc((unsigned char *) buf, 0x10);
9744 if(csum != le32_to_cpu(buf[0x10/4]))
9745 goto out;
9746
9747 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9748 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9749 if (csum != le32_to_cpu(buf[0xfc/4]))
9750 goto out;
9751
9752 err = 0;
9753
9754out:
9755 kfree(buf);
9756 return err;
9757}
9758
9759#define TG3_SERDES_TIMEOUT_SEC 2
9760#define TG3_COPPER_TIMEOUT_SEC 6
9761
9762static int tg3_test_link(struct tg3 *tp)
9763{
9764 int i, max;
9765
9766 if (!netif_running(tp->dev))
9767 return -ENODEV;
9768
9769 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9770 max = TG3_SERDES_TIMEOUT_SEC;
9771 else
9772 max = TG3_COPPER_TIMEOUT_SEC;
9773
9774 for (i = 0; i < max; i++) {
9775 if (netif_carrier_ok(tp->dev))
9776 return 0;
9777
9778 if (msleep_interruptible(1000))
9779 break;
9780 }
9781
9782 return -EIO;
9783}
9784
9785/* Only test the commonly used registers */
9786static int tg3_test_registers(struct tg3 *tp)
9787{
9788 int i, is_5705, is_5750;
9789 u32 offset, read_mask, write_mask, val, save_val, read_val;
9790 static struct {
9791 u16 offset;
9792 u16 flags;
9793#define TG3_FL_5705 0x1
9794#define TG3_FL_NOT_5705 0x2
9795#define TG3_FL_NOT_5788 0x4
9796#define TG3_FL_NOT_5750 0x8
9797 u32 read_mask;
9798 u32 write_mask;
9799 } reg_tbl[] = {
9800 /* MAC Control Registers */
9801 { MAC_MODE, TG3_FL_NOT_5705,
9802 0x00000000, 0x00ef6f8c },
9803 { MAC_MODE, TG3_FL_5705,
9804 0x00000000, 0x01ef6b8c },
9805 { MAC_STATUS, TG3_FL_NOT_5705,
9806 0x03800107, 0x00000000 },
9807 { MAC_STATUS, TG3_FL_5705,
9808 0x03800100, 0x00000000 },
9809 { MAC_ADDR_0_HIGH, 0x0000,
9810 0x00000000, 0x0000ffff },
9811 { MAC_ADDR_0_LOW, 0x0000,
9812 0x00000000, 0xffffffff },
9813 { MAC_RX_MTU_SIZE, 0x0000,
9814 0x00000000, 0x0000ffff },
9815 { MAC_TX_MODE, 0x0000,
9816 0x00000000, 0x00000070 },
9817 { MAC_TX_LENGTHS, 0x0000,
9818 0x00000000, 0x00003fff },
9819 { MAC_RX_MODE, TG3_FL_NOT_5705,
9820 0x00000000, 0x000007fc },
9821 { MAC_RX_MODE, TG3_FL_5705,
9822 0x00000000, 0x000007dc },
9823 { MAC_HASH_REG_0, 0x0000,
9824 0x00000000, 0xffffffff },
9825 { MAC_HASH_REG_1, 0x0000,
9826 0x00000000, 0xffffffff },
9827 { MAC_HASH_REG_2, 0x0000,
9828 0x00000000, 0xffffffff },
9829 { MAC_HASH_REG_3, 0x0000,
9830 0x00000000, 0xffffffff },
9831
9832 /* Receive Data and Receive BD Initiator Control Registers. */
9833 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9834 0x00000000, 0xffffffff },
9835 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9836 0x00000000, 0xffffffff },
9837 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9838 0x00000000, 0x00000003 },
9839 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9840 0x00000000, 0xffffffff },
9841 { RCVDBDI_STD_BD+0, 0x0000,
9842 0x00000000, 0xffffffff },
9843 { RCVDBDI_STD_BD+4, 0x0000,
9844 0x00000000, 0xffffffff },
9845 { RCVDBDI_STD_BD+8, 0x0000,
9846 0x00000000, 0xffff0002 },
9847 { RCVDBDI_STD_BD+0xc, 0x0000,
9848 0x00000000, 0xffffffff },
9849
9850 /* Receive BD Initiator Control Registers. */
9851 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9852 0x00000000, 0xffffffff },
9853 { RCVBDI_STD_THRESH, TG3_FL_5705,
9854 0x00000000, 0x000003ff },
9855 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9856 0x00000000, 0xffffffff },
9857
9858 /* Host Coalescing Control Registers. */
9859 { HOSTCC_MODE, TG3_FL_NOT_5705,
9860 0x00000000, 0x00000004 },
9861 { HOSTCC_MODE, TG3_FL_5705,
9862 0x00000000, 0x000000f6 },
9863 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9864 0x00000000, 0xffffffff },
9865 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9866 0x00000000, 0x000003ff },
9867 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9868 0x00000000, 0xffffffff },
9869 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9870 0x00000000, 0x000003ff },
9871 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9872 0x00000000, 0xffffffff },
9873 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9874 0x00000000, 0x000000ff },
9875 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9876 0x00000000, 0xffffffff },
9877 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9878 0x00000000, 0x000000ff },
9879 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9880 0x00000000, 0xffffffff },
9881 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9882 0x00000000, 0xffffffff },
9883 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9884 0x00000000, 0xffffffff },
9885 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9886 0x00000000, 0x000000ff },
9887 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9888 0x00000000, 0xffffffff },
9889 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9890 0x00000000, 0x000000ff },
9891 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9892 0x00000000, 0xffffffff },
9893 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9894 0x00000000, 0xffffffff },
9895 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9896 0x00000000, 0xffffffff },
9897 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9898 0x00000000, 0xffffffff },
9899 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9900 0x00000000, 0xffffffff },
9901 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9902 0xffffffff, 0x00000000 },
9903 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9904 0xffffffff, 0x00000000 },
9905
9906 /* Buffer Manager Control Registers. */
9907 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9908 0x00000000, 0x007fff80 },
9909 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9910 0x00000000, 0x007fffff },
9911 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9912 0x00000000, 0x0000003f },
9913 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9914 0x00000000, 0x000001ff },
9915 { BUFMGR_MB_HIGH_WATER, 0x0000,
9916 0x00000000, 0x000001ff },
9917 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9918 0xffffffff, 0x00000000 },
9919 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9920 0xffffffff, 0x00000000 },
9921
9922 /* Mailbox Registers */
9923 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9924 0x00000000, 0x000001ff },
9925 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9926 0x00000000, 0x000001ff },
9927 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9928 0x00000000, 0x000007ff },
9929 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9930 0x00000000, 0x000001ff },
9931
9932 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9933 };
9934
9935 is_5705 = is_5750 = 0;
9936 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9937 is_5705 = 1;
9938 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9939 is_5750 = 1;
9940 }
9941
9942 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9943 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9944 continue;
9945
9946 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9947 continue;
9948
9949 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9950 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9951 continue;
9952
9953 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9954 continue;
9955
9956 offset = (u32) reg_tbl[i].offset;
9957 read_mask = reg_tbl[i].read_mask;
9958 write_mask = reg_tbl[i].write_mask;
9959
9960 /* Save the original register content */
9961 save_val = tr32(offset);
9962
9963 /* Determine the read-only value. */
9964 read_val = save_val & read_mask;
9965
9966 /* Write zero to the register, then make sure the read-only bits
9967 * are not changed and the read/write bits are all zeros.
9968 */
9969 tw32(offset, 0);
9970
9971 val = tr32(offset);
9972
9973 /* Test the read-only and read/write bits. */
9974 if (((val & read_mask) != read_val) || (val & write_mask))
9975 goto out;
9976
9977 /* Write ones to all the bits defined by RdMask and WrMask, then
9978 * make sure the read-only bits are not changed and the
9979 * read/write bits are all ones.
9980 */
9981 tw32(offset, read_mask | write_mask);
9982
9983 val = tr32(offset);
9984
9985 /* Test the read-only bits. */
9986 if ((val & read_mask) != read_val)
9987 goto out;
9988
9989 /* Test the read/write bits. */
9990 if ((val & write_mask) != write_mask)
9991 goto out;
9992
9993 tw32(offset, save_val);
9994 }
9995
9996 return 0;
9997
9998out:
9999 if (netif_msg_hw(tp))
10000 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10001 offset);
10002 tw32(offset, save_val);
10003 return -EIO;
10004}
10005
10006static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10007{
10008 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10009 int i;
10010 u32 j;
10011
10012 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10013 for (j = 0; j < len; j += 4) {
10014 u32 val;
10015
10016 tg3_write_mem(tp, offset + j, test_pattern[i]);
10017 tg3_read_mem(tp, offset + j, &val);
10018 if (val != test_pattern[i])
10019 return -EIO;
10020 }
10021 }
10022 return 0;
10023}
10024
10025static int tg3_test_memory(struct tg3 *tp)
10026{
10027 static struct mem_entry {
10028 u32 offset;
10029 u32 len;
10030 } mem_tbl_570x[] = {
10031 { 0x00000000, 0x00b50},
10032 { 0x00002000, 0x1c000},
10033 { 0xffffffff, 0x00000}
10034 }, mem_tbl_5705[] = {
10035 { 0x00000100, 0x0000c},
10036 { 0x00000200, 0x00008},
10037 { 0x00004000, 0x00800},
10038 { 0x00006000, 0x01000},
10039 { 0x00008000, 0x02000},
10040 { 0x00010000, 0x0e000},
10041 { 0xffffffff, 0x00000}
10042 }, mem_tbl_5755[] = {
10043 { 0x00000200, 0x00008},
10044 { 0x00004000, 0x00800},
10045 { 0x00006000, 0x00800},
10046 { 0x00008000, 0x02000},
10047 { 0x00010000, 0x0c000},
10048 { 0xffffffff, 0x00000}
10049 }, mem_tbl_5906[] = {
10050 { 0x00000200, 0x00008},
10051 { 0x00004000, 0x00400},
10052 { 0x00006000, 0x00400},
10053 { 0x00008000, 0x01000},
10054 { 0x00010000, 0x01000},
10055 { 0xffffffff, 0x00000}
10056 };
10057 struct mem_entry *mem_tbl;
10058 int err = 0;
10059 int i;
10060
10061 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10062 mem_tbl = mem_tbl_5755;
10063 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10064 mem_tbl = mem_tbl_5906;
10065 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10066 mem_tbl = mem_tbl_5705;
10067 else
10068 mem_tbl = mem_tbl_570x;
10069
10070 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10071 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10072 mem_tbl[i].len)) != 0)
10073 break;
10074 }
10075
10076 return err;
10077}
10078
10079#define TG3_MAC_LOOPBACK 0
10080#define TG3_PHY_LOOPBACK 1
10081
10082static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10083{
10084 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10085 u32 desc_idx;
10086 struct sk_buff *skb, *rx_skb;
10087 u8 *tx_data;
10088 dma_addr_t map;
10089 int num_pkts, tx_len, rx_len, i, err;
10090 struct tg3_rx_buffer_desc *desc;
10091
10092 if (loopback_mode == TG3_MAC_LOOPBACK) {
10093 /* HW errata - mac loopback fails in some cases on 5780.
10094 * Normal traffic and PHY loopback are not affected by
10095 * errata.
10096 */
10097 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10098 return 0;
10099
10100 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10101 MAC_MODE_PORT_INT_LPBACK;
10102 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10103 mac_mode |= MAC_MODE_LINK_POLARITY;
10104 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10105 mac_mode |= MAC_MODE_PORT_MODE_MII;
10106 else
10107 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10108 tw32(MAC_MODE, mac_mode);
10109 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10110 u32 val;
10111
10112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10113 u32 phytest;
10114
10115 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
10116 u32 phy;
10117
10118 tg3_writephy(tp, MII_TG3_EPHY_TEST,
10119 phytest | MII_TG3_EPHY_SHADOW_EN);
10120 if (!tg3_readphy(tp, 0x1b, &phy))
10121 tg3_writephy(tp, 0x1b, phy & ~0x20);
10122 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
10123 }
10124 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10125 } else
10126 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10127
10128 tg3_phy_toggle_automdix(tp, 0);
10129
10130 tg3_writephy(tp, MII_BMCR, val);
10131 udelay(40);
10132
10133 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10135 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
10136 mac_mode |= MAC_MODE_PORT_MODE_MII;
10137 } else
10138 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10139
10140 /* reset to prevent losing 1st rx packet intermittently */
10141 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10142 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10143 udelay(10);
10144 tw32_f(MAC_RX_MODE, tp->rx_mode);
10145 }
10146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10147 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10148 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10149 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10150 mac_mode |= MAC_MODE_LINK_POLARITY;
10151 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10152 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10153 }
10154 tw32(MAC_MODE, mac_mode);
10155 }
10156 else
10157 return -EINVAL;
10158
10159 err = -EIO;
10160
10161 tx_len = 1514;
10162 skb = netdev_alloc_skb(tp->dev, tx_len);
10163 if (!skb)
10164 return -ENOMEM;
10165
10166 tx_data = skb_put(skb, tx_len);
10167 memcpy(tx_data, tp->dev->dev_addr, 6);
10168 memset(tx_data + 6, 0x0, 8);
10169
10170 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10171
10172 for (i = 14; i < tx_len; i++)
10173 tx_data[i] = (u8) (i & 0xff);
10174
10175 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10176
10177 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10178 HOSTCC_MODE_NOW);
10179
10180 udelay(10);
10181
10182 rx_start_idx = tp->hw_status->idx[0].rx_producer;
10183
10184 num_pkts = 0;
10185
10186 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
10187
10188 tp->tx_prod++;
10189 num_pkts++;
10190
10191 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
10192 tp->tx_prod);
10193 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
10194
10195 udelay(10);
10196
10197 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10198 for (i = 0; i < 25; i++) {
10199 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10200 HOSTCC_MODE_NOW);
10201
10202 udelay(10);
10203
10204 tx_idx = tp->hw_status->idx[0].tx_consumer;
10205 rx_idx = tp->hw_status->idx[0].rx_producer;
10206 if ((tx_idx == tp->tx_prod) &&
10207 (rx_idx == (rx_start_idx + num_pkts)))
10208 break;
10209 }
10210
10211 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10212 dev_kfree_skb(skb);
10213
10214 if (tx_idx != tp->tx_prod)
10215 goto out;
10216
10217 if (rx_idx != rx_start_idx + num_pkts)
10218 goto out;
10219
10220 desc = &tp->rx_rcb[rx_start_idx];
10221 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10222 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10223 if (opaque_key != RXD_OPAQUE_RING_STD)
10224 goto out;
10225
10226 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10227 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10228 goto out;
10229
10230 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10231 if (rx_len != tx_len)
10232 goto out;
10233
10234 rx_skb = tp->rx_std_buffers[desc_idx].skb;
10235
10236 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
10237 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10238
10239 for (i = 14; i < tx_len; i++) {
10240 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10241 goto out;
10242 }
10243 err = 0;
10244
10245 /* tg3_free_rings will unmap and free the rx_skb */
10246out:
10247 return err;
10248}
10249
10250#define TG3_MAC_LOOPBACK_FAILED 1
10251#define TG3_PHY_LOOPBACK_FAILED 2
10252#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10253 TG3_PHY_LOOPBACK_FAILED)
10254
10255static int tg3_test_loopback(struct tg3 *tp)
10256{
10257 int err = 0;
10258 u32 cpmuctrl = 0;
10259
10260 if (!netif_running(tp->dev))
10261 return TG3_LOOPBACK_FAILED;
10262
10263 err = tg3_reset_hw(tp, 1);
10264 if (err)
10265 return TG3_LOOPBACK_FAILED;
10266
10267 /* Turn off gphy autopowerdown. */
10268 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10269 tg3_phy_toggle_apd(tp, false);
10270
10271 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10272 int i;
10273 u32 status;
10274
10275 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10276
10277 /* Wait for up to 40 microseconds to acquire lock. */
10278 for (i = 0; i < 4; i++) {
10279 status = tr32(TG3_CPMU_MUTEX_GNT);
10280 if (status == CPMU_MUTEX_GNT_DRIVER)
10281 break;
10282 udelay(10);
10283 }
10284
10285 if (status != CPMU_MUTEX_GNT_DRIVER)
10286 return TG3_LOOPBACK_FAILED;
10287
10288 /* Turn off link-based power management. */
10289 cpmuctrl = tr32(TG3_CPMU_CTRL);
10290 tw32(TG3_CPMU_CTRL,
10291 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10292 CPMU_CTRL_LINK_AWARE_MODE));
10293 }
10294
10295 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10296 err |= TG3_MAC_LOOPBACK_FAILED;
10297
10298 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10299 tw32(TG3_CPMU_CTRL, cpmuctrl);
10300
10301 /* Release the mutex */
10302 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10303 }
10304
10305 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10306 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10307 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10308 err |= TG3_PHY_LOOPBACK_FAILED;
10309 }
10310
10311 /* Re-enable gphy autopowerdown. */
10312 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10313 tg3_phy_toggle_apd(tp, true);
10314
10315 return err;
10316}
10317
10318static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10319 u64 *data)
10320{
10321 struct tg3 *tp = netdev_priv(dev);
10322
10323 if (tp->link_config.phy_is_low_power)
10324 tg3_set_power_state(tp, PCI_D0);
10325
10326 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10327
10328 if (tg3_test_nvram(tp) != 0) {
10329 etest->flags |= ETH_TEST_FL_FAILED;
10330 data[0] = 1;
10331 }
10332 if (tg3_test_link(tp) != 0) {
10333 etest->flags |= ETH_TEST_FL_FAILED;
10334 data[1] = 1;
10335 }
10336 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10337 int err, err2 = 0, irq_sync = 0;
10338
10339 if (netif_running(dev)) {
10340 tg3_phy_stop(tp);
10341 tg3_netif_stop(tp);
10342 irq_sync = 1;
10343 }
10344
10345 tg3_full_lock(tp, irq_sync);
10346
10347 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10348 err = tg3_nvram_lock(tp);
10349 tg3_halt_cpu(tp, RX_CPU_BASE);
10350 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10351 tg3_halt_cpu(tp, TX_CPU_BASE);
10352 if (!err)
10353 tg3_nvram_unlock(tp);
10354
10355 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10356 tg3_phy_reset(tp);
10357
10358 if (tg3_test_registers(tp) != 0) {
10359 etest->flags |= ETH_TEST_FL_FAILED;
10360 data[2] = 1;
10361 }
10362 if (tg3_test_memory(tp) != 0) {
10363 etest->flags |= ETH_TEST_FL_FAILED;
10364 data[3] = 1;
10365 }
10366 if ((data[4] = tg3_test_loopback(tp)) != 0)
10367 etest->flags |= ETH_TEST_FL_FAILED;
10368
10369 tg3_full_unlock(tp);
10370
10371 if (tg3_test_interrupt(tp) != 0) {
10372 etest->flags |= ETH_TEST_FL_FAILED;
10373 data[5] = 1;
10374 }
10375
10376 tg3_full_lock(tp, 0);
10377
10378 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10379 if (netif_running(dev)) {
10380 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10381 err2 = tg3_restart_hw(tp, 1);
10382 if (!err2)
10383 tg3_netif_start(tp);
10384 }
10385
10386 tg3_full_unlock(tp);
10387
10388 if (irq_sync && !err2)
10389 tg3_phy_start(tp);
10390 }
10391 if (tp->link_config.phy_is_low_power)
10392 tg3_set_power_state(tp, PCI_D3hot);
10393
10394}
10395
10396static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10397{
10398 struct mii_ioctl_data *data = if_mii(ifr);
10399 struct tg3 *tp = netdev_priv(dev);
10400 int err;
10401
10402 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10403 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10404 return -EAGAIN;
10405 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10406 }
10407
10408 switch(cmd) {
10409 case SIOCGMIIPHY:
10410 data->phy_id = PHY_ADDR;
10411
10412 /* fallthru */
10413 case SIOCGMIIREG: {
10414 u32 mii_regval;
10415
10416 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10417 break; /* We have no PHY */
10418
10419 if (tp->link_config.phy_is_low_power)
10420 return -EAGAIN;
10421
10422 spin_lock_bh(&tp->lock);
10423 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10424 spin_unlock_bh(&tp->lock);
10425
10426 data->val_out = mii_regval;
10427
10428 return err;
10429 }
10430
10431 case SIOCSMIIREG:
10432 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10433 break; /* We have no PHY */
10434
10435 if (!capable(CAP_NET_ADMIN))
10436 return -EPERM;
10437
10438 if (tp->link_config.phy_is_low_power)
10439 return -EAGAIN;
10440
10441 spin_lock_bh(&tp->lock);
10442 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10443 spin_unlock_bh(&tp->lock);
10444
10445 return err;
10446
10447 default:
10448 /* do nothing */
10449 break;
10450 }
10451 return -EOPNOTSUPP;
10452}
10453
10454#if TG3_VLAN_TAG_USED
10455static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10456{
10457 struct tg3 *tp = netdev_priv(dev);
10458
10459 if (netif_running(dev))
10460 tg3_netif_stop(tp);
10461
10462 tg3_full_lock(tp, 0);
10463
10464 tp->vlgrp = grp;
10465
10466 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10467 __tg3_set_rx_mode(dev);
10468
10469 if (netif_running(dev))
10470 tg3_netif_start(tp);
10471
10472 tg3_full_unlock(tp);
10473}
10474#endif
10475
10476static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10477{
10478 struct tg3 *tp = netdev_priv(dev);
10479
10480 memcpy(ec, &tp->coal, sizeof(*ec));
10481 return 0;
10482}
10483
10484static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10485{
10486 struct tg3 *tp = netdev_priv(dev);
10487 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10488 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10489
10490 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10491 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10492 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10493 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10494 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10495 }
10496
10497 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10498 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10499 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10500 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10501 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10502 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10503 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10504 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10505 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10506 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10507 return -EINVAL;
10508
10509 /* No rx interrupts will be generated if both are zero */
10510 if ((ec->rx_coalesce_usecs == 0) &&
10511 (ec->rx_max_coalesced_frames == 0))
10512 return -EINVAL;
10513
10514 /* No tx interrupts will be generated if both are zero */
10515 if ((ec->tx_coalesce_usecs == 0) &&
10516 (ec->tx_max_coalesced_frames == 0))
10517 return -EINVAL;
10518
10519 /* Only copy relevant parameters, ignore all others. */
10520 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10521 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10522 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10523 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10524 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10525 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10526 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10527 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10528 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10529
10530 if (netif_running(dev)) {
10531 tg3_full_lock(tp, 0);
10532 __tg3_set_coalesce(tp, &tp->coal);
10533 tg3_full_unlock(tp);
10534 }
10535 return 0;
10536}
10537
10538static const struct ethtool_ops tg3_ethtool_ops = {
10539 .get_settings = tg3_get_settings,
10540 .set_settings = tg3_set_settings,
10541 .get_drvinfo = tg3_get_drvinfo,
10542 .get_regs_len = tg3_get_regs_len,
10543 .get_regs = tg3_get_regs,
10544 .get_wol = tg3_get_wol,
10545 .set_wol = tg3_set_wol,
10546 .get_msglevel = tg3_get_msglevel,
10547 .set_msglevel = tg3_set_msglevel,
10548 .nway_reset = tg3_nway_reset,
10549 .get_link = ethtool_op_get_link,
10550 .get_eeprom_len = tg3_get_eeprom_len,
10551 .get_eeprom = tg3_get_eeprom,
10552 .set_eeprom = tg3_set_eeprom,
10553 .get_ringparam = tg3_get_ringparam,
10554 .set_ringparam = tg3_set_ringparam,
10555 .get_pauseparam = tg3_get_pauseparam,
10556 .set_pauseparam = tg3_set_pauseparam,
10557 .get_rx_csum = tg3_get_rx_csum,
10558 .set_rx_csum = tg3_set_rx_csum,
10559 .set_tx_csum = tg3_set_tx_csum,
10560 .set_sg = ethtool_op_set_sg,
10561 .set_tso = tg3_set_tso,
10562 .self_test = tg3_self_test,
10563 .get_strings = tg3_get_strings,
10564 .phys_id = tg3_phys_id,
10565 .get_ethtool_stats = tg3_get_ethtool_stats,
10566 .get_coalesce = tg3_get_coalesce,
10567 .set_coalesce = tg3_set_coalesce,
10568 .get_sset_count = tg3_get_sset_count,
10569};
10570
10571static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10572{
10573 u32 cursize, val, magic;
10574
10575 tp->nvram_size = EEPROM_CHIP_SIZE;
10576
10577 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
10578 return;
10579
10580 if ((magic != TG3_EEPROM_MAGIC) &&
10581 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10582 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10583 return;
10584
10585 /*
10586 * Size the chip by reading offsets at increasing powers of two.
10587 * When we encounter our validation signature, we know the addressing
10588 * has wrapped around, and thus have our chip size.
10589 */
10590 cursize = 0x10;
10591
10592 while (cursize < tp->nvram_size) {
10593 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
10594 return;
10595
10596 if (val == magic)
10597 break;
10598
10599 cursize <<= 1;
10600 }
10601
10602 tp->nvram_size = cursize;
10603}
10604
10605static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10606{
10607 u32 val;
10608
10609 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
10610 return;
10611
10612 /* Selfboot format */
10613 if (val != TG3_EEPROM_MAGIC) {
10614 tg3_get_eeprom_size(tp);
10615 return;
10616 }
10617
10618 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10619 if (val != 0) {
10620 tp->nvram_size = (val >> 16) * 1024;
10621 return;
10622 }
10623 }
10624 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10625}
10626
10627static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10628{
10629 u32 nvcfg1;
10630
10631 nvcfg1 = tr32(NVRAM_CFG1);
10632 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10633 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10634 }
10635 else {
10636 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10637 tw32(NVRAM_CFG1, nvcfg1);
10638 }
10639
10640 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10641 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10642 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10643 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10644 tp->nvram_jedecnum = JEDEC_ATMEL;
10645 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10646 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10647 break;
10648 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10649 tp->nvram_jedecnum = JEDEC_ATMEL;
10650 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10651 break;
10652 case FLASH_VENDOR_ATMEL_EEPROM:
10653 tp->nvram_jedecnum = JEDEC_ATMEL;
10654 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10655 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10656 break;
10657 case FLASH_VENDOR_ST:
10658 tp->nvram_jedecnum = JEDEC_ST;
10659 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10660 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10661 break;
10662 case FLASH_VENDOR_SAIFUN:
10663 tp->nvram_jedecnum = JEDEC_SAIFUN;
10664 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10665 break;
10666 case FLASH_VENDOR_SST_SMALL:
10667 case FLASH_VENDOR_SST_LARGE:
10668 tp->nvram_jedecnum = JEDEC_SST;
10669 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10670 break;
10671 }
10672 }
10673 else {
10674 tp->nvram_jedecnum = JEDEC_ATMEL;
10675 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10676 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10677 }
10678}
10679
10680static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10681{
10682 u32 nvcfg1;
10683
10684 nvcfg1 = tr32(NVRAM_CFG1);
10685
10686 /* NVRAM protection for TPM */
10687 if (nvcfg1 & (1 << 27))
10688 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10689
10690 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10691 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10692 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10693 tp->nvram_jedecnum = JEDEC_ATMEL;
10694 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10695 break;
10696 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10697 tp->nvram_jedecnum = JEDEC_ATMEL;
10698 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10699 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10700 break;
10701 case FLASH_5752VENDOR_ST_M45PE10:
10702 case FLASH_5752VENDOR_ST_M45PE20:
10703 case FLASH_5752VENDOR_ST_M45PE40:
10704 tp->nvram_jedecnum = JEDEC_ST;
10705 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10706 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10707 break;
10708 }
10709
10710 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10711 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10712 case FLASH_5752PAGE_SIZE_256:
10713 tp->nvram_pagesize = 256;
10714 break;
10715 case FLASH_5752PAGE_SIZE_512:
10716 tp->nvram_pagesize = 512;
10717 break;
10718 case FLASH_5752PAGE_SIZE_1K:
10719 tp->nvram_pagesize = 1024;
10720 break;
10721 case FLASH_5752PAGE_SIZE_2K:
10722 tp->nvram_pagesize = 2048;
10723 break;
10724 case FLASH_5752PAGE_SIZE_4K:
10725 tp->nvram_pagesize = 4096;
10726 break;
10727 case FLASH_5752PAGE_SIZE_264:
10728 tp->nvram_pagesize = 264;
10729 break;
10730 }
10731 }
10732 else {
10733 /* For eeprom, set pagesize to maximum eeprom size */
10734 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10735
10736 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10737 tw32(NVRAM_CFG1, nvcfg1);
10738 }
10739}
10740
10741static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10742{
10743 u32 nvcfg1, protect = 0;
10744
10745 nvcfg1 = tr32(NVRAM_CFG1);
10746
10747 /* NVRAM protection for TPM */
10748 if (nvcfg1 & (1 << 27)) {
10749 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10750 protect = 1;
10751 }
10752
10753 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10754 switch (nvcfg1) {
10755 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10756 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10757 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10758 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10759 tp->nvram_jedecnum = JEDEC_ATMEL;
10760 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10761 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10762 tp->nvram_pagesize = 264;
10763 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10764 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10765 tp->nvram_size = (protect ? 0x3e200 :
10766 TG3_NVRAM_SIZE_512KB);
10767 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10768 tp->nvram_size = (protect ? 0x1f200 :
10769 TG3_NVRAM_SIZE_256KB);
10770 else
10771 tp->nvram_size = (protect ? 0x1f200 :
10772 TG3_NVRAM_SIZE_128KB);
10773 break;
10774 case FLASH_5752VENDOR_ST_M45PE10:
10775 case FLASH_5752VENDOR_ST_M45PE20:
10776 case FLASH_5752VENDOR_ST_M45PE40:
10777 tp->nvram_jedecnum = JEDEC_ST;
10778 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10779 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10780 tp->nvram_pagesize = 256;
10781 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10782 tp->nvram_size = (protect ?
10783 TG3_NVRAM_SIZE_64KB :
10784 TG3_NVRAM_SIZE_128KB);
10785 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10786 tp->nvram_size = (protect ?
10787 TG3_NVRAM_SIZE_64KB :
10788 TG3_NVRAM_SIZE_256KB);
10789 else
10790 tp->nvram_size = (protect ?
10791 TG3_NVRAM_SIZE_128KB :
10792 TG3_NVRAM_SIZE_512KB);
10793 break;
10794 }
10795}
10796
10797static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10798{
10799 u32 nvcfg1;
10800
10801 nvcfg1 = tr32(NVRAM_CFG1);
10802
10803 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10804 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10805 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10806 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10807 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10808 tp->nvram_jedecnum = JEDEC_ATMEL;
10809 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10810 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10811
10812 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10813 tw32(NVRAM_CFG1, nvcfg1);
10814 break;
10815 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10816 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10817 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10818 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10819 tp->nvram_jedecnum = JEDEC_ATMEL;
10820 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10821 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10822 tp->nvram_pagesize = 264;
10823 break;
10824 case FLASH_5752VENDOR_ST_M45PE10:
10825 case FLASH_5752VENDOR_ST_M45PE20:
10826 case FLASH_5752VENDOR_ST_M45PE40:
10827 tp->nvram_jedecnum = JEDEC_ST;
10828 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10829 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10830 tp->nvram_pagesize = 256;
10831 break;
10832 }
10833}
10834
10835static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10836{
10837 u32 nvcfg1, protect = 0;
10838
10839 nvcfg1 = tr32(NVRAM_CFG1);
10840
10841 /* NVRAM protection for TPM */
10842 if (nvcfg1 & (1 << 27)) {
10843 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10844 protect = 1;
10845 }
10846
10847 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10848 switch (nvcfg1) {
10849 case FLASH_5761VENDOR_ATMEL_ADB021D:
10850 case FLASH_5761VENDOR_ATMEL_ADB041D:
10851 case FLASH_5761VENDOR_ATMEL_ADB081D:
10852 case FLASH_5761VENDOR_ATMEL_ADB161D:
10853 case FLASH_5761VENDOR_ATMEL_MDB021D:
10854 case FLASH_5761VENDOR_ATMEL_MDB041D:
10855 case FLASH_5761VENDOR_ATMEL_MDB081D:
10856 case FLASH_5761VENDOR_ATMEL_MDB161D:
10857 tp->nvram_jedecnum = JEDEC_ATMEL;
10858 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10859 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10860 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10861 tp->nvram_pagesize = 256;
10862 break;
10863 case FLASH_5761VENDOR_ST_A_M45PE20:
10864 case FLASH_5761VENDOR_ST_A_M45PE40:
10865 case FLASH_5761VENDOR_ST_A_M45PE80:
10866 case FLASH_5761VENDOR_ST_A_M45PE16:
10867 case FLASH_5761VENDOR_ST_M_M45PE20:
10868 case FLASH_5761VENDOR_ST_M_M45PE40:
10869 case FLASH_5761VENDOR_ST_M_M45PE80:
10870 case FLASH_5761VENDOR_ST_M_M45PE16:
10871 tp->nvram_jedecnum = JEDEC_ST;
10872 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10873 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10874 tp->nvram_pagesize = 256;
10875 break;
10876 }
10877
10878 if (protect) {
10879 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10880 } else {
10881 switch (nvcfg1) {
10882 case FLASH_5761VENDOR_ATMEL_ADB161D:
10883 case FLASH_5761VENDOR_ATMEL_MDB161D:
10884 case FLASH_5761VENDOR_ST_A_M45PE16:
10885 case FLASH_5761VENDOR_ST_M_M45PE16:
10886 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10887 break;
10888 case FLASH_5761VENDOR_ATMEL_ADB081D:
10889 case FLASH_5761VENDOR_ATMEL_MDB081D:
10890 case FLASH_5761VENDOR_ST_A_M45PE80:
10891 case FLASH_5761VENDOR_ST_M_M45PE80:
10892 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10893 break;
10894 case FLASH_5761VENDOR_ATMEL_ADB041D:
10895 case FLASH_5761VENDOR_ATMEL_MDB041D:
10896 case FLASH_5761VENDOR_ST_A_M45PE40:
10897 case FLASH_5761VENDOR_ST_M_M45PE40:
10898 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10899 break;
10900 case FLASH_5761VENDOR_ATMEL_ADB021D:
10901 case FLASH_5761VENDOR_ATMEL_MDB021D:
10902 case FLASH_5761VENDOR_ST_A_M45PE20:
10903 case FLASH_5761VENDOR_ST_M_M45PE20:
10904 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10905 break;
10906 }
10907 }
10908}
10909
10910static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10911{
10912 tp->nvram_jedecnum = JEDEC_ATMEL;
10913 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10914 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10915}
10916
10917static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10918{
10919 u32 nvcfg1;
10920
10921 nvcfg1 = tr32(NVRAM_CFG1);
10922
10923 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10924 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10925 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10926 tp->nvram_jedecnum = JEDEC_ATMEL;
10927 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10928 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10929
10930 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10931 tw32(NVRAM_CFG1, nvcfg1);
10932 return;
10933 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10934 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10935 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10936 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10937 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10938 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10939 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10940 tp->nvram_jedecnum = JEDEC_ATMEL;
10941 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10942 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10943
10944 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10945 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10946 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10947 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10948 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10949 break;
10950 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10951 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10952 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10953 break;
10954 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10955 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10956 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10957 break;
10958 }
10959 break;
10960 case FLASH_5752VENDOR_ST_M45PE10:
10961 case FLASH_5752VENDOR_ST_M45PE20:
10962 case FLASH_5752VENDOR_ST_M45PE40:
10963 tp->nvram_jedecnum = JEDEC_ST;
10964 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10965 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10966
10967 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10968 case FLASH_5752VENDOR_ST_M45PE10:
10969 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10970 break;
10971 case FLASH_5752VENDOR_ST_M45PE20:
10972 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10973 break;
10974 case FLASH_5752VENDOR_ST_M45PE40:
10975 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10976 break;
10977 }
10978 break;
10979 default:
10980 return;
10981 }
10982
10983 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10984 case FLASH_5752PAGE_SIZE_256:
10985 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10986 tp->nvram_pagesize = 256;
10987 break;
10988 case FLASH_5752PAGE_SIZE_512:
10989 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10990 tp->nvram_pagesize = 512;
10991 break;
10992 case FLASH_5752PAGE_SIZE_1K:
10993 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10994 tp->nvram_pagesize = 1024;
10995 break;
10996 case FLASH_5752PAGE_SIZE_2K:
10997 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10998 tp->nvram_pagesize = 2048;
10999 break;
11000 case FLASH_5752PAGE_SIZE_4K:
11001 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11002 tp->nvram_pagesize = 4096;
11003 break;
11004 case FLASH_5752PAGE_SIZE_264:
11005 tp->nvram_pagesize = 264;
11006 break;
11007 case FLASH_5752PAGE_SIZE_528:
11008 tp->nvram_pagesize = 528;
11009 break;
11010 }
11011}
11012
11013/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11014static void __devinit tg3_nvram_init(struct tg3 *tp)
11015{
11016 tw32_f(GRC_EEPROM_ADDR,
11017 (EEPROM_ADDR_FSM_RESET |
11018 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11019 EEPROM_ADDR_CLKPERD_SHIFT)));
11020
11021 msleep(1);
11022
11023 /* Enable seeprom accesses. */
11024 tw32_f(GRC_LOCAL_CTRL,
11025 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11026 udelay(100);
11027
11028 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11029 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11030 tp->tg3_flags |= TG3_FLAG_NVRAM;
11031
11032 if (tg3_nvram_lock(tp)) {
11033 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11034 "tg3_nvram_init failed.\n", tp->dev->name);
11035 return;
11036 }
11037 tg3_enable_nvram_access(tp);
11038
11039 tp->nvram_size = 0;
11040
11041 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11042 tg3_get_5752_nvram_info(tp);
11043 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11044 tg3_get_5755_nvram_info(tp);
11045 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11048 tg3_get_5787_nvram_info(tp);
11049 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11050 tg3_get_5761_nvram_info(tp);
11051 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11052 tg3_get_5906_nvram_info(tp);
11053 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11054 tg3_get_57780_nvram_info(tp);
11055 else
11056 tg3_get_nvram_info(tp);
11057
11058 if (tp->nvram_size == 0)
11059 tg3_get_nvram_size(tp);
11060
11061 tg3_disable_nvram_access(tp);
11062 tg3_nvram_unlock(tp);
11063
11064 } else {
11065 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11066
11067 tg3_get_eeprom_size(tp);
11068 }
11069}
11070
11071static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
11072 u32 offset, u32 *val)
11073{
11074 u32 tmp;
11075 int i;
11076
11077 if (offset > EEPROM_ADDR_ADDR_MASK ||
11078 (offset % 4) != 0)
11079 return -EINVAL;
11080
11081 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
11082 EEPROM_ADDR_DEVID_MASK |
11083 EEPROM_ADDR_READ);
11084 tw32(GRC_EEPROM_ADDR,
11085 tmp |
11086 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11087 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
11088 EEPROM_ADDR_ADDR_MASK) |
11089 EEPROM_ADDR_READ | EEPROM_ADDR_START);
11090
11091 for (i = 0; i < 1000; i++) {
11092 tmp = tr32(GRC_EEPROM_ADDR);
11093
11094 if (tmp & EEPROM_ADDR_COMPLETE)
11095 break;
11096 msleep(1);
11097 }
11098 if (!(tmp & EEPROM_ADDR_COMPLETE))
11099 return -EBUSY;
11100
11101 *val = tr32(GRC_EEPROM_DATA);
11102 return 0;
11103}
11104
11105#define NVRAM_CMD_TIMEOUT 10000
11106
11107static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
11108{
11109 int i;
11110
11111 tw32(NVRAM_CMD, nvram_cmd);
11112 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
11113 udelay(10);
11114 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
11115 udelay(10);
11116 break;
11117 }
11118 }
11119 if (i == NVRAM_CMD_TIMEOUT) {
11120 return -EBUSY;
11121 }
11122 return 0;
11123}
11124
11125static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
11126{
11127 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
11128 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
11129 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
11130 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
11131 (tp->nvram_jedecnum == JEDEC_ATMEL))
11132
11133 addr = ((addr / tp->nvram_pagesize) <<
11134 ATMEL_AT45DB0X1B_PAGE_POS) +
11135 (addr % tp->nvram_pagesize);
11136
11137 return addr;
11138}
11139
11140static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
11141{
11142 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
11143 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
11144 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
11145 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
11146 (tp->nvram_jedecnum == JEDEC_ATMEL))
11147
11148 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
11149 tp->nvram_pagesize) +
11150 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
11151
11152 return addr;
11153}
11154
11155static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
11156{
11157 int ret;
11158
11159 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
11160 return tg3_nvram_read_using_eeprom(tp, offset, val);
11161
11162 offset = tg3_nvram_phys_addr(tp, offset);
11163
11164 if (offset > NVRAM_ADDR_MSK)
11165 return -EINVAL;
11166
11167 ret = tg3_nvram_lock(tp);
11168 if (ret)
11169 return ret;
11170
11171 tg3_enable_nvram_access(tp);
11172
11173 tw32(NVRAM_ADDR, offset);
11174 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
11175 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
11176
11177 if (ret == 0)
11178 *val = swab32(tr32(NVRAM_RDDATA));
11179
11180 tg3_disable_nvram_access(tp);
11181
11182 tg3_nvram_unlock(tp);
11183
11184 return ret;
11185}
11186
11187static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
11188{
11189 u32 v;
11190 int res = tg3_nvram_read(tp, offset, &v);
11191 if (!res)
11192 *val = cpu_to_le32(v);
11193 return res;
11194}
11195
11196static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
11197{
11198 int err;
11199 u32 tmp;
11200
11201 err = tg3_nvram_read(tp, offset, &tmp);
11202 *val = swab32(tmp);
11203 return err;
11204}
11205
11206static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11207 u32 offset, u32 len, u8 *buf)
11208{
11209 int i, j, rc = 0;
11210 u32 val;
11211
11212 for (i = 0; i < len; i += 4) {
11213 u32 addr;
11214 __le32 data;
11215
11216 addr = offset + i;
11217
11218 memcpy(&data, buf + i, 4);
11219
11220 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
11221
11222 val = tr32(GRC_EEPROM_ADDR);
11223 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11224
11225 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11226 EEPROM_ADDR_READ);
11227 tw32(GRC_EEPROM_ADDR, val |
11228 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11229 (addr & EEPROM_ADDR_ADDR_MASK) |
11230 EEPROM_ADDR_START |
11231 EEPROM_ADDR_WRITE);
11232
11233 for (j = 0; j < 1000; j++) {
11234 val = tr32(GRC_EEPROM_ADDR);
11235
11236 if (val & EEPROM_ADDR_COMPLETE)
11237 break;
11238 msleep(1);
11239 }
11240 if (!(val & EEPROM_ADDR_COMPLETE)) {
11241 rc = -EBUSY;
11242 break;
11243 }
11244 }
11245
11246 return rc;
11247}
11248
11249/* offset and length are dword aligned */
11250static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11251 u8 *buf)
11252{
11253 int ret = 0;
11254 u32 pagesize = tp->nvram_pagesize;
11255 u32 pagemask = pagesize - 1;
11256 u32 nvram_cmd;
11257 u8 *tmp;
11258
11259 tmp = kmalloc(pagesize, GFP_KERNEL);
11260 if (tmp == NULL)
11261 return -ENOMEM;
11262
11263 while (len) {
11264 int j;
11265 u32 phy_addr, page_off, size;
11266
11267 phy_addr = offset & ~pagemask;
11268
11269 for (j = 0; j < pagesize; j += 4) {
11270 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
11271 (__le32 *) (tmp + j))))
11272 break;
11273 }
11274 if (ret)
11275 break;
11276
11277 page_off = offset & pagemask;
11278 size = pagesize;
11279 if (len < size)
11280 size = len;
11281
11282 len -= size;
11283
11284 memcpy(tmp + page_off, buf, size);
11285
11286 offset = offset + (pagesize - page_off);
11287
11288 tg3_enable_nvram_access(tp);
11289
11290 /*
11291 * Before we can erase the flash page, we need
11292 * to issue a special "write enable" command.
11293 */
11294 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11295
11296 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11297 break;
11298
11299 /* Erase the target page */
11300 tw32(NVRAM_ADDR, phy_addr);
11301
11302 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11303 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11304
11305 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11306 break;
11307
11308 /* Issue another write enable to start the write. */
11309 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11310
11311 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11312 break;
11313
11314 for (j = 0; j < pagesize; j += 4) {
11315 __be32 data;
11316
11317 data = *((__be32 *) (tmp + j));
11318 /* swab32(le32_to_cpu(data)), actually */
11319 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11320
11321 tw32(NVRAM_ADDR, phy_addr + j);
11322
11323 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11324 NVRAM_CMD_WR;
11325
11326 if (j == 0)
11327 nvram_cmd |= NVRAM_CMD_FIRST;
11328 else if (j == (pagesize - 4))
11329 nvram_cmd |= NVRAM_CMD_LAST;
11330
11331 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11332 break;
11333 }
11334 if (ret)
11335 break;
11336 }
11337
11338 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11339 tg3_nvram_exec_cmd(tp, nvram_cmd);
11340
11341 kfree(tmp);
11342
11343 return ret;
11344}
11345
11346/* offset and length are dword aligned */
11347static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11348 u8 *buf)
11349{
11350 int i, ret = 0;
11351
11352 for (i = 0; i < len; i += 4, offset += 4) {
11353 u32 page_off, phy_addr, nvram_cmd;
11354 __be32 data;
11355
11356 memcpy(&data, buf + i, 4);
11357 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11358
11359 page_off = offset % tp->nvram_pagesize;
11360
11361 phy_addr = tg3_nvram_phys_addr(tp, offset);
11362
11363 tw32(NVRAM_ADDR, phy_addr);
11364
11365 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11366
11367 if ((page_off == 0) || (i == 0))
11368 nvram_cmd |= NVRAM_CMD_FIRST;
11369 if (page_off == (tp->nvram_pagesize - 4))
11370 nvram_cmd |= NVRAM_CMD_LAST;
11371
11372 if (i == (len - 4))
11373 nvram_cmd |= NVRAM_CMD_LAST;
11374
11375 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11376 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11377 (tp->nvram_jedecnum == JEDEC_ST) &&
11378 (nvram_cmd & NVRAM_CMD_FIRST)) {
11379
11380 if ((ret = tg3_nvram_exec_cmd(tp,
11381 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11382 NVRAM_CMD_DONE)))
11383
11384 break;
11385 }
11386 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11387 /* We always do complete word writes to eeprom. */
11388 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11389 }
11390
11391 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11392 break;
11393 }
11394 return ret;
11395}
11396
11397/* offset and length are dword aligned */
11398static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11399{
11400 int ret;
11401
11402 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11403 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11404 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11405 udelay(40);
11406 }
11407
11408 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11409 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11410 }
11411 else {
11412 u32 grc_mode;
11413
11414 ret = tg3_nvram_lock(tp);
11415 if (ret)
11416 return ret;
11417
11418 tg3_enable_nvram_access(tp);
11419 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11420 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11421 tw32(NVRAM_WRITE1, 0x406);
11422
11423 grc_mode = tr32(GRC_MODE);
11424 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11425
11426 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11427 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11428
11429 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11430 buf);
11431 }
11432 else {
11433 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11434 buf);
11435 }
11436
11437 grc_mode = tr32(GRC_MODE);
11438 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11439
11440 tg3_disable_nvram_access(tp);
11441 tg3_nvram_unlock(tp);
11442 }
11443
11444 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11445 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11446 udelay(40);
11447 }
11448
11449 return ret;
11450}
11451
11452struct subsys_tbl_ent {
11453 u16 subsys_vendor, subsys_devid;
11454 u32 phy_id;
11455};
11456
11457static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11458 /* Broadcom boards. */
11459 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11460 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11461 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11462 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11463 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11464 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11465 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11466 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11467 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11468 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11469 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11470
11471 /* 3com boards. */
11472 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11473 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11474 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11475 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11476 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11477
11478 /* DELL boards. */
11479 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11480 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11481 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11482 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11483
11484 /* Compaq boards. */
11485 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11486 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11487 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11488 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11489 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11490
11491 /* IBM boards. */
11492 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11493};
11494
11495static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11496{
11497 int i;
11498
11499 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11500 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11501 tp->pdev->subsystem_vendor) &&
11502 (subsys_id_to_phy_id[i].subsys_devid ==
11503 tp->pdev->subsystem_device))
11504 return &subsys_id_to_phy_id[i];
11505 }
11506 return NULL;
11507}
11508
11509static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11510{
11511 u32 val;
11512 u16 pmcsr;
11513
11514 /* On some early chips the SRAM cannot be accessed in D3hot state,
11515 * so need make sure we're in D0.
11516 */
11517 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11518 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11519 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11520 msleep(1);
11521
11522 /* Make sure register accesses (indirect or otherwise)
11523 * will function correctly.
11524 */
11525 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11526 tp->misc_host_ctrl);
11527
11528 /* The memory arbiter has to be enabled in order for SRAM accesses
11529 * to succeed. Normally on powerup the tg3 chip firmware will make
11530 * sure it is enabled, but other entities such as system netboot
11531 * code might disable it.
11532 */
11533 val = tr32(MEMARB_MODE);
11534 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11535
11536 tp->phy_id = PHY_ID_INVALID;
11537 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11538
11539 /* Assume an onboard device and WOL capable by default. */
11540 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11541
11542 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11543 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11544 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11545 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11546 }
11547 val = tr32(VCPU_CFGSHDW);
11548 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11549 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11550 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11551 (val & VCPU_CFGSHDW_WOL_MAGPKT))
11552 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11553 goto done;
11554 }
11555
11556 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11557 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11558 u32 nic_cfg, led_cfg;
11559 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11560 int eeprom_phy_serdes = 0;
11561
11562 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11563 tp->nic_sram_data_cfg = nic_cfg;
11564
11565 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11566 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11567 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11568 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11569 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11570 (ver > 0) && (ver < 0x100))
11571 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11572
11573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11574 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11575
11576 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11577 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11578 eeprom_phy_serdes = 1;
11579
11580 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11581 if (nic_phy_id != 0) {
11582 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11583 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11584
11585 eeprom_phy_id = (id1 >> 16) << 10;
11586 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11587 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11588 } else
11589 eeprom_phy_id = 0;
11590
11591 tp->phy_id = eeprom_phy_id;
11592 if (eeprom_phy_serdes) {
11593 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11594 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11595 else
11596 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11597 }
11598
11599 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11600 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11601 SHASTA_EXT_LED_MODE_MASK);
11602 else
11603 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11604
11605 switch (led_cfg) {
11606 default:
11607 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11608 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11609 break;
11610
11611 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11612 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11613 break;
11614
11615 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11616 tp->led_ctrl = LED_CTRL_MODE_MAC;
11617
11618 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11619 * read on some older 5700/5701 bootcode.
11620 */
11621 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11622 ASIC_REV_5700 ||
11623 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11624 ASIC_REV_5701)
11625 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11626
11627 break;
11628
11629 case SHASTA_EXT_LED_SHARED:
11630 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11631 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11632 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11633 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11634 LED_CTRL_MODE_PHY_2);
11635 break;
11636
11637 case SHASTA_EXT_LED_MAC:
11638 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11639 break;
11640
11641 case SHASTA_EXT_LED_COMBO:
11642 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11643 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11644 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11645 LED_CTRL_MODE_PHY_2);
11646 break;
11647
11648 }
11649
11650 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11651 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11652 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11653 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11654
11655 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11656 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11657
11658 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11659 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11660 if ((tp->pdev->subsystem_vendor ==
11661 PCI_VENDOR_ID_ARIMA) &&
11662 (tp->pdev->subsystem_device == 0x205a ||
11663 tp->pdev->subsystem_device == 0x2063))
11664 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11665 } else {
11666 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11667 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11668 }
11669
11670 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11671 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11672 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11673 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11674 }
11675
11676 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11677 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11678 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11679
11680 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11681 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11682 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11683
11684 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11685 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11686 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11687
11688 if (cfg2 & (1 << 17))
11689 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11690
11691 /* serdes signal pre-emphasis in register 0x590 set by */
11692 /* bootcode if bit 18 is set */
11693 if (cfg2 & (1 << 18))
11694 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11695
11696 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11697 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11698 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11699 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11700
11701 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11702 u32 cfg3;
11703
11704 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11705 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11706 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11707 }
11708
11709 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11710 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11711 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11712 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11713 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11714 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11715 }
11716done:
11717 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11718 device_set_wakeup_enable(&tp->pdev->dev,
11719 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11720}
11721
11722static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11723{
11724 int i;
11725 u32 val;
11726
11727 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11728 tw32(OTP_CTRL, cmd);
11729
11730 /* Wait for up to 1 ms for command to execute. */
11731 for (i = 0; i < 100; i++) {
11732 val = tr32(OTP_STATUS);
11733 if (val & OTP_STATUS_CMD_DONE)
11734 break;
11735 udelay(10);
11736 }
11737
11738 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11739}
11740
11741/* Read the gphy configuration from the OTP region of the chip. The gphy
11742 * configuration is a 32-bit value that straddles the alignment boundary.
11743 * We do two 32-bit reads and then shift and merge the results.
11744 */
11745static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11746{
11747 u32 bhalf_otp, thalf_otp;
11748
11749 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11750
11751 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11752 return 0;
11753
11754 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11755
11756 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11757 return 0;
11758
11759 thalf_otp = tr32(OTP_READ_DATA);
11760
11761 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11762
11763 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11764 return 0;
11765
11766 bhalf_otp = tr32(OTP_READ_DATA);
11767
11768 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11769}
11770
11771static int __devinit tg3_phy_probe(struct tg3 *tp)
11772{
11773 u32 hw_phy_id_1, hw_phy_id_2;
11774 u32 hw_phy_id, hw_phy_id_masked;
11775 int err;
11776
11777 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11778 return tg3_phy_init(tp);
11779
11780 /* Reading the PHY ID register can conflict with ASF
11781 * firwmare access to the PHY hardware.
11782 */
11783 err = 0;
11784 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11785 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11786 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11787 } else {
11788 /* Now read the physical PHY_ID from the chip and verify
11789 * that it is sane. If it doesn't look good, we fall back
11790 * to either the hard-coded table based PHY_ID and failing
11791 * that the value found in the eeprom area.
11792 */
11793 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11794 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11795
11796 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11797 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11798 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11799
11800 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11801 }
11802
11803 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11804 tp->phy_id = hw_phy_id;
11805 if (hw_phy_id_masked == PHY_ID_BCM8002)
11806 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11807 else
11808 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11809 } else {
11810 if (tp->phy_id != PHY_ID_INVALID) {
11811 /* Do nothing, phy ID already set up in
11812 * tg3_get_eeprom_hw_cfg().
11813 */
11814 } else {
11815 struct subsys_tbl_ent *p;
11816
11817 /* No eeprom signature? Try the hardcoded
11818 * subsys device table.
11819 */
11820 p = lookup_by_subsys(tp);
11821 if (!p)
11822 return -ENODEV;
11823
11824 tp->phy_id = p->phy_id;
11825 if (!tp->phy_id ||
11826 tp->phy_id == PHY_ID_BCM8002)
11827 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11828 }
11829 }
11830
11831 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11832 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11833 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11834 u32 bmsr, adv_reg, tg3_ctrl, mask;
11835
11836 tg3_readphy(tp, MII_BMSR, &bmsr);
11837 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11838 (bmsr & BMSR_LSTATUS))
11839 goto skip_phy_reset;
11840
11841 err = tg3_phy_reset(tp);
11842 if (err)
11843 return err;
11844
11845 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11846 ADVERTISE_100HALF | ADVERTISE_100FULL |
11847 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11848 tg3_ctrl = 0;
11849 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11850 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11851 MII_TG3_CTRL_ADV_1000_FULL);
11852 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11853 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11854 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11855 MII_TG3_CTRL_ENABLE_AS_MASTER);
11856 }
11857
11858 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11859 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11860 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11861 if (!tg3_copper_is_advertising_all(tp, mask)) {
11862 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11863
11864 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11865 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11866
11867 tg3_writephy(tp, MII_BMCR,
11868 BMCR_ANENABLE | BMCR_ANRESTART);
11869 }
11870 tg3_phy_set_wirespeed(tp);
11871
11872 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11873 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11874 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11875 }
11876
11877skip_phy_reset:
11878 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11879 err = tg3_init_5401phy_dsp(tp);
11880 if (err)
11881 return err;
11882 }
11883
11884 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11885 err = tg3_init_5401phy_dsp(tp);
11886 }
11887
11888 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11889 tp->link_config.advertising =
11890 (ADVERTISED_1000baseT_Half |
11891 ADVERTISED_1000baseT_Full |
11892 ADVERTISED_Autoneg |
11893 ADVERTISED_FIBRE);
11894 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11895 tp->link_config.advertising &=
11896 ~(ADVERTISED_1000baseT_Half |
11897 ADVERTISED_1000baseT_Full);
11898
11899 return err;
11900}
11901
11902static void __devinit tg3_read_partno(struct tg3 *tp)
11903{
11904 unsigned char vpd_data[256];
11905 unsigned int i;
11906 u32 magic;
11907
11908 if (tg3_nvram_read_swab(tp, 0x0, &magic))
11909 goto out_not_found;
11910
11911 if (magic == TG3_EEPROM_MAGIC) {
11912 for (i = 0; i < 256; i += 4) {
11913 u32 tmp;
11914
11915 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11916 goto out_not_found;
11917
11918 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
11919 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
11920 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11921 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11922 }
11923 } else {
11924 int vpd_cap;
11925
11926 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11927 for (i = 0; i < 256; i += 4) {
11928 u32 tmp, j = 0;
11929 __le32 v;
11930 u16 tmp16;
11931
11932 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11933 i);
11934 while (j++ < 100) {
11935 pci_read_config_word(tp->pdev, vpd_cap +
11936 PCI_VPD_ADDR, &tmp16);
11937 if (tmp16 & 0x8000)
11938 break;
11939 msleep(1);
11940 }
11941 if (!(tmp16 & 0x8000))
11942 goto out_not_found;
11943
11944 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11945 &tmp);
11946 v = cpu_to_le32(tmp);
11947 memcpy(&vpd_data[i], &v, 4);
11948 }
11949 }
11950
11951 /* Now parse and find the part number. */
11952 for (i = 0; i < 254; ) {
11953 unsigned char val = vpd_data[i];
11954 unsigned int block_end;
11955
11956 if (val == 0x82 || val == 0x91) {
11957 i = (i + 3 +
11958 (vpd_data[i + 1] +
11959 (vpd_data[i + 2] << 8)));
11960 continue;
11961 }
11962
11963 if (val != 0x90)
11964 goto out_not_found;
11965
11966 block_end = (i + 3 +
11967 (vpd_data[i + 1] +
11968 (vpd_data[i + 2] << 8)));
11969 i += 3;
11970
11971 if (block_end > 256)
11972 goto out_not_found;
11973
11974 while (i < (block_end - 2)) {
11975 if (vpd_data[i + 0] == 'P' &&
11976 vpd_data[i + 1] == 'N') {
11977 int partno_len = vpd_data[i + 2];
11978
11979 i += 3;
11980 if (partno_len > 24 || (partno_len + i) > 256)
11981 goto out_not_found;
11982
11983 memcpy(tp->board_part_number,
11984 &vpd_data[i], partno_len);
11985
11986 /* Success. */
11987 return;
11988 }
11989 i += 3 + vpd_data[i + 2];
11990 }
11991
11992 /* Part number not found. */
11993 goto out_not_found;
11994 }
11995
11996out_not_found:
11997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11998 strcpy(tp->board_part_number, "BCM95906");
11999 else
12000 strcpy(tp->board_part_number, "none");
12001}
12002
12003static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12004{
12005 u32 val;
12006
12007 if (tg3_nvram_read_swab(tp, offset, &val) ||
12008 (val & 0xfc000000) != 0x0c000000 ||
12009 tg3_nvram_read_swab(tp, offset + 4, &val) ||
12010 val != 0)
12011 return 0;
12012
12013 return 1;
12014}
12015
12016static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12017{
12018 u32 offset, major, minor, build;
12019
12020 tp->fw_ver[0] = 's';
12021 tp->fw_ver[1] = 'b';
12022 tp->fw_ver[2] = '\0';
12023
12024 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12025 return;
12026
12027 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12028 case TG3_EEPROM_SB_REVISION_0:
12029 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12030 break;
12031 case TG3_EEPROM_SB_REVISION_2:
12032 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12033 break;
12034 case TG3_EEPROM_SB_REVISION_3:
12035 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12036 break;
12037 default:
12038 return;
12039 }
12040
12041 if (tg3_nvram_read_swab(tp, offset, &val))
12042 return;
12043
12044 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12045 TG3_EEPROM_SB_EDH_BLD_SHFT;
12046 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12047 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12048 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12049
12050 if (minor > 99 || build > 26)
12051 return;
12052
12053 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12054
12055 if (build > 0) {
12056 tp->fw_ver[8] = 'a' + build - 1;
12057 tp->fw_ver[9] = '\0';
12058 }
12059}
12060
12061static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12062{
12063 u32 val, offset, start;
12064 u32 ver_offset;
12065 int i, bcnt;
12066
12067 if (tg3_nvram_read_swab(tp, 0, &val))
12068 return;
12069
12070 if (val != TG3_EEPROM_MAGIC) {
12071 if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12072 tg3_read_sb_ver(tp, val);
12073
12074 return;
12075 }
12076
12077 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
12078 tg3_nvram_read_swab(tp, 0x4, &start))
12079 return;
12080
12081 offset = tg3_nvram_logical_addr(tp, offset);
12082
12083 if (!tg3_fw_img_is_valid(tp, offset) ||
12084 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
12085 return;
12086
12087 offset = offset + ver_offset - start;
12088 for (i = 0; i < 16; i += 4) {
12089 __le32 v;
12090 if (tg3_nvram_read_le(tp, offset + i, &v))
12091 return;
12092
12093 memcpy(tp->fw_ver + i, &v, 4);
12094 }
12095
12096 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12097 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12098 return;
12099
12100 for (offset = TG3_NVM_DIR_START;
12101 offset < TG3_NVM_DIR_END;
12102 offset += TG3_NVM_DIRENT_SIZE) {
12103 if (tg3_nvram_read_swab(tp, offset, &val))
12104 return;
12105
12106 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12107 break;
12108 }
12109
12110 if (offset == TG3_NVM_DIR_END)
12111 return;
12112
12113 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12114 start = 0x08000000;
12115 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
12116 return;
12117
12118 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
12119 !tg3_fw_img_is_valid(tp, offset) ||
12120 tg3_nvram_read_swab(tp, offset + 8, &val))
12121 return;
12122
12123 offset += val - start;
12124
12125 bcnt = strlen(tp->fw_ver);
12126
12127 tp->fw_ver[bcnt++] = ',';
12128 tp->fw_ver[bcnt++] = ' ';
12129
12130 for (i = 0; i < 4; i++) {
12131 __le32 v;
12132 if (tg3_nvram_read_le(tp, offset, &v))
12133 return;
12134
12135 offset += sizeof(v);
12136
12137 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
12138 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
12139 break;
12140 }
12141
12142 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
12143 bcnt += sizeof(v);
12144 }
12145
12146 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12147}
12148
12149static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12150
12151static int __devinit tg3_get_invariants(struct tg3 *tp)
12152{
12153 static struct pci_device_id write_reorder_chipsets[] = {
12154 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12155 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12156 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12157 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12158 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12159 PCI_DEVICE_ID_VIA_8385_0) },
12160 { },
12161 };
12162 u32 misc_ctrl_reg;
12163 u32 cacheline_sz_reg;
12164 u32 pci_state_reg, grc_misc_cfg;
12165 u32 val;
12166 u16 pci_cmd;
12167 int err;
12168
12169 /* Force memory write invalidate off. If we leave it on,
12170 * then on 5700_BX chips we have to enable a workaround.
12171 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12172 * to match the cacheline size. The Broadcom driver have this
12173 * workaround but turns MWI off all the times so never uses
12174 * it. This seems to suggest that the workaround is insufficient.
12175 */
12176 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12177 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12178 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12179
12180 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12181 * has the register indirect write enable bit set before
12182 * we try to access any of the MMIO registers. It is also
12183 * critical that the PCI-X hw workaround situation is decided
12184 * before that as well.
12185 */
12186 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12187 &misc_ctrl_reg);
12188
12189 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12190 MISC_HOST_CTRL_CHIPREV_SHIFT);
12191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12192 u32 prod_id_asic_rev;
12193
12194 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12195 &prod_id_asic_rev);
12196 tp->pci_chip_rev_id = prod_id_asic_rev;
12197 }
12198
12199 /* Wrong chip ID in 5752 A0. This code can be removed later
12200 * as A0 is not in production.
12201 */
12202 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12203 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12204
12205 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12206 * we need to disable memory and use config. cycles
12207 * only to access all registers. The 5702/03 chips
12208 * can mistakenly decode the special cycles from the
12209 * ICH chipsets as memory write cycles, causing corruption
12210 * of register and memory space. Only certain ICH bridges
12211 * will drive special cycles with non-zero data during the
12212 * address phase which can fall within the 5703's address
12213 * range. This is not an ICH bug as the PCI spec allows
12214 * non-zero address during special cycles. However, only
12215 * these ICH bridges are known to drive non-zero addresses
12216 * during special cycles.
12217 *
12218 * Since special cycles do not cross PCI bridges, we only
12219 * enable this workaround if the 5703 is on the secondary
12220 * bus of these ICH bridges.
12221 */
12222 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12223 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12224 static struct tg3_dev_id {
12225 u32 vendor;
12226 u32 device;
12227 u32 rev;
12228 } ich_chipsets[] = {
12229 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12230 PCI_ANY_ID },
12231 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12232 PCI_ANY_ID },
12233 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12234 0xa },
12235 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12236 PCI_ANY_ID },
12237 { },
12238 };
12239 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12240 struct pci_dev *bridge = NULL;
12241
12242 while (pci_id->vendor != 0) {
12243 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12244 bridge);
12245 if (!bridge) {
12246 pci_id++;
12247 continue;
12248 }
12249 if (pci_id->rev != PCI_ANY_ID) {
12250 if (bridge->revision > pci_id->rev)
12251 continue;
12252 }
12253 if (bridge->subordinate &&
12254 (bridge->subordinate->number ==
12255 tp->pdev->bus->number)) {
12256
12257 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12258 pci_dev_put(bridge);
12259 break;
12260 }
12261 }
12262 }
12263
12264 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12265 static struct tg3_dev_id {
12266 u32 vendor;
12267 u32 device;
12268 } bridge_chipsets[] = {
12269 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12270 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12271 { },
12272 };
12273 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12274 struct pci_dev *bridge = NULL;
12275
12276 while (pci_id->vendor != 0) {
12277 bridge = pci_get_device(pci_id->vendor,
12278 pci_id->device,
12279 bridge);
12280 if (!bridge) {
12281 pci_id++;
12282 continue;
12283 }
12284 if (bridge->subordinate &&
12285 (bridge->subordinate->number <=
12286 tp->pdev->bus->number) &&
12287 (bridge->subordinate->subordinate >=
12288 tp->pdev->bus->number)) {
12289 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12290 pci_dev_put(bridge);
12291 break;
12292 }
12293 }
12294 }
12295
12296 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12297 * DMA addresses > 40-bit. This bridge may have other additional
12298 * 57xx devices behind it in some 4-port NIC designs for example.
12299 * Any tg3 device found behind the bridge will also need the 40-bit
12300 * DMA workaround.
12301 */
12302 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12303 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12304 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12305 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12306 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12307 }
12308 else {
12309 struct pci_dev *bridge = NULL;
12310
12311 do {
12312 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12313 PCI_DEVICE_ID_SERVERWORKS_EPB,
12314 bridge);
12315 if (bridge && bridge->subordinate &&
12316 (bridge->subordinate->number <=
12317 tp->pdev->bus->number) &&
12318 (bridge->subordinate->subordinate >=
12319 tp->pdev->bus->number)) {
12320 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12321 pci_dev_put(bridge);
12322 break;
12323 }
12324 } while (bridge);
12325 }
12326
12327 /* Initialize misc host control in PCI block. */
12328 tp->misc_host_ctrl |= (misc_ctrl_reg &
12329 MISC_HOST_CTRL_CHIPREV);
12330 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12331 tp->misc_host_ctrl);
12332
12333 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12334 &cacheline_sz_reg);
12335
12336 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
12337 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
12338 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
12339 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
12340
12341 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12342 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12343 tp->pdev_peer = tg3_find_peer(tp);
12344
12345 /* Intentionally exclude ASIC_REV_5906 */
12346 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12347 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12349 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12350 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12352 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12353
12354 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12355 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12356 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12357 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12358 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12359 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12360
12361 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12362 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12363 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12364
12365 /* 5700 B0 chips do not support checksumming correctly due
12366 * to hardware bugs.
12367 */
12368 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12369 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12370 else {
12371 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12372 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12373 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12374 tp->dev->features |= NETIF_F_IPV6_CSUM;
12375 }
12376
12377 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12378 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12379 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12380 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12381 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12382 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12383 tp->pdev_peer == tp->pdev))
12384 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12385
12386 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12387 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12388 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12389 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12390 } else {
12391 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12392 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12393 ASIC_REV_5750 &&
12394 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12395 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12396 }
12397 }
12398
12399 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12400 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12401 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12402
12403 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12404 &pci_state_reg);
12405
12406 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12407 if (tp->pcie_cap != 0) {
12408 u16 lnkctl;
12409
12410 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12411
12412 pcie_set_readrq(tp->pdev, 4096);
12413
12414 pci_read_config_word(tp->pdev,
12415 tp->pcie_cap + PCI_EXP_LNKCTL,
12416 &lnkctl);
12417 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12419 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12420 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12421 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12422 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12423 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12424 }
12425 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12426 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12427 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12428 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12429 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12430 if (!tp->pcix_cap) {
12431 printk(KERN_ERR PFX "Cannot find PCI-X "
12432 "capability, aborting.\n");
12433 return -EIO;
12434 }
12435
12436 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12437 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12438 }
12439
12440 /* If we have an AMD 762 or VIA K8T800 chipset, write
12441 * reordering to the mailbox registers done by the host
12442 * controller can cause major troubles. We read back from
12443 * every mailbox register write to force the writes to be
12444 * posted to the chip in order.
12445 */
12446 if (pci_dev_present(write_reorder_chipsets) &&
12447 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12448 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12449
12450 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12451 tp->pci_lat_timer < 64) {
12452 tp->pci_lat_timer = 64;
12453
12454 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
12455 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
12456 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
12457 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
12458
12459 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12460 cacheline_sz_reg);
12461 }
12462
12463 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12464 /* 5700 BX chips need to have their TX producer index
12465 * mailboxes written twice to workaround a bug.
12466 */
12467 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12468
12469 /* If we are in PCI-X mode, enable register write workaround.
12470 *
12471 * The workaround is to use indirect register accesses
12472 * for all chip writes not to mailbox registers.
12473 */
12474 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12475 u32 pm_reg;
12476
12477 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12478
12479 /* The chip can have it's power management PCI config
12480 * space registers clobbered due to this bug.
12481 * So explicitly force the chip into D0 here.
12482 */
12483 pci_read_config_dword(tp->pdev,
12484 tp->pm_cap + PCI_PM_CTRL,
12485 &pm_reg);
12486 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12487 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12488 pci_write_config_dword(tp->pdev,
12489 tp->pm_cap + PCI_PM_CTRL,
12490 pm_reg);
12491
12492 /* Also, force SERR#/PERR# in PCI command. */
12493 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12494 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12495 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12496 }
12497 }
12498
12499 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12500 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12501 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12502 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12503
12504 /* Chip-specific fixup from Broadcom driver */
12505 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12506 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12507 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12508 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12509 }
12510
12511 /* Default fast path register access methods */
12512 tp->read32 = tg3_read32;
12513 tp->write32 = tg3_write32;
12514 tp->read32_mbox = tg3_read32;
12515 tp->write32_mbox = tg3_write32;
12516 tp->write32_tx_mbox = tg3_write32;
12517 tp->write32_rx_mbox = tg3_write32;
12518
12519 /* Various workaround register access methods */
12520 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12521 tp->write32 = tg3_write_indirect_reg32;
12522 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12523 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12524 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12525 /*
12526 * Back to back register writes can cause problems on these
12527 * chips, the workaround is to read back all reg writes
12528 * except those to mailbox regs.
12529 *
12530 * See tg3_write_indirect_reg32().
12531 */
12532 tp->write32 = tg3_write_flush_reg32;
12533 }
12534
12535
12536 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12537 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12538 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12539 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12540 tp->write32_rx_mbox = tg3_write_flush_reg32;
12541 }
12542
12543 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12544 tp->read32 = tg3_read_indirect_reg32;
12545 tp->write32 = tg3_write_indirect_reg32;
12546 tp->read32_mbox = tg3_read_indirect_mbox;
12547 tp->write32_mbox = tg3_write_indirect_mbox;
12548 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12549 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12550
12551 iounmap(tp->regs);
12552 tp->regs = NULL;
12553
12554 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12555 pci_cmd &= ~PCI_COMMAND_MEMORY;
12556 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12557 }
12558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12559 tp->read32_mbox = tg3_read32_mbox_5906;
12560 tp->write32_mbox = tg3_write32_mbox_5906;
12561 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12562 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12563 }
12564
12565 if (tp->write32 == tg3_write_indirect_reg32 ||
12566 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12567 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12568 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12569 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12570
12571 /* Get eeprom hw config before calling tg3_set_power_state().
12572 * In particular, the TG3_FLG2_IS_NIC flag must be
12573 * determined before calling tg3_set_power_state() so that
12574 * we know whether or not to switch out of Vaux power.
12575 * When the flag is set, it means that GPIO1 is used for eeprom
12576 * write protect and also implies that it is a LOM where GPIOs
12577 * are not used to switch power.
12578 */
12579 tg3_get_eeprom_hw_cfg(tp);
12580
12581 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12582 /* Allow reads and writes to the
12583 * APE register and memory space.
12584 */
12585 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12586 PCISTATE_ALLOW_APE_SHMEM_WR;
12587 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12588 pci_state_reg);
12589 }
12590
12591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12592 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12593 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12594 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12595 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12596
12597 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12598 * GPIO1 driven high will bring 5700's external PHY out of reset.
12599 * It is also used as eeprom write protect on LOMs.
12600 */
12601 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12602 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12603 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12604 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12605 GRC_LCLCTRL_GPIO_OUTPUT1);
12606 /* Unused GPIO3 must be driven as output on 5752 because there
12607 * are no pull-up resistors on unused GPIO pins.
12608 */
12609 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12610 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12611
12612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12613 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12614 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12615
12616 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12617 /* Turn off the debug UART. */
12618 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12619 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12620 /* Keep VMain power. */
12621 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12622 GRC_LCLCTRL_GPIO_OUTPUT0;
12623 }
12624
12625 /* Force the chip into D0. */
12626 err = tg3_set_power_state(tp, PCI_D0);
12627 if (err) {
12628 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12629 pci_name(tp->pdev));
12630 return err;
12631 }
12632
12633 /* Derive initial jumbo mode from MTU assigned in
12634 * ether_setup() via the alloc_etherdev() call
12635 */
12636 if (tp->dev->mtu > ETH_DATA_LEN &&
12637 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12638 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12639
12640 /* Determine WakeOnLan speed to use. */
12641 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12642 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12643 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12644 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12645 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12646 } else {
12647 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12648 }
12649
12650 /* A few boards don't want Ethernet@WireSpeed phy feature */
12651 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12652 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12653 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12654 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12655 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12656 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12657 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12658
12659 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12660 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12661 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12662 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12663 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12664
12665 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12666 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12667 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12668 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12670 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12671 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12672 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12673 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12674 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12675 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12676 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12677 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12678 } else
12679 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12680 }
12681
12682 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12683 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12684 tp->phy_otp = tg3_read_otp_phycfg(tp);
12685 if (tp->phy_otp == 0)
12686 tp->phy_otp = TG3_OTP_DEFAULT;
12687 }
12688
12689 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12690 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12691 else
12692 tp->mi_mode = MAC_MI_MODE_BASE;
12693
12694 tp->coalesce_mode = 0;
12695 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12696 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12697 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12698
12699 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12701 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12702
12703 err = tg3_mdio_init(tp);
12704 if (err)
12705 return err;
12706
12707 /* Initialize data/descriptor byte/word swapping. */
12708 val = tr32(GRC_MODE);
12709 val &= GRC_MODE_HOST_STACKUP;
12710 tw32(GRC_MODE, val | tp->grc_mode);
12711
12712 tg3_switch_clocks(tp);
12713
12714 /* Clear this out for sanity. */
12715 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12716
12717 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12718 &pci_state_reg);
12719 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12720 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12721 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12722
12723 if (chiprevid == CHIPREV_ID_5701_A0 ||
12724 chiprevid == CHIPREV_ID_5701_B0 ||
12725 chiprevid == CHIPREV_ID_5701_B2 ||
12726 chiprevid == CHIPREV_ID_5701_B5) {
12727 void __iomem *sram_base;
12728
12729 /* Write some dummy words into the SRAM status block
12730 * area, see if it reads back correctly. If the return
12731 * value is bad, force enable the PCIX workaround.
12732 */
12733 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12734
12735 writel(0x00000000, sram_base);
12736 writel(0x00000000, sram_base + 4);
12737 writel(0xffffffff, sram_base + 4);
12738 if (readl(sram_base) != 0x00000000)
12739 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12740 }
12741 }
12742
12743 udelay(50);
12744 tg3_nvram_init(tp);
12745
12746 grc_misc_cfg = tr32(GRC_MISC_CFG);
12747 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12748
12749 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12750 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12751 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12752 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12753
12754 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12755 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12756 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12757 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12758 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12759 HOSTCC_MODE_CLRTICK_TXBD);
12760
12761 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12762 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12763 tp->misc_host_ctrl);
12764 }
12765
12766 /* Preserve the APE MAC_MODE bits */
12767 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12768 tp->mac_mode = tr32(MAC_MODE) |
12769 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12770 else
12771 tp->mac_mode = TG3_DEF_MAC_MODE;
12772
12773 /* these are limited to 10/100 only */
12774 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12775 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12776 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12777 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12778 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12779 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12780 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12781 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12782 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12783 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12784 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12785 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12786 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12787 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12788
12789 err = tg3_phy_probe(tp);
12790 if (err) {
12791 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12792 pci_name(tp->pdev), err);
12793 /* ... but do not return immediately ... */
12794 tg3_mdio_fini(tp);
12795 }
12796
12797 tg3_read_partno(tp);
12798 tg3_read_fw_ver(tp);
12799
12800 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12801 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12802 } else {
12803 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12804 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12805 else
12806 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12807 }
12808
12809 /* 5700 {AX,BX} chips have a broken status block link
12810 * change bit implementation, so we must use the
12811 * status register in those cases.
12812 */
12813 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12814 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12815 else
12816 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12817
12818 /* The led_ctrl is set during tg3_phy_probe, here we might
12819 * have to force the link status polling mechanism based
12820 * upon subsystem IDs.
12821 */
12822 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12823 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12824 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12825 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12826 TG3_FLAG_USE_LINKCHG_REG);
12827 }
12828
12829 /* For all SERDES we poll the MAC status register. */
12830 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12831 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12832 else
12833 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12834
12835 tp->rx_offset = NET_IP_ALIGN;
12836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12837 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12838 tp->rx_offset = 0;
12839
12840 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12841
12842 /* Increment the rx prod index on the rx std ring by at most
12843 * 8 for these chips to workaround hw errata.
12844 */
12845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12847 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12848 tp->rx_std_max_post = 8;
12849
12850 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12851 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12852 PCIE_PWR_MGMT_L1_THRESH_MSK;
12853
12854 return err;
12855}
12856
12857#ifdef CONFIG_SPARC
12858static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12859{
12860 struct net_device *dev = tp->dev;
12861 struct pci_dev *pdev = tp->pdev;
12862 struct device_node *dp = pci_device_to_OF_node(pdev);
12863 const unsigned char *addr;
12864 int len;
12865
12866 addr = of_get_property(dp, "local-mac-address", &len);
12867 if (addr && len == 6) {
12868 memcpy(dev->dev_addr, addr, 6);
12869 memcpy(dev->perm_addr, dev->dev_addr, 6);
12870 return 0;
12871 }
12872 return -ENODEV;
12873}
12874
12875static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12876{
12877 struct net_device *dev = tp->dev;
12878
12879 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12880 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12881 return 0;
12882}
12883#endif
12884
12885static int __devinit tg3_get_device_address(struct tg3 *tp)
12886{
12887 struct net_device *dev = tp->dev;
12888 u32 hi, lo, mac_offset;
12889 int addr_ok = 0;
12890
12891#ifdef CONFIG_SPARC
12892 if (!tg3_get_macaddr_sparc(tp))
12893 return 0;
12894#endif
12895
12896 mac_offset = 0x7c;
12897 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12898 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12899 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12900 mac_offset = 0xcc;
12901 if (tg3_nvram_lock(tp))
12902 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12903 else
12904 tg3_nvram_unlock(tp);
12905 }
12906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12907 mac_offset = 0x10;
12908
12909 /* First try to get it from MAC address mailbox. */
12910 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12911 if ((hi >> 16) == 0x484b) {
12912 dev->dev_addr[0] = (hi >> 8) & 0xff;
12913 dev->dev_addr[1] = (hi >> 0) & 0xff;
12914
12915 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12916 dev->dev_addr[2] = (lo >> 24) & 0xff;
12917 dev->dev_addr[3] = (lo >> 16) & 0xff;
12918 dev->dev_addr[4] = (lo >> 8) & 0xff;
12919 dev->dev_addr[5] = (lo >> 0) & 0xff;
12920
12921 /* Some old bootcode may report a 0 MAC address in SRAM */
12922 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12923 }
12924 if (!addr_ok) {
12925 /* Next, try NVRAM. */
12926 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12927 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12928 dev->dev_addr[0] = ((hi >> 16) & 0xff);
12929 dev->dev_addr[1] = ((hi >> 24) & 0xff);
12930 dev->dev_addr[2] = ((lo >> 0) & 0xff);
12931 dev->dev_addr[3] = ((lo >> 8) & 0xff);
12932 dev->dev_addr[4] = ((lo >> 16) & 0xff);
12933 dev->dev_addr[5] = ((lo >> 24) & 0xff);
12934 }
12935 /* Finally just fetch it out of the MAC control regs. */
12936 else {
12937 hi = tr32(MAC_ADDR_0_HIGH);
12938 lo = tr32(MAC_ADDR_0_LOW);
12939
12940 dev->dev_addr[5] = lo & 0xff;
12941 dev->dev_addr[4] = (lo >> 8) & 0xff;
12942 dev->dev_addr[3] = (lo >> 16) & 0xff;
12943 dev->dev_addr[2] = (lo >> 24) & 0xff;
12944 dev->dev_addr[1] = hi & 0xff;
12945 dev->dev_addr[0] = (hi >> 8) & 0xff;
12946 }
12947 }
12948
12949 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12950#ifdef CONFIG_SPARC
12951 if (!tg3_get_default_macaddr_sparc(tp))
12952 return 0;
12953#endif
12954 return -EINVAL;
12955 }
12956 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12957 return 0;
12958}
12959
12960#define BOUNDARY_SINGLE_CACHELINE 1
12961#define BOUNDARY_MULTI_CACHELINE 2
12962
12963static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12964{
12965 int cacheline_size;
12966 u8 byte;
12967 int goal;
12968
12969 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12970 if (byte == 0)
12971 cacheline_size = 1024;
12972 else
12973 cacheline_size = (int) byte * 4;
12974
12975 /* On 5703 and later chips, the boundary bits have no
12976 * effect.
12977 */
12978 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12979 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12980 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12981 goto out;
12982
12983#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12984 goal = BOUNDARY_MULTI_CACHELINE;
12985#else
12986#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12987 goal = BOUNDARY_SINGLE_CACHELINE;
12988#else
12989 goal = 0;
12990#endif
12991#endif
12992
12993 if (!goal)
12994 goto out;
12995
12996 /* PCI controllers on most RISC systems tend to disconnect
12997 * when a device tries to burst across a cache-line boundary.
12998 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12999 *
13000 * Unfortunately, for PCI-E there are only limited
13001 * write-side controls for this, and thus for reads
13002 * we will still get the disconnects. We'll also waste
13003 * these PCI cycles for both read and write for chips
13004 * other than 5700 and 5701 which do not implement the
13005 * boundary bits.
13006 */
13007 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13008 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13009 switch (cacheline_size) {
13010 case 16:
13011 case 32:
13012 case 64:
13013 case 128:
13014 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13015 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13016 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13017 } else {
13018 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13019 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13020 }
13021 break;
13022
13023 case 256:
13024 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13025 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13026 break;
13027
13028 default:
13029 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13030 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13031 break;
13032 }
13033 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13034 switch (cacheline_size) {
13035 case 16:
13036 case 32:
13037 case 64:
13038 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13039 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13040 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13041 break;
13042 }
13043 /* fallthrough */
13044 case 128:
13045 default:
13046 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13047 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13048 break;
13049 }
13050 } else {
13051 switch (cacheline_size) {
13052 case 16:
13053 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13054 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13055 DMA_RWCTRL_WRITE_BNDRY_16);
13056 break;
13057 }
13058 /* fallthrough */
13059 case 32:
13060 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13061 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13062 DMA_RWCTRL_WRITE_BNDRY_32);
13063 break;
13064 }
13065 /* fallthrough */
13066 case 64:
13067 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13068 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13069 DMA_RWCTRL_WRITE_BNDRY_64);
13070 break;
13071 }
13072 /* fallthrough */
13073 case 128:
13074 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13075 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13076 DMA_RWCTRL_WRITE_BNDRY_128);
13077 break;
13078 }
13079 /* fallthrough */
13080 case 256:
13081 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13082 DMA_RWCTRL_WRITE_BNDRY_256);
13083 break;
13084 case 512:
13085 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13086 DMA_RWCTRL_WRITE_BNDRY_512);
13087 break;
13088 case 1024:
13089 default:
13090 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13091 DMA_RWCTRL_WRITE_BNDRY_1024);
13092 break;
13093 }
13094 }
13095
13096out:
13097 return val;
13098}
13099
13100static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13101{
13102 struct tg3_internal_buffer_desc test_desc;
13103 u32 sram_dma_descs;
13104 int i, ret;
13105
13106 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13107
13108 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13109 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13110 tw32(RDMAC_STATUS, 0);
13111 tw32(WDMAC_STATUS, 0);
13112
13113 tw32(BUFMGR_MODE, 0);
13114 tw32(FTQ_RESET, 0);
13115
13116 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13117 test_desc.addr_lo = buf_dma & 0xffffffff;
13118 test_desc.nic_mbuf = 0x00002100;
13119 test_desc.len = size;
13120
13121 /*
13122 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13123 * the *second* time the tg3 driver was getting loaded after an
13124 * initial scan.
13125 *
13126 * Broadcom tells me:
13127 * ...the DMA engine is connected to the GRC block and a DMA
13128 * reset may affect the GRC block in some unpredictable way...
13129 * The behavior of resets to individual blocks has not been tested.
13130 *
13131 * Broadcom noted the GRC reset will also reset all sub-components.
13132 */
13133 if (to_device) {
13134 test_desc.cqid_sqid = (13 << 8) | 2;
13135
13136 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13137 udelay(40);
13138 } else {
13139 test_desc.cqid_sqid = (16 << 8) | 7;
13140
13141 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13142 udelay(40);
13143 }
13144 test_desc.flags = 0x00000005;
13145
13146 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13147 u32 val;
13148
13149 val = *(((u32 *)&test_desc) + i);
13150 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13151 sram_dma_descs + (i * sizeof(u32)));
13152 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13153 }
13154 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13155
13156 if (to_device) {
13157 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13158 } else {
13159 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13160 }
13161
13162 ret = -ENODEV;
13163 for (i = 0; i < 40; i++) {
13164 u32 val;
13165
13166 if (to_device)
13167 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13168 else
13169 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13170 if ((val & 0xffff) == sram_dma_descs) {
13171 ret = 0;
13172 break;
13173 }
13174
13175 udelay(100);
13176 }
13177
13178 return ret;
13179}
13180
13181#define TEST_BUFFER_SIZE 0x2000
13182
13183static int __devinit tg3_test_dma(struct tg3 *tp)
13184{
13185 dma_addr_t buf_dma;
13186 u32 *buf, saved_dma_rwctrl;
13187 int ret;
13188
13189 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13190 if (!buf) {
13191 ret = -ENOMEM;
13192 goto out_nofree;
13193 }
13194
13195 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13196 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13197
13198 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13199
13200 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13201 /* DMA read watermark not used on PCIE */
13202 tp->dma_rwctrl |= 0x00180000;
13203 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13204 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13205 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13206 tp->dma_rwctrl |= 0x003f0000;
13207 else
13208 tp->dma_rwctrl |= 0x003f000f;
13209 } else {
13210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13211 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13212 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13213 u32 read_water = 0x7;
13214
13215 /* If the 5704 is behind the EPB bridge, we can
13216 * do the less restrictive ONE_DMA workaround for
13217 * better performance.
13218 */
13219 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13221 tp->dma_rwctrl |= 0x8000;
13222 else if (ccval == 0x6 || ccval == 0x7)
13223 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13224
13225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13226 read_water = 4;
13227 /* Set bit 23 to enable PCIX hw bug fix */
13228 tp->dma_rwctrl |=
13229 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13230 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13231 (1 << 23);
13232 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13233 /* 5780 always in PCIX mode */
13234 tp->dma_rwctrl |= 0x00144000;
13235 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13236 /* 5714 always in PCIX mode */
13237 tp->dma_rwctrl |= 0x00148000;
13238 } else {
13239 tp->dma_rwctrl |= 0x001b000f;
13240 }
13241 }
13242
13243 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13244 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13245 tp->dma_rwctrl &= 0xfffffff0;
13246
13247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13249 /* Remove this if it causes problems for some boards. */
13250 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13251
13252 /* On 5700/5701 chips, we need to set this bit.
13253 * Otherwise the chip will issue cacheline transactions
13254 * to streamable DMA memory with not all the byte
13255 * enables turned on. This is an error on several
13256 * RISC PCI controllers, in particular sparc64.
13257 *
13258 * On 5703/5704 chips, this bit has been reassigned
13259 * a different meaning. In particular, it is used
13260 * on those chips to enable a PCI-X workaround.
13261 */
13262 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13263 }
13264
13265 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13266
13267#if 0
13268 /* Unneeded, already done by tg3_get_invariants. */
13269 tg3_switch_clocks(tp);
13270#endif
13271
13272 ret = 0;
13273 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13274 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13275 goto out;
13276
13277 /* It is best to perform DMA test with maximum write burst size
13278 * to expose the 5700/5701 write DMA bug.
13279 */
13280 saved_dma_rwctrl = tp->dma_rwctrl;
13281 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13282 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13283
13284 while (1) {
13285 u32 *p = buf, i;
13286
13287 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13288 p[i] = i;
13289
13290 /* Send the buffer to the chip. */
13291 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13292 if (ret) {
13293 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13294 break;
13295 }
13296
13297#if 0
13298 /* validate data reached card RAM correctly. */
13299 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13300 u32 val;
13301 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13302 if (le32_to_cpu(val) != p[i]) {
13303 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13304 /* ret = -ENODEV here? */
13305 }
13306 p[i] = 0;
13307 }
13308#endif
13309 /* Now read it back. */
13310 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13311 if (ret) {
13312 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13313
13314 break;
13315 }
13316
13317 /* Verify it. */
13318 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13319 if (p[i] == i)
13320 continue;
13321
13322 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13323 DMA_RWCTRL_WRITE_BNDRY_16) {
13324 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13325 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13326 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13327 break;
13328 } else {
13329 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13330 ret = -ENODEV;
13331 goto out;
13332 }
13333 }
13334
13335 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13336 /* Success. */
13337 ret = 0;
13338 break;
13339 }
13340 }
13341 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13342 DMA_RWCTRL_WRITE_BNDRY_16) {
13343 static struct pci_device_id dma_wait_state_chipsets[] = {
13344 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13345 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13346 { },
13347 };
13348
13349 /* DMA test passed without adjusting DMA boundary,
13350 * now look for chipsets that are known to expose the
13351 * DMA bug without failing the test.
13352 */
13353 if (pci_dev_present(dma_wait_state_chipsets)) {
13354 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13355 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13356 }
13357 else
13358 /* Safe to use the calculated DMA boundary. */
13359 tp->dma_rwctrl = saved_dma_rwctrl;
13360
13361 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13362 }
13363
13364out:
13365 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13366out_nofree:
13367 return ret;
13368}
13369
13370static void __devinit tg3_init_link_config(struct tg3 *tp)
13371{
13372 tp->link_config.advertising =
13373 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13374 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13375 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13376 ADVERTISED_Autoneg | ADVERTISED_MII);
13377 tp->link_config.speed = SPEED_INVALID;
13378 tp->link_config.duplex = DUPLEX_INVALID;
13379 tp->link_config.autoneg = AUTONEG_ENABLE;
13380 tp->link_config.active_speed = SPEED_INVALID;
13381 tp->link_config.active_duplex = DUPLEX_INVALID;
13382 tp->link_config.phy_is_low_power = 0;
13383 tp->link_config.orig_speed = SPEED_INVALID;
13384 tp->link_config.orig_duplex = DUPLEX_INVALID;
13385 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13386}
13387
13388static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13389{
13390 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13391 tp->bufmgr_config.mbuf_read_dma_low_water =
13392 DEFAULT_MB_RDMA_LOW_WATER_5705;
13393 tp->bufmgr_config.mbuf_mac_rx_low_water =
13394 DEFAULT_MB_MACRX_LOW_WATER_5705;
13395 tp->bufmgr_config.mbuf_high_water =
13396 DEFAULT_MB_HIGH_WATER_5705;
13397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13398 tp->bufmgr_config.mbuf_mac_rx_low_water =
13399 DEFAULT_MB_MACRX_LOW_WATER_5906;
13400 tp->bufmgr_config.mbuf_high_water =
13401 DEFAULT_MB_HIGH_WATER_5906;
13402 }
13403
13404 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13405 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13406 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13407 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13408 tp->bufmgr_config.mbuf_high_water_jumbo =
13409 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13410 } else {
13411 tp->bufmgr_config.mbuf_read_dma_low_water =
13412 DEFAULT_MB_RDMA_LOW_WATER;
13413 tp->bufmgr_config.mbuf_mac_rx_low_water =
13414 DEFAULT_MB_MACRX_LOW_WATER;
13415 tp->bufmgr_config.mbuf_high_water =
13416 DEFAULT_MB_HIGH_WATER;
13417
13418 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13419 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13420 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13421 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13422 tp->bufmgr_config.mbuf_high_water_jumbo =
13423 DEFAULT_MB_HIGH_WATER_JUMBO;
13424 }
13425
13426 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13427 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13428}
13429
13430static char * __devinit tg3_phy_string(struct tg3 *tp)
13431{
13432 switch (tp->phy_id & PHY_ID_MASK) {
13433 case PHY_ID_BCM5400: return "5400";
13434 case PHY_ID_BCM5401: return "5401";
13435 case PHY_ID_BCM5411: return "5411";
13436 case PHY_ID_BCM5701: return "5701";
13437 case PHY_ID_BCM5703: return "5703";
13438 case PHY_ID_BCM5704: return "5704";
13439 case PHY_ID_BCM5705: return "5705";
13440 case PHY_ID_BCM5750: return "5750";
13441 case PHY_ID_BCM5752: return "5752";
13442 case PHY_ID_BCM5714: return "5714";
13443 case PHY_ID_BCM5780: return "5780";
13444 case PHY_ID_BCM5755: return "5755";
13445 case PHY_ID_BCM5787: return "5787";
13446 case PHY_ID_BCM5784: return "5784";
13447 case PHY_ID_BCM5756: return "5722/5756";
13448 case PHY_ID_BCM5906: return "5906";
13449 case PHY_ID_BCM5761: return "5761";
13450 case PHY_ID_BCM8002: return "8002/serdes";
13451 case 0: return "serdes";
13452 default: return "unknown";
13453 }
13454}
13455
13456static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13457{
13458 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13459 strcpy(str, "PCI Express");
13460 return str;
13461 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13462 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13463
13464 strcpy(str, "PCIX:");
13465
13466 if ((clock_ctrl == 7) ||
13467 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13468 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13469 strcat(str, "133MHz");
13470 else if (clock_ctrl == 0)
13471 strcat(str, "33MHz");
13472 else if (clock_ctrl == 2)
13473 strcat(str, "50MHz");
13474 else if (clock_ctrl == 4)
13475 strcat(str, "66MHz");
13476 else if (clock_ctrl == 6)
13477 strcat(str, "100MHz");
13478 } else {
13479 strcpy(str, "PCI:");
13480 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13481 strcat(str, "66MHz");
13482 else
13483 strcat(str, "33MHz");
13484 }
13485 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13486 strcat(str, ":32-bit");
13487 else
13488 strcat(str, ":64-bit");
13489 return str;
13490}
13491
13492static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13493{
13494 struct pci_dev *peer;
13495 unsigned int func, devnr = tp->pdev->devfn & ~7;
13496
13497 for (func = 0; func < 8; func++) {
13498 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13499 if (peer && peer != tp->pdev)
13500 break;
13501 pci_dev_put(peer);
13502 }
13503 /* 5704 can be configured in single-port mode, set peer to
13504 * tp->pdev in that case.
13505 */
13506 if (!peer) {
13507 peer = tp->pdev;
13508 return peer;
13509 }
13510
13511 /*
13512 * We don't need to keep the refcount elevated; there's no way
13513 * to remove one half of this device without removing the other
13514 */
13515 pci_dev_put(peer);
13516
13517 return peer;
13518}
13519
13520static void __devinit tg3_init_coal(struct tg3 *tp)
13521{
13522 struct ethtool_coalesce *ec = &tp->coal;
13523
13524 memset(ec, 0, sizeof(*ec));
13525 ec->cmd = ETHTOOL_GCOALESCE;
13526 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13527 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13528 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13529 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13530 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13531 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13532 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13533 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13534 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13535
13536 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13537 HOSTCC_MODE_CLRTICK_TXBD)) {
13538 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13539 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13540 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13541 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13542 }
13543
13544 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13545 ec->rx_coalesce_usecs_irq = 0;
13546 ec->tx_coalesce_usecs_irq = 0;
13547 ec->stats_block_coalesce_usecs = 0;
13548 }
13549}
13550
13551static const struct net_device_ops tg3_netdev_ops = {
13552 .ndo_open = tg3_open,
13553 .ndo_stop = tg3_close,
13554 .ndo_start_xmit = tg3_start_xmit,
13555 .ndo_get_stats = tg3_get_stats,
13556 .ndo_validate_addr = eth_validate_addr,
13557 .ndo_set_multicast_list = tg3_set_rx_mode,
13558 .ndo_set_mac_address = tg3_set_mac_addr,
13559 .ndo_do_ioctl = tg3_ioctl,
13560 .ndo_tx_timeout = tg3_tx_timeout,
13561 .ndo_change_mtu = tg3_change_mtu,
13562#if TG3_VLAN_TAG_USED
13563 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13564#endif
13565#ifdef CONFIG_NET_POLL_CONTROLLER
13566 .ndo_poll_controller = tg3_poll_controller,
13567#endif
13568};
13569
13570static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13571 .ndo_open = tg3_open,
13572 .ndo_stop = tg3_close,
13573 .ndo_start_xmit = tg3_start_xmit_dma_bug,
13574 .ndo_get_stats = tg3_get_stats,
13575 .ndo_validate_addr = eth_validate_addr,
13576 .ndo_set_multicast_list = tg3_set_rx_mode,
13577 .ndo_set_mac_address = tg3_set_mac_addr,
13578 .ndo_do_ioctl = tg3_ioctl,
13579 .ndo_tx_timeout = tg3_tx_timeout,
13580 .ndo_change_mtu = tg3_change_mtu,
13581#if TG3_VLAN_TAG_USED
13582 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13583#endif
13584#ifdef CONFIG_NET_POLL_CONTROLLER
13585 .ndo_poll_controller = tg3_poll_controller,
13586#endif
13587};
13588
13589static int __devinit tg3_init_one(struct pci_dev *pdev,
13590 const struct pci_device_id *ent)
13591{
13592 static int tg3_version_printed = 0;
13593 struct net_device *dev;
13594 struct tg3 *tp;
13595 int err, pm_cap;
13596 char str[40];
13597 u64 dma_mask, persist_dma_mask;
13598
13599 if (tg3_version_printed++ == 0)
13600 printk(KERN_INFO "%s", version);
13601
13602 err = pci_enable_device(pdev);
13603 if (err) {
13604 printk(KERN_ERR PFX "Cannot enable PCI device, "
13605 "aborting.\n");
13606 return err;
13607 }
13608
13609 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13610 if (err) {
13611 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13612 "aborting.\n");
13613 goto err_out_disable_pdev;
13614 }
13615
13616 pci_set_master(pdev);
13617
13618 /* Find power-management capability. */
13619 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13620 if (pm_cap == 0) {
13621 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13622 "aborting.\n");
13623 err = -EIO;
13624 goto err_out_free_res;
13625 }
13626
13627 dev = alloc_etherdev(sizeof(*tp));
13628 if (!dev) {
13629 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13630 err = -ENOMEM;
13631 goto err_out_free_res;
13632 }
13633
13634 SET_NETDEV_DEV(dev, &pdev->dev);
13635
13636#if TG3_VLAN_TAG_USED
13637 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13638#endif
13639
13640 tp = netdev_priv(dev);
13641 tp->pdev = pdev;
13642 tp->dev = dev;
13643 tp->pm_cap = pm_cap;
13644 tp->rx_mode = TG3_DEF_RX_MODE;
13645 tp->tx_mode = TG3_DEF_TX_MODE;
13646
13647 if (tg3_debug > 0)
13648 tp->msg_enable = tg3_debug;
13649 else
13650 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13651
13652 /* The word/byte swap controls here control register access byte
13653 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13654 * setting below.
13655 */
13656 tp->misc_host_ctrl =
13657 MISC_HOST_CTRL_MASK_PCI_INT |
13658 MISC_HOST_CTRL_WORD_SWAP |
13659 MISC_HOST_CTRL_INDIR_ACCESS |
13660 MISC_HOST_CTRL_PCISTATE_RW;
13661
13662 /* The NONFRM (non-frame) byte/word swap controls take effect
13663 * on descriptor entries, anything which isn't packet data.
13664 *
13665 * The StrongARM chips on the board (one for tx, one for rx)
13666 * are running in big-endian mode.
13667 */
13668 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13669 GRC_MODE_WSWAP_NONFRM_DATA);
13670#ifdef __BIG_ENDIAN
13671 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13672#endif
13673 spin_lock_init(&tp->lock);
13674 spin_lock_init(&tp->indirect_lock);
13675 INIT_WORK(&tp->reset_task, tg3_reset_task);
13676
13677 tp->regs = pci_ioremap_bar(pdev, BAR_0);
13678 if (!tp->regs) {
13679 printk(KERN_ERR PFX "Cannot map device registers, "
13680 "aborting.\n");
13681 err = -ENOMEM;
13682 goto err_out_free_dev;
13683 }
13684
13685 tg3_init_link_config(tp);
13686
13687 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13688 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13689 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13690
13691 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13692 dev->ethtool_ops = &tg3_ethtool_ops;
13693 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13694 dev->irq = pdev->irq;
13695
13696 err = tg3_get_invariants(tp);
13697 if (err) {
13698 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13699 "aborting.\n");
13700 goto err_out_iounmap;
13701 }
13702
13703 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13705 dev->netdev_ops = &tg3_netdev_ops;
13706 else
13707 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13708
13709
13710 /* The EPB bridge inside 5714, 5715, and 5780 and any
13711 * device behind the EPB cannot support DMA addresses > 40-bit.
13712 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13713 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13714 * do DMA address check in tg3_start_xmit().
13715 */
13716 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13717 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13718 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13719 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13720#ifdef CONFIG_HIGHMEM
13721 dma_mask = DMA_64BIT_MASK;
13722#endif
13723 } else
13724 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13725
13726 /* Configure DMA attributes. */
13727 if (dma_mask > DMA_32BIT_MASK) {
13728 err = pci_set_dma_mask(pdev, dma_mask);
13729 if (!err) {
13730 dev->features |= NETIF_F_HIGHDMA;
13731 err = pci_set_consistent_dma_mask(pdev,
13732 persist_dma_mask);
13733 if (err < 0) {
13734 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13735 "DMA for consistent allocations\n");
13736 goto err_out_iounmap;
13737 }
13738 }
13739 }
13740 if (err || dma_mask == DMA_32BIT_MASK) {
13741 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13742 if (err) {
13743 printk(KERN_ERR PFX "No usable DMA configuration, "
13744 "aborting.\n");
13745 goto err_out_iounmap;
13746 }
13747 }
13748
13749 tg3_init_bufmgr_config(tp);
13750
13751 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13752 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13753 }
13754 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13755 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13756 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13757 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13758 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13759 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13760 } else {
13761 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13762 }
13763
13764 /* TSO is on by default on chips that support hardware TSO.
13765 * Firmware TSO on older chips gives lower performance, so it
13766 * is off by default, but can be enabled using ethtool.
13767 */
13768 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13769 if (dev->features & NETIF_F_IP_CSUM)
13770 dev->features |= NETIF_F_TSO;
13771 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13772 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13773 dev->features |= NETIF_F_TSO6;
13774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13775 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13776 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13778 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13779 dev->features |= NETIF_F_TSO_ECN;
13780 }
13781
13782
13783 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13784 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13785 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13786 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13787 tp->rx_pending = 63;
13788 }
13789
13790 err = tg3_get_device_address(tp);
13791 if (err) {
13792 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13793 "aborting.\n");
13794 goto err_out_iounmap;
13795 }
13796
13797 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13798 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13799 if (!tp->aperegs) {
13800 printk(KERN_ERR PFX "Cannot map APE registers, "
13801 "aborting.\n");
13802 err = -ENOMEM;
13803 goto err_out_iounmap;
13804 }
13805
13806 tg3_ape_lock_init(tp);
13807 }
13808
13809 /*
13810 * Reset chip in case UNDI or EFI driver did not shutdown
13811 * DMA self test will enable WDMAC and we'll see (spurious)
13812 * pending DMA on the PCI bus at that point.
13813 */
13814 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13815 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13816 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13817 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13818 }
13819
13820 err = tg3_test_dma(tp);
13821 if (err) {
13822 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13823 goto err_out_apeunmap;
13824 }
13825
13826 /* flow control autonegotiation is default behavior */
13827 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13828 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13829
13830 tg3_init_coal(tp);
13831
13832 pci_set_drvdata(pdev, dev);
13833
13834 err = register_netdev(dev);
13835 if (err) {
13836 printk(KERN_ERR PFX "Cannot register net device, "
13837 "aborting.\n");
13838 goto err_out_apeunmap;
13839 }
13840
13841 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13842 dev->name,
13843 tp->board_part_number,
13844 tp->pci_chip_rev_id,
13845 tg3_bus_string(tp, str),
13846 dev->dev_addr);
13847
13848 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13849 printk(KERN_INFO
13850 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13851 tp->dev->name,
13852 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13853 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13854 else
13855 printk(KERN_INFO
13856 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13857 tp->dev->name, tg3_phy_string(tp),
13858 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13859 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13860 "10/100/1000Base-T")),
13861 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13862
13863 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13864 dev->name,
13865 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13866 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13867 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13868 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13869 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13870 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13871 dev->name, tp->dma_rwctrl,
13872 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13873 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13874
13875 return 0;
13876
13877err_out_apeunmap:
13878 if (tp->aperegs) {
13879 iounmap(tp->aperegs);
13880 tp->aperegs = NULL;
13881 }
13882
13883err_out_iounmap:
13884 if (tp->regs) {
13885 iounmap(tp->regs);
13886 tp->regs = NULL;
13887 }
13888
13889err_out_free_dev:
13890 free_netdev(dev);
13891
13892err_out_free_res:
13893 pci_release_regions(pdev);
13894
13895err_out_disable_pdev:
13896 pci_disable_device(pdev);
13897 pci_set_drvdata(pdev, NULL);
13898 return err;
13899}
13900
13901static void __devexit tg3_remove_one(struct pci_dev *pdev)
13902{
13903 struct net_device *dev = pci_get_drvdata(pdev);
13904
13905 if (dev) {
13906 struct tg3 *tp = netdev_priv(dev);
13907
13908 flush_scheduled_work();
13909
13910 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13911 tg3_phy_fini(tp);
13912 tg3_mdio_fini(tp);
13913 }
13914
13915 unregister_netdev(dev);
13916 if (tp->aperegs) {
13917 iounmap(tp->aperegs);
13918 tp->aperegs = NULL;
13919 }
13920 if (tp->regs) {
13921 iounmap(tp->regs);
13922 tp->regs = NULL;
13923 }
13924 free_netdev(dev);
13925 pci_release_regions(pdev);
13926 pci_disable_device(pdev);
13927 pci_set_drvdata(pdev, NULL);
13928 }
13929}
13930
13931static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13932{
13933 struct net_device *dev = pci_get_drvdata(pdev);
13934 struct tg3 *tp = netdev_priv(dev);
13935 pci_power_t target_state;
13936 int err;
13937
13938 /* PCI register 4 needs to be saved whether netif_running() or not.
13939 * MSI address and data need to be saved if using MSI and
13940 * netif_running().
13941 */
13942 pci_save_state(pdev);
13943
13944 if (!netif_running(dev))
13945 return 0;
13946
13947 flush_scheduled_work();
13948 tg3_phy_stop(tp);
13949 tg3_netif_stop(tp);
13950
13951 del_timer_sync(&tp->timer);
13952
13953 tg3_full_lock(tp, 1);
13954 tg3_disable_ints(tp);
13955 tg3_full_unlock(tp);
13956
13957 netif_device_detach(dev);
13958
13959 tg3_full_lock(tp, 0);
13960 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13961 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13962 tg3_full_unlock(tp);
13963
13964 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13965
13966 err = tg3_set_power_state(tp, target_state);
13967 if (err) {
13968 int err2;
13969
13970 tg3_full_lock(tp, 0);
13971
13972 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13973 err2 = tg3_restart_hw(tp, 1);
13974 if (err2)
13975 goto out;
13976
13977 tp->timer.expires = jiffies + tp->timer_offset;
13978 add_timer(&tp->timer);
13979
13980 netif_device_attach(dev);
13981 tg3_netif_start(tp);
13982
13983out:
13984 tg3_full_unlock(tp);
13985
13986 if (!err2)
13987 tg3_phy_start(tp);
13988 }
13989
13990 return err;
13991}
13992
13993static int tg3_resume(struct pci_dev *pdev)
13994{
13995 struct net_device *dev = pci_get_drvdata(pdev);
13996 struct tg3 *tp = netdev_priv(dev);
13997 int err;
13998
13999 pci_restore_state(tp->pdev);
14000
14001 if (!netif_running(dev))
14002 return 0;
14003
14004 err = tg3_set_power_state(tp, PCI_D0);
14005 if (err)
14006 return err;
14007
14008 netif_device_attach(dev);
14009
14010 tg3_full_lock(tp, 0);
14011
14012 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14013 err = tg3_restart_hw(tp, 1);
14014 if (err)
14015 goto out;
14016
14017 tp->timer.expires = jiffies + tp->timer_offset;
14018 add_timer(&tp->timer);
14019
14020 tg3_netif_start(tp);
14021
14022out:
14023 tg3_full_unlock(tp);
14024
14025 if (!err)
14026 tg3_phy_start(tp);
14027
14028 return err;
14029}
14030
14031static struct pci_driver tg3_driver = {
14032 .name = DRV_MODULE_NAME,
14033 .id_table = tg3_pci_tbl,
14034 .probe = tg3_init_one,
14035 .remove = __devexit_p(tg3_remove_one),
14036 .suspend = tg3_suspend,
14037 .resume = tg3_resume
14038};
14039
14040static int __init tg3_init(void)
14041{
14042 return pci_register_driver(&tg3_driver);
14043}
14044
14045static void __exit tg3_cleanup(void)
14046{
14047 pci_unregister_driver(&tg3_driver);
14048}
14049
14050module_init(tg3_init);
14051module_exit(tg3_cleanup);
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