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1 | /* bnx2x.h: Broadcom Everest network driver. | |
2 | * | |
3 | * Copyright (c) 2007-2008 Broadcom Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
16 | ||
17 | /* compilation time flags */ | |
18 | ||
19 | /* define this to make the driver freeze on error to allow getting debug info | |
20 | * (you will need to reboot afterwards) */ | |
21 | /* #define BNX2X_STOP_ON_ERROR */ | |
22 | ||
23 | /* error/debug prints */ | |
24 | ||
25 | #define DRV_MODULE_NAME "bnx2x" | |
26 | #define PFX DRV_MODULE_NAME ": " | |
27 | ||
28 | /* for messages that are currently off */ | |
29 | #define BNX2X_MSG_OFF 0 | |
30 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ | |
31 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ | |
32 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ | |
33 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ | |
34 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ | |
35 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | |
36 | ||
37 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ | |
38 | ||
39 | /* regular debug print */ | |
40 | #define DP(__mask, __fmt, __args...) do { \ | |
41 | if (bp->msglevel & (__mask)) \ | |
42 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ | |
43 | bp->dev?(bp->dev->name):"?", ##__args); \ | |
44 | } while (0) | |
45 | ||
46 | /* errors debug print */ | |
47 | #define BNX2X_DBG_ERR(__fmt, __args...) do { \ | |
48 | if (bp->msglevel & NETIF_MSG_PROBE) \ | |
49 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ | |
50 | bp->dev?(bp->dev->name):"?", ##__args); \ | |
51 | } while (0) | |
52 | ||
53 | /* for errors (never masked) */ | |
54 | #define BNX2X_ERR(__fmt, __args...) do { \ | |
55 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ | |
56 | bp->dev?(bp->dev->name):"?", ##__args); \ | |
57 | } while (0) | |
58 | ||
59 | /* before we have a dev->name use dev_info() */ | |
60 | #define BNX2X_DEV_INFO(__fmt, __args...) do { \ | |
61 | if (bp->msglevel & NETIF_MSG_PROBE) \ | |
62 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ | |
63 | } while (0) | |
64 | ||
65 | ||
66 | #ifdef BNX2X_STOP_ON_ERROR | |
67 | #define bnx2x_panic() do { \ | |
68 | bp->panic = 1; \ | |
69 | BNX2X_ERR("driver assert\n"); \ | |
70 | bnx2x_int_disable(bp); \ | |
71 | bnx2x_panic_dump(bp); \ | |
72 | } while (0) | |
73 | #else | |
74 | #define bnx2x_panic() do { \ | |
75 | BNX2X_ERR("driver assert\n"); \ | |
76 | bnx2x_panic_dump(bp); \ | |
77 | } while (0) | |
78 | #endif | |
79 | ||
80 | ||
81 | #ifdef NETIF_F_HW_VLAN_TX | |
82 | #define BCM_VLAN 1 | |
83 | #endif | |
84 | ||
85 | ||
86 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) | |
87 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | |
88 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
89 | ||
90 | ||
91 | #define REG_ADDR(bp, offset) (bp->regview + offset) | |
92 | ||
93 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) | |
94 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
95 | #define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset)) | |
96 | ||
97 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
98 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) | |
99 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) | |
100 | #define REG_WR32(bp, offset, val) REG_WR(bp, offset, val) | |
101 | ||
102 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) | |
103 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
104 | ||
105 | #define REG_RD_DMAE(bp, offset, valp, len32) \ | |
106 | do { \ | |
107 | bnx2x_read_dmae(bp, offset, len32);\ | |
108 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \ | |
109 | } while (0) | |
110 | ||
111 | #define REG_WR_DMAE(bp, offset, valp, len32) \ | |
112 | do { \ | |
113 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \ | |
114 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ | |
115 | offset, len32); \ | |
116 | } while (0) | |
117 | ||
118 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ | |
119 | offsetof(struct shmem_region, field)) | |
120 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
121 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
122 | ||
123 | #define NIG_WR(reg, val) REG_WR(bp, reg, val) | |
124 | #define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) | |
125 | #define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val) | |
126 | ||
127 | ||
128 | #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) | |
129 | ||
130 | #define for_each_nondefault_queue(bp, var) \ | |
131 | for (var = 1; var < bp->num_queues; var++) | |
132 | #define is_multi(bp) (bp->num_queues > 1) | |
133 | ||
134 | ||
135 | struct regp { | |
136 | u32 lo; | |
137 | u32 hi; | |
138 | }; | |
139 | ||
140 | struct bmac_stats { | |
141 | struct regp tx_gtpkt; | |
142 | struct regp tx_gtxpf; | |
143 | struct regp tx_gtfcs; | |
144 | struct regp tx_gtmca; | |
145 | struct regp tx_gtgca; | |
146 | struct regp tx_gtfrg; | |
147 | struct regp tx_gtovr; | |
148 | struct regp tx_gt64; | |
149 | struct regp tx_gt127; | |
150 | struct regp tx_gt255; /* 10 */ | |
151 | struct regp tx_gt511; | |
152 | struct regp tx_gt1023; | |
153 | struct regp tx_gt1518; | |
154 | struct regp tx_gt2047; | |
155 | struct regp tx_gt4095; | |
156 | struct regp tx_gt9216; | |
157 | struct regp tx_gt16383; | |
158 | struct regp tx_gtmax; | |
159 | struct regp tx_gtufl; | |
160 | struct regp tx_gterr; /* 20 */ | |
161 | struct regp tx_gtbyt; | |
162 | ||
163 | struct regp rx_gr64; | |
164 | struct regp rx_gr127; | |
165 | struct regp rx_gr255; | |
166 | struct regp rx_gr511; | |
167 | struct regp rx_gr1023; | |
168 | struct regp rx_gr1518; | |
169 | struct regp rx_gr2047; | |
170 | struct regp rx_gr4095; | |
171 | struct regp rx_gr9216; /* 30 */ | |
172 | struct regp rx_gr16383; | |
173 | struct regp rx_grmax; | |
174 | struct regp rx_grpkt; | |
175 | struct regp rx_grfcs; | |
176 | struct regp rx_grmca; | |
177 | struct regp rx_grbca; | |
178 | struct regp rx_grxcf; | |
179 | struct regp rx_grxpf; | |
180 | struct regp rx_grxuo; | |
181 | struct regp rx_grjbr; /* 40 */ | |
182 | struct regp rx_grovr; | |
183 | struct regp rx_grflr; | |
184 | struct regp rx_grmeg; | |
185 | struct regp rx_grmeb; | |
186 | struct regp rx_grbyt; | |
187 | struct regp rx_grund; | |
188 | struct regp rx_grfrg; | |
189 | struct regp rx_grerb; | |
190 | struct regp rx_grfre; | |
191 | struct regp rx_gripj; /* 50 */ | |
192 | }; | |
193 | ||
194 | struct emac_stats { | |
195 | u32 rx_ifhcinoctets ; | |
196 | u32 rx_ifhcinbadoctets ; | |
197 | u32 rx_etherstatsfragments ; | |
198 | u32 rx_ifhcinucastpkts ; | |
199 | u32 rx_ifhcinmulticastpkts ; | |
200 | u32 rx_ifhcinbroadcastpkts ; | |
201 | u32 rx_dot3statsfcserrors ; | |
202 | u32 rx_dot3statsalignmenterrors ; | |
203 | u32 rx_dot3statscarriersenseerrors ; | |
204 | u32 rx_xonpauseframesreceived ; /* 10 */ | |
205 | u32 rx_xoffpauseframesreceived ; | |
206 | u32 rx_maccontrolframesreceived ; | |
207 | u32 rx_xoffstateentered ; | |
208 | u32 rx_dot3statsframestoolong ; | |
209 | u32 rx_etherstatsjabbers ; | |
210 | u32 rx_etherstatsundersizepkts ; | |
211 | u32 rx_etherstatspkts64octets ; | |
212 | u32 rx_etherstatspkts65octetsto127octets ; | |
213 | u32 rx_etherstatspkts128octetsto255octets ; | |
214 | u32 rx_etherstatspkts256octetsto511octets ; /* 20 */ | |
215 | u32 rx_etherstatspkts512octetsto1023octets ; | |
216 | u32 rx_etherstatspkts1024octetsto1522octets; | |
217 | u32 rx_etherstatspktsover1522octets ; | |
218 | ||
219 | u32 rx_falsecarriererrors ; | |
220 | ||
221 | u32 tx_ifhcoutoctets ; | |
222 | u32 tx_ifhcoutbadoctets ; | |
223 | u32 tx_etherstatscollisions ; | |
224 | u32 tx_outxonsent ; | |
225 | u32 tx_outxoffsent ; | |
226 | u32 tx_flowcontroldone ; /* 30 */ | |
227 | u32 tx_dot3statssinglecollisionframes ; | |
228 | u32 tx_dot3statsmultiplecollisionframes ; | |
229 | u32 tx_dot3statsdeferredtransmissions ; | |
230 | u32 tx_dot3statsexcessivecollisions ; | |
231 | u32 tx_dot3statslatecollisions ; | |
232 | u32 tx_ifhcoutucastpkts ; | |
233 | u32 tx_ifhcoutmulticastpkts ; | |
234 | u32 tx_ifhcoutbroadcastpkts ; | |
235 | u32 tx_etherstatspkts64octets ; | |
236 | u32 tx_etherstatspkts65octetsto127octets ; /* 40 */ | |
237 | u32 tx_etherstatspkts128octetsto255octets ; | |
238 | u32 tx_etherstatspkts256octetsto511octets ; | |
239 | u32 tx_etherstatspkts512octetsto1023octets ; | |
240 | u32 tx_etherstatspkts1024octetsto1522octet ; | |
241 | u32 tx_etherstatspktsover1522octets ; | |
242 | u32 tx_dot3statsinternalmactransmiterrors ; /* 46 */ | |
243 | }; | |
244 | ||
245 | union mac_stats { | |
246 | struct emac_stats emac; | |
247 | struct bmac_stats bmac; | |
248 | }; | |
249 | ||
250 | struct nig_stats { | |
251 | u32 brb_discard; | |
252 | u32 brb_packet; | |
253 | u32 brb_truncate; | |
254 | u32 flow_ctrl_discard; | |
255 | u32 flow_ctrl_octets; | |
256 | u32 flow_ctrl_packet; | |
257 | u32 mng_discard; | |
258 | u32 mng_octet_inp; | |
259 | u32 mng_octet_out; | |
260 | u32 mng_packet_inp; | |
261 | u32 mng_packet_out; | |
262 | u32 pbf_octets; | |
263 | u32 pbf_packet; | |
264 | u32 safc_inp; | |
265 | u32 done; | |
266 | u32 pad; | |
267 | }; | |
268 | ||
269 | struct bnx2x_eth_stats { | |
270 | u32 pad; /* to make long counters u64 aligned */ | |
271 | u32 mac_stx_start; | |
272 | u32 total_bytes_received_hi; | |
273 | u32 total_bytes_received_lo; | |
274 | u32 total_bytes_transmitted_hi; | |
275 | u32 total_bytes_transmitted_lo; | |
276 | u32 total_unicast_packets_received_hi; | |
277 | u32 total_unicast_packets_received_lo; | |
278 | u32 total_multicast_packets_received_hi; | |
279 | u32 total_multicast_packets_received_lo; | |
280 | u32 total_broadcast_packets_received_hi; | |
281 | u32 total_broadcast_packets_received_lo; | |
282 | u32 total_unicast_packets_transmitted_hi; | |
283 | u32 total_unicast_packets_transmitted_lo; | |
284 | u32 total_multicast_packets_transmitted_hi; | |
285 | u32 total_multicast_packets_transmitted_lo; | |
286 | u32 total_broadcast_packets_transmitted_hi; | |
287 | u32 total_broadcast_packets_transmitted_lo; | |
288 | u32 crc_receive_errors; | |
289 | u32 alignment_errors; | |
290 | u32 false_carrier_detections; | |
291 | u32 runt_packets_received; | |
292 | u32 jabber_packets_received; | |
293 | u32 pause_xon_frames_received; | |
294 | u32 pause_xoff_frames_received; | |
295 | u32 pause_xon_frames_transmitted; | |
296 | u32 pause_xoff_frames_transmitted; | |
297 | u32 single_collision_transmit_frames; | |
298 | u32 multiple_collision_transmit_frames; | |
299 | u32 late_collision_frames; | |
300 | u32 excessive_collision_frames; | |
301 | u32 control_frames_received; | |
302 | u32 frames_received_64_bytes; | |
303 | u32 frames_received_65_127_bytes; | |
304 | u32 frames_received_128_255_bytes; | |
305 | u32 frames_received_256_511_bytes; | |
306 | u32 frames_received_512_1023_bytes; | |
307 | u32 frames_received_1024_1522_bytes; | |
308 | u32 frames_received_1523_9022_bytes; | |
309 | u32 frames_transmitted_64_bytes; | |
310 | u32 frames_transmitted_65_127_bytes; | |
311 | u32 frames_transmitted_128_255_bytes; | |
312 | u32 frames_transmitted_256_511_bytes; | |
313 | u32 frames_transmitted_512_1023_bytes; | |
314 | u32 frames_transmitted_1024_1522_bytes; | |
315 | u32 frames_transmitted_1523_9022_bytes; | |
316 | u32 valid_bytes_received_hi; | |
317 | u32 valid_bytes_received_lo; | |
318 | u32 error_runt_packets_received; | |
319 | u32 error_jabber_packets_received; | |
320 | u32 mac_stx_end; | |
321 | ||
322 | u32 pad2; | |
323 | u32 stat_IfHCInBadOctets_hi; | |
324 | u32 stat_IfHCInBadOctets_lo; | |
325 | u32 stat_IfHCOutBadOctets_hi; | |
326 | u32 stat_IfHCOutBadOctets_lo; | |
327 | u32 stat_Dot3statsFramesTooLong; | |
328 | u32 stat_Dot3statsInternalMacTransmitErrors; | |
329 | u32 stat_Dot3StatsCarrierSenseErrors; | |
330 | u32 stat_Dot3StatsDeferredTransmissions; | |
331 | u32 stat_FlowControlDone; | |
332 | u32 stat_XoffStateEntered; | |
333 | ||
334 | u32 x_total_sent_bytes_hi; | |
335 | u32 x_total_sent_bytes_lo; | |
336 | u32 x_total_sent_pkts; | |
337 | ||
338 | u32 t_rcv_unicast_bytes_hi; | |
339 | u32 t_rcv_unicast_bytes_lo; | |
340 | u32 t_rcv_broadcast_bytes_hi; | |
341 | u32 t_rcv_broadcast_bytes_lo; | |
342 | u32 t_rcv_multicast_bytes_hi; | |
343 | u32 t_rcv_multicast_bytes_lo; | |
344 | u32 t_total_rcv_pkt; | |
345 | ||
346 | u32 checksum_discard; | |
347 | u32 packets_too_big_discard; | |
348 | u32 no_buff_discard; | |
349 | u32 ttl0_discard; | |
350 | u32 mac_discard; | |
351 | u32 mac_filter_discard; | |
352 | u32 xxoverflow_discard; | |
353 | u32 brb_truncate_discard; | |
354 | ||
355 | u32 brb_discard; | |
356 | u32 brb_packet; | |
357 | u32 brb_truncate; | |
358 | u32 flow_ctrl_discard; | |
359 | u32 flow_ctrl_octets; | |
360 | u32 flow_ctrl_packet; | |
361 | u32 mng_discard; | |
362 | u32 mng_octet_inp; | |
363 | u32 mng_octet_out; | |
364 | u32 mng_packet_inp; | |
365 | u32 mng_packet_out; | |
366 | u32 pbf_octets; | |
367 | u32 pbf_packet; | |
368 | u32 safc_inp; | |
369 | u32 driver_xoff; | |
370 | u32 number_of_bugs_found_in_stats_spec; /* just kidding */ | |
371 | }; | |
372 | ||
373 | #define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL) | |
374 | struct sw_rx_bd { | |
375 | struct sk_buff *skb; | |
376 | DECLARE_PCI_UNMAP_ADDR(mapping) | |
377 | }; | |
378 | ||
379 | struct sw_tx_bd { | |
380 | struct sk_buff *skb; | |
381 | u16 first_bd; | |
382 | }; | |
383 | ||
384 | struct bnx2x_fastpath { | |
385 | ||
386 | struct napi_struct napi; | |
387 | ||
388 | struct host_status_block *status_blk; | |
389 | dma_addr_t status_blk_mapping; | |
390 | ||
391 | struct eth_tx_db_data *hw_tx_prods; | |
392 | dma_addr_t tx_prods_mapping; | |
393 | ||
394 | struct sw_tx_bd *tx_buf_ring; | |
395 | ||
396 | struct eth_tx_bd *tx_desc_ring; | |
397 | dma_addr_t tx_desc_mapping; | |
398 | ||
399 | struct sw_rx_bd *rx_buf_ring; | |
400 | ||
401 | struct eth_rx_bd *rx_desc_ring; | |
402 | dma_addr_t rx_desc_mapping; | |
403 | ||
404 | union eth_rx_cqe *rx_comp_ring; | |
405 | dma_addr_t rx_comp_mapping; | |
406 | ||
407 | int state; | |
408 | #define BNX2X_FP_STATE_CLOSED 0 | |
409 | #define BNX2X_FP_STATE_IRQ 0x80000 | |
410 | #define BNX2X_FP_STATE_OPENING 0x90000 | |
411 | #define BNX2X_FP_STATE_OPEN 0xa0000 | |
412 | #define BNX2X_FP_STATE_HALTING 0xb0000 | |
413 | #define BNX2X_FP_STATE_HALTED 0xc0000 | |
414 | ||
415 | u8 index; /* number in fp array */ | |
416 | u8 cl_id; /* eth client id */ | |
417 | u8 sb_id; /* status block number in HW */ | |
418 | #define FP_IDX(fp) (fp->index) | |
419 | #define FP_CL_ID(fp) (fp->cl_id) | |
420 | #define BP_CL_ID(bp) (bp->fp[0].cl_id) | |
421 | #define FP_SB_ID(fp) (fp->sb_id) | |
422 | #define CNIC_SB_ID 0 | |
423 | ||
424 | u16 tx_pkt_prod; | |
425 | u16 tx_pkt_cons; | |
426 | u16 tx_bd_prod; | |
427 | u16 tx_bd_cons; | |
428 | u16 *tx_cons_sb; | |
429 | ||
430 | u16 fp_c_idx; | |
431 | u16 fp_u_idx; | |
432 | ||
433 | u16 rx_bd_prod; | |
434 | u16 rx_bd_cons; | |
435 | u16 rx_comp_prod; | |
436 | u16 rx_comp_cons; | |
437 | u16 *rx_cons_sb; | |
438 | ||
439 | unsigned long tx_pkt, | |
440 | rx_pkt, | |
441 | rx_calls; | |
442 | ||
443 | struct bnx2x *bp; /* parent */ | |
444 | }; | |
445 | ||
446 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) | |
447 | /* This is needed for determening of last_max */ | |
448 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) | |
449 | ||
450 | /* stuff added to make the code fit 80Col */ | |
451 | ||
452 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) | |
453 | ||
454 | #define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \ | |
455 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \ | |
456 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG) | |
457 | ||
458 | ||
459 | #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS | |
460 | #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS | |
461 | #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS | |
462 | ||
463 | #define BNX2X_RX_SB_INDEX \ | |
464 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]) | |
465 | ||
466 | #define BNX2X_RX_SB_BD_INDEX \ | |
467 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX]) | |
468 | ||
469 | #define BNX2X_RX_SB_INDEX_NUM \ | |
470 | (((U_SB_ETH_RX_CQ_INDEX << \ | |
471 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \ | |
472 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \ | |
473 | ((U_SB_ETH_RX_BD_INDEX << \ | |
474 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \ | |
475 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER)) | |
476 | ||
477 | #define BNX2X_TX_SB_INDEX \ | |
478 | (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]) | |
479 | ||
480 | /* common */ | |
481 | ||
482 | struct bnx2x_common { | |
483 | ||
484 | u32 chip_id; | |
485 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
486 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) | |
487 | ||
488 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) | |
489 | #define CHIP_NUM_57710 0x164e | |
490 | #define CHIP_NUM_57711 0x164f | |
491 | #define CHIP_NUM_57711E 0x1650 | |
492 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) | |
493 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
494 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
495 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ | |
496 | CHIP_IS_57711E(bp)) | |
497 | #define IS_E1H_OFFSET CHIP_IS_E1H(bp) | |
498 | ||
499 | #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) | |
500 | #define CHIP_REV_Ax 0x00000000 | |
501 | /* assume maximum 5 revisions */ | |
502 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) | |
503 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ | |
504 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
505 | !(CHIP_REV(bp) & 0x00001000)) | |
506 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ | |
507 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
508 | (CHIP_REV(bp) & 0x00001000)) | |
509 | ||
510 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
511 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
512 | ||
513 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) | |
514 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
515 | ||
516 | int flash_size; | |
517 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ | |
518 | #define NVRAM_TIMEOUT_COUNT 30000 | |
519 | #define NVRAM_PAGE_SIZE 256 | |
520 | ||
521 | u32 shmem_base; | |
522 | ||
523 | u32 hw_config; | |
524 | u32 board; | |
525 | ||
526 | u32 bc_ver; | |
527 | ||
528 | char *name; | |
529 | }; | |
530 | ||
531 | ||
532 | /* end of common */ | |
533 | ||
534 | /* port */ | |
535 | ||
536 | struct bnx2x_port { | |
537 | u32 pmf; | |
538 | ||
539 | u32 link_config; | |
540 | ||
541 | u32 supported; | |
542 | /* link settings - missing defines */ | |
543 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
544 | ||
545 | u32 advertising; | |
546 | /* link settings - missing defines */ | |
547 | #define ADVERTISED_2500baseX_Full (1 << 15) | |
548 | ||
549 | u32 phy_addr; | |
550 | ||
551 | /* used to synchronize phy accesses */ | |
552 | struct mutex phy_mutex; | |
553 | ||
554 | u32 port_stx; | |
555 | ||
556 | struct nig_stats old_nig_stats; | |
557 | }; | |
558 | ||
559 | /* end of port */ | |
560 | ||
561 | #define MAC_STX_NA 0xffffffff | |
562 | ||
563 | #ifdef BNX2X_MULTI | |
564 | #define MAX_CONTEXT 16 | |
565 | #else | |
566 | #define MAX_CONTEXT 1 | |
567 | #endif | |
568 | ||
569 | union cdu_context { | |
570 | struct eth_context eth; | |
571 | char pad[1024]; | |
572 | }; | |
573 | ||
574 | #define MAX_DMAE_C 6 | |
575 | ||
576 | /* DMA memory not used in fastpath */ | |
577 | struct bnx2x_slowpath { | |
578 | union cdu_context context[MAX_CONTEXT]; | |
579 | struct eth_stats_query fw_stats; | |
580 | struct mac_configuration_cmd mac_config; | |
581 | struct mac_configuration_cmd mcast_config; | |
582 | ||
583 | /* used by dmae command executer */ | |
584 | struct dmae_command dmae[MAX_DMAE_C]; | |
585 | ||
586 | union mac_stats mac_stats; | |
587 | struct nig_stats nig; | |
588 | struct bnx2x_eth_stats eth_stats; | |
589 | ||
590 | u32 wb_comp; | |
591 | #define BNX2X_WB_COMP_VAL 0xe0d0d0ae | |
592 | u32 wb_data[4]; | |
593 | }; | |
594 | ||
595 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
596 | #define bnx2x_sp_mapping(bp, var) \ | |
597 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
598 | ||
599 | ||
600 | /* attn group wiring */ | |
601 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
602 | ||
603 | struct attn_route { | |
604 | u32 sig[4]; | |
605 | }; | |
606 | ||
607 | struct bnx2x { | |
608 | /* Fields used in the tx and intr/napi performance paths | |
609 | * are grouped together in the beginning of the structure | |
610 | */ | |
611 | struct bnx2x_fastpath fp[MAX_CONTEXT]; | |
612 | void __iomem *regview; | |
613 | void __iomem *doorbells; | |
614 | #define BNX2X_DB_SIZE (16*2048) | |
615 | ||
616 | struct net_device *dev; | |
617 | struct pci_dev *pdev; | |
618 | ||
619 | atomic_t intr_sem; | |
620 | struct msix_entry msix_table[MAX_CONTEXT+1]; | |
621 | ||
622 | int tx_ring_size; | |
623 | ||
624 | #ifdef BCM_VLAN | |
625 | struct vlan_group *vlgrp; | |
626 | #endif | |
627 | ||
628 | u32 rx_csum; | |
629 | u32 rx_offset; | |
630 | u32 rx_buf_use_size; /* useable size */ | |
631 | u32 rx_buf_size; /* with alignment */ | |
632 | #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ | |
633 | #define ETH_MIN_PACKET_SIZE 60 | |
634 | #define ETH_MAX_PACKET_SIZE 1500 | |
635 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
636 | ||
637 | struct host_def_status_block *def_status_blk; | |
638 | #define DEF_SB_ID 16 | |
639 | u16 def_c_idx; | |
640 | u16 def_u_idx; | |
641 | u16 def_x_idx; | |
642 | u16 def_t_idx; | |
643 | u16 def_att_idx; | |
644 | u32 attn_state; | |
645 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
646 | u32 aeu_mask; | |
647 | u32 nig_mask; | |
648 | ||
649 | /* slow path ring */ | |
650 | struct eth_spe *spq; | |
651 | dma_addr_t spq_mapping; | |
652 | u16 spq_prod_idx; | |
653 | struct eth_spe *spq_prod_bd; | |
654 | struct eth_spe *spq_last_bd; | |
655 | u16 *dsb_sp_prod; | |
656 | u16 spq_left; /* serialize spq */ | |
657 | /* used to synchronize spq accesses */ | |
658 | spinlock_t spq_lock; | |
659 | ||
660 | /* Flag for marking that there is either | |
661 | * STAT_QUERY or CFC DELETE ramrod pending | |
662 | */ | |
663 | u8 stat_pending; | |
664 | ||
665 | /* End of fileds used in the performance code paths */ | |
666 | ||
667 | int panic; | |
668 | int msglevel; | |
669 | ||
670 | u32 flags; | |
671 | #define PCIX_FLAG 1 | |
672 | #define PCI_32BIT_FLAG 2 | |
673 | #define ONE_TDMA_FLAG 4 /* no longer used */ | |
674 | #define NO_WOL_FLAG 8 | |
675 | #define USING_DAC_FLAG 0x10 | |
676 | #define USING_MSIX_FLAG 0x20 | |
677 | #define ASF_ENABLE_FLAG 0x40 | |
678 | #define NO_MCP_FLAG 0x100 | |
679 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) | |
680 | ||
681 | int func; | |
682 | #define BP_PORT(bp) (bp->func % PORT_MAX) | |
683 | #define BP_FUNC(bp) (bp->func) | |
684 | #define BP_E1HVN(bp) (bp->func >> 1) | |
685 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) | |
686 | /* assorted E1HVN */ | |
687 | #define IS_E1HMF(bp) (bp->e1hmf != 0) | |
688 | #define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16) | |
689 | ||
690 | int pm_cap; | |
691 | int pcie_cap; | |
692 | ||
693 | struct work_struct sp_task; | |
694 | struct work_struct reset_task; | |
695 | ||
696 | struct timer_list timer; | |
697 | int timer_interval; | |
698 | int current_interval; | |
699 | ||
700 | u16 fw_seq; | |
701 | u16 fw_drv_pulse_wr_seq; | |
702 | u32 func_stx; | |
703 | ||
704 | struct link_params link_params; | |
705 | struct link_vars link_vars; | |
706 | ||
707 | struct bnx2x_common common; | |
708 | struct bnx2x_port port; | |
709 | ||
710 | u32 mf_config; | |
711 | u16 e1hov; | |
712 | u8 e1hmf; | |
713 | ||
714 | u8 wol; | |
715 | ||
716 | int rx_ring_size; | |
717 | ||
718 | u16 tx_quick_cons_trip_int; | |
719 | u16 tx_quick_cons_trip; | |
720 | u16 tx_ticks_int; | |
721 | u16 tx_ticks; | |
722 | ||
723 | u16 rx_quick_cons_trip_int; | |
724 | u16 rx_quick_cons_trip; | |
725 | u16 rx_ticks_int; | |
726 | u16 rx_ticks; | |
727 | ||
728 | u32 stats_ticks; | |
729 | u32 lin_cnt; | |
730 | ||
731 | int state; | |
732 | #define BNX2X_STATE_CLOSED 0x0 | |
733 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 | |
734 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
735 | #define BNX2X_STATE_OPEN 0x3000 | |
736 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 | |
737 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 | |
738 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 | |
739 | #define BNX2X_STATE_DISABLED 0xd000 | |
740 | #define BNX2X_STATE_DIAG 0xe000 | |
741 | #define BNX2X_STATE_ERROR 0xf000 | |
742 | ||
743 | int num_queues; | |
744 | ||
745 | u32 rx_mode; | |
746 | #define BNX2X_RX_MODE_NONE 0 | |
747 | #define BNX2X_RX_MODE_NORMAL 1 | |
748 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
749 | #define BNX2X_RX_MODE_PROMISC 3 | |
750 | #define BNX2X_MAX_MULTICAST 64 | |
751 | #define BNX2X_MAX_EMUL_MULTI 16 | |
752 | ||
753 | dma_addr_t def_status_blk_mapping; | |
754 | ||
755 | struct bnx2x_slowpath *slowpath; | |
756 | dma_addr_t slowpath_mapping; | |
757 | ||
758 | #ifdef BCM_ISCSI | |
759 | void *t1; | |
760 | dma_addr_t t1_mapping; | |
761 | void *t2; | |
762 | dma_addr_t t2_mapping; | |
763 | void *timers; | |
764 | dma_addr_t timers_mapping; | |
765 | void *qm; | |
766 | dma_addr_t qm_mapping; | |
767 | #endif | |
768 | ||
769 | char *name; | |
770 | ||
771 | /* used to synchronize stats collecting */ | |
772 | int stats_state; | |
773 | #define STATS_STATE_DISABLE 0 | |
774 | #define STATS_STATE_ENABLE 1 | |
775 | #define STATS_STATE_STOP 2 /* stop stats on next iteration */ | |
776 | ||
777 | /* used by dmae command loader */ | |
778 | struct dmae_command dmae; | |
779 | int executer_idx; | |
780 | ||
781 | int dmae_ready; | |
782 | /* used to synchronize dmae accesses */ | |
783 | struct mutex dmae_mutex; | |
784 | struct dmae_command init_dmae; | |
785 | ||
786 | ||
787 | ||
788 | u32 old_brb_discard; | |
789 | struct bmac_stats old_bmac; | |
790 | struct tstorm_per_client_stats old_tclient; | |
791 | struct z_stream_s *strm; | |
792 | void *gunzip_buf; | |
793 | dma_addr_t gunzip_mapping; | |
794 | int gunzip_outlen; | |
795 | #define FW_BUF_SIZE 0x8000 | |
796 | ||
797 | }; | |
798 | ||
799 | ||
800 | /* DMAE command defines */ | |
801 | #define DMAE_CMD_SRC_PCI 0 | |
802 | #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC | |
803 | ||
804 | #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT) | |
805 | #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT) | |
806 | ||
807 | #define DMAE_CMD_C_DST_PCI 0 | |
808 | #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT) | |
809 | ||
810 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
811 | ||
812 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
813 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
814 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
815 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
816 | ||
817 | #define DMAE_CMD_PORT_0 0 | |
818 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
819 | ||
820 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
821 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
822 | ||
823 | #define DMAE_LEN32_MAX 0x400 | |
824 | ||
825 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); | |
826 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
827 | u32 len32); | |
828 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); | |
829 | ||
830 | ||
831 | /* MC hsi */ | |
832 | #define RX_COPY_THRESH 92 | |
833 | #define BCM_PAGE_SHIFT 12 | |
834 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
835 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
836 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) | |
837 | ||
838 | #define NUM_TX_RINGS 16 | |
839 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd)) | |
840 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) | |
841 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) | |
842 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
843 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
844 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ | |
845 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
846 | #define TX_BD(x) ((x) & MAX_TX_BD) | |
847 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
848 | ||
849 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | |
850 | #define NUM_RX_RINGS 8 | |
851 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) | |
852 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) | |
853 | #define RX_DESC_MASK (RX_DESC_CNT - 1) | |
854 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
855 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
856 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
857 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ | |
858 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) | |
859 | #define RX_BD(x) ((x) & MAX_RX_BD) | |
860 | ||
861 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * 2) | |
862 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) | |
863 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) | |
864 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) | |
865 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
866 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
867 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ | |
868 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
869 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) | |
870 | ||
871 | ||
872 | /* used on a CID received from the HW */ | |
873 | #define SW_CID(x) (le32_to_cpu(x) & \ | |
874 | (COMMON_RAMROD_ETH_RX_CQE_CID >> 1)) | |
875 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ | |
876 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
877 | ||
878 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ | |
879 | le32_to_cpu((bd)->addr_lo)) | |
880 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
881 | ||
882 | ||
883 | #define STROM_ASSERT_ARRAY_SIZE 50 | |
884 | ||
885 | ||
886 | ||
887 | /* must be used on a CID before placing it on a HW ring */ | |
888 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x) | |
889 | ||
890 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
891 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
892 | ||
893 | ||
894 | #define BNX2X_BTR 3 | |
895 | #define MAX_SPQ_PENDING 8 | |
896 | ||
897 | ||
898 | #define BNX2X_NUM_STATS 34 | |
899 | #define BNX2X_NUM_TESTS 1 | |
900 | ||
901 | ||
902 | #define DPM_TRIGER_TYPE 0x40 | |
903 | #define DOORBELL(bp, cid, val) \ | |
904 | do { \ | |
905 | writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \ | |
906 | DPM_TRIGER_TYPE); \ | |
907 | } while (0) | |
908 | ||
909 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, | |
910 | int wait) | |
911 | { | |
912 | u32 val; | |
913 | ||
914 | do { | |
915 | val = REG_RD(bp, reg); | |
916 | if (val == expected) | |
917 | break; | |
918 | ms -= wait; | |
919 | msleep(wait); | |
920 | ||
921 | } while (ms > 0); | |
922 | ||
923 | return val; | |
924 | } | |
925 | ||
926 | ||
927 | /* load/unload mode */ | |
928 | #define LOAD_NORMAL 0 | |
929 | #define LOAD_OPEN 1 | |
930 | #define LOAD_DIAG 2 | |
931 | #define UNLOAD_NORMAL 0 | |
932 | #define UNLOAD_CLOSE 1 | |
933 | ||
934 | /* DMAE command defines */ | |
935 | #define DMAE_CMD_SRC_PCI 0 | |
936 | #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC | |
937 | ||
938 | #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT) | |
939 | #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT) | |
940 | ||
941 | #define DMAE_CMD_C_DST_PCI 0 | |
942 | #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT) | |
943 | ||
944 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
945 | ||
946 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
947 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
948 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
949 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
950 | ||
951 | #define DMAE_CMD_PORT_0 0 | |
952 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
953 | ||
954 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
955 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
956 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
957 | ||
958 | #define DMAE_LEN32_RD_MAX 0x80 | |
959 | #define DMAE_LEN32_WR_MAX 0x400 | |
960 | ||
961 | #define DMAE_COMP_VAL 0xe0d0d0ae | |
962 | ||
963 | #define MAX_DMAE_C_PER_PORT 8 | |
964 | #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ | |
965 | BP_E1HVN(bp)) | |
966 | #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ | |
967 | E1HVN_MAX) | |
968 | ||
969 | ||
970 | /* PCIE link and speed */ | |
971 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
972 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
973 | #define PCICFG_LINK_SPEED 0xf0000 | |
974 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
975 | ||
976 | #define BMAC_CONTROL_RX_ENABLE 2 | |
977 | ||
978 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | |
979 | ||
980 | /* must be used on a CID before placing it on a HW ring */ | |
981 | ||
982 | #define BNX2X_RX_SUM_OK(cqe) \ | |
983 | (!(cqe->fast_path_cqe.status_flags & \ | |
984 | (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ | |
985 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) | |
986 | ||
987 | /* CMNG constants | |
988 | derived from lab experiments, and not from system spec calculations !!! */ | |
989 | #define DEF_MIN_RATE 100 | |
990 | /* resolution of the rate shaping timer - 100 usec */ | |
991 | #define RS_PERIODIC_TIMEOUT_USEC 100 | |
992 | /* resolution of fairness algorithm in usecs - | |
993 | coefficient for clauclating the actuall t fair */ | |
994 | #define T_FAIR_COEF 10000000 | |
995 | /* number of bytes in single QM arbitration cycle - | |
996 | coeffiecnt for calculating the fairness timer */ | |
997 | #define QM_ARB_BYTES 40000 | |
998 | #define FAIR_MEM 2 | |
999 | ||
1000 | ||
1001 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1002 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1003 | #define GPIO_2_FUNC (1L << 10) | |
1004 | #define GPIO_3_FUNC (1L << 11) | |
1005 | #define GPIO_4_FUNC (1L << 12) | |
1006 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1007 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1008 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1009 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1010 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1011 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1012 | ||
1013 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1014 | #define ATTENTION_ID 4 | |
1015 | ||
1016 | ||
1017 | /* stuff added to make the code fit 80Col */ | |
1018 | ||
1019 | #define BNX2X_PMF_LINK_ASSERT \ | |
1020 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
1021 | ||
1022 | #define BNX2X_MC_ASSERT_BITS \ | |
1023 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1024 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1025 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1026 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1027 | ||
1028 | #define BNX2X_MCP_ASSERT \ | |
1029 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1030 | ||
1031 | #define BNX2X_DOORQ_ASSERT \ | |
1032 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT | |
1033 | ||
1034 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) | |
1035 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1036 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1037 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1038 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1039 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1040 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1041 | ||
1042 | #define HW_INTERRUT_ASSERT_SET_0 \ | |
1043 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1044 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1045 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
1046 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) | |
1047 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ | |
1048 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ | |
1049 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1050 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
1051 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) | |
1052 | #define HW_INTERRUT_ASSERT_SET_1 \ | |
1053 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1054 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1055 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1056 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1057 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1058 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1059 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1060 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1061 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1062 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1063 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
1064 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ | |
1065 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ | |
1066 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ | |
1067 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ | |
1068 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ | |
1069 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ | |
1070 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ | |
1071 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
1072 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ | |
1073 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
1074 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) | |
1075 | #define HW_INTERRUT_ASSERT_SET_2 \ | |
1076 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
1077 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
1078 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
1079 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
1080 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
1081 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ | |
1082 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ | |
1083 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
1084 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
1085 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
1086 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ | |
1087 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
1088 | ||
1089 | ||
1090 | #define MULTI_FLAGS \ | |
1091 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ | |
1092 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ | |
1093 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ | |
1094 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ | |
1095 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE) | |
1096 | ||
1097 | #define MULTI_MASK 0x7f | |
1098 | ||
1099 | ||
1100 | #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES) | |
1101 | #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES) | |
1102 | #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES) | |
1103 | #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES) | |
1104 | ||
1105 | #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH | |
1106 | ||
1107 | #define BNX2X_SP_DSB_INDEX \ | |
1108 | (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]) | |
1109 | ||
1110 | ||
1111 | #define CAM_IS_INVALID(x) \ | |
1112 | (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) | |
1113 | ||
1114 | #define CAM_INVALIDATE(x) \ | |
1115 | (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) | |
1116 | ||
1117 | ||
1118 | /* Number of u32 elements in MC hash array */ | |
1119 | #define MC_HASH_SIZE 8 | |
1120 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
1121 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
1122 | ||
1123 | ||
1124 | #ifndef PXP2_REG_PXP2_INT_STS | |
1125 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
1126 | #endif | |
1127 | ||
1128 | /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */ | |
1129 | ||
1130 | #endif /* bnx2x.h */ |