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i2c-i801: Add Intel Patsburg device ID
[net-next-2.6.git] / drivers / i2c / busses / i2c-i801.c
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1/*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22/*
23 Supports the following Intel I/O Controller Hubs (ICH):
24
25 I/O Block I2C
26 region SMBus Block proc. block
27 Chip name PCI ID size PEC buffer call read
28 ----------------------------------------------------------------------
29 82801AA (ICH) 0x2413 16 no no no no
30 82801AB (ICH0) 0x2423 16 no no no no
31 82801BA (ICH2) 0x2443 16 no no no no
32 82801CA (ICH3) 0x2483 32 soft no no no
33 82801DB (ICH4) 0x24c3 32 hard yes no no
34 82801E (ICH5) 0x24d3 32 hard yes yes yes
35 6300ESB 0x25a4 32 hard yes yes yes
36 82801F (ICH6) 0x266a 32 hard yes yes yes
37 6310ESB/6320ESB 0x269b 32 hard yes yes yes
38 82801G (ICH7) 0x27da 32 hard yes yes yes
39 82801H (ICH8) 0x283e 32 hard yes yes yes
40 82801I (ICH9) 0x2930 32 hard yes yes yes
41 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
42 ICH10 0x3a30 32 hard yes yes yes
43 ICH10 0x3a60 32 hard yes yes yes
44 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
45 Cougar Point (PCH) 0x1c22 32 hard yes yes yes
46 Patsburg (PCH) 0x1d22 32 hard yes yes yes
47
48 Features supported by this driver:
49 Software PEC no
50 Hardware PEC yes
51 Block buffer yes
52 Block process call transaction no
53 I2C block read transaction yes (doesn't use the block buffer)
54
55 See the file Documentation/i2c/busses/i2c-i801 for details.
56*/
57
58/* Note: we assume there can only be one I801, with one SMBus interface */
59
60#include <linux/module.h>
61#include <linux/pci.h>
62#include <linux/kernel.h>
63#include <linux/stddef.h>
64#include <linux/delay.h>
65#include <linux/ioport.h>
66#include <linux/init.h>
67#include <linux/i2c.h>
68#include <linux/acpi.h>
69#include <linux/io.h>
70#include <linux/dmi.h>
71
72/* I801 SMBus address offsets */
73#define SMBHSTSTS (0 + i801_smba)
74#define SMBHSTCNT (2 + i801_smba)
75#define SMBHSTCMD (3 + i801_smba)
76#define SMBHSTADD (4 + i801_smba)
77#define SMBHSTDAT0 (5 + i801_smba)
78#define SMBHSTDAT1 (6 + i801_smba)
79#define SMBBLKDAT (7 + i801_smba)
80#define SMBPEC (8 + i801_smba) /* ICH3 and later */
81#define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
82#define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
83
84/* PCI Address Constants */
85#define SMBBAR 4
86#define SMBHSTCFG 0x040
87
88/* Host configuration bits for SMBHSTCFG */
89#define SMBHSTCFG_HST_EN 1
90#define SMBHSTCFG_SMB_SMI_EN 2
91#define SMBHSTCFG_I2C_EN 4
92
93/* Auxillary control register bits, ICH4+ only */
94#define SMBAUXCTL_CRC 1
95#define SMBAUXCTL_E32B 2
96
97/* kill bit for SMBHSTCNT */
98#define SMBHSTCNT_KILL 2
99
100/* Other settings */
101#define MAX_TIMEOUT 100
102#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
103
104/* I801 command constants */
105#define I801_QUICK 0x00
106#define I801_BYTE 0x04
107#define I801_BYTE_DATA 0x08
108#define I801_WORD_DATA 0x0C
109#define I801_PROC_CALL 0x10 /* unimplemented */
110#define I801_BLOCK_DATA 0x14
111#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
112#define I801_BLOCK_LAST 0x34
113#define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
114#define I801_START 0x40
115#define I801_PEC_EN 0x80 /* ICH3 and later */
116
117/* I801 Hosts Status register bits */
118#define SMBHSTSTS_BYTE_DONE 0x80
119#define SMBHSTSTS_INUSE_STS 0x40
120#define SMBHSTSTS_SMBALERT_STS 0x20
121#define SMBHSTSTS_FAILED 0x10
122#define SMBHSTSTS_BUS_ERR 0x08
123#define SMBHSTSTS_DEV_ERR 0x04
124#define SMBHSTSTS_INTR 0x02
125#define SMBHSTSTS_HOST_BUSY 0x01
126
127#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
128 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
129 SMBHSTSTS_INTR)
130
131static unsigned long i801_smba;
132static unsigned char i801_original_hstcfg;
133static struct pci_driver i801_driver;
134static struct pci_dev *I801_dev;
135
136#define FEATURE_SMBUS_PEC (1 << 0)
137#define FEATURE_BLOCK_BUFFER (1 << 1)
138#define FEATURE_BLOCK_PROC (1 << 2)
139#define FEATURE_I2C_BLOCK_READ (1 << 3)
140static unsigned int i801_features;
141
142static const char *i801_feature_names[] = {
143 "SMBus PEC",
144 "Block buffer",
145 "Block process call",
146 "I2C block read",
147};
148
149static unsigned int disable_features;
150module_param(disable_features, uint, S_IRUGO | S_IWUSR);
151MODULE_PARM_DESC(disable_features, "Disable selected driver features");
152
153/* Make sure the SMBus host is ready to start transmitting.
154 Return 0 if it is, -EBUSY if it is not. */
155static int i801_check_pre(void)
156{
157 int status;
158
159 status = inb_p(SMBHSTSTS);
160 if (status & SMBHSTSTS_HOST_BUSY) {
161 dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n");
162 return -EBUSY;
163 }
164
165 status &= STATUS_FLAGS;
166 if (status) {
167 dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n",
168 status);
169 outb_p(status, SMBHSTSTS);
170 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
171 if (status) {
172 dev_err(&I801_dev->dev,
173 "Failed clearing status flags (%02x)\n",
174 status);
175 return -EBUSY;
176 }
177 }
178
179 return 0;
180}
181
182/* Convert the status register to an error code, and clear it. */
183static int i801_check_post(int status, int timeout)
184{
185 int result = 0;
186
187 /* If the SMBus is still busy, we give up */
188 if (timeout) {
189 dev_err(&I801_dev->dev, "Transaction timeout\n");
190 /* try to stop the current command */
191 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
192 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
193 msleep(1);
194 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
195
196 /* Check if it worked */
197 status = inb_p(SMBHSTSTS);
198 if ((status & SMBHSTSTS_HOST_BUSY) ||
199 !(status & SMBHSTSTS_FAILED))
200 dev_err(&I801_dev->dev,
201 "Failed terminating the transaction\n");
202 outb_p(STATUS_FLAGS, SMBHSTSTS);
203 return -ETIMEDOUT;
204 }
205
206 if (status & SMBHSTSTS_FAILED) {
207 result = -EIO;
208 dev_err(&I801_dev->dev, "Transaction failed\n");
209 }
210 if (status & SMBHSTSTS_DEV_ERR) {
211 result = -ENXIO;
212 dev_dbg(&I801_dev->dev, "No response\n");
213 }
214 if (status & SMBHSTSTS_BUS_ERR) {
215 result = -EAGAIN;
216 dev_dbg(&I801_dev->dev, "Lost arbitration\n");
217 }
218
219 if (result) {
220 /* Clear error flags */
221 outb_p(status & STATUS_FLAGS, SMBHSTSTS);
222 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
223 if (status) {
224 dev_warn(&I801_dev->dev, "Failed clearing status "
225 "flags at end of transaction (%02x)\n",
226 status);
227 }
228 }
229
230 return result;
231}
232
233static int i801_transaction(int xact)
234{
235 int status;
236 int result;
237 int timeout = 0;
238
239 result = i801_check_pre();
240 if (result < 0)
241 return result;
242
243 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
244 * INTREN, SMBSCMD are passed in xact */
245 outb_p(xact | I801_START, SMBHSTCNT);
246
247 /* We will always wait for a fraction of a second! */
248 do {
249 msleep(1);
250 status = inb_p(SMBHSTSTS);
251 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
252
253 result = i801_check_post(status, timeout > MAX_TIMEOUT);
254 if (result < 0)
255 return result;
256
257 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
258 return 0;
259}
260
261/* wait for INTR bit as advised by Intel */
262static void i801_wait_hwpec(void)
263{
264 int timeout = 0;
265 int status;
266
267 do {
268 msleep(1);
269 status = inb_p(SMBHSTSTS);
270 } while ((!(status & SMBHSTSTS_INTR))
271 && (timeout++ < MAX_TIMEOUT));
272
273 if (timeout > MAX_TIMEOUT)
274 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
275
276 outb_p(status, SMBHSTSTS);
277}
278
279static int i801_block_transaction_by_block(union i2c_smbus_data *data,
280 char read_write, int hwpec)
281{
282 int i, len;
283 int status;
284
285 inb_p(SMBHSTCNT); /* reset the data buffer index */
286
287 /* Use 32-byte buffer to process this transaction */
288 if (read_write == I2C_SMBUS_WRITE) {
289 len = data->block[0];
290 outb_p(len, SMBHSTDAT0);
291 for (i = 0; i < len; i++)
292 outb_p(data->block[i+1], SMBBLKDAT);
293 }
294
295 status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
296 I801_PEC_EN * hwpec);
297 if (status)
298 return status;
299
300 if (read_write == I2C_SMBUS_READ) {
301 len = inb_p(SMBHSTDAT0);
302 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
303 return -EPROTO;
304
305 data->block[0] = len;
306 for (i = 0; i < len; i++)
307 data->block[i + 1] = inb_p(SMBBLKDAT);
308 }
309 return 0;
310}
311
312static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
313 char read_write, int command,
314 int hwpec)
315{
316 int i, len;
317 int smbcmd;
318 int status;
319 int result;
320 int timeout;
321
322 result = i801_check_pre();
323 if (result < 0)
324 return result;
325
326 len = data->block[0];
327
328 if (read_write == I2C_SMBUS_WRITE) {
329 outb_p(len, SMBHSTDAT0);
330 outb_p(data->block[1], SMBBLKDAT);
331 }
332
333 for (i = 1; i <= len; i++) {
334 if (i == len && read_write == I2C_SMBUS_READ) {
335 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
336 smbcmd = I801_I2C_BLOCK_LAST;
337 else
338 smbcmd = I801_BLOCK_LAST;
339 } else {
340 if (command == I2C_SMBUS_I2C_BLOCK_DATA
341 && read_write == I2C_SMBUS_READ)
342 smbcmd = I801_I2C_BLOCK_DATA;
343 else
344 smbcmd = I801_BLOCK_DATA;
345 }
346 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
347
348 if (i == 1)
349 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
350
351 /* We will always wait for a fraction of a second! */
352 timeout = 0;
353 do {
354 msleep(1);
355 status = inb_p(SMBHSTSTS);
356 } while ((!(status & SMBHSTSTS_BYTE_DONE))
357 && (timeout++ < MAX_TIMEOUT));
358
359 result = i801_check_post(status, timeout > MAX_TIMEOUT);
360 if (result < 0)
361 return result;
362
363 if (i == 1 && read_write == I2C_SMBUS_READ
364 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
365 len = inb_p(SMBHSTDAT0);
366 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
367 dev_err(&I801_dev->dev,
368 "Illegal SMBus block read size %d\n",
369 len);
370 /* Recover */
371 while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
372 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS);
373 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
374 return -EPROTO;
375 }
376 data->block[0] = len;
377 }
378
379 /* Retrieve/store value in SMBBLKDAT */
380 if (read_write == I2C_SMBUS_READ)
381 data->block[i] = inb_p(SMBBLKDAT);
382 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
383 outb_p(data->block[i+1], SMBBLKDAT);
384
385 /* signals SMBBLKDAT ready */
386 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS);
387 }
388
389 return 0;
390}
391
392static int i801_set_block_buffer_mode(void)
393{
394 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
395 if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
396 return -EIO;
397 return 0;
398}
399
400/* Block transaction function */
401static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
402 int command, int hwpec)
403{
404 int result = 0;
405 unsigned char hostc;
406
407 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
408 if (read_write == I2C_SMBUS_WRITE) {
409 /* set I2C_EN bit in configuration register */
410 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
411 pci_write_config_byte(I801_dev, SMBHSTCFG,
412 hostc | SMBHSTCFG_I2C_EN);
413 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
414 dev_err(&I801_dev->dev,
415 "I2C block read is unsupported!\n");
416 return -EOPNOTSUPP;
417 }
418 }
419
420 if (read_write == I2C_SMBUS_WRITE
421 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
422 if (data->block[0] < 1)
423 data->block[0] = 1;
424 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
425 data->block[0] = I2C_SMBUS_BLOCK_MAX;
426 } else {
427 data->block[0] = 32; /* max for SMBus block reads */
428 }
429
430 /* Experience has shown that the block buffer can only be used for
431 SMBus (not I2C) block transactions, even though the datasheet
432 doesn't mention this limitation. */
433 if ((i801_features & FEATURE_BLOCK_BUFFER)
434 && command != I2C_SMBUS_I2C_BLOCK_DATA
435 && i801_set_block_buffer_mode() == 0)
436 result = i801_block_transaction_by_block(data, read_write,
437 hwpec);
438 else
439 result = i801_block_transaction_byte_by_byte(data, read_write,
440 command, hwpec);
441
442 if (result == 0 && hwpec)
443 i801_wait_hwpec();
444
445 if (command == I2C_SMBUS_I2C_BLOCK_DATA
446 && read_write == I2C_SMBUS_WRITE) {
447 /* restore saved configuration register value */
448 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
449 }
450 return result;
451}
452
453/* Return negative errno on error. */
454static s32 i801_access(struct i2c_adapter *adap, u16 addr,
455 unsigned short flags, char read_write, u8 command,
456 int size, union i2c_smbus_data *data)
457{
458 int hwpec;
459 int block = 0;
460 int ret, xact = 0;
461
462 hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
463 && size != I2C_SMBUS_QUICK
464 && size != I2C_SMBUS_I2C_BLOCK_DATA;
465
466 switch (size) {
467 case I2C_SMBUS_QUICK:
468 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
469 SMBHSTADD);
470 xact = I801_QUICK;
471 break;
472 case I2C_SMBUS_BYTE:
473 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
474 SMBHSTADD);
475 if (read_write == I2C_SMBUS_WRITE)
476 outb_p(command, SMBHSTCMD);
477 xact = I801_BYTE;
478 break;
479 case I2C_SMBUS_BYTE_DATA:
480 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
481 SMBHSTADD);
482 outb_p(command, SMBHSTCMD);
483 if (read_write == I2C_SMBUS_WRITE)
484 outb_p(data->byte, SMBHSTDAT0);
485 xact = I801_BYTE_DATA;
486 break;
487 case I2C_SMBUS_WORD_DATA:
488 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
489 SMBHSTADD);
490 outb_p(command, SMBHSTCMD);
491 if (read_write == I2C_SMBUS_WRITE) {
492 outb_p(data->word & 0xff, SMBHSTDAT0);
493 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
494 }
495 xact = I801_WORD_DATA;
496 break;
497 case I2C_SMBUS_BLOCK_DATA:
498 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
499 SMBHSTADD);
500 outb_p(command, SMBHSTCMD);
501 block = 1;
502 break;
503 case I2C_SMBUS_I2C_BLOCK_DATA:
504 /* NB: page 240 of ICH5 datasheet shows that the R/#W
505 * bit should be cleared here, even when reading */
506 outb_p((addr & 0x7f) << 1, SMBHSTADD);
507 if (read_write == I2C_SMBUS_READ) {
508 /* NB: page 240 of ICH5 datasheet also shows
509 * that DATA1 is the cmd field when reading */
510 outb_p(command, SMBHSTDAT1);
511 } else
512 outb_p(command, SMBHSTCMD);
513 block = 1;
514 break;
515 default:
516 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
517 return -EOPNOTSUPP;
518 }
519
520 if (hwpec) /* enable/disable hardware PEC */
521 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
522 else
523 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
524
525 if (block)
526 ret = i801_block_transaction(data, read_write, size, hwpec);
527 else
528 ret = i801_transaction(xact | ENABLE_INT9);
529
530 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
531 time, so we forcibly disable it after every transaction. Turn off
532 E32B for the same reason. */
533 if (hwpec || block)
534 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
535 SMBAUXCTL);
536
537 if (block)
538 return ret;
539 if (ret)
540 return ret;
541 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
542 return 0;
543
544 switch (xact & 0x7f) {
545 case I801_BYTE: /* Result put in SMBHSTDAT0 */
546 case I801_BYTE_DATA:
547 data->byte = inb_p(SMBHSTDAT0);
548 break;
549 case I801_WORD_DATA:
550 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
551 break;
552 }
553 return 0;
554}
555
556
557static u32 i801_func(struct i2c_adapter *adapter)
558{
559 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
560 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
561 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
562 ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
563 ((i801_features & FEATURE_I2C_BLOCK_READ) ?
564 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
565}
566
567static const struct i2c_algorithm smbus_algorithm = {
568 .smbus_xfer = i801_access,
569 .functionality = i801_func,
570};
571
572static struct i2c_adapter i801_adapter = {
573 .owner = THIS_MODULE,
574 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
575 .algo = &smbus_algorithm,
576};
577
578static const struct pci_device_id i801_ids[] = {
579 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
580 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
581 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
582 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
583 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
584 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
585 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
586 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
587 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
588 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
589 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
590 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
591 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
592 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
593 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
594 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
595 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
596 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
597 { 0, }
598};
599
600MODULE_DEVICE_TABLE(pci, i801_ids);
601
602#if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
603static unsigned char apanel_addr;
604
605/* Scan the system ROM for the signature "FJKEYINF" */
606static __init const void __iomem *bios_signature(const void __iomem *bios)
607{
608 ssize_t offset;
609 const unsigned char signature[] = "FJKEYINF";
610
611 for (offset = 0; offset < 0x10000; offset += 0x10) {
612 if (check_signature(bios + offset, signature,
613 sizeof(signature)-1))
614 return bios + offset;
615 }
616 return NULL;
617}
618
619static void __init input_apanel_init(void)
620{
621 void __iomem *bios;
622 const void __iomem *p;
623
624 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
625 p = bios_signature(bios);
626 if (p) {
627 /* just use the first address */
628 apanel_addr = readb(p + 8 + 3) >> 1;
629 }
630 iounmap(bios);
631}
632#else
633static void __init input_apanel_init(void) {}
634#endif
635
636#if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
637struct dmi_onboard_device_info {
638 const char *name;
639 u8 type;
640 unsigned short i2c_addr;
641 const char *i2c_type;
642};
643
644static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
645 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
646 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
647 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
648};
649
650static void __devinit dmi_check_onboard_device(u8 type, const char *name,
651 struct i2c_adapter *adap)
652{
653 int i;
654 struct i2c_board_info info;
655
656 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
657 /* & ~0x80, ignore enabled/disabled bit */
658 if ((type & ~0x80) != dmi_devices[i].type)
659 continue;
660 if (strcasecmp(name, dmi_devices[i].name))
661 continue;
662
663 memset(&info, 0, sizeof(struct i2c_board_info));
664 info.addr = dmi_devices[i].i2c_addr;
665 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
666 i2c_new_device(adap, &info);
667 break;
668 }
669}
670
671/* We use our own function to check for onboard devices instead of
672 dmi_find_device() as some buggy BIOS's have the devices we are interested
673 in marked as disabled */
674static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
675 void *adap)
676{
677 int i, count;
678
679 if (dm->type != 10)
680 return;
681
682 count = (dm->length - sizeof(struct dmi_header)) / 2;
683 for (i = 0; i < count; i++) {
684 const u8 *d = (char *)(dm + 1) + (i * 2);
685 const char *name = ((char *) dm) + dm->length;
686 u8 type = d[0];
687 u8 s = d[1];
688
689 if (!s)
690 continue;
691 s--;
692 while (s > 0 && name[0]) {
693 name += strlen(name) + 1;
694 s--;
695 }
696 if (name[0] == 0) /* Bogus string reference */
697 continue;
698
699 dmi_check_onboard_device(type, name, adap);
700 }
701}
702#endif
703
704static int __devinit i801_probe(struct pci_dev *dev,
705 const struct pci_device_id *id)
706{
707 unsigned char temp;
708 int err, i;
709
710 I801_dev = dev;
711 i801_features = 0;
712 switch (dev->device) {
713 default:
714 i801_features |= FEATURE_I2C_BLOCK_READ;
715 /* fall through */
716 case PCI_DEVICE_ID_INTEL_82801DB_3:
717 i801_features |= FEATURE_SMBUS_PEC;
718 i801_features |= FEATURE_BLOCK_BUFFER;
719 /* fall through */
720 case PCI_DEVICE_ID_INTEL_82801CA_3:
721 case PCI_DEVICE_ID_INTEL_82801BA_2:
722 case PCI_DEVICE_ID_INTEL_82801AB_3:
723 case PCI_DEVICE_ID_INTEL_82801AA_3:
724 break;
725 }
726
727 /* Disable features on user request */
728 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
729 if (i801_features & disable_features & (1 << i))
730 dev_notice(&dev->dev, "%s disabled by user\n",
731 i801_feature_names[i]);
732 }
733 i801_features &= ~disable_features;
734
735 err = pci_enable_device(dev);
736 if (err) {
737 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
738 err);
739 goto exit;
740 }
741
742 /* Determine the address of the SMBus area */
743 i801_smba = pci_resource_start(dev, SMBBAR);
744 if (!i801_smba) {
745 dev_err(&dev->dev, "SMBus base address uninitialized, "
746 "upgrade BIOS\n");
747 err = -ENODEV;
748 goto exit;
749 }
750
751 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
752 if (err) {
753 err = -ENODEV;
754 goto exit;
755 }
756
757 err = pci_request_region(dev, SMBBAR, i801_driver.name);
758 if (err) {
759 dev_err(&dev->dev, "Failed to request SMBus region "
760 "0x%lx-0x%Lx\n", i801_smba,
761 (unsigned long long)pci_resource_end(dev, SMBBAR));
762 goto exit;
763 }
764
765 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
766 i801_original_hstcfg = temp;
767 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
768 if (!(temp & SMBHSTCFG_HST_EN)) {
769 dev_info(&dev->dev, "Enabling SMBus device\n");
770 temp |= SMBHSTCFG_HST_EN;
771 }
772 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
773
774 if (temp & SMBHSTCFG_SMB_SMI_EN)
775 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
776 else
777 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
778
779 /* Clear special mode bits */
780 if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
781 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
782 SMBAUXCTL);
783
784 /* set up the sysfs linkage to our parent device */
785 i801_adapter.dev.parent = &dev->dev;
786
787 /* Retry up to 3 times on lost arbitration */
788 i801_adapter.retries = 3;
789
790 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
791 "SMBus I801 adapter at %04lx", i801_smba);
792 err = i2c_add_adapter(&i801_adapter);
793 if (err) {
794 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
795 goto exit_release;
796 }
797
798 /* Register optional slaves */
799#if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
800 if (apanel_addr) {
801 struct i2c_board_info info;
802
803 memset(&info, 0, sizeof(struct i2c_board_info));
804 info.addr = apanel_addr;
805 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
806 i2c_new_device(&i801_adapter, &info);
807 }
808#endif
809#if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
810 if (dmi_name_in_vendors("FUJITSU"))
811 dmi_walk(dmi_check_onboard_devices, &i801_adapter);
812#endif
813
814 return 0;
815
816exit_release:
817 pci_release_region(dev, SMBBAR);
818exit:
819 return err;
820}
821
822static void __devexit i801_remove(struct pci_dev *dev)
823{
824 i2c_del_adapter(&i801_adapter);
825 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
826 pci_release_region(dev, SMBBAR);
827 /*
828 * do not call pci_disable_device(dev) since it can cause hard hangs on
829 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
830 */
831}
832
833#ifdef CONFIG_PM
834static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
835{
836 pci_save_state(dev);
837 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
838 pci_set_power_state(dev, pci_choose_state(dev, mesg));
839 return 0;
840}
841
842static int i801_resume(struct pci_dev *dev)
843{
844 pci_set_power_state(dev, PCI_D0);
845 pci_restore_state(dev);
846 return pci_enable_device(dev);
847}
848#else
849#define i801_suspend NULL
850#define i801_resume NULL
851#endif
852
853static struct pci_driver i801_driver = {
854 .name = "i801_smbus",
855 .id_table = i801_ids,
856 .probe = i801_probe,
857 .remove = __devexit_p(i801_remove),
858 .suspend = i801_suspend,
859 .resume = i801_resume,
860};
861
862static int __init i2c_i801_init(void)
863{
864 input_apanel_init();
865 return pci_register_driver(&i801_driver);
866}
867
868static void __exit i2c_i801_exit(void)
869{
870 pci_unregister_driver(&i801_driver);
871}
872
873MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
874 "Jean Delvare <khali@linux-fr.org>");
875MODULE_DESCRIPTION("I801 SMBus driver");
876MODULE_LICENSE("GPL");
877
878module_init(i2c_i801_init);
879module_exit(i2c_i801_exit);
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